Computers and Electrical Engineering 49 (2016) 39–49

Contents lists available at ScienceDirect

Computers and Electrical Engineering

journal homepage: [Link]/locate/compeleceng

A novel high-speed approach for 16 × 16 Vedic multiplication

with compressor adders R
Yogita Bansal∗, Charu Madhu
Department of Electronics and Communication, University Institute of Engineering and Technology, Panjab University, Chandigarh, India

a r t i c l e i n f o a b s t r a c t

Article history: In this paper, a novel architecture of Vedic multiplier with ‘Urdhava-tiryakbhyam’ method-
Received 26 May 2014 ology for 16 bit multiplier and multiplicand is proposed with the use of compressor adders.
Revised 10 October 2015
Equations for each bit of 32 bit resultant are calculated distinctly and compressor adders are
Accepted 6 November 2015
used to implement these equations. They are chosen as they decrease vertical critical delay in
comparison to the conventional architectures of compressors implemented using half and full
Keywords: adders only and so make the multiplier fast. The designs are coded in VHDL (Very High-speed
Vedic mathematics Integrated Circuits Hardware Description Language) and synthesized with Xilinx ISE 13.1 using
Vedic multiplier Spartan 3e series of FPGA (Field Programmable Gate Array). The combinational delay calcu-
‘Urdhava-tiryakbhyam’ sutra lated for proposed 16 × 16 bit multiplier is 32 ns. Further speed comparisons of compressor
5-3 compressor adders with traditional ones and proposed multiplier with popular methods for multiplica-
10-4 compressor
tion are shown. Results clearly indicate the better speed performance of our proposed Vedic
15-4 compressor
multiplier.
20-5 compressor
© 2015 Elsevier Ltd. All rights reserved.

1. Introduction

Vedic multiplier is built on Vedic mathematics which further is extracted from the ancient Vedas by the Sri Bharati Krishna
Tirthaji in between 1911 and 1918 [1]. The specialty of Vedic mathematics is that it gives simple way to solve the calculations
which can be easily understood by human minds. This Vedic mathematics is divided into 16 sutras which give different rules
for the simplification of the problems related to trigonometry, algebra, geometry etc. Designs based on Vedic mathematics have
been used in many applications like ALU, MAC etc. and have shown better results in terms of delay, area [2–6]. Among the 16
sutras, ‘Urdhava-tiryakbhyam’ is picked as this sutra is a universal method for multiplication and thus always remained favorite
method of implementers. Previously this method was used only for multiplication of decimal numbers but from some time it
has been used and proved to be better for binary number multiplication. Also the increase in delay and area with the increase in
number of input bits is at a slow rate with respect to other sutras [1]. With the selection of ‘Urdhava-tiryakbhyam’ sutra, further
selection comes with adders to add the partial products generated for the resultant bits (s0 –s31 ). These adders decide the speed
of the multiplier and thus requirement of high-speed adder becomes the need for concern. In this paper, we have given a novel
architecture for the separate calculation of product bits of the multiplication of multiplier and multiplicand. For this method,
compressor adders [7] have been used over conventional architectures of half-adders and full adders because of their higher
speed performance. These compressors actually act as counters and count the number of 1s in the given bits and thus behave
as adders. They make use of multiplexer in addition with half-adders and full adders which allow the use of lesser XOR gates

R
“Reviews processed and approved for publication by the Editor-in-Chief”.
∗
Corresponding author. Tel.: +91 9465481844 (mobile).
E-mail address: [Link].21@[Link] (Y. Bansal).

[Link]
0045-7906/© 2015 Elsevier Ltd. All rights reserved.
40 Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49

Fig. 1. Three digit multiplication with ‘Vertically and crosswise’ technique [9]

and thus high speed. With each resultant bit some carries are also generated which goes further for the calculation of next final
product bits.
The paper is divided into 4 sections. Section 2 describes the ‘Vertically and crosswise’ technique for multiplication of the
binary as well as decimal numbers. Section 3 describes the concept and full architectures of the 5, 10, 15 compressor adders
which are used in the implementation of proposed architecture. Section 4 depicts the full details of proposed architecture by
conjoining the architectures of Vedic multiplier and compressor adders. Section 5 illustrates simulation results for the multiplier
and Section 6 describes its conclusion and future scope.

2. ‘Vertically and crosswise’ technique

The Sanskrit name for this rule is ‘Urdhava-tiryakbhyam’ which is a universal formula for the multiplication. This method
multiplies the digits vertically and crosswise and finally adds them with the help of the appropriate adder. This rule is applicable
to both integers and binary numbers. The best feature of this method is that the partial products needed for the multiplication
are already generated in advance and this leads to decrease in delay and thus saves the time. The increase in number of bits
however brings little increase in area and critical delay [3].The method is explained for multiplication of decimal numbers and
binary numbers differently.

2.1. For decimal number

For N digit number there will be 2N − 1 steps. The digits on the ends of the line are multiplied and result is stored. Then the
previous carry is added to it. The least significant digit of resultant coming from addition is kept as answer bit of the multipli-
cation and all other digits are considered as previous carries for the next step. When the number of lines becomes more than
one in the same step, then all the outcomes are accumulated with the previous carries. Following same steps, final output of
multiplication comes. Initial carry in this case is taken as zero [8]. Fig. 1 shows the multiplication of two 3 digit decimal numbers,
325 and 738 in five steps.

2.2. For binary numbers

The same way is extended to the binary digit multiplication. One bit multiplication is simple AND gate operation of the
operands. For the higher bit product, the following method is used for the evaluation of the equations for the resultant bits of
multiplication. This method is known as square table method. In this technique firstly each small square block inside the table is
partitioned into two identical parts. Then multiplier and multiplicand are written on the successive sides of the table.
After that each bit of them is multiplied separately and result is stored in the lower part of small square block. Then starting
from least significant bit of multiplier, all the bits coming in lower part of small square blocks are added and sum bit of the their
resultant is considered as the resultant bit of the multiplication. Carry bits of the addition are further sent to succeeding blocks
 Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49 41

Fig. 2. 4 × 4 binary Vedic multiplication [9].

and also added to the results coming in their way [9]. Fig. 2 shows the multiplication of the two binary numbers a = a3 a2 a1 a0 (4
bits) and b = b3 b2 b1 b0 (4 bits) and final product is r7 r6 r5 r4 r3 r2 r1 r0 (8 bit). Because partial products are generated in parallel, so
the critical delay will be only the time taken by the signal to pass through the logical gates [9].

3. Compressor adder’s architectures used

Compressor adders are basic circuits which add bits more than four at a time to give better delay results over the combina-
tional circuits of half and full adders. The symbolic representation of compressor architecture is N − r where ‘N’ represents the
number of the bits that are fed and ‘r’ represents the total count of the 1s present in N bits. It actually reduces the gate counts and
delay in comparison to adder circuits and that is why named as compressor. A large part of research has been done in improv-
ing the circuits of lower compressors [10-12]. Along with this, higher compressors are also implemented to add higher number
of bits. In this paper, the main compressor architectures which are used are 5-3, 10-4, 15-4 and 20-5. They are defined below
separately.

3.1. 5-3 compressor

A 5-3 compressor adder is a logical circuit in which maximum five bits can be added at the same time and three bit resultant
of maximum value 101 is obtained. The circuit uses three 4:1 multiplexers. This multiplexer allows only one output to be high at
a time and this property makes the multiplier fast and low power consuming circuit [13–15]. The circuit is reorganized in such
a way that only 3 XOR operations are used instead of 5 XOR operations (in case of conventional 5-3 compressor) and other two
inputs (X3 and X4) acts as a control signals. The conventional and the modified 5-3 compressor adder circuit are shown in Fig. 3a
and b.

3.2. 10-4 compressor

Its circuitry takes ten inputs, adds them and gives four bit output. The maximum resultant can be 1010. It makes use of two 5-
3 compressors, two full adders and a half adder at the required position. Because of the use of modified 5-3 compressor circuitry,
this compressor shows lesser delay and gate counts making the multiplier fast and ultimately the processer. Fig. 4 given below
represents the modified circuitry of the 10-4 compressor.

3.3. 15-4 compressor

1. Similar to the 5-3, 10-4 compressor adders, 15-4 compressors feed 15 bits at a time and give four bit resultant which can
go to extreme value of 1111. Its circuitry contains two 5-3 compressors, five full adders and one 4 bit parallel adder. The
inputs are given in a group of three to the five full adders. Then the sum bits of all five full adder are added using one 5-3
42 Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49

Fig. 3. (a) Modified design for 5-3 compressor [13], (b) 5-3 compressors with full adders and half-adders [13].

compressor and the carry bits of the full adders are fed to another 5-3 compressor. Further a 4 bit parallel adder is used to
add the outputs of these two 5-3 compressor and gives the final result. Fig. 5 given below represents the modified circuitry of
the 15-4 compressor.

3.4. 20-5 compressor

In the proposed design we need to add 19 bits at the same time and so need to use a higher compressor adder circuit. In 20-5
compressor circuit, it converts 20 partial products into five output bits having maximum value of 10010. This makes use of one
15-4 compressor, one 5-3 compressor, two half-adders and two full adders. The improved architectures of lower compressors
15-4 and 5-3 bring speed improvement in its circuit in comparison with conventional architectures containing only full and
half-adders. The 20-5 compressor adder circuit is shown in Fig. 6.

4. Proposed architecture

In conventional designs of the Vedic multiplier, half-adders and full adders are used for the accumulation of the partial
products which are generated during the process. They lead to increase in propagation delay of the circuit and thus cause large
processing time. In our novel approach, we propose a 16 × 16 bit Vedic multiplier with the use of compressor adders which
calculate the resultant bits (32 in this case) individually. Equations are calculated by using ‘Vertically and crosswise’ technique of
Vedic mathematics.

4.1. Equations for the 32 bit resultant product

Both ‘a’ and ‘b’ are 16 bit inputs a = a1 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49 43

Fig. 4. 10-4 compressor with 5-3 compressor.

Fig. 5. 15-4 compressor with 5-3 compressors [13].

Fig. 6. 20-5 compressor with 15-4 and 5-3 compressor.

44 Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49

And
b = b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
And their product ‘r’ is 32 bit (r31−0 ).
The carry signals c1 − c89 , generated during the implementation, have partial results and are added to the next sum bits.
The equations that are required to be implemented are given below.
s0 = a0 b0 (1)

c1 s1 = a0 b1 + a1 b0 (2)

c3 c2 s2 = c1 + a0 b2 + a1 b1 + a2 b0 (3)

c5 c4 s3 = c2 + a0 b3 + a1 b2 + a2 b1 + a3 b0 (4)

c7 c6 s4 = c4 + c3 + a0 b4 + a1 b3 + a2 b2 + a3 b1 + a4 b0 (5)

c10 c9 c8 s5 = c6 + c5 + a0 b5 + a1 b4 + a2 b3 + a3 b2 + a4 b1 + a5 b0 (6)

c13 c12 c11 s6 = c8 + c7 + a0 b6 + a1 b5 + a2 b4 + a3 b3 + a4 b2 + a5 b1 + a6 b0 (7)

c16 c15 c14 s7 = c11 + c9 + a0 b7 + a1 b6 + a2 b5 + a3 b4 + a4 b3 + a5 b2 + a6 b1 + a7 b0 (8)

c19 c18 c17 s8 = c10 + c12 + c14 + a0 b8 + a1 b7 + a2 b6 + a3 b5 + a4 b4 + a5 b3 + a6 b2 + a7 b1 + a8 b0 (9)

c22 c21 c20 s9 = c17 + c15 + c13 + a0 b9 + a1 b8 + a2 b7 + a3 b6 + a4 b5 + a5 b4 + a6 b3 + a7 b2 + a8 b1 + a9 b0 (10)

c25 c24 c23 s10 = c20 + c18 + c16 + a0 b10 + a1 b9 + a2 b8 + a3 b7 + a4 b6 + a5 b5 + a6 b4 + a7 b3 + a8 b2 + a9 b1 + a10 b0 (11)

c28 c27 c26 s11 = c23 + c21 + c19 + a0 b11 + a1 b10 + a2 b9 + a3 b8 + a4 b7 + a5 b6 + a6 b5 + a7 b4 + a8 b3

+ a9 b2 + a10 b1 + a11 b0 (12)

c32 c31 c30 c29 s12 = c26 + c24 + c22 + a0 b12 + a1 b11 + a2 b10 + a3 b9 + a4 b8 + a5 b7 + a6 b6 + a7 b5 + a8 b4
+ a9 b3 + a10 b2 + a11 b1 + a12 b0 (13)

c36 c35 c34 c33 s13 = c29 + c27 + c25 + a0 b13 + a1 b12 + a2 b11 + a3 b10 + a4 b9 + a5 b8 + a6 b7
+ a7 b6 + a8 b5 + a9 b4 + a10 b3 + a11 b2 + a12 b1 + a13 b0 (14)

c40 c39 c38 c37 s14 = c33 + c30 + c28 + a0 b14 + a1 b13 + a2 b12 + a3 b11 + a4 b10 + a5 b9 + a6 b8 + a7 b7 + a8 b6 + a9 b5
+ a10 b4 + a11 b3 + a12 b2 + a13 b1 + a14 b0 (15)

c44 c43 c3842 c41 s15 = c37 + c34 + c31 + a0 b15 + a1 b14 + a2 b13 + a3 b12 + a4 b11 + a5 b10 + a6 b9 + a7 b8 + a8 b7 + a9 b6
+ a10808 b5 + a11 b4 + a12 b3 + a13 b2 + a14 b1 + a1545 b0 (16)

c48 c47 c3846 c45 s16 = c32 + c35 + c33 + c41 + a1 b15 + a2 b14 + a3 b13 + a4 b12 + a5 b11 + a6 b10 + a7 b9 + a8 b8 + a9 b7
+ a10808 b6 + a11 b5 + a12 b4 + a13 b3 + a14 b2 + a1545 b1 (17)

c52 c51 c3850 c49 s17 = c45 + c42 + c39 + c36 + a2 b15 + a3 b14 + a4 b13 + a5 b12 + a6 b11 + a7 b10 + a8 b9 + a9 b8
+ a10 b7 + a11808 b6 + a12 b5 + a13 b4 + a14 b3 + a15 b2 (18)

c56 c55 c54 c53 s18 = c49 + c43 + c46 + c40 + a3 b15 + a4 b14 + a5 b13 + a6 b12 + a7 b11 + a8 b10 + a9 b9 + a10 b8
+ a11 b7 + a12 b6 + a13 b5 + a14 b4 + a15 b3 (19)

c60 c59 c58 c57 s19 = c53 + c50 + c47 + c44 + a4 b15 + a5 b14 + a6 b13 + a7 b12 + a8 b11 + a9 b10 + a10 b9 + a11 b8 + a12 b7
+ a13 b6 + a14 b5 + a15 b4 (20)
 Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49 45

Table 1.
Comparison table of combinational delay for modified and traditional compressor adder.

Input bits Combinational delay (ns) Percentage improvement(%)

Traditional adder Compressor adder

5 5.663 5.294 6.5

10 6.875 6.791 1.2
15 8.156 7.676 5.9
20 8.500 8.050 5.9

c63 c62 c61 s20 = c57 + c54 + c51 + c48 + a5 b15 + a6 b14 + a7 b13 + a8 b12 + a9 b11 + a10 b10 + a11 b9 + a12 b8 + a13 b7
+ a14 b6 + a15 b5 (21)

c66 c65 c64 s21 = c61 + c58 + c55 + c52 + a6 b15 + a7 b14 + a8 b13 + a9 b12 + a10 b11 + a11 b10 + a12 b9
+ a13 b8 + a14 b7 + a15 b6 (22)

c69 c68 c67 s22 = c56 + c59 + c62 + c64 + a7 b15 + a8 b14 + a9 b13 + a10 b12 + a11 b11 + a12 b10 + a13 b9 + a14 b8 + a15 b7 (23)

c72 c71 c70 s23 = c67 + c65 + c63 + c60 + a8 b15 + a9 b14 + a10 b13 + a11 b12 + a12 b11 + a13 b10 + a14 b9 + a15 b8 (24)

c75 c74 c73 s24 = c70 + c68 + c66 + a9 b15 + a10 b14 + a11 b13 + a12 b12 + a13 b11 + a14 b10 + a15 b9 (25)

c78 c77 c76 s25 = c73 + c71 + c69 + a10 b15 + a11 b14 + a12 b13 + a13 b12 + a14 b11 + a15 b10 (26)

c81 c80 c79 s26 = c76 + c76 + c72 + a11 b15 + a12 b14 + a13 b13 + a14 b12 + a15 b11 (27)

c33 c32 s27 = c79 + c77 + c75 + a12 b15 + a13 b14 + a14 b13 + a15 b12 (28)

c85 c84 s28 = c82 + c80 + c78 + a13 b15 + a14 b14 + a15 b13 (29)

c87 c86 s29 = c84 + c83 + c81 + a14 b15 + a15 b14 (30)

c88 s30 = c85 + c86 + a15 b15 (31)

c89 s31 = c88 + c87 (32)

Clearly for the evaluation we require adder circuitry which can add 2,3,4,5,6,7,8,9,10,12,13,14,15,16,17,18,19 bits at the same
time. Here we propose to use the compressor adder structure in place of conventional adders.

4.2. Proposed hardware architecture

The proposed architecture shown in Fig. 7 uses the above equations and calculates each output bit separately for the product
of two 16 bit operands. It consists of the four main compressor adders 5-3, 10-4, 15-4 and 20-5 shown by using dark blue, red,
purple and brown color blocks respectively. Input to these adders is given in accordance with the equations and represented by
blue lines. Full and half-adder’s architectures also have been used at the required stages shown with green and graycolor blocks
respectively. Implementation of each equation gives a sum bit and some carries. These sum bits are product bits shown by red
line and carries go to next blocks again according to the equations. Carry flow is shown by green color. The use of multiplexer in
the proposed architecture brings the lesser XOR gate operation and causes the improvement of the speed of the multiplier. It also
reduces the parallel stages to implement the result which further enhances the speed of the Vedic multiplier by using ‘Vertically
and crosswise’ technique. The comparison of combinational delay of the used modified compressor adders with conventional
one and proposed multiplier with existing ones is presented in next section. Results support the improvement in speed by our
proposed architecture.
46 Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49

Fig. 7. Proposed hardware realization for 16 bit multiplication. (For interpretation of the references to color in this figure, the reader is referred to the web
version of this article.)

Table 2.
Comparison table of combinational delay for 16 bit Vedic multipliers

16 bit multiplier Combinational delay (ns) Percentage improvement (%)

Array multiplier 43.946 27

Wallace tree multiplier 46.046 30.5
Booth multiplier 37.041 13.6
Proposed multiplier 32

5. Results and comparisons

The architectures of 16 bit Vedic multiplier and modified compressor adders are designed in VHDL language. Logic synthe-
sis and simulation is done using EDA (Electronic Design Automation) tool in Xilinx ISE 13.1 simulator. Device used is XILINX:
SPARTAN 3E:XC3S500e fg320, speed grade – [Link] of combinational delay (ns) for the modified compressor adder with
conventional one is tabulated in Table 1. For inputs of bits 5, 10, 15 and 20 compressor adder has shown combinational delay (ns)
of 5.294, 6.791, 7.676 and 8.050, respectively which are lesser than conventional adders.
A combinational delay of 32 ns is seen for proposed 16 bit Vedic multiplier architecture which is small in comparison to the
Array, Wallace Tree and Booth multiplier clearly shown in Table 2. Our purposed architecture has shown approximately 27%,
30.5% and 13.6% improvement in comparison with Array, Wallace tree and Booth multiplier respectively. The higher speed of the
multiplier is come across by the use of modified compressor architectures. These compressors use multiplexer which is a low
 Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49 47

9
8
7
6

Time (ns)
5
Tradional adder
4
Compresser adder
3
2
1
0
5 bit 10 bit 15 bit 20 bit

Fig. 8. Comparison chart of combinational delay (ns) for modified compressor and traditional compressor adder.

50
45
40
35
Time (ns)

30
25
20
15
10
5
0
Array Wallace Booth Proposed
Mulplier Tree Mulplier Mulplier
Mulplier

Fig. 9. Comparison chart of combinational delay (ns) for different 16 bit Vedic multiplier.

Fig. 10. Simulation results for 5-3 compressor adder.

power and high-speed circuit and reduces the sum operations. The comparison table of the speed of the modified and original
compressors, given in Table 1, validates the use of modified compressor adder in our architecture.
Comparison charts of the modified compressor with conventional one and proposed 16 bit Vedic multiplier with Array, Wal-
lace tree and Booth multiplier is given in Figs. 8 and 9, respectively.
Figs. 10–13 show the simulation results for 5-3, 10-4, 15-4 and 20-5 compressor adders respectively. Compressor adder act as
counter and counts number of ‘1’s in input bit. Fig. 14 shows the simulation results for proposed 16 bit Vedic multiplier with ‘a’
and ‘b’ as 16 bit input bits and ‘s’ as an 32 output bit which is multiplication result of a and b.
48 Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49

Fig. 11. Simulation results for 10-4 compressor.

Fig. 12. Simulation results for 15-4 compressor.

Fig. 13. Simulation results for 20-5 compressor.

6. Conclusion and future scope

A novel technique for multiplication of 16 bit operands with the help of Vedic multiplier is described. The proposed architec-
ture is based upon ‘Urdhava-tiryakbhyam’ sutra of Vedic mathematics which is a general multiplication technique for multipli-
cation. This sutra makes the parallel generation of partial products and removes unwanted multiplication steps. Also with this
sutra increase in area and delay is less with increase in number of bits. This proposed technique works in two steps. First Step
is computation of equation for each bit of resultant. Second step is execution of that equation with required compressor adders.
These compressor adders add more than 4 bits at a time and use multiplexers in its circuitry which reduces the XOR gate opera-
tions and this results in reduction of delay. Compressor adders of 5-3, 10-4, 15-4, and 20-5 have shown speed improvement with
 Y. Bansal, C. Madhu / Computers and Electrical Engineering 49 (2016) 39–49 49

Fig. 14. Simulation results for proposed 16 × 16 Vedic multiplier.

percentage of 6.5, 1.2, 5.9 and 5.9, respectively over the traditional adders which use only half adder and full adder. A good result
in terms of speed is seen in the work with an approximate combinational path delay of 32 ns for multiplier. On comparing it with
Array, Wallace tree and Booth multiplier, it shows approximate percentage improvement of 27, 30.5 and 13.6, respectively in
terms of speed. This proposed optimized Vedic multiplier design may prove to be of great use in future digital signal processing
applications, ALU, MAC etc. with stringent demands of speed, area and power.

Supplementary materials

Supplementary material associated with this article can be found, in the online version, at doi:10.1016/[Link].2015.
11.006.

References

[1] Saokar SS, Banakar RM, Siddamal S. High-speed signed multiplier for digital signal processing applications. In: Proceedings of signal processing, computing
and control (ISPCC),; 2012. p. 1–6. doi:10.1109/ISPCC.2012.6224373.
[2] Kumar A, Raman A. Low power ALU design by ancient mathematics. In: Proceedings of IEEE international conference on aerospace and aviation engineering
(ICAAE); 2010. p. 862–5.
[3] Hanumantharaju MC, Jayalaxmi H, Renuka RK, Ravishankar M. A high-speed block convolution using ancient indian Vedic mathematics. In: Proceedings of
IEEE conference on computational intelligence and multimedia applications (ICCIMA); 2007. p. 169–73. doi:10.1109/ICCIMA.2007.332.
[4] Prakash AR, Kirubaveni S. Performance evaluation of FFT processor using conventional and Vedic algorithm. In: Proceedings of IEEE conference on emerging
trends in computing, communication and nanotechnology (ICE-CCN); 2013. p. 89–94. doi:10.1109/ICE-CCN.2013.6528470.
[5] Saha P, Banerjee A, Dandapat A, Bhattacharyya P. ASIC design of a high-speed low power circuit for factorial calculation using ancient Vedic mathematics.
Microelectron J 2011;42:1343–52.
[6] Ramalatha M, Thanushkodi K, Deena Dayalan K, Dharani P. A novel time and energy efficient cubing circuit using Vedic mathematics for finite field arith-
metic. In: Proceedings of advances in recent technologies in communication and computing; 2009. p. 873–5. doi:10.1109/ARTCom.2009.227.
[7] Aliparast P, Koozehkanani ZD, Khianvi AM, Karimian G, Bahar HB. A new very high-speed MOS 4-2 compressor for fast digital arithmetic circuits. In:
Proceedings of mixed design of integrated circuits and systems (MIXDES); 2010. p. 191–4.
[8] Jaina D, Sethi K, Panda R. Vedic mathematics Based Multiply Accumulate Unit. In: Proceedings of computational intelligence and communication systems
(CICN); 2011. p. 754–7. doi:10.1109/CICN.2011.167.
[9] Kunchigi V, Kulkarni L, Kulkarni S. High-speed and area efficient Vedic multiplier. In: Proceedings of international conference on devices, circuits and
systems (ICDCS); 2012. p. 360–4. doi:10.1109/ICDCSyst.2012.6188747.
[10] Gu J, Chang CH. Low voltage, low power (5-2) compressor cell for fast arithmetic circuits. In: Proceedings of international conference on acoustics, speech,
and signal processing (ICASSP); 2003. p. II-661-664. doi:10.1109/ICASSP.2003.1202453.
[11] Aliparast P. and Koozehkanani Z.D., Khiavi A.M., Karimian G., Bahar H.B.. A very high-speed CMOS 4-2 compressor using fully differential current-mode
circuit technique. Analog Integr Circ Sig Process (2011); 66: pp. 235-243.
[12] Radhakrishnan D, Preethy AP. Low power CMOS pass logic 4-2 compressor for high-speed multiplication. In: Proceedings of circuits and systems; 2000.
p. 1296–8.
[13] Marimuthu R, PradeepKumar M, Bansal D, Balamurugan S, Mallick PS. Design of high-speed and low power 15-4 compressor. In: Proceedings of international
conference on communications and signal processing (ICCSP); 2013. p. 533–6.
[14] Chowdhury SR, Banerjee A, Roy A, Hiranmay Saha H. Design, simulation and testing of a high-speed low power 15-4 compressor for high-speed multiplica-
tion applications. In: Proceedings of emerging trends in engineering and technology (ICETET ’08); 2008. p. 434–8. doi:10.1109/ICETET.2008.151.
[15] Huddar SR, Rupanagudi SR, Kalpana M, Mohan S. Novel high-speed Vedic mathematics multiplier using compressors. In: Proceedings of automation, com-
puting, communication, control and compressed sensing (iMac4s); 2013. p. 465–9. doi:10.1109/iMac4s.2013.6526456.

Yogita Bansal has received her [Link] in 2014 from University Institute of Electronics and Technology, Panjab University, Chandigarh, India in the field of
Microelectronics. Her area of interest includes Image processing and VLSI.

Charu Madhu has done her B.E. in 2002 and M.E. in 2007 in the field of Electronics and Communication. Currently, she is working as Assistant Professor
in Department of Electronics and Communication at University Institute of Electronics and Technology, Panjab University, Chandigarh, India. She has several
publications in reputed Journals and conference proceedings.