ADE Module-4

MODULE-4
Topics:

4.1Flip-Flop Timing
4.2 JK Master –Slave Flip-Flop
4.3 Switch contact Bounce circuits
4.4 Various representations of Flip-Flops
4.5 HDL implementation of Flip-Flop
4.6 SISO
4.7 SIPO
4.8 PISO
4.9 PIPO
4.10 Universal Shift register
4.11 Applications of Shift register
4.12 Register Implementation in HDL
4.13 Asynchronous Counters
4.14 Decoding Gates
4.15 Synchronous Counters
4.16 Counter Modulus

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FLIP-FLOP Timing:

Flip-flop cannot change states immediately, it always take small amount of time to
change its state. Figure below shows switching time of D-Flip- Flop.

Set-up time (tsetup): it is minimum amount of time that the data bit to be at the input before clock
edge arrives.

Hold time (thold): it is minimum amount of time that data bit must be present after clock edge.

Propagation delay (tp): the amount of time flip-flop takes to change its output after the input
changes

JK Master-Slave FLIP-FLOP:

 Two flip-flops are used in JK master Slave Flip-Flop, first Flip-Flop is Master, Second
Flip-Flop is Slave, Master is Positive Level-triggered Flip-Flop and Slave is Negative
Level-Triggered Flip-Flop. Output of Master Flip flop is depends on inputs J and K when
Clock is positive, output of master is connected to Slave, hence Slave follows the Master
when clock is negative.

Case 1: when clock C=1, and inputs J=K=0 , master output remains in last state, slave
follows the master when C=0, hence output Q remains in last state

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Case2: When C=1, J=1 and K=0, master output is 1, slave follows the master when clock =0,
hence Q=1

Case 3: when C=1, J=0, K=1 master output is 0, J and K inputs of slave are 0 and 1, when
C=0, output of slave Q =0

Case 4: When C=1 J=1, K=1, Master Toggles, slave also toggles when clock goes Low

Symbol Truth Table:

The symbol ┐appearing next to Q indicates Postponed Output. The master output is
dependent on inputs J and K while clock is high, the state of master is shifted to slave when
clock goes Low.

Switch Contact Bounce Circuits:

In digital system, Switches are used to generate Low and High voltages, SPST (single
pole single Throw) switch is used in the above figure, when Switch is open the voltage at
point A is +5v, when switch is closed, the voltage at point A is 0v, ideal waveform at point A
is shown in figure (b), but actual waveform at point A appears as shown in figure (C), as a
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result of a phenomenon known as contact bounce, when the switch arm is moved from one
position to another, the arm bounces twice or thrice, because of this bouncy arm the
waveform at point A appears as shown in figure (c)

RS Latch De-bounce Circuit:

RS Latch can be used to avoid the contact bounce problem, the output Q can be used to
generate desired waveform.

When switch is moved to position H, S=1and R=0, bouncing occurs at S input, the flip-
flop output Q becomes 1 when arm touches H for the first time, when arm bounces both inputs S
and R will become 0, hence flip flop output does not change, it remains 1, similarly when switch
is moved to position L, S=0 and R=1, flip-flop output Q becomes 0, when arm bounces, both R
and S will become 0, Q does not change, it remains 0.

Various Representations of SR Flip-Flop:

Characteristic equation of SR Flip-Flop can be derived from the truth of the SR flip –flop,
expressing next state of flip-flop (Qn+1) as a function of previous state Qn and inputs of flip-flop
is characteristic equation.

Truth table of SR flip-Flop: Characteristic table: Excitation Table:

S R Qn+1 Qn S R Qn+1 Qn Qn+1 S R
0 0 Qn 0 0 0 0
0 0 0 ×
0 0 1 0
0 1 0 0 1 0 1 0 1 1 0
1 0 1 0 1 1 × 1 0 0 1
1 0 0 1
1 1 forbidden 1 1 × 0
1 0 1 0
1 1 0 1
1 1 1 ×

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Characteristic Equation can be derived from characteristic table using K-map for output Qn+1

From the K-map Qn+1 can be written as

Qn+1 = S + R Qn

State Transition Diagram of SR Flip-Flop:

Various Representations of D-Flip Flop:

Truth Table: Characteristic table: Excitation Table:

D Qn+1 Qn D Qn+1 Qn Qn+1 D

0 0 0 0 0 0 0 0
1 1 0 1 1 0 1 1
1 0 0 1 0 0
1 1 1 1 1 1

Characteristic equation of D flip-flop can be derived from characteristic table using K-map for
output Qn+1
Characteristic Equation can be written as

Qn+1 = D

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State Transition Diagram of D Flip-Flop:

Various Representations of JK Flip-Flop:

Truth Table: Characteristic Table: Excitation Table:

J K Qn+1 Qn J K Qn+1 Qn Qn+1 J K

0 0 Qn 0 0 0 0
0 0 0 ×
0 0 1 0
0 1 0
0 1 0 1 0 1 1 ×
1 0 1 0 1 1 1
1 0 0 1 1 0 × 1
1 1 Qn 1 0 1 0 1 1 × 0
1 1 0 1
1 1 1 0

Characteristic Equation of JK Flip-Flop is

State Transition Diagram of JK Flip-Flop:

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T Flip-Flop:

 T Flip-Flop is also called as Toggle Flip-Flop.

 T Flip-Flop has only one input.

Symbol: Truth Table:

CLK T Qn+1

0 × Qn

0 Qn

1 Qn

Characteristic Table Characteristic Equation Excitation Table:

Qn Qn+1 T
Qn T Qn+1
0 0 0
0 0 0
0 1 1
0 1 1
1 0 1
1 0 1
1 1 0
1 1 0
State Transition diagram of T Flip-Flop:

Problem: A fictitious Flip-Flop with two inputs A and B Functions like this, For AB=00 and 11
the output becomes 0 and 1 respectively, for AB=01 Flip flop retains previous state while output
complements for AB=10, write truth table and excitation table of this Flip-Flop.

Truth Table: Characteristic Table: Excitation table:

A B Qn+1 Qn A B Qn+1 Qn Qn+1 A B
0 0 0 0 0 0 0 ×
0 0 0 0 0 1 0 0 1 1 ×
0 1 0 1
0 1 Qn 1 0 × 0
0 1 1 1
1 1 × 1
1 0 Qn 1 0 0 0
1 0 1 1
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HDL Implementation of Flip-Flops:

Program: Write Verilog Code for D Latch with Enable Input.

Characteristic Equation of D Latch is

Qn+1=D

program: Write Verilog code for SR Latch with Enable Input.

Characteristic Equation of SR Flip-Flop is

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Program: Write Verilog Code for Positive-Edge Triggered D Flip-Flop.

Program: Write Verilog Code for Positive-Edge Triggered D Flip-Flop.

Program: Write Verilog code for Positive-Edge Triggered D Flip-Flop with Asynchronous input
CLR

Registers:

 Register is a group of flip-flops, which is used to store a word.

 Bits in register can be shifted by applying clock signal, hence registers are also called as
Shift Register.

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Types of Registers:

Data can be shifted into a register either serially or in parallel, similarly data can be
shifted out of the register either serially or in parallel. Based on serial and parallel transmission,
registers are classified into four types

1. Serial in -Serial out Register

2. Serial in-Parallel out Register

3. Parallel in-Serial out Register

4. Parallel in-Parallel out register

Serial IN-Serial OUT Register:

Operation:

Assume initial state of counter is 0, hence Q3Q2Q1Q0 = 0000

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When bits 1011 are applied serially to register, data in the counter shifted as follows

At first clock Negative edge: LSB bit 1 will be shifted to FF-3, Q3 bit will be shifted to Q2, Q2
will be shifted to Q1, Q1 will be shifted to Q0, hence after first Negative edge of clock

Q3Q2Q1Q0 = 1000

At second Clock Negative Edge: Bit 1 is applied to FF-3, bits in counter will be shifted right side
by one position, after second clock negative edge

Q3Q2Q1Q0 = 1100

At third Clock Negative Edge: Bit 0 is applied to FF-3, bits in counter shifts right side, hence
after third clock negative edge

Q3Q2Q1Q0 = 0110

At Fourth Clock Negative Edge: Bit 1 is applied to FF-3, bits in counter shifts right side, hence
after third clock negative edge

Q3Q2Q1Q0 = 1011

Hence, after four clock cycles serial data 1011 is loaded in to the register

CLK Serial Q3 Q2 Q1 Q0
Data
0 0 0 0 0 0
1 1 1 0 0 0
2 1 1 1 0 0
3 0 0 1 1 0
4 1 1 0 1 1

Timing Waveforms:

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Serial IN-Parallel OUT Register:

In SIPO, Data bits are entered serially and data bits are taken at output in parallel as shown in the
figure.

Operation:

Assume initial state of counter is 0, hence Q3Q2Q1Q0 = 0000

When bits 1011 are applied serially to register, data in the counter shifted as follows

At first clock Negative edge: LSB bit 1 will be shifted to FF-3, Q3 bit will be shifted to Q2, Q2
will be shifted to Q1, Q1 will be shifted to Q0, hence after first Negative edge of clock

Q3Q2Q1Q0 = 1000

At second Clock Negative Edge: Bit 1 is applied to FF-3, bits in counter will be shifted right side
by one position, after second clock negative edge

Q3Q2Q1Q0 = 1100

At third Clock Negative Edge: Bit 0 is applied to FF-3, bits in counter shifts right side, hence
after third clock negative edge

Q3Q2Q1Q0 = 0110

At Fourth Clock Negative Edge: Bit 1 is applied to FF-3, bits in counter shifts right side, hence
after third clock negative edge

Q3Q2Q1Q0 = 1011

Hence, after four clock cycles serial data 1011 is loaded in to the register

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CLK Serial Q3 Q2 Q1 Q0
Data
0 0 0 0 0 0
1 1 1 0 0 0
2 1 1 1 0 0
3 0 0 1 1 0
4 1 1 0 1 1

Parallel IN –Parallel Output register:

In PIPO register, All data bits b3b2b1b0 are applied in parallel and outputs Q3Q2Q1Q0 are
collected in parallel.

Operation:

Assume initially all flip-flops are in state 0, hence output Q3Q2Q1Q0=0000, to put the data bits
1011 in to register, apply these four bits in parallel, at positive clock edge these four bits will be
stored in four flips simultaneously, hence outputs Q3Q2Q1Q0 = 1011, one clock cycle is enough to
store all four bits into register.

CLK b3 b2 b1 b0 Q3 Q2 Q1 Q0
1 1 0 1 1 1 0 1 1

Parallel IN-Serial OUT Register:

In Parallel IN-Serial OUT register, data bits b3b2b1b0 are applied as input in parallel to register,
bits are shifted out serially.

Figure below shows 4-bit Parallel IN-Serial OUT register

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Operation:

To Shift data into register:

To shift the data in register serially, set LOAD/SHIFT =0, since inversion of
LOAD/SHIFT is applied as input for AND gates 1a, 1b, 1c, inputs for AND gate 1a are Q3 and 1
hence AND gate 1a output =Q3, similarly output of AND gate 2a is Q2 and output of AND gate 3a
is Q1, since LOAD/SHIFT is connected directly to AND gate 1b, 2b,3b hence input for all AND
gates 1b,2b,3b is 0, output of all AND 1b,2b,3b gates 2 is 0.

Output of AND gates are connected to inputs of OR gates as shown in figure, inputs of OR gate
1 are 1, Q3 hence OR gate1 output =Q3, similarly OR gate 2 Output =Q2, OR gate 3 output =Q1,
OR gate 1 output Q3 is applied as input to second flip flop, OR gate 2 output Q2 is applied as input
to third flip-flop, output of OR gate 3 Q1 is applied as input to fourth flip-flop, hence Q3 is shifted
to Q2, Q2 is shifted to Q1, Q1 is shifted to Q0.

To Load data into register:

To load data b3b2b1b0=1011 into register in parallel, set LOAD/SHIFT =1, since
inversion of LOAD/ SHIFT is connected to 1a, 2a, 3a, outputs of AND gates 1a, 2a, 3a are 0, b3 is
connected directly as input to FF-3, inputs for AND gate 1b are 1, b2 hence its output is b2,
similarly output of AND gates 2b is b1, output of AND gate 3b is b0.

Outputs of OR gates are connected as inputs to FF-2 FF-1 and FF-0, inputs for OR gate 1 are 0,
b2, hence OR gate 1 output is b2 which is connected as input for FF-2, similarly output of OR gate
2 is b1, which is connected as input to FF-1, output of OR gate 3 is b0, which is connected as input
for FF-0, hence the data b3 b2 b1 b0 is loaded to FF-3 FF-2 FF-1 and FF-0 respectively
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Truth table when LOAD/SHIFT=0 and assume initial values of Q3Q2Q1Q0=0000 to put data
1011 into register serially, apply the bits 1011 serially at b3

CLK b3 Q3 Q2 Q1 Q0
1 1 1 0 0 0
2 1 1 1 0 0
3 0 0 1 1 0
4 1 1 0 1 1

Applications of Shift Register:

1. Ring Counter
2. Switched-Tail Counter or Johnson counter
3. Sequence Generator & Sequence Detector
5. Serial Adder
Ring Counter:

 In ring counter, output of Last flip-flop is connected to input of the first flip-flop.
 It is also called as circulating register.
 Number of states = Number of Flip-flops

Operation:

Initially, SET input is made 0, it sets the flip-flop3 hence Q3=1, and it clears all other
three flip-flops hence, Q2=0, Q1=0, Q0=0. When first negative clock occurs, the output of flip-
flop 3 is shifted to flip-flop 2, output of flip-flop 2 is shifted to flip-flop 1, this cycle repeats at
every negative clock cycle. As shown in truth table, 1 is shifting around register each time the
clock goes negative.

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Truth Table: Timing Diagram:

SET CLK Q3 Q2 Q 1 Q0
0 × 1 0 0 0
1 0 1 0 0
1 0 0 1 0
1 0 0 0 1
1 1 0 0 0

Johnson counter or Switched-Tail counter:

 In Johnson’s counter, inverted output (Q) from the last flip-flop is connected to the input
of first flip-flop.
 Number of states = twice the number of flip-flops

Operation:

Initially, the CLEAR input is made 0, hence all flips-flops outputs will be 0, since Q0 is
connected to input of first flip flop, when clock goes negative, the output of FF-3 becomes 1 and
its previous output will be shifted to FF-2, FF-2 output will be shifted to FF-1 and so on, this
cycle repeats for every negative cycle.

Truth Table:

CLEAR CLK Q3 Q2 Q1 Q0
0 × 0 0 0 0
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
1 1 1 1 1
1 0 1 1 1
1 0 0 1 1
1 0 0 0 1

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Sequence Generator:

The shift register can be used to generate particular bit pattern repetitively, figure below
shows the basic block diagram of a sequence generator, Left most flip-flop accept the serial input
and right most flip-flop gives serial data output, serial data output is connected back to serial data
input, on every clock cycle, data shifts right, if we load desired bit pattern in register, same bit
pattern will be produced repetitively,

Sequence Detector:

Sequence detector can be used to detect desired sequence, as shown in figure below,
circuit uses two registers, one register is used to store bit pattern to be detected, and other register
accepts the input data bits serially, and sends the data out serially, on every clock cycle each and
every bit of both registers are compared using EX-NOR gates, when both inputs are same EX-
NOR gate produces high output, when the content of both registers are equal, all EX-NOR gates
produces 1, outputs of EX-NOR gates are connected to AND gate, hence AND gate produces 1
when all bits are equal in two registers, otherwise it produces zero.

As shown in figure, sequence to be detected is 1011, it is stored in below register, in

upper register data enters serially, when sequence of bits in upper register becomes 1011, AND
gate produces high output which indicates desired sequence is detected.

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Serial Adder:

Serial adder can be used to add two numbers bit by bit by using two registers, which hold
two numbers, and Full adder to perform addition at every negative clock cycle.

Operation:

On first negative clock cycle, LSB of two number A and B i.e. A0 and B0 are added by
full adder, sum S0 and carry C0 are produced, Sum S0 will be applied at serial in of Register A
and carry C0 is applied to D-Flip flop, on second negative cycle S0 will be stored in register A at
MSB position, full adder adds A1 and B1 and carry C0 from D Flip Flop will be added by , Sum
S1 and C1 are produces, on next negative clock cycle, S1 will ne stored in register A at MSB
position, S0 in register will be shifted right by one position, full adder will add A2 and B2 and
produces S2 and C2, this process continues, after 8 clock cycles final sum S7S6S5S4S3S2S1S0 will
be stored in Register A.

Universal Shift Register:

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A register which can shift data in both directions, and accepts data in serial as well as in
parallel is called Universal Shift Register. It can perform operations of all registers, SISO,
SIPO, PISO, PIPO.

Above figure shows the Universal shift register, four 4:1 multiplexers and 4 D-Flip Flops
are used, Select Lines S1 S0 are used to control the operations of universal shift register.

When S1S0 = 00, universal shift registers remains in previous state i.e. all flip-flops hold
previous outputs (Qn)

When S1S0 = 01, serial data input is applied to 1 input of left most Multiplexer, and data
will be shifted right.

When S1S0 = 10, serial data input is applied to 2 input of right most multiplexer, and data
will be shifted left.

When S1S0 = 11, parallel data b3b2b1b0 is applied to 3 input of all multiplexers
respectively, these parallel inputs will be loaded into flip-flops in parallel.

S1 S0 Function
0 0 Previous state (HOLD)
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load

Register Implementation in HDL:

Program: Write Verilog code for 6-bit negative edge triggered parallel input parallel
output register

module PIPO (D, CLK, CLR, Q);

input CLK, CLR;
input [5:0] D;
output [5:0] Q;
reg [5:0] Q;
always @ (negedge CLK or negedge CLR)
if (CLR==0) Q=6’b000000;
else Q=D;
endmodule

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Program: Write Verilog code for 4-bit negative edge triggered SISO

module SISO(D, CLK, T);

input CLK, D;
output T;
reg Q,R,S,T;
always @ (negedge CLK)
Q <= D;
R <= Q;
S <= R;
T <= S;
endmodule

Program: Write Verilog Code for negative edge triggered serial input parallel output
register

module SIPO(D, CLK, Q);

input CLK, D;
output [3:0]Q;
reg [3:0]Q;
Always @ (negedge CLK)
Q[3] <= D;
Q[2] <= Q[3];
Q[1] <= Q[2];
Q[0]<=Q[1];
endmodule

Program: Write Verilog code for Johnson Counter

module JC(CLK,Q);
input CLK;
ouput [3:0]Q;
reg [3:0]Q;
Always @ (negedge CLK)
Q[3] = ~ Q[0];
Q[2] = Q[3];
Q[1] = Q[2];
Q[0] = Q[1];
endmodule

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Counter: Counter is a series of flip-flops used to count number of clock cycles.

Number of counts (states) of flip-flop = 2n
n number of flip flops
E.g. if counter has three flip-flops, n=3, the number of states =23 = 8 states (0-7)
There are two types of counters
1. Asynchronous Counter
2. Synchronous Counter
Asynchronous UP Counter or Ripple Counter:

 In Asynchronous counter, clock is connected to first flip-flop, the output of first flip-flop
is connected to clock input of second flip-flop, and output of second flip-flop is
connected to clock input of third flip-flop.
 Negative-Edge Triggered JK Flip-Flops can be used to design Asynchronous counter as
shown in figure below.
 JK inputs of each flip-flop is connected to +Vcc, each flip-flop toggles its state at negative
edge of the clock.

Operation:

Assume initial state of all flip-flops is 0, hence CBA=000, at first negative edge of clock,
flip-flop A toggles to 1, hence output is CBA=001, flip-flop A toggles its state for every
negative edge of the clock, since the output of flip-flop A is connected as clock input to
flip-flop B, B toggles its state at every second negative edge of the clock, Flip-flop C
toggles its state at every fourth negative edge of the clock.

Timing Waveforms:

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Truth Table:

Asynchronous Down Counter:

 In Asynchronous down counter, count decreases by one for every negative edge of clock,
 In down counter, the complemented output of flip-flop is connected to clock input of next
flip-flop.

Operation:

Flip-flop A toggles its state at every negative edge of the clock, Flip-flop B toggles its
state when A changes from 1 to 0, similarly flip-flop C toggles when B changes from 1 to 0.

Timing Waveforms: Truth Table:

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Asynchronous UP-DOWN Counter:

Operation:

When count-up is 1 and count-down is 0, upper AND gate connects the output of flip-
flop to clock input of next flip-flop, hence counter works as UP-counter.

When Count-up is 0 and count-down is 1 Lower AND gate connects Complemented

output of flip-flop to clock input of next flip-flop, hence counter works as down counter.

Decoding Gates:

A Decoding gate can be connected to the outputs of a counter in such a way that the
output of gate will be HIGH only when the counter contents are equal to a given state.

Example: the Decoding gate connected to the 3-bit ripple counter in figure below will decode
state 7 i.e. C B A = 111, thus gate output is high only when C B A=111

Gate to decode state 5: Gate to decode state 0: Gate to decode state 1:

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Gate to decode 2 Gate to decode 3 Gate to decode 4 Gate to decode 5

Disadvantage of Asynchronous or Ripple counter:

 Each Flip-flop has to wait for the previous flip-flop output; it increases the delay at the
counter output.
 Glitches may occur at the output of decoding gates.

Synchronous UP Counter:

In Synchronous counter, same clock is applied to all the flip-flops, all flips flops get
triggered simultaneously.

J and K inputs of all flip-flops are connected to VCC, hence all flip-flops change its state
at negative clock edge. And gate is used to connect clock and output of previous flip-flop to
clock input of next flip-flop.

Operation:

Assume initially all flip-flops are in state 0, hence CBA=000, clock is applied directly to
flip-flop A, it changes its state at every negative clock edge, since clock and FF-A output is
connected to clock input of Flip-flop B through AND gate, FF-B changes its state at every
second negative clock edge, similarly FF-C changes its output at every fourth negative clock
cycle, since three flip-flops are used count starts from 000 to and last state is 111 after 111 it
repeats the count from 000

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Truth table and timing waveforms of Synchronous Up Counter:

Synchronous Down Counter:

In synchronous Down counter, ALL J and K inputs are tied to VCC and clock is applied
directly to FF-A, complemented output of FF-A and clock is connected to clock input of FF-B
through AND gate, complemented outputs of FF-A and FF-B and clock are connected to clock
input of FF-C through AND gate.

Operation:

Assume initial state of all Flip-flops is 0, hence QCQBQA=000,Clock is applied directly to

FF-A, it changes its state at every negative clock edge, FF-B changes its state at every second
negative clock edge, FF-C changes its state at every fourth negative clock cycle.

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Truth table and timing waveforms of Synchronous Down Counter:

QC QB QA Count
1 1 1 7
1 1 0 6
1 0 1 5
1 0 0 4
0 1 1 3
0 1 0 2
0 0 1 1
0 0 0 0

Synchronous UP-DOWN Counter:

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All JK inputs are connected to VCC, both outputs of FFA are connected to clock input of
FFB through two AND gates, both outputs of FF A and FFB and clock is connected to clock
input of FF C through two AND gates.

Count-UP Mode:

When count-up control input is made 1 and count-down is made 0, clock is applied
directly to FF-A, and upper AND gates are enabled, Lower AND gates outputs are zero hence
Lower AND gates are disabled, hence FF-A output and CLOCK Is connected to connected to
clock input of FF-B, outputs of FF-A and FF-B and clock are connected to clock input of FF-C,
hence counter works as UP-counter.

Count –Down Mode:

When count-down control input is made 1 and count-up is made 0, clock is applied directly to
FF-A, and Lower AND gates are enabled, Upper AND gates outputs are zero hence upper AND
gates are disabled, hence complemented output of FF-A and CLOCK Is connected to connected
to clock input of FF-B, complemented outputs of FF-A and FF-B and clock are connected to
clock input of FF-C, hence counter works as DOWN-counter

Changing Counter Modulus:

In counter Modules = number of states in counter= 2n, where ‘n’ is number of flip-flops,
modifying number of states of counter is called changing counter modulus.

Example: when two flip-flops are used for counter, number of states =4, it can be modified
to 3 as shown below.

MOD-3 counter:

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Operation:

1. Prior to point ‘a’ on the time line, A=0 and B=0 , a negative clock at ‘a’ will cause

a. A to toggle to 1 since its J and K inputs are high

b. B remains 0, since its J=0 and K=1
2. Prior to point ‘b’ on the time line, A=1 and B=0 , a negative clock at ‘b’ will cause
a. A to toggle to 0 since its J and K inputs are high
b. B to toggle to 1, since its J=1 and K=1
2. Prior to point ‘c’ on the time line, A=0 and B=1 , a negative clock at ‘c’ will cause
a. A remains 0 since its J=0 and K=1
b. B changes to 0, since its J=0 and K=1

Truth table of MOD-3 Logic Block of MOD-3

MOD-6 Counter:

MOD-6 counter can be designed by using MOD-3 and MOD-2 Counter (for MOD-2
single Flip-flop is enough) if B output of MOD-3 is connected to clock input of next flip-flop, it
works as MOD-6 counter.

Waveforms of MOD-6

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ADE Module-4

Truth table of MOD-6:

CLK Q B A
0 0 0 0 Note: This MOD-6 counter has 6 states, but count is not in straight sequence
1 0 0 1
2 0 1 0
3 1 0 0
4 1 0 1
5 1 1 0

Truth Table:
Note: this mod-6 counter has 6 states, count is in straight sequence
CLK B A Q
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1

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ADE Module-4

Comparison between Asynchronous and Synchronous Counters:

Asynchronous Counter Synchronous Counter

1. Output of flip-flop is connected to clock of 1. clock inputs of all flip-flops are connected to
next flip-flop same external clock

2.Flip-flops are not triggered simultaneously 2. ALL Flip-flops are triggered simultaneously

3. Design is simple 3. Design is difficult

4. Asynchronous counter is slow 4. Synchronous Counter is faster.

Important Questions

1. What is Race-Around Condition? With block diagram and truth table explain working of JK
Master-Slave Flip-Flop JAN&JUL -17 (10 M)

2. Give State transition diagram and characteristic equations for JK and SR Flip-Flop
JAN-17 (6 M)
3. With neat diagram, explain Ring Counter JAN-17 (4 M)
4. What is shift register? With neat diagram explain 4 –bit PISO register JAN-17 (8 M)
Register in which binary bits are shifted either right side or left side is called as shift register.
5. Compare Synchronous and Asynchronous counters JAN&JUL-17 (4 M)
6. Derive characteristic equations for SR, D and JK Flip-flop JUL-17 (6 M)
7. Using negative edge triggered D Flip-flop, draw logic diagram of 4 bit SISO register , draw
waveform to shift Binary number 1010 into this register JUL-17 (6 M)
8. Explain with neat diagram how shift register can be used for serial addition JUL-17 (7 M)
9. With circuit diagram explain MOD-3 Counter
10. Design Mod-6 counter using MOD-3 and MOD-2 Counters
11. Write Verilog code for SIPO
12. Explain the operation of Universal shift register
12. Write Verilog code for Positive-Edge triggered D-Flip-Flop

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