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DSP Algorithms and Architecture Overview

This document outlines a lesson plan for a course on DSP Algorithms and Architecture. The course is divided into 8 units covering topics such as digital signal processing systems, DSP architectures, programmable DSP processors, implementation of DSP algorithms, and interfacing DSP devices. The plan lists 51 classes covering these topics from August 2010 to October 2010. It also provides textbook and reference book recommendations.

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303 views3 pages

DSP Algorithms and Architecture Overview

This document outlines a lesson plan for a course on DSP Algorithms and Architecture. The course is divided into 8 units covering topics such as digital signal processing systems, DSP architectures, programmable DSP processors, implementation of DSP algorithms, and interfacing DSP devices. The plan lists 51 classes covering these topics from August 2010 to October 2010. It also provides textbook and reference book recommendations.

Uploaded by

patilrajuc
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

P E S Institute of Technology & Management

NH-206, Sagar Road, Shivamogga – 577204


Phone: 08182-640733 Fax: 08182-233797
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Lesson Plan
Subject :DSP Algorithms And Architecture. Subject code : 06EC74
IA Marks : 21 Hrs / Week : 04
Exam Hours : 03 Total Hours : 52
Exam marks : 100 Prepared on : 07/08/2010

Class Planned Conducted


Topics to be Covered Remark
No. Date Date

PART – A

UNIT – 1: INTRODUCTION TO DIGITAL SIGNAL PROCESSING 05 Hours

01 Introduction, A Digital Signal-Processing System. 02-08-10 01


02 The Sampling Process. 03-08-10 01
Discrete Time Sequences, Discrete Fourier
03 04-08-10 01
Transform (DFT).
Fast Fourier Transform (FFT), Linear Time-
04 Invariant Systems, 07-08-10 01

05 Digital Filters, Decimation and Interpolation 09-08-10 01


UNIT – 2 : ARCHITECTURES FOR PROGRAMMABLE DIGITAL SIGNAL-
08 Hours
PROCESSORS
06 Introduction, Basic Architectural Features 10-08-10 01
07 DSP Computational Building Blocks 11-08-10 01
08 Bus Architecture and Memory. 14-08-10 01

09 Bus Architecture and Memory Contd.. 16-08-10 01

10 Data Addressing Capabilities. 17-08-10 01


11 Address Generation Unit. 18-08-10 01
12 Programmability and Program Execution. 21-08-10 01
13 Features for External Interfacing 23-08-10 01

UNIT – 3 : PROGRAMMABLE DIGITAL SIGNAL PROCESSORS 06 Hours

Introduction, Commercial Digital Signal-


14 processing Devices 24-08-10 01

15 Data Addressing Modes of TMS32OC54xx., 25-08-10 01


16 Data Addressing Modes of TMS32OC54xx., 28-08-10 01
17 Memory Space of TMS32OC54xx Processors, 30-08-10 01
P E S Institute of Technology & Management
NH-206, Sagar Road, Shivamogga – 577204
Phone: 08182-640733 Fax: 08182-233797
18 Memory Space of TMS32OC54xx Processors, 31-08-10 01
19 Program Control. 01-09-10 01

UNIT – 4 : PROGRAMMABLE DIGITAL SIGNAL PROCESSORS Continued… 06 Hours

20 Detail Study of TMS320C54X & 54xx Instructions 04-09-10 01


21 TMS320C54X & 54xx Programming 06-09-10 01
22 On-Chip peripherals. 07-09-10 01
23 Interrupts of TMS32OC54XX Processors. 08-09-10 01
24 Interrupts of TMS32OC54XX Processors. 11-09-10 01
25 Pipeline Operation of TMS32OC54xx Processor. 13-09-10 01

PART-B

UNIT – 5 : IMPLEMENTATION OF BASIC DSP ALGORITHMS 06Hours

26 Introduction, The Q-notation 14-09-10 01


27 FIR Filters. 15-09-10 01
28 IIR Filters. 18-09-10 01
29 Interpolation Filters. 20-09-10 01
30 Decimation Filters. 21-09-10 01
31 Examples. 22-09-10 01

UNIT – 6 : IMPLEMENTATION OF FFT ALGORITHMS 06 Hours

Introduction, An FFT Algorithm for DFT


32 25-09-10 01
Computation.
33 An FFT Algorithm for DFT Computation. 27-09-10 01
34 Overflow and Scaling. 28-09-10 01
35 Overflow and Scaling. 29-09-10 01
Bit-Reversed Index Generation & Implementation
36 on the TMS32OC54xx. 04-10-10 01

Bit-Reversed Index Generation & Implementation


37 05-10-10 01
on the TMS32OC54xx.
UNIT-7 INTERFACING MEMORY AND PARALLEL I/O PERIPHERALS TO DSP
08 Hours
DEVICES
38 Introduction, Memory Space Organization 06-10-10 01
39 Introduction, Memory Space Organization 09-10-10 01
P E S Institute of Technology & Management
NH-206, Sagar Road, Shivamogga – 577204
Phone: 08182-640733 Fax: 08182-233797
40 External Bus Interfacing Signals. 11-10-10 01
41 Memory Interface. 12-10-10 01
42 Parallel I/O Interface. 13-10-10 01
43 Programmed I/O. 18-10-10 01
44 Interrupts and I / O 19-10-10 01
45 Direct Memory Access (DMA). 20-10-10 01
UNIT-8 : INTERFACING AND APPLICATIONS OF DSP PROCESSOR 06 Hours
46 Introduction, Synchronous Serial Interface. 23-10-10 01
47 A CODEC Interface Circuit. 25-10-10 01
48 DSP Based Bio-telemetry Receiver. 26-10-10 01
49 A Speech Processing System 27-10-10 01
50 An Image Processing System. 30-10-10 01
51 An Image Processing System. 08-10-10 01

TEXT BOOKS:
1. “Digital Signal Processing”, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

REFERENCE BOOKS:
1. Digital Signal Processing: A practical approach, Ifeachor E. C., Jervis B. W Pearson-
Education, PHI/ 2002
2. “Digital Signal Processors”, B Venkataramani and M Bhaskar TMH, 2002
3. “Architectures for Digital Signal Processing”, Peter Pirsch John Weily, 2007

Prepared by Checked by the HOD Approved by the Principal

Signature

Date 07 / 08 / 2010
Mr. Pradeep Kumar
Name [Link] M Yadhahalli Dr. Vishwanath P. Baligar
CM

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