CHAPTER 2 – SUBSTRATE PREPARATION
2.1 Wafer Preparation
SEMICONDUCTOR ELECTRONICS
MATERIALS
Types of Semiconductors:
•Elemental: Silicon or Germanium (Si or Ge) – group IV
•Compound: Gallium Arsenide (GaAs) & Indium
Phosphide (InP) - III-V, and ZnS – II-VI
Compound Semiconductors:
Offer high performance
(optical characteristics,
higher frequency, higher
power) than elemental
semiconductors and greater
device design flexibility due
to mixing of materials.
ADVANTAGES OF SI OVER GE
Silicon is the most important semiconductor for the
microelectronics industry. When compared to
germanium, silicon excels for the following reasons:
(1) Si has a larger bandgap (1.1 eV for Si versus 0.66 eV
for Ge).
(2) Si devices can operate at a higher temperature (150oC
vs 100oC).
(3) Intrinsic resistivity is higher (2.3 x 105 Ω-cm vs 47 Ω-
cm).
(4) SiO2 is more stable than GeO2 which is also water
soluble.
(5) Si is less costly.
CRYSTAL STRUCTURE
Amorphous Materials
No discernible long range atomic order (no detectable crystal
structure). Examples are silicon dioxide (SiO2), amorphous-Si, silicon
nitride (Si3N4), and others. Though usually thought of as less perfect
than crystalline materials, this class of materials is extremely useful.
Polycrystalline Materials
Material consisting of several “domains” of crystalline material. Each
domain can be oriented differently than other domains. However, within
a single domain, the material is crystalline. The size of the domains
may range from cubic nanometers to several cubic centimeters. Many
semiconductors are polycrystalline as are most metals.
Crystalline Materials
Crystalline materials are characterized by an atomic symmetry that
repeats spatially. The shape of the unit cell depends on the bonding of
the material. The most common unit cell structures are
diamond,zincblende (a derivative of the diamond structure), hexagonal,
and rock salt (simple cubic).
CRYSTAL STRUCTURE
Crystal Structure
• The processing characteristics and some material properties of
silicon wafers depend on its orientation.
• The <111> planes have the highest density of atoms on the
surface, so crystals grow most easily on these planes and oxidation
occurs at a higher pace when compared to other crystal planes.
• Traditionally, bipolar devices are fabricated in <111> oriented
crystals whereas <100> materials are preferred for MOS devices.
LATTICE ORIENTATION
The lattice orientation refers to the organized
pattern of the silicon crystals in the wafer and
their orientation to the surface.
The orientation is obtained based on the
orientation of the crystal that is placed into the
molten silicon bath.
The different orientations have different benefits
and are used in different types of chips.
DEFECTS IN SILICON CRYSTALS
1. Grown-in defects from crystal pulling
2. Defects resulting from wafering
3. Process-induced defects
Classification of defects:
I. Point defects
II. Line defects
III. Area defects
IV. Bulk defects
THE CHIP MANUFACTURING PROCESS
Wafer preparation process
FROM SAND - MOLTEN SILICON TO IC CHIP
WAFER PREPARATION
Wafer preparation (or substrate) is the
beginning of the process in making an IC chip .
The goal for this part of the process is to grow
the ingot that will be sliced up into wafers.
The wafer is a round solid silicon disc that will
have all of the processing performed on it.
STEP 1: OBTAINING THE SAND
The sand used to grow the wafers has to be a
very clean and good form of silicon.
For this reason not just any sand scraped off
the beach will do.
Most of the sand used for these processes is
shipped from the beaches of Australia.
STEP 2: PREPARING THE MOLTEN
SILICON BATH
The sand is taken and put into a pot
where it is heated to about 1600 degrees
C where it melts.
The molten sand will become the source
that will ultimately produce the raw poly-
crystalline silicon.
1- RAW POLYSILICON
Raw polycrystalline silicon
produced by mixing refined
trichlorosilane (SiHCl3) with
hydrogen gas in a reaction
furnace.
The poly-crystalline silicon is
allowed to grow on the surface
of electrically heated tantalum
hollow metal wicks
2- POLYSILICON INGOTS
Polycrystalline silicon has
randomly oriented crystallites,
electrical characteristics not
ready for device fabrication.
Must be transformed into
single crystal silicon using
crystal pulling
3- ELECTRONIC GRADE SILICON
Electronic-grade silicon (EGS), a
polycrystalline material of high purity,
is the starting material for the
preparation of single crystal silicon.
EGS is made from metallurgical-grade
silicon (MGS) which in turn is made
from quartzite, which is a relatively
pure form of sand. MGS is purified by
the following reaction:
Si(solid) + 3HCl (gas) →SiHCl3 (gas) +
H2 (gas) + heat
The boiling point of
trichlorosilane (SiHCl3) is 32oC
and can be readily purified
using fractional distillation.
EGS is formed by reacting
trichlorosilane with hydrogen:
SiHCl3 (gas) + H2 (gas) →Si
(solid) + 3HCl (gas)
STEP 3: MAKING THE INGOT
( CZOCHRALSKI PROCESS)
A pure silicon seed
crystal is now placed
into the molten sand
bath.
This crystal will be
pulled out slowly as it
is rotated.
The result is a pure
silicon tube that is
called an ingot
https://www.youtube.com/watch?v=xftnhfa-Dmo
INGOT SIZES
Most ingots produced
today are 150mm (6")
and 200mm (8")
diameter,
For the most current
technology 300mm
(12") and 400mm (16")
diameter ingots are
being developed.
DEVELOPMENT OF WAFER DIAMETERS
COMPARISON OF MATERIAL PROPERTIES
AND REQUIREMENTS FOR VLSI
CRYSTAL GROWTH: ADDING IMPURITIES
Impurities can be added to the melt to dope
the semiconductor as p-type or n-type.
Generally, impurities “prefer to stay in the
liquid” as opposed to being incorporated into
the solid. This process is known as
segregation.
The degree of segregation is characterized by
the segregation coefficient, k, for the
impurity, (k = Cs/Cl)
• As pulling advances, the melt volume
decreases, dopant concentration in the melt
increases and therefore dopant concentration Cs
can be calculated as impurity distribution:
PROBLEM: If wafer resistivity specifications are 5-
10 Ohm-cm (phosphorous), calculate which fraction
of the ingot that yields wafers within this
specification.
5 Ohm-cm Cs = 8*1014 cm-3 (FROM Figure 4.1)
(k = Cs/Cl)
10 Ohm-cm C0 = 4*1014 cm-3 / 0.35 = 1.14*1015 cm-3
Where k0 = 0.35 is the segregation coefficient of phosphorous.
Cs k0C0 1 X
k0 1
8*1014 cm-3 = 0.35 * 1.14*1015 cm-3 (1-X)0.35-1
X = 0.66
Roughly 2/3 of the ingot is within specs.
Of course the rest can be sold with different specs.
STEP 4: PREPARING THE WAFERS
The ingot is grind into
the correct diameter
for the wafers.
Then it is sliced into
very thin wafers.
This is usually done
with a diamond saw.
DIAMETER GRINDING
Silicon Wafer Grinding for Labeling
450 main base section main base section
additional section
111 n-type 111 p-type
1800
main base section main base section
900
additional section
additional section
100 , n-type 100 , p-type
FLAT GRINDING
SAWING
SURFACE GRINDING
WAFER LAPPING
The sliced wafers are
mechanically lapped
using a counter-rotating
lapping machine and
aluminum oxide slurry.
This flattens the wafer
surfaces, makes them
parallel and reduces
mechanical defects like
saw markings
WAFER LAPPING MACHINE
Different edge rounding
WAFER ETCHING
After lapping, wafers are etched in a solution of
nitric acid/ acetic acid or sodium hydroxide to
remove microscopic cracks or surface damage
created by the lapping process.
The acid or caustic solution is removed by a
series of high-purity RO/DI water baths
DONOR ANNEALING
Thermal donors are
charged interstitial
oxygen complexes
which behave like n-
type dopants.
An annealing step at
600-800 C destroys
thermal donors and
stabilizes wafer
resistivity
WAFER POLISHING
Next, the wafers are
polished in a series of
combination chemical
and mechanical polish
processes called CMP
The wafers are held in a
hard ceramic chuck using
either wax bond or
vacuum and buffed with a
slurry of silica powder,
RO/DI water and sodium
hydroxide
WAFER CLEANING
Most wafer manufacturers use a 3-step process
which starts with an SC1 solution (ammonia,
hydrogen peroxide and RO/DI water) to remove
organic impurities and particles from the wafer
surface.
Next, natural oxides and metal impurities are
removed with hydrofluoric acid.
Finally, the SC2 solution, (hydrochloric acid and
hydrogen peroxide), causes super clean new
natural oxides to grow on the surface.
CRITICAL CLEANING
Contact locations
n-w ell p-w ell
p-channel transistor n-channel transistor
p+ substrate
Process Conditions
1 2 3 4 5
Temperature: Piranha Strip is 180 degrees C.
1 Organics 2 Oxides 3 Particles 4 Metals 5 Dry
H2SO4 + HF + NH4OH + HCl + H2O or IPA +
H2O2 H2O H2O2 + H2O H2O2 + H2O N2
H2O Rinse H2O Rinse H2O Rinse H2O Rinse
RCA Clean Nitride Strip Dry Strip Solvent Cleans
SC1 Clean (H2O + NH4OH + H2O2) * H3PO4 * N2 O NMP
* SC2 Clean (H2O + HCl + H2O2) * Oxide Strip O2 Proprietary Amines (liquid)
Piranha Strip HF + H2O * CF4 + O2 Dry Cleans
* H2SO4 + H2O2 * O3 HF
O2 Plasma
Alcohol + O3
THICKNESS LOSS FOR 200 MM WAFERS
SI WAFER TYPES IN PRODUCTION
Reclaim (Dummy) wafer
Test wafer
Prime wafer
SiWafer
SOI Wafer
Reclaimed Silicon Wafers
•Reclaiming wafers is a process in which, the wafers are stripped of films,
metals or other contaminants, cleaned and then polished to a customer’s
specification. This allows customers to get three and four uses out of one
wafer, instead of having to buy new wafers each time.
•Different types of reclaim can be provided depending on the condition of the
wafers. The customer specifies how clean and flat the wafers need to be after
the reclaim process is finished.
•The wafers can also be sorted into specific groups for resistivity, thickness,
type and dopant or any specification that is of particular interest to you or
your project.
Test Wafer
•Test Silicon wafers are ideal for running equipment tests, research and
development, experiments and many other applications.
Furnace Grade
•Furnace grade wafers have very tightly controlled electrical characteristics.
Typically they are used for high temperature applications or thin film
depositions.
•The wafers are also doped very evenly.
Lithography Grade
•Lithography grade wafers are used for lithography or photolithography
applications that require wafers to have very tightly controlled metrology.
•Litho wafers have a very tight site flatness specification that provides little
variation in thickness from site to site making for a very flat wafer.
Mechanical Grade
Mechanical grade wafers are usually 300 mm wafers.
Although the specifications can be applied to any
diameter wafer, the term “mechanical grade” most often
refers to a 300 mm specification.
Mechanical grade wafers are also referred to as handling
wafers. Mechanical grade specifications aren’t quite as
stringent as most other wafer grades. Example of
mechanical grade specifications. :
Diameter: 300 +/- 0.5 mm
Type/Dopant: P/Boron
Orientation: {100} +/- 1º
Growth Method: Cz
Resistivity: 1-100 Ω-cm
Thickness: 750-800 μm
Front Surface: Polished
Back Surface: Polished
Notch: SEMI Standard
Particle Grade
Particle grade wafers typically refer to 300 mm wafers and have a minimal amount of
contaminants, or particles. Particles are measured at various sizes, 0.09 μm, 0.12 μm, 0.16
μm, 0.20 and 0.30 are common specifications. The number of particles at a certain size is
limited to a predetermined number, 10, 20, 50, etc. The specification is written: ≤50@≥0.12
μm. This means there are less than or equal to 50 particles greater than 0.12 μm in size on
the entire wafer. Considering one human hair is approximately 1 μm thick, these particles
are very small and cannot be seen with the naked eye. The smallest particle that can be
seen with the naked eye is 0.5 μm.
Particle Grade wafers are considered to be very clean. Depending on the user’s application,
there are a couple of specifications that can be considered particle grade. Here are a couple
of particle grade specification.
Diameter: 300 +/- 0.5 mm
Type/Dopant: P/Boron
Orientation: {100} +/- 1º
Growth Method: Cz
Resistivity: 1-30 Ω-cm
Radial Resistivity Gradient (RRG): <=10%
Oxygen Concentration: <=30 ppma
Carbon Concentration: <= 1 ppma
Surface Metals: <=1xE10
Thickness: 750-800 μm
TTV: <=2 μm
GBIR: <=5 μm
STIR: <0.25 μm
Bow/Warp: <= 40 μm
Front Surface: Polished
Particle Count: <=50@>=0.09 μm
Back Surface: Polished
Prime wafer
Prime Silicon wafers are high quality wafers. While they
have many different applications, they are most often
used as a surface to build electronic devices on, such as
microchips for a laptop computer. Prime wafers have
tightly controlled resistivity, metals, flatness and particle
counts and often times customers have very unique
specifications.
Some prime wafers have an epitaxial layer grown onto
the wafer to provide an even smoother surface for
building devices or depositing films. The “Epi” layer is
doped separately, so the layer can have its own specific
electrical characteristics.
Silicon On Insulator (SOI) Wafers
•The technology for SOI wafers has been around for more than
20 years. However it was never seen as a cost-effective method
for manufacturing semiconductors until recently.
•One challenge chip manufacturers are constantly encountering
is heat. When electronic devices built on top of wafers operate,
they give off heat; excessive heat causes the device to
malfunction.
•A number of different solutions have been developed, but, as
the space between circuits grows smaller and smaller, more
power is running through microchips then ever before. One
solution is the SOI wafer.
EXAMPLE WAFER SPECIFICATION
Growth Thickne
Dia. Type Dopant Orientation Resistivity Surface Grade
ss
Method
Cz 100 N ANTIMONY <100> 0.005-0.02 500-550 P/E PRIME
Cz 100 N PHOS <100> 1 to 20 300-350 P/E PRIME
Cz 100 N PHOS <100> 1 to 20 475-575 P/E TEST
Cz 100 N PHOS <100> 1 to 20 375-425 P/E PRIME
Cz 100 N PHOS <110> 1 to 20 500-550 P/E PRIME
Cz 100 P BORON <100> 1 to 20 475-575 P/E TEST
Cz 100 P BORON <100> 1 to 20 500-550 P/E PRIME
Cz 100 P BORON <111> 1 to 20 500-550 P/E PRIME
Cz 100 P BORON <111> 1 to 20 475-575 P/E TEST
SOME WAFERS IN STORAGE TRAYS
END OF WAFER
PREPARATION..
2.2 Epitaxial Growth
GROWTH OF EPITAXIAL SILICON
The purpose of EPI growth is to create a layer
with different, usually lower, concentration of
electrically active dopant on the substrate.
For example, an n-type layer on a p-type
wafer.
This layer is of a much better quality then the
slightly damaged or unclean layer of silicon
in the wafer
It is called the Epitaxial layer - where the
actual processing will be done.
Epitaxy(epi means "upon" and taxis means
"ordered") is a term applied to processes used to
grow a thin crystalline layer on a crystalline
substrate. The seed crystal in epitaxial processes
is the substrate.
Unlike the Czochralski process, crystalline thin
films can be grown below the melting point using
techniques such as chemical vapor deposition
(CVD), molecular beam epitaxy(MBE), etc.
Advantages of epitaxy:
(1) Doping profiles that
are not attainable
through other
conventional means
such as diffusion or ion
implantation
(2) Physical and chemical
properties of the
epitaxial layers can be
made different from
the bulk materials.
2 types of epitaxy:
1. Homoepitaxy – material is grown
epitaxially on a substrate of the
same material. E.g. grow of Si on
Si substrate
2. Heteroepitaxy – a layer grown on
a chemically different substrate.
E.g. SOI, Si growth on sapphire
Film deposited on a
<111> oriented wafer
<111> orientation
The presence of SiO2
Layer cause depositing
atoms have no
structurepolysilicon
Epitaxial and polysilicon film growth
APPLICATIONS OF EPITAXIAL LAYERS
1. Discrete and power devices
2. Integrated circuits and MOS devices
Transistors Integrated circuits
1. DISCRETE AND POWER DEVICES
Technology change: junction transistors diffused planar
structure
Requires a material structure that are not achieved by diffusion of
dopants from the surface
Si epitaxy was developed to enhance the electrical
performance of discrete bipolar transistors
Structure needed: thin, lightly doped and single crystal layer of
high perfection upon more heavily doped Si substrate
Discrete transistor fabricated in an
epitaxial layer on a heavily doped N+
substrate
2. INTEGRATED CIRCUIT (IC) & MOS DEVICES
Development of planar bipolar IC caused the
requirement for devices built on the same substrate to
be electrically isolated
The use of opposite typed substrate and
epitaxial layer met part of the requirement
Device isolation was completed by the
diffusion of “isolation” region through the
epitaxial layer to contact the substrate
between active areas
(a) A junction isolated
bipolar device fabricated as
part of an integrated circuit
using a buried layer
subcollector and a lightly
doped n-epitaxial layer
(b) An N-Well CMOS
structure fabricated in a
lightly doped p-epitaxial
layer
Unipolar devices such as junction field-effect
transistors (JFETs), VMOS, DRAMs technology also use
epitaxial structures
VLSI CMOS (complimentary metal-oxide-
semiconductor) devices have been built in thin (3-8
micron) lightly doped epitaxial layers on heavily doped
substrates of the same type (N or P)
TECHNIQUES FOR SILICON EPITAXY
1. Vapor Phase- Chemical Vapour Deposition
(CVD)
2. Molecular Beam Epitaxy (MBE)
3. Liquid Phase Epitaxy (LPE)
VAPOR PHASE- CHEMICAL VAPOUR DEPOSITION (CVD)
The most common technique in Si epitaxy
Crystallization from vapor phase
In the CVD technique ;
Epitaxial layers are generally grown on Si
substrates by the controlled deposition of Si
atoms onto the surface from a chemical vapor
containing Si
e.g. SiCl4 + 2H2 Si + 4HCl (for deposition as
well as for etching)
Schematic drawing of a simple horizontal
flow, cold wall, CVD reactor
Schematic CVD reactor
geometries for
(a) True vertical reactor
(b) Classic horizontal flow
reactor
(c) Modified vertical (or
pancake) reactor
(d) Downflow cylinder reactor
CVD
CVD REACTIONS
1. Pyrolysis: chemical reaction is driven by heat alone, e.g.
silane decomposes with heating
SiH4 Si + 2H2
2. Reduction: chemical reaction by reacting a molecule
with hydrogen, e.g. silicon tetrachloride- reduction in
hydrogen ambient to form solid silicon
SiCl4 + 2H2 Si + 4HCl
3. Oxidation: chemical reaction of an atom or molecule
with oxygen, e.g. SiH4 decomposes at lower temperature
SiH4 + O2 SiO2 + 2H2
4. Nitridation: chemical process of forming silicon nitride
by exposing Si wafer to nitrogen at high temperature
e.g. SiH2Cl2 readily decomposes at 1050C
3SiH2Cl2 + 4NH3 Si3N4 + pH + 6H2
2. MOLECULAR BEAM EPITAXY (MBE)
Substrate is held in high vacuum in the range 10-10
torr
Components along with dopants, are heated in
separate cylindrical cells.
Collimated beams of these escape into the vacuum
and are directed into the surface of a substrate
Sample held at relatively low temperature (600oC for
GaAs)
Conventional temperature range is 400oC to 800oC
Growth rates are in the range of 0.01 to 0.3 μm/min
In MBE,
Si and dopant(s) are evaporated in an ultra high
vacuum (UHV) chamber
The evaporated atoms are transported at relatively
high velocity in a straight line from the source to the
substrate
They condense on the low temperature substrate
The condensed atoms of Si or dopant will diffuse on
the surface until they reach a low energy site that
they fit well the atomic structure of the surface
Then it bonds in that low energy site, extending the
underlying crystal by a vapour to solid phase crystal
growth
Wider range of dopants for MBE than CVD epitaxy:
Typical dopants: Antimony, Sb (N-type),
aluminum, Al or gallium (Ga) for P-type
N-type dopant: As and P, evaporate rapidly
even at 200C. Difficult to control
P-type dopant: Boron, evaporate slowly even
at 1300C
Precise control of doping
No chemical reactions along with high thermal
velocities results in properties rapidly changing
with source
molecular beam epitaxial system
Schematic drawing of a multiple chamber MBE system
MBE Equipment
3. LIQUID PHASE EPITAXY (LPE)
In films growth by LPE from solution melts, low cooling
rates, when the surface reaction (growth)
Increase cooling rates, mass transport rate will
increase and the growth rate will increase with cooling
rate until growth rate becomes limited by surface
reaction kinetics
Growing crystals from a liquid solution below their
melting point.
E.x: Melting point of GaAs is 1238oC whereas a
mixture of GaAs with Ga metal has considerably
lower melting point
Single crystal GaAs layer can be grown from
Ga+GaAs melt.
Low temperature eliminates many problems of
impurity introduction.
Schematic drawing of a typical silicon liquid phase epitaxy (LPE)
•Fabrication sequence for a
vertical channel field effect
transistor
•N and N+ epitaxial structure can
be built using liquid or vapour
phase epitaxial growth
•Preferential etching can be used
to open areas part way through
the N type epitaxial layer
• In this figure, LPE is used to fill
the etched out gate areas which
control current flow vertically from
the top side source to the N+ Schematic of fabrication steps in the
fabrication vertical field effect transistors by
substrate drain region etch and LPE refill techniques
DEFECTS
(1)Line (or edge) dislocation initially present in the substrate and
extending into the epitaxiallayer
(2)Epitaxial stacking fault by an impurity precipitate on the
substrate surface
(3)Impurity precipitate caused by epitaxial process contamination
(4)Growth hillock
(5)Bulk stacking faults, one of which intersects the substrate
surface, thereby being extended into the layer
Generally, defects can be reduced by a higher
growth temperature, reduced gas pressure,
lower growth rate, and cleaner substrate
surface.
HETEROEPITAXY
Silicon on insulators (SOI)
Fabrication of devices in small islands of
silicon on an insulating substrate eg.
Silicon on Sapphire (Al2O3)
Substrates have the appropriate thermal
expansion match to silicon.
Epitaxial films grown by CVD (eg. Pyrolysis
of silane)
END OF CHAPTER 2
