What method can be used to change the signal radix in a ModelSim Wave Window, and why is this feature significant?

In ModelSim, the signal radix in a Wave Window can be changed using the Global Signal Radix feature. This is done through the Wave Window interface, allowing the radix to be set for all signals displayed. This feature is significant because it enables the user to view signal values in different formats (e.g., binary, hexadecimal, decimal), which is crucial for accurately interpreting and debugging the design data based on specific signal representation needs .

How can changes to the Global Signal Radix affect the interpretation of simulation results in ModelSim?

Changing the Global Signal Radix in ModelSim affects how signal values are represented in the Wave Window, potentially altering their interpretation in the context of simulation analysis. For example, a binary radix might highlight bitwise behavior, crucial for low-level debugging, whereas a decimal or hexadecimal radix could simplify the reading of larger numerical values. The ability to adjust radix ensures that users can analyze simulation outputs in formats best suited to their specific examination needs, albeit requiring corresponding adjustments in analysis strategies .

Explain how the vsim command integrates into the typical simulation workflow using ModelSim.

The vsim command is an integral step in ModelSim’s simulation workflow that follows design compilation. It is used to load the top-level modules of a design into the simulator, thereby initiating the simulation process. After the vsim command loads these modules, it iteratively brings the instantiated modules and user-defined primitives (UDPs) into the simulation environment, resolving hierarchical references and port connections. This command effectively links the design elements, preparing it for simulation execution and analysis .

How do ModelSim's working libraries differ from resource libraries, and how does this distinction affect the simulation process?

Working libraries in ModelSim are temporary storage locations where the compiled version of a design is kept. They are updated as designs are modified and recompiled, serving a dynamic role in the design process. In contrast, resource libraries are static and typically contain pre-prepared parts or shared resources used across multiple projects or by various teams. This distinction affects simulation processes as only the working library is recompiled during updates, optimizing the simulation load times and workflow efficiency by avoiding unnecessary recompilation of unchanged modules .

Discuss the advantages and potential challenges of using VCD files as a stimulus in ModelSim simulations.

Using VCD files as a stimulus in ModelSim offers the advantage of leveraging well-established circuit test vectors within simulation processes, providing a consistent and repeatable input set. However, challenges include the potential complexity of managing large VCD files and their dependence on existing waveform data, which might limit flexibility compared to dynamically generated stimuli. Additionally, aligning VCD files with the expected simulation environment can require thorough verification to avoid mismatches with library or design updates .

In what ways does encryption with ModelSim protect source code, and what are the potential implications for design sharing?

ModelSim uses encryption techniques like AES128-CBC and RSA to protect source code through its `protect pragmas in VHDL and Verilog. This encryption helps in protecting intellectual property by ensuring that only authorized users with the proper decryption keys can access and simulate the encrypted code. The implications for design sharing include enhanced security and control over distribution, allowing authors to confidently share their designs with clients or partners without risking exposure of sensitive IP details .

What role do GUI elements like the Source Window and Structure Window play in enhancing user experience in ModelSim, especially in managing complex simulations?

GUI elements like the Source Window and Structure Window in ModelSim provide powerful interfaces for managing complex simulations. The Source Window allows users to customize views, aiding in quick identification and debugging of source code issues through adjustable settings like syntax highlighting. The Structure Window offers a hierarchical visualization of the simulation, enhancing navigation and understanding of the simulation's architecture. Together, these tools improve accessibility and control over simulation processes, reducing cognitive load and increasing efficiency in handling complex designs .

Evaluate how the integration of third-party test bench generation tools can enhance the ModelSim simulation workflow.

Integrating third-party test bench generation tools into the ModelSim simulation workflow can significantly enhance productivity and simulation accuracy. These tools automate stimulus creation, reducing the time and potential errors involved in manual test bench development. Moreover, they often include advanced capabilities such as coverage analysis and corner case evaluation, which contribute to a more thorough design verification. However, relying on third-party tools may introduce dependency concerns and require compatibility checks with ModelSim's library and file management systems .

Why is it important to map logical library names to their directory pathnames in ModelSim, and how can this be accomplished?

Mapping logical library names to their directory pathnames in ModelSim is crucial to ensure that the simulator can locate and load necessary libraries during simulation or compilation. Without proper mapping, the simulation process may fail because required components cannot be found. This mapping can be done using the vmap command, which sets the relationship between a logical library name and the physical directory pathname where the library is located. This process can be executed via the GUI or command line .

How does the use of encryption envelopes with pragma protect expressions influence the compilation process in ModelSim?

Encryption envelopes with pragma protect expressions encapsulate sections of the source code, protecting them during the compilation process in ModelSim. When the +protect argument is used with vcom or vlog, the compiler transforms these expressions into encrypted forms while maintaining the necessary decryption mechanisms. This adds a layer of security, ensuring that only authorized tools or users can access protected portions of the files. Such an approach demands careful management of encryption keys and validation of the protected IP with intended tools .

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ModelSim Users Manual v10.1c PDF

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ModelSim® User’s Manual

Software Version 10.1c

© 1991-2012 Mentor Graphics Corporation

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Table of Contents

Chapter 1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operational Structure and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Simulation Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Basic Steps for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Step 1 — Collect Files and Map Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Step 2 — Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Step 3 — Load the Design for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Step 4 — Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Step 5 — Debug the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Command Line Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Batch Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Definition of an Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Standards Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Installation Directory Pathnames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Deprecated Features, Commands, and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 2
Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Design Object Icons and Their Meanings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Setting Fonts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Using the Find and Filter Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Using the Find Options Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
User-Defined Radices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Using the radix define Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Saving and Reloading Formats and Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Active Time Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Window Specific Keyboard Shortcuts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Working with Bookmarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Managing Your Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Elements of the Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Selecting the Active Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Rearranging the Main Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Navigating in the Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Main Window Menu Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Main Window Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Call Stack Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

ModelSim User’s Manual, v10.1c 3

Table of Contents

Call Stack Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Related Commands of the Call Stack Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
GUI Elements of the Call Stack Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Class Graph Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Class Graph Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
GUI Elements of the Class Graph Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Class Instances Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
GUI Elements of the Class Instances Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Class Tree Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
GUI Elements of the Class Tree Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Dataflow Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
GUI Elements of the Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
FSM List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
GUI Elements of the FSM List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
FSM Viewer Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
FSM Viewer Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
GUI Elements of the FSM Viewer Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Library Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
GUI Elements of the Library Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
List Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
GUI Elements of the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Locals Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Locals Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
GUI Elements of the Locals Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Memory List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Memory List Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
GUI Elements of the Memory List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Memory Data Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Memory Data Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
GUI Elements of the Memory Data Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Message Viewer Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Message Viewer Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
GUI Elements of the Message Viewer Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Objects Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Objects Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Processes Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Processes Window Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
GUI Elements of the Processes Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Opening Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Displaying Multiple Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Dragging and Dropping Objects into the Wave and List Windows . . . . . . . . . . . . . . . . . . 175
Setting your Context by Navigating Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Language Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Setting File-Line Breakpoints with the GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Adding File-Line Breakpoints with the bp Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

4 ModelSim User’s Manual, v10.1c

Table of Contents

Editing File-Line Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Setting Conditional Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Checking Object Values and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Marking Lines with Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Performing Incremental Search for Specific Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Customizing the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Viewing the Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Structure Window Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
GUI Elements of the Structure Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Transcript Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Displaying the Transcript Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Viewing Data in the Transcript Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Saving the Transcript File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Colorizing the Transcript . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Disabling Creation of the Transcript File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Performing an Incremental Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Using Automatic Command Help. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Using drivers And readers Command Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Using Transcript Menu Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Adding Objects to the Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Expanding Objects to Show Individual Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Grouping and Ungrouping Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Saving and Reloading Format Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Add Objects to the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Objects You Can View in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Wave Window Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Chapter 3
Protecting Your Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Creating Encryption Envelopes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Configuring the Encryption Envelope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Protection Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Using the `include Compiler Directive (Verilog only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Compiling with +protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
The Runtime Encryption Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Language-Specific Usage Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Usage Models for Protecting Verilog Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Usage Models for Protecting VHDL Source Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Proprietary Source Code Encryption Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Using Proprietary Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Protecting Source Code Using -nodebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Encryption Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Encryption and Encoding Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
How Encryption Envelopes Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

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Using Public Encryption Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Using the Mentor Graphics Public Encryption Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Chapter 4
Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
What are Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
What are the Benefits of Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Project Conversion Between Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Getting Started with Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Step 1 — Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Step 2 — Adding Items to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Step 3 — Compiling the Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Step 4 — Simulating a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Other Basic Project Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
The Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Sorting the List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Creating a Simulation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Organizing Projects with Folders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Adding a Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Specifying File Properties and Project Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
File Compilation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Accessing Projects from the Command Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Chapter 5
Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Design Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Design Unit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Working Library Versus Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Archives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Working with Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Creating a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Managing Library Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Assigning a Logical Name to a Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Moving a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Setting Up Libraries for Group Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Specifying Resource Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Verilog Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
VHDL Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Predefined Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Alternate IEEE Libraries Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Regenerating Your Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Importing FPGA Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Protecting Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Chapter 6
VHDL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Basic VHDL Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

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Compilation and Simulation of VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Creating a Design Library for VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Compiling a VHDL Design—the vcom Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Simulating a VHDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Naming Behavior of VHDL For Generate Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Differences Between Versions of VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Simulator Resolution Limit for VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Default Binding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Delta Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Using the TextIO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Syntax for File Declaration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Using STD_INPUT and STD_OUTPUT Within ModelSim . . . . . . . . . . . . . . . . . . . . . . . 290
TextIO Implementation Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Writing Strings and Aggregates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Reading and Writing Hexadecimal Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Dangling Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
The ENDLINE Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
The ENDFILE Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Using Alternative Input/Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Flushing the TEXTIO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Providing Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
VITAL Usage and Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
VITAL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
VITAL 1995 and 2000 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
VITAL Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Compiling and Simulating with Accelerated VITAL Packages . . . . . . . . . . . . . . . . . . . . . 294
VHDL Utilities Package (util) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
get_resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
init_signal_driver() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
init_signal_spy() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
signal_force() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
signal_release() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
to_real(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
to_time() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Modeling Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Examples of Different Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Affecting Performance by Cancelling Scheduled Events. . . . . . . . . . . . . . . . . . . . . . . . . . 308

Chapter 7
Verilog and SystemVerilog Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Standards, Nomenclature, and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Basic Verilog Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Verilog Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Creating a Working Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Invoking the Verilog Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Initializing enum Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Library Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

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SystemVerilog Multi-File Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Verilog-XL Compatible Compiler Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Verilog-XL uselib Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Verilog Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Verilog Generate Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Verilog Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Simulator Resolution Limit (Verilog). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Event Ordering in Verilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Debugging Event Order Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Debugging Signal Segmentation Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Negative Timing Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Force and Release Statements in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Verilog-XL Compatible Simulator Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Using Escaped Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
SDF Timing Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Delay Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
IEEE Std 1364 System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Verilog-XL Compatible System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
IEEE Std 1364 Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Verilog-XL Compatible Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Verilog PLI/VPI and SystemVerilog DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Standards, Nomenclature, and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Extensions to SystemVerilog DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
SystemVerilog Class Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Class Debug Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Viewing Class Objects in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Conditional Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Stepping Through Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
The Run Until Here Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Command Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Chapter 8
Recording Simulation Results With Datasets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Saving a Simulation to a WLF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
WLF File Parameter Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Limiting the WLF File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Multithreading on Linux Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Opening Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Viewing Dataset Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Structure Tab Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Managing Multiple Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Managing Multiple Datasets in the GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Restricting the Dataset Prefix Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Saving at Intervals with Dataset Snapshot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

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Collapsing Time and Delta Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Virtual Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Virtual Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Virtual Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Virtual Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Virtual Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

Chapter 9
Waveform Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Objects You Can View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Wave Window Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Adding Objects to the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Adding Objects with Mouse Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Adding Objects with Menu Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Adding Objects with a Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Adding Objects with a Window Format File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Inserting Signals in a Specific Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Working with Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Adding Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Jumping to a Signal Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Measuring Time with Cursors in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Syncing All Active Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Linking Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Understanding Cursor Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Shortcuts for Working with Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Expanded Time in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Expanded Time Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Recording Expanded Time Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Viewing Expanded Time Information in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . 398
Selecting the Expanded Time Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Switching Between Time Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Expanding and Collapsing Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Zooming the Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Zooming with the Menu, Toolbar and Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Saving Zoom Range and Scroll Position with Bookmarks. . . . . . . . . . . . . . . . . . . . . . . . . 405
Searching in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Searching for Values or Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Using the Expression Builder for Expression Searches . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Filtering the Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Formatting the Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Setting Wave Window Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Formatting Objects in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Dividing the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Splitting Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Wave Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Creating a Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Deleting or Ungrouping a Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

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Adding Items to an Existing Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Removing Items from an Existing Wave Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Miscellaneous Wave Group Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Composite Signals or Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Saving the Window Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Exporting Waveforms from the Wave window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Exporting the Wave Window as a Bitmap Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Printing the Wave Window to a Postscript File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Printing the Wave Window on the Windows Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Saving Waveforms Between Two Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Combining Objects into Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Extracting a Bus Slice. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Splitting a Bus into Several Smaller Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Using the Virtual Signal Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Creating a Virtual Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Miscellaneous Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Examining Waveform Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Displaying Drivers of the Selected Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Sorting a Group of Objects in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Creating and Managing Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Signal Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
File-Line Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Saving and Restoring Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

Chapter 10
Debugging with the Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Dataflow Window Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Dataflow Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Post-Simulation Debug Flow Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Common Tasks for Dataflow Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Adding Objects to the Dataflow Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Exploring the Connectivity of the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Exploring Designs with the Embedded Wave Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Tracing Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Tracing the Source of an Unknown State (StX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Finding Objects by Name in the Dataflow Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Automatically Tracing All Paths Between Two Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Dataflow Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Symbol Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Current vs. Post-Simulation Command Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Dataflow Window Graphic Interface Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
What Can I View in the Dataflow Window? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
How is the Dataflow Window Linked to Other Windows? . . . . . . . . . . . . . . . . . . . . . . . . 458
How Can I Print and Save the Display? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
How Do I Configure Window Options? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

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Chapter 11
Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Creating and Editing Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Creating New Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Opening Existing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Editing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Language Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Searching for Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Navigating Through Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Data and Objects in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Determining Object Values and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Debugging and Textual Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Hyperlinked Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Highlighted Text in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Dragging Source Window Objects Into Other Windows . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Setting Individual Breakpoints in a Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Setting Breakpoints with the bp Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Editing Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Saving and Restoring Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Setting Conditional Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Run Until Here . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Source Window Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Setting and Removing Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Setting Source Window Preferences.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Chapter 12
Signal Spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Signal Spy Formatting Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
Signal Spy Supported Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
disable_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
enable_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
init_signal_driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
init_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
signal_force. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
signal_release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Chapter 13
Generating Stimulus with Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Getting Started with the Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Using Waveform Editor Prior to Loading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Using Waveform Editor After Loading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Creating Waveforms from Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Creating Waveforms with Wave Create Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Editing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Selecting Parts of the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Stretching and Moving Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Simulating Directly from Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

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Exporting Waveforms to a Stimulus File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Driving Simulation with the Saved Stimulus File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Signal Mapping and Importing EVCD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Saving the Waveform Editor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Chapter 14
Standard Delay Format (SDF) Timing Annotation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Specifying SDF Files for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Instance Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
SDF Specification with the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Errors and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
VHDL VITAL SDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
SDF to VHDL Generic Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Resolving Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Verilog SDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
$sdf_annotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
SDF to Verilog Construct Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Retain Delay Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Optional Edge Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Optional Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Rounded Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
SDF for Mixed VHDL and Verilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Interconnect Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Disabling Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Specifying the Wrong Instance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Matching a Single Timing Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Mistaking a Component or Module Name for an Instance Label. . . . . . . . . . . . . . . . . . . . 529
Forgetting to Specify the Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Chapter 15
Value Change Dump (VCD) Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Creating a VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Four-State VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Extended VCD File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
VCD Case Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Using Extended VCD as Stimulus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Simulating with Input Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Replacing Instances with Output Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . . 534
VCD Commands and VCD Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Using VCD Commands with SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Compressing Files with VCD Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
VCD File from Source to Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
VHDL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
VCD Simulator Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
VCD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
VCD to WLF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Capturing Port Driver Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

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Table of Contents

Driver States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Identifier Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Resolving Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Chapter 16
Tcl and Macros (DO Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Tcl Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Tcl References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Tcl Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
If Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Command Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Command Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Multiple-Line Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Evaluation Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Tcl Relational Expression Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Variable Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
System Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Simulator State Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Referencing Simulator State Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
Special Considerations for the now Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
List Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Simulator Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Simulator Tcl Time Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Tcl Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Macros (DO Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Creating DO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Using Parameters with DO Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Deleting a File from a .do Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Making Macro Parameters Optional. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Error Action in DO Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

Appendix A
[Link] Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Organization of the [Link] File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Making Changes to the [Link] File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Changing the [Link] Read-Only Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
The Runtime Options Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Editing [Link] Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Overriding the Default Initialization File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
AddPragmaPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
AmsStandard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
AssertFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

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BindAtCompile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
BreakOnAssertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
CheckPlusargs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
CheckpointCompressMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
CheckSynthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
ClassDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
CommandHistory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
CompilerTempDir. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
ConcurrentFileLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
CreateDirForFileAccess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
DatasetSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
DefaultForceKind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
DefaultRadix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
DefaultRadixFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
DefaultRestartOptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
DelayFileOpen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
displaymsgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
DpiOutOfTheBlue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
DumpportsCollapse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
EnumBaseInit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
ErrorFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Explicit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
fatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
floatfixlib. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
ForceSigNextIter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
ForceUnsignedIntegerToVHDLInteger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
FsmImplicitTrans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
FsmResetTrans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
FsmSingle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
FsmXAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
GenerateFormat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
GenerateLoopIterationMax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
GenerateRecursionDepthMax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
GenerousIdentifierParsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
GlobalSharedObjectsList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Hazard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
ieee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
IgnoreError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
IgnoreFailure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
IgnoreNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
IgnorePragmaPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
ignoreStandardRealVector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
IgnoreVitalErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
IgnoreWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
ImmediateContinuousAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
IncludeRecursionDepthMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
InitOutCompositeParam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
IterationLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

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LargeObjectSilent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
LargeObjectSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
LibrarySearchPath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
MaxReportRhsCrossProducts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
MessageFormat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
MessageFormatBreak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
MessageFormatBreakLine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
MessageFormatError. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
MessageFormatFail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
MessageFormatFatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
MessageFormatNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
MessageFormatWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
MixedAnsiPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
modelsim_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
msgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
mtiAvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
mtiOvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
MultiFileCompilationUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
NoCaseStaticError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
NoDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
NoDeferSubpgmCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
NoIndexCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
NoOthersStaticError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
NoRangeCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
NoVital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
NoVitalCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
NumericStdNoWarnings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
OldVHDLConfigurationVisibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
OldVhdlForGenNames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
OnFinish . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Optimize_1164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
PathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
PedanticErrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
PliCompatDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
PreserveCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
PrintSimStats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
RequireConfigForAllDefaultBinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
RunLength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
SeparateConfigLibrary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Show_BadOptionWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Show_Lint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Show_source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Show_VitalChecksWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Show_Warning1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Show_Warning2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

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Show_Warning3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Show_Warning4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Show_Warning5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
ShowFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
ShutdownFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
SignalSpyPathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
std_developerskit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
StdArithNoWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
suppress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
SuppressFileTypeReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
sv_std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
SVExtensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
SVFileExtensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Svlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
synopsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
SyncCompilerFiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
TranscriptFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
UnbufferedOutput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
UserTimeUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
UVMControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Veriuser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
VHDL93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
VhdlVariableLogging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
vital2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
vlog95compat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
WarnConstantChange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
WaveSignalNameWidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
WLFCacheSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
WLFCollapseMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
WLFCompress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
WLFDeleteOnQuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
WLFFileLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
WLFFilename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
WLFOptimize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
WLFSaveAllRegions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
WLFSimCacheSize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
WLFSizeLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
WLFTimeLimit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
WLFUpdateInterval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
WLFUseThreads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Commonly Used [Link] Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Common Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Hierarchical Library Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Creating a Transcript File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Using a Startup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

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Turning Off Assertion Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

Turning Off Warnings from Arithmetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Force Command Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Restart Command Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
VHDL Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Opening VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

Appendix B
Location Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Referencing Source Files with Location Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Using Location Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Pathname Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
How Location Mapping Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Mapping with TCL Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

Appendix C
Error and Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Message System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Getting More Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Changing Message Severity Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Suppressing Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Suppressing VCOM Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Suppressing VLOG Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Suppressing VSIM Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Exit Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Miscellaneous Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Enforcing Strict 1076 Compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

Appendix D
Verilog Interfaces to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Implementation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
GCC Compiler Support for use with C Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Registering PLI Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Registering VPI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Registering DPI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
DPI Use Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
DPI and the vlog Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
When Your DPI Export Function is Not Getting Called . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Troubleshooting a Missing DPI Import Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Simplified Import of Library Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Optimizing DPI Import Call Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Making Verilog Function Calls from non-DPI C Models . . . . . . . . . . . . . . . . . . . . . . . . . 655
Calling C/C++ Functions Defined in PLI Shared Objects from DPI Code . . . . . . . . . . . . 656
Compiling and Linking C Applications for Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Windows Platforms — C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Compiling and Linking C++ Applications for Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Windows Platforms — C++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

ModelSim User’s Manual, v10.1c 17

Table of Contents

Specifying Application Files to Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

PLI and VPI File Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
DPI File Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Loading Shared Objects with Global Symbol Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . 661
PLI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
VPI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
DPI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
The PLI Callback reason Argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
The sizetf Callback Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
PLI Object Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Third Party PLI Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Support for VHDL Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
IEEE Std 1364 ACC Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
IEEE Std 1364 TF Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
SystemVerilog DPI Access Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Verilog-XL Compatible Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
64-bit Support for PLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Using 64-bit ModelSim with 32-bit Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
PLI/VPI Tracing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
The Purpose of Tracing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Invoking a Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Debugging Interface Application Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

Appendix E
Command and Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Command Shortcuts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Command History Shortcuts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Main and Source Window Mouse and Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . 676
List of Keyboard Shortcuts in GUI Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
List Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Wave Window Mouse and Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

Appendix F
Setting GUI Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Customizing the Simulator GUI Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Layout Mode Loading Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Configure Window Layouts Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Creating a Custom Layout Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Changing Layout Mode Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Resetting a Layout Mode to its Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Deleting a Custom Layout Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Configuring Default Windows for Restored Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Simulator GUI Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Setting Preference Variables from the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Saving GUI Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
The [Link] File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
GUI Preference Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Wave Window Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

18 ModelSim User’s Manual, v10.1c

Table of Contents

Appendix G
System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Files Accessed During Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Environment Variable Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Creating Environment Variables in Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
Referencing Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Removing Temp Files (VSOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Index
Third-Party Information
End-User License Agreement

ModelSim User’s Manual, v10.1c 19

List of Examples

Example 2-1. Using the radix define Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Example 2-2. Using radix define to Specify Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Example 3-1. Encryption Envelope Contains Verilog IP Code to be Protected . . . . . . . . . . 217
Example 3-2. Encryption Envelope Contains `include Compiler Directives . . . . . . . . . . . . 218
Example 3-3. Results After Compiling with vlog +protect . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Example 3-4. Using the Mentor Graphics Public Encryption Key in Verilog/SystemVerilog 244
Example 6-1. Memory Model Using VHDL87 and VHDL93 Architectures . . . . . . . . . . . . 300
Example 6-2. Conversions Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Example 6-3. Memory Model Using VHDL02 Architecture . . . . . . . . . . . . . . . . . . . . . . . . 304
Example 7-1. Invocation of the Verilog Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Example 7-2. Incremental Compilation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Example 7-3. Sub-Modules with Common Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Example 15-1. Verilog Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Example 15-2. VHDL Adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Example 15-3. Mixed-HDL Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Example 15-4. Replacing Instances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Example 15-5. VCD Output from vcd dumpports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Example 16-1. Tcl while Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Example 16-2. Tcl for Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Example 16-3. Tcl foreach Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Example 16-4. Tcl break Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Example 16-5. Tcl continue Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Example 16-6. Access and Transfer System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Example 16-7. Tcl Used to Specify Compiler Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Example 16-8. Tcl Used to Specify Compiler Arguments—Enhanced . . . . . . . . . . . . . . . . 561
Example 16-9. Specifying Files to Compile With argc Macro . . . . . . . . . . . . . . . . . . . . . . . 563
Example 16-10. Specifying Compiler Arguments With Macro . . . . . . . . . . . . . . . . . . . . . . 563
Example 16-11. Specifying Compiler Arguments With Macro—Enhanced. . . . . . . . . . . . . 563
Example D-1. VPI Application Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

20 ModelSim User’s Manual, v10.1c

List of Figures

Figure 1-1. Operational Structure and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 2-1. Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 2-2. Find Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 2-3. Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 2-4. Find Options Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 2-5. User-Defined Radix “States” in the Wave Window . . . . . . . . . . . . . . . . . . . . . . 54
Figure 2-6. User-Defined Radix “States” in the List Window . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 2-7. Setting the Global Signal Radix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 2-8. Fixed Point Radix Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 2-9. Active Cursor Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 2-10. Enter Active Time Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 2-11. Schematic Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 2-12. Manage Bookmarks Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 2-13. Bookmark Options Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 2-14. Main Window of the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 2-15. Main Window — Menu Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 2-16. Main Window — Toolbar Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 2-17. Main Window — Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-18. GUI Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 2-19. GUI Tab Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 2-20. Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 2-21. Main Window Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 2-22. Window Header Handle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 2-23. Tab Handle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 2-24. Window Undock Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 2-25. Bookmarks Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 2-26. Compile Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 2-27. Coverage Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 2-28. Dataflow Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 2-29. FSM Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 2-30. Help Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 2-31. Layout Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2-32. Memory Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2-33. Mode Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2-34. Objectfilter Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 2-35. Process Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 2-36. Profile Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 2-37. Schematic Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 2-38. Simulate Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 2-39. Source Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

ModelSim User’s Manual, v10.1c 21

List of Figures

Figure 2-40. Standard Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 2-41. The Add Selected to Window Dropdown Menu. . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 2-42. Step Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 2-43. Wave Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 2-44. Wave Compare Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 2-45. Wave Cursor Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 2-46. Wave Edit Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 2-47. Wave Expand Time Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 2-48. Zoom Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 2-49. Call Stack Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 2-50. Class Graph Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 2-51. Class Instances Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 2-52. Class Tree Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 2-53. Dataflow Window - ModelSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 2-54. Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 2-55. Dataflow Window and Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 2-56. Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 2-57. FSM List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 2-58. FSM Viewer Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 2-59. Combining Common Transition Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 2-60. Library Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 2-61. Tabular Format of the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 2-62. List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 2-63. Time Markers in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 2-64. List Window After configure list -delta none Option is Used . . . . . . . . . . . . . 131
Figure 2-65. List Window After configure list -delta collapse Option is Used. . . . . . . . . . . 132
Figure 2-66. List Window After write list -delta all Option is Used . . . . . . . . . . . . . . . . . . . 132
Figure 2-67. List Window After write list -event Option is Used . . . . . . . . . . . . . . . . . . . . . 133
Figure 2-68. Wave Signal Search Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 2-69. Expression Builder Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 2-70. Selecting Signals for Expression Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 2-71. Modifying List Window Display Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 2-72. List Signal Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 2-73. Changing the Radix in the List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 2-74. Line Triggering in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 2-75. Setting Trigger Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 2-76. Trigger Gating Using Expression Builder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 2-77. Locals Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 2-78. Change Selected Variable Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 2-79. Memory LIst Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 2-80. Memory Data Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 2-81. Split Screen View of Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 2-82. Message Viewer Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 2-83. Message Viewer Window — Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 2-84. Message Viewer Filter Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

22 ModelSim User’s Manual, v10.1c

List of Figures

Figure 2-85. Objects Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 2-86. Setting the Global Signal Radix from the Objects Window . . . . . . . . . . . . . . . 166
Figure 2-87. Processes Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 2-88. Column Heading Changes When States are Filtered . . . . . . . . . . . . . . . . . . . . 169
Figure 2-89. Next Active Process Displayed in Order Column. . . . . . . . . . . . . . . . . . . . . . . 170
Figure 2-90. Sample Process Report in the Transcript Window . . . . . . . . . . . . . . . . . . . . . . 171
Figure 2-91. Source Window Showing Language Templates . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 2-92. Displaying Multiple Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 2-93. Setting Context from Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 2-94. Language Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 2-95. Create New Design Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 2-96. Language Template Context Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 2-97. Breakpoint in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 2-98. Modifying Existing Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 2-99. Source Code for [Link]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 2-100. Source Window Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 2-101. Source Window with Find Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 2-102. Preferences Dialog for Customizing Source Window . . . . . . . . . . . . . . . . . . 189
Figure 2-103. Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 2-104. Find Mode Popup Displays Matches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 2-105. Changing the colorizeTranscript Preference Value . . . . . . . . . . . . . . . . . . . . 196
Figure 2-106. Transcript Window with Find Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 2-107. drivers Command Results in Transcript . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 2-108. Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 2-109. Scrollable Hierarchical Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 2-110. Expanded Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 2-111. Grouping Objects in the Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 2-112. Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 2-113. Pathnames Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 2-114. Setting the Global Signal Radix from the Wave Window . . . . . . . . . . . . . . . 206
Figure 2-115. Values Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 2-116. Waveform Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 2-117. Analog Sidebar Toolbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 2-118. Cursor Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 2-119. Toolbox for Cursors and Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 2-120. Editing Grid and Timeline Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 2-121. Cursor Properties Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 2-122. Wave Window - Message Bar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 2-123. View Objects Window Dropdown Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 3-1. Create an Encryption Envelope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 3-2. Verilog/SystemVerilog Encryption Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 3-3. Delivering IP Code with User-Defined Macros . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 3-4. Delivering IP with `protect Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 4-1. Create Project Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 4-2. Project Window Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

ModelSim User’s Manual, v10.1c 23

List of Figures

Figure 4-3. Add items to the Project Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 4-4. Create Project File Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 4-5. Add file to Project Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 4-6. Right-click Compile Menu in Project Window . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 4-7. Click Plus Sign to Show Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 4-8. Setting Compile Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 4-9. Grouping Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 4-10. Start Simulation Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 4-11. Structure WIndow with Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 4-12. Project Window Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 4-13. Add Simulation Configuration Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 4-14. Simulation Configuration in the Project Window. . . . . . . . . . . . . . . . . . . . . . . 259
Figure 4-15. Add Folder Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 4-16. Specifying a Project Folder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 4-17. Project Compiler Settings Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 4-18. Specifying File Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 4-19. Project Settings Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 5-1. Creating a New Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 5-2. Design Unit Information in the Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 5-3. Edit Library Mapping Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 5-4. Import Library Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 6-1. VHDL Delta Delay Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 7-1. Fatal Signal Segmentation Violation (SIGSEGV) . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 7-2. Current Process Where Error Occurred . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Figure 7-3. Blue Arrow Indicating Where Code Stopped Executing . . . . . . . . . . . . . . . . . . 334
Figure 7-4. Null Values in the Locals Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Figure 7-5. The Class Instances Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 7-6. Placing Class Objects in the Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 7-7. Class Information Popup in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 7-8. Classes in the Class Tree Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 7-9. Class Viewing in the Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Figure 8-1. Displaying Two Datasets in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 8-2. Open Dataset Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 8-3. Structure Tabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Figure 8-4. The Dataset Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Figure 8-5. Dataset Snapshot Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 8-6. Virtual Objects Indicated by Orange Diamond. . . . . . . . . . . . . . . . . . . . . . . . . . 381
Figure 9-1. The Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Figure 9-2. Wave Window Object Pathnames Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Figure 9-3. Wave Window Object Values Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Figure 9-4. Wave Window Waveform Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Figure 9-5. Wave Window Cursor Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Figure 9-6. Wave Window Messages Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Figure 9-7. Insertion Point Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Figure 9-8. Grid and Timeline Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

24 ModelSim User’s Manual, v10.1c

List of Figures

Figure 9-9. Cursor Properties Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Figure 9-10. Find Previous and Next Transition Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Figure 9-11. Original Names of Wave Window Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Figure 9-12. Sync All Active Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Figure 9-13. Cursor Linking Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Figure 9-14. Configure Cursor Links Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Figure 9-15. Waveform Pane with Collapsed Event and Delta Time . . . . . . . . . . . . . . . . . . 399
Figure 9-16. Waveform Pane with Expanded Time at a Specific Time . . . . . . . . . . . . . . . . 399
Figure 9-17. Waveform Pane with Event Not Logged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Figure 9-18. Waveform Pane with Expanded Time Over a Time Range . . . . . . . . . . . . . . . 401
Figure 9-19. Bookmark Properties Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Figure 9-20. Wave Signal Search Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 9-21. Expression Builder Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Figure 9-22. Selecting Signals for Expression Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Figure 9-23. Display Tab of the Wave Window Preferences Dialog Box. . . . . . . . . . . . . . . 412
Figure 9-24. Grid and Timeline Tab of Wave Window Preferences Dialog Box . . . . . . . . . 413
Figure 9-25. Clock Cycles in Timeline of Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Figure 9-26. Wave Format Menu Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Figure 9-27. Format Tab of Wave Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Figure 9-28. Changing Signal Radix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Figure 9-29. Global Signal Radix Dialog in Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 9-30. Separate Signals with Wave Window Dividers . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 9-31. Splitting Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Figure 9-32. Wave Groups Denoted by Red Diamond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Figure 9-33. Contributing Signals Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Figure 9-34. Save Format Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Figure 9-35. Waveform Save Between Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Figure 9-36. Wave Filter Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Figure 9-37. Wave Filter Dataset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Figure 9-38. Signals Combined to Create Virtual Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Figure 9-39. Wave Extract/Pad Bus Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Figure 9-40. Virtual Signal Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Figure 9-41. Creating a Virtual Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Figure 9-42. Virtual Signal in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Figure 9-43. Modifying the Breakpoints Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Figure 9-44. Signal Breakpoint Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Figure 9-45. Breakpoints in the Source Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 9-46. File Breakpoint Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Figure 10-1. The Dataflow Window (undocked) - ModelSim . . . . . . . . . . . . . . . . . . . . . . . 441
Figure 10-2. Dot Indicates Input in Process Sensitivity Lis . . . . . . . . . . . . . . . . . . . . . . . . . 445
Figure 10-3. Active Time Label in Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Figure 10-4. Controlling Display of Redundant Buffers and Inverters . . . . . . . . . . . . . . . . . 448
Figure 10-5. Green Highlighting Shows Your Path Through the Design . . . . . . . . . . . . . . . 448
Figure 10-6. Highlight Selected Trace with Custom Color . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 10-7. Wave Viewer Displays Inputs and Outputs of Selected Process . . . . . . . . . . . 450

ModelSim User’s Manual, v10.1c 25

List of Figures

Figure 10-8. Unknown States Shown as Red Lines in Wave Window . . . . . . . . . . . . . . . . . 452
Figure 10-9. Dataflow: Point-to-Point Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Figure 10-10. The Print Postscript Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Figure 10-11. The Print Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Figure 10-12. The Page Setup Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Figure 10-13. Dataflow Options Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Figure 11-1. Language Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Figure 11-2. New Design Wizard Adding Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Figure 11-3. Language Template Block1 Added to Source Code . . . . . . . . . . . . . . . . . . . . . 467
Figure 11-4. Inserting Module Statement from Verilog Language Template . . . . . . . . . . . . 467
Figure 11-5. Expanding list_of_ansi_params . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Figure 11-6. Language Template Context Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Figure 11-7. Bookmark All Instances of a Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Figure 11-8. Setting Context from Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Figure 11-9. Examine Pop Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Figure 11-10. Time Indicator in Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Figure 11-11. Enter an Event Time Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Figure 11-12. Breakpoint in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Figure 11-13. Editing Existing Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Figure 11-14. Source Code for [Link]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Figure 11-15. Preferences By - Window Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Figure 13-1. Waveform Editor: Library Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Figure 13-2. Opening Waveform Editor from Structure or Objects Windows . . . . . . . . . . . 507
Figure 13-3. Create Pattern Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 13-4. Wave Edit Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Figure 13-5. Manipulating Waveforms with the Wave Edit Toolbar and Cursors . . . . . . . . 511
Figure 13-6. Export Waveform Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Figure 13-7. Evcd Import Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Figure 14-1. SDF Tab in Start Simulation Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Figure A-1. Runtime Options Dialog: Defaults Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure A-2. Runtime Options Dialog Box: Severity Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Figure A-3. Runtime Options Dialog Box: WLF Files Tab . . . . . . . . . . . . . . . . . . . . . . . . . 571
Figure D-1. DPI Use Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Figure E-1. Schematic Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Figure F-1. Change Text Fonts for Selected Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Figure F-2. Making Global Font Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Figure F-3. Modifying Signal Display Attributes in the Wave Window. . . . . . . . . . . . . . . . 690

26 ModelSim User’s Manual, v10.1c

List of Tables

Table 1-1. Simulation Tasks — ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 1-2. Use Modes for ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 1-3. Possible Definitions of an Object, by Language . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 1-4. Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 1-5. Deprecated Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 1-6. Deprecated Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 1-7. Deprecated Command Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 2-1. GUI Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 2-2. Design Object Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 2-3. Icon Shapes and Design Object Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 2-4. Graphic Elements of Toolbar in Find Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 2-5. Graphic Elements of Toolbar in Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 2-6. Information Displayed in Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 2-7. File Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 2-8. Edit Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 2-9. View Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 2-10. Compile Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 2-11. Simulate Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 2-12. Add Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 2-13. Tools Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 2-14. Layout Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 2-15. Bookmarks Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 2-16. Window Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 2-17. Help Menu — Item Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 2-18. Bookmarks Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 2-19. Compile Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 2-20. Coverage Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 2-21. Dataflow Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 2-22. FSM Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 2-23. Help Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 2-24. Layout Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 2-25. Memory Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 2-26. Mode Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 2-27. Objectfilter Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 2-28. Process Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 2-29. Profile Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 2-30. Schematic Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 2-31. Simulate Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 2-32. Source Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 2-33. Standard Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

ModelSim User’s Manual, v10.1c 27

List of Tables

Table 2-34. Step Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 2-35. Wave Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 2-36. Wave Compare Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 2-37. Wave Cursor Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 2-38. Wave Edit Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 2-39. Wave Expand Time Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 2-40. Zoom Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 2-41. Commands Related to the Call Stack Window . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 2-42. Call Stack Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 2-43. Class Graph Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 2-44. Class Instances Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 2-45. Class Tree Window Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 2-46. Class Tree Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 2-47. Class Tree Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 2-48. Files Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 2-49. Files Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 2-50. Files Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 2-51. FSM List Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 2-52. FSM List Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 2-53. FSM List Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 2-54. FSM Viewer Window — Graphical Elements . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 2-55. FSM View Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 2-56. FSM View Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 2-57. Library Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 2-58. Library Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 2-59. Actions for Time Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 2-60. Triggering Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 2-61. List Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 2-62. Locals Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 2-63. Locals Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 2-64. Memory Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 2-65. Memory List Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 2-66. Memory List Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 2-67. Memories Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 2-68. Memory Data Popup Menu — Address Pane . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 2-69. Memory Data Popup Menu — Data Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 2-70. Memory Data Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 2-71. Message Viewer Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 2-72. Message Viewer Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 2-73. Message Viewer Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 2-74. Objects Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 2-75. Processes Window Column Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 2-76. Structure Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 2-77. Columns in the Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 2-78. Analog Sidebar Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

28 ModelSim User’s Manual, v10.1c

List of Tables

Table 2-79. Icons and Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 2-80. Window Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 3-1. Compile Options for the -nodebug Compiling . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 7-1. Evaluation 1 of always Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Table 7-2. Evaluation 2 of always Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table 7-3. IEEE Std 1364 System Tasks and Functions - 1 . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 7-4. IEEE Std 1364 System Tasks and Functions - 2 . . . . . . . . . . . . . . . . . . . . . . . . . 348
Table 7-5. IEEE Std 1364 System Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Table 7-6. IEEE Std 1364 File I/O Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table 7-7. Stepping Within the Current Context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Table 8-1. WLF File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Table 8-2. Structure Tab Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Table 8-3. vsim Arguments for Collapsing Time and Delta Steps . . . . . . . . . . . . . . . . . . . . 380
Table 9-1. Actions for Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Table 9-2. Recording Delta and Event Time Information . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Table 9-3. Menu Selections for Expanded Time Display Modes . . . . . . . . . . . . . . . . . . . . . 402
Table 9-4. Actions for Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Table 9-5. Actions for Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Table 10-1. Icon and Menu Selections for Exploring Design Connectivity . . . . . . . . . . . . . 446
Table 10-2. Dataflow Window Links to Other Windows and Panes . . . . . . . . . . . . . . . . . . 458
Table 12-1. Signal Spy Reference Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Table 13-1. Signal Attributes in Create Pattern Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Table 13-2. Waveform Editing Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Table 13-3. Selecting Parts of the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Table 13-4. Wave Editor Mouse/Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Table 13-5. Formats for Saving Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Table 13-6. Examples for Loading a Stimulus File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Table 14-1. Matching SDF to VHDL Generics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Table 14-2. Matching SDF IOPATH to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Table 14-3. Matching SDF INTERCONNECT and PORT to Verilog . . . . . . . . . . . . . . . . 520
Table 14-4. Matching SDF PATHPULSE and GLOBALPATHPULSE to Verilog . . . . . . 521
Table 14-5. Matching SDF DEVICE to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
Table 14-6. Matching SDF SETUP to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
Table 14-7. Matching SDF HOLD to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
Table 14-8. Matching SDF SETUPHOLD to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Table 14-9. Matching SDF RECOVERY to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Table 14-10. Matching SDF REMOVAL to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Table 14-11. Matching SDF RECREM to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Table 14-12. Matching SDF SKEW to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Table 14-13. Matching SDF WIDTH to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Table 14-14. Matching SDF PERIOD to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Table 14-15. Matching SDF NOCHANGE to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Table 14-16. RETAIN Delay Usage (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
Table 14-17. RETAIN Delay Usage (with +vlog_retain_same2same_on) . . . . . . . . . . . . . 524
Table 14-18. Matching Verilog Timing Checks to SDF SETUP . . . . . . . . . . . . . . . . . . . . . 525

ModelSim User’s Manual, v10.1c 29

List of Tables

Table 14-19. SDF Data May Be More Accurate Than Model . . . . . . . . . . . . . . . . . . . . . . . 525
Table 14-20. Matching Explicit Verilog Edge Transitions to Verilog . . . . . . . . . . . . . . . . . 525
Table 14-21. SDF Timing Check Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Table 14-22. SDF Path Delay Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Table 14-23. Disabling Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Table 15-1. VCD Commands and SystemTasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 15-2. VCD Dumpport Commands and System Tasks . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 15-3. VCD Commands and System Tasks for Multiple VCD Files . . . . . . . . . . . . . . 537
Table 15-4. SystemC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Table 15-5. Driver States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Table 15-6. State When Direction is Unknown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Table 15-7. Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Table 15-8. VCD Values When Force Command is Used . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Table 15-9. Values for file_format Argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Table 15-10. Sample Driver Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Table 16-1. Changes to ModelSim Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Table 16-2. Tcl Backslash Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Table 16-3. Tcl List Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Table 16-4. Simulator-Specific Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Table 16-5. Tcl Time Conversion Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Table 16-6. Tcl Time Relation Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Table 16-7. Tcl Time Arithmetic Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Table 16-8. Commands for Handling Breakpoints and Errors in Macros . . . . . . . . . . . . . . 564
Table A-1. Runtime Option Dialog: Defaults Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . 569
Table A-2. Runtime Option Dialog: Severity Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . 571
Table A-3. Runtime Option Dialog: WLF Files Tab Contents . . . . . . . . . . . . . . . . . . . . . . . 571
Table A-4. Commands for Overriding the Default Initialization File . . . . . . . . . . . . . . . . . 573
Table A-5. License Variable: License Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Table A-6. MessageFormat Variable: Accepted Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Table C-1. Severity Level Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Table C-2. Exit Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Table D-1. VPI Compatibility Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Table D-2. vsim Arguments for DPI Application Using External Compilation Flows . . . . 660
Table D-3. Supported VHDL Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Table D-4. Supported ACC Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Table D-5. Supported TF Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Table D-6. Values for action Argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Table E-1. Command History Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Table E-2. Mouse Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
Table E-3. Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Table E-4. List Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Table E-5. Wave Window Mouse Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Table E-6. Wave Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Table F-1. Global Fonts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Table F-2. Default ListTranslateTable Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

30 ModelSim User’s Manual, v10.1c

List of Tables

Table F-3. Default LogicStyleTable Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

Table G-1. Files Accessed During Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Table G-2. Add Library Mappings to [Link] File . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

ModelSim User’s Manual, v10.1c 31

List of Tables

32 ModelSim User’s Manual, v10.1c

Chapter 1
Introduction

Documentation for ModelSim is intended for users of UNIX, Linux, and Microsoft Windows.

Not all versions of ModelSim are supported on all platforms. For more information on your
platform or operating system, contact your Mentor Graphics sales representative.

Operational Structure and Flow

Figure 1-1 illustrates the structure and general usage flow for verifying a design with
ModelSim.

ModelSim User’s Manual, v10.1c 33

Introduction
Simulation Task Overview

Figure 1-1. Operational Structure and Flow

VHDL
Design
Libraries vlib
Map libraries

Vendor vmap local work

Libraries library

vlog/
Design
files vcom Verilog/VHDL
Analyze/ Analyze/
Compile Compile
.ini or
.mpf file

compiled
database

vsim Simulate

Interactive Debugging Debug

activities

Simulation Output
(for example, vcd)

Post-processing Debug

Simulation Task Overview

The following table provides a reference for the tasks required for compiling, loading, and
simulating a design in ModelSim.

34 ModelSim User’s Manual, v10.1c

Introduction
Basic Steps for Simulation

Table 1-1. Simulation Tasks — ModelSim

Task Example Command Line GUI Menu Pull-down GUI Icons
Entry
Step 1: vlib <library_name> a. File > New > Project N/A
Map libraries vmap work <library_name> b. Enter library name
c. Add design files to
project
Step 2: vlog file1.v file2.v ... a. Compile > Compile Compile or
Compile the (Verilog) or Compile All
design vcom [Link] [Link] ... Compile > Compile All
(VHDL)

Step 3: vsim <top> a. Simulate > Start Simulate icon:

Load the Simulation
design into the b. Click on top design
simulator module or optimized
design unit name
c. Click OK
This action loads the
design for simulation
Step 4: run Simulate > Run Run, or
Run the step Run continue, or
simulation Run -all

Step 5: Common debugging N/A N/A

Debug the commands:
design bp
describe
drivers
examine
force
log
show

Basic Steps for Simulation

This section describes the basic procedure for simulating your design using ModelSim.

ModelSim User’s Manual, v10.1c 35

Introduction
Basic Steps for Simulation

Step 1 — Collect Files and Map Libraries

Files needed to run ModelSim on your design:

• design files (VHDL and/or Verilog ), including stimulus for the design
• libraries, both working and resource
• [Link] file (automatically created by the library mapping command)
For detailed information on the files accessed during system startup (including the [Link]
file), initialization sequences, and system environment variables, see the Appendix entitled
“System Initialization”.

Providing Stimulus to the Design

You can provide stimulus to your design in several ways:

• Language-based test bench

• Tcl-based ModelSim interactive command, force
• VCD files / commands
See Creating a VCD File and Using Extended VCD as Stimulus
• Third-party test bench generation tools

What is a Library?
A library is a location on your file system where ModelSim stores data to be used for
simulation. ModelSim uses one or more libraries to manage the creation of data before it is
needed for use in simulation. A library also helps to streamline simulation invocation. Instead of
compiling all design data each time you simulate, ModelSim uses binary pre-compiled data
from its libraries. For example, if you make changes to a single Verilog module, ModelSim
recompiles only that module, rather than all modules in the design.

Work and Resource Libraries

You can use design libraries in two ways:

• As a local working library that contains the compiled version of your design
• As a resource library
The contents of your working library will change as you update your design and recompile. A
resource library is typically unchanging, and serves as a parts source for your design. Examples
of resource libraries are shared information within your group, vendor libraries, packages, or
previously compiled elements of your own working design. You can create your own resource

36 ModelSim User’s Manual, v10.1c

Introduction
Basic Steps for Simulation

libraries, or they may be supplied by another design team or a third party (for example, a silicon
vendor).

For more information on resource libraries and working libraries, refer to Working Library
Versus Resource Libraries, Managing Library Contents, Working with Design Libraries, and
Specifying Resource Libraries.

Creating the Logical Library (vlib)

Before you can compile your source files, you must create a library in which to store the
compilation results. You can create the logical library using the GUI, by choosing File > New >
Library from the main menu (see Creating a Library), or you can use the vlib command. For
example, the following command:

vlib work

creates a library named work. By default, compilation results are stored in the work library.

Mapping the Logical Work to the Physical Work Directory (vmap)

VHDL uses logical library names that can be mapped to ModelSim library directories. If
libraries are not mapped properly, and you invoke your simulation, necessary components will
not be loaded and simulation will fail. Similarly, compilation can also depend on proper library
mapping.

By default, ModelSim can find libraries in your current directory (assuming they have the right
name), but for it to find libraries located elsewhere, you need to map a logical library name to
the pathname of the library.

You can use the GUI (Library Mappings with the GUI), a command (Library Mapping from the
Command Line), or a project (Getting Started with Projects) to assign a logical name to a design
library.

The format for command line entry is:

vmap <logical_name> <directory_pathname>

This command sets the mapping between a logical library name and a directory.

Use braces ({}) for cases where the path contains multiple items that need to be escaped, such as
spaces in the pathname or backslash characters. For example:

vmap celllib {$LIB_INSTALL_PATH/Documents And Settings/All/celllib}

Step 2 — Compile the Design

To compile a design, run one of the following ModelSim commands, depending on the
language used to create the design:

ModelSim User’s Manual, v10.1c 37

Introduction
Basic Steps for Simulation

• vlog — Verilog
• vcom — VHDL
• sccom — SystemC

Compiling Verilog (vlog)

The vlog command compiles Verilog modules in your design. You can compile Verilog files in
any order, since they are not order dependent. See Verilog Compilation for details.

Compiling VHDL (vcom)

The vcom command compiles VHDL design units. You must compile VHDL files in the order
necessitate to any design requirements. Projects may assist you in determining the compile
order: for more information, see Auto-Generating Compile Order. See Compilation and
Simulation of VHDL for details on VHDL compilation.

Step 3 — Load the Design for Simulation

Running the vsim Command on the Top Level of the Design
After you have compiled your design, it is ready for simulation. You can then run the vsim
command using the names of any top-level modules (many designs contain only one top-level
module). For example, if your top-level modules are named “testbench” and “globals,” then
invoke the simulator as follows:

vsim testbench globals

After the simulator loads the top-level modules, it iteratively loads the instantiated modules and
UDPs in the design hierarchy, linking the design together by connecting the ports and resolving
hierarchical references.

Using Standard Delay Format Files

You can incorporate actual delay values to the simulation by applying standard delay format
(SDF) back-annotation files to the design. For more information on how SDF is used in the
design, see Specifying SDF Files for Simulation.

Step 4 — Simulate the Design

Once you have successfully loaded the design, simulation time is set to zero, and you must enter
a run command to begin simulation. For more information, see Verilog and SystemVerilog
Simulation, and VHDL Simulation.

The basic commands you use to run simulation are:

38 ModelSim User’s Manual, v10.1c

Introduction
Modes of Operation

• add wave
• bp
• force
• run
• step

Step 5 — Debug the Design

The ModelSim GUI provides numerous commands, operations, and windows useful in
debugging your design. In addition, you can also use the command line to run the following
basic simulation commands for debugging:

• describe
• drivers
• examine
• force
• log
• show

Modes of Operation
Many users run ModelSim interactively with the graphical user interface (GUI)—using the
mouse to perform actions from the main menu or in dialog boxes. However, there are really
three modes of ModelSim operation, as described in Table 1-2.

Table 1-2. Use Modes for ModelSim

Mode Characteristics How ModelSim is invoked
GUI interactive; has graphical from a desktop icon or from the OS command
windows, push-buttons, shell prompt. Example:
menus, and a command OS> vsim
line in the transcript.
Default mode
Command-line interactive command with -c argument at the OS command prompt.
line; no GUI Example:
OS> vsim -c
Batch non-interactive batch at OS command shell prompt using redirection
script; no windows or of standard input. Example:
interactive command line C:\ vsim vfiles.v <infile >outfile

ModelSim User’s Manual, v10.1c 39

Introduction
Modes of Operation

The ModelSim User’s Manual focuses primarily on the GUI mode of operation. However, this
section provides an introduction to the Command-line and Batch modes.

A command is available to help batch users access commands not available for use in batch
mode. Refer to the batch_mode command in the ModelSim Reference Manual for more details.

Command Line Mode

In command line mode ModelSim executes any startup command specified by the Startup
variable in the [Link] file. If vsim is invoked with the -do "command_string" option, a
DO file (macro) is called. A DO file executed in this manner will override any startup command
in the [Link] file.

During simulation a transcript file is created containing any messages to stdout. A transcript file
created in command line mode may be used as a DO file if you invoke the transcript on
command after the design loads (see the example below). The transcript on command writes all
of the commands you invoke to the transcript file.

For example, the following series of commands results in a transcript file that can be used for
command input if top is re-simulated (remove the quit -f command from the transcript file if
you want to remain in the simulator).

vsim -c top

library and design loading messages… then execute:

transcript on
force clk 1 50, 0 100 -repeat 100
run 500
run @5000
quit -f

Rename a transcript file that you intend to use as a DO file—if you do not rename it, ModelSim
will overwrite it the next time you run vsim. Also, simulator messages are already commented
out, but any messages generated from your design (and subsequently written to the transcript
file) will cause the simulator to pause. A transcript file that contains only valid simulator
commands will work fine; comment out anything else with a pound sign (#).

Refer to Creating a Transcript File for more information about creating, locating, and saving a
transcript file.

Stand-alone tools pick up project settings in command-line mode if you invoke them in the
project's root directory. If invoked outside the project directory, stand-alone tools pick up
project settings only if you set the MODELSIM environment variable to the path to the project
file (<Project_Root_Dir>/<Project_Name>.mpf).

40 ModelSim User’s Manual, v10.1c

Introduction
Definition of an Object

Batch Mode
Batch mode is an operational mode that provides neither an interactive command line nor
interactive windows. In a Windows environment, you run vsim from a Windows command
prompt and standard input and output are redirected to and from files.

Here is an example of a batch mode simulation using redirection of std input and output:

vsim counter <yourfile >outfile

where “yourfile” represents a script containing various ModelSim commands, and the angle
brackets (< >) are redirection indicators.

You can use the CTRL-C keyboard interrupt to terminate batch simulation in UNIX and
Windows environments.

Definition of an Object
Because ModelSim supports a variety of design languages (Verilog, VHDL, SystemVerilog),
the word “object” is used to refer to any valid design element in those languages, whenever a
specific language reference is not needed. Table 1-3 summarizes the language constructs that an
object can refer to.
Table 1-3. Possible Definitions of an Object, by Language
Design Language An object can be
VHDL block statement, component instantiation, constant,
generate statement, generic, package, signal, alias,
variable
Verilog function, module instantiation, named fork, named
begin, net, task, register, variable
SystemVerilog In addition to those listed above for Verilog:
class, package, program, interface, array, directive,
property, sequence
PSL property, sequence, directive, endpoint

Standards Supported
Standards documents are sometimes informally referred to as the Language Reference Manual
(LRM). This standards listed here are the complete name of each manual. Elsewhere in this
manual the individual standards are referenced using the IEEE Std number.

The following standards are supported for the ModelSim products:

• VHDL —

ModelSim User’s Manual, v10.1c 41

Introduction
Assumptions

o IEEE Std 1076-2008, IEEE Standard VHDL Language Reference Manual.

ModelSim supports a subset of the VHDL 2008 standard features. For detailed
standard support information see the vhdl2008 technote available at
<install_dir>/docs/technotes/[Link], or from the GUI menu pull-down Help
> Technotes > vhdl2008.
Potential migration issues and mixing use of VHDL 2008 with older VHDL code are
addressed in the vhdl2008migration technote.
o IEEE Std 1164-1993, Standard Multivalue Logic System for VHDL Model
Interoperability
o IEEE Std 1076.2-1996, Standard VHDL Mathematical Packages
Any design developed with ModelSim will be compatible with any other VHDL system
that is compliant with the 1076 specifications.
• Verilog/SystemVerilog —
o IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description Language
o IEEE Std 1800-2009. IEEE Standard for SystemVerilog -- Unified Hardware
Design, Specification, and Verification Language
Both PLI (Programming Language Interface) and VCD (Value Change Dump) are
supported for ModelSim users.
• SDF and VITAL —
o SDF – IEEE Std 1497-2001, IEEE Standard for Standard Delay Format (SDF) for
the Electronic Design Process
o VITAL 2000 – IEEE Std 1076.4-2000, IEEE Standard for VITAL ASIC Modeling
Specification

Assumptions
Using the ModelSim product and its documentation is based on the following assumptions:

• You are familiar with how to use your operating system and its graphical interface.
• You have a working knowledge of the design languages. Although ModelSim is an
excellent application to use while learning HDL concepts and practices, this document is
not written to support that goal.
• You have worked through the appropriate lessons in the ModelSim Tutorial and are
familiar with the basic functionality of ModelSim. You can find the ModelSim Tutorial
by choosing Help from the main menu.

42 ModelSim User’s Manual, v10.1c

Introduction
Text Conventions

Text Conventions
Table 1-4 lists the text conventions used in this manual.

Table 1-4. Text Conventions

Text Type Description
italic text provides emphasis and sets off filenames,
pathnames, and design unit names
bold text indicates commands, command options, menu
choices, package and library logical names, as
well as variables, dialog box selections, and
language keywords
monospace type monospace type is used for program and
command examples
The right angle (>) is used to connect menu choices when
traversing menus as in: File > Quit
UPPER CASE denotes file types used by ModelSim (such as
DO, WLF, INI, MPF, PDF.)

Installation Directory Pathnames

When referring to installation paths, this manual uses “<installdir>” as a generic representation
of the installation directory for all versions of ModelSim. The actual installation directory on
your system may contain version information.

Deprecated Features, Commands, and Variables

This section provides tables of features, commands, command arguments, and [Link]
variables that have been superseded by new versions. Although you can still use superseded
features, commands, arguments, or variables, Mentor Graphics deprecates their usage—you
should use the corresponding new version whenever possible or convenient.

The following tables indicate the in which the item was superseded and a link to the new item
that replaces it, where applicable.

Table 1-5. Deprecated Features

Feature Version New Feature / Information
Support for Solaris SPARC and 10.1 None. Solaris is no longer supported.
Solaris x86 operating systems

ModelSim User’s Manual, v10.1c 43

Introduction
Deprecated Features, Commands, and Variables

Table 1-6. Deprecated Commands

Command Version New Command / Information

Table 1-7. Deprecated Command Arguments

Argument Version New Argument / Information
vopt -bbox 10.1 vopt -pdu, name change only.
vopt -save_bbox_hier_refs 10.1 vopt -save_pdu_hier_refs, name change only.
vsim -ignore_bbox 10.1 vsim -ignore_pdu, name change only.
vcom -synthprefix 10.1 vcom -addpragmaprefix
vlog -synthprefix 10.1 vlog -addpragmaprefix

44 ModelSim User’s Manual, v10.1c

Chapter 2
Graphical User Interface

The ModelSim graphical user interface (GUI) provides access to numerous debugging tools and
windows that enable you to analyze different parts of your design. All windows initially display
within the ModelSim Main window.

Figure 2-1. Graphical User Interface

ModelSim User’s Manual, v10.1c 45

Graphical User Interface

The following table summarizes all of the available windows.

Table 2-1. GUI Windows

Window name Description More details
Main central GUI access point Main Window
Call Stack displays the current call stack, allowing Call Stack Window
you to debug your design by analyzing
the depth of function calls
Class Graph displays interactive relationships of Class Graph Window
SystemVerilog classes in graphical
form
Class Instances displays class instances Class Instances Window
Class Tree displays interactive relationships of Class Tree Window
SystemVerilog classes in tabular form.
Dataflow displays "physical" connectivity and Dataflow Window
lets you trace events (causality)
Files displays the source files and their Files Window
locations for the loaded simulation
FSM List lists all recognized FSMs in the design FSM List Window
FSM View graphical representation of a recognized FSM Viewer Window
FSM
Library lists design libraries and compiled Library Window
design units
List shows waveform data in a tabular List Window
format
Locals displays data objects that are Locals Window
immediately visible at the current
execution point of the selected process
Memory windows that show memories and their Memory List Window
contents Memory Data Window
Message Viewer allows easy access, organization, and Message Viewer Window
analysis of Note, Warning, Errors or
other messages written to transcript
during simulation
Objects displays all declared data objects in the Objects Window
current scope
Process displays all processes that are scheduled Processes Window
to run during the current simulation
cycle

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Design Object Icons and Their Meanings

Table 2-1. GUI Windows (cont.)

Window name Description More details
Project provides access to information about Projects
Projects
Source a text editor for viewing and editing Source Window
files, such as Verilog, VHDL, and DO
files
Structure (sim) displays hierarchical view of active Structure Window
simulation. Name of window is either
“sim” or “<dataset_name>”
Transcript keeps a running history of commands Transcript Window
and messages and provides a command-
line interface
Watch displays signal or variable values at the Watch Window
current simulation time
Wave displays waveforms Wave Window
The windows are customizable in that you can position and size them as you see fit, and
ModelSim will remember your settings upon subsequent invocations. You can restore
ModelSim windows and panes to their original settings by selecting Layout > Reset in the
menu bar.

You can copy the title text in a window or pane header by selecting it and right-clicking to
display a popup menu. This is useful for copying the file name of a source file for use elsewhere
(see Figure 2-58 for an example of this in an FSM Viewer window).

Design Object Icons and Their Meanings

The color and shape of icons convey information about the language and type of a design
object. Table 2-2 shows the icon colors and the languages they indicate.
Table 2-2. Design Object Icons
Icon color Design Language
light blue Verilog or SystemVerilog
dark blue VHDL
orange virtual object

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Design Object Icons and Their Meanings

Here is a list of icon shapes and the design object types they indicate:

Table 2-3. Icon Shapes and Design Object Types

Icon shape Example Design Object Type
Square any scope (VHDL block, Verilog named block, SC module,
class, interface, task, function, and so forth.)
Square and SystemVerilog object, OVM, and UVM test bench scope or
red asterix object
Circle process

Diamond valued object (signals, nets, registers, and so forth.)

Diamond an editable waveform created with the waveform editor

and yellow
pulse on red
dot
Diamond valued object (abstract)
and red
asterix
Diamond indicates mode (In, Inout, Out) of an object port
and green
arrow
Triangle caution sign on comparison object

Star transaction; The color of the star for each transaction depends
on the language of the region in which the transaction stream
occurs: dark blue for VHDL, light blue for Verilog and
SystemVerilog, green for SystemC.

Setting Fonts
You may need to adjust font settings to accommodate the aspect ratios of wide screen and
double screen displays or to handle launching ModelSim from an X-session. Refer to Making
Global Font Changes for more information.

Font Scaling
To change font scaling, select the Transcript window, then Transcript > Adjust Font Scaling.
You will need a ruler to complete the instructions in the lower right corner of the dialog. When
you have entered the pixel and inches information, click OK to close the dialog. Then, restart
ModelSim to see the change. This is a one time setting; you should not need to set it again
unless you change display resolution or the hardware (monitor or video card). The font scaling

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Using the Find and Filter Functions

applies to Windows and UNIX operating systems. On UNIX systems, the font scaling is stored
based on the $DISPLAY environment variable.

Using the Find and Filter Functions

Finding and/or filtering capabilities are available for most windows. The Find mode toolbar is
shown in Figure 2-2. The filtering function is denoted by a “Contains” field (Figure 2-3).

Figure 2-2. Find Mode

Figure 2-3. Filter Mode

Windows that support both Find (Figure 2-2) and Filter modes (Figure 2-3) allow you to toggle
between the two modes by doing any one of the following:

• Use the Ctrl+M hotkey.

• Click the “Find” or “Contains” words in the toolbar at the bottom of the window.
• Select the mode from the Find Options popup menu (see Using the Find Options Popup
Menu).
The last selected mode is remembered between sessions.

A “Find” toolbar will appear along the bottom edge of the active window when you do either of
the following:

• Select Edit > Find in the menu bar.

• Click the Find icon in the Standard Toolbar.
All of the above actions are toggles - repeat the action and the Find toolbar will close.

The Find or Filter entry fields prefill as you type, based on the context of the current window
selection. The find or filter action begins as you type.

There is a simple history mechanism that saves find or filter strings for later use. The keyboard
shortcuts to use this feature are:

• Ctrl+P — retrieve previous search string

• Ctrl+N — retrieve next search string
Other hotkey actions include:

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Using the Find and Filter Functions

• Esc — closes the Find toolbar

• Enter (Windows) or Return (UNIX or Linux) — initiates a “Find Next” action
• Ctrl+T — search while typing (default is on)
The entry field turns red if no matches are found.

The graphic elements associated with the Find toolbar are shown in Table 2-4.

Note
The Find Toolbar graphic elements are context driven. The actions available change for
each window.

Table 2-4. Graphic Elements of Toolbar in Find Mode

Graphic Element Action
Find opens the find toolbar in the active
window

Close closes the find toolbar

Find entry field allows entry of find parameters

Find Options opens the Find Options popup menu at

the bottom of the active window. The
contents of the menu changes for each
window.
Clear Entry Field clears the entry field

Execute Search initiates the search

Toggle Search Direction toggles search direction upward or

downward through the active window
Find All Matches; highlights every occurrence of the find
Bookmark All Matches (for Source item; for the Source window only,
window only) places a blue flag (bookmark) at every
occurrence of the find item
Search For Click and hold the button to open a
drop down menu with the following
options:
• Instance
• Design Unit

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Using the Find and Filter Functions

Table 2-4. Graphic Elements of Toolbar in Find Mode (cont.)

Graphic Element Action
Match Case search must match the case of the text
entered in the Find field
Exact (whole word) searches for whole words that match
those entered in the Find field
Regular Expression Searches for a regular expression;
Source window only.
Wrap Search Searches from cursor to bottom of
window then continues search from top
of the window.

Using the Filter Mode

By entering a string in the “Contains” text entry box you can filter the view of the selected
window down to the specific information you are looking for.
Table 2-5. Graphic Elements of Toolbar in Filter Mode
Button Name Shortcuts Description
Filter Regular Expression None A drop down menu that allows
you to set the wildcard mode.

A text entry box for your filter

string.
Clear Filter None Clears the text entry box and
removes the filter from the
active window.

Wildcard Usage
There are three wildcard modes:

• glob-style — Allows you to use the following special wildcard characters:

o * — matches any sequence of characters in the string
o ? — matches any single character in the string
o [<chars>] — matches any character in the set <chars>.
o \<x> — matches the single character <x>, which allows you to match on any special
characters (*, ?, [, ], and \)
Refer to Finding Items in the Structure Window and the Tcl documentation for more
information:

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User-Defined Radices

Help > Tcl Man Pages

Tcl Commands > string > string match
• regular-expression — (Source window only) allows you to use wildcard characters
based on Tcl regular expressions. For more information refer to the Tcl documentation:
Help > Tcl Man Pages
Tcl Commands > re_syntax
• exact — indicates that no characters have special meaning, thus disabling wildcard
features.
The string entry field of the Contains toolbar item is case-insensitive, If you need to search for
case-sensitive strings in the Source window select “regular-expression” and prepend the string
with (?c).

Using the Find Options Popup Menu

When you click the Find Options icon in the Find entry field it will open a Find Options
popup menu (Figure 2-4).

Figure 2-4. Find Options Popup Menu

The Find Options menu displays the options available to you as well as hot keys for initiating
the actions without the menu.

User-Defined Radices
A user definable radix is used to map bit patterns to a set of enumeration labels. After defining a
new radix, the radix will be available for use in the List, Watch, and Wave windows or with the
examine command.

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User-Defined Radices

There are four commands used to manage user defined radices:

• radix define
• radix names
• radix list
• radix delete

Using the radix define Command

The radix define command is used to create or modify a radix. It must include a radix name and
a definition body, which consists of a list of number pattern, label pairs. Optionally, it may
include the -color argument for setting the radix color (see Example 2-2).

{
<numeric-value> <enum-label>,
<numeric-value> <enum-label>
-default <radix>
}

A <numeric-value> is any legitimate HDL integer numeric literal. To be more specific:

<base>#<base-integer># --- <base> is 2, 8, 10, or 16

<base>"bit-value" --- <base> is B, O, or X
<integer>
<size>'<base><number> --- <size> is an integer, <base> is b, d, o, or h.

Check the Verilog and VHDL LRMs for exact definitions of these numeric literals.

The comma (,) in the definition body is optional. The <enum-label> is any arbitrary string. It
should be quoted (""), especially if it contains spaces.

The -default entry is optional. If present, it defines the radix to use if a match is not found for a
given value. The -default entry can appear anywhere in the list, it does not have to be at the end.

Example 2-1 shows the radix define command used to create a radix called “States,” which
will display state values in the List, Watch, and Wave windows instead of numeric values.

Example 2-1. Using the radix define Command

radix define States {

11'b00000000001 "IDLE",
11'b00000000010 "CTRL",
11'b00000000100 "WT_WD_1",
11'b00000001000 "WT_WD_2",
11'b00000010000 "WT_BLK_1",
11'b00000100000 "WT_BLK_2",
11'b00001000000 "WT_BLK_3",
11'b00010000000 "WT_BLK_4",
11'b00100000000 "WT_BLK_5",

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User-Defined Radices

11'b01000000000 "RD_WD_1",
11'b10000000000 "RD_WD_2",
-default hex
}

Figure 2-5 shows an FSM signal called /test-sm/sm_seq0/sm_0/state in the Wave window with
a binary radix and with the user-defined “States” radix (as defined in Example 2-1).

Figure 2-5. User-Defined Radix “States” in the Wave Window

Figure 2-6 shows an FSM signal called /test-sm/sm_seq0/sm_0/state in the List window with a
binary radix and with the user-defined “States” radix (as defined in Example 2-1)

Figure 2-6. User-Defined Radix “States” in the List Window

Using radix define to Specify Radix Color

The following example illustrates how to use the radix define command to specify the radix
color:

Example 2-2. Using radix define to Specify Color

radix define States {

11'b00000000001 "IDLE" -color yellow,
11'b00000000010 "CTRL" -color #ffee00,
11'b00000000100 "WT_WD_1" -color orange,
11'b00000001000 "WT_WD_2" -color orange,

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User-Defined Radices

11'b00000010000 "WT_BLK_1",
11'b00000100000 "WT_BLK_2",
11'b00001000000 "WT_BLK_3",
11'b00010000000 "WT_BLK_4",
11'b00100000000 "WT_BLK_5",
11'b01000000000 "RD_WD_1" -color green,
11'b10000000000 "RD_WD_2" -color green,
-default hex
-defaultcolor white
}

If a pattern/label pair does not specify a color, the normal wave window colors will be used. If
the value of the waveform does not match any pattern, then -default <radix_type> and
-defaultcolor will be used.

To specify a range of values, wildcards may be specified for bits or characters of the value. The
wildcard character is '?', similar to the iteration character in a Verilog UDP, for example:

radix define {
6'b01??00 "Write" -color orange,
6'b10??00 "Read" -color green
}

In this example, the first pattern will match "010000", "010100", "011000", and "011100". In
case of overlaps, the first matching pattern is used, going from top to bottom.

Setting Global Signal Radix

The Global Signal Radix feature allows you to set the radix for a selected signal or signals in the
active window and in other windows where the signal appears. The Global Signal Radix can be
set from the Locals, Objects, Schematic, or Wave windows as follows:

• Select a signal or group of signals.

• Right-click the selected signal(s) and click Global Signal Radix from the popup menu
(in the Wave window, select Radix > Global Signal Radix).
This opens the Global Signal Radix dialog box (Figure 2-7), where you may select a
radix. This sets the radix for the selected signal(s) in the active window and every other
window where the signal appears.

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User-Defined Radices

Figure 2-7. Setting the Global Signal Radix

Setting a Fixed Point Radix

Fixed point types are used in VHDL and SystemC to represents non-integer numbers without
using a floating point format. ModelSim automatically recognizes VHDL sfixed and ufixeda
types as well as SystemC SC_FIXED and SC_UFIXED types and displays them correctly with
a fixed point format.

In addition, a general purpose fixed point radix feature is available for displaying any vector,
regardless of type, in a fixed point format in the Wave window. You simply have to specify how
many bits to use as fraction bits from the whole vector.

With the Wave window active:

1. Select (LMB) a signal or signals in the Pathnames pane of the Wave window.
2. Right-click the selected signal(s) and select Radix > Fixed Point from the popup menu.
This opens the Fixed Point Radix dialog.

Figure 2-8. Fixed Point Radix Dialog

3. Type the number of bits you want to appear as the fraction and click OK.

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Saving and Reloading Formats and Content

Saving and Reloading Formats and Content

You can use the write format restart command to create a single .do file that will recreate all
debug windows and breakpoints (see Saving and Restoring Breakpoints) when invoked with the
do command in subsequent simulation runs. The syntax is:

write format restart <filename>

If the ShutdownFile [Link] variable is set to this .do filename, it will call the write
format restart command upon exit.

Active Time Label

The Active Time Label displays the current time of the active cursor or the Now (end of
simulation) time in the Dataflow, Schematic, Source, and FSM windows. This is the time used
to control state values displayed or annotated in the window.

Figure 2-9. Active Cursor Time

When you run a simulation and it comes to an end, the Active Time Label displays the Now
time - which is the end-of-simulation time. When you select a cursor in the Wave window, or in
the Wave viewer of the Schematic or Dataflow window, the Active Time Label automatically
changes to display the time of the current active cursor.

The Active Time label includes a minimize/maximize button that allows you to hide or display
the label.

When a signal or net is selected, you can jump to the previous or next transition of that signal,
with respect to the active time, by clicking the Find Previous/Next Transition buttons.

To change the display from showing the Active Time to showing the Now time, or vice versa,
do the following:

• Make the Source, Dataflow, Schematic, or FSM window the active window by clicking
on it.
• Open the dedicated menu for the selected window (i.e., if the Schematic window is
active, open the Schematic menu in the menu bar).

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Window Specific Keyboard Shortcuts

• Select either “Examine Now” or “Examine Current Cursor.”

You can also change the Active Time by simply clicking on the Active Time Label to open the
Enter Value dialog box (Figure 2-10), where you can change the value.

Figure 2-10. Enter Active Time Value

To enable the Active Time Label in the Dataflow window, select Dataflow > Dataflow
Preferences > Options and check Active Time label in the Show field of the Dataflow
Options dialog box.

Window Specific Keyboard Shortcuts

You can open a list of commonkeyboard shortcuts for many windows by entering Ctrl-?

Figure 2-11. Schematic Keyboard Shortcuts

The following windows have keyboard shortcuts assigned:

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Bookmarks

Dataflow Window
Library Window
Objects Window
Source Window
Structure Window
Transcript Window
Wave Window
For more information about Window specific keyboard shortcuts as well as Global keyboard
shortcuts, refer to the Command and Keyboard Shortcuts Appendix.

Bookmarks
You can create bookmarks that allow you to return to a specific view or place in your design for
some of the windows. The bookmarks you make can be saved and automatically restored. Some
of the windows that allow bookmarking include the Structure, Files, Objects, Wave, and
Objects windows.

Working with Bookmarks

The Bookmarks toolbar and the Bookmarks menu give you access to the following
bookmarking features:

• Add Bookmarks
Bookmarks are added to an active window by selecting Bookmarks > Add
Bookmark or by clicking the Add Bookmark button. You will be prompted to
automatically save and restore your bookmarks when you set the first bookmark.
You can change the automatic save and restore settings in the Bookmark Options
Dialog Box.
• Add Custom
Selecting Add Custom opens the New Bookmark dialog box with the context
field(s) populated and a field for specifying an alias for the bookmark. Click and
hold the Add Bookmark button to access this feature from the Bookmarks toolbar.

Note
Aliases are mapped to the window in which a bookmark is set. You can use the same alias
for different bookmarks as long as each alias is assigned to a bookmark set in a different
window.

• Deleting Bookmarks

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Bookmarks

You can choose to delete the bookmarks from the currently active window or from
all windows.
• Manage Bookmarks
Opens the Manage Bookmarks dialog box. Refer to Managing Your Bookmarks
for more information.
• Load Bookmarks
Loads the bookmarks saved in the [Link] file. You can choose whether to
load bookmarks for the currently active window or all the bookmarks saved in the
[Link] file. Bookmarks are automatically loaded from the saved
[Link] file when you start a new simulation session.

Note
You must reload bookmarks for a window if you close then reopen that window during
the current session.

• Jump to Bookmark
Shows the available bookmarks in the currently active window followed by a drop
down list of bookmarks for each window. You can set the maximum number of
bookmarks listed in the Bookmark Options Dialog Box.

Managing Your Bookmarks

You can open the Manage Bookmarks dialog box with the Manage Bookmarks toolbar button
or by selecting Bookmarks > Manage Bookmarks. The dialog box can be kept open during
your simulation (Figure 2-12).

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Bookmarks

Figure 2-12. Manage Bookmarks Dialog Box

• Simple view mode changes the buttons from name and icon mode to icon only mode.
• Checking Active window only changes the display to show the bookmarks in the
currently active window. Selecting a different window in the tool changes the display to
the bookmarks set in that window.
• Selecting New opens the New Bookmark dialog box. The fields in the dialog
automatically load the settings of the view in the currently active window. You can
choose to name the bookmark with an alias to provide a more meaningful description.
Aliases are displayed in the Alias column in the Manage Bookmarks dialog box.
• Selecting Options opens the Bookmark Options dialog box (Figure 2-13).

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Bookmarks

Figure 2-13. Bookmark Options Dialog Box

The Menu Display section allows you to:

o Set the number of bookmarks displayed in the Bookmarks menu or the Jump to
Bookmark button menu.
o Select the types of information displayed for each bookmark.
The Other section allows you to:
o Specify a different base name for bookmarks.
o Choose whether you want to automatically save bookmarks and when they are
saved.
o Automatically restore the bookmarks when windows are first loaded in the current
session.
o Show informational message after bookmark actions sends bookmark actions to
the transcript. For example:

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Main Window

# Bookmark(s) were restored for window "Source"

Main Window
The primary access point in the ModelSim GUI is called the Main window. It provides
convenient access to design libraries and objects, source files, debugging commands, simulation
status messages, and so forth. When you load a design, or bring up debugging tools, ModelSim
opens windows appropriate for your debugging environment.

Elements of the Main Window

The following sections outline the GUI terminology used in this manual.

Menu Bar Toolbar Frame

Toolbar Window
Tab Group Pane

The Main window is the primary access point in the GUI. Figure 2-14 shows an example of the
Main window during a simulation run.

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Main Window

Figure 2-14. Main Window of the GUI

The Main window contains a menu bar, toolbar frame, windows, tab groups, and a status bar,
which are described in the following sections.

Menu Bar
The menu bar provides access to many tasks available for your workflow. Figure 2-15 shows
the selection in the menu bar that changes based on whichever window is currently active.

The menu items that are available and how certain menu items behave depend on which
window is active. For example, if the Structure window is active and you choose Edit from the
menu bar, the Clear command is disabled. However, if you click in the Transcript window and
choose Edit, the Clear command is enabled. The active window is denoted by a blue title bar

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Main Window

Figure 2-15. Main Window — Menu Bar

Toolbar Frame
The toolbar frame contains several toolbars that provide quick access to various commands and
functions.

Figure 2-16. Main Window — Toolbar Frame

Toolbar
A toolbar is a collection of GUI elements in the toolbar frame and grouped by similarity of task.
There are many toolbars available within the GUI, refer to the section “Main Window Toolbar”
for more information about each toolbar. Figure 2-17 highlights the Compile toolbar in the
toolbar frame.

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Main Window

Figure 2-17. Main Window — Toolbar

Window
ModelSim can display over 40 different windows you can use with your workflow. This manual
refers to all of these objects as windows, even though you can rearrange them such that they
appear as a single window with tabs identifying each window.

Figure 2-18 shows an example of a layout with five windows visible; the Structure, Objects,
Processes, Wave and Transcript windows.

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Main Window

Figure 2-18. GUI Windows

Tab Group
You can group any number of windows into a single space called a tab group, allowing you to
show and hide windows by selecting their tabs. Figure 2-19 shows a tab group of the Library,
Files, Capacity and Structure windows, with the Structure (sim) window visible.

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Main Window

Figure 2-19. GUI Tab Group

Pane
Some windows contain panes, which are separate areas of a window display containing distinct
information within that window. One way to tell if a window has panes is whether you receive
different popup menus (right-click menu) in different areas. Windows that have panes include
the Wave, Source, and List windows. Figure 2-20 shows the Wave window with its the three
panes.

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Main Window

Figure 2-20. Wave Window Panes

Main Window Status Bar

Fields at the bottom of the Main window provide the following information about the current
simulation:

Figure 2-21. Main Window Status Bar

Table 2-6. Information Displayed in Status Bar

Field Description
Project name of the current project
Now the current simulation time

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Main Window

Table 2-6. Information Displayed in Status Bar (cont.)

Field Description
Delta the current simulation iteration number
Profile Samples the number of profile samples collected during the
current simulation
Memory the total memory used during the current simulation
environment name of the current context (object selected in the
active Structure window)
line/column line and column numbers of the cursor in the active
Source window

Selecting the Active Window

When the title bar of a window is highlighted - solid blue - it is the active window. All menu
selections will correspond to this active window. You can change the active window in the
following ways.

• (default) Click anywhere in a window or on its title bar.

• Move the mouse pointer into the window.
To turn on this feature, select Window > FocusFollowsMouse. Default time delay
for activating a window after the mouse cursor has entered the window is 300ms.
You can change the time delay with the PrefMain(FFMDelay) preference variable.

Rearranging the Main Window

You can alter the layout of the Main window using any of the following methods.

• Moving a Window or Tab Group

• Moving a Tab out of a Tab Group
• Undocking a Window from the Main Window
When you exit ModelSim, the current layout is saved for a given design so that it appears the
same the next time you invoke the tool.

Moving a Window or Tab Group

1. Click on the header handle in the title bar of the window or tab group.

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Main Window

Figure 2-22. Window Header Handle

2. Drag, without releasing the mouse button, the window or tab group to a different area of
the Main window
Wherever you move your mouse you will see a dark blue outline that previews where
the window will be placed.
If the preview outline is a rectangle centered within a window, it indicates that you will
convert the window or tab group into new tabs within the highlighted window.
3. Release the mouse button to complete the move.

Moving a Tab out of a Tab Group

1. Click on the tab handle that you want to move.

Figure 2-23. Tab Handle

2. Drag, without releasing the mouse button, the tab to a different area of the Main window
Wherever you move your mouse you will see a dark blue outline that previews where
the tab will be placed.
If the preview outline is a rectangle centered within a window, it indicates that you will
move the tab into the highlighted window.
3. Release the mouse button to complete the move.

Undocking a Window from the Main Window

• Follow the steps in Moving a Window or Tab Group, but drag the window outside of the
Main window, or
• Click on the Dock/Undock button for the window.

Figure 2-24. Window Undock Button

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Navigating in the Main Window

Navigating in the Main Window

The Main window can contain of a number of windows that display various types of
information about your design, simulation, or debugging session.

Main Window Menu Bar

The main window menu bar is dynamic based on which window is selected, resulting in some
menu items changing name or becoming unavailable (greyed out). This section describes the
menu items at the highest-possible level.

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Navigating in the Main Window

File Menu
Table 2-7. File Menu — Item Description
Menu Item Description
New • Folder — create a new folder in the current directory
• Source — create a new VHDL, Verilog or other source file
• Project — create a new project
• Library — create a new library and mapping
•
Open Open a file of any type.
Load Load and run a macro file (.do or .tcl)
Close Close an opened file
Import • Library — import FPGA libraries
• EVCD — import an extended VCD file previously created
with the ModelSim Waveform Editor. This item is enabled
only when a Wave window is active
• Memory Data — initialize a memory by reloading a
previously saved memory file.
• Column Layout — apply a previously saved column layout
to the active window
•
Export • Waveform — export a created waveform
• Tabular list — writes List window data to a file in tabular
format
• Event list — writes List window data to a file as a series of
transitions that occurred during simulation
• TSSI list — writes List window data to a file in TSSI
format
• Image — saves an image of the active window
• Memory Data — saves data from the selected memory in
the Memory List window or an active Memory Data
window to a text file
• Column Layout — saves a column layout from the active
window
•
• HTML — opens up a dialog where you can specify the
name of an HMTL file and the directory where it is saved
Save These menu items change based on the active window.
Save as
Report Produce a textual report based on the active window
Change Directory Opens a browser for you to change your current directory. Not
available during a simulation, or if you have a dataset open.

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Navigating in the Main Window

Table 2-7. File Menu — Item Description (cont.)

Menu Item Description
Use Source Specifies an alternative file to use for the current source file.
This mapping only exists for the current simulation. This
option is only available from the Structure window.
Source Directory Control which directories are searched for source files.
Datasets Manage datasets for the current session.
Environment Set up how different windows should be updated, by dataset,
process, and/or context. This is only available when the
Structure, Locals, Processes, and Objects windows are active.
Page Setup Manage the printing of information from the selected window.
Print
Print Postscript
Recent Directories Display a list of recently opened working directories
Recent Projects Display a list of recently opened projects
Close Window Close the active window
Quit Quit the application

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Edit Menu
Table 2-8. Edit Menu — Item Description
Menu Item Description
Undo Alter your previous edit in a Source window.
Redo
Cut Use or remove selected text.
Copy
Paste
Delete Remove an object from the Wave and List windows
Clear Clear the Transcript window
Select All Change the selection of items in a window
Unselect All
Expand Expand or collapse hierarchy information
Goto Goto a specific line number in the Source window
Find Open the find toolbar. Refer to the section “Using the Find and
Filter Functions” for more information
Replace Find and replace text in a Source window.
Signal Search Search the Wave or List windows for a specified value, or the
next transition for the selected object
Find in Files search for text in saved files
Previous Coverage Miss Find the previous or next line with missed coverage in the
Next Coverage Miss active Source window

View Menu
Table 2-9. View Menu — Item Description
Menu Item Description
window name Displays the selected window
New Window Open additional instances of the Wave, List, or Dataflow
windows
Sort Change the sort order of the Wave window
Filter Filters information from the Objects and Structure windows.
Justify Change the alignment of data in the selected window.
Properties Displays file property information from the Files or Source
windows.

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Compile Menu
Table 2-10. Compile Menu — Item Description
Menu Item Description
Compile Compile source files
Compile Options Set various compile options.
Compile All Compile all files in the open project. Disabled if you don’t
have a project open
Compile Selected Compile the files selected in the project tab. Disabled if you
don’t have a project open
Compile Order Set the compile order of the files in the open project. Disabled
if you don’t have a project open
Compile Report report on the compilation history of the selected file(s) in the
project. Disabled if you don’t have a project open
Compile Summary report on the compilation history of all files in the project.
Disabled if you don’t have a project open

Simulate menu
Table 2-11. Simulate Menu — Item Description
Menu item Description
Design Optimization Open the Design Optimization dialog to configure simulation
optimizations
Start Simulation Load the selected design unit
Runtime Options Set various simulation runtime options
Run • Run <default> — run simulation for one default run length;
change the run length with Simulate > Runtime Options,
or use the Run Length text box on the toolbar
• Run -All — run simulation until you stop it
• Continue — continue the simulation
• Run -Next — run to the next event time
• Step — single-step the simulator
• Step -Over — execute without single-stepping through a
subprogram call
• Restart — reload the design elements and reset the
simulation time to zero; only design elements that have
changed are reloaded; you specify whether to maintain
various objects (logged signals, breakpoints, etc.)
Break Stop the current simulation run
End Simulation Quit the current simulation run

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Add Menu
Table 2-12. Add Menu — Item Description
Menu Item Description
To Wave Add information to the Wave window
To List Add information to the List window
To Log Add information to the Log file
To Dataflow Add information to the Dataflow window
Window Pane Add an additional pane to the Wave window. You can remove
this pane by selecting Wave > Delete Window Pane.

Tools Menu
Table 2-13. Tools Menu — Item Description
Menu Item Description
Breakpoints Manage breakpoints
Trace Perform signal trace actions.
Dataset Snapshot Enable periodic saving of simulation data to a .wlf file.
Tcl Execute or debug a Tcl macro.
Wildcard Filter Refer to the section “Using the WildcardFilter Preference
Variable” for more information
Edit Preferences Set GUI preference variables. Refer to the section “Simulator
GUI Preferences” for more information.

Layout Menu
Table 2-14. Layout Menu — Item Description
Menu Item Description
Reset Reset the GUI to the default appearance for the selected layout.
Save Layout As Save your reorganized view to a custom layout. Refer to the
section “Customizing the Simulator GUI Layout” for more
information.
Configure Configure the layout-specific behavior of the GUI. Refer to the
section “Configure Window Layouts Dialog Box” for more
information.
Delete Delete a customized layout. You can not delete any of the five
standard layouts.

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Table 2-14. Layout Menu — Item Description (cont.)

Menu Item Description
layout name Select a standard or customized layout.

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Bookmarks Menu
Table 2-15. Bookmarks Menu — Item Description
Menu Item Description
Add Clicking this button bookmarks the current view of the Wave
window.
Add Custom Opens the New Bookmark dialog box.
Manage Opens the Manage Bookmarks dialog box.
Delete All • Active Window Only
• All Windows.
Reload from File • Active Window Only
• All Windows.

Window Menu
Table 2-16. Window Menu — Item Description
Menu Item Description
Cascade Arrange all undocked windows. These options do not impact
Tile Horizontally any docked windows.
Tile Vertically
Icon Children Minimize (Icon) or Maximize (Deicon) undocked windows.
Icon All These options do not impact any docked windows.
Deicon All
Show Toolbar Toggle the appearance of the Toolbar frame of the Main
window
Show Window Headers Toggle the appearance of the window headers. Note that you
will be unable to rearrange windows if you do not show the
window headers.
FocusFollowsMouse Mouse pointer makes window active when pointer hovers in
the window briefly. Refer to Navigating in the Main
Windowfor more information.
Toolbars Toggle the appearance of available toolbars. Similar behavior
to right-clicking in the toolbar frame.
window name Make the selected window active.
Windows Display the Windows dialog box, which allows you to activate,
close or undock the selected window(s).

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Help Menu
Table 2-17. Help Menu — Item Description
Menu Item Description
About Display ModelSim application information.
Release Notes Display the current Release Notes in the ModelSim Notepad
editor. You can find past release notes in the
<install_dir>/docs/rlsnotes/ directory.
Welcome Window Display the Important Information splash screen. By default
this window is displayed on startup. You can disable the
automatic display by toggling the Don’t show this dialog
again radio button.
Command Completion Toggles the command completion dropdown box in the
transcript window.
When you start typing a command at the Transcript prompt, a
dropdown box appears which lists the available commands
matching what has been typed so far. You may use the Up and
Down arrow keys or the mouse to select the desired command.
When a unique command has been entered, the command
usage is presented in the drop down box.
Register File Types Associate files types (such as .v, .sv, .vhd, .do) with the
product. These associations are typically made upon install, but
this option allows you to update your system in case changes
have been made since installation.
ModelSim Open the HTML-based portal for all PDF and HTML
Documentation - documentation.
InfoHub
ModelSim Open the PDF-based portal for the most commonly used PDF
Documentation - PDF documents.
Bookcase
Tcl Help Open the Tcl command reference (man pages) in Windows
help format.
Tcl Syntax Open the Tcl syntax documentation in your web browser.
Tcl Man pages Open the Tcl/Tk manual in your web browser.
Technotes Open a technical note in the ModelSim Notepad editor.

Main Window Toolbar

The Main window contains a toolbar frame that displays context-specific toolbars. The
following sections describe the toolbars and their associated buttons.

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• Bookmarks Toolbar
• Compile Toolbar
• Coverage Toolbar
• Dataflow Toolbar
• FSM Toolbar
• Help Toolbar
• Layout Toolbar
• Memory Toolbar
• Mode Toolbar
• Objectfilter Toolbar
• Process Toolbar
• Profile Toolbar
• Schematic Toolbar
• Simulate Toolbar
• Source Toolbar
• Standard Toolbar
• Step Toolbar
• Wave Compare Toolbar
• Wave Cursor Toolbar
• Wave Edit Toolbar
• Wave Expand Time Toolbar
• Wave Toolbar
• Zoom Toolbar

Bookmarks Toolbar
The Bookmark toolbar allows you to manage your bookmarks of the Wave window

Figure 2-25. Bookmarks Toolbar

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Table 2-18. Bookmarks Toolbar Buttons

Button Name Shortcuts Description
Add Command Wave window Clicking this button
Bookmark only: bookmark add wave bookmarks the current view of
Menu Wave window only: the active window.
Add > To Wave >
Bookmark Click and hold the button to
open a drop down menu with
the following options:
• Add Current View
• Add Custom ...
• Set Default Action
Delete All CommandWave window Removes all bookmarks, after
Bookmarks only: bookmark delete wave prompting for your
-all confirmation.

Click and hold the button to

open a drop down menu with
the following options:
• Active Window
• All Windows
Manage None Displays the Manage
Bookmarks Bookmarks dialog box.

Reload from None Reloads bookmarks from the

File [Link] file.
• Set Default Action
Jump to CommandWave window Displays bookmarks grouped
Bookmark only: bookmark goto wave by window. Select the
<name> bookmark you want to display.

Compile Toolbar
The Compile toolbar provides access to compile and simulation actions.

Figure 2-26. Compile Toolbar

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Table 2-19. Compile Toolbar Buttons

Button Name Shortcuts Description
Compile Command: vcom or vlog Opens the Compile Source
Menu: Compile > Compile Files dialog box.

Compile All Command: vcom or vlog Compiles all files in the open
Menu: Compile > Compile project.
all
Simulate Command: vsim Opens the Start Simulation
Menu: Simulate > Start dialog box.
Simulation
Break Menu: Simulate > Break Stop a compilation,
Hotkey: Break elaboration, or the current
simulation run.

Coverage Toolbar
The Coverage toolbar provides tools for filtering code coverage data in the Structure and
Instance Coverage windows.

Figure 2-27. Coverage Toolbar

Table 2-20. Coverage Toolbar Buttons

Button Name Shortcuts Description
Enable None Enables display filtering of
Filtering coverage statistics in the
Structure and Instance
Coverage windows.
Threshold None Displays all coverage statistics
Above above the Filter Threshold for
selected columns.
Threshold None Displays all coverage statistics
Below below the Filter Threshold for
selected columns
Filter None Specifies the display coverage
Threshold percentage for the selected
coverage columns

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Table 2-20. Coverage Toolbar Buttons (cont.)

Button Name Shortcuts Description
Statement None Applies the display filter to all
Statement coverage columns in
the Structure and Instance
Coverage windows.
Branch None Applies the display filter to all
Branch coverage columns in
the Structure and Instance
Coverage windows.
Condition None Applies the display filter to all
Condition coverage columns in
the Structure and Instance
Coverage windows.
Expression None Applies the display filter to all
Expression coverage columns
in the Structure and Instance
Coverage windows.
Toggle None Applies the display filter to all
Toggle coverage columns in
the Structure and Instance
Coverage windows.

Dataflow Toolbar
The Dataflow toolbar provides access to various tools to use in the Dataflow window.

Figure 2-28. Dataflow Toolbar

Table 2-21. Dataflow Toolbar Buttons

Button Name Shortcuts Description
Trace Input Menu: Tools > Trace > Move the next event cursor to
Net to Event Trace next event the next input event driving the
selected output.
Trace Set Menu: Tools > Trace > Jump to the source of the
Trace event set selected input event.

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Table 2-21. Dataflow Toolbar Buttons (cont.)

Button Name Shortcuts Description
Trace Reset Menu: Tools > Trace > Return the next event cursor to
Trace event reset the selected output.

Trace Net to Menu: Tools > Trace > Step back to the last driver of
Driver of X TraceX an unknown value.

Expand Net None Display driver(s) of the

to all Drivers selected signal, net, or register.

Expand Net None Display driver(s) and reader(s)

to all Drivers of the selected signal, net, or
and Readers register.
Expand Net None Display reader(s) of the
to all Readers selected signal, net, or register.

Show Wave Menu: Dataflow > Display the embedded wave

Show Wave viewer pane.

FSM Toolbar
The FSM toolbar provides access to tools that control the information displayed in the FSM
Viewer window.

Figure 2-29. FSM Toolbar

Table 2-22. FSM Toolbar Buttons

Button Name Shortcuts Description
Show State Menu: FSM View > Show (only available when
Counts State Counts simulating with -coverage)
Displays the coverage count
over each state.
Show Menu: FSM View > Show (only available when
Transition Transition Counts simulating with -coverage)
Counts Displays the coverage count
for each transition.

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Table 2-22. FSM Toolbar Buttons (cont.)

Button Name Shortcuts Description
Show Menu: FSM View > Show Displays the conditions of each
Transition Transition Conditions transition.
Conditions
Track Wave Menu: FSM View > Track The FSM Viewer tracks your
Cursor Wave Cursor current cursor location.

Enable Info Menu: FSM View > Enable Displays information when
Mode Popups Info Mode Popups you mouse over each state or
transition
Previous None Steps to the previous state in
State the FSM Viewer window.

Next State None Steps to the next state in the

FSM Viewer window.

Help Toolbar
The Help toolbar provides a way for you to search the HTML documentation for a specified
string. The HTML documentation will be displayed in a web browser.

Figure 2-30. Help Toolbar

Table 2-23. Help Toolbar Buttons

Button Name Shortcuts Description
Search None A text entry box for your
Documentation search string.
Search Hotkey: Enter Activates the search for the
Documentation term you entered into the text
entry box.

Layout Toolbar
The Layout toolbar allows you to select a predefined or user-defined layout of the graphical
user interface. Refer to the section “Customizing the Simulator GUI Layout” for more
information.

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Figure 2-31. Layout Toolbar

Table 2-24. Layout Toolbar Buttons

Button Name Shortcuts Description
Change Menu: Layout > A dropdown box that allows
Layout <layoutName> you to select a GUI layout.
• NoDesign
• Simulate
• Coverage
• VMgmt

Memory Toolbar
The Memory toolbar provides access to common functions.

Figure 2-32. Memory Toolbar

Table 2-25. Memory Toolbar Buttons

Button Name Shortcuts Description
Split Screen Menu: Memory > Splits the memory window.
Split Screen

Goto Address Highlights the first element of

the specified address.

Mode Toolbar
The Mode toolbar provides access to tools for controlling the mode of mouse navigation.

Figure 2-33. Mode Toolbar

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Table 2-26. Mode Toolbar Buttons

Button Name Shortcuts Description
Select Mode Menu: Dataflow > Set the left mouse button to
Mouse Mode > Select Mode select mode and middle mouse
button to zoom mode.
Zoom Mode Menu: Dataflow > Set left mouse button to zoom
Mouse Mode > Zoom Mode mode and middle mouse
button to pan mode.
Pan Mode Menu: Dataflow > Set left mouse button to pan
Mouse Mode > Pan Mode mode and middle mouse
button to zoom mode.
Edit Mode Menu: Wave or Dataflow > Set mouse to Edit Mode,
Mouse Mode > Edit Mode where you drag the left mouse
button to select a range and
drag the middle mouse button
to zoom.
Stop None Halt any drawing currently
Drawing happening in the window.

Objectfilter Toolbar
The Objectfilter toolbar provides filtering of design objects appearing in the Objects window.

Figure 2-34. Objectfilter Toolbar

Table 2-27. Objectfilter Toolbar Buttons

Button Name Shortcuts Description
View Inputs None Changes the view of the Objects Window
Only to show inputs.

View None Changes the view of the Objects Window

Outputs Only to show outputs.

View Inouts None Changes the view of the Objects Window

Only to show inouts.

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Table 2-27. Objectfilter Toolbar Buttons (cont.)

Button Name Shortcuts Description
Vies Internal None Changes the view of the Objects Window
Signals to show Internal Signals.

Reset All None Clears the filtering of Objects Window

Filters entries and displays all objects.

Change Filter None Opens the Filter Objects dialog box.

Process Toolbar
The Process toolbar contains three toggle buttons (only one can be active at any time) that
controls the view of the Process window.

Figure 2-35. Process Toolbar

Table 2-28. Process Toolbar Buttons

Button Name Shortcuts Description
View Active Menu: Process > Active Changes the view of the
Processes Processes Window to only
show active processes.
View Menu: Process > In Region Changes the view of the
Processes in Processes window to only
Region show processes in the active
region.
View Menu: Process > Design Changes the view of the
Processes for Processes window to show
the Design processes in the design.
View Process Menu: Process > Hierarchy Changes the view of the
hierarchy Processes window to show
process hierarchy.

Profile Toolbar
The Profile toolbar provides access to tools related to the profiling windows (Ranked, Calltree,
Design Unit, and Structural.

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Figure 2-36. Profile Toolbar

Table 2-29. Profile Toolbar Buttons

Button Name Shortcuts Description
Collapse Menu: Tools > Profile > Toggle the reporting for
Sections Collapse Sections collapsed processes and
functions.
Profile None Display performance and
Cutoff memory profile data equal to
or greater than set percentage.
Refresh None Refresh profile performance
Profile Data and memory data after
changing profile cutoff.
Save Profile Menu: Tools > Profile > Save profile data to output file
Results Profile Report (prompts for file name).

Schematic Toolbar
The Schematic toolbar provides access to tools for manipulating highlights and signals in the
Dataflow and Schematic windows.

Figure 2-37. Schematic Toolbar

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Table 2-30. Schematic Toolbar Buttons

Button Name Shortcuts Description
Remove All Menu: Dataflow > Clear the green highlighting
Highlights Remove Highlight identifying the path you’ve
or traversed through the design.
Schematic > Edit > Remove
Highlight Click and hold the button to
open a drop down menu with
the following options:
• Remove All Highlights
• Remove Selected
Highlights
• Set Default Action
Delete Menu: Delete the selected signal.
Content Dataflow > Delete
or Click and hold the button to
Schematic > Edit > Delete open a drop down menu with
Schematic > Edit > Delete the following options:
All • Delete Selected
• Delete All
• Set Default Action
Regenerate Menu: Dataflow > Clear and redraw the display
Regenerate using an optimal layout.
or
Schematic > Edit >
Regenerate

Simulate Toolbar
The Simulate toolbar provides various tools for controlling your active simulation.

Figure 2-38. Simulate Toolbar

Table 2-31. Simulate Toolbar Buttons

Button Name Shortcuts Description
Source None Toggles display of hyperlinks
Hyperlinking in design source files.

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Table 2-31. Simulate Toolbar Buttons (cont.)

Button Name Shortcuts Description
Environment Command: env .. Changes your environment up
Up Menu: File > Environment one level of hierarchy.

Environment Command: env -back Change your environment to

Back Menu: File > Environment its previous location.

Environment Command: env -forward Change your environment

Forward Menu: File > Environment forward to a previously
selected environment.
Restart Command: restart Reload the design elements
Menu: Simulate > Run > and reset the simulation time to
Restart zero, with the option of
maintaining various settings
and objects.
Run Length Command: run Specify the run length for the
Menu: Simulate > current simulation.
Runtime Options
Run Command: run Run the current simulation for
Menu: Simulate > Run > the specified run length.
Run default_run_length
Continue Command: run Continue the current
Run -continue simulation run until the end of
Menu: Simulate > Run > the specified run length or until
Continue it hits a breakpoint or specified
break event.
Run All Command: run -all Run the current simulation
Menu: Simulate > Run > forever, or until it hits a
Run -All breakpoint or specified break
event.
Break Menu: Simulate > Break Immediate stop of a
Hotkey: Break compilation, elaboration, or
simulation run. Similar to
hitting a breakpoint if the
simulator is in the middle of a
process.
Stop -sync None Stop simulation the next time
time/delta is advanced.
Performance Menu: Tools > Profile > Enable collection of statistical
Profiling Performance performance data.

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Table 2-31. Simulate Toolbar Buttons (cont.)

Button Name Shortcuts Description
Memory Menu: Tools > Profile > Enable collection of memory
Profiling Memory usage data.

Edit Menu: Tools > Breakpoint Enable breakpoint editing,

Breakpoints loading, and saving.

Source Toolbar
The Source toolbar allows you to perform several activities on Source windows.

Figure 2-39. Source Toolbar

Table 2-32. Source Toolbar Buttons

Button Name Shortcuts Description
Previous None Jump to previous line with
Zero Hits zero coverage.

Next Zero None Jump to next line with zero

Hits coverage.

Show Menu: Source > Display language templates in

Language Show Language Templates the left hand side of every open
Templates source file.

Clear Menu: Source > Removes any bookmarks in

Bookmarks Clear Bookmarks the active source file.

Standard Toolbar
The Standard toolbar contains common buttons that apply to most windows.

Figure 2-40. Standard Toolbar

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Table 2-33. Standard Toolbar Buttons

Button Name Shortcuts Description
New File Menu: File > New > Source Opens a new Source text file.
The icon changes to reflect the
default file type set with the
Set Default Action menu pick
from the dropdown menu.

Click and hold the button to

open a dropdown menu with
the following options:
• VHDL
• Verilog
• SystemC
• SystemVerilog
• Do
• Other
• Set Default Action
Open Menu: File > Open Opens the Open File dialog

Save Menu: File > Save Saves the contents of the active
window or
Saves the current wave
window display and signal
preferences to a macro file
(DO fie).
Reload Command: Dataset Restart Reload the current dataset.
Menu: File > Datasets

Print Menu: File > Print Opens the Print dialog box.

Cut Menu: Edit > Cut

Hotkey: Ctrl+x

Copy Menu: Edit > Copy

Hotkey: Ctrl+c

Paste Menu: Edit > Paste

Hotkey: Ctrl+v

Undo Menu: Edit > Undo

Hotkey: Ctrl+z

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Table 2-33. Standard Toolbar Buttons (cont.)

Button Name Shortcuts Description
Redo Menu: Edit > Redo
Hotkey: Ctrl+y

Add Selected Menu: Add > to Wave Clicking adds selected objects
to Window Hotkey: Ctrl+w to the Wave window. Refer to
“Add Selected to Window
Button” for more information
about the dropdown menu
selections. 1
• Set Default Action
Find Menu: Edit > Find Opens the Find dialog box.
Hotkey: Ctrl+f (Windows)
or Ctrl+s (UNIX)
Collapse All Menu: Edit > Expand >
Collapse All

1. You can set the default insertion location in the Wave window from menus and hotkeys with the
PrefWave(InsertMode) preference variable.

Add Selected to Window Button

This button is available when you have selected an object in any of the following windows:
Dataflow, List, Locals, Memory, Objects, Process, Structure, Watch, and Wave windows.
Using a single click, the objects are added to the Wave window. However, if you click-and-hold
the button you can access additional options via a dropdown menu, as shown in Figure 2-41.

Figure 2-41. The Add Selected to Window Dropdown Menu

• Add to Wave (Anchor Location) — Adds selected signals tabove the Insertion Point Bar
in the Pathname Pane by default.

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• Add to Wave (Append Point) — Adds selected signals below the insertion pointer in the
Pathname Pane.
• Add to Wave (End) — Adds selected signals after the last signal in the Wave Window.
• Add to Wave (Top) — Adds selected signals above the first signal in the Wave window.
• Add to List — Adds selected objects to the List Window.
• Add to Dataflow — Adds selected objects to the Dataflow Window.
• Add to Watch — Adds selected objects to the Watch Window.
• Set Default Action — Selecting one of the items from the dropdown menu sets that item
as the default action when you click the Add Selected to Window button. The title of
the selection is shown in bold type in the Add Selected to Window dropdown menu and
two asterisks ( **) are placed after the title to indicate the current default action. For
example, Add to Wave (Anchor Location) is the default action in Figure 2-41.
• You can change the default

Step Toolbar
The Step toolbar allows you to step through your source code.

Figure 2-42. Step Toolbar

Table 2-34. Step Toolbar Buttons

Button Name Shortcuts Description
Step Into Command: step Step the current simulation to
Menu: Simulate > Run > the next statement.
Step
Step Over Command: step -over Execute HDL statements,
Menu: Simulate > Run > treating them as simple
Step -Over statements instead of entered
and traced line by line.
Step Out Command: step -out Step the current simulation out
of the current function or
procedure.

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Table 2-34. Step Toolbar Buttons (cont.)

Button Name Shortcuts Description
Step Into Command: step -inst <env> Step the current simulation
Current into an instance, process, or
thread.
• Into current
• Over current
• Out current
Step Over Command: step - over -inst Step the simulation over the
Current <env> current instance, process, or
thread.
Step Out Command: step -out -inst Step the simulation out of the
Current <env> currant instance, process, or
thread.

Wave Toolbar
The Wave toolbar allows you to perform specific actions in the Wave window.

Figure 2-43. Wave Toolbar

Table 2-35. Wave Toolbar Buttons

Button Name Shortcuts Description
Show Drivers None Display driver(s) of the
selected signal, net, or
register in the Dataflow and
Source windows.

Display drivers only in the

Show Drivers Source window
(source only)
The source window is not
shown if there are no
drivers.

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Table 2-35. Wave Toolbar Buttons (cont.)

Button Name Shortcuts Description
Show Readers None Display reader(s) of the
selected signal, net, or
register in the Dataflow
window.

Show Readers Display drivers only in the

(source only) Source window

The source window is not

shown if there are no
readers.
Add Menu: Add > To Wave Creates a group labeled
Contributing > Contributing Signals Contributors: <name>,
Signals where <name> is the name
of the currently selected
signal. This group contains
the inputs to the process
driving <name>.
Wave Search Click on the box when in Text-entry box for the search
Box transition mode (Falling string. Dropdown button
Edge, Rising Edge, or displays previous search
Any Transition) to cycle strings. Long search times
through these options. result in the display of a stop
icon you can use to cancel
the search.
Search Previous: Shift+Enter Searches for the next
Previous/Next Next: enter occurrence of the string,
either backward or forward
in time, from the cursor.
Search Dropdown button to:
Options • Change Mode: value,
rising edge, falling edge,
or any transition.
• Display the Wave Signal
Search Dialog Box for
advanced search
behavior.
• Clear the value history.
Using the Wave Search Box
You can use the Wave Search box to search the timeline of a selected signal for transitions to a
specific value, or just for transitions themselves.

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1. Select a signal in the left-hand side of the Wave window.

2. Place a wave cursor where you want to begin the search.
3. Enter a value in the Wave Search box. The value must be of a compatible format type
for the signal you selected.
Alternatively you can use the Search Options button to change the mode from “value” to
Rising Edge, Falling Edge, or Any Transition. This populates the Wave Search box with
the selected transition type.
4. Use the Search Previous or Search Next buttons to locate the next occurrence of the
value (or transition).
For large simulations, if the search takes a long time, the Wave Search box will display
a stop icon you can click to stop the search.

Wave Compare Toolbar

The Wave Compare toolbar allows you to quickly find differences in a waveform comparison.

Figure 2-44. Wave Compare Toolbar

Table 2-36. Wave Compare Toolbar Buttons

Button Name Shortcuts Description
Find First None Find the first difference in a
Difference waveform comparison

Find None Find the previous annotated

Previous difference in a waveform
Annotated comparison
Difference
Find None Find the previous difference in
Previous a waveform comparison
Difference
Find Next None Find the next difference in a
Difference waveform comparison

Find Next None Find the next annotated

Annotated difference in a waveform
Difference comparison

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Graphical User Interface
Navigating in the Main Window

Table 2-36. Wave Compare Toolbar Buttons (cont.)

Button Name Shortcuts Description
Find Last None Find the last difference in a
Difference waveform comparison

Wave Cursor Toolbar

The Wave Cursor toolbar provides various tools for manipulating cursors in the Wave window.

Figure 2-45. Wave Cursor Toolbar

Table 2-37. Wave Cursor Toolbar Buttons

Button Name Shortcuts Description
Insert Cursor None Adds a new cursor to the active
Wave window.

Delete Menu: Wave > Deletes the active cursor.

Cursor Delete Cursor

Find Menu: Edit > Signal Search Moves the active cursor to the
Previous Hotkey: Shift + Tab previous signal value change
Transition for the selected signal.
Find Next Menu: Edit > Signal Search Moves the active cursor to the
Transition Hotkey: Tab next signal value change for
the selected signal.
Find Menu: Edit > Signal Search Moves the active cursor to the
Previous previous falling edge for the
Falling Edge selected signal.
Find Next Menu: Edit > Signal Search Moves the active cursor to the
Falling Edge next falling edge for the
selected signal.
Find Menu: Edit > Signal Search Moves the active cursor to the
Previous previous rising edge for the
Rising Edge selected signal.
Find Next Menu: Edit > Signal Search Moves the active cursor to the
Rising Edge next rising edge for the
selected signal.

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Navigating in the Main Window

Wave Edit Toolbar

The Wave Edit toolbar provides easy access to tools for modifying an editable wave.

Figure 2-46. Wave Edit Toolbar

Table 2-38. Wave Edit Toolbar Buttons

Button Name Shortcuts Description
Insert Pulse Menu: Wave > Insert a transition at the
Wave Editor > Insert Pulse selected time.
Command: wave edit
insert_pulse
Delete Edge Menu: Wave > Delete the selected transition.
Wave Editor > Delete Edge
Command: wave edit delete
Invert Menu: Wave > Invert the selected section of
Wave Editor > Invert the waveform.
Command: wave edit invert
Mirror Menu: Wave > Mirror the selected section of
Wave Editor > Mirror the waveform.
Command: wave edit mirror
Change Menu: Wave > Change the value of the
Value Wave Editor > Value selected section of the
Command: wave edit waveform.
change_value
Stretch Edge Menu: Wave > Move the selected edge by
Wave Editor > Stretch Edge increasing/decreasing
Command: wave edit stretch waveform duration.
Move Edge Menu: Wave > Move the selected edge
Wave Editor > Move Edge without increasing/decreasing
Command: wave edit move waveform duration.
Extend All Menu: Wave > Increase the duration of all
Waves Wave Editor > editable waves.
Extend All Waves
Command: wave edit extend

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Graphical User Interface
Navigating in the Main Window

Wave Expand Time Toolbar

The Wave Expand Time toolbar provides access to enabling and controlling wave expansion
features.

Figure 2-47. Wave Expand Time Toolbar

Table 2-39. Wave Expand Time Toolbar Buttons

Button Name Shortcuts Description
Expanded Menu: Wave > Expanded turns off the expanded time
Time Off Time > Off display (default mode)

Expanded Menu: Wave > Expanded displays delta time steps

Time Deltas Time > Deltas Mode
Mode
Expanded Menu: Wave > Expanded displays event time steps
Time Events Time > Events Mode
Mode
Expand All Menu: Wave > Expanded expands simulation time over
Time Time > Expand All the entire simulation time
range, from 0 to current time
Expand Time Menu: Wave > Expanded expands simulation time at the
at Active Time > Expand Cursor simulation time of the active
Cursor cursor
Collapse All Menu: Wave > Expanded collapses simulation time over
Time Time > Collapse All entire simulation time range

Collapse Menu: Wave > Expanded collapses simulation time at

Time at Time > Collapse Cursor the simulation time of the
Active active cursor
Cursor

Zoom Toolbar
The Zoom toolbar allows you to change the view of the Wave window.

Figure 2-48. Zoom Toolbar

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Call Stack Window

Table 2-40. Zoom Toolbar Buttons

Button Name Shortcuts Description
Zoom In Menu: Wave > Zoom > Zooms in by a factor of 2x
Zoom In
Hotkey: i, I, or +
Zoom Out Menu: Wave > Zoom > Zooms out by a factor of 2x
Zoom Out
Hotkey: o, O, or -
Zoom Full Menu: Wave > Zoom > Zooms to show the full length
Zoom Full of the simulation.
Hotkey: f or F
Zoom in Menu: Wave > Zoom > Zooms in by a factor of 2x,
on Active Zoom Cursor centered on the active cursor
Cursor Hotkey: c or C
Zoom Other Changes the view in additional
Window instances of the Wave window
to match the view of the active
Wave window.

Call Stack Window

The Call Stack window displays the current call stack when:

• you single step the simulation.

• the simulation has encountered a breakpoint.
• you select any process in either the Structure or Processes windows.
When debugging your design you can use the call stack data to analyze the depth of function
calls that led up to the current point of the simulation, which include:

• Verilog functions and tasks

• VHDL functions and procedures
• SystemC methods and threads
• C/C++ functions
Accessing
View > Call Stack

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Graphical User Interface
Call Stack Window

Figure 2-49. Call Stack Window

Call Stack Window Tasks

This window allows you to perform the following actions:

• Double-click on the line of any function call:

o Displays the local variables at that level in the Locals Window.
o Displays the corresponding source code in the Source Window.

Related Commands of the Call Stack Window

Table 2-41. Commands Related to the Call Stack Window

Command Name Description
stack down this command moves down the call stack.
stack frame this command selects the specified call frame.
stack level this command reports the current call frame number.
stack tb this command is an alias for the tb command.
stack up this command moves up the call stack.

GUI Elements of the Call Stack Window

This section describes GUI elements specific to this Window.

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Class Graph Window

Column Descriptions

Table 2-42. Call Stack Window Columns

Column Title Description
# indicates the depth of the function call, with the most recent
at the top.
In indicates the function. If you see “unknown” in this column,
you have most likely optimized the design such that the
information is not available during the simulation.
Line indicates the line number containing the function call.
File indicates the location of the file containing the function call.
Address indicates the address of the execution in a foreign
subprogram, such as C.

Class Graph Window

The Class Graph window provides a graphical view of your SystemVerilog classes, including
any extensions of other classes and related methods and properties.

Accessing
• Menu item: View > Class Browser > Class Graph
• Command: view classgraph

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Graphical User Interface
Class Graph Window

Figure 2-50. Class Graph Window

Class Graph Window Tasks

This section describes tasks for using the Cover Directives window.

Navigating in the Class Graph Window

You can change the view of the Class Graph window with your mouse or the arrow keys on
your keyboard.

• Left click-drag — allows you to move the contents around in the window.
• Middle Mouse scroll — zooms in and out.
• Middle mouse button strokes:
o Upper left — zoom full
o Upper right — zoom out. The length of the stroke changes the zoom factor.

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Class Instances Window

o Lower right — zoom area.

• Arrow Keys — scrolls the window in the specified direction.
o Unmodified — scrolls by a small amount.
o Ctrl+<arrow key> — scrolls by a larger amount
o Shift+<arrow key> — shifts the view to the edge of the display

GUI Elements of the Class Graph Window

This section describes the GUI elements specific to the Class Graph window.

Popup Menu Items

Table 2-43. Class Graph Window Popup Menu

Popup Menu Item Description
Filter Controls the display of methods and properties from
the class boxes.
Zoom Full
View Entire Design Reloads the view to show the class hierarchy of the
complete design.
Print to Postscript
Organize by Base/Extended Class reorganizes the window so that the base or extended
(default) classes are at the top of the hierarchy.

Class Instances Window

The Class Instances window shows the list of class instances and their values for a particular
selected class type. You may add the class items directly to the wave or list windows, log them,
or get other information about them.

Accessing
• Menu item: View > Class Browser > Class Instances
• Command: view classinstances

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Graphical User Interface
Class Instances Window

Figure 2-51. Class Instances Window

Viewing Class Instances

The Class Instances window is dynamically populated by selecting SVClasses in the Structure
(sim) window. All currently active instances of the selected class are displayed in the Class
Instances window. Class instances that have not yet come into existence or have been destroyed
are not displayed.

Once you have chosen the class type you want to observe, you can fix that instance in the
window while you debug by selecting File > Environment > Fix to Current Context.

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Class Tree Window

Class Naming Format

Class instance names are formatted as follows: @<class_type>@<nnn> where
@<class_type>@ is the name of the class type and <n> is the reference identifier for a
particular instance of the class type. For example, @uvm_queue_3@14 is the 14th instance of
the class uvm_queue_3.

GUI Elements of the Class Instances Window

This section describes the GUI elements specific to the Class Instances window.

Popup Menu Items

Table 2-44. Class Instances Window Popup Menu

Popup Menu Item Description
View Declaration Highlights the line of code where the type of the
instance is declared, opening the source file if
necessary.
Add Wave Adds the selected class instance to the Wave window.
Add to Allows you to log the selected class instance, or add it
to the Wave or List windows.

Class Tree Window

The Class Tree window provides a hierarchical view of your SystemVerilog classes, including
any extensions of other classes, related methods and properties, as well as any covergroups.

Figure 2-52. Class Tree Window

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Graphical User Interface
Class Tree Window

Accessing
• Select View > Class Browser > Class Tree
• Use the command:
view classtree

GUI Elements of the Class Tree Window

This section describes the GUI elements specific to the Class Tree window.

Icons

Table 2-45. Class Tree Window Icons

Icon Description
Class

Parameterized Class

Function

Task

Variable

Virtual Interface

Covergroup

Structure

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Dataflow Window

Column Descriptions

Table 2-46. Class Tree Window Columns

Column Description
Class The name of the item
Type The type of item
File The source location of the item
Unique Id The internal name of the parameterized class
(only available with parameterized classes)
Scope The scope of the covergroup
(only available with covergroups

Popup Menu Items

Table 2-47. Class Tree Window Popup Menu

Popup Menu Item Description
View Declaration Highlights the line of code where the item is declared,
opening the source file if necessary.
View as Graph Displays the class and any dependent classes in the
Class Graph window.
(only available for classes)
Filter allows you to filter out methods and or properties
Organize by Base/Extended Class reorganizes the window so that the base or extended
(default) classes are at the top of the hierarchy.

Dataflow Window
Use this window to explore the "physical" connectivity of your design. You can also use it to
trace events that propagate through the design; and to identify the cause of unexpected outputs.

The Dataflow window displays:

• processes
• signals, nets, and registers
The window has built-in mappings for all Verilog primitive gates (that is, AND, OR, PMOS,
NMOS, and so forth.). For components other than Verilog primitives, you can define a mapping
between processes and built-in symbols. See Symbol Mapping for details.

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Graphical User Interface
Dataflow Window

Note
This version of ModelSim has limited Dataflow functionality resulting in many of the
features described in this chapter operating differently. The window will show only one
process and its attached signals or one signal and its attached processes, as displayed in
Figure 2-53.

Accessing
Access the window using either of the following:

• Menu item: View > Dataflow

• Command: view dataflow

Figure 2-53. Dataflow Window - ModelSim

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Dataflow Window

Figure 2-54. Dataflow Window

Dataflow Window Tasks

This section describes tasks for using the Dataflow window.

You can interact with the Dataflow in one of three different Mouse modes, which you can
change through the DataFlow menu or the Zoom Toolbar:

• Select Mode — your left mouse button is used for selecting objects and your middle
mouse button is used for zooming the window. This is the default mode.
• Zoom Mode — your left mouse button is used for zooming the window and your middle
mouse button is used for panning the window.
• Pan Mode — your left mouse button is used for panning the window and your middle
mouse button is used for zooming the window.

Selecting Objects in the Dataflow Window

When you select an object, or objects, it will be highlighted an orange color.

• Select a single object — Single click.

• Select multiple objects — Shift-click on all objects you want to select or click and drag
around all objects in a defined area. Only available in Select Mode.

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Graphical User Interface
Dataflow Window

Zooming the View of the Dataflow Window

Several zoom controls are available for changing the view of the Dataflow window, including
mouse strokes, toolbar icons and a mouse scroll wheel.

• Zoom Full — Fills the Dataflow window with all visible data.
o Mouse stroke — Up/Left. Middle mouse button in Select and Pan mode, Left mouse
button in Zoom mode.
o Menu — DataFlow > Zoom Full
o Zoom Toolbar — Zoom Full
• Zoom Out
o Mouse stroke — Up/Right. Middle mouse button in Select and Pan mode, Left
mouse button in Zoom mode.
o Menu — DataFlow > Zoom Out
o Zoom Toolbar — Zoom Out
o Mouse Scroll — Push forward on the scroll wheel.
• Zoom In
o Menu — DataFlow > Zoom In
o Zoom Toolbar — Zoom In
o Mouse Scroll — Pull back on the scroll wheel.
• Zoom Area — Fills the Dataflow window with the data within the bounding box.
o Mouse stroke — Down/Right
• Zoom Selected — Fills the Dataflow window so that all selected objects are visible.
o Mouse stroke — Down/Left

Panning the View of the Dataflow Window

You can pan the view of the Dataflow window with the mouse or keyboard.

• Pan with the Mouse — In Zoom mode, pan with the middle mouse button. In Pan mode,
pan with the left mouse button. In Select mode, pan with the Ctrl key and the middle
mouse button.
• Pan with the Keyboard — Use the arrow keys to pan the view. Shift+<arrow key> pans
to the far edge of the view. Ctrl+<arrow key> pans by a moderate amount.

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Dataflow Window

Displaying the Wave Viewer Pane

You can embed a miniature wave viewer in the Dataflow window (Figure 2-55.

1. Select the DataFlow > Show Wave menu item.

2. Select a process in the Dataflow pane to populate the Wave pane with signal
information.
Refer to the section “Exploring Designs with the Embedded Wave Viewer” for more
information.

Figure 2-55. Dataflow Window and Panes

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Graphical User Interface
Files Window

Files Window
Use this window to display the source files and their locations for the loaded simulation.

Prerequisites
You must have executed the vsim command before this window will contain any information
about your simulation environment.

Accessing
Access the window using either of the following:

• Menu item: View > Files

• Command: view files

Figure 2-56. Files Window

GUI Elements of the Files Window

This section describes GUI elements specific to this Window.

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Files Window

Column Descriptions

Table 2-48. Files Window Columns

Column Title Description
Name The name of the file
Specified Path The location of the file as specified in the
design files.
Full Path The full-path location of the design files.
Type The file type.

Popup Menu
Right-click anywhere in the window to display the popup menu and select one of the following
options:

Table 2-49. Files Window Popup Menu

Menu Item Description
View Source Opens the selected file in a Source window
Open in external editor Opens the selected file in an external editor.
Only available if you have set the Editor preference:
• set PrefMain(Editor) {<path_to_executable>}
• Tools > Edit Preferences; by Name tab, Main group.
Properties Displays the File Properties dialog box, containing
information about the selected file.

Files Menu
This menu becomes available in the Main menu when the Files window is active.
Table 2-50. Files Menu
Files Menu Item Description
View Source Opens the selected file in a Source window
Open in external editor Opens the selected file in an external editor.
Only available if you have set the Editor preference:
• set PrefMain(Editor) {<path_to_executable>}
• Tools > Edit Preferences; by Name tab, Main
group.
Save Files Saves a text file containing a sorted list of unique
files, one per line. The default name is [Link].

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Graphical User Interface
FSM List Window

FSM List Window

Use this window to view a list of finite state machines in your design.

Prerequisites
This window is populated when you specify any of the following switches during compilation
(vcom/vlog).

• +cover or +cover=f
• +acc or +acc=f

Accessing
Access the window using either of the following:

• Menu item: View > FSM List

• Command: view fsmlist

Figure 2-57. FSM List Window

GUI Elements of the FSM List Window

This section describes GUI elements specific to this Window.

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FSM List Window

Column Descriptions

Table 2-51. FSM List Window Columns

Column Title Description
Instance Lists the FSM instances.
You can reduce the number of path elements in this
column by selecting the FSM List > Options menu
item and altering the Number of Path Elements
selection box.
States The number of states in the FSM.
Transitions The number of transitions in the FSM.

Popup Menu
Right-click on one of the FSMs in the window to display the popup menu and select one of the
following options:
Table 2-52. FSM List Window Popup Menu
Popup Menu Item Description
View FSM Opens the FSM in the FSM Viewer window.
View Declaration Opens the source file for the FSM instance.
Set Context Changes the context to the FSM instance.
Add to <window> Adds FSM information to the specified window.
Properties Displays the FSM Properties dialog box containing
detailed information about the FSM.

FSM List Menu

This menu becomes available in the Main menu when the FSM List window is active.

Table 2-53. FSM List Menu

Popup Menu Item Description
View FSM Opens the FSM in the FSM Viewer window.
View Declaration Opens the source file for the FSM instance.
Add to <window> Adds FSM information to the specified window.

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Graphical User Interface
FSM Viewer Window

Table 2-53. FSM List Menu (cont.)

Popup Menu Item Description
Options Displays the FSM Display Options dialog box,
which allows you to control:
• how FSM information is added to the Wave
Window.
• how much information is shown in the Instance
Column.

FSM Viewer Window

Use this window to graphically analyze finite state machines in your design.

Prerequisites
• Analyze FSMs and their coverage data — you must specify +cover, or explicitly
+cover=f, during compilation and -coverage on the vsim command line to fully analyze
FSMs with coverage data.
• Analyze FSMs without coverage data — you must specify +acc, or explicitly +acc=f,
during compilation (vcom/vlog) to analyze FSMs with the FSM Viewer window.

Accessing
Access the window:

• From the FSM List window, double-click on the FSM you want to analyze.
• From the Objects, Locals, Wave, or Code Coverage Analyze’s FSM Analysis windows,
click on the FSM button for the FSM you want to analyze.

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FSM Viewer Window

Figure 2-58. FSM Viewer Window

FSM Viewer Window Tasks

This section describes tasks for using the FSM Viewer window.

Using the Mouse in the FSM Viewer

These mouse operations are defined for the FSM Viewer:

• The mouse wheel performs zoom & center operations on the diagram.
o Mouse wheel up — zoom out.
o Mouse wheel down — zoom in.
Whether zooming in or out, the view will re-center towards the mouse location.
• Left mouse button — click and drag to move the view of the FSM.
• Middle mouse button — click and drag to perform the following stroke actions:
o Up and left — Zoom Full.
o Up and right — Zoom Out. The amount is determined by the distance dragged.

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FSM Viewer Window

o Down and right — Zoom In on the area of the bounding box.

Using the Keyboard in the FSM Viewer

These keyboard operations are defined for the FSM Viewer:

• Arrow Keys — scrolls the window in the specified direction.

o Unmodified — scrolls by a small amount.
o Ctrl+<arrow key> — scrolls by a larger amount.
o Shift+<arrow key> — shifts the view to the edge of the display.

Exporting the FSM Viewer Window as an Image

Save the FSM view as an image for use in other applications.

1. Select the FSM Viewer window.

2. Export to one of the following formats:
o Postscript — File > Print Postscript
o Bitmap (.bmp) — File > Export > Image
JPEG (.jpg)
PNG (.png)
GIF (.gif)

Combining Common Transitions to Reset

By default, the FSM Viewer window combines transitions to reset that are based upon common
conditions. This reduces the amount of information drawn in the window and eases your FSM
debugging tasks.

Figure 2-59 shows two versions of the same FSM. The top image shows all of the transitions
and the bottom image combines the common conditions (rst) into a single transition, as
referenced by the gray diamond placeholder.

You control the level of detail for transitions with the FSM View > Transitions to “reset”
menu items.

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FSM Viewer Window

Figure 2-59. Combining Common Transition Conditions

ModelSim User’s Manual, v10.1c 123

Graphical User Interface
FSM Viewer Window

GUI Elements of the FSM Viewer Window

This section describes GUI elements specific to this Window.

Table 2-54. FSM Viewer Window — Graphical Elements

Graphical Element Description Definition
Blue state bubble Default appearance for non-reset states.

Tan state bubble with Indicates a reset state.

double outline.

Gray diamond Indicates there are several transitions to reset

with the same expression. This is a placeholder
to reduce the number of objects drawn in the
window. You can view all common
expressions by selecting:
FSM View > Transitions to “reset” > Show
All
Transition box Contains information about the transition,
• Cond: specifies the transition condition1
• Count: specifies the coverage count

Black transition line. Indicates a transition.

Red transition line. Indicates a transition that has zero (0) coverage.

1. The condition format is based on the GUI_expression_format Operators.

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FSM Viewer Window

Popup Menu
Right-click in the window to display the popup menu and select one of the following options:

Table 2-55. FSM View Window Popup Menu

Popup Menu Item Description
Transition Only available when right-clicking on a transition.
• Goto Source — Opens the source file containing
the state machine and highlights the transition
code.
• View Full Text — Opens the View Transition
dialog box, which contains the full text of the
condition.
View Declaration Opens the source file and bookmarks the file line
containing the declaration of the state machine
Zoom Full Displays the FSM completely within the window.
Set Context Executes the env command to change the context to
that of the state machine.
Add to ... Adds information about the state machine to the
specific window.
Properties Displays the FSM Properties dialog box containing
detailed information about the FSM.

FSM View Menu

This menu becomes available in the Main menu when the FSM View window is active.
Table 2-56. FSM View Menu
FSM View Menu Item Description
Show State Counts Displays the coverage counts for each state in the
state bubble.
Show Transition Counts Displays the coverage counts for each transition.
Show Transition Conditions Displays the condition for each transition.
The condition format is based on the
GUI_expression_format Operators.
Enable Info Mode Popups Displays popup information when you hover over a
state or transition.
Track Wave Cursor Displays current and previous state information
based on the cursor location in the Wave window.

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Graphical User Interface
Library Window

Table 2-56. FSM View Menu (cont.)

FSM View Menu Item Description
Transitions to “Reset” Controls the display of transitions to a reset state:
• Show All
• Show None — will also add a “hide all” note to
the lower-right hand corner.
• Hide Asynchronous Only
• Combine Common Transitions — (default)
creates a single transition for any transitions to
reset that use the same condition. The transition
is shown from a gray diamond that acts as a
placeholder.
Options Displays the FSM Display Options dialog box,
which allows you to control:
• how FSM information is added to the Wave
Window.
• how much information is shown in the Instance
Column

Library Window
Use this window to view design libraries and compiled design units.

Accessing
Access the window using either of the following:

• Menu item: View > Library

• Command: view library

Figure 2-60. Library Window

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Graphical User Interface
Library Window

GUI Elements of the Library Window

This section describes GUI elements specific to this Window.

Column Descriptions

Table 2-57. Library Window Columns

Column Title Description
Name Name of the library or design unit
Path Full pathname to the file
Type Type of file

Popup Menu
Right-click anywhere in the window to display the popup menu and select one of the following
options:

Table 2-58. Library Window Popup Menu

Popup Menu Item Description
Simulate Loads a simulation of the selected design unit
Simulate with Coverage Loads a simulation of the selected design unity,
enabling coverage (-coverage)
Edit Opens the selected file in your editor window.
Refresh Reloads the contents of the window
Recompile Compiles the selected file.
Update
Create Wave Runs the wave create command for any ports in the
selected design unit.
Delete Removes a design unit from the library or runs the
vdel command on a selected library.
Copy Copies the directory location of libraries or the
library location of design units within the library.
New Allows you to create a new library with the Create a
New Library dialog box.
Properties Displays information about the selected library or
design unit.

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Graphical User Interface
List Window

List Window
The List window displays simulation results in tabular format. Common List window tasks
include:

• Using gating expressions and trigger settings to focus in on particular signals or events.
See Configuring New Line Triggering.
• Debugging delta delay issues. See Delta Delays for more information.
The window is divided into two adjustable panes, which allows you to scroll horizontally
through the listing on the right, while keeping time and delta visible on the left.

Figure 2-61. Tabular Format of the List Window

Use this window to display a textual representation of waveforms, which you can configure to
show events and delta events for the signals or objects you have added to the window.

You can view the following object types in the List window:

• VHDL — signals, aliases, process variables, and shared variables

• Verilog — nets, registers, and variables
• Virtuals — virtual signals and functions

Accessing
Access the window using either of the following:

• Menu item: View > List

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List Window

• Command: view list

Figure 2-62. List Window

List Window Tasks

This section describes tasks for using the List window.

Adding Data to the List Window

You can add objects to the List window in any of the following ways:

• right-clicking on signals and objects in the Objects window or the Structure window and
selecting Add > to List.
• using the add list command.
• using the “Add Selected to Window Button“.

Selecting Multiple Signals

To create a larger group of signals and assign a new name to this group, do the following:

1. Select a group of signals

o Shift-click on signal columns to select a range of signals.
o Control-click on signal columns to select a group of specific signals.
2. Select List > Combine Signals

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Graphical User Interface
List Window

3. Complete the Combine Selected Signals dialog box

o Name — Specify the name you want to appear as the name of the new signal.
o Order of Indexes — Specify the order of the new signal as ascending or descending.
o Remove selected signals after combining — Specify whether the grouped signals
should remain in the List window.
This process creates virtual signals. For more information, refer to the section Virtual Signals.

Setting Time Markers in the List Window

Time markers in the List window are similar to cursors in the Wave window. Time markers tag
lines in the data table so you can quickly jump back to that time. Markers are indicated by a thin
box surrounding the marked line.

Figure 2-63. Time Markers in the List Window

Working with Markers

The table below summarizes actions you can take with markers.

Table 2-59. Actions for Time Markers

Action Method
Add marker Select a line and then select List > Add Marker
Delete marker Select a tagged line and then select List > Delete Marker

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Table 2-59. Actions for Time Markers (cont.)

Action Method
Goto marker Select View > Goto > <time> (only available when
undocked)

Expanded Time Viewing in the List Window

Event time may be shown in the List window in the same manner as delta time by using the
-delta events option with the configure list command.

When the List window displays event times, the event time is relative to events on other signals
also displayed in the List window. This may be misleading, as it may not correspond to event
times displayed in the Wave window for the same events if different signals are added to the
Wave and List windows.

The write list command (when used after the configure list -delta events command) writes a list
file in tabular format with a line for every event. Please note that this is different from the write
list -events command, which writes a non-tabular file using a print-on-change format.

The following examples illustrate the appearance of the List window and the corresponding text
file written with the write list command after various options for the configure list -delta
command are used.

Figure 2-64 shows the appearance of the List window after the configure list -delta none
command is used. It corresponds to the file resulting from the write list command. No column is
shown for deltas or events.

Figure 2-64. List Window After configure list -delta none Option is Used

Figure 2-65 shows the appearance of the List window after the configure list -delta collapse
command is used. It corresponds to the file resulting from the write list command. There is a
column for delta time and only the final delta value and the final value for each signal for each
simulation time step (at which any events have occurred) is shown.

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Figure 2-65. List Window After configure list -delta collapse Option is Used

Figure 2-66 shows the appearance of the List window after the configure list -delta all option is
used. It corresponds to the file resulting from the write list command. There is a column for
delta time, and each delta time step value is shown on a separate line along with the final value
for each signal for that delta time step.

Figure 2-66. List Window After write list -delta all Option is Used

Figure 2-67 shows the appearance of the List window after the configure list -delta events
command is used. It corresponds to the file resulting from the write list command. There is a
column for event time, and each event time step value is shown on a separate line along with the
final value for each signal for that event time step. Since each event corresponds to a new event
time step, only one signal will change values between two consecutive lines.

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Figure 2-67. List Window After write list -event Option is Used

Searching in the List Window

The List window provides two methods for locating objects:

1. Finding signal names:

o Select Edit > Find
o click the Find toolbar button (binoculars icon)
o use the find command
The first two of these options will open a Find mode toolbar at the bottom of the List
window. By default, the “Search For” option is set to “Name.” For more information,
see Using the Find and Filter Functions.
2. Search for values or transitions:
o Select Edit > Signal Search
o click the Find toolbar button (binoculars icon) and select Search For > Value from
the Find toolbar that appears at the bottom of the List window.

Searching for Values or Transitions

The search command lets you search for values of selected signals. When you select Edit >
Signal Search, the List Signal Search dialog (Figure 2-68) appears.

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Figure 2-68. Wave Signal Search Dialog Box

One option of note is Search for Expression. The expression can involve more than one signal
but is limited to signals currently in the window. Expressions can include constants, variables,
and DO files. Refer to Expression Syntax for more information.

Any search terms or settings you enter are saved from one search to the next in the current
simulation. To clear the search settings during debugging click the Reset To Initial Settings
button. The search terms and settings are cleared when you close ModelSim.

Using the Expression Builder for Expression Searches

The Expression Builder is a feature of the List Signal Search dialog box and the List trigger
properties dialog box. You can use it to create a search expression that follows the
GUI_expression_format.

To display the Expression Builder dialog box, do the following:

1. Choose Edit > Signal Search... from the main menu. This displays the Wave Signal
Search dialog box.
2. Select Search for Expression.

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3. Click the Builder button. This displays the Expression Builder dialog box shown in
Figure 2-69

Figure 2-69. Expression Builder Dialog Box

You click the buttons in the Expression Builder dialog box to create a GUI expression. Each
button generates a corresponding element of Expression Syntax and is displayed in the
Expression field. In addition, you can use the Selected Signal button to create an expression
from signals you select from the List window.

For example, instead of typing in a signal name, you can select signals in a List window and
then click Selected Signal in the Expression Builder. This displays the Select Signal for
Expression dialog box shown in Figure 2-70.

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Figure 2-70. Selecting Signals for Expression Builder

Note that the buttons in this dialog box allow you to determine the display of signals you want
to put into an expression:

• List only Select Signals — list only those signals that are currently selected in the parent
window.
• List All Signals — list all signals currently available in the parent window.
Once you have selected the signals you want displayed in the Expression Builder, click OK.

Saving an Expression to a Tcl Variable

Clicking the Save button will save the expression to a Tcl variable. Once saved this variable can
be used in place of the expression. For example, say you save an expression to the variable
"foo." Here are some operations you could do with the saved variable:

• Read the value of foo with the set command:

set foo

• Put $foo in the Expression: entry box for the Search for Expression selection.
• Issue a searchlog command using foo:
searchlog -expr $foo 0

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Formatting the List Window

Setting List Window Display Properties

Before you add objects to the List window, you can set the window’s display properties. To
change when and how a signal is displayed in the List window, select Tools > List Preferences
from the List window menu bar (when the window is undocked).

Figure 2-71. Modifying List Window Display Properties

Formatting Objects in the List Window

You can adjust various properties of objects to create the view you find most useful. Select one
or more objects and then select View > Signal Properties from the List window menu bar
(when the window is undocked).

Changing Radix (base) for the List Window

One common adjustment you can make to the List window display is to change the radix (base)
of an object. To do this, choose View > Properties from the main menu, which displays the List
Signal Properties dialog box. Figure 2-72 shows the list of radix types you can select in this
dialog box.

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Figure 2-72. List Signal Properties Dialog

The default radix type is symbolic, which means that for an enumerated type, the window lists
the actual values of the enumerated type of that object. For the other radix types (binary, octal,
decimal, unsigned, hexadecimal, ASCII, time), the object value is converted to an appropriate
representation in that radix.

Changing the radix can make it easier to view information in the List window. Compare the
image below (with decimal values) with the image in the section List Window (with symbolic
values).

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Figure 2-73. Changing the Radix in the List Window

In addition to the List Signal Properties dialog box, you can also change the radix:

• Change the default radix for the current simulation using Simulate > Runtime Options
(Main window)
• Change the default radix for the current simulation using the radix command.
• Change the default radix permanently by editing the DefaultRadix variable in the
[Link] file.

Saving the Window Format

By default, all List window information is lost once you close the window. If you want to
restore the windows to a previously configured layout, you must save a window format file as
follows:

1. Add the objects you want to the List window.

2. Edit and format the objects to create the view you want.
3. Save the format to a file by selecting File > Save Format. This opens the Save Format
dialog box where you can save List window formats in a .do file.
To use the format file, start with a blank List window and run the DO file in one of two ways:

• Invoke the do command from the command line:

VSIM> do <my_format_file>

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• Select File > Load.

Note
Window format files are design-specific. Use them only with the design you were
simulating when they were created.

In addition, you can use the write format restart command to create a single .do file that will
recreate all debug windows and breakpoints (see Saving and Restoring Breakpoints) when
invoked with the do command in subsequent simulation runs. The syntax is:

write format restart <filename>

If the ShutdownFile [Link] variable is set to this .do filename, it will call the write format
restart command upon exit.

Combining Signals into Buses

You can combine signals in the List window into buses. A bus is a collection of signals
concatenated in a specific order to create a new virtual signal with a specific value. A virtual
compare signal (the result of a comparison simulation) is not supported for combination with
any other signal.

To combine signals into a bus, use one of the following methods:

• Select two or more signals in the Wave or List window and then choose List > Combine
Signals from the menu bar. A virtual signal that is the result of a comparison simulation
is not supported for combining with any other signal.
• Use the virtual signal command at the Main window command prompt.

Configuring New Line Triggering

New line triggering refers to what events cause a new line of data to be added to the List
window. By default ModelSim adds a new line for any signal change including deltas within a
single unit of time resolution.

You can set new line triggering on a signal-by-signal basis or for the whole simulation. To set
for a single signal, select View > Signal Properties from the List window menu bar (when the
window is undocked) and select the Triggers line setting. Individual signal settings override
global settings.

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Figure 2-74. Line Triggering in the List Window

To modify new line triggering for the whole simulation, select Tools > List Preferences from
the List window menu bar (when the window is undocked), or use the configure command.
When you select Tools > List Preferences, the Modify Display Properties dialog appears:

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Figure 2-75. Setting Trigger Properties

The following table summaries the triggering options:

Table 2-60. Triggering Options

Option Description
Deltas Choose between displaying all deltas (Expand
Deltas), displaying the value at the final delta
(Collapse Delta). You can also hide the delta
column all together (No Delta), however this will
display the value at the final delta.
Strobe trigger Specify an interval at which you want to trigger
data display
Trigger gating Use a gating expression to control triggering; see
Using Gating Expressions to Control Triggering for
more details

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Using Gating Expressions to Control Triggering

Trigger gating controls the display of data based on an expression. Triggering is enabled once
the gating expression evaluates to true. This setup behaves much like a hardware signal analyzer
that starts recording data on a specified setup of address bits and clock edges.

Here are some points about gating expressions:

• Gating expressions affect the display of data but not acquisition of the data.
• The expression is evaluated when the List window would normally have displayed a
row of data (given the other trigger settings).
• The duration determines for how long triggering stays enabled after the gating
expression returns to false (0). The default of 0 duration will enable triggering only
while the expression is true (1). The duration is expressed in x number of default
timescale units.
• Gating is level-sensitive rather than edge-triggered.

Trigger Gating Example Using the Expression Builder

This example shows how to create a gating expression with the ModelSim Expression Builder.
Here is the procedure:

1. Select Tools > Window Preferences from the List window menu bar (when the
window is undocked) and select the Triggers tab.
2. Click the Use Expression Builder button.

Figure 2-76. Trigger Gating Using Expression Builder

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3. Select the signal in the List window that you want to be the enable signal by clicking on
its name in the header area of the List window.
4. Click Insert Selected Signal and then 'rising in the Expression Builder.
5. Click OK to close the Expression Builder.
You should see the name of the signal plus "rising" added to the Expression entry box of
the Modify Display Properties dialog box.
6. Click OK to close the dialog.
If you already have simulation data in the List window, the display should immediately switch
to showing only those cycles for which the gating signal is rising. If that isn't quite what you
want, you can go back to the expression builder and play with it until you get it the way you
want it.

If you want the enable signal to work like a "One-Shot" that would display all values for the
next, say 10 ns, after the rising edge of enable, then set the On Duration value to 10 ns.

Trigger Gating Example Using Commands

The following commands show the gating portion of a trigger configuration statement:

configure list -usegating 1

configure list -gateduration 100
configure list -gateexpr {/test_delta/iom_dd'rising}

See the configure command for more details.

Sampling Signals at a Clock Change

You easily can sample signals at a clock change using the add list command with the
-notrigger argument. The -notrigger argument disables triggering the display on the specified
signals. For example:

add list clk -notrigger a b c

When you run the simulation, List window entries for clk, a, b, and c appear only when clk
changes.

If you want to display on rising edges only, you have two options:

1. Turn off the List window triggering on the clock signal, and then define a repeating
strobe for the List window.
2. Define a "gating expression" for the List window that requires the clock to be in a
specified state. See above.

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Other List Window Tasks

• List > List Preferences — Allows you to specify the preferences of the List window.
• File > Export > Tabular List — Exports the information in the List window to a file in
tabular format. Equivalent to the command:
write list <filename>

• File > Export > Event List — Exports the information in the List window to a file in
print-on-change format. Equivalent to the command:
write list -event <filename>

• File > Export > TSSI List — Exports the information in the List window to a file in
TSSI. Equivalent to the command:
write tssi -event <filename>

• Edit > Signal Search — Allows you to search the List window for activity on the
selected signal.

GUI Elements of the List Window

This section describes the GUI elements specific to the List window.

Window Panes
The List window is divided into two adjustable panes, which allow you to scroll horizontally
through the listing on the right, while keeping time and delta visible on the left.

• The left pane shows the time and any deltas that exist for a given time.
• The right pane contains the data for the signals and objects you have added for each time
shown in the left pane. The top portion of the window contains the names of the signals.
The bottom portion shows the signal values for the related time.

Note
The display of time values in the left column is limited to 10 characters. Any time value
of more than 10 characters is replaced with the following:

too narrow

Markers
The markers in the List window are analogous to cursors in the Wave window. You can add,
delete and move markers in the List window similarly to the Wave window. You will notice two
different types of markers:

• Active Marker — The most recently selected marker shows as a black highlight.

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• Non-active Marker — Any markers you have added that are not active are shown with a
green border.
You can manipulate the markers in the following ways:

• Setting a marker — When you click in the right-hand portion of the List window, you
will highlight a given time (black horizontal highlight) and a given signal or object
(green vertical highlight).
• Moving the active marker — List window markers behave the same as Wave window
cursors. There is one active marker which is where you click along with inactive
markers generated by the Add Marker command. Markers move based on where you
click. The closest marker (either active or inactive) will become the active marker, and
the others remain inactive.
• Adding a marker — You can add an additional marker to the List window by right-
clicking at a location in the right-hand side and selecting Add Marker.
• Deleting a marker — You can delete a marker by right-clicking in the List window and
selecting Delete Marker. The marker closest to where you clicked is the marker that will
be deleted.
Popup Menu
Right-click in the right-hand pane to display the popup menu and select one of the following
options:
Table 2-61. List Window Popup Menu
Popup Menu Item Description
Examine Displays the value of the signal over which you used
the right mouse button, at the time selected with the
Active Marker
Add Marker Adds a marker at the location of the Active Marker
Delete Marker Deletes the closest marker to your mouse location

The following menu items are available when the List window is active:

Locals Window
Use this window to display data objects declared in the current, or local, scope of the active
process. These data objects are immediately visible from the statement that will be executed
next, which is denoted by a blue arrow in a Source window. The contents of the window change
from one statement to the next.

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Accessing
Access the window using either of the following:

• Menu item: View > locals

• Command: view locals

Figure 2-77. Locals Window

Locals Window Tasks

This section describes tasks for using the Locals window.

Viewing Data in the Locals Window

You cannot actively place information in the Locals window, it is updated as you go through
your simulation. However, there are several ways you can trigger the Locals window to be
updated.

• Run your simulation while debugging.

• Select a Process from the Processes Window.
• Select a Verilog function or task or VHDL function or procedure from the Call Stack
Window.

GUI Elements of the Locals Window

This section describes the GUI elements specific to the Locals Window.

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Column Descriptions

Table 2-62. Locals Window Columns

Column Description
Name lists the names of the immediately visible data objects.
This column also includes design object icons for the
objects, refer to the section “Design Object Icons and
Their Meanings” for more information
Value lists the current value(s) associated with each name
State Count Not shown by default. This column, State Hits, and
State % are all specific to coverage analysis
State Hits Not shown by default
State % Not shown by default

Popup Menu
Right-click anywhere in the Locals window to open a popup menu.

Table 2-63. Locals Window Popup Menu

Popup Menu Item Description
View Declaration Displays, in the Source window, the declaration
of the object
Add Adds the selected object(s) to the specified
window (Wave, List, Log, Dataflow, )
Copy Copies selected item to clipboard
Find Opens the Find toolbar at the bottom of the
window
Expand/Collapse Expands or collapses data in the window
Global Signal Radix Sets radix for selected signal(s) in all windows
Change Displays the Change Selected Variable Dialog
Box, which allows you to alter the value of the
object

Change Selected Variable Dialog Box

This dialog box allows you to change the value of the object you selected. When you click
Change, the tool executes the change command on the object.

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Figure 2-78. Change Selected Variable Dialog Box

The Change Selected Variable dialog is prepopulated with the following information about the
object you had selected in the Locals window:

• Variable Name — contains the complete name of the object.

• Value — contains the current value of the object.
When you change the value of the object, you can enter any value that is valid for the variable.
An array value must be specified as a string (without surrounding quotation marks). To modify
the values in a record, you need to change each field separately.

Memory List Window

Use this window to view a list of all memories in your design.

Single dimensional arrays of integers are interpreted as 2D memory arrays. In these cases, the
word width listed in the Memory window is equal to the integer size, and the depth is the size of
the array itself.

Memories with three or more dimensions display with a plus sign ’+’ next to their names in the
Memory window. Click the ’+’ to show the array indices under that level. When you finally
expand down to the 2D level, you can double-click on the index, and the data for the selected
2D slice of the memory will appear in a memory contents window.

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Prerequisites
The simulator identifies certain kinds of arrays in various scopes as memories. Memory
identification depends on the array element kind as well as the overall array kind (that is,
associative array, unpacked array, and so forth.).

Table 2-64. Memory Identification

VHDL Verilog/SystemVerilog SystemC
Element Kind1 • enum2 any integral type (that is, • unsigned char
• bit_vector integer_type): • unsigned short
• floating point type • shortint • unsigned int
• std_logic_vector • int • unsigned long
• std_ulogic_vector • longint • unsigned long long
• integer type • byte • char
• bit (2 state) • short
• logic • int
• reg • float
• integer • double
• time (4 state) • enum
• packed_struct/ • sc_bigint
packed_union (2 state) • sc_biguint
• packed_struct/ • sc_int
packed_union (4 state) • sc_uint
• packed_array • sc_signed
(single-Dim, multi-D, 2 • sc_unsigned
state and 4 state)
• enum
• string
Scope: • architecture • module • sc_module
Recognizable • process • interface
in • record • package
• compilation unit
• struct
• static variables within a
• task
• function
• named block
• class
Array Kind • single-dimensional • any combination of • single-dimensional
• multi-dimensional unpacked, dynamic and • multi-dimensional
associative arrays3
• real/shortreal
• float
1. The element can be "bit" or "std_ulogic" if the array has dimensionality >= 2.
2. These enumerated types must have at least one enumeration literal that is not a character literal. The listed
width is the number of entries in the enumerated type definition and the depth is the size of the array itself.

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3. Any combination of unpacked, dynamic, and associative arrays is considered a memory, provided the leaf
level of the data structure is a string or an integral type.

Accessing
Access the window using either of the following:

• Menu item: View > Memory List

• Command: view memory list

Figure 2-79. Memory LIst Window

Memory List Window Tasks

This section describes tasks for using the Memory List window.

Viewing Packed Arrays

By default, packed dimensions are treated as single vectors in the Memory List window. To
expand packed dimensions of packed arrays, select Memories > Expand Packed Memories.

To change the permanent default, edit the PrefMemory(ExpandPackedMem) variable. This

variable affects only packed arrays. If the variable is set to 1, the packed arrays are treated as
unpacked arrays and are expanded along the packed dimensions such that they appear as a
linearized bit vector. Refer to the section “Simulator GUI Preferences” for details on setting
preference variables.

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Viewing Memory Contents

When you double-click an instance on the Memory List window, ModelSim automatically
displays a Memory Data window, where the name used on the tab is taken from the name of the
instance, as seen in the Memory window. You can also enter the command add mem
<instance> at the vsim command prompt.

Viewing Multiple Memory Instances

You can view multiple memory instances simultaneously. A Memory Data window appears for
each instance you double-click in the Memory List window. When you open more than one
window for the same memory, the name of the tab receives an numerical identifier after the
name, such as “(2)”.

Saving Memory Formats in a DO File

You can save all open memory instances and their formats (for example, address radix, data
radix, and so forth) by creating a DO file.

1. Select the Memory List window

2. Select File > Save Format
displays the Save Memory Format dialog box
3. Enter the file name in the “Save memory format” dialog box
By default it is named [Link]. The file will contain all open memory instances and their
formats.
To load it at a later time, select File > Load.

Saving Memories to the WLF File

By default, memories are not saved in the WLF file when you issue a "log -r /*" command. To
get memories into the WLF file you will need to explicitly log them. For example:

log /top/dut/i0/mem

It you want to use wildcards, then you will need to remove memories from the WildcardFilter
list. To see what is currently in the WildcardFilter list, use the following command:

set WildcardFilter

If "Memories" is in the list, reissue the set WildcardFilter command with all items in the list
except "Memories." For details, see Using the WildcardFilter Preference Variable.

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Note
For post-process debug, you can add the memories into the Wave or List windows but the
Memory List window is not available.

GUI Elements of the Memory List Window

This section describes GUI elements specific to this Window.

Column Descriptions

Table 2-65. Memory List Window Columns

Column Title Description
Instance Hierarchical name of the memory
Range Memory range
Depth Memory depth
Width Word width

Popup Menu
Right-click anywhere in the window to display the popup menu and select one of the following
options:

Table 2-66. Memory List Popup Menu

Popup Menu Item Description
View Contents Opens a Memory Data window for the selected
memory.
Memory Declaration Opens a Source window to the file and line number
where the memory is declared.
Compare Contents Allows you to compare the selected memory against
another memory in the design or an external file.
Import Data Patterns Allows you to import data patterns into the selected
memory through the Import Memory dialog box.
Export Data Patterns Allows you to export data patterns from the selected
memory through the Export Memory dialog box.

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Memory List Menu

This menu becomes available in the Main menu when the Memory List window is active.

Table 2-67. Memories Menu

Popup Menu Item Description
View Contents Refer to items in the Memory List Popup Menu
Memory Declaration
Compare Contents
Import Data Patterns
Export Data Patterns
Expand Packed Memories Toggle the expansion of packed memories.
Identify Memories Within Toggle the identification of memories within Verilog
Cells cells.
Show VHDL String as Toggle the identification of VHDL strings as
Memory memories.

Memory Data Window

Use this window to view the contents of a memory.

Accessing
Access the window by:

• Double-clicking on a memory in the Memory List window.

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Figure 2-80. Memory Data Window

Memory Data Window Tasks

This section describes tasks for using the Memory Data window.

Direct Address Navigation

You can navigate to any address location directly by editing the address in the address column.
Double-click on any address, type in the desired address, and hit Enter. The address display
scrolls to the specified location.

Splitting the Memory Contents Window

To split a memory contents window into two screens displaying the contents of a single
memory instance select Memory Data > Split Screen.

This allows you to view different address locations within the same memory instance
simultaneously.

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Figure 2-81. Split Screen View of Memory Contents

GUI Elements of the Memory Data Window

This section describes GUI elements specific to this Window.

Popup Menu
Right-click in the window to display the popup menu and select one of the following options:

Table 2-68. Memory Data Popup Menu — Address Pane

Popup Menu Item Description
Goto Allows you to go to a specific address
Split Screen Splits the Memory Data window to allow you to
view different parts of the memory simultaneously.
Properties Allows you to set various properties for the Memory
Data window.
Close Instance Closes the active Memory Data window.
Close All Closes all Memory Data windows.

Table 2-69. Memory Data Popup Menu — Data Pane

Popup Menu Item Description
Edit Allows you to edit the value of the selected data.
Change Allows you to change data within the memory
through the use of the Change Memory dialog box.

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Table 2-69. Memory Data Popup Menu — Data Pane (cont.)

Popup Menu Item Description
Import Data Patterns Allows you to import data patterns into the selected
memory through the Import Memory dialog box.
Export Data Patterns Allows you to export data patterns from the selected
memory through the Export Memory dialog box.
Split Screen Refer to items in the Memory Data Popup Menu —
Address Pane
Properties
Close Instance
Close All

Memory Data Menu

This menu becomes available in the Main menu when the Memory Data window is active.

Table 2-70. Memory Data Menu

Popup Menu Item Description
Memory Declaration Opens a Source window to the file and line number
where the memory is declared.
Compare Contents Allows you to compare the selected memory against
another memory in the design or an external file.
Import Data Patterns Refer to items in the Memory Data Popup Menu —
Data Pane
Export Data Patterns

Expand Packed Memories Toggle the expansion of packed memories.

Identify Memories Within Toggle the identification of memories within Verilog
Cells cells.
Show VHDL String as Toggle the identification of VHDL strings as
Memory memories.
Split Screen Refer to items in the Memory Data Popup Menu —
Address Pane

Message Viewer Window

Use this window to easily access, organize, and analyze any Note, Warning, Error or other
elaboration and runtime messages written to the transcript during the simulation run.

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Prerequisites
By default, the tool writes transcripted messages during elaboration and runtime only to the
transcript. To write messages to the WLF file (thus the Message Viewer window), use the
-displaymsgmode and -msgmode options with the vsim commmand to change the default
behavior. By writing messages to the WLF file, the Message Viewer window is able to organize
the messages for your analysis during the current simulation as well as during post simulation.

You can control what messages are available in the transcript, WLF file, or both with the
following switches:

• displaymsgmode messages — User generated messages resulting from calls to Verilog

Display System Tasks and PLI/FLI print function calls. By default, these messages are
written only to the transcript, which means you cannot access them through the Message
Viewer window. In many cases, these user generated messages are intended to be output
as a group of transcripted messages, thus the default of transcript only. The Message
Viewer treats each message individually, therefore you could lose the context of these
grouped messages by modifying the view or sort order of the Message Viewer.
To change this default behavior you can use the -displaymsgmode argument with the
vsim command. The syntax is:
vsim -displaymsgmode {both | tran | wlf}

You can also use the displaymsgmode variable in the [Link] file.
The message transcribing methods that are controlled by -displaymsgmode include:
o Verilog Display System Tasks — $write, $display, $monitor, and $strobe. The
following also apply if they are sent to STDOUT: $fwrite, $fdisplay, $fmonitor, and
$fstrobe.
o FLI Print Function Calls — mti_PrintFormatted and mti_PrintMessage.
o PLI Print Function Calls — io_printf and vpi_printf.
• msgmode messages — All elaboration and runtime messages not part of the
displaymsgmode messages. By default, these messages are written only to the transcript.
To change this default behavior you can use the -msgmode argument with the vsim
command. The syntax is:
vsim -msgmode {both | tran | wlf}

To write messages to the WLF file and transcript, which provides access to the messages
through the Message Viewer window, you can also use the msgmode variable in the
[Link] file.

Accessing
Access the window using either of the following:

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• Menu item: View > Message Viewer

• Command: view msgviewer

Figure 2-82. Message Viewer Window

Message Viewer Window Tasks

Figure 2-83 and Table 2-71 provide an overview of the Message Viewer and several tasks you
can perform.

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Figure 2-83. Message Viewer Window — Tasks

Table 2-71. Message Viewer Tasks

Icon Task Action
1 Display a detailed description of the right click the message text then
message. select View Verbose Message.
2 Open the source file and add a bookmark to double click the object name(s).
the location of the object(s).
3 Change the focus of the Structure and double click the hierarchical
Objects windows. reference.
4 Open the source file and set a marker at the double click the file name.
line number.

GUI Elements of the Message Viewer Window

This section describes the GUI elements specific to this window.

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Column Descriptions
Table 2-72. Message Viewer Window Columns
Column Description
Assertion Expression
Assertion Name
Assertion Start Time
Category Keyword for the various categories of messages:
• DISPLAY
• FLI
• PA
• PLI
• SDF
• TCHK
• VCD
• VITAL
• WLF
• MISC
• <user-defined>
Effective Time
File Info Filename related to the cause of the message, and in
some cases the line number in parentheses.
Id Message number
Messages Organized tree-structure of the sorted messages, as well
as, when expanded, the text of the messages.
Objects Object(s) related to the message, if any.
Process
Region Hierarchical region related to the message, if any.
Severity Message severity, such as Warning, Note or Error.
Time Time of simulation when the message was issued.
Timing Check Kind Information about timing checks
Verbosity Verbosity information from Verilog-XL Compatible
System Tasks and Functions system tasks.

Popup Menu
Right-click anywhere in the window to open a popup menu that contains the following

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selections:

Table 2-73. Message Viewer Window Popup Menu

Popup Menu Item Description
View Source Opens a Source window for the file, and in some cases
takes you to the associated line number.
View Verbose Message Displays the Verbose Message dialog box containing
further details about the selected message.
Object Declaration Opens and highlights the object declaration related to the
selected message.
Goto Wave Opens the Wave window and places the cursor at the
simulation time for the selected message.
Display Reset Resets the display of the window.
Display Options Displays the Message Viewer Display Options dialog
box, which allows you to further control which messages
appear in the window.
Filter Displays the Message Viewer Filter Dialog Box, which
allows you to create specialized rules for filtering the
Message Viewer.
Clear Filter Restores the Message Viewer to an unfiltered view by
issuing the messages clearfilter command.
Expand/Collapse Manipulates the expansion of the Messages column.
Selected/All

Related GUI Features

• The Messages Bar in the Wave window provides indicators as to when a message
occurred.

Message Viewer Display Options Dialog Box

This dialog box allows you to control display options for the message viewer tab of the
transcript window.

• Hierarchy Selection — This field allows you to control the appearance of message
hierarchy, if any.
o Display with Hierarchy — enables or disables a hierarchical view of messages.
o First by, Then by — specifies the organization order of the hierarchy, if enabled.
• Time Range — Allows you to filter which messages appear according to simulation
time. The default is to display messages for the complete simulation time.

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• Displayed Objects — Allows you to filter which messages appear according to the
values in the Objects column. The default is to display all messages, regardless of the
values in the Objects column. The Objects in the list text entry box allows you to specify
filter strings, where each string must be on a new line.

Message Viewer Filter Dialog Box

This dialog box allows you to create filter rules that specify which messages should be shown in
the message viewer. It contains a series of dropdown and text entry boxes for creating the filter
rules and supports the addition of additional rule (rows) to create logical groupings.

From left to right, each filter rule is made up of the following:

• Add and Remove buttons — either add a rule filter row below the current row or remove
that rule filter row.
• Logic field — specifies a logical argument for combining adjacent rules. Your choices
are: AND, OR, NAND, and NOR. This field is greyed out for the first rule filter row.
• Open Parenthesis field — controls rule groupings by specifying, if necessary, any open
parentheses. The up and down arrows increase or decrease the number of parentheses in
the field.
• Column field — specifies that your filter value applies to a specific column of the
Message Viewer.
• Inclusion field — specifies whether the Column field should or should not contain a
given value.
o For text-based filter values your choices are: Contains, Doesn’t Contain, or Exact.
o For numeric- and time-based filter values your choices are: ==, !=, <, <=, >, and >=.
• Case Sensitivity field — specifies whether your filter rule should treat your filter value
as Case Sensitive or Case Insensitive. This field only applies to text-based filter values.
• Filter Value field — specifies the filter value associated with your filter rule.
• Time Unit field — specifies the time unit. Your choices are: fs, ps, ns, us, ms. This field
only applies to the Time selection from the Column field.
• Closed Parenthesis field — controls rule groupings by specifying, if necessary, any
closed parentheses. The up and down arrows increase or decrease the number of
parentheses in the field.
Figure 2-84 shows an example where you want to show all messages, either errors or warnings,
that reference the 15th line of the file cells.v.

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Figure 2-84. Message Viewer Filter Dialog Box

When you select OK or Apply, the Message Viewer is updated to contain only those messages
that meet the criteria defined in the Message Viewer Filter dialog box.

Also, when selecting OK or Apply, the Transcript window will contain an echo of the messages
setfilter command, where the argument is a Tcl definition of the filter. You can then cut/paste
this command for reuse at another time.

Objects Window
Use this window to view the names and current values of declared data objects in the current
region, as selected in the Structure window. Data objects include:

• signals
• nets
• registers
• constants and variables not declared in a process
• generics
• parameters

Accessing
Access the window using either of the following:

• Menu item: View > Objects

• Command: view objects
• Wave window: View Objects Window Button

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Figure 2-85. Objects Window

Objects Window Tasks

This section describes tasks for using the Objects window.

Interacting with Other Windows

1. Click an entry in the window to highlight that object in the Dataflow, and Wave
windows.
2. Double-click an entry to highlights that object in a Source window

Setting Signal Radix

You can set the signal radix for a selected signal or signals in the Objects window as follows:

1. Click (LMB) a signal to select it or use Ctrl-Click Shift-Click to select a group of

signals.
2. Select Objects > Radix from the menu bar; or right-click the selected signal(s) and
select Radix from the popup menu.
This opens the Signal Radix dialog box (Figure 2-86), where you may select a radix.
This sets the radix for the selected signal(s) in the Objects window and every other
window where the signal appears.

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Figure 2-86. Setting the Global Signal Radix from the Objects Window

Finding Contents of the Objects Window

You can filter the contents of the Objects window by either the Name or Value columns.

1. Ctrl-F to display the Find box at the bottom of the window.

2. Click the “Search For” button and select the column to filter on.
3. Enter a string in the Find text box
4. Enter
Refer to the section “Using the Find and Filter Functions” for more information.

Filtering Contents of the Objects Window

You can filter the contents of the Objects window by the Name column.

1. Ctrl-F to display the Find box at the bottom of the window.

2. Ctrl-M to change to “Contains” mode.
3. Enter a string in the Contains text box
The filtering will occur as you begin typing. You can disable this feature with ctrl-T.
Filters are stored relative to the region selected in the Structure window. If you re-select a
region that had a filter applied, that filter is restored. This allows you to apply different filters to
different regions.

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Refer to the section “Using the Find and Filter Functions” for more information.

Filtering by Signal Type

The View > Filter menu selection allows you to specify which signal types to display in the
Objects window. Multiple options can be selected. Select Change Filter to open the Filter
Objects dialog, where you can select port modes and object types to be displayed.

Popup Menu
Right-click anywhere in the window to display the popup menu and select one of the following
options:

Table 2-74. Objects Window Popup Menu

Popup Menu Item Description
View Declaration Opens a Source window to the declaration of the
object
View Memory Contents
Add Wave Adds the selected object(s) to the Wave window
Add Wave New Creates a new instance of the Wave window and
adds the selected object(s) to that window.
Add Dataflow Adds the selected object(s) to a Dataflow window
Add to Add the selected object(s) to any one of the
following: Wave window, List window, Log file,
Schematic window, Dataflow window. You may
choose to add only the Selected Signals, all Signals
in Region, all Signals in Design.
Copy Copies information about the object to the clipboard
Find Opens the Find box
Insert Breakpoint Adds a breakpoint for the selected object
Modify Modify the selected object(s) by selecting one of the
following from the submenu:
• Force - opens Force Selected Signal dialog
• Remove Force - remove effect of force command
• Change Value - change value of selected
• Apply Clock - opens Define Clock dialog
• Apply Wave - opens Create Pattern Wizard
Radix Opens Signal Radix dialog, allowing you to set the
radix of selected signal(s) in all windows

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Table 2-74. Objects Window Popup Menu (cont.)

Popup Menu Item Description
Show Shows list of port types and object kinds that are
displayed. Includes a Change Filter selection that
opens the Filter Objects dialog, which allows you to
filter the display.

Processes Window
Use this window to view a list of HDL processes in one of four viewing modes:

• Active (default) — active processes in your simulation.

• In Region — process in the selected region.
• Design — intended for primary navigation of ESL (Electronic System Level) designs
where processes are a foremost consideration.
• Hierarchy — a tree view of any SystemVerilog nested fork-joins.
In addition, the data in this window will change as you run your simulation and processes
change states or become inactive.

Accessing
Access the window using either of the following:

• Menu item: View > Process

• Command: view process

Figure 2-87. Processes Window

Processes Window Tasks

This section describes tasks for using the Processes window.

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Changing Your Viewing Mode

You can change the display to show all the processes in a region or in the entire design by doing
any one of the following:

• Select Process > In Region, Design, Active, or Hierarchy.

• Use the Process Toolbar
• Right-click in the Process window and select In Region, Design, Active, or Hierarchy.
The view mode you select is persistent and is “remembered” when you exit the simulation. The
next time you bring up the tool, this window will initialize in the last view mode used.

Filtering Processes
You can control which processes are visible in the Processes window as follows:

1. Right-click in the Processes window and select Display Options.

2. In the Process Display Options dialog box select the Type or States you want to include
or exclude from the window.
3. OK
When you filter the window according to specific process states, the heading of the State
column changes to “State (filtered)” as shown in Figure 2-88.

Figure 2-88. Column Heading Changes When States are Filtered

The default “No Implicit & Primitive” selection causes the Process window to display all
process types except implicit and primitive types. When you filter the display according to
specific process types, the heading of the Type column becomes “Type (filtered)”.

Once you select the options, data will update as the simulation runs and processes change their
states. When the In Region view mode is selected, data will update according to the region
selected in the Structure window.

Viewing the Full Path of the Process

By default, all processes are displayed without the full hierarchical context (path). You can
display processes with the full path by selecting Process > Show Full Path

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Viewing Processes in Post-Processing Mode

This window also shows data in the post-processing (WLF view or Coverage view) mode. You
will need to log processes in the simulation mode to be able to view them in post-processing
mode.

In the post-processing mode, the default selection values will be same as the default values in
the live simulation mode.

Things to remember about the post-processing mode:

• There are no active processes, so the Active view mode selection will not show
anything.
• All processes will have same ‘Done’ state in the post-processing mode.
• There is no order information, so the Order column will show ‘-‘ for all processes.

Setting a Ready Process as the Next Active Process

You can select any “Ready” process and set it to be the next Active process executed by the
simulator, ahead of any other queued processes. To do this, simply right-click any “Ready”
process and select Set Next Active from the popup context menu.

When you set a process as the next active process, you will see “(Next Active)” in the Order
column of that process (Figure 2-89).

Figure 2-89. Next Active Process Displayed in Order Column

Creating Textual Process Report

You can create a textual report of all processes by using the process report command.

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Figure 2-90. Sample Process Report in the Transcript Window

GUI Elements of the Processes Window

This section describes GUI elements specific to this Window.

Column Descriptions

Table 2-75. Processes Window Column Descriptions

Column Title Description
Name Name of the process.
Order Execution order of all processes in the
Active and Ready states. Refer to the
section “Process Order Description” for
more information.
Parent Path Hierarchical parent pathname of the process
State Process state. Refer to the section “Process
State Definitions” for more information.
Type Process type, according to the language.
Refer to the section “Process Type
Definitions” for more information.

Process State Definitions

• Idle — Indicates an inactive SystemC Method, or a process that has never been active.
The Idle state will occur only for SC processes or methods. It will never occur for HDL
processes.

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• Wait — Indicates the process is waiting for a wake up trigger (change in VHDL signal,
Verilog net, SystemC signal, or a time period).
• Ready — Indicates the process is scheduled to be executed in current simulation phase
(or in active simulation queue) of current delta cycle.
• Active – Indicates the process is currently active and being executed.
• Queued — Indicates the process is scheduled to be executed in current delta cycle, but
not in current simulation phase (or in active simulation queue).
• Done — Indicates the process has been terminated, and will never restart during current
simulation run.
Processes in the Idle and Wait states are distinguished as follows. Idle processes (except for
ScMethods) have never been executed before in the simulation, and therefore have never been
suspended. Idle processes will become Active, Ready, or Queued when a trigger occurs. A
process in the Wait state has been executed before but has been suspended, and is now waiting
for a trigger.

SystemC methods can have one of the four states: Active, Ready, Idle or Queued. When
ScMethods are not being executed (Active), or scheduled (Ready or Queued), they are inactive
(Idle). ScMethods execute in 0 time, whenever they get triggered. They are never suspended or
terminated.

Process Type Definitions

The Type column displays the process type according to the language used. It includes the
following types:

• Always
• Assign
• Final
• Fork-Join (dynamic process like fork-join, sc_spawn, and so forth.)
• Initial
• Implicit (internal processes created by simulator like Implicit wires, and so forth.)
• Primitive (UDP, Gates, and so forth.)
• ScMethod
• ScThread (SC Thread and SC CThread processes)
• VHDL Process

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Process Order Description

The Order column displays the execution order of all processes in the Active and Ready states
in the active kernel queue. Processes that are not in the Active or Ready states do not yet have
any order, in which case the column displays a dash (-). The Process window updates the
execution order automatically as simulation proceeds.

Source Window
The Source window allows you to view and edit source files as well as set breakpoints, step
through design files, and view code coverage statistics.

By default, the Source window displays your source code with line numbers. You may also see
the following graphic elements:

• Red line numbers — denote executable lines, where you can set a breakpoint
• Blue arrow — denotes the currently active line or a process that you have selected in the
Processes Window
• Red ball in line number column — denotes file-line breakpoints; gray ball denotes
breakpoints that are currently disabled
• Blue flag in line number column — denotes line bookmarks
• Language Templates pane — displays templates for writing code in VHDL, Verilog,
SystemC, Verilog 95, and SystemVerilog (Figure 2-91). See Language Templates.

Figure 2-91. Source Window Showing Language Templates

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• Underlined text — denotes a hypertext link that jumps to a linked location, either in the
same file or to another Source window file. Display is toggled on and off by the Source
Navigation button.
• Active Time Label — Displays the current Active Time or the Now (end of simulation)
time. This is the time used to control state values annotated in the window. (For details,
see Active Time Label.)

Opening Source Files

You can open source files using the File > Open command or by clicking the Open icon.
Alternatively, you can open source files by double-clicking objects in other windows. For
example, if you double-click an item in the Objects window or in the structure tab (sim tab), the
underlying source file for the object will open in the Source window and scroll to the line where
the object is defined.

From the command line you can use the edit command.

By default, files you open from within the design (such as when you double-click an object in
the Objects window) open in Read Only mode. To make the file editable, right-click in the
Source window and select (uncheck) Read Only. To change this default behavior, set the
PrefSource(ReadOnly) variable to 0. See Simulator GUI Preferences for details on setting
preference variables.

Displaying Multiple Source Files

By default each file you open or create is marked by a window tab, as shown in the graphic
below.

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Figure 2-92. Displaying Multiple Source Files

Dragging and Dropping Objects into the Wave and List

Windows
ModelSim allows you to drag and drop objects from the Source window to the Wave and List
windows. Double-click an object to highlight it, then drag the object to the Wave or List
window. To place a group of objects into the Wave and List windows, drag and drop any
section of highlighted code. When an object is dragged and dropped into the Wave window, the
add wave command will be reflected in the Transcript window.

Setting your Context by Navigating Source Files

When debugging your design from within the GUI, you can change your context while
analyzing your source files. Figure 2-93 shows the pop-up menu the tool displays after you
select then right-click an instance name in a source file.

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Figure 2-93. Setting Context from Source Files

The title bar of the Source window displays your current context, parenthetically, after the file
name and location. This changes as you alter your context, either through the pop-up menu or
by changing your selection in the Structure window.

This functionality allows you to easily navigate your design for debugging purposes by
remembering where you have been, similar to the functionality in most web browsers. The
navigation options in the pop-up menu function as follows:

• Open Instance — changes your context to the instance you have selected within the
source file. This is not available if you have not placed your cursor in, or highlighted the
name of, an instance within your source file.
If any ambiguities exists, most likely due to generate statements, this option opens a
dialog box allowing you to choose from all available instances.
• Ascend Env — changes your context to the file and line number in the parent region
where the current region is instantiated. This is not available if you are at the top-level of
your design.
• Forward/Back — allows you to change to previously selected contexts. This is not
available if you have not changed your context.
The Open Instance option is essentially executing an environment command to change your
context, therefore any time you use this command manually at the command prompt, that
information is also saved for use with the Forward/Back options.

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Highlighted Text in a Source Window

The Source window can display text that is highlighted as a result of various conditions or
operations, such as the following:

• Double-clicking an error message in the transcript shown during compilation

In these cases, the relevant text in the source code is shown with a persistent highlighting. To
remove this highlighted display, choose More > Clear Highlights from the right-click popup
menu of the Source window. If the Source window is docked, you can also perform this action
by selecting Source > More > Clear Highlights from the Main menu. If the window is
undocked, select Edit > Advanced > Clear Highlights.

Note
Clear Highlights does not affect text that you have selected with the mouse cursor.

Example
To produce a compile error that displays highlighted text in the Source window, do the
following:

1. Choose Compile > Compile Options

2. In the Compiler Options dialog box, click either the VHDL tab or the Verilog &
SystemVerilog tab.
3. Enable Show source lines with errors and click OK.
4. Open a design file and create a known compile error (such as changing the word “entity”
to “entry” or “module” to “nodule”).
5. Choose Compile > Compile and then complete the Compile Source Files dialog box to
finish compiling the file.
6. When the compile error appears in the Transcript window, double-click on it.
7. The source window is opened (if needed), and the text containing the error is
highlighted.
8. To remove the highlighting, choose Source > More > Clear Highlights.

Hyperlinked (Underlined) Text in a Source Window

The Source window supports hyperlinked navigation, providing links displayed as underlined
text. To turn hyperlinked text on or off in the Source window, do the following:

1. Click anywhere in the Source window. This enables the display of the Simulate toolbar
(see Table 2-31).
2. Click the Source Navigation button.

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When you double-click on hyperlinked text, the selection jumps from the usage of an object to
its declaration. This provides the following operations:

• Jump from the usage of a signal, parameter, macro, or a variable to its declaration.
• Jump from a module declaration to its instantiation, and vice versa.
• Navigate back and forth between visited source files.

Language Templates
ModelSim language templates help you write code. They are a collection of wizards, menus,
and dialogs that produce code for new designs, test benches, language constructs, logic blocks,
and so forth.

Note
The language templates are not intended to replace thorough knowledge of coding. They
are intended as an interactive reference for creating small sections of code. If you are
unfamiliar with a particular language, you should attend a training class or consult one of
the many available books.

To use the templates, either open an existing file, or select File > New > Source to create a new
file. Once the file is open, select Source > Show Language Templates if the Source window is
docked in the Main window; select View > Show Language Templates of the Source window
is undocked.

Figure 2-94. Language Templates

The template that appears depends on the type of file you create. For example Module and
Primitive templates are available for Verilog files, and Entity and Architecture templates are
available for VHDL files.

VHDL, Verilog, and SystemVerilog language templates display the following options:

a. New Design Wizard — Opens the Create New Design Wizard dialog. (Figure 2-95)

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The New Design Wizard will step you through the tasks necessary to add a VHDL
Design Unit, or Verilog Module to your code.
b. Create Testbench — Opens the Create Testbench Wizard dialog.
The Create Testbench Wizard allows you to create a testbench for a previously
compiled design unit in your library. It generates code that instantiates your design
unit and wires it up inside a top-level design unit. You can add stimulus to your
testbench at a later time.
c. Language Constructs — Menu driven code templates you can use in your design.
Includes Modules, Primitives, Declarations, Statements and so on.
d. Stimulus Generators — Provides three interactive wizards:
• Create Clock Wizard
Steps you through the tasks necessary to add a clock generator to your code. It
allows you to control a number of clock generation variables.
• Create Count Wizard
Helps you make a counter. You can specify various parameters for the counter.
For example, rising/falling edge triggered, reset active high or low, and so on.
• Create Simulation Stop Wizard
The simulation time at which you wish to end your simulation run. This adds
code that will stop the simulator at a specified time.

Language Template Wizards

Double-click an object in the list to open the Create New Design Wizard. (Figure 2-95) Simply
follow the directions in the wizard to create a new block in your design.

Figure 2-95. Create New Design Wizard

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Highlighted Code in Language Templates

Code inserted into your source contains a variety of highlighted fields. The example below
shows a module statement inserted from the Verilog template.

Figure 2-96. Language Template Context Menus

The highlighting indicates the following type of information must be entered:

• Yellow — Requires user supplied data or string. For example, module_name in

Figure 2-96 must be replaced with the name of the module.
• Green — Opens a drop-down context menu. Selections open more green and yellow
highlighted options.
• Red — Opens a drop-down context menu. Selections here can affect multiple code lines.
Figure 2-96 shows the menu that appears when you double-click module_item then
select gate_instantiation.

Setting File-Line Breakpoints with the GUI

You can easily set file-line breakpoints in your source code by clicking your mouse cursor in
the line number column of a Source window. Click the left mouse button in the line number
column next to a red line number and a red ball denoting a breakpoint will appear (Figure 2-97).

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Figure 2-97. Breakpoint in the Source Window

The breakpoint markers are toggles. Click once to create the breakpoint; click again to disable
or enable the breakpoint.

To delete the breakpoint completely, right click the red breakpoint marker, and select Remove
Breakpoint. Other options on the context menu include:

• Disable Breakpoint — Deactivate the selected breakpoint.

• Edit Breakpoint — Open the File Breakpoint dialog to change breakpoint arguments.
• Edit All Breakpoints — Open the Modify Breakpoints dialog.
• Run Until Here — Run the simulation from the current simulation time up to the
specified line of code. Refer to Run Until Here for more information.
• Add/Remove Bookmark — Add or remove a file-line bookmark.

Adding File-Line Breakpoints with the bp Command

Use the bp command to add a file-line breakpoint from the VSIM> prompt.

For example:

bp [Link] 147

sets a breakpoint in the source file [Link] at line 147.

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Editing File-Line Breakpoints

To modify (or add) a breakpoint according to the line number in a source file, do any one of the
following:

• Select Tools > Breakpoints from the Main menu.

• Right-click a breakpoint and select Edit All Breakpoints from the popup menu.
• Click the Edit Breakpoints toolbar button. See Simulate Toolbar.
This displays the Modify Breakpoints dialog box shown in Figure 2-98.

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Figure 2-98. Modifying Existing Breakpoints

The Modify Breakpoints dialog box provides a list of all breakpoints in the design. To modify a
breakpoint, do the following:

1. Select a file-line breakpoint from the list.

2. Click Modify, which opens the File Breakpoint dialog box shown in Figure 2-98.
3. Fill out any of the following fields to modify the selected breakpoint:
• Breakpoint Label — Designates a label for the breakpoint.

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• Instance Name — The full pathname to an instance that sets a SystemC breakpoint
so it applies only to that specified instance.
• Breakpoint Condition — One or more conditions that determine whether the
breakpoint is observed. If the condition is true, the simulation stops at the
breakpoint. If false, the simulation bypasses the breakpoint. A condition cannot refer
to a VHDL variable (only a signal). Refer to the tip below for more information on
proper syntax for breakpoints entered in the GUI.
• Breakpoint Command — A string, enclosed in braces ({}) that specifies one or more
commands to be executed at the breakpoint. Use a semicolon (;) to separate multiple
commands.

Tip: All fields in the File Breakpoint dialog box, except the Breakpoint Condition field,
use the same syntax and format as the -inst switch and the command string of the bp
command. Do not enclose the expression entered in the Breakpoint Condition field in
quotation marks (“ ”). For more information on these command options, refer to the bp
command in the Questa SV/AFV Reference Manual.

Click OK to close the File Breakpoints dialog box.

1. Click OK to close the Modify Breakpoints dialog box.

Loading and Saving Breakpoints

The Modify Breakpoints dialog (Figure 2-98) includes Load and Save buttons that allow you to
load or save breakpoints.

Setting Conditional Breakpoints

In dynamic class-based code, an expression can be executed by more than one object or class
instance during the simulation of a design. You set a conditional breakpoint on the line in the
source file that defines the expression and specifies a condition of the expression or instance
you want to examine. You can write conditional breakpoints to evaluate an absolute expression
or a relative expression.

You can use the SystemVerilog keyword this when writing conditional breakpoints to refer to
properties, parameters or methods of an instance. The value of this changes every time the
expression is evaluated based on the properties of the current instance. Your context must be
within a local method of the same class when specifying the keyword this in the condition for a
breakpoint. Strings are not allowed.

The conditional breakpoint examples below refer to the following SystemVerilog source code
file [Link]:

Figure 2-99. Source Code for [Link]

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1 class Simple;
2 integer cnt;
3 integer id;
4 Simple next;
5
6 function new(int x);
7 id=x;
8 cnt=0
9 next=null
10 endfunction
11
12 task up;
13 cnt=cnt+1;
14 if (next) begin
15 [Link];
16 end
17 endtask
18 endclass
19
20 module test;
21 reg clk;
22 Simple a;
23 Simple b;
24
25 initial
26 begin
27 a = new(7);
28 b = new(5);
29 end
30
31 always @(posedge clk)
32 begin
33 [Link];
34 [Link];
35 [Link]
36 end;
37 endmodule

Prerequisites
Compile and load your simulation.

Setting a Breakpoint For a Specific Instance

Enter the following on the command line:

bp [Link] 13 -cond {[Link]==7}

Results
The simulation breaks at line 13 of the [Link] source file (Figure 2-99) the first time module
a hits the expression because the breakpoint is evaluating for an id of 7 (refer to line 27).

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Setting a Breakpoint For a Specified Value of Any Instance.

Enter the following on the command line:

bp [Link] 13 -cond {[Link]==8}

Results
The simulation evaluates the expression at line 13 in the [Link] source file (Figure 2-99),
continuing the simulation run if the breakpoint evaluates to false. When an instance evaluates to
true the simulation stops, the source is opened and highlights line 13 with a blue arrow. The first
time cnt=8 evaluates to true, the simulation breaks for an instance of module Simple b. When
you resume the simulation, the expression evaluates to cnt=8 again, but this time for an instance
of module Simple a.

You can also set this breakpoint with the GUI:

1. Right-click on line 13 of the [Link] source file.

2. Select Edit Breakpoint 13 from the drop menu.
3. Enter
[Link]==8

in the Breakpoint Condition field of the Modify Breakpoint dialog box. (Refer to
Figure 2-98) Note that the file name and line number are automatically entered.

Checking Object Values and Descriptions

You can check the value or description of signals, indexes, and other objects in the Source
[Link] are two quick methods to determine the value and description of an object:

• Select an object, then right-click and select Examine or Describe from the context
menu.
• Pause the cursor over an object to see an examine pop-up

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Figure 2-100. Source Window Description

You can select Source > Examine Now or Source > Examine Current Cursor to choose at
what simulation time the object is examined or described.

You can also invoke the examine and/or describe commands on the command line or in a
macro.

Marking Lines with Bookmarks

Source window bookmarks are blue flags that mark lines in a source file. These graphical icons
may ease navigation through a large source file by highlighting certain lines.

As noted above in the discussion about finding text in the Source window, you can insert
bookmarks on any line containing the text for which you are searching. The other method for
inserting bookmarks is to right-click a line number and select Add/Remove Bookmark. To
remove a bookmark, right-click the line number and select Add/Remove Bookmark again.

To remove all bookmarks from the Source window, select Source > Clear Bookmarks from
the menu bar when the Source window is active.

Performing Incremental Search for Specific Code

The Source window includes a Find function that allows you to do an incremental
search for specific code. To activate the Find bar (Figure 2-101) in the Source window
select Edit > Find from the Main menus or click the Find icon in the Main toolbar. For
more information see Using the Find and Filter Functions.

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Figure 2-101. Source Window with Find Toolbar

Customizing the Source Window

You can customize a variety of settings for Source windows. For example, you can change
fonts, spacing, colors, syntax highlighting, and so forth. To customize Source window settings,
select Tools > Edit Preferences. This opens the Preferences dialog. Select Source Windows
from the Window List.

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Figure 2-102. Preferences Dialog for Customizing Source Window

Select an item from the Category list and then edit the available properties on the right. Click
OK or Apply to accept the changes.

The changes will be active for the next Source window you open. The changes are saved
automatically when you quit ModelSim. See Setting Preference Variables from the GUI for
details.

Structure Window
Use this window to view the hierarchical structure of the active simulation.

The name of the structure window, as shown in the title bar or in the tab if grouped with other
windows, can vary:

• sim — This is the name shown for the Structure window for the active simulation.
• dataset_name — The Structure window takes the name of any dataset you load through
the File > Datasets menu item or the dataset open command.

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Viewing the Structure Window

By default, the Structure window opens in a tab group with the Library windows after starting a
simulation. You can also open the Structure window with the “View Objects Window Button”.

The hierarchical view includes an entry for each object within the design. When you select an
object in a Structure window, it becomes the current region.

The contents of several windows automatically update based on which object you select,
including the Source window, Objects window, Processes window, and Locals window. All
mouse button operations clear the current selection and select the item under the cursor.

Accessing
Access the window using any of the following:

• Menu item: View > Structure

• Command: view structure
• Button: View Objects Window Button

Figure 2-103. Structure Window

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Structure Window Tasks

This section describes tasks for using the Structure window.

Using the Popup Menu

Right-click on an object in the Structure window to display the popup menu and select one of
the following options:

Table 2-76. Structure Window Popup Menu

Popup Menu Item Description
View Declaration Opens the source file and bookmarks the object.
View Instantiation Opens the source file and bookmarks the object.
Add Wave Adds the selected object(s) to the Wave window.
Add Wave New Creates a new instance of the Wave window and
adds the selected object(s) to that window.
Add Wave To Opens a drop down list of Wave windows when
multiple windows exist. Adds the selected object(s)
to the selected Wave window.
Add Dataflow Adds the selected object(s) to a Dataflow window.
Add to Add the selected object(s) to any one of the
following: Wave window, List window, Log file,
Schematic window, Dataflow window. You may
choose to add only the Selected Signals, all Signals
in Region, all Signals in Design.
Copy Copies the object instance path to the clipboard
Find Opens the Search Bar (at bottom of window) in the
Find mode to make searching for objects easier,
especially with large designs.
Expand Selected Displays the hierarchy of the object recursively.
Collapse Selected Closes the hierarchy of the object.
Collapse All Collapses the hierarchy to the top instance.
XML Import Hint Displays the XML Import Hint dialog box with
information about the Link Type and Name

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Table 2-76. Structure Window Popup Menu (cont.)

Popup Menu Item Description
Show Lists the design unit types that are currently
displayed.
• Processes
• Functions
• Packages
• Tasks
• Statement
• VPackages
• VITypedef
• SVClass
• Class Instances
• Capacity
• Change Filter

Display Source Code of a Structure Window Object

You can highlight the line of code that declares a given object in the following ways:

1. Double-click on an object — Opens the file in a new Source window, or activates the
file if it is already open.
2. Single-click on an object — Highlights the code if the file is already showing in an
active Source window.

Add Structure Window Objects to Other Windows

You can add objects from the Structure window to the Dataflow window, List window, Watch
window or Wave window in the following ways:

• Mouse — Drag and drop

• Menu Selection — Add > To window
• Toolbar — Add Selected to Window Button > Add to window
• Command — add list, add wave, add dataflow
When you drag and drop objects from the Structure window to the Wave, Dataflow, or
Schematic windows, the add wave, add dataflow, and add schematic (respectively) commands
will be reflected in the Transcript window.

Finding Items in the Structure Window

To find items in the Structure window, press Ctrl-F on your keyboard with the Structure
window active. This opens the Find bar at the bottom of the window. See the Using the Find and

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Filter Functions section for details. As you type in the Find field, a popup window opens to
display a list of matches (Figure 2-104).

Figure 2-104. Find Mode Popup Displays Matches

The structure window Find bar supports hierarchical searching to limit the regions of a search,
searching by Design Unit name, case sensitive search, and exact match. The forward slash (/)
character is used to separate the search words. A double slash (//) is used to specify a recursive
search from the double slash down the hierarchy. For example:

foo — search the entire design space for regions containing "foo" in it’s name.
/foo — search the top of the design hierarchy for regions containing "foo".
/foo/bar — search for regions containing "foo" at the top, and then regions containing
"bar".
/foo//bar — search for regions containing "bar" recursively below all top level regions
containing "foo".
To search for a name that contains the slash (/) character, escape the slash using a backslash (\).
For example: \/bar.

When you double-click any item in the match list that item is highlighted in the Structure
window and the popup is removed. The search can be canceled by clicking on the ‘x’ button or
by pressing the Esc key on your keyboard.

With 'Search While Typing' enabled (the default) each keypress that changes the pattern restarts
the search immediately.

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Filtering Structure Window Objects

You can control the types of information available in the Structure window through the View >
Filter menu items.

Processes — Implicit wire processes

Functions — Verilog and VHDL Functions
Packages — VHDL Packages
Tasks — Verilog Tasks
Statement — Verilog Statements
SVClass— SystemVerilog class instances
VlPackage — Verilog Packages
VlTypedef — Verilog Type Definitions
Leaf Instances — Verilog cell instances or
VHDL architecture instance.
Capacity — Memory capacity design unit

GUI Elements of the Structure Window

This section describes GUI elements specific to this Window. For a complete list of all columns
in the Structure window and a description of their contents, see Table 2-77.

Column Descriptions
The table below lists columns in the Structure window with a description of their contents
(Table 2-77).

Table 2-77. Columns in the Structure Window

Column name Description
Design Unit The name of the design unit
Design Unit Type The type of design unit
Visibility The +acc settings used for compilation/optimization of that design unit

Transcript Window
The Transcript window maintains a running history of commands that are invoked and
messages that occur as you work with ModelSim. When a simulation is running, the Transcript
displays a VSIM prompt, allowing you to enter command-line commands from within the
graphic interface.

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You can scroll backward and forward through the current work history by using the vertical
scrollbar. You can also use arrow keys to recall previous commands, or copy and paste using
the mouse within the window (see Main and Source Window Mouse and Keyboard Shortcuts
for details).

Displaying the Transcript Window

The Transcript window is always open in the Main window and cannot be closed.

Viewing Data in the Transcript Window

The Transcript tab contains the command line interface, identified by the ModelSim prompt,
and the simulation interface, identified by the VSIM prompt.

Saving the Transcript File

Variable settings determine the filename used for saving the transcript. If either PrefMain(file)
in the .modelsim file or TranscriptFile in the [Link] file is set, then the transcript output
is logged to the specified file. By default the TranscriptFile variable in [Link] is set to
transcript. If either variable is set, the transcript contents are always saved and no explicit
saving is necessary.

If you would like to save an additional copy of the transcript with a different filename, click in
the Transcript window and then select File > Save As, or File > Save. The initial save must be
made with the Save As selection, which stores the filename in the Tcl variable
PrefMain(saveFile). Subsequent saves can be made with the Save selection. Since no
automatic saves are performed for this file, it is written only when you invoke a Save command.
The file is written to the specified directory and records the contents of the transcript at the time
of the save.

Refer to Creating a Transcript File for more information about creating, locating, and saving a
transcript file.

Saving a Transcript File as a Macro (DO file)

1. Open a saved transcript file in a text editor.
2. Remove all commented lines leaving only the lines with commands.
3. Save the file as <name>.do.
Refer to the do command for information about executing a DO file.

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Changing the Number of Lines Saved in the Transcript Window

By default, the Transcript window retains the last 5000 lines of output from the transcript. You
can change this default by selecting Transcript > Saved Lines. Setting this variable to 0
instructs the tool to retain all lines of the transcript.

Colorizing the Transcript

By default, all Transcript window messages are printed in blue. You may colorized Transcript
messages according to severity as follows:

1. Select Tools > Edit Preferences from the Main window menus.
2. In the Preferences window select the By Name tab.
3. Expand the list of Preferences under "Main."
4. Select the colorizeTranscript preference and click the Change Value button.
5. Enter "1" in the Change Main Preference Value dialog and click OK (Figure 2-105).

Figure 2-105. Changing the colorizeTranscript Preference Value

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Disabling Creation of the Transcript File

You can disable the creation of the transcript file by using the following ModelSim command
immediately after ModelSim starts:

transcript file ""

Performing an Incremental Search

The Transcript tab includes an Find function (Figure 2-106) that allows you to do an
incremental search for specific text. To activate the Find bar select Edit > Find from the menus
or click the Find icon in the toolbar. For more information see Using the Find and Filter
Functions.

Figure 2-106. Transcript Window with Find Toolbar

Using Automatic Command Help

When you start typing a command at the prompt, a dropdown box appears which lists the
available commands matching what has been typed so far. You may use the Up and Down
arrow keys or the mouse to select the desired command. When a unique command has been
entered, the command usage is presented in the drop down box.

You can toggle this feature on and off by selecting Help > Command Completion.

Using drivers And readers Command Results

The output from the drivers and readers commands, which is displayed in the Transcript
window as hypertext links, allows you to right-click to open a drop-down menu and to quickly
add signals to various windows. It also includes a "View Declaration" item to open the source
definition of the signal.

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Figure 2-107. drivers Command Results in Transcript

Using Transcript Menu Items

When the Transcript window is active, a "Transcript" menu selection appears in the Main
window menu bar. The following items may be selected when you open the Transcript menu:

• Adjust Font Scaling — Displays the Adjust Scaling dialog box, which allows you to
adjust how fonts appear for your display environment. Directions are available in the
dialog box.
• Transcript File — Allows you to change the default name used when saving the
transcript file. The saved transcript file will contain all the text in the current transcript
file.
• Command History — Allows you to change the default name used when saving
command history information. This file is saved at the same time as the transcript file.
• Save File — Allows you to change the default name used when selecting File > Save
As.
• Saved Lines — Allows you to change how many lines of text are saved in the transcript
window. Setting this value to zero (0) saves all lines.
• Line Prefix — Allows you to change the character(s) that precedes the lines in the
transcript.
• Update Rate — Allows you to change the length of time (in ms) between transcript
refreshes.
• ModelSim Prompt — Allows you to change the string used for the command line
prompt.
• VSIM Prompt — Allows you to change the string used for the simulation prompt.
• Paused Prompt — Allows you to change the string used for when the simulation is
paused.

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Transcript Toolbar Items

When undocked, the Transcript window allows access to the following toolbars:

• Standard Toolbar
• Help Toolbar

Watch Window
The Watch window shows values for signals and variables at the current simulation time, allows
you to explore the hierarchy of object oriented designs. Unlike the Objects or Locals windows,
the Watch window allows you to view any signal or variable in the design regardless of the
current context. You can view the following objects:

• VHDL objects — signals, aliases, generics, constants, and variables

• Verilog objects — nets, registers, variables, named events, and module parameters
• Virtual objects — virtual signals and virtual functions
The address of an object, if one can be obtained, is displayed in the title in parentheses as shown
in Figure 2-108.

Items displayed in red are values that have changed during the previous Run command. You can
change the radix of displayed values by selecting an item, right-clicking to open a popup
context menu, then selecting Properties.

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Figure 2-108. Watch Window

Items are displayed in a scrollable, hierarchical list, such as in Figure 2-109 where extended
SystemVerilog classes hierarchically display their super members.

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Figure 2-109. Scrollable Hierarchical Display

Two Ref handles that refer to the same object will point to the same Watch window box, even if
the name used to reach the object is different. This means circular references will be draw as
circular.

Selecting a line item in the window adds the item’s full name to the global selection. This
allows you to paste the full name in the Transcript (by simply clicking the middle mouse button)
or other external application that accepts text from the global selection.

Adding Objects to the Watch Window

To add objects to the Watch window, drag -and-drop objects from the Structure window or from
any of the following windows: List, Locals, Objects, Source, and Wave. You can also use the
“Add Selected to Window Button”. You can also use the add watch command.

Expanding Objects to Show Individual Bits

If you add an array or record to the window, you can view individual bit values by double-
clicking the array or record. As shown in Figure 2-110, /ram_tb/spram4/mem has been
expanded to show all the individual bit values. Notice the arrow that "ties" the array to the
individual bit display.

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Figure 2-110. Expanded Array

Grouping and Ungrouping Objects

You can group objects in the window so they display and move together. Select the objects,
then right click one of the objects and choose Group.

In Figure 2-111, two different sets of objects have been grouped together.

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Figure 2-111. Grouping Objects in the Watch Window

To ungroup them, right-click the group and select Ungroup.

Saving and Reloading Format Files

You can save a format file (a DO file, actually) that will redraw the contents of the window.
Right-click anywhere in the window and select Save Format. The default name of the format
file is [Link].

Once you have saved the file, you can reload it by right-clicking and selecting Load Format.

Wave Window
The Wave window, like the List window, allows you to view the results of your simulation. In
the Wave window, however, you can see the results as waveforms and their values.

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Wave Window

Figure 2-112. Wave Window

Add Objects to the Wave Window

You can add objects to the Wave window from other windows in the following ways:

• Mouse — Drag and drop.

• Mouse — Click the middle mouse button when the cursor is over an object or group of
objects in the Objects or Locals windows. The specified object(s) are added to the Wave
Window.
• Toolbar — Click-and-hold the “Add Selected to Window Button” to specify where
selected signals are placed: above the Insertion Point Bar in the Pathnames Pane,
appended after the Insertion Pointer in the Pathnames Pane, at the top or the end of the
Pathnames Pane.
• Command line — Use the add wave command.
When you drag and drop objects into the Wave window, the add wave command is reflected in
the Transcript window.

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Refer to Adding Objects to the Wave Window for more information about adding objects to the
Wave window.

Wave Window Panes

The Wave window is divided into a number of window panes. All window panes in the Wave
window can be resized by clicking and dragging the bar between any two panes.

Pathname Pane
The pathname pane displays signal pathnames. Signals can be displayed with full pathnames, as
shown here, or with any number of path elements. You can increase the size of the pane by
clicking and dragging on the right border. The selected signal is highlighted.

The white bar along the left margin indicates the selected Wave window or pane of a split wave
window (see Splitting Wave Window Panes).

Insertion Point Bar

You can select the location for inserting signals by placing the cursor over the left white bar in
the Pathnames Pane. The white arrow and green bar indicate the selected location for the
insertion pointer. Clicking the left mouse button sets the new insertion pointer.

Figure 2-113. Pathnames Pane

Values Pane
The values pane displays the values of the displayed signals. You can resize the values pane by
clicking on and dragging the right border. Some signals may be too wide (too many bits) for

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their values to be fully displayed. Use the scroll bar at the bottom of the pane to see the entire
signal value. Small signal values will remain in view while scrolling.

The radix for each signal can be symbolic, binary, octal, decimal, unsigned, hexadecimal,
ASCII, or default. The default radix for all signals can be set by selecting Simulate > Runtime
Options.

Note
When the symbolic radix is chosen for SystemVerilog reg and integer types, the values
are treated as binary. When the symbolic radix is chosen for SystemVerilog bit and int
types, the values are considered to be decimal.

To change the radix for just the selected signal or signals, select Wave > Format > Radix >
Global Signal Radix from the menus, or right-click the selected signal(s) and select Radix >
Global Signal Radix from the popup menu. This opens the Global Signal Radix dialog
(Figure 2-114), where you may select a radix. This sets the radix for the selected signal(s) in the
Wave window and every other window where the signal appears.

Figure 2-114. Setting the Global Signal Radix from the Wave Window

The data in this pane is similar to that shown in the Objects Window, except that the values
change dynamically whenever a cursor in the waveform pane is moved.

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Figure 2-115. Values Pane

Waveform Pane
Figure 2-116 shows waveform pane, which displays waveforms that correspond to the
displayed signal pathnames. It can also display as many as 20 user-defined cursors. Signal
values can be displayed in analog step, analog interpolated, analog backstep, literal, logic, and
event formats. You can set the format of each signal individually by right-clicking the signal in
the pathname or values panes and choosing Format from the popup menu. The default format is
Logic.

If you place your mouse pointer on a signal in the waveform pane, a popup menu displays with
information about the signal. You can toggle this popup on and off in the Wave Window
Properties dialog box.

Figure 2-116. Waveform Pane

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Analog Sidebar Toolbox

When the waveform pane contains an analog waveform, you can hover your mouse pointer over
the left edge of the waveform to display the Analog Sidebar toolbox (see Figure 2-117). This
toolbox shows a group of icons that gives you quick access to actions you can perform on the
waveform display, as described in Table 2-78.

Figure 2-117. Analog Sidebar Toolbox

Table 2-78. Analog Sidebar Icons

Icon Action Description
Open Wave Properties Opens the Format tab of the Wave Properties
dialog box, with the Analog format already
selected. This dialog box duplicates the Wave
Analog dialog box displayed by choosing
Format > Format... > Analog (custom)
from the main menu.
Toggle Row Height Changes the height of the row that contains the
analog waveform. Toggles the height between
the Min and Max values (in pixels) you specified
in the Open Wave Properties dialog box under
Analog Display.
Rescale to fit Y data Changes the waveform height so that it fits top-
to-bottom within the current height of the row.
Show menu of other actions Displays
• View Min Y
• View Max Y
• Overlay Above
• Overlay Below
• Colorize All
• Colorize Selected

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Table 2-78. Analog Sidebar Icons (cont.)

Icon Action Description
Drag to resize waveform height Creates an up/down dragging arrow that you can
use to temporarily change the height of the row
containing the analog waveform.

Cursor Pane
Figure 2-118 shows the Cursor Pane, which displays cursor names, cursor values and the cursor
locations on the timeline. You can link cursors so that they move across the timeline together.
See Linking Cursors in the Waveform Analysis chapter.

Figure 2-118. Cursor Pane

On the left side of this pane is a group of icons called the Cursor and Timeline Toolbox (see
Figure 2-119). This toolbox gives you quick access to cursor and timeline features and
configurations. See Measuring Time with Cursors in the Wave Window for more information.

Cursor and Timeline Toolbox

The Cursor and Timeline Toolbox displays several icons that give you quick access to cursor
and timeline features.

Figure 2-119. Toolbox for Cursors and Timeline

The action for each toolbox icon is shown in Table 2-79.

Table 2-79. Icons and Actions
Icon Action
Toggle leaf name <-> full names

Edit grid and timeline properties

Insert cursor

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Graphical User Interface
Wave Window

Table 2-79. Icons and Actions (cont.)

Icon Action
Toggle lock on cursor to prevent it from moving

Edit this cursor

Remove this cursor

The Toggle leaf names <-> full names icon allows you to switch from displaying full
pathnames (the default) in the Pathnames Pane to displaying leaf or short names. You can also
control the number of path elements in the Wave Window Preferences dialog. Refer to
Hiding/Showing Path Hierarchy.

The Edit grid and timeline properties icon opens the Wave Window Properties dialog to the
Grid & Timeline tab (Figure 2-120).

Figure 2-120. Editing Grid and Timeline Properties

The Grid Configuration selections allow you to set grid offset, minimum grid spacing, and grid
period; or you can reset the grid configuration to default values.

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Wave Window

The Timeline Configuration selections give you a user-definable time scale. You can display
simulation time on the timeline or a clock cycle count. The time value is scaled appropriately
for the selected unit.

By default, the timeline will display time delta between any two adjacent cursors. By clicking
the Show frequency in cursor delta box, you can display the cursor delta as a frequency
instead.

Adding Cursors to the Wave Window

You can add cursors when the Wave window is active by:

• clicking the Insert Cursor icon.

• choosing Add > Wave > Cursor from the menu bar
• pressing the “A” key while the mouse cursor is in the cursor pane.
• right clicking in the cursor pane at the time you want place a cursor, then selecting New
Cursor.
Each added cursor is given a default cursor name (Cursor 2, Cursor 3, and so forth.) which you
can be change by right-clicking the cursor name, then typing in a new name, or by clicking the
Edit this cursor icon. The Edit this cursor icon opens the Cursor Properties dialog box
(Figure 2-121), where you assign a cursor name and time. You can also lock the cursor to the
specified time.

Figure 2-121. Cursor Properties Dialog

Messages Bar
The messages bar, located at the top of the Wave window, contains indicators pointing to the
times at which a message was output from the simulator. By default, the indicators are not
displayed. To turn on message indicators, use the -msgmode argument with the vsim command
or use the msgmode variable in the [Link] file.

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Graphical User Interface
Wave Window

Figure 2-122. Wave Window - Message Bar

The message indicators (the down-pointing arrows) are color-coded as follows:

• Red — Indicates an error.

• Yellow — Indicates a warning.
• Green — Indicates a note.
• Grey — Indicates any other type of message.

You can use the Message bar in the following ways.

• Move the cursor to the next message — You can do this in two ways:
o Click on the word “Messages” in the message bar to cycle the cursor to the next
message after the current cursor location.
o Click anywhere in the message bar, then use Tab or Shift+Tab to cycle the cursor
between error messages either forward or backward, respectively.
• Display the Message Viewer Window — Double-click anywhere amongst the message
indicators.
• Display, in the Message Viewer window, the message entry related to a specific
indicator — Double-click on any message indicator.
This function only works if you are using the Message Viewer in flat mode. To display
your messages in flat mode:
a. Right-click in the Message Viewer and select Display Options
b. In the Message Viewer Display Options dialog box, deselect Display with
Hierarchy.

View Objects Window Button

This button opens the Objects window with a single click. However, if you click-and-hold the
button you can access additional options via a dropdown menu, as shown in Figure 2-123

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Wave Window

Figure 2-123. View Objects Window Dropdown Menu

Wave Window Icons

The following icons can be found in the Wave window.

Table 2-80. Window Icons

Icon shape Example Description
FSM button opens the FSM Viewer window

Null verilog/system verilog name event

Objects You Can View in the Wave Window

The following types of objects can be viewed in the Wave window

• VHDL objects (indicated by a dark blue diamond) — signals, aliases, process variables,
and shared variables
• Verilog objects (indicated by a light blue diamond) — nets, registers, variables, and
named events
The GUI displays inout variables of a clocking block separately, where the output of the
inout variable is appended with “__o”, for example you would see following two
objects:
clock1.c1 /input portion of the inout c1
clock1.c1__o /output portion of the inout c1

This display technique also applies to the Objects window

• Verilog transactions (indicated by a blue four point star) — see for more information
• Virtual objects (indicated by an orange diamond) — virtual signals, buses, and
functions, see; Virtual Objects for more information
The data in the object values pane is very similar to the Objects window, except that the values
change dynamically whenever a cursor in the waveform pane is moved.

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Graphical User Interface
Wave Window

At the bottom of the waveform pane you can see a time line, tick marks, and the time value of
each cursor’s position. As you click and drag to move a cursor, the time value at the cursor
location is updated at the bottom of the cursor.

You can resize the window panes by clicking on the bar between them and dragging the bar to a
new location.

Waveform and signal-name formatting are easily changed via the Format menu. You can reuse
any formatting changes you make by saving a Wave window format file (see Saving the
Window Format).

Wave Window Toolbar

The Wave window (in the undocked Wave window) gives you quick access to the following
toolbars:

• Standard Toolbar
• Compile Toolbar
• Simulate Toolbar
• Step Toolbar
• Wave Cursor Toolbar
• Wave Edit Toolbar
• Wave Toolbar
• Wave Compare Toolbar
• Zoom Toolbar
• Wave Expand Time Toolbar

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Chapter 3
Protecting Your Source Code

As today’s IC designs increase in complexity, silicon manufacturers are leveraging third-party

intellectual property (IP) to maintain or shorten design cycle times. This third-party IP is often
sourced from several IP authors, each of whom may require different levels of protection in
EDA tool flows. The number of protection/encryption schemes developed by IP authors has
complicated the use of protected IP in design flows made up of tools from different EDA
providers.

ModelSim’s encryption solution allows IP authors to deliver encrypted IP code for a wide range
of EDA tools and design flows. You can, for example, make module ports, parameters, and
specify blocks publicly visible while keeping the implementation private.

ModelSim supports VHDL, Verilog, and SystemVerilog IP code encryption by means of

protected encryption envelopes. VHDL encryption is defined by the IEEE Std 1076-2008,
section 24.1 (titled “Protect tool directives”) and Annex H, section H.3 (titled “Digital
envelopes”). Verilog/SystemVerilog encryption is defined by the IEEE Std 1364-2005, section
28 (titled “Protected envelopes”) and Annex H, section H.3 (titled “Digital envelopes”). The
protected envelopes usage model, as presented in Annex H section H.3 of both standards, is the
recommended methodology for users of VHDL’s `protect and Verilog's `pragma protect
compiler directives. We recommend that you obtain these specifications for reference.

In addition, Questa supports the recommendations from the IEEE P1735 working group for
encryption interoperability between different encryption and decryption tools. The current
recommendations are denoted as “version 1” by P1735. They address use model, algorithm
choices, conventions, and minor corrections to the HDL standards to achieve useful
interoperability.

ModelSim also supports encryption using the vcom/vlog -nodebug command.

Creating Encryption Envelopes

Encryption envelopes define a region of code to be protected with Protection Expressions. The
protection expressions (`protect for VHDL and `pragma protect for Verilog/SystemVerilog)
specify the encryption algorithm used to protect the source code, the encryption key owner, the
key name, and envelope attributes.

Creating encryption envelopes requires that you:

• identify the region(s) of code to be encrypted,

• enclose the code to be encrypted within protection directives, and

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Protecting Your Source Code
Creating Encryption Envelopes

• compile your code with ModelSim encryption utilities - vencrypt for

Verilog/SystemVerilog or vhencrypt for VHDL - or with the vcom/vlog +protect
command.
The flow diagram for creating encryption envelopes is shown in Figure 3-1.

Figure 3-1. Create an Encryption Envelope

Symmetric and asymmetric keys can be combined in encryption envelopes to provide the safety
of asymmetric keys with the efficiency of symmetric keys (see Encryption and Encoding
Methods). Encryption envelopes can also be used by the IP author to produce encrypted source
files that can be safely decrypted by multiple authors. For these reasons, encryption envelopes
are the preferred method of protection.

Configuring the Encryption Envelope

The encryption envelope may be configured two ways:

1. The encryption envelope may contain the textual design data to be encrypted
(Example 3-1).

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Creating Encryption Envelopes

2. The encryption envelope may contain `include compiler directives that point to files
containing the textual design data to be encrypted (Example 3-2). See Using the `include
Compiler Directive (Verilog only).

Example 3-1. Encryption Envelope Contains Verilog IP Code to be Protected

module test_dff4(output [3:0] q, output err);

parameter WIDTH = 4;
parameter DEBUG = 0;
reg [3:0] d;
reg clk;

dff4 d4(q, clk, d);

assign err = 0;

initial
begin
$dump_all_vpi;
$dump_tree_vpi(test_dff4);
$dump_tree_vpi(test_dff4.d4);
$dump_tree_vpi("test_dff4");
$dump_tree_vpi("test_dff4.d4");
$dump_tree_vpi("test_dff4.d", "test_dff4.clk", "test_dff4.q");
$dump_tree_vpi("test_dff4.d4.d0", "test_dff4.d4.d3");
$dump_tree_vpi("test_dff4.d4.q", "test_dff4.[Link]");
end
endmodule

module dff4(output [3:0] q, input clk, input [3:0] d);

`pragma protect data_method = "aes128-cbc"
`pragma protect author = "IP Provider"
`pragma protect author_info = "Widget 5 version 3.2"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect begin
dff_gate d0(q[0], clk, d[0]);
dff_gate d1(q[1], clk, d[1]);
dff_gate d2(q[2], clk, d[2]);
dff_gate d3(q[3], clk, d[3]);
endmodule // dff4

module dff_gate(output q, input clk, input d);

wire preset = 1;
wire clear = 1;

nand #5
g1(l1,preset,l4,l2),
g2(l2,l1,clear,clk),
g3(l3,l2,clk,l4),
g4(l4,l3,clear,d),
g5(q,preset,l2,qbar),
g6(qbar,q,clear,l3);
endmodule
`pragma protect end

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Protecting Your Source Code
Creating Encryption Envelopes

In this example, the Verilog code to be encrypted follows the `pragma protect begin
expression and ends with the `pragma protect end expression. If the code had been written in
VHDL, the code to be protected would follow a `protect BEGIN PROTECTED expression
and would end with a `protect END PROTECTED expression.

Example 3-2. Encryption Envelope Contains `include Compiler Directives

`timescale 1ns / 1ps

`cell define

module dff (q, d, clear, preset, clock);

output q;
input d, clear, preset, clock;
reg q;

`pragma protect data_method = "aes128-cbc"

`pragma protect author = "IP Provider", author_info = "Widget 5 v3.2"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect begin

ìnclude diff.v
ìnclude prim.v
ìnclude top.v

`pragma protect end

always @(posedge clock)

q = d;

endmodule

`endcelldefine

In Example 3-2, the entire contents of diff.v, prim.v, and top.v will be encrypted.

For a more technical explanation, see How Encryption Envelopes Work.

Protection Expressions
The encryption envelope contains a number of `pragma protect (Verilog/SystemVerilog) or
`protect (VHDL) expressions. The following protection expressions are expected when
creating an encryption envelope:

• data_method — defines the encryption algorithm that will be used to encrypt the
designated source text. ModelSim supports the following encryption algorithms: des-
cbc, 3des-cbc, aes128-cbc, aes256-cbc, blowfish-cbc, cast128-cbc, and rsa.
• key_keyowner — designates the owner of the encryption key.

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Creating Encryption Envelopes

• key_keyname — specifies the keyowner’s key name.

• key_method — specifies an encryption algorithm that will be used to encrypt the key.

Note
The combination of key_keyowner and key_keyname expressions uniquely identify a
key. The key_method is required with these two expressions to complete the definition of
the key.

• begin — designates the beginning of the source code to be encrypted.

• end — designates the end of the source code to be encrypted

Note
Encryption envelopes cannot be nested. A `pragma protect begin/end pair cannot bracket
another `pragma protect begin/end pair.

Optional `protect (VHDL) or `pragma protect (Verilog/SystemVerilog) expressions that may

be included are as follows:

• author — designates the IP provider.

• author_info — designates optional author information.
• encoding — specifies an encoding method. The default encoding method, if none is
specified, is “base 64.”
If a number of protection expressions occur in a single protection directive, the expressions are
evaluated in sequence from left to right. In addition, the interpretation of protected envelopes is
not dependent on this sequence occurring in a single protection expression or a sequence of
protection expressions. However, the most recent value assigned to a protection expression
keyword will be the one used.

Unsupported Protection Expressions

Optional protection expressions that are not currently supported include:

• any digest_* expression

• decrypt_license
• runtime_license
• viewport

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Protecting Your Source Code
Creating Encryption Envelopes

Using the `include Compiler Directive (Verilog only)

If any `include directives occur within a protected region of Verilog code and you use vlog
+protect to compile, the compiler generates a copy of the include file with a “.vp” or a “.svp”
extension and encrypts the entire contents of the include file. For example, if we have a header
file, header.v, with the following source code:

initial begin
a <= b;
b <= c;
end

and the file we want to encrypt, top.v, contains the following source code:

module top;
`pragma protect begin
`include "header.v"
`pragma protect end
endmodule

then, when we use the vlog +protect command to compile, the source code of the header file
will be encrypted. If we could decrypt the resulting work/[Link] file it would look like:

module top;
`pragma protect begin
initial begin
a <= b;
b <= c;
end
`pragma protect end
endmodule

In addition, vlog +protect creates an encrypted version of header.v in work/[Link].

When using the vencrypt compile utility (see Delivering IP Code with Undefined Macros), any
`include statements will be treated as text just like any other source code and will be encrypted
with the other Verilog/SystemVerilog source code. So, if we used the vencrypt utility on the
top.v file above, the resulting work/[Link] file would look like the following (if we could
decrypt it):

module top;
`protect
`include "header.v"
`endprotect
endmodule

The vencrypt utility will not create an encrypted version of header.h.

When you use vlog +protect to generate encrypted files, the original source files must all be
complete Verilog or SystemVerilog modules or packages. Compiler errors will result if you
attempt to perform compilation of a set of parameter declarations within a module. (See also
Compiling with +protect.)

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Creating Encryption Envelopes

You can avoid such errors by creating a dummy module that includes the parameter
declarations. For example, if you have a file that contains your parameter declarations and a file
that uses those parameters, you can do the following:

module dummy;
`protect
ìnclude "params.v" // contains various parameters
ìnclude "tasks.v" // uses parameters defined in params.v
èndprotect
endmodule

Then, compile the dummy module with the +protect switch to generate an encrypted output file
with no compile errors.

vlog +protect dummy.v

After compilation, the work library will contain encrypted versions of params.v and tasks.v,
called [Link] and [Link]. You may then copy these encrypted files out of the work
directory to more convenient locations. These encrypted files can be included within your
design files; for example:

module main
'include "[Link]"
'include "[Link]"
...

Using Portable Encryption for Multiple Tools

An IP author can use the concept of multiple key blocks to produce code that is secure and
portable across any tool that supports Version 1 recommendations from the IEEE P1735
working group. This capability is not language-specific - it can be used for VHDL or Verilog.

To illustrate, suppose the author wants to modify the following VHDL sample file so the
encrypted model can be decrypted and simulated by both ModelSim and by a hypothetical
company named XYZ inc.

========== sample file ==========

-- The entity "ip1" is not protected

...
entity ip1 is
...
end ip1;

-- The architecture "a" is protected

-- The internals of "a" are hidden from the user
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" )
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect KEY_BLOCK
`protect begin

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Creating Encryption Envelopes

architecture a of ip1 is
...
end a;
`protect end

-- Both the entity "ip2" and its architecture "a" are completely protected
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" )
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect KEY_BLOCK
`protect begin
library ieee;
use ieee.std_logic_1164.all;
entity ip2 is
...
end ip2;
architecture a of ip2 is
...
end a;
`protect end

========== end of sample file ==========

The author does this by writing a key block for each decrypting tool. If XYZ publishes a public
key, the two key blocks in the IP source code might look like the following:

`protect key_keyowner = "Mentor Graphics Corporation"

`protect key_method = "rsa"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect KEY_BLOCK
`protect key_keyowner = "XYZ inc"
`protect key_method = "rsa"
`protect key_keyname = "XYZ-keyPublicKey"
`protect key_public_key = <public key of XYZ inc.>
`protect KEY_BLOCK

The encrypted code would look very much like the sample file, with the addition of another key
block:

`protect key_keyowner = "XYZ inc"

`protect key_method = "rsa"
`protect key_keyname = "XYZ-keyPublicKey"
`protect KEY_BLOCK
<encoded encrypted key information for "XYZ inc">

ModelSim uses its key block to determine the encrypted session key and XYZ Incorporated
uses the second key block to determine the same key. Consequently, both implementations
could successfully decrypt the code.

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Protecting Your Source Code
Compiling with +protect

Note
The IP owner is responsible for obtaining the appropriate key for the specific tool(s)
protected IP is intended for, and should validate the encrypted results with those tools to
insure his IP is protected and will function as intended in those tools.

Compiling with +protect

To encrypt IP code with ModelSim, the +protect argument must be used with either the vcom
command (for VHDL) or the vlog command (for Verilog and SystemVerilog). For example, if a
Verilog source code file containing encryption envelopes is named encrypt.v, it would be
compiled as follows:

vlog +protect encrypt.v

When +protect is used with vcom or vlog, encryption envelope expressions are transformed into
decryption envelope expressions and decryption content expressions. Source text within
encryption envelopes is encrypted using the specified key and is recorded in the decryption
envelope within a data_block. The new encrypted file is created with the same name as the
original unencrypted file but with a ‘p’ added to the filename extension. For Verilog, the
filename extension for the encrypted file is .vp; for SystemVerilog it is .svp, and for VHDL it is
.vhdp. This encrypted file is placed in the current work library directory.

You can designate the name of the encrypted file using the +protect=<filename> argument
with vcom or vlog as follows:

vlog +protect=[Link] encrypt.v

Example 3-3 shows the resulting source code when the Verilog IP code used in Example 3-1 is
compiled with vlog +protect.

Example 3-3. Results After Compiling with vlog +protect

module test_dff4(output [3:0] q, output err);

parameter WIDTH = 4;
parameter DEBUG = 0;
reg [3:0] d;
reg clk;
dff4 d4(q, clk, d);
assign err = 0;
initial
begin
$dump_all_vpi;
$dump_tree_vpi(test_dff4);
$dump_tree_vpi(test_dff4.d4);
$dump_tree_vpi("test_dff4");
$dump_tree_vpi("test_dff4.d4");
$dump_tree_vpi("test_dff4.d", "test_dff4.clk", "test_dff4.q");
$dump_tree_vpi("test_dff4.d4.d0", "test_dff4.d4.d3");
$dump_tree_vpi("test_dff4.d4.q", "test_dff4.[Link]");
end

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Protecting Your Source Code
The Runtime Encryption Model

endmodule

module dff4(output [3:0] q, input clk, input [3:0] d);

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "Model Technology"
`pragma protect encrypt_agent_info = "6.6a"
`pragma protect author = "IP Provider"
`pragma protect author_info = "Widget 5 version 3.2"
`pragma protect data_method = "aes128-cbc"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect key_method = "rsa"
`pragma protect key_block encoding = (enctype = "base64", line_length =
64, bytes = 128)
SdI6t9ewd9GE4va+2BgfnRuBNc45wVwjyPeSD/5qnojnbAHdpjWa/O/Tyhw0aq1T
NbDGrDg6I5dbzbLs5UQGFtB2lgOBMnE4JTpGRfV0sEqUdibBHiTpsNrbLpp1iJLi
7l4kQhnivnUuCx87GuqXIf5AaoLGBz5rCxKyA47ElQM=
`pragma protect data_block encoding = (enctype = "base64", line_length =
64, bytes = 496)
efkkPz4gJSO6zZfYdr37fqEoxgLZ3oTgu8y34GTYkO0ZZGKkyonE9zDQct5d0dfe
/BZwoHCWnq4xqUp2dxF4x6cw6qBJcSEifCPDY1hJASoVX+7owIPGnLh5U0P/Wohp
LvkfhIuk2FENGZh+y3rWZAC1vFYKXwDakSJ3neSglHkwYr+T8vGviohIPKet+CPC
d/RxXOi2ChI64KaMY2/fKlerXrnXV7o9ZIrJRHL/CtQ/uxY7aMioR3/WobFrnuoz
P8fH7x/I30taK25KiL6qvuN0jf7g4LiozSTvcT6iTTHXOmB0fZiC1eREMF835q8D
K5lzU+rcb17Wyt8utm71WSu+2gtwvEp39G6R60fkQAuVGw+xsqtmWyyIOdM+PKWl
sqeoVOsBUHFY3x85F534PQNVIVAT1VzFeioMxmJWV+pfT3OlrcJGqX1AxAG25CkY
M1zF77caF8LAsKbvCTgOVsHb7NEqOVTVJZZydVy23VswClYcrxroOhPzmqNgn4pf
zqcFpP+yBnt4UELa63Os6OfsAu7DZ/4kWPAwExyvaahI2ciWs3HREcZEO+aveuLT
gxEFSm0TvBBsMwLc7UvjjC0aF1vUWhDxhwQDAjYT89r2h1G7Y0PGlGOo24s0/A2+
TjdCcOogiGsTDKx6Bxf91g==
`pragma protect end_protected

In this example, the `pragma protect data_method expression designates the encryption
algorithm used to encrypt the Verilog IP code. The key for this encryption algorithm is also
encrypted – in this case, with the RSA public key. The key is recorded in the key_block of the
protected envelope. The encrypted IP code is recorded in the data_block of the envelope.
ModelSim allows more than one key_block to be included so that a single protected envelope
can be encrypted by ModelSim then decrypted by tools from different users.

The Runtime Encryption Model

After you compile with the +protect compile argument, all source text, identifiers, and line
number information are hidden from the end user in the resulting compiled object. ModelSim
cannot locate or display any information of the encrypted regions. Specifically, this means that:

• a Source window will not display the design units’ source code
• a Structure window will not display the internal structure
• the Objects window will not display internal signals
• the Processes window will not display internal processes

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Protecting Your Source Code
Language-Specific Usage Models

• the Locals window will not display internal variables

• none of the hidden objects may be accessed through the Dataflow window or with
ModelSim commands.

Language-Specific Usage Models

This section includes the following usage models that are language-specific:

• Usage Models for Protecting Verilog Source Code

o Delivering IP Code with Undefined Macros
o Delivering IP Code with User-Defined Macros
• Usage Models for Protecting VHDL Source Code
o Using the vhencrypt Utility
o Using ModelSim Default Encryption for VHDL
o User-Selected Encryption for VHDL
o Using raw Encryption for VHDL
o Encrypting Several Parts of a VHDL Source File
o Using Portable Encryption for Multiple Tools

Usage Models for Protecting Verilog Source Code

ModelSim’s encryption capabilities support the following Verilog and SystemVerilog usage
models for IP authors and their customers.

• IP authors may use the vencrypt utility to deliver Verilog and SystemVerilog code
containing undefined macros and `directives. The IP user can then define the macros and
`directives and use the code in a wide range of EDA tools and design flows. See
Delivering IP Code with Undefined Macros.
• IP authors may use `pragma protect directives to protect Verilog and SystemVerilog
code containing user-defined macros and `directives. The IP code can be delivered to IP
customers for use in a wide range of EDA tools and design flows. See Delivering IP
Code with User-Defined Macros.

Delivering IP Code with Undefined Macros

The vencrypt utility enables IP authors to deliver VHDL and Verilog/ SystemVerilog IP code
(respectively) that contains undefined macros and `directives. The resulting encrypted IP code
can then be used in a wide range of EDA tools and design flows.

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The recommended encryption usage flow is shown in Figure 3-2.

Figure 3-2. Verilog/SystemVerilog Encryption Usage Flow

1. The IP author creates code that contains undefined macros and `directives.
2. The IP author creates encryption envelopes (see Creating Encryption Envelopes) to
protect selected regions of code or entire files (see Protection Expressions).
3. The IP author uses ModelSim’s vencrypt utility to encrypt Verilog and SystemVerilog
code contained within encryption envelopes. Macros are not pre-processed before
encryption so macros and other `directives are unchanged.
The vencrypt utility produces a file with a .vp or a .svp extension to distinguish it from
non-encrypted Verilog and SystemVerilog files, respectively. The file extension may be
changed for use with simulators other than ModelSim. The original file extension is
preserved if the -d <dirname> argument is used with vencrypt, or if a `directive is used
in the file to be encrypted.
With the -h <filename> argument for vencrypt the IP author may specify a header file
that can be used to encrypt a large number of files that do not contain the `pragma
protect (or proprietary `protect information - see Proprietary Source Code Encryption
Tools) about how to encrypt the file. Instead, encryption information is provided in the

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<filename> specified by -h <filename>. This argument essentially concatenates the

header file onto the beginning of each file and saves the user from having to edit
hundreds of files in order to add in the same `pragma protect to every file. For
example,
vencrypt -h encrypt_head top.v cache.v gates.v memory.v

concatenates the information in the encrypt_head file into each verilog file listed. The
encrypt_head file may look like the following:
`pragma protect data_method = "aes128-cbc"
`pragma protect author = "IP Provider"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect encoding = (enctype = "base64")
`pragma protect begin

Notice, there is no `pragma protect end expression in the header file, just the header
block that starts the encryption. The `pragma protect end expression is implied by the
end of the file.
4. The IP author delivers encrypted IP with undefined macros and `directives.
5. The IP user defines macros and `directives.
6. The IP user compiles the design with vlog.
7. The IP user simulates the design with ModelSim or other simulation tools.

Delivering IP Code with User-Defined Macros

IP authors may use `pragma protect expressions to protect proprietary code containing user-
defined macros and `directives. The resulting encrypted IP code can be delivered to customers
for use in a wide range of EDA tools and design flows. An example of the recommended usage
flow for Verilog and SystemVerilog IP is shown in Figure 3-3.

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Figure 3-3. Delivering IP Code with User-Defined Macros

1. The IP author creates proprietary code that contains user-defined macros and `directives.
2. The IP author creates encryption envelopes with `pragma protect expressions to protect
regions of code or entire files. See Creating Encryption Envelopes and Protection
Expressions.
3. The IP author uses the +protect argument for the vlog command to encrypt IP code
contained within encryption envelopes. The `pragma protect expressions are ignored
unless the +protect argument is used during compile. (See Compiling with +protect.)
The vlog +protect command produces a .vp or a .svp extension for the encrypted file to
distinguish it from non-encrypted Verilog and SystemVerilog files, respectively. The
file extension may be changed for use with simulators other than ModelSim. The
original file extension is preserved if a `directive is used in the file to be encrypted. For
more information, see Compiling with +protect.
4. The IP author delivers the encrypted IP.
5. The IP user simulates the code like any other file.
When encrypting source text, any macros without parameters defined on the command line are
substituted (not expanded) into the encrypted file. This makes certain macros unavailable in the
encrypted source text.

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ModelSim takes every simple macro that is defined with the compile command (vlog) and
substitutes it into the encrypted text. This prevents third party users of the encrypted blocks
from having access to or modifying these macros.

Note
Macros not specified with vlog via the +define+ option are unmodified in the encrypted
block.

For example, the code below is an example of an file that might be delivered by an IP provider.
The filename for this module is [Link].

`pragma protect data_method = "aes128-cbc"

`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect author = "Mentor", author_info = "Mentor_author"
`pragma protect begin
`timescale 1 ps / 1 ps

module example00 ();

ìfdef IPPROTECT
reg ÌPPROTECT ;
reg otherReg ;
initial begin
ÌPPROTECT = 1;
otherReg = 0;

$display("ifdef defined as true");

`define FOO 0
$display("FOO is defined as: ", `FOO);
$display("reg IPPROTECT has the value: ", ÌPPROTECT );
end
èlse
initial begin
$display("ifdef defined as false");
end
èndif

endmodule

`pragma protect end

We encrypt the [Link] module with the vlog command as follows:

vlog +define+IPPROTECT=ip_value +protect=[Link] [Link]

This creates an encrypted file called [Link]. We can then compile this file with a macro
override for the macro “FOO” as follows:

vlog +define+FOO=99 [Link]

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The macro FOO can be overridden by a customer while the macro IPPROTECT retains the
value specified at the time of encryption, and the macro IPPROTECT no longer exists in the
encrypted file.

Usage Models for Protecting VHDL Source Code

ModelSim’s encryption capabilities support the following VHDL usage models.

• IP authors may use `protect directives to create an encryption envelope (see Creating
Encryption Envelopes) for the VHDL code to be protected and use ModelSim’s
vhencrypt utility to encrypt the code. The encrypted IP code can be delivered to IP
customers for use in a wide range of EDA tools and design flows. See Using the
vhencrypt Utility.
• IP authors may use `protect directives to create an encryption envelope (see Creating
Encryption Envelopes) for the VHDL code to be protected and use ModelSim’s default
encryption and decryption actions. The IP code can be delivered to IP customers for use
in a wide range of EDA tools and design flows. See Using ModelSim Default
Encryption for VHDL.
• IP authors may use `protect directives to create an encryption envelope for VHDL code
and select encryption methods and encoding other than ModelSim’s default methods.
See User-Selected Encryption for VHDL.
• IP authors may use “raw” encryption and encoding to aid debugging. See Using raw
Encryption for VHDL.
• IP authors may encrypt several parts of the source file, choose the encryption method for
encrypting the source (the data_method), and use a key automatically provided by
ModelSim. See Encrypting Several Parts of a VHDL Source File.
• IP authors can use the concept of multiple key blocks to produce code that is secure and
portable across different simulators. See Using Portable Encryption for Multiple Tools.
The usage models are illustrated by examples in the sections below.

Note
VHDL encryption requires that the KEY_BLOCK (the sequence of key_keyowner,
key_keyname, and key_method directives) end with a `protect KEY_BLOCK directive.

Using the vhencrypt Utility

The vhencrypt utility enables IP authors to deliver encrypted VHDL IP code to users. The
resulting encrypted IP code can then be used in a wide range of EDA tools and design flows.

1. The IP author creates code.

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2. The IP author creates encryption envelopes (see Creating Encryption Envelopes) to

protect selected regions of code or entire files (see Protection Expressions).
3. The IP author uses ModelSim’s vhencrypt utility to encrypt code contained within
encryption envelopes.
The vhencrypt utility produces a file with a .vhdp or a .vhdlp extension to distinguish it
from non-encrypted VHDL files. The file extension may be changed for use with
simulators other than ModelSim. The original file extension is preserved if the
-d <dirname> argument is used with vhencrypt.
With the -h <filename> argument for vencrypt the IP author may specify a header file
that can be used to encrypt a large number of files that do not contain the `protect
information about how to encrypt the file. Instead, encryption information is provided in
the <filename> specified by -h <filename>. This argument essentially concatenates the
header file onto the beginning of each file and saves the user from having to edit
hundreds of files in order to add in the same `protect to every file. For example,
vhencrypt -h encrypt_head [Link] [Link] [Link] [Link]

concatenates the information in the encrypt_head file into each VHDL file listed. The
encrypt_head file may look like the following:
`protect data_method = "aes128-cbc"
`protect author = "IP Provider"
`protect encoding = (enctype = "base64")
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_method = "rsa"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect KEY_BLOCK
`protect begin

Notice, there is no `protect end expression in the header file, just the header block that
starts the encryption. The `protect end expression is implied by the end of the file.
4. The IP author delivers encrypted IP.
5. The IP user compiles the design with vcom.
6. The IP user simulates the design with ModelSim or other simulation tools.

Using ModelSim Default Encryption for VHDL

Suppose an IP author needs to make a design entity, called IP1, visible to the user so the user
can instantiate the design, but the author wants to hide the architecture implementation from the
user. In addition, suppose that IP1 instantiates entity IP2, which the author wants to hide
completely from the user. The easiest way to accomplish this is to surround the regions to be
protected with `protect begin and `protect end directives and let ModelSim choose default
actions. For this example, all the source code exists in a single file, [Link]:

========== file [Link] ==========

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-- The entity "ip1" is not protected

...
entity ip1 is
...
end ip1;

-- The architecture "a" is protected

-- The internals of "a" are hidden from the user
`protect begin
architecture a of ip1 is
...
end a;
`protect end

-- Both the entity "ip2" and its architecture "a" are completely protected
`protect begin
entity ip2 is
...
end ip2;
architecture a of ip2 is
...
end a;
`protect end

========== end of file [Link] ==========

The IP author compiles this file with the vcom +protect command as follows:

vcom +protect=[Link] [Link]

The compiler produces an encrypted file, [Link] which looks like the following:

========== file [Link] ==========

-- The entity "ip1" is not protected

...
entity ip1 is
...
end ip1;

-- The architecture "a" is protected

-- The internals of "a" are hidden from the user
`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect encoding = ( enctype = "base64" )
`protect KEY_BLOCK
<encoded encrypted session key>
`protect data_method="aes128-cbc"
`protect encoding = ( enctype = "base64" , bytes = 224 )
`protect DATA_BLOCK
<encoded encrypted IP>
`protect END_PROTECTED

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-- Both the entity "ip2" and its architecture "a" are completely protected
`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_method = "rsa"
`protect encoding = ( enctype = "base64" )
`protect KEY_BLOCK
<encoded encrypted session key>
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" , bytes = 224 )
`protect DATA_BLOCK
<encoded encrypted IP>
`protect END_PROTECTED

========== end of file [Link] ==========

When the IP author surrounds a text region using only `protect begin and `protect end,
ModelSim uses default values for both encryption and encoding. The first few lines following
the `protect BEGIN_PROTECTED region in file [Link] contain the key_keyowner,
key_keyname, key_method and KEY_BLOCK directives. The session key is generated into the
key block and that key block is encrypted using the “rsa” method. The data_method indicates
that the default data encryption method is aes128-cbc and the “enctype” value shows that the
default encoding is base64.

Alternatively, the IP author can compile file [Link] with the command:

vcom +protect [Link]

Here, the author does not supply the name of the file to contain the protected source. Instead,
ModelSim creates a protected file, gives it the name of the original source file with a 'p' placed
at the end of the file extension, and puts the new file in the current work library directory. With
the command described above, ModelSim creates file work/[Link]. (See Compiling
with +protect.)

The IP user compiles the encrypted file work/[Link] the ordinary way. The +protect
switch is not needed and the IP user does not have to treat the .vhdp file in any special manner.
ModelSim automatically decrypts the file internally and keeps track of protected regions.

If the IP author compiles the file [Link] and does not use the +protect argument, then the
file is compiled, various `protect directives are checked for correct syntax, but no protected file
is created and no protection is supplied.

ModelSim’s default encryption methods provide an easy way for IP authors to encrypt VHDL
designs while hiding the architecture implementation from the user. It should be noted that the
results are only usable by ModelSim tools.

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User-Selected Encryption for VHDL

Suppose that the IP author wants to produce the same code as in the [Link] file used
above, but wants to provide specific values and not use any default values. To do this the author
adds `protect directives for keys, encryption methods, and encoding, and places them before
each `protect begin directive. The input file would look like the following:

========== file [Link] ==========

-- The entity "ip1" is not protected

...
entity ip1 is
...
end ip1;

-- The architecture "a" is protected

========== end of file [Link] ==========

The data_method directive indicates that the encryption algorithm “aes128-cbc” should be used
to encrypt the source code (data). The encoding directive selects the “base64” encoding method,
and the various key directives specify that the Mentor Graphic key named “MGC-VERIF-SIM-
RSA-1” and the “RSA” encryption method are to be used to produce a key block containing a
randomly generated session key to be used with the “aes128-cbc” method to encrypt the source
code. See Using the Mentor Graphics Public Encryption Key.

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Using raw Encryption for VHDL

Suppose that the IP author wants to use “raw” encryption and encoding to help with debugging
the following entity:

entity example3_ent is

port (
in1 : in bit;
out1 : out bit);

end example3_ent;

Then the architecture the author wants to encrypt might be this:

========== File example3_arch.vhd

`protect data_method = "raw"

`protect encoding = ( enctype = "raw")
`protect begin
architecture arch of example3_ent is

begin

out1 <= in1 after 1 ns;

end arch;
`protect end

========== End of file example3_arch.vhd ==========

If (after compiling the entity) the example3_arch.vhd file were compiled using the command:

vcom +protect example3_arch.vhd

Then the following file would be produced in the work directory

========== File work/example3_arch.vhdp ==========

`protect data_method = "raw"

`protect encoding = ( enctype = "raw")
`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect data_method = "raw"
`protect encoding = ( enctype = "raw", bytes = 81 )
`protect DATA_BLOCK
architecture arch of example3_ent is

begin

out1 <= in1 after 1 ns;

end arch;
`protect END_PROTECTED

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========== End of file work/example3_arch.vhdp

Notice that the protected file is very similar to the original file. The differences are that `protect
begin is replaced by `protect BEGIN_PROTECTED, `protect end is replaced by `protect
END_PROTECTED, and some additional encryption information is supplied after the BEGIN
PROTECTED directive.

See Encryption and Encoding Methods for more information about raw encryption and
encoding.

Encrypting Several Parts of a VHDL Source File

This example shows the use of symmetric encryption. (See Encryption and Encoding Methods
for more information on symmetric and asymmetric encryption and encoding.) It also
demonstrates another common use model, in which the IP author encrypts several parts of a
source file, chooses the encryption method for encrypting the source code (the data_method),
and uses a key automatically provided by ModelSim. (This is very similar to the proprietary
`protect method in Verilog - see Proprietary Source Code Encryption Tools.)

========== file [Link] ==========

entity ex4_ent is

end ex4_ent;

architecture ex4_arch of ex4_ent is

signal s1: bit;
`protect data_method = "aes128-cbc"
`protect begin
signal s2: bit;
`protect end
signal s3: bit;

begin -- ex4_arch

`protect data_method = "aes128-cbc"

`protect begin
s2 <= s1 after 1 ns;
`protect end

s3 <= s2 after 1 ns;

end ex4_arch;

========== end of file [Link]

If this file were compiled using the command:

vcom +protect [Link]

Then the following file would be produced in the work directory:

========== File work/[Link] ==========

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entity ex4_ent is

end ex4_ent;

architecture ex4_arch of ex4_ent is

signal s1: bit;
`protect data_method = "aes128-cbc"
`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" , bytes = 18 )
`protect DATA_BLOCK
<encoded encrypted declaration of s2>
`protect END_PROTECTED
signal s3: bit;

begin -- ex4_arch

`protect data_method = "aes128-cbc"

`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" , bytes = 21 )
`protect DATA_BLOCK
<encoded encrypted signal assignment to s2>
`protect END_PROTECTED

s3 <= s2 after 1 ns;

end ex4_arch;

========== End of file work/[Link]

The encrypted [Link] file shows that an IP author can encrypt both declarations and
statements. Also, note that the signal assignment

s3 <= s2 after 1 ns;

is not protected. This assignment compiles and simulates even though signal s2 is protected. In
general, executable VHDL statements and declarations simulate the same whether or not they
refer to protected objects.

Proprietary Source Code Encryption Tools

Mentor Graphics provides two proprietary methods for encrypting source code.

• The `protect / `endprotect compiler directives allow you to encrypt regions within
Verilog and SystemVerilog files.

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• The -nodebug argument for the vcom and vlog compile commands allows you to
encrypt entire VHDL, Verilog, or SystemVerilog source files.

Using Proprietary Compiler Directives

The proprietary `protect vlog compiler directive is not compatible with other simulators.
Though other simulators have a `protect directive, the algorithm ModelSim uses to encrypt
Verilog and SystemVerilog source files is different. Therefore, even though an uncompiled
source file with `protect is compatible with another simulator, once the source is compiled in
ModelSim, the resulting .vp or .svp source file is not compatible.

IP authors and IP users may use the `protect compiler directive to define regions of Verilog and
SystemVerilog code to be protected. The code is then compiled with the vlog +protect
command and simulated with ModelSim. The vencrypt utility may be used if the code contains
undefined macros or `directives, but the code must then be compiled and simulated with
ModelSim.

Note
While ModelSim supports both `protect and `pragma protect encryption directives,
these two approaches to encryption are incompatible. Code encrypted by one type of
directive cannot be decrypted by another.

The usage flow for delivering IP with the Mentor Graphics proprietary `protect compiler
directive is as follows:

Figure 3-4. Delivering IP with `protect Compiler Directives

1. The IP author protects selected regions of Verilog or SystemVerilog IP with the

`protect / `endprotect directive pair. The code in `protect / `endprotect encryption
envelopes has all debug information stripped out. This behaves exactly as if using

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vlog -nodebug=ports+pli

except that it applies to selected regions of code rather than the whole file.
2. The IP author uses the vlog +protect command to encrypt IP code contained within
encryption envelopes. The `protect / `endprotect directives are ignored by default
unless the +protect argument is used with vlog.
Once compiled, the original source file is copied to a new file in the current work
directory. The vlog +protect command produces a .vp or a .svp extension to distinguish
it from other non-encrypted Verilog and SystemVerilog files, respectively. For example,
top.v becomes [Link] and [Link] becomes [Link]. This new file can be delivered
and used as a replacement for the original source file. (See Compiling with +protect.)

Note
The vencrypt utility may be used if the code also contains undefined macros or
`directives, but the code must then be compiled and simulated with ModelSim.

You can use vlog +protect=<filename> to create an encrypted output file, with the
designated filename, in the current directory (not in the work directory, as in the default
case where [=<filename>] is not specified). For example:
vlog test.v +protect=[Link]

If the filename is specified in this manner, all source files on the command line will be
concatenated together into a single output file. Any `include files will also be inserted
into the output file.

Caution
`protect and `endprotect directives cannot be nested.

If errors are detected in a protected region, the error message always reports the first line of the
protected block.

Protecting Source Code Using -nodebug

Verilog/SystemVerilog and VHDL IP authors and users may use the proprietary vlog -nodebug
or vcom -nodebug command, respectively, to protect entire files. The -nodebug argument for
both vcom and vlog hides internal model data, allowing you to provide pre-compiled libraries
without providing source code and without revealing internal model variables and structure.

Note
The -nodebug argument encrypts entire files. The `protect compiler directive allows you
to encrypt regions within a file. Refer to Compiler Directives for details.

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When you compile with -nodebug, all source text, identifiers, and line number information are
stripped from the resulting compiled object, so ModelSim cannot locate or display any
information of the model except for the external pins.

You can access the design units comprising your model via the library, and you may invoke
vsim directly on any of these design units to see the ports. To restrict even this access in the
lower levels of your design, you can use the following -nodebug options when you compile:
Table 3-1. Compile Options for the -nodebug Compiling
Command and Switch Result
vcom -nodebug=ports makes the ports of a VHDL design unit
invisible
vlog -nodebug=ports makes the ports of a Verilog design unit
invisible
vlog -nodebug=pli prevents the use of PLI functions to
interrogate the module for information
vlog -nodebug=ports+pli combines the functions of -nodebug=ports
and -nodebug=pli

Note
Do not use the =ports option on a design without hierarchy, or on the top level of a
hierarchical design. If you do, no ports will be visible for simulation. Rather, compile all
lower portions of the design with -nodebug=ports first, then compile the top level with
-nodebug alone.

Design units or modules compiled with -nodebug can only instantiate design units or modules
that are also compiled -nodebug.

Do not use -nodebug=ports for mixed language designs, especially for Verilog modules to be
instantiated inside VHDL.

Encryption Reference
This section includes reference details on:

• Encryption and Encoding Methods

• How Encryption Envelopes Work
• Using Public Encryption Keys
• Using the Mentor Graphics Public Encryption Key

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Encryption and Encoding Methods

There are two basic encryption techniques: symmetric and asymmetric.

• Symmetric encryption uses the same key for both encrypting and decrypting the code
region.
• Asymmetric encryption methods use two keys: a public key for encryption, and a private
key for decryption.

Symmetric Encryption
For symmetric encryption, security of the key is critical and information about the key must be
supplied to ModelSim. Under certain circumstances, ModelSim will generate a random key for
use with a symmetric encryption method or will use an internal key.

The symmetric encryption algorithms ModelSim supports are:

• des-cbc
• 3des-cbc
• aes128-cbc
• aes192-cbc
• aes256-cbc
• blowfish-cbc
• cast128-cbc
The default symmetric encryption method ModelSim uses for encrypting IP source code is
aes128-cbc.

Asymmetric Encryption
For asymmetric encryption, the public key is openly available and is published using some form
of key distribution system. The private key is secret and is used by the decrypting tool, such as
ModelSim. Asymmetric methods are more secure than symmetric methods, but take much
longer to encrypt and decrypt data.

The only asymmetric method ModelSim supports is:

rsa
This method is only supported for specifying key information, not for encrypting IP source code
(i.e., only for key methods, not for data methods).

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For testing purposes, ModelSim also supports raw encryption, which doesn't change the
protected source code (the simulator still hides information about the protected region).

All encryption algorithms (except raw) produce byte streams that contain non-graphic
characters, so there needs to be an encoding mechanism to transform arbitrary byte streams into
portable sequences of graphic characters which can be used to put encrypted text into source
files. The encoding methods supported by ModelSim are:

• uuencode
• base64
• raw
Base 64 encoding, which is technically superior to uuencode, is the default encoding used by
ModelSim, and is the recommended encoding for all applications.

Raw encoding must only be used in conjunction with raw encryption for testing purposes.

How Encryption Envelopes Work

Encryption envelopes work as follows:

1. The encrypting tool generates a random key for use with a symmetric method, called a
“session key.”
2. The IP protected source code is encrypted using this session key.
3. The encrypting tool communicates the session key to the decrypting tool —which could
be ModelSim or some other tool — by means of a KEY_BLOCK.
4. For each potential decrypting tool, information about that tool must be provided in the
encryption envelope. This information includes the owner of the key (key_keyowner),
the name of the key (key_keyname), the asymmetric method for encrypting/decrypting
the key (key_method), and sometimes the key itself (key_public_key).
5. The encrypting tool uses this information to encrypt and encode the session key into a
KEY_BLOCK. The occurrence of a KEY_BLOCK in the source code tells the
encrypting tool to generate an encryption envelope.
6. The decrypting tool reads each KEY_BLOCK until it finds one that specifies a key it
knows about. It then decrypts the associated KEY_BLOCK data to determine the
original session key and uses that session key to decrypt the IP source code.

Note
VHDL encryption requires that the KEY_BLOCK (the sequence of key_keyowner,
key_keyname, and key_method directives) end with a `protect KEY_BLOCK directive.

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Using Public Encryption Keys

If IP authors want to encrypt for third party EDA tools, other public keys need to be specified
with the key_public_key directive as follows.

For Verilog and SystemVerilog:

`pragma protect key_keyowner="Acme"

`pragma protect key_keyname="AcmeKeyName"
`pragma protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB

For VHDL:

`protect key_keyowner="Acme"
`protect key_keyname="AcmeKeyName"
`protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB

This defines a new key named “AcmeKeyName” with a key owner of “Acme.” The data block
following key_public_key directive is an example of a base64 encoded version of a public key
that should be provided by a tool vendor.

Using the Mentor Graphics Public Encryption Key

The Mentor Graphics base64 encoded RSA public key is:

MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB

For Verilog and SystemVerilog applications, copy and paste the entire Mentor Graphics key
block, as follows, into your code:

`pragma protect key_keyowner = "Mentor Graphics Corporation"

`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB

The vencrypt utility will recognize the Mentor Graphics public key. If vencrypt is not used, you
must use the +protect switch with the vlog command during compile.

For VHDL applications, copy and paste the entire Mentor Graphics key block, as follows, into
your code:

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Encryption Reference

`protect key_keyowner = "Mentor Graphics Corporation"

`protect key_method = "rsa"
`protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB

The vhencrypt utility will recognize the Mentor Graphics public key. If vhencrypt is not used,
you must use the +protect switch with the vcom command during compile.

Example 3-4 illustrates the encryption envelope methodology for using this key in
Verilog/SystemVerilog. With this methodology you can collect the public keys from the various
companies whose tools process your IP, then create a template that can be included into the files
you want encrypted. During the encryption phase a new key is created for the encryption
algorithm each time the source is compiled. These keys are never seen by a human. They are
encrypted using the supplied RSA public keys.

Example 3-4. Using the Mentor Graphics Public Encryption Key in

Verilog/SystemVerilog
//
// Copyright 1991-2009 Mentor Graphics Corporation
//
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE
PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
//

`timescale 1ns / 1ps

`celldefine

module dff (q, d, clear, preset, clock); output q; input d, clear, preset, clock;
reg q;

`pragma protect data_method = "aes128-cbc"

`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvIf9Tif2em
i4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT80Xs0QgRqkrGYxW1
RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB

`pragma protect key_keyowner = "XYZ inc"

`pragma protect key_method = "rsa"
`pragma protect key_keyname = "XYZ-keyPublicKey"
`pragma protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQDZQTj5T5jO1og8ykyaxVg9B+4V+smyCJGW36ZjoqEGq
6jXHxfqB2VAmIC/j9x4xRxtCaOeBxRpcrnIKTP13Y3ydHqpYW0s0+R4h5+cMwCzWqB18Fn0ibSEW+8gW/
/BP4dHzaJApEz2Ryj+IG3UinvvWVNheZd+j0ULHGMgrOQqrwIDAQAB

`pragma protect begin

always @(clear or preset)
if (!clear)
assign q = 0;
else if (!preset)
assign q = 1;

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else
deassign q;
`pragma protect end
always @(posedge clock)
q = d;

endmodule

`endcelldefine

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246 ModelSim User’s Manual, v10.1c

Chapter 4
Projects

Projects simplify the process of compiling and simulating a design and are a great tool for
getting started with ModelSim.

What are Projects?

Projects are collection entities for designs under specification or test. At a minimum, projects
have a root directory, a work library, and "metadata" which are stored in an .mpf file located in
a project's root directory. The metadata include compiler switch settings, compile order, and file
mappings. Projects may also include:

• Source files or references to source files

• other files such as READMEs or other project documentation
• local libraries
• references to global libraries
• Simulation Configurations (see Creating a Simulation Configuration)
• Folders (see Organizing Projects with Folders)

Note
Project metadata are updated and stored only for actions taken within the project itself.
For example, if you have a file in a project, and you compile that file from the command
line rather than using the project menu commands, the project will not update to reflect
any new compile settings.

What are the Benefits of Projects?

Projects offer benefits to both new and advanced users. Projects

• simplify interaction with ModelSim; you don’t need to understand the intricacies of
compiler switches and library mappings
• eliminate the need to remember a conceptual model of the design; the compile order is
maintained for you in the project. Compile order is maintained for HDL-only designs.
• remove the necessity to re-establish compiler switches and settings at each session; these
are stored in the project metadata as are mappings to source files

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Getting Started with Projects

• allow users to share libraries without copying files to a local directory; you can establish
references to source files that are stored remotely or locally
• allow you to change individual parameters across multiple files; in previous versions
you could only set parameters one file at a time
• enable "what-if" analysis; you can copy a project, manipulate the settings, and rerun it to
observe the new results
• reload the initial settings from the project .mpf file every time the project is opened

Project Conversion Between Versions

Projects are generally not backwards compatible for either number or letter releases. When you
open a project created in an earlier version, you will see a message warning that the project will
be converted to the newer version. You have the option of continuing with the conversion or
cancelling the operation.

As stated in the warning message, a backup of the original project is created before the
conversion occurs. The backup file is named <project name>.[Link] and is created in the
same directory in which the original project is located.

Getting Started with Projects

This section describes the four basic steps to working with a project.

• Step 1 — Creating a New Project

This creates an .mpf file and a working library.
• Step 2 — Adding Items to the Project
Projects can reference or include source files, folders for organization, simulations, and
any other files you want to associate with the project. You can copy files into the project
directory or simply create mappings to files in other locations.
• Step 3 — Compiling the Files
This checks syntax and semantics and creates the pseudo machine code ModelSim uses
for simulation.
• Step 4 — Simulating a Design
This specifies the design unit you want to simulate and opens a structure tab in the
Workspace pane.

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Getting Started with Projects

Step 1 — Creating a New Project

Select File > New > Project to create a new project. This opens the Create Project dialog
where you can specify a project name, location, and default library name. You can generally
leave the Default Library Name set to "work." The name you specify will be used to create a
working library subdirectory within the Project Location. This dialog also allows you to
reference library settings from a selected .ini file or copy them directly into the project.

Figure 4-1. Create Project Dialog

After selecting OK, you will see a blank Project window in the Main window (Figure 4-2)

Figure 4-2. Project Window Detail

and the Add Items to the Project dialog (Figure 4-3).

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Getting Started with Projects

Figure 4-3. Add items to the Project Dialog

The name of the current project is shown at the bottom left corner of the Main window.

Step 2 — Adding Items to the Project

The Add Items to the Project dialog includes these options:

• Create New File — Create a new VHDL, Verilog, Tcl, or text file using the Source
editor. See below for details.
• Add Existing File — Add an existing file. See below for details.
• Create Simulation — Create a Simulation Configuration that specifies source files and
simulator options. See Creating a Simulation Configuration for details.
• Create New Folder — Create an organization folder. See Organizing Projects with
Folders for details.

Create New File

The File > New > Source menu selections allow you to create a new VHDL, Verilog, Tcl, or
text file using the Source editor.

You can also create a new project file by selecting Project > Add to Project > New File (the
Project tab in the Workspace must be active) or right-clicking in the Project tab and selecting
Add to Project > New File. This will open the Create Project File dialog (Figure 4-4).

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Getting Started with Projects

Figure 4-4. Create Project File Dialog

Specify a name, file type, and folder location for the new file.

When you select OK, the file is listed in the Project tab. Double-click the name of the new file
and a Source editor window will open, allowing you to create source code.

Add Existing File

You can add an existing file to the project by selecting Project > Add to Project > Existing
File or by right-clicking in the Project tab and selecting Add to Project > Existing File.

Figure 4-5. Add file to Project Dialog

When you select OK, the file(s) is added to the Project tab.

Step 3 — Compiling the Files

The question marks in the Status column in the Project tab denote either the files haven’t been
compiled into the project or the source has changed since the last compile. To compile the files,
select Compile > Compile All or right click in the Project tab and select Compile > Compile
All (Figure 4-6).

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Figure 4-6. Right-click Compile Menu in Project Window

Once compilation is finished, click the Library window, expand library work by clicking the
"+", and you will see the compiled design units.

Figure 4-7. Click Plus Sign to Show Design Hierarchy

Changing Compile Order

The Compile Order dialog box is functional for HDL-only designs. When you compile all files
in a project, ModelSim by default compiles the files in the order in which they were added to the
project. You have two alternatives for changing the default compile order: 1) select and compile
each file individually; 2) specify a custom compile order.

To specify a custom compile order, follow these steps:

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1. Select Compile > Compile Order or select it from the context menu in the Project tab.

Figure 4-8. Setting Compile Order

2. Drag the files into the correct order or use the up and down arrow buttons. Note that you
can select multiple files and drag them simultaneously.

Auto-Generating Compile Order

Auto Generate is supported for HDL-only designs. The Auto Generate button in the Compile
Order dialog (see above) "determines" the correct compile order by making multiple passes
over the files. It starts compiling from the top; if a file fails to compile due to dependencies, it
moves that file to the bottom and then recompiles it after compiling the rest of the files. It
continues in this manner until all files compile successfully or until a file(s) can’t be compiled
for reasons other than dependency.

Files can be displayed in the Project window in alphabetical or compile order (by clicking the
column headings). Keep in mind that the order you see in the Project tab is not necessarily the
order in which the files will be compiled.

Grouping Files
You can group two or more files in the Compile Order dialog so they are sent to the compiler at
the same time. For example, you might have one file with a bunch of Verilog define statements
and a second file that is a Verilog module. You would want to compile these two files together.

To group files, follow these steps:

1. Select the files you want to group.

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Figure 4-9. Grouping Files

1. Click the Group button.

To ungroup files, select the group and click the Ungroup button.

Step 4 — Simulating a Design

To simulate a design, do one of the following:

• double-click the Name of an appropriate design object (such as a test bench module or
entity) in the Library window
• right-click the Name of an appropriate design object and select Simulate from the
popup menu
• select Simulate > Start Simulation from the menus to open the Start Simulation dialog
(Figure 4-10). Select a design unit in the Design tab. Set other options in the VHDL,
Verilog, Libraries, SDF, and Others tabs. Then click OK to start the simulation.

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Figure 4-10. Start Simulation Dialog

A new Structure window, named sim, appears that shows the structure of the active simulation
(Figure 4-11).

Figure 4-11. Structure WIndow with Projects

At this point you are ready to run the simulation and analyze your results. You often do this by
adding signals to the Wave window and running the simulation for a given period of time. See
the ModelSim Tutorial for examples.

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The Project Window

Other Basic Project Operations

Open an Existing Project
If you previously exited ModelSim with a project open, ModelSim automatically will open that
same project upon startup. You can open a different project by selecting File > Open and
choosing Project Files from the Files of type drop-down.

Print the Absolute Pathnames For All Files

You can send a list of all project filenames to the transcript window by entering the command
project filenames. This command only works when a project is open.

Close a Project
Right-click in the Project window and select Close Project. This closes the Project window but
leaves the Library window open. Note that you cannot close a project while a simulation is in
progress.

The Project Window

The Project window contains information about the objects in your project. By default the
window is divided into five columns.

Figure 4-12. Project Window Overview

• Name – The name of a file or object.

• Status – Identifies whether a source file has been successfully compiled. Applies only to
VHDL or Verilog files. A question mark means the file hasn’t been compiled or the
source file has changed since the last successful compile; an X means the compile
failed; a check mark means the compile succeeded; a checkmark with a yellow triangle
behind it means the file compiled but there were warnings generated.

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• Type – The file type as determined by registered file types on Windows or the type you
specify when you add the file to the project.
• Order – The order in which the file will be compiled when you execute a Compile All
command.
• Modified – The date and time of the last modification to the file.
You can hide or show columns by right-clicking on a column title and selecting or deselecting
entries.

Sorting the List

You can sort the list by any of the five columns. Click on a column heading to sort by that
column; click the heading again to invert the sort order. An arrow in the column heading
indicates which field the list is sorted by and whether the sort order is descending (down arrow)
or ascending (up arrow).

Creating a Simulation Configuration

A Simulation Configuration associates a design unit(s) and its simulation options. For example,
assume you routinely load a particular design and you also have to specify the simulator
resolution limit, generics, and SDF timing files. Ordinarily you would have to specify those
options each time you load the design. With a Simulation Configuration, you would specify the
design and those options and then save the configuration with a name (for example, top_config).
The name is then listed in the Project tab and you can double-click it to load the design along
with its options.

To create a Simulation Configuration, follow these steps:

1. Select Project > Add to Project > Simulation Configuration from the main menu, or
right-click the Project tab and select Add to Project > Simulation Configuration from
the popup context menu in the Project window.

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Figure 4-13. Add Simulation Configuration Dialog

2. Specify a name in the Simulation Configuration Name field.

3. Specify the folder in which you want to place the configuration (see Organizing Projects
with Folders).
4. Select one or more design unit(s). Use the Control and/or Shift keys to select more than
one design unit. The design unit names appear in the Simulate field when you select
them.
5. Use the other tabs in the dialog to specify any required simulation options.
Click OK and the simulation configuration is added to the Project window.

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Figure 4-14. Simulation Configuration in the Project Window

Double-click the Simulation Configuration verilog_sim to load the design.

Organizing Projects with Folders

The more files you add to a project, the harder it can be to locate the item you need. You can
add "folders" to the project to organize your files. These folders are akin to directories in that
you can have multiple levels of folders and sub-folders. However, no actual directories are
created via the file system–the folders are present only within the project file.

Adding a Folder
To add a folder to your project, select Project > Add to Project > Folder or right-click in the
Project window and select Add to Project > Folder (Figure 4-15).

Figure 4-15. Add Folder Dialog

Specify the Folder Name, the location for the folder, and click OK. The folder will be displayed
in the Project tab.

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Organizing Projects with Folders

You use the folders when you add new objects to the project. For example, when you add a file,
you can select which folder to place it in.

Figure 4-16. Specifying a Project Folder

If you want to move a file into a folder later on, you can do so using the Properties dialog for the
file. Simply right-click on the filename in the Project window and select Properties from the
context menu that appears. This will open the Project Compiler Settings Dialog (Figure 4-17).
Use the Place in Folder field to specify a folder.

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Specifying File Properties and Project Settings

Figure 4-17. Project Compiler Settings Dialog

On Windows platforms, you can also just drag-and-drop a file into a folder.

Specifying File Properties and Project Settings

You can set two types of properties in a project: file properties and project settings. File
properties affect individual files; project settings affect the entire project.

File Compilation Properties

The VHDL and Verilog compilers (vcom and vlog, respectively) have numerous options that
affect how a design is compiled and subsequently simulated. You can customize the settings on
individual files or a group of files.

Note
Any changes you make to the compile properties outside of the project, whether from the
command line, the GUI, or the [Link] file, will not affect the properties of files
already in the project.

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Specifying File Properties and Project Settings

To customize specific files, select the file(s) in the Project window, right click on the file names,
and select Properties. The resulting Project Compiler Settings dialog (Figure 4-18) varies
depending on the number and type of files you have selected. If you select a single VHDL or
Verilog file, you will see the General tab, Coverage tab, and the VHDL or Verilog tab,
respectively. On the General tab, you will see file properties such as Type, Location, and Size.
If you select multiple files, the file properties on the General tab are not listed. Finally, if you
select both a VHDL file and a Verilog file, you will see all tabs but no file information on the
General tab.

Figure 4-18. Specifying File Properties

When setting options on a group of files, keep in mind the following:

• If two or more files have different settings for the same option, the checkbox in the
dialog will be "grayed out." If you change the option, you cannot change it back to a
"multi- state setting" without cancelling out of the dialog. Once you click OK,
ModelSim will set the option the same for all selected files.
• If you select a combination of VHDL and Verilog files, the options you set on the
VHDL and Verilog tabs apply only to those file types.

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Specifying File Properties and Project Settings

Project Settings
To modify project settings, right-click anywhere within the Project tab and select Project
Settings.

Figure 4-19. Project Settings Dialog

Converting Pathnames to Softnames for Location Mapping

If you are using location mapping, you can convert the following into a soft pathname:

• a relative pathname
• full pathname
• pathname with an environment variable

Tip: A softname is a term for a pathname that uses location mapping with
MGC_LOCATION_MAP. The soft pathname looks like a pathname containing an
environment variable, it locates the source using the location map rather than the
environment.

To convert the pathname to a softname for projects using location mapping, follow these steps:

1. Right-click anywhere within the Project tab and select Project Settings
2. Enable the Convert pathnames to softnames within the Location map area of the
Project Settings dialog box (Figure 4-19).

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Accessing Projects from the Command Line

Once enabled, all pathnames currently in the project and any that are added later are then
converted to softnames.

During conversion, if there is no softname in the mgc location map matching the entry, the
pathname is converted in to a full (hardened) pathname. A pathname is hardened by removing
the environment variable or the relative portion of the path. If this happens, any existing
pathnames that are either relative or use environment variables are also changed: either to
softnames if possible, or to hardened pathnames if not.

For more information on location mapping and pathnames, see Using Location Mapping.

Accessing Projects from the Command Line

Generally, projects are used from within the ModelSim GUI. However, standalone tools will
use the project file if they are invoked in the project's root directory. If you want to invoke
outside the project directory, set the MODELSIM environment variable with the path to the
project file (<Project_Root_Dir>/<Project_Name>.mpf).

You can also use the project command from the command line to perform common operations
on projects.

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Chapter 5
Design Libraries

VHDL designs are associated with libraries, which are objects that contain compiled design
units. Verilog and SystemVerilog designs simulated within ModelSim are compiled into
libraries as well.

Design Library Overview

A design library is a directory or archive that serves as a repository for compiled design units.
The design units contained in a design library consist of VHDL entities, packages, architectures,
and configurations; Verilog modules and UDPs (user-defined primitives). The design units are
classified as follows:

• Primary design units — Consist of entities, package declarations, configuration

declarations, modules and UDPs. Primary design units within a given library must have
unique names.
• Secondary design units — Consist of architecture bodies and package bodies.
Secondary design units are associated with a primary design unit. Architectures by the
same name can exist if they are associated with different entities or modules.

Design Unit Information

The information stored for each design unit in a design library is:

• retargetable, executable code

• debugging information
• dependency information

Working Library Versus Resource Libraries

Design libraries can be used in two ways:

1. as a local working library that contains the compiled version of your design;
2. as a resource library.
The contents of your working library will change as you update your design and recompile. A
resource library is typically static and serves as a parts source for your design. You can create

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Working with Design Libraries

your own resource libraries or they may be supplied by another design team or a third party (for
example, a silicon vendor).

Only one library can be the working library.

Any number of libraries can be resource libraries during a compilation. You specify which
resource libraries will be used when the design is compiled, and there are rules to specify in
which order they are searched (refer to Specifying Resource Libraries).

A common example of using both a working library and a resource library is one in which your
gate-level design and test bench are compiled into the working library and the design references
gate-level models in a separate resource library.

The Library Named "work"

The library named "work" has special attributes within ModelSim — it is predefined in the
compiler and need not be declared explicitly (that is, library work). It is also the library name
used by the compiler as the default destination of compiled design units (that is, it does not need
to be mapped). In other words, the work library is the default working library.

Archives
By default, design libraries are stored in a directory structure with a sub-directory for each
design unit in the library. Alternatively, you can configure a design library to use archives. In
this case, each design unit is stored in its own archive file. To create an archive, use the -archive
argument to the vlib command.

Generally you would do this only in the rare case that you hit the reference count limit on I-
nodes due to the ".." entries in the lower-level directories (the maximum number of sub-
directories on UNIX and Linux is 65533). An example of an error message that is produced
when this limit is hit is:

mkdir: cannot create directory `65534': Too many links

Archives may also have limited value to customers seeking disk space savings.

Working with Design Libraries

The implementation of a design library is not defined within standard VHDL or Verilog. Within
ModelSim, design libraries are implemented as directories and can have any legal name allowed
by the operating system, with one exception: extended identifiers are not supported for library
names.

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Working with Design Libraries

Creating a Library
When you create a project (refer to Getting Started with Projects), ModelSim automatically
creates a working design library. If you don’t create a project, you need to create a working
design library before you run the compiler. This can be done from either the command line or
from the ModelSim graphic interface.

From the ModelSim prompt or a UNIX/DOS prompt, use this vlib command:

vlib <directory_pathname>

To create a new library with the graphic interface, select File > New > Library.

Figure 5-1. Creating a New Library

When you click OK, ModelSim creates the specified library directory and writes a specially-
formatted file named _info into that directory. The _info file must remain in the directory to
distinguish it as a ModelSim library.

The new map entry is written to the [Link] file in the [Library] section. Refer to
[Link] Variables for more information.

Note
Remember that a design library is a special kind of directory. The only way to create a
library is to use the ModelSim GUI or the vlib command. Do not try to create libraries
using UNIX, DOS, or Windows commands.

Managing Library Contents

Library contents can be viewed, deleted, recompiled, edited and so on using either the graphic
interface or command line.

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Working with Design Libraries

The Library window provides access to design units (configurations, modules, packages,
entities, and architectures) in a library. Various information about the design units is displayed
in columns to the right of the design unit name.

Figure 5-2. Design Unit Information in the Workspace

The Library window has a popup menu with various commands that you access by clicking
your right mouse button.

The context menu includes the following commands:

• Simulate — Loads the selected design unit(s) and opens Structure (sim) and Files
windows. Related command line command is vsim.
• Edit — Opens the selected design unit(s) in the Source window; or, if a library is
selected, opens the Edit Library Mapping dialog (refer to Library Mappings with the
GUI).
• Refresh — Rebuilds the library image of the selected library without using source code.
Related command line command is vcom or vlog with the -refresh argument.
• Recompile — Recompiles the selected design unit(s). Related command line command
is vcom or vlog.
• Update — Updates the display of available libraries and design units.

Assigning a Logical Name to a Design Library

VHDL uses logical library names that can be mapped to ModelSim library directories. By
default, ModelSim can find libraries in your current directory (assuming they have the right
name), but for it to find libraries located elsewhere, you need to map a logical library name to
the pathname of the library.

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You can use the GUI, a command, or a project to assign a logical name to a design library.

Library Mappings with the GUI

To associate a logical name with a library, select the library in the Library window, right-click
your mouse, and select Edit from the context menu that appears. This brings up a dialog box
that allows you to edit the mapping.

Figure 5-3. Edit Library Mapping Dialog

The dialog box includes these options:

• Library Mapping Name — The logical name of the library.

• Library Pathname — The pathname to the library.

Library Mapping from the Command Line

You can set the mapping between a logical library name and a directory with the vmap
command using the following syntax:

vmap <logical_name> <directory_pathname>

You may invoke this command from either a UNIX/DOS prompt or from the command line
within ModelSim.

The vmap command adds the mapping to the library section of the [Link] file. You can
also modify [Link] manually by adding a mapping line. To do this, use a text editor and
add a line under the [Library] section heading using the syntax:

<logical_name> = <directory_pathname>

More than one logical name can be mapped to a single directory. For example, suppose the
[Link] file in the current working directory contains following lines:

[Library]
work = /usr/rick/design

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Working with Design Libraries

my_asic = /usr/rick/design

This would allow you to use either the logical name work or my_asic in a library or use clause
to refer to the same design library.

Unix Symbolic Links

You can also create a UNIX symbolic link to the library using the host platform command:

ln -s <directory_pathname> <logical_name>

The vmap command can also be used to display the mapping of a logical library name to a
directory. To do this, enter the shortened form of the command:

vmap <logical_name>

Library Search Rules

The system searches for the mapping of a logical name in the following order:

• First the system looks for a [Link] file.

• If the system doesn’t find a [Link] file, or if the specified logical name does not
exist in the [Link] file, the system searches the current working directory for a
subdirectory that matches the logical name.
An error is generated by the compiler if you specify a logical name that does not resolve to an
existing directory.

Moving a Library
Individual design units in a design library cannot be moved. An entire design library can be
moved, however, by using standard operating system commands for moving a directory or an
archive.

Setting Up Libraries for Group Use

By adding an “others” clause to your [Link] file, you can have a hierarchy of library
mappings. If the tool does not find a mapping in the [Link] file, then it will search the
[library] section of the initialization file specified by the “others” clause. For example:

[library]
asic_lib = /cae/asic_lib
work = my_work
others = /usr/modeltech/[Link]

You can specify only one "others" clause in the library section of a given [Link] file.

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Specifying Resource Libraries

The “others” clause only instructs the tool to look in the specified [Link] file for a library.
It does not load any other part of the specified file.

If there are two libraries with the same name mapped to two different locations – one in the
current [Link] file and the other specified by the "others" clause – the mapping specified
in the current .ini file will take effect.

Specifying Resource Libraries

Verilog Resource Libraries
ModelSim supports separate compilation of distinct portions of a Verilog design. The vlog
compiler is used to compile one or more source files into a specified library. The library thus
contains pre-compiled modules and UDPs that are referenced by the simulator as it loads the
design.

Resource libraries are specified differently for Verilog and VHDL. For Verilog you use either
the -L or -Lf argument to vlog. Refer to Library Usage for more information.

The LibrarySearchPath variable in the [Link] file (in the [vlog] section) can be used to
define a space-separated list of resource library paths and/or library path variables. This
behavior is identical with the -L argument for the vlog command.

LibrarySearchPath = <path>/lib1 <path>/lib2 <path>/lib3

The default for LibrarySearchPath is:

LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF

VHDL Resource Libraries

Within a VHDL source file, you use the VHDL library clause to specify logical names of one
or more resource libraries to be referenced in the subsequent design unit. The scope of a library
clause includes the text region that starts immediately after the library clause and extends to the
end of the declarative region of the associated design unit. It does not extend to the next design
unit in the file.

Note that the library clause is not used to specify the working library into which the design unit
is placed after compilation. The vcom command adds compiled design units to the current
working library. By default, this is the library named work. To change the current working
library, you can use vcom -work and specify the name of the desired target library.

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Specifying Resource Libraries

Predefined Libraries
Certain resource libraries are predefined in standard VHDL. The library named std contains the
packages standard, env, and textio, which should not be modified. The contents of these
packages and other aspects of the predefined language environment are documented in the IEEE
Standard VHDL Language Reference Manual, Std 1076. Refer also to, Using the TextIO
Package.

A VHDL use clause can be specified to select particular declarations in a library or package that
are to be visible within a design unit during compilation. A use clause references the compiled
version of the package—not the source.

By default, every VHDL design unit is assumed to contain the following declarations:

LIBRARY std, work;

USE [Link]

To specify that all declarations in a library or package can be referenced, add the suffix .all to
the library/package name. For example, the use clause above specifies that all declarations in
the package standard, in the design library named std, are to be visible to the VHDL design unit
immediately following the use clause. Other libraries or packages are not visible unless they are
explicitly specified using a library or use clause.

Another predefined library is work, the library where a design unit is stored after it is compiled
as described earlier. There is no limit to the number of libraries that can be referenced, but only
one library is modified during compilation.

Alternate IEEE Libraries Supplied

The installation directory may contain two or more versions of the IEEE library:

• ieeepure — Contains only IEEE approved packages (accelerated for ModelSim).

• ieee — Contains precompiled Synopsys and IEEE arithmetic packages which have been
accelerated for ModelSim including math_complex, math_real, numeric_bit,
numeric_std, std_logic_1164, std_logic_misc, std_logic_textio, std_logic_arith,
std_logic_signed, std_logic_unsigned, vital_primitives, and vital_timing.
You can select which library to use by changing the mapping in the [Link] file. The
[Link] file in the installation directory defaults to the ieee library.

Regenerating Your Design Libraries

Depending on your current ModelSim version, you may need to regenerate your design libraries
before running a simulation. Check the installation README file to see if your libraries require
an update. You can regenerate your design libraries using the Refresh command from the

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Importing FPGA Libraries

Library tab context menu (refer to Managing Library Contents), or by using the -refresh
argument to vcom and vlog.

From the command line, you would use vcom with the -refresh argument to update VHDL
design units in a library, and vlog with the -refresh argument to update Verilog design units. By
default, the work library is updated. Use either vcom or vlog with the -work <library>
argument to update a different library. For example, if you have a library named mylib that
contains both VHDL and Verilog design units:

vcom -work mylib -refresh

vlog -work mylib -refresh

Note
You may specify a specific design unit name with the -refresh argument to vcom and
vlog in order to regenerate a library image for only that design, but you may not specify a
file name.

An important feature of -refresh is that it rebuilds the library image without using source code.
This means that models delivered as compiled libraries without source code can be rebuilt for a
specific release of ModelSim. In general, this works for moving forwards or backwards on a
release. Moving backwards on a release may not work if the models used compiler switches,
directives, language constructs, or features that do not exist in the older release.

Note
You don't need to regenerate the std, ieee, vital22b, and verilog libraries. Also, you
cannot use the -refresh option to update libraries that were built before the 4.6 release.

Importing FPGA Libraries

ModelSim includes an import wizard for referencing and using vendor FPGA libraries. The
wizard scans for and enforces dependencies in the libraries and determines the correct mappings
and target directories.

Note
The FPGA libraries you import must be pre-compiled. Most FPGA vendors supply pre-
compiled libraries configured for use with ModelSim.

To import an FPGA library, select File > Import > Library.

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Protecting Source Code

Figure 5-4. Import Library Wizard

Follow the instructions in the wizard to complete the import.

Protecting Source Code

The Protecting Your Source Code chapter provides details about protecting your internal model
data. This allows a model supplier to provide pre-compiled libraries without providing source
code and without revealing internal model variables and structure.

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Chapter 6
VHDL Simulation

This chapter covers the following topics related to using VHDL in a ModelSim design:

• Basic VHDL Usage — A brief outline of the steps for using VHDL in a ModelSim
design.
• Compilation and Simulation of VHDL — How to compile, optimize, and simulate a
VHDL design
• Using the TextIO Package — Using the TextIO package provided with ModelSim
• VITAL Usage and Compliance — Implementation of the VITAL (VHDL Initiative
Towards ASIC Libraries) specification for ASIC modeling
• VHDL Utilities Package (util) — Using the special built-in utilities package (Util
Package) provided with ModelSim
• Modeling Memory — The advantages of using VHDL variables or protected types
instead of signals for memory designs.

Basic VHDL Usage

Simulating VHDL designs with ModelSim consists of the following general steps:

1. Compile your VHDL code into one or more libraries using the vcom command. Refer to
Compiling a VHDL Design—the vcom Command for more information.
2. Load your design with the vsim command. Refer to Simulating a VHDL Design.
3. Simulate the loaded design, then debug as needed.

Compilation and Simulation of VHDL

Creating a Design Library for VHDL
Before you can compile your VHDL source files, you must create a library in which to store the
compilation results. Use vlib to create a new library. For example:

vlib work

This creates a library named work. By default, compilation results are stored in the work library.

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The work library is actually a subdirectory named work. This subdirectory contains a special
file named _info. Do not create a VHDL library as a directory by using a UNIX, Linux,
Windows, or DOS command—always use the vlib command.

See Design Libraries for additional information on working with VHDL libraries.

Compiling a VHDL Design—the vcom Command

ModelSim compiles one or more VHDL design units with a single invocation of the vcom
command, the VHDL compiler. The design units are compiled in the order that they appear on
the command line. For VHDL, the order of compilation is important—you must compile any
entities or configurations before an architecture that references them.

You can simulate a design written with the following versions of VHDL:

• 1076-1987
• 1076-1993
• 1076-2002
• 1076-2008
To do so you need to compile units from each VHDL version separately.

The vcom command compiles using 1076 -2002 rules by default; use the -87, -93, or -2008
arguments to vcom to compile units written with version 1076-1987, 1076 -1993, or 1076-2008
respectively. You can also change the default by modifying the VHDL93 variable in the
[Link] file (see [Link] Variables for more information).

Note
Only a limited number of VHDL 1076-2008 constructs are currently supported.

Dependency Checking
You must re-analyze dependent design units when you change the design units they depend on
in the library. The vcom command determines whether or not the compilation results have
changed.

For example, if you keep an entity and its architectures in the same source file and you modify
only an architecture and recompile the source file, the entity compilation results will remain
unchanged. This means you do not have to recompile design units that depend on the entity.

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VHDL Case Sensitivity

VHDL is a case-insensitive language for all basic identifiers. For example, clk and CLK are
regarded as the same name for a given signal or variable. This differs from Verilog and
SystemVerilog, which are case-sensitive.

The vcom command preserves both uppercase and lowercase letters of all user-defined object
names in a VHDL source file.

Usage Notes
• You can make the vcom command convert uppercase letters to lowercase by either of
the following methods:
o Use the -lower argument with the vcom command.
o Set the PreserveCase variable to 0 in your [Link] file.
• The supplied precompiled packages in STD and IEEE have their case preserved. This
results in slightly different version numbers for these packages. As a result, you may
receive out-of-date reference messages when refreshing to the current release. To
resolve this, use vcom -force_refresh instead of vcom -refresh.
• Mixed language interactions
o Design unit names — Because VHDL and Verilog design units are mixed in the
same library, VHDL design units are treated as if they are lowercase. This is for
compatibility with previous releases. This also to provide consistent filenames in the
file system for make files and scripts.
o Verilog packages compiled with -mixedsvvh — not affected by VHDL uppercase
conversion.
o VHDL packages compiled with -mixedsvvh — not affected by VHDL uppercase
conversion; VHDL basic identifiers are still converted to lowercase for compatibility
with previous releases.
o FLI — Functions that return names of an object will not have the original case
unless the source is compiled using vcom -lower. Port and Generic names in the
mtiInterfaceListT structure are converted to lowercase to provide compatibility with
programs doing case sensitive comparisons (strcmp) on the generic and port names.

How Case Affects Default Binding

The following rules describe how ModelSim handles uppercase and lowercase names in default
bindings.

1. All VHDL names are case-insensitive, so ModelSim always stores them in the library in
lowercase to be consistent and compatible with older releases.

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2. When looking for a design unit in a library, ModelSim ignores the VHDL case and looks
first for the name in lowercase. If present, ModelSim uses it.
3. If no lowercase version of the design unit name exists in the library, then ModelSim
checks the library, ignoring case.
a. If ONE match is found this way, ModelSim selects that design unit.
b. If NO matches or TWO or more matches are found, ModelSim does not select
anything.

The following examples demonstrate these rules. Here, the VHDL compiler needs to find a
design unit named Test. Because VHDL is case-insensitive, ModelSim looks for "test" because
previous releases always converted identifiers to lowercase.

Example 1
Consider the following library:

work
entity test
Module TEST

The VHDL entity test is selected because it is stored in the library in lowercase. The original
VHDL could have contained TEST, Test, or TeSt, but the library always has the entity as "test."

Example 2
Consider the following library:

work
Module Test

No design unit named "test" exists, but "Test" matches when case is ignored, so ModelSim
selects it.

Example 3
Consider the following library:

work
Module Test
Module TEST

No design unit named "test" exists, but both "Test" and "TEST" match when case is ignored, so
ModelSim does not select either one.

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Range and Index Checking

A range check verifies that a scalar value defined to be of a subtype with a range is always
assigned a value within its range. An index check verifies that whenever an array subscript
expression is evaluated, the subscript will be within the array's range.

Range and index checks are performed by default when you compile your design. You can
disable range checks (potentially offering a performance advantage) using arguments to the
vcom command. Or, you can use the NoRangeCheck and NoIndexCheck variables in the
[vcom] section of the [Link] file to specify whether or not they are performed. Refer to
[Link] Variables for more information.

Generally, these checks are disabled only after the design is known to be error-free. If you run a
simulation with range checking disabled, any scalar values that are out of range are indicated by
showing the value in the following format: ?(N) where N is the current value. For example, the
range constraint for STD_ULOGIC is 'U' to '-'; if the value is reported as ?(25), the value is out
of range because the type STD_ULOGIC value internally is between 0 and 8 (inclusive). A
similar thing will arise for integer subtypes and floating point subtypes. This generally
indicates that there is an error in the design that is not being caught because range checking was
disabled.

Range checks in ModelSim are slightly more restrictive than those specified by the VHDL
Language Reference Manual (LRM). ModelSim requires any assignment to a signal to also be
in range whereas the LRM requires only that range checks be done whenever a signal is
updated. Most assignments to signals update the signal anyway, and the more restrictive
requirement allows ModelSim to generate better error messages.

Subprogram Inlining
ModelSim attempts to inline subprograms at compile time to improve simulation performance.
This happens automatically and should be largely transparent. However, you can disable
automatic inlining two ways:

• Invoke vcom with the -O0 or -O1 argument

• Use the mti_inhibit_inline attribute as described below
Single-stepping through a simulation varies slightly, depending on whether inlining occurred.
When single-stepping to a subprogram call that has not been inlined, the simulator stops first at
the line of the call, and then proceeds to the line of the first executable statement in the called
subprogram. If the called subprogram has been inlined, the simulator does not first stop at the
subprogram call, but stops immediately at the line of the first executable statement.

mti_inhibit_inline Attribute
You can disable inlining for individual design units (a package, architecture, or entity) or
subprograms with the mti_inhibit_inline attribute. Follow these rules to use the attribute:

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• Declare the attribute within the design unit's scope as follows:

attribute mti_inhibit_inline : boolean;

• Assign the value true to the attribute for the appropriate scope. For example, to inhibit
inlining for a particular function (for example, "foo"), add the following attribute
assignment:
attribute mti_inhibit_inline of foo : procedure is true;

To inhibit inlining for a particular package (for example, "pack"), add the following
attribute assignment:
attribute mti_inhibit_inline of pack : package is true;

Do similarly for entities and architectures.

Simulating a VHDL Design

A VHDL design is ready for simulation after it has been compiled with vcom. You can then use
the vsim command to invoke the simulator with the name(s) of the configuration or
entity/architecture pair.

Note
This section discusses simulation from the UNIX or Windows/DOS command line. You
can also use a project to simulate (see Getting Started with Projects) or the Start
Simulation dialog box (open with Simulate > Start Simulation menu selection).

This example begins simulation on a design unit with an entity named my_asic and an
architecture named structure:

vsim my_asic structure

Timing Specification
The vsim command can annotate a design using VITAL-compliant models with timing data
from an SDF file. You can specify delay by invoking vsim with the -sdfmin, -sdftyp, or -sdfmax
arguments. The following example uses an SDF file named [Link] in the current work directory,
and an invocation of vsim annotating maximum timing values for the design unit my_asic:

vsim -sdfmax /my_asic=[Link] my_asic

By default, the timing checks within VITAL models are enabled. You can disable them with the
+notimingchecks argument. For example:

vsim +notimingchecks topmod

If you specify vsim +notimingchecks, the generic TimingChecksOn is set to FALSE for all
VITAL models with the Vital_level0 or Vital_level1 attribute (refer to VITAL Usage and

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Compliance). Setting this generic to FALSE disables the actual calls to the timing checks along
with anything else that is present in the model's timing check block. In addition, if these models
use the generic TimingChecksOn to control behavior beyond timing checks, this behavior will
not occur. This can cause designs to simulate differently and provide different results.

Naming Behavior of VHDL For Generate Blocks

A VHDL for … generate statement, when elaborated in a design, places a given number of
for … generate equivalent blocks into the scope in which the statement exists; either an
architecture, a block, or another generate block. The simulator constructs a design path name for
each of these for … generate equivalent blocks based on the original generate statement's label
and the value of the generate parameter for that particular iteration. For example, given the
following code:

g1: for I in 1 to Depth generate

L: BLK port map (A(I), B(I+1));
end generate g1

the default names of the blocks in the design hierarchy would be:
g1(1), g1(2), ...

This name appears in the GUI to identify the blocks. You should use this name with any
commands when referencing a block that is part of the simulation environment. The format of
the name is based on the VHDL Language Reference Manual P1076-2008 section 16.2.5
Predefined Attributes of Named Entities.

If the type of the generate parameter is an enumeration type, the value within the parenthesis
will be an enumeration literal of that type; such as: g1(red).

For mixed-language designs, in which a Verilog hierarchical reference is used to reference

something inside a VHDL for … generate equivalent block, the parentheses are replaced with
brackets ( [] ) to match Verilog syntax. If the name is dependent upon enumeration literals, the
literal will be replaced with its position number because Verilog does not support using
enumerated literals in its for … generate equivalent block.

In releases prior to the 6.6 series, this default name was controlled by the GenerateFormat
[Link] file variable would have appeared as:

g11, g12, ...

All previously-generated scripts using this old format should work by default. However, if not,
you can use the GenerateFormat and OldVhdlForGenNames [Link] variables to ensure
that the old and current names are mapped correctly.

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Differences Between Versions of VHDL

There are four versions of the VHDL standard (IEEE Std 1076): 1076-1987, 1076-1993,
1076-2002, and 1076-2008. The default language version supported for ModelSim is 1076-
2002.

If your code was written according to the 1987, 1993, or 2008 version, you may need to update
your code or instruct ModelSim to use rules for different version.

To select a specific language version, do one of the following:

• Select the appropriate version from the compiler options menu in the GUI
• Invoke vcom using the argument -87, -93, -2002, or -2008.
• Set the VHDL93 variable in the [vcom] section of the [Link] file to one of the
following values:
- 0, 87, or 1987 for 1076-1987
- 1, 93, or 1993 for 1076-1993
- 2, 02, or 2002 for 1076-2002
- 3, 08, or 2008 for 1076-2008
The following is a list of language incompatibilities that may cause problems when compiling a
design.

Tip: Please refer to ModelSim Release Notes for the most current and comprehensive
description of differences between supported versions of the VHDL standard.

• VHDL-93 and VHDL-2002 — The only major problem between VHDL-93 and VHDL-
2002 is the addition of the keyword "PROTECTED". VHDL-93 programs which use
this as an identifier should choose a different name.
All other incompatibilities are between VHDL-87 and VHDL-93.
• VITAL and SDF — It is important to use the correct language version for VITAL.
VITAL2000 must be compiled with VHDL-93 or VHDL-2002. VITAL95 must be
compiled with VHDL-87. A typical error message that indicates the need to compile
under language version VHDL-87 is:
"VITALPathDelay DefaultDelay parameter must be locally static"

• Purity of NOW — In VHDL-93 the function "now" is impure. Consequently, any

function that invokes "now" must also be declared to be impure. Such calls to "now"
occur in VITAL. A typical error message:

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"Cannot call impure function 'now' from inside pure function

'<name>'"

• Files — File syntax and usage changed between VHDL-87 and VHDL-93. In many
cases vcom issues a warning and continues:
"Using 1076-1987 syntax for file declaration."

In addition, when files are passed as parameters, the following warning message is
produced:
"Subprogram parameter name is declared using VHDL 1987 syntax."

This message often involves calls to endfile(<name>) where <name> is a file parameter.
• Files and packages — Each package header and body should be compiled with the same
language version. Common problems in this area involve files as parameters and the size
of type CHARACTER. For example, consider a package header and body with a
procedure that has a file parameter:
procedure proc1 ( out_file : out [Link]) ...

If you compile the package header with VHDL-87 and the body with VHDL-93 or
VHDL-2002, you will get an error message such as:
"** Error: mixed_package_b.vhd(4): Parameter kinds do not conform
between declarations in package header and body: 'out_file'."

• Direction of concatenation — To solve some technical problems, the rules for direction
and bounds of concatenation were changed from VHDL-87 to VHDL-93. You won't see
any difference in simple variable/signal assignments such as:
v1 := a & b;

But if you (1) have a function that takes an unconstrained array as a parameter, (2) pass
a concatenation expression as a formal argument to this parameter, and (3) the body of
the function makes assumptions about the direction or bounds of the parameter, then you
will get unexpected results. This may be a problem in environments that assume all
arrays have "downto" direction.
• xnor — "xnor" is a reserved word in VHDL-93. If you declare an xnor function in
VHDL-87 (without quotes) and compile it under VHDL-2002, you will get an error
message like the following:
** Error: [Link](3): near "xnor": expecting: STRING IDENTIFIER

• 'FOREIGN attribute — In VHDL-93 package STANDARD declares an attribute

'FOREIGN. If you declare your own attribute with that name in another package, then
ModelSim issues a warning such as the following:
-- Compiling package foopack

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** Warning: [Link](9): (vcom-1140) VHDL-1993 added a definition

of the attribute foreign to package [Link]. The attribute is
also defined in package 'standard'. Using the definition from
package 'standard'.

• Size of CHARACTER type — In VHDL-87 type CHARACTER has 128 values; in

VHDL-93 it has 256 values. Code which depends on this size will behave incorrectly.
This situation occurs most commonly in test suites that check VHDL functionality. It's
unlikely to occur in practical designs. A typical instance is the replacement of warning
message:
"range nul downto del is null"

by
"range nul downto 'ÿ' is null" -- range is nul downto y(umlaut)

• bit string literals — In VHDL-87 bit string literals are of type bit_vector. In VHDL-93
they can also be of type STRING or STD_LOGIC_VECTOR. This implies that some
expressions that are unambiguous in VHDL-87 now become ambiguous is VHDL-93. A
typical error message is:
** Error: bit_string_literal.vhd(5): Subprogram '=' is ambiguous.
Suitable definitions exist in packages 'std_logic_1164' and
'standard'.

• Sub-element association — In VHDL-87 when using individual sub-element association

in an association list, associating individual sub-elements with NULL is discouraged. In
VHDL-93 such association is forbidden. A typical message is:
"Formal '<name>' must not be associated with OPEN when subelements
are associated individually."

• VHDL-2008 packages — ModelSim does not provide VHDL source for VHDL-2008
IEEE-defined standard packages because of copyright restrictions. You can obtain
VHDL source from [Link] for the
following packages:
IEEE.fixed_float_types
IEEE.fixed_generic_pkg
IEEE.fixed_pkg
IEEE.float_generic_pkg
IEEE.float_pkg
IEEE.MATH_REAL
IEEE.MATH_COMPLEX
IEEE.NUMERIC_BIT
IEEE.NUMERIC_BIT_UNSIGNED
IEEE.NUMERIC_STD
IEEE.NUMERIC_STD_UNSIGNED
IEEE.std_logic_1164
IEEE.std_logic_textio

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Simulator Resolution Limit for VHDL

The simulator internally represents time as a 64-bit integer in units equivalent to the smallest
unit of simulation time, also known as the simulator resolution limit. The default resolution
limit is set to the value specified by the Resolution variable in the [Link] file. You can
view the current resolution by invoking the report command with the simulator state argument.

Note
In Verilog, this representation of time units is referred to as precision or timescale.

Overriding the Resolution

To override the default resolution of ModelSim, specify a value for the -t argument of the vsim
command line or select a different Simulator Resolution in the Simulate dialog box. Available
values of simulator resolution are:

1 fs, 10 fs, 100 fs

1 ps, 10 ps, 100 ps
1 ns, 10 ns, 100 ns
1 us, 10 us, 100 us
1 ms, 10 ms, 100 ms
1 s, 10 s, 100 s
For example, the following command sets resolution to 10 ps:

vsim -t 10ps topmod

Note that you need to take care in specifying a resolution value larger than a delay value in your
design—delay values in that design unit are rounded to the closest multiple of the resolution. In
the example above, a delay of 4 ps would be rounded down to 0 ps.

Choosing the Resolution for VHDL

You should specify the coarsest value for time resolution that does not result in undesired
rounding of your delay times. The resolution value should not be unnecessarily small because it
decreases the maximum simulation time limit and can cause longer simulations.

Default Binding
By default, ModelSim performs binding when you load the design with vsim. The advantage of
this default binding at load time is that it provides more flexibility for compile order. Namely,
VHDL entities don't necessarily have to be compiled before other entities/architectures that
instantiate them.

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However, you can force ModelSim to perform default binding at compile time instead. This
may allow you to catch design errors (for example, entities with incorrect port lists) earlier in
the flow. Use one of these two methods to change when default binding occurs:

• Specify the -bindAtCompile argument to vcom

• Set the BindAtCompile variable in the [Link] to 1 (true)

Default Binding Rules

When searching for a VHDL entity to bind with, ModelSim searches the currently visible
libraries for an entity with the same name as the component. ModelSim does this because IEEE
Std 1076-1987 contained a flaw that made it almost impossible for an entity to be directly
visible if it had the same name as the component. This meant if a component was declared in an
architecture, any entity with the same name above that declaration would be hidden because
component/entity names cannot be overloaded. As a result, ModelSim observes the following
rules for determining default binding:

• If performing default binding at load time, search the libraries specified with the -Lf
argument to vsim.
• If a directly visible entity has the same name as the component, use it.
• If an entity would be directly visible in the absence of the component declaration, use it.
• If the component is declared in a package, search the library that contained the package
for an entity with the same name.
If none of these methods is successful, ModelSim then does the following:

• Search the work library.

• Search all other libraries that are currently visible by means of the library clause.
• If performing default binding at load time, search the libraries specified with the -L
argument to vsim.
Note that these last three searches are an extension to the 1076 standard.

Disabling Default Binding

If you want default binding to occur using only configurations, you can disable normal default
binding methods by setting the RequireConfigForAllDefaultBinding variable in the
[Link] file to 1 (true).

Delta Delays
Event-based simulators such as ModelSim may process many events at a given simulation time.
Multiple signals may need updating, statements that are sensitive to these signals must be

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executed, and any new events that result from these statements must then be queued and
executed as well. The steps taken to evaluate the design without advancing simulation time are
referred to as "delta times" or just "deltas."

The diagram below represents the process for VHDL designs. This process continues until the
end of simulation time.

Figure 6-1. VHDL Delta Delay Process

Execute concurrent
statements at Advance delta time
current time

Advance simulation No Any transactions to

time process?

Yes

Any events to No
process?

Yes

Execute concurrent
statements that are
sensitive to events

This mechanism in event-based simulators may cause unexpected results. Consider the
following code fragment:

clk2 <= clk;

process (rst, clk)

begin
if(rst = '0')then
s0 <= '0';
elsif(clk'event and clk='1') then
s0 <= inp;
end if;
end process;

process (rst, clk2)

begin
if(rst = '0')then
s1 <= '0';
elsif(clk2'event and clk2='1') then
s1 <= s0;
end if;
end process;

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In this example you have two synchronous processes, one triggered with clk and the other with
clk2. To your surprise, the signals change in the clk2 process on the same edge as they are set in
the clk process. As a result, the value of inp appears at s1 rather than s0.

During simulation an event on clk occurs (from the test bench). From this event ModelSim
performs the "clk2 <= clk" assignment and the process which is sensitive to clk. Before
advancing the simulation time, ModelSim finds that the process sensitive to clk2 can also be
run. Since there are no delays present, the effect is that the value of inp appears at s1 in the same
simulation cycle.

In order to get the expected results, you must do one of the following:

• Insert a delay at every output

• Make certain to use the same clock
• Insert a delta delay
To insert a delta delay, you would modify the code like this:

process (rst, clk)

begin
if(rst = ’0’)then
s0 <= ’0’;
elsif(clk’event and clk=’1’) then
s0 <= inp;
end if;
end process;
s0_delayed <= s0;
process (rst, clk2)
begin
if(rst = ’0’)then
s1 <= ’0’;
elsif(clk2’event and clk2=’1’) then
s1 <= s0_delayed;
end if;
end process;

The best way to debug delta delay problems is observe your signals in the List window. There
you can see how values change at each delta time.

Detecting Infinite Zero-Delay Loops

If a large number of deltas occur without advancing time, it is usually a symptom of an infinite
zero-delay loop in the design. In order to detect the presence of these loops, ModelSim defines a
limit, the “iteration limit", on the number of successive deltas that can occur. When ModelSim
reaches the iteration limit, it issues a warning message.

The iteration limit default value is 1000. If you receive an iteration limit warning, first increase
the iteration limit and try to continue simulation. You can set the iteration limit from the

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Using the TextIO Package

Simulate > Runtime Options menu or by modifying the IterationLimit variable in the
[Link]. See [Link] Variables for more information on modifying the [Link]
file.

If the problem persists, look for zero-delay loops. Run the simulation and look at the source
code when the error occurs. Use the step button to step through the code and see which signals
or variables are continuously oscillating. Two common causes are a loop that has no exit, or a
series of gates with zero delay where the outputs are connected back to the inputs.

Using the TextIO Package

The TextIO package is defined within the IEEE Std 1076-2002, IEEE Standard VHDL
Language Reference Manual. This package allows human-readable text input from a declared
source within a VHDL file during simulation.

To access the routines in TextIO, include the following statement in your VHDL source code:

USE [Link];

A simple example using the package TextIO is:

USE [Link];
ENTITY simple_textio IS
END;

ARCHITECTURE simple_behavior OF simple_textio IS

BEGIN
PROCESS
VARIABLE i: INTEGER:= 42;
VARIABLE LLL: LINE;
BEGIN
WRITE (LLL, i);
WRITELINE (OUTPUT, LLL);
WAIT;
END PROCESS;
END simple_behavior;

Syntax for File Declaration

The VHDL 1987 syntax for a file declaration is:

file identifier : subtype_indication is [ mode ] file_logical_name ;

where "file_logical_name" must be a string expression.

In newer versions of the 1076 spec, syntax for a file declaration is:

file identifier_list : subtype_indication [ file_open_information ] ;

where "file_open_information" is:

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[open file_open_kind_expression] is file_logical_name

You can specify a full or relative path as the file_logical_name; for example (VHDL 1987):

Normally if a file is declared within an architecture, process, or package, the file is opened when
you start the simulator and is closed when you exit from it. If a file is declared in a subprogram,
the file is opened when the subprogram is called and closed when execution RETURNs from
the subprogram. Alternatively, the opening of files can be delayed until the first read or write by
setting the DelayFileOpen variable in the [Link] file. Also, the number of concurrently
open files can be controlled by the ConcurrentFileLimit variable. These variables help you
manage a large number of files during simulation. See [Link] Variables for more details.

Using STD_INPUT and STD_OUTPUT Within ModelSim

The standard VHDL1987 TextIO package contains the following file declarations:

file input: TEXT is in "STD_INPUT";

file output: TEXT is out "STD_OUTPUT";

Updated versions of the TextIO package contain these file declarations:

file input: TEXT open read_mode is "STD_INPUT";

file output: TEXT open write_mode is "STD_OUTPUT";

STD_INPUT is a file_logical_name that refers to characters that are entered interactively from
the keyboard, and STD_OUTPUT refers to text that is displayed on the screen.

In ModelSim, reading from the STD_INPUT file allows you to enter text into the current buffer
from a prompt in the Transcript pane. The lines written to the STD_OUTPUT file appear in the
Transcript.

TextIO Implementation Issues

Writing Strings and Aggregates

A common error in VHDL source code occurs when a call to a WRITE procedure does not
specify whether the argument is of type STRING or BIT_VECTOR. For example, the VHDL
procedure:

WRITE (L, "hello");

will cause the following error:

ERROR: Subprogram "WRITE" is ambiguous.

In the TextIO package, the WRITE procedure is overloaded for the types STRING and
BIT_VECTOR. These lines are reproduced here:

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procedure WRITE(L: inout LINE; VALUE: in BIT_VECTOR;

JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);

procedure WRITE(L: inout LINE; VALUE: in STRING;

JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);

The error occurs because the argument "hello" could be interpreted as a string or a bit vector,
but the compiler is not allowed to determine the argument type until it knows which function is
being called.

The following procedure call also generates an error:

WRITE (L, "010101");

This call is even more ambiguous, because the compiler could not determine, even if allowed to,
whether the argument "010101" should be interpreted as a string or a bit vector.

There are two possible solutions to this problem:

• Use a qualified expression to specify the type, as in:

WRITE (L, string’("hello"));

• Call a procedure that is not overloaded, as in:

WRITE_STRING (L, "hello");

The WRITE_STRING procedure simply defines the value to be a STRING and calls the
WRITE procedure, but it serves as a shell around the WRITE procedure that solves the
overloading problem. For further details, refer to the WRITE_STRING procedure in the io_utils
package, which is located in the file
<install_dir>/modeltech/examples/vhdl/io_utils/io_utils.vhd.

Reading and Writing Hexadecimal Numbers

The reading and writing of hexadecimal numbers is not specified in standard VHDL. The Issues
Screening and Analysis Committee of the VHDL Analysis and Standardization Group (ISAC-
VASG) has specified that the TextIO package reads and writes only decimal numbers.

To expand this functionality, ModelSim supplies hexadecimal routines in the package io_utils,
which is located in the file <install_dir>/modeltech/examples/gui/io_utils.vhd. To use these
routines, compile the io_utils package and then include the following use clauses in your VHDL
source code:

use [Link];
use work.io_utils.all;

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Dangling Pointers
Dangling pointers are easily created when using the TextIO package, because WRITELINE de-
allocates the access type (pointer) that is passed to it. Following are examples of good and bad
VHDL coding styles:

Bad VHDL (because L1 and L2 both point to the same buffer):

READLINE (infile, L1); -- Read and allocate buffer

L2 := L1; -- Copy pointers
WRITELINE (outfile, L1); -- Deallocate buffer

Good VHDL (because L1 and L2 point to different buffers):

READLINE (infile, L1); -- Read and allocate buffer

L2 := new string’([Link]); -- Copy contents
WRITELINE (outfile, L1); -- Deallocate buffer

The ENDLINE Function

The ENDLINE function — described in the IEEE Std 1076-2002, IEEE Standard VHDL
Language Reference Manual — contains invalid VHDL syntax and cannot be implemented in
VHDL. This is because access values must be passed as variables, but functions do not allow
variable parameters.

Based on an ISAC-VASG recommendation the ENDLINE function has been removed from the
TextIO package. The following test may be substituted for this function:

(L = NULL) OR (L’LENGTH = 0)

The ENDFILE Function

In the VHDL Language Reference Manuals, the ENDFILE function is listed as:

-- function ENDFILE (L: in TEXT) return BOOLEAN;

As you can see, this function is commented out of the standard TextIO package. This is because
the ENDFILE function is implicitly declared, so it can be used with files of any type, not just
files of type TEXT.

Using Alternative Input/Output Files

You can use the TextIO package to read and write to your own files. To do this, just declare an
input or output file of type TEXT. For example, for an input file:

The VHDL1987 declaration is:

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VITAL Usage and Compliance

file myinput : TEXT is in "[Link]";

The VHDL1993 declaration is:

file myinput : TEXT open read_mode is "[Link]";

Then include the identifier for this file ("myinput" in this example) in the READLINE or
WRITELINE procedure call.

Flushing the TEXTIO Buffer

Flushing of the TEXTIO buffer is controlled by the UnbufferedOutput variable in the
[Link] file.

Providing Stimulus
You can provide an input stimulus to a design by reading data vectors from a file and assigning
their values to signals. You can then verify the results of this input. A VHDL test bench has
been included with the ModelSim install files as an example. Check for this file:

<install_dir>/examples/gui/[Link]

VITAL Usage and Compliance

The VITAL (VHDL Initiative Towards ASIC Libraries) modeling specification is sponsored by
the IEEE to promote the development of highly accurate, efficient simulation models for ASIC
(Application-Specific Integrated Circuit) components in VHDL.

The IEEE Std 1076.4-2000, IEEE Standard for VITAL ASIC Modeling Specification is available
from the Institute of Electrical and Electronics Engineers, Inc.

IEEE Customer Service

445 Hoes Lane
Piscataway, NJ 08854-1331
Tel: (732) 981-0060
Fax: (732) 981-1721
[Link]

VITAL Source Code

The source code for VITAL packages is provided in the following ModelSim installation
directories:

/<install_dir>/vhdl_src/vital22b
/vital95

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/vital2000

VITAL 1995 and 2000 Packages

VITAL 2000 accelerated packages are pre-compiled into the ieee library in the installation
directory. VITAL 1995 accelerated packages are pre-compiled into the vital1995 library. If you
need to use the older library, you either need to change the ieee library mapping or add a use
clause to your VHDL code to access the VITAL 1995 packages.

To change the ieee library mapping, issue the following command:

vmap ieee <modeltech>/vital1995

Or, alternatively, add use clauses to your code:

LIBRARY vital1995;
USE vital1995.vital_primitives.all;
USE vital1995.vital_timing.all;
USE vital1995.vital_memory.all;

Note that if your design uses two libraries—one that depends on vital95 and one that depends
on vital2000—then you will have to change the references in the source code to vital2000.
Changing the library mapping will not work.

ModelSim VITAL built-ins are generally updated as new releases of the VITAL packages
become available.

VITAL Compliance
A simulator is VITAL-compliant if it implements the SDF mapping and if it correctly simulates
designs using the VITAL packages—as outlined in the VITAL Model Development
Specification. ModelSim is compliant with IEEE Std 1076.4-2002, IEEE Standard for VITAL
ASIC Modeling Specification. In addition, ModelSim accelerates the VITAL_Timing,
VITAL_Primitives, and VITAL_memory packages. The optimized procedures are functionally
equivalent to the IEEE Std 1076.4 VITAL ASIC Modeling Specification (VITAL 1995 and
2000).

VITAL Compliance Checking

If you are using VITAL 2.2b, you must turn off the compliance checking either by not setting
the attributes, or by invoking vcom with the argument -novitalcheck.

Compiling and Simulating with Accelerated VITAL

Packages
The vcom command automatically recognizes that a VITAL function is being referenced from
the ieee library and generates code to call the optimized built-in routines.

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Invoke vcom with the -novital argument if you do not want to use the built-in VITAL routines
(when debugging for instance). To exclude all VITAL functions, use -novital all:

vcom -novital all [Link]

To exclude selected VITAL functions, use one or more -novital <fname> arguments:

vcom -novital VitalTimingCheck -novital VitalAND [Link]

The -novital switch only affects calls to VITAL functions from the design units currently being
compiled. Pre-compiled design units referenced from the current design units will still call the
built-in functions unless they too are compiled with the -novital argument.

VHDL Utilities Package (util)

The util package contains various VHDL utilities that you can run as commands. The package is
part of the modelsim_lib library, which is located in the /modeltech tree and is mapped in the
default [Link] file.

To include the utilities in this package, add the following lines similar to your VHDL code:

library modelsim_lib;
use modelsim_lib.[Link];

get_resolution
The get_resolution utility returns the current simulator resolution as a real number. For
example, a resolution of 1 femtosecond (1 fs) corresponds to 1e-15.

Syntax
resval := get_resolution;

Returns
Name Type Description
resval real The simulator resolution represented as a
real

Arguments
None

Related functions
• to_real()
• to_time()

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Example
If the simulator resolution is set to 10ps, and you invoke the command:

resval := get_resolution;

the value returned to resval would be 1e-11.

init_signal_driver()
The init_signal_driver() utility drives the value of a VHDL signal or Verilog net onto an
existing VHDL signal or Verilog net. This allows you to drive signals or nets at any level of the
design hierarchy from within a VHDL architecture (such as a test bench).

See init_signal_driver for complete details.

init_signal_spy()
The init_signal_spy() utility mirrors the value of a VHDL signal or Verilog register/net onto an
existing VHDL signal or Verilog register. This allows you to reference signals, registers, or nets
at any level of hierarchy from within a VHDL architecture (such as a test bench).

See init_signal_spy for complete details.

signal_force()
The signal_force() utility forces the value specified onto an existing VHDL signal or Verilog
register or net. This allows you to force signals, registers, or nets at any level of the design
hierarchy from within a VHDL architecture (such as a test bench). A signal_force works the
same as the force command when you set the [Link] variable named ForceSigNextIter to
1. The variable ForceSigNextIter in the [Link] file can be set to honor the signal update
event in next iteration for all force types. Note that the signal_force utility cannot issue a
repeating force.

See signal_force for complete details.

signal_release()
The signal_release() utility releases any force that was applied to an existing VHDL signal or
Verilog register or net. This allows you to release signals, registers, or nets at any level of the
design hierarchy from within a VHDL architecture (such as a test bench). A signal_release
works the same as the noforce command.

See signal_release for complete details.

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to_real()
The to_real() utility converts the physical type time value into a real value with respect to the
current value of simulator resolution. The precision of the converted value is determined by the
simulator resolution. For example, if you were converting 1900 fs to a real and the simulator
resolution was ps, then the real value would be rounded to 2.0 (that is, 2 ps).

Syntax
realval := to_real(timeval);

Returns
Name Type Description
realval real The time value represented as a real with
respect to the simulator resolution

Arguments
Name Type Description
timeval time The value of the physical type time

Related functions
• get_resolution
• to_time()
Example
If the simulator resolution is set to ps, and you enter the following function:

realval := to_real(12.99 ns);

then the value returned to realval would be 12990.0. If you wanted the returned value to be in
units of nanoseconds (ns) instead, you would use the get_resolution function to recalculate the
value:

realval := 1e+9 * (to_real(12.99 ns)) * get_resolution();

If you wanted the returned value to be in units of femtoseconds (fs), you would enter the
function this way:

realval := 1e+15 * (to_real(12.99 ns)) * get_resolution();

to_time()
The to_time() utility converts a real value into a time value with respect to the current simulator
resolution. The precision of the converted value is determined by the simulator resolution. For

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example, if you converted 5.9 to a time and the simulator resolution was 1 ps, then the time
value would be rounded to 6 ps.

Syntax
timeval := to_time(realval);

Returns
Name Type Description
timeval time The real value represented as a physical
type time with respect to the simulator
resolution

Arguments
Name Type Description
realval real The value of the type real

Related functions
• get_resolution
• to_real()
Example
If the simulator resolution is set to 1 ps, and you enter the following function:

timeval := to_time(72.49);

then the value returned to timeval would be 72 ps.

Modeling Memory
If you want to model a memory with VHDL using signals, you may encounter either of the
following common problems with simulation:

• Memory allocation error, which typically means the simulator ran out of memory and
failed to allocate enough storage.
• Very long times to load, elaborate, or run.
These problems usually result from the fact that signals consume a substantial amount of
memory (many dozens of bytes per bit), all of which must be loaded or initialized before your
simulation starts.

As an alternative, you can model a memory design using variables or protected types instead of
signals, which provides the following performance benefits:

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• Reduced storage required to model the memory, by as much as one or two orders of
magnitude
• Reduced startup and run times
• Elimination of associated memory allocation errors

Examples of Different Memory Models

Example 6-1 shown below uses different VHDL architectures for the entity named memory to
provide the following models for storing RAM:

• bad_style_87 — uses a VHDL signal

• style_87 — uses variables in the memory process
• style_93 — uses variables in the architecture
For large memories, the run time for architecture bad_style_87 is many times longer than the
other two and uses much more memory. Because of this, you should avoid using VHDL signals
to model memory.

To implement this model, you will need functions that convert vectors to integers. To use it, you
will probably need to convert integers to vectors.

Converting an Integer Into a bit_vector

The following code shows how to convert an integer variable into a bit_vector.

library ieee;
use ieee.numeric_bit.ALL;

entity test is
end test;

architecture only of test is

signal s1 : bit_vector(7 downto 0);
signal int : integer := 45;
begin
p:process
begin
wait for 10 ns;
s1 <= bit_vector(to_signed(int,8));
end process p;
end only;

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Examples Using VHDL1987, VHDL1993, VHDL2002 Architectures

• Example 6-1 contains two VHDL architectures that demonstrate recommended memory
models: style_93 uses shared variables as part of a process, style_87 uses For
comparison, a third architecture, bad_style_87, shows the use of signals.
The style_87 and style_93 architectures work with equal efficiency for this example.
However, VHDL 1993 offers additional flexibility because the RAM storage can be
shared among multiple processes. In the example, a second process is shown that
initializes the memory; you could add other processes to create a multi-ported memory.
• Example 6-2 is a package (named conversions) that is included by the memory model in
Example 6-1.
• For completeness, Example 6-3 shows protected types using VHDL 2002. Note that
using protected types offers no advantage over shared variables.

Example 6-1. Memory Model Using VHDL87 and VHDL93 Architectures

Example functions are provided below in package “conversions.”

-------------------------------------------------------------------------
-- Source: [Link]
-- Component: VHDL synchronous, single-port RAM
-- Remarks: Provides three different architectures
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use [Link];

entity memory is
generic(add_bits : integer := 12;
data_bits : integer := 32);
port(add_in : in std_ulogic_vector(add_bits-1 downto 0);
data_in : in std_ulogic_vector(data_bits-1 downto 0);
data_out : out std_ulogic_vector(data_bits-1 downto 0);
cs, mwrite : in std_ulogic;
do_init : in std_ulogic);
subtype word is std_ulogic_vector(data_bits-1 downto 0);
constant nwords : integer := 2 ** add_bits;
type ram_type is array(0 to nwords-1) of word;
end;

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architecture style_93 of memory is

------------------------------
shared variable ram : ram_type;
------------------------------
begin
memory:
process (cs)
variable address : natural;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = '1') then
ram(address) := data_in;
end if;
data_out <= ram(address);
end if;
end process memory;
-- illustrates a second process using the shared variable
initialize:
process (do_init)
variable address : natural;
begin
if rising_edge(do_init) then
for address in 0 to nwords-1 loop
ram(address) := data_in;
end loop;
end if;
end process initialize;
end architecture style_93;

architecture style_87 of memory is

begin
memory:
process (cs)
-----------------------
variable ram : ram_type;
-----------------------
variable address : natural;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = '1') then
ram(address) := data_in;
end if;
data_out <= ram(address);
end if;
end process;
end style_87;

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architecture bad_style_87 of memory is

----------------------
signal ram : ram_type;
----------------------
begin
memory:
process (cs)
variable address : natural := 0;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = '1') then
ram(address) <= data_in;
data_out <= data_in;
else
data_out <= ram(address);
end if;
end if;
end process;
end bad_style_87;

Example 6-2. Conversions Package

library ieee;
use ieee.std_logic_1164.all;

package conversions is
function sulv_to_natural(x : std_ulogic_vector) return
natural;
function natural_to_sulv(n, bits : natural) return
std_ulogic_vector;
end conversions;

package body conversions is

function sulv_to_natural(x : std_ulogic_vector) return

natural is
variable n : natural := 0;
variable failure : boolean := false;
begin
assert (x'high - x'low + 1) <= 31
report "Range of sulv_to_natural argument exceeds
natural range"
severity error;
for i in x'range loop
n := n * 2;
case x(i) is
when '1' | 'H' => n := n + 1;
when '0' | 'L' => null;
when others => failure := true;
end case;
end loop;

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assert not failure

report "sulv_to_natural cannot convert indefinite
std_ulogic_vector"
severity error;

if failure then
return 0;
else
return n;
end if;
end sulv_to_natural;

function natural_to_sulv(n, bits : natural) return

std_ulogic_vector is
variable x : std_ulogic_vector(bits-1 downto 0) :=
(others => '0');
variable tempn : natural := n;
begin
for i in x'reverse_range loop
if (tempn mod 2) = 1 then
x(i) := '1';
end if;
tempn := tempn / 2;
end loop;
return x;
end natural_to_sulv;

end conversions;

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Example 6-3. Memory Model Using VHDL02 Architecture

-------------------------------------------------------------------------
-- Source: sp_syn_ram_protected.vhd
-- Component: VHDL synchronous, single-port RAM
-- Remarks: Various VHDL examples: random access memory (RAM)
-------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY sp_syn_ram_protected IS
GENERIC (
data_width : positive := 8;
addr_width : positive := 3
);
PORT (
inclk : IN std_logic;
outclk : IN std_logic;
we : IN std_logic;
addr : IN unsigned(addr_width-1 DOWNTO 0);
data_in : IN std_logic_vector(data_width-1 DOWNTO 0);
data_out : OUT std_logic_vector(data_width-1 DOWNTO 0)
);

END sp_syn_ram_protected;

ARCHITECTURE intarch OF sp_syn_ram_protected IS

TYPE mem_type IS PROTECTED

PROCEDURE write ( data : IN std_logic_vector(data_width-1 downto 0);
addr : IN unsigned(addr_width-1 DOWNTO 0));
IMPURE FUNCTION read ( addr : IN unsigned(addr_width-1 DOWNTO 0))
RETURN
std_logic_vector;
END PROTECTED mem_type;

TYPE mem_type IS PROTECTED BODY

TYPE mem_array IS ARRAY (0 TO 2**addr_width-1) OF
std_logic_vector(data_width-1 DOWNTO 0);
VARIABLE mem : mem_array;

PROCEDURE write ( data : IN std_logic_vector(data_width-1 downto 0);

addr : IN unsigned(addr_width-1 DOWNTO 0)) IS
BEGIN
mem(to_integer(addr)) := data;
END;

IMPURE FUNCTION read ( addr : IN unsigned(addr_width-1 DOWNTO 0))

RETURN
std_logic_vector IS
BEGIN
return mem(to_integer(addr));
END;

END PROTECTED BODY mem_type;

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SHARED VARIABLE memory : mem_type;

BEGIN

ASSERT data_width <= 32

REPORT "### Illegal data width detected"
SEVERITY failure;

control_proc : PROCESS (inclk, outclk)

BEGIN
IF (inclk'event AND inclk = '1') THEN
IF (we = '1') THEN
[Link](data_in, addr);
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN

data_out <= [Link](addr);
END IF;
END PROCESS;

END intarch;

-------------------------------------------------------------------------
-- Source: ram_tb.vhd
-- Component: VHDL test bench for RAM memory example
-- Remarks: Simple VHDL example: random access memory (RAM)
-------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ram_tb IS
END ram_tb;

ARCHITECTURE testbench OF ram_tb IS

-------------------------------------------
-- Component declaration single-port RAM
-------------------------------------------
COMPONENT sp_syn_ram_protected
GENERIC (
data_width : positive := 8;
addr_width : positive := 3
);
PORT (
inclk : IN std_logic;
outclk : IN std_logic;
we : IN std_logic;
addr : IN unsigned(addr_width-1 DOWNTO 0);
data_in : IN std_logic_vector(data_width-1 DOWNTO 0);
data_out : OUT std_logic_vector(data_width-1 DOWNTO 0)
);
END COMPONENT;

-------------------------------------------

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-- Intermediate signals and constants

-------------------------------------------
SIGNAL addr : unsigned(19 DOWNTO 0);
SIGNAL inaddr : unsigned(3 DOWNTO 0);
SIGNAL outaddr : unsigned(3 DOWNTO 0);
SIGNAL data_in : unsigned(31 DOWNTO 0);
SIGNAL data_in1 : std_logic_vector(7 DOWNTO 0);
SIGNAL data_sp1 : std_logic_vector(7 DOWNTO 0);
SIGNAL we : std_logic;
SIGNAL clk : std_logic;
CONSTANT clk_pd : time := 100 ns;

BEGIN

---------------------------------------------------
-- instantiations of single-port RAM architectures.
-- All architectures behave equivalently, but they
-- have different implementations. The signal-based
-- architecture (rtl) is not a recommended style.
---------------------------------------------------
spram1 : entity work.sp_syn_ram_protected
GENERIC MAP (
data_width => 8,
addr_width => 12)
PORT MAP (
inclk => clk,
outclk => clk,
we => we,
addr => addr(11 downto 0),
data_in => data_in1,
data_out => data_sp1);

-------------------------------------------
-- clock generator
-------------------------------------------
clock_driver : PROCESS
BEGIN
clk <= '0';
WAIT FOR clk_pd / 2;
LOOP
clk <= '1', '0' AFTER clk_pd / 2;
WAIT FOR clk_pd;
END LOOP;
END PROCESS;

-------------------------------------------
-- data-in process
-------------------------------------------
datain_drivers : PROCESS(data_in)
BEGIN
data_in1 <= std_logic_vector(data_in(7 downto 0));
END PROCESS;

-------------------------------------------
-- simulation control process
-------------------------------------------
ctrl_sim : PROCESS

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BEGIN
FOR i IN 0 TO 1023 LOOP
we <= '1';
data_in <= to_unsigned(9000 + i, data_in'length);
addr <= to_unsigned(i, addr'length);
inaddr <= to_unsigned(i, inaddr'length);
outaddr <= to_unsigned(i, outaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';

data_in <= to_unsigned(7 + i, data_in'length);

addr <= to_unsigned(1 + i, addr'length);
inaddr <= to_unsigned(1 + i, inaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';

data_in <= to_unsigned(3, data_in'length);

addr <= to_unsigned(2 + i, addr'length);
inaddr <= to_unsigned(2 + i, inaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';

data_in <= to_unsigned(30330, data_in'length);

addr <= to_unsigned(3 + i, addr'length);
inaddr <= to_unsigned(3 + i, inaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';

we <= '0';
addr <= to_unsigned(i, addr'length);
outaddr <= to_unsigned(i, outaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';

addr <= to_unsigned(1 + i, addr'length);

outaddr <= to_unsigned(1 + i, outaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';

addr <= to_unsigned(2 + i, addr'length);

outaddr <= to_unsigned(2 + i, outaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';

addr <= to_unsigned(3 + i, addr'length);

outaddr <= to_unsigned(3 + i, outaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';

END LOOP;
ASSERT false
REPORT "### End of Simulation!"
SEVERITY failure;
END PROCESS;

END testbench;

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Affecting Performance by Cancelling Scheduled Events

Simulation performance is likely to get worse if events are scheduled far into the future but then
cancelled before they take effect. This situation acts like a memory leak and slows down
simulation.

In VHDL, this situation can occur several ways. The most common are waits with time-out
clauses and projected waveforms in signal assignments.

The following shows a wait with a time-out:

signals synch : bit := '0';

...
p: process
begin
wait for 10 ms until synch = 1;
end process;

synch <= not synch after 10 ns;

At time 0, process p makes an event for time 10ms. When synch goes to 1 at 10 ns, the event at
10 ms is marked as cancelled but not deleted, and a new event is scheduled at 10ms + 10ns. The
cancelled events are not reclaimed until time 10ms is reached and the cancelled event is
processed. As a result, there will be 500000 (10ms/20ns) cancelled but un-deleted events. Once
10ms is reached, memory will no longer increase because the simulator will be reclaiming
events as fast as they are added.

For projected waveforms, the following would behave the same way:

signals synch : bit := '0';

...
p: process(synch)
begin
output <= '0', '1' after 10ms;
end process;

synch <= not synch after 10 ns;

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Chapter 7
Verilog and SystemVerilog Simulation

This chapter describes how to compile and simulate Verilog and SystemVerilog designs with
ModelSim. This chapter covers the following topics:

• Basic Verilog Usage — A brief outline of the steps for using Verilog in a ModelSim
design.
• Verilog Compilation — Information on the requirements for compiling Verilog designs
and libraries.
• Verilog Simulation — Information on the requirements for running simulation.
• Cell Libraries — Criteria for using Verilog cell libraries from ASIC and FPGA vendors
that are compatible with ModelSim.
• System Tasks and Functions — System tasks and functions that are built into the
simulator.
• Compiler Directives — Verilog compiler directives supported for ModelSim.
• Verilog PLI/VPI and SystemVerilog DPI — Verilog and SystemVerilog interfaces that
you can use to define tasks and functions that communicate with the simulator through a
C procedural interface.
• SystemVerilog Class Debugging — Information on debugging SV Class objects.

Standards, Nomenclature, and Conventions

ModelSim implements the Verilog and SystemVerilog languages as defined by the following
standards:

• IEEE 1364-2005 and 1364-1995 (Verilog)

• IEEE 1800-2009 and 1800-2005 (SystemVerilog)

Note
ModelSim supports partial implementation of SystemVerilog IEEE Std 1800-2009.
For release-specific information on currently supported implementation, refer to the
following text file located in the ModelSim installation directory:

<install_dir>/docs/technotes/[Link]

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Verilog and SystemVerilog Simulation

SystemVerilog is built “on top of” IEEE Std 1364 for the Verilog HDL and improves the
productivity, readability, and reusability of Verilog-based code. The language enhancements in
SystemVerilog provide more concise hardware descriptions, while still providing an easy route
with existing design and verification products into current hardware implementation flows. The
enhancements also provide extensive support for directed and constrained random testbench
development, coverage-driven verification, and assertion-based verification.

The standard for SystemVerilog specifies extensions for a higher level of abstraction for
modeling and verification with the Verilog hardware description language (HDL). This
standard includes design specification methods, embedded assertions language, testbench
language including coverage and assertions application programming interface (API), and a
direct programming interface (DPI).

In this chapter, the following terms apply:

• “Verilog” refers to IEEE Std 1364 for the Verilog HDL.

• “Verilog-1995” refers to IEEE Std 1364-1995 for the Verilog HDL.
• “Verilog-2001” refers to IEEE Std 1364-2001 for the Verilog HDL.
• “Verilog-2005” refers to IEEE Std 1364-2005 for the Verilog HDL.
• “SystemVerilog” refers to the extensions to the Verilog standard (IEEE Std 1364) as
defined in IEEE Std 1800-2009.

Note
The term “Language Reference Manual” (or LRM) is often used informally to refer to the
current IEEE standard for Verilog or SystemVerilog.

Supported Variations in Source Code

It is possible to use syntax variations of constructs that are not explicitly defined as being
supported in the Verilog LRM (such as “shortcuts” supported for similar constructs in another
language).

for Loops
ModelSim allows using Verilog syntax that omits any or all three specifications of a for loop:
initialization, termination, increment. This is similar to allowed usage in C and is shown in the
following examples.

Note
If you use this variation, a suppressible warning (2252) is displayed, which you can
change to an error if you use the vlog -pedanticerrors command.

• Missing initializer (in order to continue where you left off):

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Basic Verilog Usage

for (; incr < foo; incr++) begin ... end

• Missing incrementer (in order to increment in the loop body):

for (ii = 0; ii <= foo; ) begin ... end

• Missing initializer and terminator (in order to implement a while loop):

for (; goo < foo; ) begin ... end

• Missing all specifications (in order to create an infinite loop):

for (;;) begin ... end

Basic Verilog Usage

Simulating Verilog designs with ModelSim consists of the following general steps:

1. Compile your Verilog code into one or more libraries using the vlog command. See
Verilog Compilation for details.
2. Load your design with the vsim command. Refer to Verilog Simulation.
3. Simulate the loaded design and debug as needed.

Verilog Compilation
The first time you compile a design there is a two-step process:

1. Create a working library with vlib or select File > New > Library.
2. Compile the design using vlog or select Compile > Compile.

Creating a Working Library

Before you can compile your design, you must create a library in which to store the compilation
results. Use the vlib command or select File > New > Library to create a new library. For
example:

vlib work

This creates a library named work. By default compilation results are stored in the work
library.

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Verilog Compilation

The work library is actually a subdirectory named work. This subdirectory contains a special
file named _info. Do not create libraries using UNIX commands – always use the vlib
command.

See Design Libraries for additional information on working with libraries.

Invoking the Verilog Compiler

The vlog command invokes the Verilog compiler, which compiles Verilog source code into
retargetable, executable code. You can simulate your design on any supported platform without
having to recompile your design; the library format is also compatible across all platforms.

As the design compiles, the resulting object code for modules and user-defined primitives
(UDPs) is generated into a library. As noted above, the compiler places results into the work
library by default. You can specify an alternate library with the -work argument of the vlog
command.

Example 7-1. Invocation of the Verilog Compiler

The following example shows how to use the vlog command to invoke the Verilog compiler:

vlog top.v +libext+.v+.u -y vlog_lib

After compiling top.v, vlog searches the vlog_lib library for files with modules with the same
name as primitives referenced, but undefined in top.v. The use of +libext+.v+.u implies
filenames with a .v or .u suffix (any combination of suffixes may be used). Only referenced
definitions are compiled.

Verilog Case Sensitivity

Note that Verilog and SystemVerilog are case-sensitive languages. For example, clk and CLK
are regarded as different names that you can apply to different signals or variables. This differs
from VHDL, which is case-insensitive.

Parsing SystemVerilog Keywords

With standard Verilog files (<filename>.v), vlog does not automatically parse SystemVerilog
keywords. SystemVerilog keywords are parsed when either of the following situations exists:

• Any file within the design contains the .sv file extension
• You use the -sv argument with the vlog command
The following examples of the vlog command show how to enable SystemVerilog features and
keywords in ModelSim:

vlog [Link] top.v memory.v cache.v

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vlog -sv testbench.v proc.v

In the first example, the .sv extension for testbench automatically causes ModelSim to parse
SystemVerilog keywords. In the second example, the -sv argument enables SystemVerilog
features and keywords.

Keyword Compatibility
One of the primary goals of SystemVerilog standardization has been to ensure full backward
compatibility with the Verilog standard. Questa recognizes all reserved keywords listed in
Table B-1 in Annex B of IEEE Std 1800-2009.

In previous ModelSim releases, the vlog command read some IEEE Std 1800-2009 keywords
and treated them as IEEE Std 1800-2005 keywords. However, those keywords are no longer
recognized in the IEEE Std 1800-2005 keyword set.

The following reserved keywords have been added since IEEE Std 1800-2005:

accept_on reject_on sync_accept_on

checker restrict sync_reject_on
endchecker s_always unique0
eventually s_eventually until
global s_nexttime until_with
implies s_until untyped
let s_until_with weak
nexttime strong

If you use or produce SystemVerilog code that uses any of these strings as identifiers from a
previous release in which they were not considered reserved keywords, you can do either of the
following to avoid a compilation error:

• Use a different set of strings in your design. You can add one or more characters as a
prefix or suffix (such as an underscore, _) to the string, which will cause the string to be
read in as an identifier and not as a reserved keyword.
• Use the SystemVerilog pragmas `begin_keywords and `end_keywords to define
regions where only IEEE Std 1800-2005 keywords are recognized.

Recognizing SystemVerilog Files by File Name Extension

If you use the -sv argument with the vlog command, then ModelSim assumes that all input files
are SystemVerilog, regardless of their respective filename extensions.

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Verilog Compilation

If you do not use the -sv argument with the vlog command, then ModelSim assumes that only
files with the extension .sv, .svh, or .svp are SystemVerilog.

File extensions of include files

Similarly, if you do not use the -sv argument while reading in a file that uses an `include
statement to specify an include file, then the file extension of the include file is ignored and the
language is assumed to be the same as the file containing the `include. For example, if you do
not use the -sv argument:

If a.v included [Link], then [Link] would be read as a Verilog file.

If [Link] included d.v, then d.v would be read as a SystemVerilog file.

File extension settings in [Link]

You can define which file extensions indicate SystemVerilog files with the SVFileExtensions
variable in the [Link] file. By default, this variable is defined in [Link] as follows:

; SVFileExtensions = sv svp svh

For example, the following command:

vlog a.v [Link] [Link] d.v

reads in a.v and d.v as a Verilog files and reads in [Link] and [Link] as SystemVerilog files.

File types affecting compilation units

Note that whether a file is Verilog or SystemVerilog can affect when ModelSim changes from
one compilation unit to another.

By default, ModelSim instructs the compiler to treat all files within a compilation command line
as separate compilation units (single-file compilation unit mode, which is the equivalent of
using vlog -sfcu).

vlog a.v aa.v [Link] [Link] d.v

ModelSim would group these source files into three compilation units:

Files in first unit — a.v, aa.v, [Link]

File in second unit — [Link]
File in third unit — d.v
This behavior is governed by two basic rules:

• Anything read in is added to the current compilation unit.

• A compilation unit ends at the close of a SystemVerilog file.

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Initializing enum Variables

By default, ModelSim initializes enum variables using the default value of the base type instead
of the leftmost value. However, you can change this so that ModelSim sets the initial value of
an enum variable to the left most value in the following ways:

• Run vlog -enumfirstinit when compiling and run vsim -enumfirstinit when simulating.
• Set EnumBaseInit = 0 in the [Link] file.

Incremental Compilation
ModelSim supports incremental compilation of Verilog designs—there is no requirem