RAJIV GANDHI UNIVERSITY OF KNOWLEDGE
TECHNOLOGIES
RGUKT- SRIKAKULAM
DEPARTMENT OF ECE
Engg. (AY:2019-20) Semester-1 _LAB Internal Questions
Lab name: VLSI lab
1. Realize 8-bit RCA design using half-adder in Verilog HDL
Add the following numbers and store it in a 10-bit SISO register
a. A=44; B=55;
b. A=102; B=201;
c. A=83; B=56;
2. Design a 20-LED display system using two decoders (each 10 leds) and generate two
numbers to two decoders (one number is up count and another is down count.)
Design it in Multisim also.
3. Design the following counters using Verilog HDL
4. Design the following registers using Verilog HDL (Clock time period :175 ns)
(note: register in the question a PIPO register)
5. Design a Digital Clock using three always blocks (Seconds , Minutes, Hours) in Verilog HDL
and design digital clock using one always block after result compare the both programs RTLs.
6. Design three items vending machine based on following prices using Verilog HDL
Item Cost
Candy 5
Cake 10
Cold drink 15
7. Design the following vending machine using Verilog HDL
Type Type1 Type2
Item Cost
A = 50 A1 A2
B = 30 B1 B2
C =10 C1 C2
8. Design sequence detectors (melay) using Verilog HDL
a. 1001 b. 010 c. 101
9. Design following Flip-Flop converters using Verilog HDL
a. JK –FF to D- FF
b. D – FF to T- FF
10. Design 4KB memory using Verilog HDL and retrieve memory when read enable signal equal
to high and write memory when write enable signal equal to high.
Store 8-bits of data into given locations
Address Data
1240 45
4950 554
3450 280
190 249
11. Design following state diagram using Verilog HDL
12. Design Armed assault state diagram using Verilog HDL
The States represent what a unit might encounter during a fictional battle.
13. There are 4 push buttons available that allow you to operate the
machine: turnOn, turnOff, work, and stop. An espresso machine that has 3 states:
It can be turned off (OFF), it can be enabled and ready for operation (STANDBY)
and it can be actively pumping water to make an espresso (WORKING) .
14. A).Design Fibonacci series generated machine using Verilog HDL
(note: The adder must be a Ripple carry adder and series length is up to 1000.)
15. Design a Gray to Binary code converter and store the converted binary into a register.
Assign that binary number to Binary to Gray converter Inputs to the Gray to Binary
converter should be assigned by 4-bit counter using Verilog HDL.
16. Design the following circuit using Verilog HDL
17. Design the following LFSRs using Verilog HDL
a). X^6+X^3+1
b). X^5+X^2+X+1
c). X^8+X^2+X+1
Store the XOR gate output in a register and show the required number of clock pulses to
repeat the sequence.
18. Design the following circuit using Verilog HDL
Flip-flops are connected to 4 to 10 decoder and decoder connected to 7-segment display
19. Design following circuit using Verilog HDL write the expressions of F1 and F2
20. Design following SOP and POS functions using NAND gate using Verilog HDL
a). F2(A,B,C,D) = ∑m (1,2,5,7,10,13,15)
b). F4(A,B,C,D) = πM(0,3,6,9,12,,13,14)
21. Design the following circuit using Verilog HDL
22. Design Decimal adder using Verilog HDL
Add the following numbers 1. (12)10 and (9)10, 2. (8)10 and (9)10
23. Design a 8 to 1 MUX using 2 to 1 mux by module instantiation method
Instantiated modules includes data flow, gate level and behavioural modelling (includes
case statement, if condition and Use Conditional operator)
24. a).Design a 4 to 2 Priority encoder using 2 to 1 Mux by module instantiation method
using Verilog HDL.
b). Design a 8 to 3 priority encoder and display various tasks using Verilog HDL
25. Design following circuit using Verilog HDL
26. a). Design a common circuit for 3-bit Full ADDER - Full SUBTRACTOR using Verilog
HDL.
b). Design the following circuit using Verilog HDL
27. Design the following circuit using Verilog HDL
28. Design the following circuits using Verilog HDL
a). b).
29. a). Design ALU for the following operations using one conditional operator using Verilog
HDL
(Note: use conditional operator with in a conditional operator.)
b). Design the following random counters using Verilog HDL.
30. Design the following using Verilog HDL
31. Design Asynchronous 4-bit up/down counter with JK Flip-Flops using Verilog HDL.
32. Design a circuit that which count the number of 1’s in the given 10-bit shift register. If the
any bit value in the 10-bit register is equal to logic-1 then count should increase,
otherwise count should remain same. Count initial value is equal to zero.
33. Design the following Modulo counters at a clock frequency of 2GHz using Verilog HDL
34. Design GCD machine using Datapath and Controlpath using Verilog HDL.
35. Design 2X2 multiplier using Verilog HDL
a). Using Data Flow modelling
b). Using Gate level Modelling
36. Design a following system based on given state diagram using Verilog HDL
a). If Stata is forever given a sequence of ones (i.e. 11111…), where will it eventually end up?
b) If Stata is forever given a sequence of 01s (i.e. 010101…), which location will it never visit?
37. Design the following ASM using Verilog
38.
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