S32K1xx Series Reference Manual

Supports S32K116, S32K118, S32K142, S32K144, S32K146, and

S32K148

Document Number: S32K1XXRM

Rev. 11, 06/2019
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 Contents
Section number Title Page

Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 51

1.2 Organization..................................................................................................................................................................51

1.3 Module descriptions......................................................................................................................................................51

1.3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 52

1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 53

1.4 Register descriptions.....................................................................................................................................................54

1.5 Conventions.................................................................................................................................................................. 55

1.5.1 Notes, Cautions, and Warnings......................................................................................................................55

1.5.2 Numbering systems........................................................................................................................................55

1.5.3 Typographic notation..................................................................................................................................... 56

1.5.4 Special terms.................................................................................................................................................. 56

Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................59

2.2 S32K1xx Series introduction........................................................................................................................................ 59

2.2.1 S32K14x.........................................................................................................................................................59

2.2.2 S32K11x ........................................................................................................................................................61

2.3 Feature summary...........................................................................................................................................................62

2.4 Block diagram...............................................................................................................................................................65

2.5 Feature comparison.......................................................................................................................................................66

2.5.1 Differences between S32K14x and S32K11x................................................................................................68

2.6 Applications.................................................................................................................................................................. 69

2.7 Module functional categories........................................................................................................................................70

2.7.1 Arm Cortex-M4F Core Modules....................................................................................................................71

2.7.2 Arm Cortex-M0+ Core Modules....................................................................................................................72

2.7.3 System modules............................................................................................................................................. 72

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2.7.4 Memories and memory interfaces..................................................................................................................73

2.7.5 Power Management........................................................................................................................................74

2.7.6 Clocking......................................................................................................................................................... 74

2.7.7 Analog modules............................................................................................................................................. 75

2.7.8 Timer modules............................................................................................................................................... 75

2.7.9 Communication interfaces............................................................................................................................. 76

2.7.10 Debug modules.............................................................................................................................................. 77

Chapter 3
Memory Map
3.1 Introduction...................................................................................................................................................................79

3.2 SRAM memory map..................................................................................................................................................... 79

3.2.1 S32K14x: SRAM memory map .................................................................................................................... 79

3.2.2 S32K11x: SRAM memory map .................................................................................................................... 79

3.3 Flash memory map........................................................................................................................................................80

3.4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................80

3.4.1 Read-after-write sequence and required serialization of memory operations................................................81

3.5 Private Peripheral Bus (PPB) memory map..................................................................................................................82

3.6 Aliased bit-band regions for CM4 core........................................................................................................................ 83

Chapter 4
Signal Multiplexing and Pin Assignment
4.1 Introduction...................................................................................................................................................................85

4.2 Functional description...................................................................................................................................................85

4.3 Pad description..............................................................................................................................................................86

4.4 Default pad state........................................................................................................................................................... 87

4.5 Signal Multiplexing sheet............................................................................................................................................. 88

4.5.1 IO Signal Table ............................................................................................................................................. 88

4.5.2 Input muxing table......................................................................................................................................... 90

4.6 Pinout diagrams............................................................................................................................................................ 91

Chapter 5
Security Overview

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5.1 Introduction...................................................................................................................................................................93

5.2 Device security..............................................................................................................................................................93

5.2.1 Flash memory security................................................................................................................................... 93

5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................94

5.2.3 Device Boot modes........................................................................................................................................ 95

5.3 Security use case examples...........................................................................................................................................95

5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 95

5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 96

5.3.3 Secure communication................................................................................................................................... 97

5.3.4 Component protection....................................................................................................................................98

5.3.5 Message-authentication example................................................................................................................... 99

5.4 Steps required before failure analysis........................................................................................................................... 100

5.5 Security programming flow example (Secure Boot).................................................................................................... 101

Chapter 6
Safety Overview
6.1 Introduction...................................................................................................................................................................103

6.2 S32K1xx safety concept............................................................................................................................................... 104

6.2.1 Cortex-M4/M0+ Structural Core Self Test (SCST).......................................................................................105

6.2.2 ECC on RAM and flash memory................................................................................................................... 106

6.2.3 Power supply monitoring............................................................................................................................... 106

6.2.4 Clock monitoring........................................................................................................................................... 107

6.2.5 Temporal protection....................................................................................................................................... 107

6.2.6 Operational interference protection............................................................................................................... 107

6.2.7 CRC................................................................................................................................................................109

6.2.8 Diversity of system resources........................................................................................................................ 109

Chapter 7
CM4 Overview
7.1 Arm Cortex-M4F core configuration............................................................................................................................111

7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 112

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7.1.2 System Tick Timer.........................................................................................................................................112

7.1.3 Debug facilities.............................................................................................................................................. 112

7.1.4 Caches............................................................................................................................................................ 113

7.1.5 Core privilege levels...................................................................................................................................... 113

7.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 114

7.2.1 Interrupt priority levels.................................................................................................................................. 114

7.2.2 Non-maskable interrupt..................................................................................................................................115

7.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 115

7.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................116

7.3.1 Wake-up sources............................................................................................................................................ 116

7.4 FPU configuration.........................................................................................................................................................117

7.5 JTAG controller configuration......................................................................................................................................118

Chapter 8
CM0+ Overview
8.1 Arm Cortex-M0+ core introduction..............................................................................................................................119

8.1.1 Buses, interconnects, and interfaces.............................................................................................................. 120

8.1.2 System tick timer........................................................................................................................................... 120

8.1.3 Debug facilities.............................................................................................................................................. 120

8.1.4 Core privilege levels...................................................................................................................................... 120

8.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................121

8.2.1 Interrupt priority levels.................................................................................................................................. 121

8.2.2 Non-maskable interrupt..................................................................................................................................121

8.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 121

8.3 AWIC introduction....................................................................................................................................................... 122

8.3.1 Wake-up sources............................................................................................................................................ 122

Chapter 9
Micro Trace Buffer (MTB)
9.1 Introduction...................................................................................................................................................................125

9.1.1 Overview........................................................................................................................................................ 125

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9.1.2 Features.......................................................................................................................................................... 127

9.1.3 Modes of operation........................................................................................................................................ 128

9.2 Memory map and register definition.............................................................................................................................128

9.2.1 MTB_DWT Memory Map.............................................................................................................................129

Chapter 10
Miscellaneous Control Module (MCM)
10.1 Chip-specific MCM information.................................................................................................................................. 141

10.2 Introduction...................................................................................................................................................................142

10.2.1 Features.......................................................................................................................................................... 142

10.3 Memory map/register descriptions............................................................................................................................... 142

10.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................143

10.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 144

10.3.3 Core Platform Control Register (MCM_CPCR)............................................................................................145

10.3.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................... 148

10.3.5 Process ID Register (MCM_PID).................................................................................................................. 151

10.3.6 Compute Operation Control Register (MCM_CPO)..................................................................................... 152

10.3.7 Local Memory Descriptor Register (MCM_LMDRn)...................................................................................153

10.3.8 Local Memory Descriptor Register2 (MCM_LMDR2).................................................................................156

10.3.9 LMEM Parity and ECC Control Register (MCM_LMPECR).......................................................................160

10.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR)...................................................................... 161

10.3.11 LMEM Fault Address Register (MCM_LMFAR).........................................................................................162

10.3.12 LMEM Fault Attribute Register (MCM_LMFATR)..................................................................................... 163

10.3.13 LMEM Fault Data High Register (MCM_LMFDHR).................................................................................. 164

10.3.14 LMEM Fault Data Low Register (MCM_LMFDLR)....................................................................................164

10.4 Functional description...................................................................................................................................................165

10.4.1 Interrupts........................................................................................................................................................ 165

Chapter 11
System Integration Module (SIM)
11.1 Chip-specific SIM information..................................................................................................................................... 167

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11.1.1 SIM register bitfield implementation............................................................................................................. 167

11.2 Introduction...................................................................................................................................................................167

11.2.1 Features.......................................................................................................................................................... 167

11.3 Memory map and register definition.............................................................................................................................168

11.3.1 SIM register descriptions............................................................................................................................... 168

Chapter 12
Port Control and Interrupts (PORT)
12.1 Chip-specific PORT information..................................................................................................................................195

12.1.1 Number of PCRs............................................................................................................................................ 195

12.1.2 Finding address for PORTx_PCRn ...............................................................................................................196

12.1.3 I/O configuration sequence ........................................................................................................................... 196

12.1.4 Digital input filter configuration sequence ................................................................................................... 197

12.1.5 Reset pin configuration ................................................................................................................................. 198

12.2 Introduction...................................................................................................................................................................198

12.3 Overview.......................................................................................................................................................................198

12.3.1 Features.......................................................................................................................................................... 198

12.3.2 Modes of operation........................................................................................................................................ 199

12.4 External signal description............................................................................................................................................200

12.5 Detailed signal description............................................................................................................................................200

12.6 Memory map and register definition.............................................................................................................................200

12.6.1 Pin Control Register n (PORT_PCRn).......................................................................................................... 203

12.6.2 Global Pin Control Low Register (PORT_GPCLR)......................................................................................206

12.6.3 Global Pin Control High Register (PORT_GPCHR).....................................................................................206

12.6.4 Global Interrupt Control Low Register (PORT_GICLR).............................................................................. 207

12.6.5 Global Interrupt Control High Register (PORT_GICHR)............................................................................. 207

12.6.6 Interrupt Status Flag Register (PORT_ISFR)................................................................................................ 208

12.6.7 Digital Filter Enable Register (PORT_DFER).............................................................................................. 209

12.6.8 Digital Filter Clock Register (PORT_DFCR)................................................................................................209

12.6.9 Digital Filter Width Register (PORT_DFWR).............................................................................................. 210

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12.7 Functional description...................................................................................................................................................210

12.7.1 Pin control...................................................................................................................................................... 210

12.7.2 Global pin control.......................................................................................................................................... 211

12.7.3 Global interrupt control..................................................................................................................................212

12.7.4 External interrupts..........................................................................................................................................212

12.7.5 Digital filter....................................................................................................................................................213

Chapter 13
General-Purpose Input/Output (GPIO)
13.1 Chip-specific GPIO information...................................................................................................................................215

13.1.1 Instantiation information................................................................................................................................215

13.1.2 GPIO ports memory map............................................................................................................................... 215

13.1.3 GPIO register reset values .............................................................................................................................216

13.2 Introduction...................................................................................................................................................................216

13.2.1 Features.......................................................................................................................................................... 217

13.2.2 Modes of operation........................................................................................................................................ 217

13.2.3 GPIO signal descriptions............................................................................................................................... 217

13.3 Memory map and register definition.............................................................................................................................218

13.3.1 GPIO register descriptions............................................................................................................................. 218

13.4 Functional description...................................................................................................................................................226

13.4.1 General-purpose input....................................................................................................................................226

13.4.2 General-purpose output..................................................................................................................................226

Chapter 14
Crossbar Switch Lite (AXBS-Lite)
14.1 Chip-specific AXBS-Lite information..........................................................................................................................229

14.1.1 Crossbar Switch master assignments............................................................................................................. 229

14.1.2 Crossbar Switch slave assignments................................................................................................................229

14.2 Introduction...................................................................................................................................................................230

14.2.1 Features.......................................................................................................................................................... 230

14.3 Functional Description..................................................................................................................................................231

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14.3.1 General operation........................................................................................................................................... 231

14.3.2 Arbitration...................................................................................................................................................... 231

14.4 Initialization/application information........................................................................................................................... 233

Chapter 15
Memory Protection Unit (MPU)
15.1 Chip-specific MPU information................................................................................................................................... 235

15.1.1 MPU Slave Port Assignments........................................................................................................................235

15.1.2 MPU Logical Bus Master Assignments.........................................................................................................236

15.1.3 Current PID.................................................................................................................................................... 236

15.1.4 Region descriptors and slave port configuration............................................................................................236

15.2 Introduction...................................................................................................................................................................237

15.3 Overview.......................................................................................................................................................................237

15.3.1 Block diagram................................................................................................................................................ 237

15.3.2 Features.......................................................................................................................................................... 238

15.4 MPU register descriptions.............................................................................................................................................239

15.4.1 MPU Memory map........................................................................................................................................ 239

15.4.2 Control/Error Status Register (CESR)........................................................................................................... 242

15.4.3 Error Address Register, slave port n (EAR0 - EAR4)................................................................................... 244

15.4.4 Error Detail Register, slave port n (EDR0 - EDR4)...................................................................................... 245

15.4.5 Region Descriptor n, Word 0 (RGD0_WORD0 - RGD15_WORD0)...........................................................247

15.4.6 Region Descriptor 0, Word 1 (RGD0_WORD1)...........................................................................................248

15.4.7 Region Descriptor 0, Word 2 (RGD0_WORD2)...........................................................................................249

15.4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)...........................................................................................252

15.4.9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)...........................................................253

15.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)...........................................................254

15.4.11 Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_WORD3)...........................................................257

15.4.12 Region Descriptor Alternate Access Control 0 (RGDAAC0)....................................................................... 259

15.4.13 Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)............................................... 262

15.5 Functional description...................................................................................................................................................265

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15.5.1 Access evaluation macro................................................................................................................................265

15.5.2 Putting it all together and error terminations................................................................................................. 267

15.5.3 Power management........................................................................................................................................ 267

15.6 Initialization information.............................................................................................................................................. 268

15.7 Application information................................................................................................................................................268

Chapter 16
Peripheral Bridge (AIPS-Lite)
16.1 Chip-specific AIPS information................................................................................................................................... 271

16.1.1 Instantiation information................................................................................................................................271

16.1.2 Memory maps................................................................................................................................................ 271

16.2 Introduction...................................................................................................................................................................272

16.2.1 Features.......................................................................................................................................................... 273

16.2.2 General operation........................................................................................................................................... 273

16.3 Memory map/register definition................................................................................................................................... 273

16.3.1 AIPS register descriptions..............................................................................................................................273

16.4 Functional description...................................................................................................................................................317

16.4.1 Access support............................................................................................................................................... 317

Chapter 17
Direct Memory Access Multiplexer (DMAMUX)
17.1 Chip-specific DMAMUX information......................................................................................................................... 319

17.1.1 Number of channels ...................................................................................................................................... 319

17.1.2 DMA transfers via TRGMUX trigger............................................................................................................319

17.2 Introduction...................................................................................................................................................................320

17.2.1 Overview........................................................................................................................................................ 320

17.2.2 Features.......................................................................................................................................................... 320

17.2.3 Modes of operation........................................................................................................................................ 321

17.3 Memory map/register definition................................................................................................................................... 321

17.3.1 DMAMUX register descriptions....................................................................................................................321

17.4 Functional description...................................................................................................................................................323

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17.4.1 DMA channels with periodic triggering capability........................................................................................323

17.4.2 DMA channels with no triggering capability.................................................................................................326

17.4.3 Always-enabled DMA sources...................................................................................................................... 326

17.5 Initialization/application information........................................................................................................................... 327

17.5.1 Reset...............................................................................................................................................................327

17.5.2 Enabling and configuring sources..................................................................................................................327

Chapter 18
Enhanced Direct Memory Access (eDMA)
18.1 Chip-specific eDMA information ................................................................................................................................ 331

18.1.1 Seamless eDMA transfer .............................................................................................................................. 331

18.1.2 Number of channels ...................................................................................................................................... 332

18.2 Introduction...................................................................................................................................................................332

18.2.1 eDMA system block diagram........................................................................................................................ 332

18.2.2 Block parts..................................................................................................................................................... 333

18.2.3 Features.......................................................................................................................................................... 334

18.3 Modes of operation....................................................................................................................................................... 335

18.4 Memory map/register definition................................................................................................................................... 336

18.4.1 TCD memory................................................................................................................................................. 336

18.4.2 TCD initialization.......................................................................................................................................... 336

18.4.3 TCD structure.................................................................................................................................................336

18.4.4 Reserved memory and bit fields.....................................................................................................................337

18.4.5 DMA register descriptions............................................................................................................................. 337

18.5 Functional description...................................................................................................................................................386

18.5.1 eDMA basic data flow................................................................................................................................... 386

18.5.2 Fault reporting and handling.......................................................................................................................... 389

18.5.3 Channel preemption....................................................................................................................................... 392

18.6 Initialization/application information........................................................................................................................... 392

18.6.1 eDMA initialization....................................................................................................................................... 392

18.6.2 Programming errors....................................................................................................................................... 394

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18.6.3 Arbitration mode considerations.................................................................................................................... 395

18.6.4 Performing DMA transfers............................................................................................................................ 395

18.6.5 Monitoring transfer descriptor status............................................................................................................. 399

18.6.6 Channel Linking.............................................................................................................................................401

18.6.7 Dynamic programming.................................................................................................................................. 402

18.6.8 Suspend/resume a DMA channel with active hardware service requests...................................................... 406

Chapter 19
Trigger MUX Control (TRGMUX)
19.1 Chip-specific TRGMUX information...........................................................................................................................409

19.1.1 Module interconnectivity............................................................................................................................... 409

19.1.2 TRGMUX register information..................................................................................................................... 413

19.2 Introduction...................................................................................................................................................................413

19.3 Features......................................................................................................................................................................... 413

19.4 Memory map and register definition.............................................................................................................................414

19.4.1 TRGMUX register descriptions..................................................................................................................... 414

Chapter 20
External Watchdog Monitor (EWM)
20.1 Chip-specific EWM information ................................................................................................................................. 453

20.1.1 EWM_OUT signal configuration...................................................................................................................453

20.1.2 EWM Memory Map access............................................................................................................................453

20.1.3 EWM low-power modes................................................................................................................................ 453

20.2 Introduction...................................................................................................................................................................453

20.2.1 Features.......................................................................................................................................................... 454

20.2.2 Modes of Operation....................................................................................................................................... 454

20.2.3 Block Diagram............................................................................................................................................... 455

20.3 EWM Signal Descriptions............................................................................................................................................ 456

20.4 Memory Map/Register Definition.................................................................................................................................457

20.4.1 EWM register descriptions.............................................................................................................................457

20.5 Functional Description..................................................................................................................................................462

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20.5.1 The EWM_OUT_b Signal............................................................................................................................. 462

20.5.2 EWM_OUT_b pin state in low power modes................................................................................................463

20.5.3 The EWM_in Signal...................................................................................................................................... 463

20.5.4 EWM Counter................................................................................................................................................ 464

20.5.5 EWM Compare Registers.............................................................................................................................. 464

20.5.6 EWM Refresh Mechanism.............................................................................................................................464

20.5.7 EWM Interrupt............................................................................................................................................... 465

20.5.8 Counter clock prescaler..................................................................................................................................465

Chapter 21
Error Injection Module (EIM)
21.1 Chip-specific EIM information.....................................................................................................................................467

21.1.1 EIM channel assignments.............................................................................................................................. 467

21.2 Introduction...................................................................................................................................................................467

21.2.1 Overview........................................................................................................................................................ 467

21.2.2 Features.......................................................................................................................................................... 469

21.3 EIM register descriptions..............................................................................................................................................469

21.3.1 EIM Memory map..........................................................................................................................................470

21.3.2 Error Injection Module Configuration Register (EIMCR)............................................................................ 470

21.3.3 Error Injection Channel Enable register (EICHEN)...................................................................................... 471

21.3.4 Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 - EICHD1_WORD0)............................474

21.3.5 Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)............................476

21.4 Functional description...................................................................................................................................................477

21.4.1 Error injection scenarios................................................................................................................................ 477

Chapter 22
Error Reporting Module (ERM)
22.1 Chip-specific ERM information................................................................................................................................... 479

22.1.1 Sources of memory error events.................................................................................................................... 479

22.2 Introduction...................................................................................................................................................................479

22.2.1 Overview........................................................................................................................................................ 479

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22.2.2 Features.......................................................................................................................................................... 480

22.3 ERM register descriptions.............................................................................................................................................480

22.3.1 ERM Memory map........................................................................................................................................ 480

22.3.2 ERM Configuration Register 0 (CR0)........................................................................................................... 481

22.3.3 ERM Status Register 0 (SR0)........................................................................................................................ 483

22.3.4 ERM Memory n Error Address Register (EAR0 - EAR1)............................................................................ 485

22.4 Functional description...................................................................................................................................................486

22.4.1 Single-bit correction events........................................................................................................................... 486

22.4.2 Non-correctable error events..........................................................................................................................487

22.5 Initialization.................................................................................................................................................................. 488

Chapter 23
Watchdog timer (WDOG)
23.1 Chip-specific WDOG information................................................................................................................................489

23.1.1 WDOG clocks................................................................................................................................................ 489

23.1.2 WDOG low-power modes............................................................................................................................. 489

23.1.3 Default watchdog timeout ............................................................................................................................. 490

23.1.4 Watchdog Timeout Reaction......................................................................................................................... 490

23.2 Introduction...................................................................................................................................................................491

23.2.1 Features.......................................................................................................................................................... 491

23.2.2 Block diagram................................................................................................................................................ 492

23.3 Memory map and register definition.............................................................................................................................492

23.3.1 WDOG register descriptions.......................................................................................................................... 492

23.4 Functional description...................................................................................................................................................499

23.4.1 Clock source...................................................................................................................................................499

23.4.2 Watchdog refresh mechanism........................................................................................................................ 500

23.4.3 Configuring the Watchdog.............................................................................................................................502

23.4.4 Using interrupts to delay resets...................................................................................................................... 503

23.4.5 Backup reset................................................................................................................................................... 503

23.4.6 Functionality in debug and low-power modes............................................................................................... 504

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23.4.7 Fast testing of the watchdog...........................................................................................................................504

23.5 Application Information................................................................................................................................................506

23.5.1 Disable Watchdog.......................................................................................................................................... 506

23.5.2 Disable Watchdog after Reset........................................................................................................................506

23.5.3 Configure Watchdog...................................................................................................................................... 507

23.5.4 Refreshing the Watchdog...............................................................................................................................507

Chapter 24
Cyclic Redundancy Check (CRC)
24.1 Chip-specific CRC information.................................................................................................................................... 509

24.2 Introduction...................................................................................................................................................................509

24.2.1 Features.......................................................................................................................................................... 509

24.2.2 Block diagram................................................................................................................................................ 510

24.2.3 Modes of operation........................................................................................................................................ 510

24.3 Memory map and register descriptions.........................................................................................................................510

24.3.1 CRC register descriptions.............................................................................................................................. 510

24.4 Functional description...................................................................................................................................................515

24.4.1 CRC initialization/reinitialization.................................................................................................................. 515

24.4.2 CRC calculations............................................................................................................................................515

24.4.3 Transpose feature........................................................................................................................................... 516

24.4.4 CRC result complement................................................................................................................................. 518

Chapter 25
Reset and Boot
25.1 Introduction...................................................................................................................................................................519

25.2 Reset..............................................................................................................................................................................519

25.2.1 Power-on reset (POR).................................................................................................................................... 520

25.2.2 System reset sources...................................................................................................................................... 520

25.2.3 MCU Resets................................................................................................................................................... 524

25.2.4 Reset pin ........................................................................................................................................................524

25.2.5 Debug resets................................................................................................................................................... 525

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25.3 Boot...............................................................................................................................................................................526

25.3.1 Boot sources................................................................................................................................................... 526

25.3.2 FOPT boot options......................................................................................................................................... 526

25.3.3 Boot sequence................................................................................................................................................ 527

Chapter 26
Reset Control Module (RCM)
26.1 Chip-specific RCM information................................................................................................................................... 529

26.1.1 RCM register information ............................................................................................................................. 529

26.2 Reset pin filter operation in STOP1/2 modes .............................................................................................................. 530

26.3 Introduction...................................................................................................................................................................530

26.4 Reset memory map and register descriptions............................................................................................................... 530

26.4.1 Version ID Register (RCM_VERID).............................................................................................................531

26.4.2 Parameter Register (RCM_PARAM)............................................................................................................ 532

26.4.3 System Reset Status Register (RCM_SRS)................................................................................................... 534

26.4.4 Reset Pin Control register (RCM_RPC)........................................................................................................ 537

26.4.5 Sticky System Reset Status Register (RCM_SSRS)......................................................................................539

26.4.6 System Reset Interrupt Enable Register (RCM_SRIE)................................................................................. 541

Chapter 27
Clock Distribution
27.1 Introduction...................................................................................................................................................................545

27.2 High level clocking diagram.........................................................................................................................................545

27.3 Clock definitions...........................................................................................................................................................546

27.4 Internal clocking requirements..................................................................................................................................... 548

27.4.1 Clock divider values after reset......................................................................................................................552

27.4.2 HSRUN mode clocking................................................................................................................................. 552

27.4.3 VLPR mode clocking.....................................................................................................................................552

27.4.4 VLPR/VLPS mode entry............................................................................................................................... 552

27.5 Clock Gating................................................................................................................................................................. 553

27.6 Module clocks...............................................................................................................................................................553

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Chapter 28
System Clock Generator (SCG)
28.1 Chip-specific SCG information.................................................................................................................................... 565

28.1.1 Supported frequency ranges...........................................................................................................................565

28.1.2 Oscillator and SPLL guidelines..................................................................................................................... 565

28.1.3 System clock switching .................................................................................................................................566

28.1.4 System clock and clock monitor requirement ...............................................................................................566

28.2 Introduction...................................................................................................................................................................567

28.2.1 Features.......................................................................................................................................................... 567

28.3 Memory Map/Register Definition.................................................................................................................................568

28.3.1 Version ID Register (SCG_VERID)..............................................................................................................569

28.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 570

28.3.3 Clock Status Register (SCG_CSR)................................................................................................................ 571

28.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................573

28.3.5 VLPR Clock Control Register (SCG_VCCR)............................................................................................... 575

28.3.6 HSRUN Clock Control Register (SCG_HCCR)............................................................................................577

28.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................579

28.3.8 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................581

28.3.9 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 583

28.3.10 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 584

28.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................586

28.3.12 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 587

28.3.13 Slow IRC Configuration Register (SCG_SIRCCFG).................................................................................... 588

28.3.14 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 589

28.3.15 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................591

28.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 592

28.3.17 System PLL Control Status Register (SCG_SPLLCSR)............................................................................... 593

28.3.18 System PLL Divide Register (SCG_SPLLDIV)............................................................................................595

28.3.19 System PLL Configuration Register (SCG_SPLLCFG)............................................................................... 596

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28.4 Functional description...................................................................................................................................................598

28.4.1 SCG Clock Mode Transitions........................................................................................................................ 598

Chapter 29
Peripheral Clock Controller (PCC)
29.1 Chip-specific PCC information.....................................................................................................................................601

29.1.1 PCC register information............................................................................................................................... 601

29.2 Introduction...................................................................................................................................................................604

29.3 Features......................................................................................................................................................................... 604

29.4 Functional description...................................................................................................................................................605

29.5 Memory map and register definition.............................................................................................................................606

29.6 PCC register descriptions..............................................................................................................................................606

29.6.1 PCC Memory map......................................................................................................................................... 606

29.6.2 PCC FTFC Register (PCC_FTFC)................................................................................................................ 607

29.6.3 PCC DMAMUX Register (PCC_DMAMUX).............................................................................................. 609

29.6.4 PCC FlexCAN0 Register (PCC_FlexCAN0)................................................................................................ 610

29.6.5 PCC FlexCAN1 Register (PCC_FlexCAN1)................................................................................................ 612

29.6.6 PCC FTM3 Register (PCC_FTM3)............................................................................................................... 613

29.6.7 PCC ADC1 Register (PCC_ADC1)...............................................................................................................615

29.6.8 PCC FlexCAN2 Register (PCC_FlexCAN2)................................................................................................ 616

29.6.9 PCC LPSPI0 Register (PCC_LPSPI0)...........................................................................................................618

29.6.10 PCC LPSPI1 Register (PCC_LPSPI1)...........................................................................................................620

29.6.11 PCC LPSPI2 Register (PCC_LPSPI2)...........................................................................................................621

29.6.12 PCC PDB1 Register (PCC_PDB1)................................................................................................................ 623

29.6.13 PCC CRC Register (PCC_CRC)....................................................................................................................625

29.6.14 PCC PDB0 Register (PCC_PDB0)................................................................................................................ 626

29.6.15 PCC LPIT Register (PCC_LPIT)...................................................................................................................628

29.6.16 PCC FTM0 Register (PCC_FTM0)............................................................................................................... 629

29.6.17 PCC FTM1 Register (PCC_FTM1)............................................................................................................... 631

29.6.18 PCC FTM2 Register (PCC_FTM2)............................................................................................................... 632

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29.6.19 PCC ADC0 Register (PCC_ADC0)...............................................................................................................634

29.6.20 PCC RTC Register (PCC_RTC).................................................................................................................... 636

29.6.21 PCC LPTMR0 Register (PCC_LPTMR0)..................................................................................................... 637

29.6.22 PCC PORTA Register (PCC_PORTA)......................................................................................................... 639

29.6.23 PCC PORTB Register (PCC_PORTB)..........................................................................................................641

29.6.24 PCC PORTC Register (PCC_PORTC)..........................................................................................................642

29.6.25 PCC PORTD Register (PCC_PORTD)......................................................................................................... 644

29.6.26 PCC PORTE Register (PCC_PORTE).......................................................................................................... 645

29.6.27 PCC SAI0 Register (PCC_SAI0)...................................................................................................................647

29.6.28 PCC SAI1 Register (PCC_SAI1)...................................................................................................................648

29.6.29 PCC FlexIO Register (PCC_FlexIO)............................................................................................................. 650

29.6.30 PCC EWM Register (PCC_EWM)................................................................................................................ 651

29.6.31 PCC LPI2C0 Register (PCC_LPI2C0).......................................................................................................... 653

29.6.32 PCC LPI2C1 Register (PCC_LPI2C1).......................................................................................................... 654

29.6.33 PCC LPUART0 Register (PCC_LPUART0)................................................................................................ 656

29.6.34 PCC LPUART1 Register (PCC_LPUART1)................................................................................................ 657

29.6.35 PCC LPUART2 Register (PCC_LPUART2)................................................................................................ 659

29.6.36 PCC FTM4 Register (PCC_FTM4)............................................................................................................... 661

29.6.37 PCC FTM5 Register (PCC_FTM5)............................................................................................................... 662

29.6.38 PCC FTM6 Register (PCC_FTM6)............................................................................................................... 664

29.6.39 PCC FTM7 Register (PCC_FTM7)............................................................................................................... 666

29.6.40 PCC CMP0 Register (PCC_CMP0)...............................................................................................................667

29.6.41 PCC QSPI Register (PCC_QSPI).................................................................................................................. 669

29.6.42 PCC ENET Register (PCC_ENET)............................................................................................................... 671

Chapter 30
Clock Monitoring Unit (CMU)
30.1 CMU chip-specific information....................................................................................................................................673

30.2 Introduction...................................................................................................................................................................674

30.2.1 Basic operation...............................................................................................................................................675

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30.2.2 Features.......................................................................................................................................................... 676

30.3 CMU_FC register descriptions..................................................................................................................................... 676

30.3.1 CMU_FC Memory map................................................................................................................................. 676

30.3.2 Global Configuration Register (GCR)........................................................................................................... 677

30.3.3 Reference Count Configuration Register (RCCR).........................................................................................678

30.3.4 High Threshold Configuration Register (HTCR).......................................................................................... 679

30.3.5 Low Threshold Configuration Register (LTCR)........................................................................................... 680

30.3.6 Status Register (SR)....................................................................................................................................... 681

30.3.7 Interrupt Enable Register (IER)..................................................................................................................... 682

30.4 Functional description...................................................................................................................................................685

30.4.1 Monitored clock lost...................................................................................................................................... 685

30.5 Programming guidelines............................................................................................................................................... 685

30.5.1 Programming HFREF and LFREF................................................................................................................ 685

30.5.2 Programming RCCR[REF_CNT].................................................................................................................. 686

30.5.3 CMU_FC programming sequence................................................................................................................. 687

Chapter 31
Memories and Memory Interfaces
31.1 Introduction...................................................................................................................................................................689

31.2 Flash Memory Controller and flash memory modules................................................................................................. 689

31.3 SRAM configuration.....................................................................................................................................................690

31.3.1 SRAM sizes....................................................................................................................................................690

31.3.2 SRAM accessibility........................................................................................................................................691

31.3.3 SRAM arbitration and priority control...........................................................................................................692

31.3.4 SRAM retention: power modes and resets.....................................................................................................692

31.3.5 SRAM access: Behavior of device when in accessing a memory with multi-bit ECC error.........................693

Chapter 32
PRAM Controller (PRAMC)
32.1 PRAMC chip-specific information .............................................................................................................................. 695

32.2 Introduction...................................................................................................................................................................695

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32.3 Memory map and register definition.............................................................................................................................696

32.4 Functional description...................................................................................................................................................696

32.4.1 Error Correcting Code (ECC)........................................................................................................................ 696

32.4.2 Read/Write introduction.................................................................................................................................697

32.4.3 Reads.............................................................................................................................................................. 697

32.4.4 Writes............................................................................................................................................................. 698

32.4.5 Late write hits.................................................................................................................................................699

32.5 Initialization / application information......................................................................................................................... 700

Chapter 33
Local Memory Controller (LMEM)
33.1 Chip-specific LMEM information ............................................................................................................................... 701

33.1.1 LMEM region description..............................................................................................................................701

33.1.2 LMEM SRAM sizes.......................................................................................................................................701

33.2 Introduction...................................................................................................................................................................701

33.2.1 Block Diagram............................................................................................................................................... 702

33.2.2 Cache features................................................................................................................................................ 703

33.3 Memory Map/Register Definition.................................................................................................................................705

33.3.1 LMEM register descriptions.......................................................................................................................... 705

33.4 Functional Description..................................................................................................................................................714

33.4.1 LMEM Function............................................................................................................................................ 714

33.4.2 SRAM Function............................................................................................................................................. 715

33.4.3 Cache Function.............................................................................................................................................. 717

33.4.4 Cache Control................................................................................................................................................ 718

Chapter 34
Miscellaneous System Control Module (MSCM)
34.1 Chip-specific MSCM information................................................................................................................................ 723

34.1.1 Chip-specific TMLSZ/TMUSZ information................................................................................................. 723

34.1.2 Chip-specific register information................................................................................................................. 723

34.2 Overview.......................................................................................................................................................................724

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34.3 Chip Configuration and Boot........................................................................................................................................724

34.4 MSCM Memory Map/Register Definition....................................................................................................................725

34.4.1 CPU Configuration Memory Map and Registers...........................................................................................725

34.4.2 MSCM register descriptions.......................................................................................................................... 725

Chapter 35
Flash Memory Controller (FMC)
35.1 Chip-specific FMC information....................................................................................................................................757

35.1.1 FMC masters.................................................................................................................................................. 757

35.1.2 Program flash and Data flash port width....................................................................................................... 758

35.2 Introduction...................................................................................................................................................................758

35.2.1 Overview........................................................................................................................................................ 758

35.2.2 Features.......................................................................................................................................................... 758

35.3 Modes of operation....................................................................................................................................................... 759

35.4 External signal description............................................................................................................................................759

35.5 Functional description...................................................................................................................................................759

35.5.1 Default configuration..................................................................................................................................... 759

35.5.2 Speculative reads............................................................................................................................................760

35.6 Initialization and application information.....................................................................................................................761

Chapter 36
Flash Memory Module (FTFC)
36.1 Chip-specific FTFC information...................................................................................................................................763

36.1.1 Flash memory types....................................................................................................................................... 763

36.1.2 Flash memory sizes........................................................................................................................................ 764

36.1.3 Flash memory map.........................................................................................................................................783

36.1.4 Flash memory security................................................................................................................................... 784

36.1.5 Power mode restrictions on flash memory programming.............................................................................. 784

36.1.6 Flash memory modes..................................................................................................................................... 784

36.1.7 Erase all contents of flash memory................................................................................................................ 784

36.1.8 Customize MCU operations via FTFC_FOPT register..................................................................................785

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36.1.9 Simultaneous operations on PFLASH read partitions .................................................................................. 785

36.2 Introduction...................................................................................................................................................................785

36.2.1 Features.......................................................................................................................................................... 786

36.2.2 Block diagram................................................................................................................................................ 788

36.2.3 Glossary......................................................................................................................................................... 789

36.3 External signal description............................................................................................................................................791

36.4 Memory map and registers............................................................................................................................................792

36.4.1 Flash configuration field description............................................................................................................. 792

36.4.2 Program flash 0 IFR map............................................................................................................................... 792

36.4.3 Data flash 0 IFR map..................................................................................................................................... 793

36.4.4 Register descriptions...................................................................................................................................... 794

36.5 Functional description...................................................................................................................................................812

36.5.1 Flash protection..............................................................................................................................................812

36.5.2 FlexNVM description.................................................................................................................................... 814

36.5.3 Interrupts........................................................................................................................................................ 817

36.5.4 Flash operation in low-power modes............................................................................................................. 818

36.5.5 Functional modes of operation.......................................................................................................................818

36.5.6 Flash memory reads and ignored writes........................................................................................................ 818

36.5.7 Read while write (RWW).............................................................................................................................. 819

36.5.8 Flash program and erase................................................................................................................................ 819

36.5.9 FTFC command operations............................................................................................................................819

36.5.10 Margin read commands..................................................................................................................................826

36.5.11 Flash command descriptions.......................................................................................................................... 827

36.5.12 Security.......................................................................................................................................................... 853

36.5.13 Cryptographic Services Engine (CSEc)......................................................................................................... 855

36.5.14 Reset sequence............................................................................................................................................... 893

Chapter 37
Quad Serial Peripheral Interface (QuadSPI)
37.1 Chip-specific QuadSPI information..............................................................................................................................895

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37.1.1 Overview........................................................................................................................................................ 895

37.1.2 Memory size requirement ............................................................................................................................. 895

37.1.3 QuadSPI register reset values........................................................................................................................ 896

37.1.4 Use case..........................................................................................................................................................896

37.1.5 Supported read modes.................................................................................................................................... 896

37.1.6 External memory options............................................................................................................................... 897

37.1.7 Recommended software configuration.......................................................................................................... 897

37.1.8 Recommended programming sequence......................................................................................................... 898

37.1.9 Clock ratio between QuadSPI clocks ............................................................................................................898

37.1.10 QuadSPI_MCR[SCLKCFG] implementation ...............................................................................................898

37.1.11 QuadSPI_SOCCR[SOCCFG] implementation .............................................................................................899

37.2 Introduction...................................................................................................................................................................901

37.2.1 Features.......................................................................................................................................................... 901

37.2.2 Block Diagram............................................................................................................................................... 902

37.2.3 QuadSPI Modes of Operation........................................................................................................................ 903

37.2.4 Acronyms and Abbreviations.........................................................................................................................904

37.2.5 Glossary for QuadSPI module....................................................................................................................... 904

37.3 External Signal Description.......................................................................................................................................... 906

37.3.1 Driving External Signals................................................................................................................................ 907

37.4 Memory Map and Register Definition..........................................................................................................................909

37.4.1 Register Write Access.................................................................................................................................... 909

37.4.2 Peripheral Bus Register Descriptions............................................................................................................ 910

37.4.3 Serial Flash Address Assignment.................................................................................................................. 954

37.5 Flash memory mapped AMBA bus.............................................................................................................................. 955

37.5.1 AHB Bus Access Considerations...................................................................................................................956

37.5.2 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A..................................................... 956

37.5.3 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B..................................................... 957

37.5.4 AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31).......................................................................... 958

37.6 Interrupt Signals............................................................................................................................................................960

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37.7 Functional Description..................................................................................................................................................961

37.7.1 Serial Flash Access Schemes......................................................................................................................... 961

37.7.2 Normal Mode................................................................................................................................................. 961

37.7.3 HyperRAM Support....................................................................................................................................... 980

37.8 Initialization/Application Information.......................................................................................................................... 981

37.8.1 Power Up and Reset....................................................................................................................................... 981

37.8.2 Available Status/Flag Information................................................................................................................. 981

37.8.3 Flash Device Selection...................................................................................................................................984

37.8.4 DMA Usage................................................................................................................................................... 984

37.9 Byte Ordering - Endianness.......................................................................................................................................... 988

37.9.1 Programming Flash Data............................................................................................................................... 989

37.9.2 Reading Flash Data into the RX Buffer......................................................................................................... 989

37.9.3 Reading Flash Data into the AHB Buffer...................................................................................................... 990

37.10 Driving Flash Control Signals in Single and Dual Mode............................................................................................. 991

37.11 Serial Flash Devices......................................................................................................................................................991

37.11.1 Example Sequences........................................................................................................................................991

37.12 Sampling of Serial Flash Input Data.............................................................................................................................997

37.12.1 Basic Description........................................................................................................................................... 997

37.12.2 Supported read modes.................................................................................................................................... 998

37.12.3 Data Strobe (DQS) sampling method............................................................................................................ 1001

37.13 Data Input Hold Requirement of Flash.........................................................................................................................1004

Chapter 38
Power Management
38.1 Introduction...................................................................................................................................................................1005

38.2 Power modes description.............................................................................................................................................. 1005

38.3 Entering and exiting power modes............................................................................................................................... 1007

38.4 Clocking modes............................................................................................................................................................ 1007

38.4.1 Clock gating................................................................................................................................................... 1007

38.4.2 Stop mode options..........................................................................................................................................1007

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38.4.3 DMA wake-up................................................................................................................................................1008

38.4.4 Compute Operation (CPO).............................................................................................................................1009

38.4.5 Peripheral Doze..............................................................................................................................................1010

38.5 Power mode transitions.................................................................................................................................................1011

38.6 Shutdown sequencing for power modes....................................................................................................................... 1012

38.7 Power mode restrictions on flash memory programming.............................................................................................1012

38.8 Module operation in available power modes................................................................................................................ 1013

38.9 QuadSPI, Ethernet, and SAI operation ........................................................................................................................ 1017

Chapter 39
System Mode Controller (SMC)
39.1 Introduction...................................................................................................................................................................1019

39.2 Modes of operation....................................................................................................................................................... 1019

39.3 Memory map and register descriptions.........................................................................................................................1021

39.3.1 SMC Version ID Register (SMC_VERID)....................................................................................................1022

39.3.2 SMC Parameter Register (SMC_PARAM)................................................................................................... 1023

39.3.3 Power Mode Protection register (SMC_PMPROT).......................................................................................1024

39.3.4 Power Mode Control register (SMC_PMCTRL)...........................................................................................1025

39.3.5 Stop Control Register (SMC_STOPCTRL)...................................................................................................1027

39.3.6 Power Mode Status register (SMC_PMSTAT)............................................................................................. 1029

39.4 Functional description...................................................................................................................................................1029

39.4.1 Power mode transitions.................................................................................................................................. 1030

39.4.2 Power mode entry/exit sequencing................................................................................................................ 1031

39.4.3 Run modes......................................................................................................................................................1034

39.4.4 Stop modes..................................................................................................................................................... 1036

39.4.5 Debug in low power modes........................................................................................................................... 1037

Chapter 40
Power Management Controller (PMC)
40.1 Chip-specific PMC information....................................................................................................................................1039

40.1.1 Modes supported............................................................................................................................................ 1039

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40.2 Introduction...................................................................................................................................................................1039

40.3 Features......................................................................................................................................................................... 1039

40.4 Modes of Operation...................................................................................................................................................... 1040

40.4.1 Full Performance Mode (FPM)......................................................................................................................1040

40.4.2 Low Power Mode (LPM)............................................................................................................................... 1040

40.5 Low Voltage Detect (LVD) System............................................................................................................................. 1040

40.5.1 Low Voltage Reset (LVR) Operation............................................................................................................ 1041

40.5.2 LVD Interrupt Operation............................................................................................................................... 1041

40.5.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 1041

40.6 Memory Map and Register Definition..........................................................................................................................1041

40.6.1 PMC register descriptions.............................................................................................................................. 1041

Chapter 41
ADC Configuration
41.1 Instantiation information...............................................................................................................................................1049

41.1.1 Number of ADC channels..............................................................................................................................1049

41.1.2 ADC Connections/Channel Assignment........................................................................................................1050

41.2 Register implementation............................................................................................................................................... 1051

41.3 DMA Support on ADC................................................................................................................................................. 1051

41.4 ADC Hardware Interleaved Channels.......................................................................................................................... 1052

41.5 ADC internal supply monitoring.................................................................................................................................. 1053

41.6 ADC Reference Options............................................................................................................................................... 1053

41.7 ADC Trigger Sources................................................................................................................................................... 1053

41.7.1 PDB triggering scheme.................................................................................................................................. 1055

41.7.2 TRGMUX trigger scheme..............................................................................................................................1056

41.8 Trigger Selection...........................................................................................................................................................1057

41.9 Trigger Latching and Arbitration..................................................................................................................................1058

41.10 ADC triggering configurations .................................................................................................................................... 1060

41.11 ADC low-power modes................................................................................................................................................ 1067

41.12 ADC Trigger Concept – Use Case................................................................................................................................1067

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41.13 ADC calibration scheme............................................................................................................................................... 1069

41.14 S32K11X to S32K14X difference ............................................................................................................................... 1070

Chapter 42
Analog-to-Digital Converter (ADC)
42.1 Chip-specific ADC information....................................................................................................................................1071

42.2 Introduction...................................................................................................................................................................1071

42.2.1 Features.......................................................................................................................................................... 1071

42.2.2 Block diagram................................................................................................................................................ 1072

42.3 ADC signal descriptions............................................................................................................................................... 1073

42.3.1 Analog Power (VDDA)................................................................................................................................. 1073

42.3.2 Analog Ground (VSSA).................................................................................................................................1073

42.3.3 Voltage Reference Select............................................................................................................................... 1073

42.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 1074

42.4 ADC register descriptions.............................................................................................................................................1074

42.4.1 ADC Memory map.........................................................................................................................................1074

42.4.2 ADC Status and Control Register 1 (SC1A - aSC1P)................................................................................... 1076

42.4.3 ADC Configuration Register 1 (CFG1)......................................................................................................... 1079

42.4.4 ADC Configuration Register 2 (CFG2)......................................................................................................... 1081

42.4.5 ADC Data Result Registers (RA - aRP)........................................................................................................ 1082

42.4.6 Compare Value Registers (CV1 - CV2)........................................................................................................ 1084

42.4.7 Status and Control Register 2 (SC2).............................................................................................................. 1085

42.4.8 Status and Control Register 3 (SC3).............................................................................................................. 1088

42.4.9 BASE Offset Register (BASE_OFS)............................................................................................................. 1089

42.4.10 ADC Offset Correction Register (OFS).........................................................................................................1090

42.4.11 USER Offset Correction Register (USR_OFS)............................................................................................. 1091

42.4.12 ADC X Offset Correction Register (XOFS).................................................................................................. 1092

42.4.13 ADC Y Offset Correction Register (YOFS).................................................................................................. 1093

42.4.14 ADC Gain Register (G)..................................................................................................................................1094

42.4.15 ADC User Gain Register (UG)...................................................................................................................... 1096

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42.4.16 ADC General Calibration Value Register S (CLPS)..................................................................................... 1097

42.4.17 ADC Plus-Side General Calibration Value Register 3 (CLP3)..................................................................... 1098

42.4.18 ADC Plus-Side General Calibration Value Register 2 (CLP2)..................................................................... 1099

42.4.19 ADC Plus-Side General Calibration Value Register 1 (CLP1)..................................................................... 1099

42.4.20 ADC Plus-Side General Calibration Value Register 0 (CLP0)..................................................................... 1100

42.4.21 ADC Plus-Side General Calibration Value Register X (CLPX)....................................................................1101

42.4.22 ADC Plus-Side General Calibration Value Register 9 (CLP9)..................................................................... 1102

42.4.23 ADC General Calibration Offset Value Register S (CLPS_OFS)................................................................. 1103

42.4.24 ADC Plus-Side General Calibration Offset Value Register 3 (CLP3_OFS)................................................. 1104

42.4.25 ADC Plus-Side General Calibration Offset Value Register 2 (CLP2_OFS)................................................. 1105

42.4.26 ADC Plus-Side General Calibration Offset Value Register 1 (CLP1_OFS)................................................. 1106

42.4.27 ADC Plus-Side General Calibration Offset Value Register 0 (CLP0_OFS)................................................. 1107

42.4.28 ADC Plus-Side General Calibration Offset Value Register X (CLPX_OFS)............................................... 1108

42.4.29 ADC Plus-Side General Calibration Offset Value Register 9 (CLP9_OFS)................................................. 1109

42.4.30 ADC Status and Control Register 1 (SC1AA - SC1Z).................................................................................. 1110

42.4.31 ADC Data Result Registers (RAA - RZ)....................................................................................................... 1113

42.5 Functional description...................................................................................................................................................1115

42.5.1 Clock select and divide control...................................................................................................................... 1115

42.5.2 Voltage reference selection............................................................................................................................ 1116

42.5.3 Hardware trigger and channel selects............................................................................................................ 1116

42.5.4 Conversion control......................................................................................................................................... 1117

42.5.5 Automatic compare function..........................................................................................................................1121

42.5.6 Calibration function....................................................................................................................................... 1122

42.5.7 User-defined offset function.......................................................................................................................... 1123

42.5.8 MCU Normal Stop mode operation............................................................................................................... 1124

Chapter 43
Comparator (CMP)
43.1 Chip-specific CMP information....................................................................................................................................1125

43.1.1 Instantiation information................................................................................................................................1125

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43.1.2 CMP input connections.................................................................................................................................. 1125

43.1.3 CMP external references................................................................................................................................ 1127

43.1.4 External window/sample input.......................................................................................................................1127

43.1.5 CMP trigger mode..........................................................................................................................................1127

43.1.6 Programming recommendation......................................................................................................................1128

43.1.7 S32K11X to S32K14X difference ................................................................................................................ 1128

43.2 Introduction...................................................................................................................................................................1129

43.3 Features......................................................................................................................................................................... 1129

43.3.1 CMP features..................................................................................................................................................1129

43.3.2 8-bit DAC key features.................................................................................................................................. 1130

43.3.3 ANMUX key features.................................................................................................................................... 1130

43.4 CMP, DAC, and ANMUX diagram..............................................................................................................................1131

43.5 CMP block diagram...................................................................................................................................................... 1132

43.6 CMP pin descriptions....................................................................................................................................................1134

43.6.1 External pins.................................................................................................................................................. 1134

43.7 CMP functional modes................................................................................................................................................. 1135

43.7.1 Disabled mode (# 1)....................................................................................................................................... 1136

43.7.2 Continuous mode (#s 2A & 2B).................................................................................................................... 1137

43.7.3 Sampled, Non-Filtered mode (#s 3A & 3B).................................................................................................. 1137

43.7.4 Sampled, Filtered mode (#s 4A & 4B).......................................................................................................... 1139

43.7.5 Windowed mode (#s 5A & 5B)..................................................................................................................... 1141

43.7.6 Windowed/Resampled mode (# 6).................................................................................................................1143

43.7.7 Windowed/Filtered mode (#7)....................................................................................................................... 1144

43.8 Memory map/register definitions..................................................................................................................................1145

43.8.1 CMP Control Register 0 (CMP_C0).............................................................................................................. 1145

43.8.2 CMP Control Register 1 (CMP_C1).............................................................................................................. 1149

43.8.3 CMP Control Register 2 (CMP_C2).............................................................................................................. 1152

43.9 CMP functional description.......................................................................................................................................... 1154

43.9.1 Initialization................................................................................................................................................... 1154

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43.9.2 Low-pass filter............................................................................................................................................... 1155

43.10 Interrupts....................................................................................................................................................................... 1157

43.11 DMA support................................................................................................................................................................ 1157

43.12 DAC functional description.......................................................................................................................................... 1158

43.12.1 Digital-to-analog converter block diagram.................................................................................................... 1158

43.12.2 DAC resets..................................................................................................................................................... 1158

43.12.3 DAC clocks.................................................................................................................................................... 1159

43.12.4 DAC interrupts............................................................................................................................................... 1159

43.13 Trigger mode.................................................................................................................................................................1159

Chapter 44
Programmable delay block (PDB)
44.1 Chip-specific PDB information.................................................................................................................................... 1163

44.1.1 Instantiation Information................................................................................................................................1163

44.1.2 PDB trigger interconnections with ADC and TRGMUX.............................................................................. 1164

44.1.3 Back-to-back acknowledgement connections................................................................................................ 1164

44.1.4 Pulse-Out Enable Register Implementation................................................................................................... 1171

44.1.5 S32K11X to S32K14X difference ................................................................................................................ 1171

44.2 Introduction...................................................................................................................................................................1171

44.2.1 Features.......................................................................................................................................................... 1171

44.2.2 Implementation.............................................................................................................................................. 1172

44.2.3 Back-to-back acknowledgment connections..................................................................................................1173

44.2.4 Block diagram................................................................................................................................................ 1173

44.2.5 Modes of operation........................................................................................................................................ 1174

44.3 Memory map and register definition.............................................................................................................................1175

44.3.1 Status and Control register (PDB_SC)...........................................................................................................1177

44.3.2 Modulus register (PDB_MOD)......................................................................................................................1180

44.3.3 Counter register (PDB_CNT)........................................................................................................................ 1181

44.3.4 Interrupt Delay register (PDB_IDLY)........................................................................................................... 1181

44.3.5 Channel n Control register 1 (PDB_CHnC1)................................................................................................ 1182

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44.3.6 Channel n Status register (PDB_CHnS)........................................................................................................ 1183

44.3.7 Channel n Delay 0 register (PDB_CHnDLY0)..............................................................................................1183

44.3.8 Channel n Delay 1 register (PDB_CHnDLY1)..............................................................................................1184

44.3.9 Channel n Delay 2 register (PDB_CHnDLY2)..............................................................................................1185

44.3.10 Channel n Delay 3 register (PDB_CHnDLY3)..............................................................................................1185

44.3.11 Channel n Delay 4 register (PDB_CHnDLY4)..............................................................................................1186

44.3.12 Channel n Delay 5 register (PDB_CHnDLY5)..............................................................................................1187

44.3.13 Channel n Delay 6 register (PDB_CHnDLY6)..............................................................................................1187

44.3.14 Channel n Delay 7 register (PDB_CHnDLY7)..............................................................................................1188

44.3.15 Pulse-Out n Enable register (PDB_POEN)....................................................................................................1188

44.3.16 Pulse-Out n Delay register (PDB_POnDLY)................................................................................................ 1189

44.4 Functional description...................................................................................................................................................1189

44.4.1 PDB pre-trigger and trigger outputs...............................................................................................................1189

44.4.2 PDB trigger input source selection................................................................................................................ 1192

44.4.3 Pulse-Out's..................................................................................................................................................... 1192

44.4.4 Updating the delay registers...........................................................................................................................1193

44.4.5 Interrupts........................................................................................................................................................ 1195

44.4.6 DMA.............................................................................................................................................................. 1195

44.5 Application information................................................................................................................................................1195

44.5.1 Impact of using the prescaler and multiplication factor on timing resolution............................................... 1195

Chapter 45
FlexTimer Module (FTM)
45.1 Chip-specific FTM information....................................................................................................................................1197

45.1.1 Instantiation Information................................................................................................................................1197

45.1.2 FTM Interrupts............................................................................................................................................... 1198

45.1.3 FTM Fault Detection Inputs...........................................................................................................................1198

45.1.4 FTM Hardware Triggers and Synchronization.............................................................................................. 1200

45.1.5 FTM Input Capture Options...........................................................................................................................1202

45.1.6 FTM Hall sensor support............................................................................................................................... 1203

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45.1.7 FTM Modulation Implementation................................................................................................................. 1203

45.1.8 FTM Global Time Base................................................................................................................................. 1204

45.1.9 FTM BDM and debug halt mode................................................................................................................... 1205

45.1.10 S32K11X to S32K14X difference ................................................................................................................ 1205

45.2 Introduction...................................................................................................................................................................1207

45.2.1 Features.......................................................................................................................................................... 1207

45.2.2 Modes of operation........................................................................................................................................ 1208

45.2.3 Block Diagram............................................................................................................................................... 1209

45.3 FTM signal descriptions............................................................................................................................................... 1211

45.4 Memory map and register definition.............................................................................................................................1211

45.4.1 Memory map.................................................................................................................................................. 1211

45.4.2 Register descriptions...................................................................................................................................... 1212

45.4.3 FTM register descriptions.............................................................................................................................. 1212

45.5 Functional Description..................................................................................................................................................1269

45.5.1 Clock source...................................................................................................................................................1269

45.5.2 Prescaler......................................................................................................................................................... 1269

45.5.3 Counter...........................................................................................................................................................1270

45.5.4 Channel Modes.............................................................................................................................................. 1276

45.5.5 Input Capture Mode....................................................................................................................................... 1278

45.5.6 Output Compare mode................................................................................................................................... 1283

45.5.7 Edge-Aligned PWM (EPWM) mode............................................................................................................. 1284

45.5.8 Center-Aligned PWM (CPWM) mode.......................................................................................................... 1286

45.5.9 Combine mode............................................................................................................................................... 1288

45.5.10 Modified Combine PWM Mode.................................................................................................................... 1296

45.5.11 Complementary Mode....................................................................................................................................1299

45.5.12 Registers updated from write buffers.............................................................................................................1301

45.5.13 PWM synchronization....................................................................................................................................1302

45.5.14 Inverting......................................................................................................................................................... 1318

45.5.15 Software Output Control Mode......................................................................................................................1319

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45.5.16 Deadtime insertion......................................................................................................................................... 1321

45.5.17 Output mask................................................................................................................................................... 1325

45.5.18 Fault Control.................................................................................................................................................. 1326

45.5.19 Polarity Control..............................................................................................................................................1330

45.5.20 Initialization................................................................................................................................................... 1331

45.5.21 Features Priority............................................................................................................................................. 1331

45.5.22 External Trigger............................................................................................................................................. 1332

45.5.23 Initialization Trigger...................................................................................................................................... 1333

45.5.24 Capture Test Mode.........................................................................................................................................1335

45.5.25 DMA.............................................................................................................................................................. 1336

45.5.26 Dual Edge Capture Mode...............................................................................................................................1337

45.5.27 Quadrature Decoder Mode.............................................................................................................................1345

45.5.28 Debug mode................................................................................................................................................... 1351

45.5.29 Reload Points................................................................................................................................................. 1352

45.5.30 Global Load....................................................................................................................................................1355

45.5.31 Global time base (GTB)................................................................................................................................. 1356

45.5.32 Channel trigger output................................................................................................................................... 1357

45.5.33 External Control of Channels Output.............................................................................................................1358

45.5.34 Dithering........................................................................................................................................................ 1358

45.6 Reset Overview.............................................................................................................................................................1369

45.7 FTM Interrupts..............................................................................................................................................................1371

45.7.1 Timer Overflow Interrupt...............................................................................................................................1371

45.7.2 Reload Point Interrupt.................................................................................................................................... 1371

45.7.3 Channel (n) Interrupt......................................................................................................................................1371

45.7.4 Fault Interrupt................................................................................................................................................ 1371

45.8 Initialization Procedure.................................................................................................................................................1372

Chapter 46
Low Power Interrupt Timer (LPIT)
46.1 Chip-specific LPIT information....................................................................................................................................1375

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46.1.1 Instantiation Information................................................................................................................................1375

46.1.2 LPIT/DMA Periodic Trigger Assignments ...................................................................................................1375

46.1.3 LPIT input triggers ........................................................................................................................................1376

46.1.4 LPIT/ADC Trigger.........................................................................................................................................1376

46.1.5 S32K11X to S32K14X difference ................................................................................................................ 1377

46.2 Introduction...................................................................................................................................................................1378

46.2.1 Overview........................................................................................................................................................ 1378

46.2.2 Block Diagram............................................................................................................................................... 1379

46.3 Modes of operation....................................................................................................................................................... 1380

46.4 Memory Map and Registers..........................................................................................................................................1381

46.4.1 LPIT register descriptions.............................................................................................................................. 1381

46.5 Functional description...................................................................................................................................................1397

46.5.1 LPIT programming model............................................................................................................................. 1397

46.5.2 Initialization................................................................................................................................................... 1399

46.5.3 Timer Modes.................................................................................................................................................. 1400

46.5.4 Trigger Control for Timers............................................................................................................................ 1400

46.5.5 Channel Chaining...........................................................................................................................................1401

46.5.6 Detailed timing...............................................................................................................................................1402

Chapter 47
Low Power Timer (LPTMR)
47.1 Chip-specific LPTMR information...............................................................................................................................1415

47.1.1 Instantiation Information................................................................................................................................1415

47.1.2 LPTMR pulse counter input options.............................................................................................................. 1415

47.1.3 S32K11X to S32K14X difference ................................................................................................................ 1416

47.2 Introduction...................................................................................................................................................................1416

47.2.1 Features.......................................................................................................................................................... 1416

47.2.2 Modes of operation........................................................................................................................................ 1416

47.3 LPTMR signal descriptions.......................................................................................................................................... 1417

47.3.1 Detailed signal descriptions........................................................................................................................... 1417

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47.4 Memory map and register definition.............................................................................................................................1418

47.4.1 LPTMR register descriptions......................................................................................................................... 1418

47.5 Functional description...................................................................................................................................................1423

47.5.1 LPTMR power and reset................................................................................................................................ 1423

47.5.2 LPTMR clocking............................................................................................................................................1424

47.5.3 LPTMR prescaler/glitch filter........................................................................................................................ 1424

47.5.4 LPTMR counter............................................................................................................................................. 1425

47.5.5 LPTMR compare............................................................................................................................................1426

47.5.6 LPTMR interrupt............................................................................................................................................1426

47.5.7 LPTMR hardware trigger...............................................................................................................................1427

Chapter 48
Real Time Clock (RTC)
48.1 Chip-specific RTC information.................................................................................................................................... 1429

48.1.1 RTC instantiation........................................................................................................................................... 1429

48.1.2 RTC interrupts ...............................................................................................................................................1429

48.1.3 Software recommendation............................................................................................................................. 1429

48.1.4 Multiple trigger ............................................................................................................................................. 1429

48.1.5 S32K11X to S32K14X difference ................................................................................................................ 1430

48.2 Introduction...................................................................................................................................................................1430

48.2.1 Features.......................................................................................................................................................... 1430

48.2.2 Modes of operation........................................................................................................................................ 1430

48.2.3 RTC signal descriptions................................................................................................................................. 1430

48.3 Register definition.........................................................................................................................................................1431

48.3.1 RTC register descriptions...............................................................................................................................1431

48.4 Functional description...................................................................................................................................................1442

48.4.1 Power, clocking, and reset............................................................................................................................. 1442

48.4.2 Time counter.................................................................................................................................................. 1443

48.4.3 Compensation.................................................................................................................................................1443

48.4.4 Time alarm..................................................................................................................................................... 1444

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48.4.5 Update mode.................................................................................................................................................. 1445

48.4.6 Register lock.................................................................................................................................................. 1445

48.4.7 Interrupt..........................................................................................................................................................1445

Chapter 49
Low Power Serial Peripheral Interface (LPSPI)
49.1 Chip-specific LPSPI information..................................................................................................................................1447

49.1.1 Instantiation Information................................................................................................................................1447

49.2 Introduction...................................................................................................................................................................1448

49.2.1 Features.......................................................................................................................................................... 1450

49.2.2 Block Diagram............................................................................................................................................... 1450

49.2.3 Modes of operation........................................................................................................................................ 1451

49.2.4 Signal Descriptions........................................................................................................................................ 1451

49.2.5 Wiring options................................................................................................................................................1452

49.3 Memory Map and Registers..........................................................................................................................................1454

49.3.1 LPSPI register descriptions............................................................................................................................ 1454

49.4 Functional description...................................................................................................................................................1477

49.4.1 Clocking and resets........................................................................................................................................ 1477

49.4.2 Master Mode.................................................................................................................................................. 1478

49.4.3 Slave Mode.................................................................................................................................................... 1484

49.4.4 Interrupts and DMA Requests........................................................................................................................1486

49.4.5 Peripheral Triggers.........................................................................................................................................1487

Chapter 50
Low Power Inter-Integrated Circuit (LPI2C)
50.1 Chip-specific LPI2C information................................................................................................................................. 1489

50.1.1 Instantiation information................................................................................................................................1489

50.2 Introduction...................................................................................................................................................................1490

50.2.1 Features.......................................................................................................................................................... 1491

50.2.2 Block Diagram............................................................................................................................................... 1493

50.2.3 Modes of operation........................................................................................................................................ 1493

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50.2.4 Signal Descriptions........................................................................................................................................ 1493

50.2.5 Wiring options................................................................................................................................................1494

50.3 Memory Map and Registers..........................................................................................................................................1495

50.3.1 LPI2C register descriptions............................................................................................................................1496

50.4 Functional description...................................................................................................................................................1534

50.4.1 Clocking and Resets.......................................................................................................................................1534

50.4.2 Master Mode.................................................................................................................................................. 1535

50.4.3 Slave Mode.................................................................................................................................................... 1541

50.4.4 Interrupts and DMA Requests........................................................................................................................1543

50.4.5 Peripheral Triggers.........................................................................................................................................1545

Chapter 51
Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
51.1 Chip-specific LPUART information.............................................................................................................................1547

51.1.1 Instantiation Information................................................................................................................................1547

51.2 Introduction...................................................................................................................................................................1548

51.2.1 Features.......................................................................................................................................................... 1548

51.2.2 Modes of operation........................................................................................................................................ 1549

51.2.3 Signal Descriptions........................................................................................................................................ 1549

51.2.4 Block diagram................................................................................................................................................ 1549

51.3 Register definition.........................................................................................................................................................1551

51.3.1 LPUART register descriptions.......................................................................................................................1551

51.4 Functional description...................................................................................................................................................1577

51.4.1 Clocking and Resets.......................................................................................................................................1577

51.4.2 Baud rate generation...................................................................................................................................... 1577

51.4.3 Transmitter functional description................................................................................................................. 1578

51.4.4 Receiver functional description..................................................................................................................... 1582

51.4.5 Additional LPUART functions...................................................................................................................... 1588

51.4.6 Infrared interface............................................................................................................................................1590

51.4.7 Interrupts and status flags.............................................................................................................................. 1591

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51.4.8 Peripheral Triggers.........................................................................................................................................1592

Chapter 52
Flexible I/O (FlexIO)
52.1 Chip-specific FlexIO information.................................................................................................................................1595

52.1.1 FlexIO Configuration..................................................................................................................................... 1595

52.2 Introduction...................................................................................................................................................................1595

52.2.1 Overview........................................................................................................................................................ 1595

52.2.2 Features.......................................................................................................................................................... 1596

52.2.3 Block Diagram............................................................................................................................................... 1596

52.2.4 Modes of operation........................................................................................................................................ 1597

52.2.5 FlexIO Signal Descriptions............................................................................................................................ 1597

52.3 Memory Map and Registers..........................................................................................................................................1598

52.3.1 FLEXIO register descriptions........................................................................................................................ 1598

52.4 Functional description...................................................................................................................................................1622

52.4.1 Clocking and Resets.......................................................................................................................................1622

52.4.2 Shifter operation.............................................................................................................................................1623

52.4.3 Timer Operation............................................................................................................................................. 1625

52.4.4 Pin operation.................................................................................................................................................. 1629

52.4.5 Interrupts and DMA Requests........................................................................................................................1630

52.4.6 Peripheral Triggers.........................................................................................................................................1630

52.5 Application Information................................................................................................................................................1631

52.5.1 UART Transmit............................................................................................................................................. 1631

52.5.2 UART Receive............................................................................................................................................... 1632

52.5.3 SPI Master......................................................................................................................................................1634

52.5.4 SPI Slave........................................................................................................................................................ 1636

52.5.5 I2C Master......................................................................................................................................................1637

52.5.6 I2S Master...................................................................................................................................................... 1639

52.5.7 I2S Slave........................................................................................................................................................ 1641

Chapter 53

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FlexCAN
53.1 Chip-specific FlexCAN information.............................................................................................................................1643

53.1.1 Instantiation information................................................................................................................................1643

53.1.2 Reset value of MDIS bit.................................................................................................................................1644

53.1.3 FlexCAN external time tick .......................................................................................................................... 1644

53.1.4 FlexCAN Interrupts........................................................................................................................................1644

53.1.5 FlexCAN Operation in Low Power Modes....................................................................................................1645

53.1.6 FlexCAN oscillator clock...............................................................................................................................1645

53.1.7 Supported baud rate ...................................................................................................................................... 1645

53.1.8 Requirements for entering FlexCAN modes: Freeze, Disable, Stop............................................................. 1645

53.2 Introduction...................................................................................................................................................................1647

53.2.1 Overview........................................................................................................................................................ 1648

53.2.2 FlexCAN module features............................................................................................................................. 1649

53.2.3 Modes of operation........................................................................................................................................ 1650

53.3 FlexCAN signal descriptions........................................................................................................................................ 1652

53.3.1 CAN Rx .........................................................................................................................................................1652

53.3.2 CAN Tx .........................................................................................................................................................1653

53.4 Memory map/register definition................................................................................................................................... 1653

53.4.1 FlexCAN memory mapping...........................................................................................................................1653

53.4.2 CAN register descriptions.............................................................................................................................. 1654

53.4.3 Message buffer structure................................................................................................................................ 1725

53.4.4 FlexCAN memory partition for CAN FD...................................................................................................... 1732

53.4.5 FlexCAN message buffer memory map.........................................................................................................1733

53.4.6 Rx FIFO structure.......................................................................................................................................... 1735

53.5 Functional description...................................................................................................................................................1738

53.5.1 Transmit process............................................................................................................................................ 1738

53.5.2 Arbitration process......................................................................................................................................... 1740

53.5.3 Receive process..............................................................................................................................................1743

53.5.4 Matching process........................................................................................................................................... 1745

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53.5.5 Receive process under Pretended Networking mode.....................................................................................1750

53.5.6 Move process................................................................................................................................................. 1754

53.5.7 Data coherence............................................................................................................................................... 1756

53.5.8 Rx FIFO......................................................................................................................................................... 1759

53.5.9 CAN protocol related features....................................................................................................................... 1762

53.5.10 Clock domains and restrictions...................................................................................................................... 1782

53.5.11 Modes of operation details............................................................................................................................. 1786

53.5.12 Interrupts........................................................................................................................................................ 1789

53.5.13 Bus interface.................................................................................................................................................. 1791

53.6 Initialization/application information........................................................................................................................... 1792

53.6.1 FlexCAN initialization sequence................................................................................................................... 1792

Chapter 54
Synchronous Audio Interface (SAI)
54.1 Chip-specific SAI information .....................................................................................................................................1795

54.1.1 SAI configuration...........................................................................................................................................1795

54.1.2 Chip-specific register information................................................................................................................. 1796

54.2 Introduction...................................................................................................................................................................1797

54.2.1 Features.......................................................................................................................................................... 1797

54.2.2 Block diagram................................................................................................................................................ 1797

54.2.3 Modes of operation........................................................................................................................................ 1798

54.3 External signals.............................................................................................................................................................1799

54.4 Memory map and register definition.............................................................................................................................1799

54.4.1 I2S register descriptions.................................................................................................................................1799

54.5 Functional description...................................................................................................................................................1832

54.5.1 SAI clocking.................................................................................................................................................. 1832

54.5.2 SAI resets....................................................................................................................................................... 1834

54.5.3 Synchronous modes....................................................................................................................................... 1835

54.5.4 Frame sync configuration...............................................................................................................................1836

54.5.5 Data FIFO...................................................................................................................................................... 1836

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54.5.6 Word mask register........................................................................................................................................ 1840

54.5.7 Interrupts and DMA requests......................................................................................................................... 1841

Chapter 55
Ethernet MAC (ENET)
55.1 Chip-specific ENET information..................................................................................................................................1845

55.1.1 Software guideline during ENET operation...................................................................................................1845

55.2 Introduction...................................................................................................................................................................1845

55.3 Overview.......................................................................................................................................................................1846

55.3.1 Features.......................................................................................................................................................... 1846

55.3.2 Block diagram................................................................................................................................................ 1849

55.4 External signal description............................................................................................................................................1849

55.5 Memory map/register definition................................................................................................................................... 1851

55.5.1 Interrupt Event Register (ENET_EIR)...........................................................................................................1856

55.5.2 Interrupt Mask Register (ENET_EIMR)........................................................................................................1859

55.5.3 Receive Descriptor Active Register (ENET_RDAR).................................................................................... 1862

55.5.4 Transmit Descriptor Active Register (ENET_TDAR)...................................................................................1863

55.5.5 Ethernet Control Register (ENET_ECR)....................................................................................................... 1864

55.5.6 MII Management Frame Register (ENET_MMFR)...................................................................................... 1866

55.5.7 MII Speed Control Register (ENET_MSCR)................................................................................................ 1866

55.5.8 MIB Control Register (ENET_MIBC).......................................................................................................... 1869

55.5.9 Receive Control Register (ENET_RCR)....................................................................................................... 1870

55.5.10 Transmit Control Register (ENET_TCR)...................................................................................................... 1873

55.5.11 Physical Address Lower Register (ENET_PALR)........................................................................................ 1875

55.5.12 Physical Address Upper Register (ENET_PAUR)........................................................................................ 1875

55.5.13 Opcode/Pause Duration Register (ENET_OPD)........................................................................................... 1876

55.5.14 Descriptor Individual Upper Address Register (ENET_IAUR).................................................................... 1876

55.5.15 Descriptor Individual Lower Address Register (ENET_IALR).................................................................... 1877

55.5.16 Descriptor Group Upper Address Register (ENET_GAUR)......................................................................... 1877

55.5.17 Descriptor Group Lower Address Register (ENET_GALR)......................................................................... 1878

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55.5.18 Transmit FIFO Watermark Register (ENET_TFWR)................................................................................... 1878

55.5.19 Receive Descriptor Ring Start Register (ENET_RDSR)............................................................................... 1879

55.5.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR).................................................................. 1880

55.5.21 Maximum Receive Buffer Size Register (ENET_MRBR)............................................................................ 1881

55.5.22 Receive FIFO Section Full Threshold (ENET_RSFL).................................................................................. 1882

55.5.23 Receive FIFO Section Empty Threshold (ENET_RSEM)............................................................................ 1882

55.5.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)............................................................................ 1883

55.5.25 Receive FIFO Almost Full Threshold (ENET_RAFL)..................................................................................1883

55.5.26 Transmit FIFO Section Empty Threshold (ENET_TSEM)........................................................................... 1884

55.5.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM)...........................................................................1884

55.5.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)................................................................................ 1885

55.5.29 Transmit Inter-Packet Gap (ENET_TIPG).................................................................................................... 1885

55.5.30 Frame Truncation Length (ENET_FTRL)..................................................................................................... 1886

55.5.31 Transmit Accelerator Function Configuration (ENET_TACC).................................................................... 1886

55.5.32 Receive Accelerator Function Configuration (ENET_RACC)......................................................................1887

55.5.33 Reserved Statistic Register (ENET_RMON_T_DROP)................................................................................1888

55.5.34 Tx Packet Count Statistic Register (ENET_RMON_T_PACKETS)............................................................ 1889

55.5.35 Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)........................................................1889

55.5.36 Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)........................................................1890

55.5.37 Tx Packets with CRC/Align Error Statistic Register (ENET_RMON_T_CRC_ALIGN)............................ 1890

55.5.38 Tx Packets Less Than Bytes and Good CRC Statistic Register (ENET_RMON_T_UNDERSIZE)............ 1890

55.5.39 Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (ENET_RMON_T_OVERSIZE)..........1891

55.5.40 Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_T_FRAG)..................... 1891

55.5.41 Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (ENET_RMON_T_JAB)........ 1892

55.5.42 Tx Collision Count Statistic Register (ENET_RMON_T_COL).................................................................. 1892

55.5.43 Tx 64-Byte Packets Statistic Register (ENET_RMON_T_P64)................................................................... 1892

55.5.44 Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127)............................................ 1893

55.5.45 Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)........................................ 1893

55.5.46 Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)........................................ 1894

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55.5.47 Tx 512- to 1023-byte Packets Statistic Register (ENET_RMON_T_P512TO1023).................................... 1894

55.5.48 Tx 1024- to 2047-byte Packets Statistic Register (ENET_RMON_T_P1024TO2047)................................ 1895

55.5.49 Tx Packets Greater Than 2048 Bytes Statistic Register (ENET_RMON_T_P_GTE2048).......................... 1895

55.5.50 Tx Octets Statistic Register (ENET_RMON_T_OCTETS).......................................................................... 1895

55.5.51 Reserved Statistic Register (ENET_IEEE_T_DROP)................................................................................... 1896

55.5.52 Frames Transmitted OK Statistic Register (ENET_IEEE_T_FRAME_OK)................................................ 1896

55.5.53 Frames Transmitted with Single Collision Statistic Register (ENET_IEEE_T_1COL)............................... 1897

55.5.54 Frames Transmitted with Multiple Collisions Statistic Register (ENET_IEEE_T_MCOL).........................1897

55.5.55 Frames Transmitted after Deferral Delay Statistic Register (ENET_IEEE_T_DEF)....................................1897

55.5.56 Frames Transmitted with Late Collision Statistic Register (ENET_IEEE_T_LCOL).................................. 1898

55.5.57 Frames Transmitted with Excessive Collisions Statistic Register (ENET_IEEE_T_EXCOL).....................1898

55.5.58 Frames Transmitted with Tx FIFO Underrun Statistic Register (ENET_IEEE_T_MACERR).................... 1899

55.5.59 Frames Transmitted with Carrier Sense Error Statistic Register (ENET_IEEE_T_CSERR)....................... 1899

55.5.60 Reserved Statistic Register (ENET_IEEE_T_SQE)...................................................................................... 1899

55.5.61 Flow Control Pause Frames Transmitted Statistic Register (ENET_IEEE_T_FDXFC)...............................1900

55.5.62 Octet Count for Frames Transmitted w/o Error Statistic Register (ENET_IEEE_T_OCTETS_OK)........... 1900

55.5.63 Rx Packet Count Statistic Register (ENET_RMON_R_PACKETS)............................................................ 1901

55.5.64 Rx Broadcast Packets Statistic Register (ENET_RMON_R_BC_PKT)....................................................... 1901

55.5.65 Rx Multicast Packets Statistic Register (ENET_RMON_R_MC_PKT)....................................................... 1901

55.5.66 Rx Packets with CRC/Align Error Statistic Register (ENET_RMON_R_CRC_ALIGN)............................1902

55.5.67 Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
(ENET_RMON_R_UNDERSIZE)................................................................................................................ 1902

55.5.68 Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (ENET_RMON_R_OVERSIZE)...1903

55.5.69 Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_R_FRAG).................... 1903

55.5.70 Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (ENET_RMON_R_JAB)....... 1903

55.5.71 Reserved Statistic Register (ENET_RMON_R_RESVD_0)......................................................................... 1904

55.5.72 Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64)................................................................... 1904

55.5.73 Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127)........................................... 1905

55.5.74 Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255)....................................... 1905

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Section number Title Page

55.5.75 Rx 256- to 511-Byte Packets Statistic Register (ENET_RMON_R_P256TO511)....................................... 1905

55.5.76 Rx 512- to 1023-Byte Packets Statistic Register (ENET_RMON_R_P512TO1023)................................... 1906

55.5.77 Rx 1024- to 2047-Byte Packets Statistic Register (ENET_RMON_R_P1024TO2047)............................... 1906

55.5.78 Rx Packets Greater than 2048 Bytes Statistic Register (ENET_RMON_R_P_GTE2048)........................... 1907

55.5.79 Rx Octets Statistic Register (ENET_RMON_R_OCTETS).......................................................................... 1907

55.5.80 Frames not Counted Correctly Statistic Register (ENET_IEEE_R_DROP)................................................. 1907

55.5.81 Frames Received OK Statistic Register (ENET_IEEE_R_FRAME_OK).................................................... 1908

55.5.82 Frames Received with CRC Error Statistic Register (ENET_IEEE_R_CRC).............................................. 1908

55.5.83 Frames Received with Alignment Error Statistic Register (ENET_IEEE_R_ALIGN)................................ 1909

55.5.84 Receive FIFO Overflow Count Statistic Register (ENET_IEEE_R_MACERR)..........................................1909

55.5.85 Flow Control Pause Frames Received Statistic Register (ENET_IEEE_R_FDXFC)................................... 1909

55.5.86 Octet Count for Frames Received without Error Statistic Register (ENET_IEEE_R_OCTETS_OK)......... 1910

55.5.87 Adjustable Timer Control Register (ENET_ATCR)..................................................................................... 1910

55.5.88 Timer Value Register (ENET_ATVR).......................................................................................................... 1912

55.5.89 Timer Offset Register (ENET_ATOFF)........................................................................................................ 1913

55.5.90 Timer Period Register (ENET_ATPER)........................................................................................................1913

55.5.91 Timer Correction Register (ENET_ATCOR)................................................................................................ 1914

55.5.92 Time-Stamping Clock Period Register (ENET_ATINC).............................................................................. 1914

55.5.93 Timestamp of Last Transmitted Frame (ENET_ATSTMP).......................................................................... 1915

55.5.94 Timer Global Status Register (ENET_TGSR)...............................................................................................1915

55.5.95 Timer Control Status Register (ENET_TCSRn)............................................................................................1916

55.5.96 Timer Compare Capture Register (ENET_TCCRn)...................................................................................... 1917

55.6 Functional description...................................................................................................................................................1918

55.6.1 Ethernet MAC frame formats........................................................................................................................ 1918

55.6.2 IP and higher layers frame format..................................................................................................................1921

55.6.3 IEEE 1588 message formats.......................................................................................................................... 1925

55.6.4 MAC receive.................................................................................................................................................. 1929

55.6.5 MAC transmit................................................................................................................................................ 1935

55.6.6 Full-duplex flow control operation................................................................................................................ 1939

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55.6.7 Magic packet detection.................................................................................................................................. 1941

55.6.8 IP accelerator functions..................................................................................................................................1942

55.6.9 Resets and stop controls................................................................................................................................. 1946

55.6.10 IEEE 1588 functions...................................................................................................................................... 1949

55.6.11 FIFO thresholds..............................................................................................................................................1953

55.6.12 Loopback options........................................................................................................................................... 1956

55.6.13 Legacy buffer descriptors...............................................................................................................................1957

55.6.14 Enhanced buffer descriptors...........................................................................................................................1958

55.6.15 Client FIFO application interface.................................................................................................................. 1964

55.6.16 FIFO protection..............................................................................................................................................1967

55.6.17 Reference clock..............................................................................................................................................1969

55.6.18 PHY management interface........................................................................................................................... 1970

55.6.19 Ethernet interfaces..........................................................................................................................................1973

Chapter 56
Debug
56.1 Introduction...................................................................................................................................................................1979

56.2 CM4 and CM0+ ROM table......................................................................................................................................... 1982

56.3 Debug port.................................................................................................................................................................... 1983

56.3.1 JTAG-to-SWD change sequence................................................................................................................... 1984

56.4 Debug port pin descriptions.......................................................................................................................................... 1985

56.5 System TAP connection................................................................................................................................................1985

56.5.1 IR codes..........................................................................................................................................................1985

56.6 MDM-AP status and control registers.......................................................................................................................... 1986

56.6.1 MDM-AP Control Register............................................................................................................................1987

56.6.2 MDM-AP Status Register.............................................................................................................................. 1988

56.7 Debug resets..................................................................................................................................................................1989

56.8 AHB-AP........................................................................................................................................................................1990

56.9 ITM............................................................................................................................................................................... 1990

56.10 Core trace connectivity................................................................................................................................................. 1991

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Section number Title Page

56.11 TPIU..............................................................................................................................................................................1991

56.12 DWT............................................................................................................................................................................. 1992

56.13 MTB .............................................................................................................................................................................1992

56.14 Debug in low-power modes.......................................................................................................................................... 1993

56.14.1 Debug module state in low-power modes......................................................................................................1993

56.15 Debug and security....................................................................................................................................................... 1994

Chapter 57
JTAG Controller (JTAGC)
57.1 Chip-specific JTAGC information................................................................................................................................1995

57.2 Introduction...................................................................................................................................................................1995

57.2.1 Block diagram................................................................................................................................................ 1995

57.2.2 Features.......................................................................................................................................................... 1996

57.2.3 Modes of operation........................................................................................................................................ 1996

57.3 External signal description............................................................................................................................................1998

57.3.1 Test clock input (TCK).................................................................................................................................. 1998

57.3.2 Test data input (TDI)......................................................................................................................................1998

57.3.3 Test data output (TDO).................................................................................................................................. 1998

57.3.4 Test mode select (TMS)................................................................................................................................. 1999

57.4 Register description...................................................................................................................................................... 1999

57.4.1 Instruction register......................................................................................................................................... 1999

57.4.2 Bypass register............................................................................................................................................... 1999

57.4.3 Device identification register......................................................................................................................... 2000

57.4.4 Boundary scan register...................................................................................................................................2000

57.5 Functional description...................................................................................................................................................2001

57.5.1 JTAGC reset configuration............................................................................................................................ 2001

57.5.2 IEEE 1149.1-2001 (JTAG) TAP....................................................................................................................2001

57.5.3 TAP controller state machine.........................................................................................................................2001

57.5.4 JTAGC block instructions..............................................................................................................................2004

57.5.5 Boundary scan................................................................................................................................................2007

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Section number Title Page

57.6 Initialization/application information........................................................................................................................... 2007

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 S32K1xx Series Reference Manual, Rev. 11, 06/2019
50 NXP Semiconductors
Chapter 1
About This Manual

1.1 Audience
This reference manual is intended for system software and hardware developers and
applications programmers who want to develop products with this device. It assumes that
the reader understands operating systems, microprocessor system design, and basic
principles of software and hardware. The manual describes the functionality of the
superset device of the S32K1xx series. For the available features, register implementation
of a specific S32K1xx derivative (derivative device), please refer to the respective Chip-
specific module information.

1.2 Organization
This manual has two main sets of chapters.
1. Chapters in the first set contain information that applies to all components on the
chip.
2. Chapters in the second set are organized into functional groupings that detail
particular areas of functionality.
• Examples of these groupings are clocking, timers, and communication interfaces.
• Each grouping includes chapters that provide a technical description of
individual modules.

1.3 Module descriptions

Each module chapter has two main parts:

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Module descriptions

• The first section, Chip-specific [module name] information, provides details such as
the number of module instances on the chip and connections between the module and
other modules. Read this section first because its content is crucial to understanding
the information in other sections of the chapter.
• The subsequent sections provide general information about the module, including its
signals, registers, and functional description.

L E
Chapter 49
Enhanced Serial Communication Interface (eSCI)

P
49.1 Chip-specific eSCI information
This chip has six instances of the eSCI module. Some feature details vary between the
instances.

M
The following table summarizes the feature differences. The table does not list feature
details that the instances share.
Table 49-1. eSCI instance feature differences
Chip-specific information
Instance DMA support that should be read first

A
eSCI_A and eSCI_B Yes
eSCI_C, eSCI_D, eSCI_E, and eSCI_F No: descriptions of eSCI DMA functionality do not apply to
these instances

X
NOTE
For eSCI_D, the single wire feature does not apply for TX/RX
via PCSA3 because this pad works only as an output.

E
49.2 Introduction
The eSCI block is an enhanced SCI block with a LIN master interface layer and DMA
support. The LIN master layer complies with the specifications LIN 1.3, LIN 2.0, LIN
2.1, and SAE J2602/1.
Beginning of general
49.2.1 Bibliography module information
• LIN Specification Package Revision 1.3; December 12, 2002
• LIN Specification Package Revision 2.0; September 23, 2003

Sample Reference Manual

Figure 1-1. Example: chapter chip-specific information and general module information

1.3.1 Example: chip-specific information that clarifies content in

the same chapter
The example below shows chip-specific information that clarifies general module
information presented later in the chapter. In this case, the chip-specific register reset
values supercede the reset values that appear in the register diagram.

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 Chapter 1 About This Manual

Chapter 34 Software Watchdog Timer (SWT)

accesses by masters without permission. If the RIA bit in the SWT_CR is set then the
SWT generates a system reset on an invalid access otherwise a bus error is generated. If

E
either the HLK or SLK bits in the SWT_CR are set, then the SWT_CR, SWT_TO,
SWT_WN, and SWT_SK registers are read-only.
The SWT memory map is shown in the following table.

L
SWT memory map
Chapter 34 Address Width Section/
Software Watchdog Timer (SWT) offset (hex)
Register name
(in bits)
Access Reset value
page
0 SWT Control Register (SWT_CR) 32 R/W See section 34.4.1/1331

P
4 SWT Interrupt Register (SWT_IR) 32 R/W 0000_0000h 34.4.2/1334

34.1 Chip-specific SWT information 8 SWT Time-out Register (SWT_TO) 32 R/W See section 34.4.3/1334
C SWT Window Register (SWT_WN) 32 R/W 0000_0000h 34.4.4/1335
This chip has two instances of the SWT module: SWT_A and SWT_B. 10 SWT Service Register (SWT_SR) 32 W 0000_0000h 34.4.5/1335
14 SWT Counter Output Register (SWT_CO) 32 R 0000_0000h 34.4.6/1336
18 SWT Service Key Register (SWT_SK) 32 R/W 0000_0000h 34.4.7/1336

M
34.1.1 SWT register reset values
The following table identifies chip-specific reset values of SWT registers.
34.4.1 SWT Control Register (SWT_CR)
Table 34-1. Chip-specific SWT register reset values
NOTE

A
Register SWT_A SWT_B
The reset value for the SWT_CR is implementation specific.
CR FF00_010Bh FF00_010Ah
See the configuration information.
TO 0005_FCD0h 0005_FCD0h
The SWT_CR contains fields for configuring and controlling the SWT.
This register is read-only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are set.

X
Address: 0h base + 0h offset = 0h
34.2 Introduction Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

This section provides an overview, list of features, and modes of operation for the SWT. R 0

E MAP0

MAP1

MAP2

MAP3

MAP4

MAP5

MAP6

MAP7
W

34.2.1 Overview Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
The Software Watchdog Timer (SWT) is a peripheral module that can prevent system
lockup in situations such as software getting trapped in a loop or if a bus transaction fails R 0
SMD RIA WND ITR HLK SLK CSL STP FRZ WEN
to terminate. When enabled, the SWT requires periodic execution of a watchdog W
servicing operation. The servicing operation resets the timer to a specified time-out
period. If this servicing action does not occur before the timer expires the SWT generates Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

an interrupt or hardware reset. The SWT can be configured to generate a reset or interrupt * Notes:
• The reset value for the SWT_CR is implementation specific. See the configuration information.
on an initial time-out. A reset is always generated on a second consecutive time-out.

Sample Reference Manual

Sample Reference Manual

Figure 1-2. Example: chip-specific information that clarifies content in the same chapter

1.3.2 Example: chip-specific information that refers to a different

chapter
The chip-specific information below refers to another chapter's chip-specific information.
In this case, read both sets of chip-specific information before reading further in the
chapter.

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Register descriptions

LE
Chapter 10 Chapter 9
Crossbar Integrity Checker (XBIC) Crossbar Switch (XBAR)

P
10.1 Chip-specific XBIC information 9.1 Chip-specific XBAR information
This chip has one instance of the XBIC module. This chip has one instance of the XBAR module.

M
10.1.1 XBIC master and slave assignments 9.1.1 XBAR master and slave assignments
The XBIC identifies each XBAR master and slave in terms of the master or slave's The following table lists the XBAR physical port numbers and logical IDs for all master
physical port number. See the "Physical master port" assignments in Table 9-1 and the ports on this SoC.
"Slave port" assignments in Table 9-2. • Each port number matches the default priority assigned to the corresponding physical

A
master port. This default priority equals the reset value of the priority field for each
master port in the PRSn registers.
• A priority value of 0 is the highest priority. There is no "disabled" value for the
10.1.2 Unimplemented MCR and ESR fields
priority.

X
On this chip, the MCR[SE5] and ESR[DPSE5] fields are not implemented. In XBIC • A Nexus_3 module and core data bus share the same physical master port for each
Module Control Register (XBIC_MCR) and XBIC Error Status Register (XBIC_ESR), core.
these fields are reserved.
The logical master ID corresponds to the logical address provided by the master module
and is unique for each module. The logical master IDs are used by the bus masters

E
connected to the XBAR. The Nexus master is identified by setting the MSB in the 4-bit
10.2 Overview field that supplies the master ID number.
The Crossbar Integrity Checker (XBIC) verifies the integrity of the crossbar transfers. Table 9-1. XBAR master ports and logical master IDs
For forward signals (master to slave), it is done by verifying the integrity of the attribute Module Physical master port Logical master ID Comment
information using an 8-bit Error Detection Code (EDC). The EDC detects any single- or Core0 instruction 0 0
double-bit errors in the attribute information and signals the Fault Collection and Control Core0 data 1 0
Unit (FCCU) when an error is detected. For feedback signals (slave to master), it is done Nexus_3_0 8 Nexus_3_0 arbitrates with Core0 data for XBAR port 1
by comparing the consistency of the signals during the AHB dataphase.There are three Core1 instruction 2 1
signals from slave to master, hready, hresp0, and hresp2. If any of the master signals is Core1 data 3 1
different from the slave signals during dataphase, the error will be reported in the Error Nexus_3_1 9 Nexus_3_1 arbitrates with Core1 data for XBAR port 3

Status Register. Table continues on the next page...

Sample Reference Manual Sample Reference Manual

Figure 1-3. Example: chip-specific information that refers to a different chapter

1.4 Register descriptions

Module chapters present register information in:
• Memory maps containing:
• An offset from the module's base address
• The name and acronym/abbreviation of each register
• The width of each register (in bits)
• Each register's reset value
• The page number on which each register is described
• Register figures
• Field-description tables
• Associated text
The register figures show the field structure using the conventions in the following figure.

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 Chapter 1 About This Manual

R R Mnemonic R R 0 R 1
Mnemonic
W W W Mnemonic W Mnemonic W Mnemonic
Read/write Read-only Write-only Write-only Write-only
reads zero reads one

R R Mnemonic R Mnemonic R Mnemonic R Mnemonic

W Mnemonic W 0 W 1 W W w1c
Write-only Read-only Read-only Read-only Write one to clear
reads undefined writes zero writes one writes undefined

R R R R 1 R 0
Reserved
W W 1 W 0 W W
Reserved, Write-only one Write-only zero Read-only one Read-only zero
unimplemented

Figure 1-4. Register figure conventions

1.5 Conventions

1.5.1 Notes, Cautions, and Warnings

Note, Caution, and Warning notices appear throughout this manual. Each notice type
alerts readers to a specific kind of information.
NOTE
Notes convey information that may be tangential to a topic or
that may not apply to all readers.
CAUTION
Caution notices call out information that readers should know
before taking further action. Cautions frequently point to
trouble spots that may damage the chip or board.
WARNING
Warning notices inform readers about actions that could result
in unwanted consequences, especially those that may cause
bodily injury.

1.5.2 Numbering systems

The following suffixes identify different numbering systems:

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Conventions

This suffix Identifies a

b Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases,
binary numbers are shown with the prefix 0b.
d Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion
exists. In general, decimal numbers are shown without a suffix.
h Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In
some cases, hexadecimal numbers are shown with the prefix 0x.

1.5.3 Typographic notation

The following typographic notation is used throughout this document:
Example Description
placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as
placeholders for single letters and numbers.
code Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction
mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type
is also used for example code. Instruction mnemonics and directives in text and tables are
shown in all caps; for example, BSR.
SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the
Scaling Mode (SCM) field in the Status Register (SR).
REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:
• A subset of a register's named field
For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus
For example, XAD[7:0] refers to signals 7–0 of the XAD bus.

1.5.4 Special terms

The following terms have special meanings:
Term Meaning
asserted Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).

In some cases, deasserted signals are described as negated.

Table continues on the next page...

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 Chapter 1 About This Manual

Term Meaning
reserved Refers to a memory space, register, field, or programming setting. Device operation is not
guaranteed when reserved locations are written to any value.
• Do not modify the default value of a reserved programming setting, such as the reset value of
a reserved register field.
• Consider undefined locations in memory to be reserved.
w1c Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared."

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Conventions

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58 NXP Semiconductors
Chapter 2
Introduction

2.1 Overview
The S32K1xx product series further extends the highly scalable portfolio of Arm®
Cortex®-M0+/M4F MCUs in the automotive industry. It builds on the legacy of the KEA
series, while introducing higher memory options alongside a richer peripheral set
extending capability into a variety of automotive applications. With a 2.70–5.5 V supply
and focus on automotive environment robustness, the S32K product series devices are
well suited to a wide range of applications in electrically harsh environments, and are
optimized for cost-sensitive applications offering low pin-count options. The S32K
product series offers a broad range of memory, peripherals, and package options. It shares
common peripherals and pin counts, allowing developers to migrate easily within an
MCU family or among the MCU families to take advantage of more memory or feature
integration. This scalability allows developers to use the S32K product series as the
standard for their end product platforms, maximizing hardware and software reuse and
reducing time to market.

2.2 S32K1xx Series introduction

2.2.1 S32K14x
S32K14x series of devices are 32-bit general purpose automotive microcontrollers based
on the Arm Cortex-M4F core. They offer superior performance, large memories and the
most scalable peripherals in this class. This product series provides up to 112 MHz CPU
performance with DSP and FPU support, with up to 2 MB Flash and up to 256 KB
SRAM. Overview of device features:
• 32-bit Arm Cortex-M4F core with FPU, up to 112 MHz (HSRUN) and 80 MHz
(Normal RUN)

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S32K1xx Series introduction

• Up to 2 MB code flash memory and 64 KB FlexMem (supports up to 4 KB emulated

EEPROM 1 with 4 KB FlexRAM)
• Up to 256 KB SRAM supporting both CPU private access and crossbar access to
provide parallel access of instruction and data
• Modified Harvard connections with Local Memory controller (LMEM) to support
tightly coupled RAM and 4 KB Code Cache2
• Integrated clocking architecture with on-chip fast IRC 48-60 MHz, slow IRC 8
MHz / 2 MHz, 128 KHz LPO and a PLL unit
• Analog modules providing precision mixed-signal capabilities, including 12-bit up to
two 1 Msps SAR ADC, high-speed comparator
• Power Management Controller (PMC) with internal regulators capable of supporting
multiple power modes including:
• HSRUN 2, , 3
• RUN
• STOP
• VLPR
• VLPS
• I/O supporting 2.7 V to 5.5 V supply
• Wide operating voltage ranges (2.7–5.5 V) with fully functional flash memory
program/erase/read operations
• 48 LQFP, 64 LQFP, 100 LQFP, 144 LQFP, 176 LQFP and 100 MAPBGA packages
with up to 156 GPIO pins
• Ambient operating temperature ranges from –40 °C to 125 °C 3
The S32K14x MCU portfolio is supported by a highly comprehensive set of development
tools and software. The enablement package includes: NXP Arduino compatible
evaluation boards, S32K Software Development Kit (SDK) including graphical
configurability and S32 Design Studio software, as well as broad support from IAR
Systems, Arm, Software, Green Hills, and other partners.

1. CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case
is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 Mhz) to execute CSEc
(Security) or EEPROM writes/erase.
2. This refers to region addressable by Arm CM4 Code bus and is used to cache code as well as data in this region.
See S32K1xx_memory_map.xlsx for more details on cacheability of different regions.
3. HSRUN mode (112 MHz) operation is not valid at 125 °C.

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 Chapter 2 Introduction

2.2.2 S32K11x
S32K11x series of devices are 32-bit general purpose automotive microcontrollers based
on the Arm Cortex-M0+ core. They offer superior performance, large memories and the
most scalable peripherals in this class. This product series provides 48 MHz CPU
performance, with up to 256 KB Flash and up to 25 KB SRAM. Overview of device
features:
• 32-bit Arm Cortex-M0+ core with 48 MHz CPU
• Up to 256 KB code flash memory and 32 KB FlexMem (supports up to 2 KB
emulated EEPROM with 2 KB FlexRAM)
• Up to 25 KB SRAM
• Integrated clocking architecture with on-chip fast IRC 48 MHz, slow IRC 8MHz, and
128 KHz LPO
• Analog modules providing precision mixed-signal capabilities, including 12-bit 1
Msps SAR ADC, high-speed comparator
• Power Management Controller (PMC) with internal regulators capable of supporting
multiple power modes including:
• RUN
• STOP
• VLPR
• VLPS
• I/O supporting 2.7 V to 5.5 V supply
• Wide operating voltage ranges (2.7–5.5 V) with fully functional flash memory
program/erase/read operations
• 32-pin QFN, 48-pinLQFP, 64-pinLQFP with up to 58 GPIO pins
• Ambient operating temperature ranges from –40 °C to 125 °C
The S32K11x MCU portfolio is supported by a highly comprehensive set of development
tools and software. The enablement package includes: NXP Arduino compatible
evaluation boards, S32K Software Development Kit (SDK) including graphical
configurability and S32 Design Studio software, as well as broad support from IAR
Systems, Cosmic Software, Green Hills, and other partners.

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Feature summary

2.3 Feature summary

The following table lists the features integrated on S32K1xx product series.
Table 2-1. Device feature summary
Feature S32K14x product series S32K11x product series
Hardware Characteristics
Package 48-pin LQFP, 7*7 mm, 0.5 mm pitch 32-pin QFN , 5*5 mm, 0.5 mm pitch
64-pin LQFP, 10*10 mm, 0.5 mm pitch 48-pin LQFP, 7*7 mm, 0.5 mm pitch
100-pin LQFP, 14*14 mm, 0.5 mm pitch 64-pin LQFP, 10*10 mm, 0.5 mm pitch
144-pin LQFP, 20*20 mm, 0.5 mm pitch
176-pin LQFP, 24*24 mm, 0.5 mm pitch
100-pin MAPBGA, 11*11 mm, 1 mm ball
pitch
Voltage range 2.7 V to 5.5 V
Temperature range (TA) -40 °C to 125 °C12
Temperature range (TJ) -40 °C to 135 °C
System
Central processing unit (CPU) Arm Cortex-M4F Arm Cortex-M0+
Maximum CPU frequency 112 MHz 1, 2 48 MHz
Digital signal processor (DSP) Yes No
Floating point unit (FPU) Yes No
System memory protection unit Yes
(MPU)3
Code Cache size 4 KB Not available
Nested vectored Interrupt up to 240 vectored interrupts up to 48 interrupts
controller (NVIC)
16 programmable interrupt priority levels 4 programmable interrupt priority levels
Wake-up interrupt controller (WIC) Yes
Direct memory access (DMA) 16 channels 4 channels
Direct memory access multiplexer Yes
(DMAMUX)
Non-maskable interrupt (NMI) Yes
Software watchdog Yes
Hardware watchdog Yes, with external monitor pin. Not available
Debug 2-pin serial wire debug (SWD)
IEEE 1149.1 Joint Test Access Group Available only for BSR
(JTAG)
Trace Trace Port Interface Unit (TPIU) MTB
Boundary scan Yes
Unique Identification (ID) Number 128-bit wide
Memory

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 Chapter 2 Introduction

Table 2-1. Device feature summary (continued)

Feature S32K14x product series S32K11x product series
Program flash memory up to 2MB up to 256 KB
FlexMemory 64 KB 32 KB
Data flash (D-flash)/emulated EEPROM 2 Data flash (D-flash)/emulated EEPROM
backup (E-Flash) memory: 4 KB additional backup (E-Flash) memory: 2 KB additional
FlexRAM supporting high-endurance, non- FlexRAM supporting high-endurance, non-
volatile emulated EEPROM volatile emulated EEPROM
Flash memory controller cache Yes (single speculative prefetch buffer only)
Flash memory access control No
(FAC)
Random-access memory (RAM) Up to 256 KB. 4 KB is part of the EEERAM Up to 25 KB. 2 KB is part of the EEERAM
solution solution
Low-leakage standby memory RAM retained in all modes
QuadSPI Supports SDR and HyperRAM modes upto Not avaiable
4 and 8 bidirectional data lines respectively
Cyclic redundancy check (CRC) 16- or 32-bit CRC with programmable generator polynomial
Clocks
System clock generator (SCG) OSC, FIRC, SIRC, PLL OSC, FIRC, SIRC
External crystal oscillator or OSC: 4 - 40 MHz with low power or full-swing
resonator
External square wave input clock DC to 50 MHz
Internal clock references (IRC) 48 MHz internal IRC (FIRC) with 1% max deviation across full temperature
8 MHz internal IRC (SIRC) with 3% maximum deviation across full temperature
Phase-locked loop (PLL) Up to 320 MHz VCO Not available
Human-Machine Interface (HMI)
General-purpose input/output Up to 156 GPIOs Up to 58 GPIOs
(GPIO)
Pin interrupt / DMA request capability
Configurable digital glitch filter
Hysteresis, pull up and pull down control on all input pins
Passive input filter on NMI_b and RESET_B input pins
High drive capability on up to 32 pins
Analog
Power management controller Low voltage warning
(PMC)
Internal regulators offering various power modes
128 kHz LPO clock
12-bit analog-to-digital converter 1 Msps with 12-bit mode
1.2 Msps with 10-bit mode
Up to 64 single-ended external channels Up to 32 single-ended external channels
Up to 64 control and result registers Up to 32 control and result registers
Support result compare
High-speed comparator (CMP) Comparator with own 8-bit DAC
Timers

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NXP Semiconductors 63
Feature summary

Table 2-1. Device feature summary (continued)

Feature S32K14x product series S32K11x product series
Programmable delay block (PDB) PDB0 with up to 4 ADC channels with 8 pre-triggers for each channel for ADC0
1 pulse-out channel
PDB1 with up 2 ADC channel with 8 pre- Not available
triggers for each channel for ADC1
1 pulse-out channel
Flexible timer (FTM) 16-bit, 64 channels 16-bit, 16 channels
GTB and Global Load
Up to 2 with Quadrature Decoder
Deadtime by Pair
Up to 2 with Dither enable
32-bit Low-power programmable 4 independent channels
interrupt timer (LPIT)
Real-time clock (RTC) Yes
Low-power timer (LPTMR) LPTMR
1-channel, 16-bit pulse counter or Periodic interrupt
Communication Interfaces
Ethernet controller Dual-speed 10/100-Mbit/s Ethernet MAC Not available
compliant with the IEEE802.3-2002
standard.
Compatible with half- or fullduplex 10/100-
Mbit/s Ethernet LANs
Control Area Network (CAN) With optional ISO CAN-FD support With optional ISO CAN-FD support
FlexIO Capable of supporting a wide range of protocols (UART, I2C, SPI, I2S) and PWM/
waveform generation
Low Power Serial peripheral DMA support, 4 word FIFO support on all LPSPIs
interface (LPSPI)
Low Power Inter-Integrated Circuit Standard SMBUS compatible I2C
(LPI2C)
4 word FIFO support on LPI2C0
DMA support
1 Mbps ability (even with maximum I2C bus loading of 400 pF)
Only high-drive pins are able to support 1 Mbps
Low Power UART (LPUART) Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE J2602
Standard features
Configurable from 4x to 32x oversampling
LIN slave operation support
32-bit data width
All LPUARTs support DMA and 4-word FIFO

SAI Supports full duplex serial interfaces with Not available

frame synchronization such as I2S, AC97,
TDM, and codec/DSP interfaces.

1. HSRUN mode is limited to a maximum ambient temperature of 105°C TA

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 Chapter 2 Introduction

2. CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not
allowed to execute simultaneously. The device need to switch to RUN mode (80 Mhz) to execute CSEc (Security) or
EEPROM writes/erase.
3. On this device, NXP's system MPU implements the safety mechanisms to prevent masters from accessing restricted
memory regions. This system MPU provides memory protection at the level of the Crossbar Switch. Each Crossbar master
(Core, DMA, Ethernet) can be assigned different access rights to each protected memory region. The Arm M4 core version
in this family does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.

2.4 Block diagram

The following figure shows block diagram of the S32K14x product series.

MCM Arm Cortex M4F

Async Core
Trace TPIU PPB
port NVIC AWIC
JTAG & ITM
SWJ-DP AHB-AP
Serial Wire
FPU FPB
Clock generation
DSP DWT
DMA
MUX LPO SIRC FIRC SOSC
DCODE

System
ICODE

128 kHz 8 MHz 48 MHz 4-40 MHz 8-40 MHz

Mux SPLL
eDMA TCD
512B
LMEM
System MPU1

Main SRAM2

Upper region EIM LMEM

controller
Lower region Code Cache

ENET
M0 M1 M2 M3
S1 S2 Crossbar switch (AXBS-Lite) S3 S0

System MPU1 System MPU1 System MPU1

Mux
GPIO QuadSPI
Flash memory
controller

Peripheral bus controller

FlexRAM/
SRAM
ERM WDOG 12-bit ADC LPI2C FlexIO Low Power LPIT
Timer

Code flash Data flash

CMP memory memory
EWM 8-bit DAC
LPUART FlexCAN FlexTimer QSPI

CSEc3
CRC TRGMUX LPSPI PDB LPIT
RTC SAI

1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the Device architectural IP
level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned on all S32K devices
different access rights to each protected memory region. The Arm M4 core version in this family
Key: Peripherals present
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU. on all S32K devices
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces" Peripherals present
chapter of the S32K1xx Series Reference Manual. on selected S32K devices
(see the "Feature Comparison"
3: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this
section)
use case is not allowed to execute simultaneously. The device need to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.

Figure 2-1. S32K14x product series block diagram

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NXP Semiconductors 65
Feature comparison

The following figure shows block diagram of the S32K11x product series.
IO PORT

Arm Cortex M0+

Clock generation
IO PORT

NVIC LPO SIRC FIRC SOSC

Serial Wire SW-DP AHB-AP AWIC 128 kHz 8 MHz 48 MHz 4-40 MHz
PPB DMA
Unified Bus MUX
BPU

MTB+DWT

eDMA
AHBLite

AHBLite
M0 M2
Crossbar switch (AXBS-Lite)
S0 S1 S2

System MPU1 System MPU1

EIM
Flash memory
controller
SRAM2

FlexRAM/
SRAM2

Code flash Data flash

Peripheral bus controller
memory memory
Low Power
ERM WDOG 12-bit ADC LPI2C FlexIO LPIT
Timer
CSEc
CMP
CMU 8-bit DAC
LPUART FlexCAN FlexTimer GPIO

CRC TRGMUX LPSPI PDB LPIT

RTC

1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from Device architectural IP
accessing restricted memory regions. This system MPU provides memory protection at the on all S32K devices
level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned
different access rights to each protected memory region. The Arm M0+ core version in this family Peripherals present
Key:
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory on all S32K devices
accesses. In this document, the term MPU refers to NXP’s system MPU.
Peripherals present
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces" on selected S32K devices
chapter of the S32K1xx Series Reference Manual. (see the "Feature Comparison"
section)

Figure 2-2. S32K11x product series block diagram

2.5 Feature comparison

The following figure summarizes the memory, peripherals and packaging options for the
S32K1xx devices. All devices which share a common package are pin-to-pin compatible.

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 Chapter 2 Introduction

NOTE
Availability of peripherals depends on the pin availability in a
particular package. For more information see IO Signal
Description Input Multiplexing sheet(s) attached with
Reference Manual.

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Feature comparison

S32K11x S32K14x
Parameter K116 K118 K142 K144 K146 K148
Core Arm® Cortex™-M0+ Arm® Cortex™-M4F
Frequency 48 MHz 80 MHz (RUN mode) or 112 MHz (HSRUN mode)1
IEEE-754 FPU
Cryptographic Services Engine (CSEc)1
CRC module 1x 1x
ISO 26262 capable up to ASIL-B capable up to ASIL-B
Peripheral speed up to 48 MHz up to 112 MHz (HSRUN)
Crossbar
DMA
System

External Watchdog Monitor (EWM)

Memory Protection Unit (MPU)
FIRC CMU
Watchdog 1x 1x
Low power modes
HSRUN mode1
Number of I/Os up to 43 up to 58 up to 89 up to 128 up to 156
Single supply voltage 2.7 - 5.5 V 2.7 - 5.5 V
Ambient Operation Temperature (Ta) -40oC to +105oC / +125oC -40oC to +105oC / +125oC
Flash 128 KB 256 KB 256 KB 512 KB 1 MB 2 MB2
Error Correcting Code (ECC)
System RAM (including FlexRAM and MTB) 17 KB 25 KB 32 KB 64 KB 128 KB 256 KB
Memory

FlexRAM (also available as system RAM) 2 KB 4 KB

Cache 4 KB

EEPROM emulated by FlexRAM1 2 KB (up to 32 KB D-Flash) 4 KB (up to 64 KB D-Flash) See footnote 3

External memory interface QuadSPI incl.

HyperBus™
Low Power Interrupt Timer (LPIT) 1x 1x
FlexTimer (16-bit counter) 8 channels 2x (16) 4x (32) 6x (48) 8x (64)
Timer

Low Power Timer (LPTMR) 1x 1x

Real Time Counter (RTC) 1x 1x
Programmable Delay Block (PDB) 1x 2x
Trigger mux (TRGMUX) 1x (43) 1x (45) 1x (64) 1x (73) 1x (81)
Analog

12-bit SAR ADC (1 Msps each) 1x (13) 1x (16) 2x (16) 2x (24) 2x (32)
Comparator with 8-bit DAC 1x 1x
10/100 Mbps IEEE-1588 Ethernet MAC 1x
Serial Audio Interface (AC97, TDM, I2S) 2x
Communication

Low Power UART/LIN (LPUART)

(Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE J2602) 2x 2x 3x

Low Power SPI (LPSPI) 1x 2x 2x 3x

Low Power I2C (LPI2C) 1x 1x 2x
FlexCAN 1x 2x 3x 3x 3x
(CAN-FD ISO/CD 11898-1) (1x with FD) (1x with FD) (1x with FD) (2x with FD) (3x with FD)
FlexIO (8 pins configurable as UART, SPI, I2C, I2S) 1x 1x
SWD, JTAG
Debug & trace SWD, MTB (1 KB), JTAG4 SWD, JTAG (ITM, SWV, SWO) (ITM, SWV,
IDEs

SWO), ETM
Ecosystem NXP S32 Design Studio (GCC) + SDK, NXP S32 Design Studio (GCC) + SDK,
(IDE, compiler, debugger) IAR, GHS, Arm®, Lauterbach, iSystems IAR, GHS, Arm®, Lauterbach, iSystems
48-pin LQFP 64-pin LQFP 100-pin MAPBGA
48-pin LQFP
Other

Packages5 32-pin QFN 48-pin LQFP 64-pin LQFP 100-pin MAPBGA 100-pin LQFP6
64-pin LQFP
48-pin LQFP 64-pin LQFP 100-pin LQFP 100-pin LQFP 144-pin LQFP
100-pin LQFP
100-pin MAPBGA 144-pin LQFP 176-pin LQFP
LEGEND:
Not implemented
Available on the device
1 No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when
device is running at HSRUN mode (112MHz) or VLPR mode.
2 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash.
3 4 KB (up to 512 KB D-Flash as a part of 2 MB Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB
of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details.
4 Only for Boundary Scan Register
5 See Dimensions section for package drawings
6 Under development, QuadSPI not supported for S32K148 in 100-pin LQFP

Figure 2-3. S32K1xx product series comparison

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 Chapter 2 Introduction

2.5.1 Differences between S32K14x and S32K11x

Due to the differences in core and cache architecture between S32K11x and S32K14x
devices, their CPU execution and interrupt latency will be different which in turn will
affect the observed time among the timers, and the associated events triggered by them.
See Arm Cortex-M4F Technical Reference Manual and Arm Cortex-M0+ Technical
Reference Manual for core architecture details. For more differences, see AN11997,
available at nxp.com.

2.6 Applications
The S32K1xx product series are the ideal choices for general purpose automotive
applications, which include but not limited to:
• Exterior and interior lighting
• HVAC
• Door/Window/Wiper/Seat controller
• BLDC/PMSM motor control
• Park assistant
• E-shifter
• TPMS
• Real time control in infotainment system
• Battery management system
• Human machine interface such as touch sense control
• Secured vehicle data transfer
• Safety controller
• Over the air update 4
Moreover, the 100 Mbit IEEE-1588 Ethernet MAC and Serial audio interface (AC97,
TDM, and I2S) on S32K148 make it fit perfectly for Ethernet connected edge nodes in
vehicle, and the audio streaming application.
In addition to automotive applications, the S32K1xx product series can also be used in
challenging environments found in industrial, automation, communications,
transportation, medical and A & D applications which need high level quality, reliability
and safety.
NOTE
• For safety aware and critical application, the user must
refer to S32K1xx Safety Manual and Using the S32K1xx

4. See S32K Architecture and Capabilities to Enable Over the Air Updates

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NXP Semiconductors 69
Module functional categories

EEPROM Functionality application note available on

nxp.com for correct part operation requirements.
• See S32K1xx Safety Manual and Production Flash
Programming Best Practices for S32K1xx MCUs
application note available on nxp.com for correct part
operation and memory handling during programming of the
internal flash memory.

2.7 Module functional categories

The modules on this device are grouped into functional categories. The following
sections describe the modules assigned to each category in more detail.
Table 2-2. Module functional categories
Module category Description
Arm® Cortex®-M4F core • 32-bit MCU core from Arm's Cortex-M class adding DSP instructions and
single-precision floating point unit based on Armv7 architecture
Arm® Cortex®-M0+ core • 32-bit MCU core from Arm’s Cortex-M class, implements the Armv6-M
architecture profile.
System • Miscellaneous control module (MCM)
• System integration module (SIM)
• Port Control and Interrupts (PORT)
• General purpose input/output controller (GPIO)
• Crossbar switch (AXBS-Lite)
• Peripheral bridge (AIPS-Lite)
• Trigger Mux Control (TRGMUX)
• Watchdog timer (WDOG)
• Cyclic Redundancy Check (CRC)
Clocking • Multiple clock generation options available from internally- and externally-
generated clocks
• System oscillator to provide clock source for the MCU
Memories • Internal memories include:
• Program flash memory
• FlexMemory
• FlexNVM
• FlexRAM
• SRAM
• Direct memory access (DMA) controller with multiplexer to increase available
DMA requests. DMA can now handle transfers in VLPS mode
Power Management Power management and mode controllers (PMC)
• Multiple power modes available based on high speed run, run, stop
Security • Error-correcting code (ECC) on Flash and SRAM memories
• 128-bit unique identification (ID) number
• System Memory Protection Unit (MPU) module
Safety Clock monitoring unit (CMU), for monitoring FIRC clock
Power Management Power management and mode controllers (PMC)
• Multiple power modes available based on high speed run, run, stop

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Table 2-2. Module functional categories (continued)

Module category Description
Analog • High speed analog-to-digital converter (ADC)
• Comparator (CMP), containing 8 bit reference DAC
• Bandgap voltage reference (1V reference voltage)
Timers • Programmable delay block (PDB)
• FlexTimers
• Low-power periodic interrupt timer (LPIT)
• Low power timer (LPTMR)
• Independent real time clock (RTC)
Communications • Ethernet MAC with IEEE802.3-2002 standard.
• Low-power Serial peripheral interface (LPSPI)
• Low-power Inter-integrated circuit (LPI2C)
• Low-power UART (LPUART)
• Synchronous Audio Interface (SAI)/Integrated interchip sound (I2S)
• FlexIO
• FlexCAN
Debug • JTAG Controller (JTAGC)

2.7.1 Arm® Cortex®-M4F Core Modules

The following core modules are available on this device.
Table 2-3. Core modules
Module Description
Arm Cortex-M4F The Arm® Cortex®-M4F is the newest member of the Cortex M Series of
processors targeting microcontroller cores focused on very cost sensitive,
deterministic, interrupt driven environments. The Cortex M4F processor is based
on the Armv7 Architecture and Thumb®-2 ISA and is upward compatible with the
Cortex M3, Cortex M1, and Cortex M0 architectures. Cortex M4F improvements
include an Armv7 Thumb-2 DSP (ported from the Armv7-A/R profile architectures)
providing 32-bit instructions with SIMD (single instruction multiple data) DSP style
multiply-accumulates and saturating arithmetic.
Floating point unit (FPU) A single-precision floating point unit (FPU) that is compliant to the IEEE Standard
for Floating-Point Arithmetic (IEEE 754).
NVIC The Armv7-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single
non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a
particular handler. The address is fetched via the instruction port allowing parallel
register stacking and look-up. The first sixteen entries are allocated to Arm internal
sources, with the others mapping to MCU-defined interrupts.
AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and then signal to clock
control logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.

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Module functional categories

Table 2-3. Core modules (continued)

Module Description
Debug interfaces Most of the debug capability on this device is based on the Arm CoreSight™
architecture. Following debug interfaces are supported:
• Serial wire IEEE 1149.1 JTAG debug Port (SWJ-DP), with 2 pin serial wire
debug (SWD) for external debugger
• Debug Watchpoint and Trace (DWT), with four configurable comparators as
hardware watchpoints
• Serial wire output (SWO)-synchronous trace data support
• Instrumentation Trace Macrocell (ITM) with software and hardware trace,
plus time stamping
• Flash Patch and Breakpoints (FPB) with ability to patch code and data from
code space to system space
• Serial Wire Viewer (SWV): A trace capability providing displays of reads,
writes, exceptions, PC Samples and printf.
• Supports 4 pin trace interface

2.7.2 Arm Cortex-M0+ Core Modules

The following core modules are available on this device.
Table 2-4. Core modules
Module Description
Arm Cortex-M0+ The Arm® Cortex™-M0+processor is a configurable, multistage, 32-bit RISC
processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It
also has optional hardware debug, single-cycle I/O interfacing, and memory-
protection functionality. The processor can execute Thumb code and is compatible
with other Cortex-M profile processors.
NVIC NVIC features up to 32 external interrupt inputs, each with four levels of priority. It
implements optional relocation of the vector table.
It features dedicated Non-Maskable Interrupt (NMI) input, supprts optional Wake-
up Interrupt Controller (WIC), providing ultra-low power sleep mode support.
AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control
logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.
Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor
implements a dedicated single-cycle I/O port.
Debug interfaces Most of this device's debug is based on the Arm CoreSight™ architecture. One
debug interfaces are supported:
• Serial Wire Debug (SWD)
• Micro Trace Buffer (MTB)

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2.7.3 System modules

The following system modules are available on this device.
Table 2-5. System modules
Module Description
Miscellaneous control module (MCM) The MCM includes miscellaneous control logic for Core and System modules.
System integration module (SIM) The SIM includes miscellaneous device configuration and status registers.
PORT The Port Control and Interrupt (PORT) module provides support for port control,
digital filtering, and external interrupt functions.
GPIO The general-purpose input and output (GPIO) module communicates to the
processor core via a zero wait state interface for maximum pin performance. The
GPIO registers support 8-bit, 16-bit or 32-bit accesses.
Crossbar switch (AXBS-Lite) The AXBS-Lite connects bus masters and bus slaves, allowing all bus masters to
access different bus slaves simultaneously and providing arbitration among the bus
masters when they access the same slave.
System Memory protection unit (MPU) The system MPU provides memory protection and task isolation. It concurrently
monitors all bus master transactions for the slave connections.
Peripheral bridge (AIPS-Lite) The AIPS-Lite converts the crossbar switch interface to an interface that allows
access to a majority of peripherals on the device.
Direct memory access multiplexer The DMAMUX selects from many DMA requests down to a smaller number for the
(DMAMUX) DMA controller.
enhanced Direct Memory Access The eDMA provides programmable channels with transfer control descriptors for
controller (eDMA) data movement via dual-address transfers for 8-bit, 16-bit, 32-bit, 16-byte and 32-
byte data values.
TRGMUX The trigger multiplexer (TRGMUX) module allows software to configure the trigger
sources for various peripherals.
External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that
monitors both internal and external system operation for fail conditions.
Software watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 128 kHz low power oscillator with a
programmable refresh window to detect deviations in program flow or system
frequency.
CRC Hardware CRC generator circuit using 16/32-bit shift register. Error detection for all
single, double, odd, and most multi-bit errors, programmable initial seed value, and
optional feature to transpose input data and CRC result via transpose register.

2.7.4 Memories and memory interfaces

The following memories and memory interfaces are available on this device.
Table 2-6. Memories and memory interfaces
Module Description
Local memory controller(LMEM) Manages simultaneous accesses to system RAM by multiple master peripherals
and core. Also provide cache control, which improves system performance by
providing single-cycle access to the instruction and data pipelines.

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Module functional categories

Table 2-6. Memories and memory interfaces (continued)

Module Description
Miscellaneous System Control Module The Miscellaneous System Control Module (MSCM) contains CPU configuration
(MSCM) registers and on-chip memory controller registers.
Flash memory • Program flash memory — non-volatile flash memory that can execute
program code
• FlexMemory — encompasses the following memory types:
• FlexNVM — Non-volatile flash memory that can execute program
code, store data, or backup emulated EEPROM data
• FlexRAM — RAM memory that can be used as traditional SRAM or as
high-endurance emulated EEPROM storage, and also accelerates
flash programming
QuadSPI The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to
external serial flash device. It supports SDR and HyperRAM modes up to 4 and 8
bidirectional data lines respectively.
Flash memory controller Manages the interface between the device and the on-chip flash memory.
SRAM Internal system RAM.

2.7.5 Power Management

The following modules are available on this device for power management and system
power modes control:
Table 2-7. Power Management modules
Module Description
PMC The PMC contains the internal voltage regulator, power on reset (POR) and the
low voltage detect (LVD) system.
SMC The System Mode Controller (SMC) is responsible for sequencing the system into
and out of all low-power Stop and Run modes.

2.7.6 Clocking
The following clock modules are available on this device.
Table 2-8. Clock modules
Module Description
System clock generator (SCG) The SCG provides several clock sources for the MCU that include:
• Phase-locked loop (PLL) — Voltage-controlled oscillator (VCO)
• Fast internal reference clock (FIRC) — An internally-generated 48 MHz
clock, which can be used as a clock source for other on-chip peripherals
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 Chapter 2 Introduction

Table 2-8. Clock modules (continued)

Module Description
• Slow internal reference clock (SIRC) — An internally-generated 8 MHz clock,
which can be used as a clock source for other on-chip peripherals
• System oscillator (OSC) — The system oscillator, in conjunction with an
external crystal or resonator, generates a reference clock for the MCU
Low Power Oscillator (LPO) An internally-generated low power clock with typical frequency of 128 kHz, which
can be used as clock source for modules operational in low power modes.
Peripheral Clock Control (PCC) Controls the clock selection for most modules.

2.7.7 Analog modules

The following analog modules are available on this device:
Table 2-9. Analog modules
Module Description
12-bit analog-to-digital converters (ADC) 12-bit successive-approximation ADC
Analog comparators (CMP) Compares two analog input voltages across the full range of the supply voltage.
8-bit digital-to-analog converters (DAC) 256-tap resistor ladder network which provides a selectable voltage reference for
within CMP applications where a voltage reference is needed.

2.7.8 Timer modules

The following timer modules are available on this device:
Table 2-10. Timer modules
Module Description
Programmable delay block (PDB) • 16-bit resolution
• 3-bit prescaler
• Positive transition of trigger event signal initiates the counter
• Supports multiple triggered delay output signals, each with an independently-
controlled delay from the trigger event
• Continuous-pulse output or single-shot mode supported, each output is
independently enabled, with possible trigger events
• Supports bypass mode
• Supports DMA
Flexible timer module (FTM) • Selectable FTM source clock, programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up
or up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM
modes
• Operation of FTM channels as pairs with equal outputs, pairs with
complementary outputs, or independent channels with independent outputs
Table continues on the next page...

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Module functional categories

Table 2-10. Timer modules (continued)

Module Description
• Deadtime insertion is available for each complementary pair
• Generation of hardware triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• Configurable channel polarity
• Programmable interrupt on input capture, reference compare, overflowed
counter, or detected fault condition and reload opportunity.
• Quadrature decoder with input filters, relative position counting, and interrupt
on position count or capture of position count on external event
• DMA support for FTM events
Low-power periodic interrupt timer • Four general purpose interrupt timers
(LPIT) • Interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• The counter is clocked by an asynchronous clock that can remain enabled in
low power modes.
• DMA support
• Supports chaining of Timer channels
Low power timer (LPTMR) • Selectable clock for prescaler/glitch filter of 128 kHz (internal LPO), or
internal reference clock
• Configurable glitch filter or prescaler with 16-bit counter
• 16-bit time or pulse counter with compare
• Interrupt generated on Timer Compare
• Hardware trigger generated on Timer Compare
Real-time clock (RTC) • 32-bit seconds counter with 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm
and 3906 ppm

2.7.9 Communication interfaces

The following communication interfaces are available on this device:
Table 2-11. Communication modules
Module Description
Low-power Serial peripheral interface Synchronous serial bus for communication to an external device. LPSPI optionally
(LPSPI) remains functional in low power modes.
Low-power Inter-integrated circuit Allows communication between a number of devices. Also supports the System
(LPI2C) Management Bus (SMBus) Specification, version 2. LPI2C optionally remains
functional in low power modes.
Low-power Universal asynchronous Asynchronous serial bus communication interface, supporting LIN master and
receiver/transmitters (LPUART) slave operation. LPUART optionally remains functional in low power modes.
SAI/I2S The I2S (or I2S) module provides a synchronous audio interface (SAI) that
supports fullduplex serial interfaces with frame synchronization such as I2S, AC97,
TDM, and codec/DSP interfaces.
ENET The core implements a dual-speed 10/100-Mbit/s Ethernet MAC compliant with the
IEEE802.3-2002 standard. The MAC layer provides compatibility with half- or
fullduplex 10/100-Mbit/s Ethernet LANs.

Table continues on the next page...

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 Chapter 2 Introduction

Table 2-11. Communication modules (continued)

Module Description
FlexCAN The FlexCAN module is a communication controller implementing the CAN
protocol according to the ISO 11898-1 standard and CAN 2.0 B protocol
specifications.

2.7.10 Debug modules

The following Debug modules are available on this device:
Table 2-12. Debug modules
Module Description
JTAGC The JTAGC block provides the means to test chip functionality and connectivity
while remaining transparent to system logic when not in test mode. Testing is
performed via a boundary scan technique, as defined in the IEEE 1149.1-2001
standard. All data input to and output from the JTAGC block is communicated in
serial format.

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Module functional categories

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Chapter 3
Memory Map

3.1 Introduction
This chip contains various memories and memory-mapped peripherals that are located in
one 32-bit contiguous memory space. This chapter describes the memory and peripheral
locations within that memory space.
Details about the memory map appear in the spreadsheet that is attached to this
document: S32K1xx_memory_map.xlsx. To access this spreadsheet, view the document's
list of attachments.

3.2 SRAM memory map

3.2.1 S32K14x: SRAM memory map

The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in
the memory map. See S32K1xx_memory_map.xlsx attached to this document for details.
Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on
the chip causes the bus cycle to be terminated with an error followed by the appropriate
response in the requesting bus master.

3.2.2 S32K11x: SRAM memory map

In S32K11x on-chip RAM can be used in following applications:
• Safety critical applications: SRAM_U can be used, which starts from 2000_0000
• Non-safety critical applications: SRAM_U along with 1 KB MTB can be used

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Flash memory map

NOTE
CM0+ architecture implements single RAM controller, hence
SRAM_U and MTB are referred as single contiguous memory
regions. MTB in S32K11x is present at the same location as
SRAM_L in S32K14x.
See S32K1xx_memory_map.xlsx attached to this document for details. Accesses to the
memory ranges outside the amount of RAM on the chip causes the bus cycle to be
terminated with an error followed by the appropriate response in the requesting bus
master.

3.3 Flash memory map

The various flash memories and the flash memory registers are located at different base
addresses as shown in the following figure. The base address for each is specified in the
S32K1xx_memory_map.xlsx file attached to this document.

Flash memory base address

Registers

Program flash memory base address

Flash memory configuration field
Program flash
memory

FlexNVM base address

FlexNVM

FlexRAM base address

FlexRAM

Figure 3-1. Flash memory map

3.4 Peripheral bridge (AIPS-Lite) memory map

The peripheral memory map is accessible via a crossbar slave port.
There are three regions associated with peripheral space, as shown in the following table.

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 Chapter 3 Memory Map

Table 3-1. Regions associated with peripheral space

Address space Region description
0x4000_0000–0x4001_FFFF A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for on-
platform peripheral devices. AIPS-Lite generates unique module enables for all 32
spaces.
0x4002_0000–0x4007_FFFF A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for off-
platform modules. AIPS-Lite generates unique module enables for all 96 spaces.
0x400F_F000 A 4 KB region for accessing the GPIO module. This block is connected to the
AMBA bus via the port splitter and provides direct master access without incurring
wait states associated with accesses via the AIPS-Lite modules. The GPIO is
implemented only in the upper space of this region (4 KB beginning at
0x400F_F000).

Modules that are disabled via their clock gate control bits in the PCC/SIM registers
disable the associated AIPS-Lite slots. Access to any address within an unimplemented or
disabled peripheral bridge slot results in a transfer error termination.
NOTE
While trying to access memory map region of unavailable
feature (See SIM_SDID[FEATURES]) with corresponding
module clock enabled through PCC CGC bit, there will not be
any transfer error termination.

3.4.1 Read-after-write sequence and required serialization of

memory operations
In some situations, a write to a peripheral must be completed fully before a subsequent
action can occur. Examples of such situations include:
• Exiting an interrupt service routine (ISR)
• Changing a mode
• Configuring a function
In these situations, the application software must perform a read-after-write sequence to
guarantee the required serialization of the memory operations, as shown in the following
table.
Table 3-2. Read-after-write sequence to guarantee required serialization of memory
operations
Step Action
1 Write the peripheral register.
2 Read the written peripheral register to verify the write.
3 Continue with subsequent operations.

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Private Peripheral Bus (PPB) memory map

NOTE
In S32K14x series of devices, one factor contributing to these
situations is processor write buffering. The processor
architecture has a programmable configuration field to disable
write buffering: ACTLR[DISDEFWBUF]. (For details see
Arm® Cortex® M4 Processor Technical Reference Manual,
Revision r0p1, at http://arm.com ). However, disabling buffered
writes is likely to degrade system performance much more than
simply performing the required memory serialization for the
situations that truly require it.

3.5 Private Peripheral Bus (PPB) memory map

The PPB is part of the defined Arm bus architecture and provides access to select
processor-local modules. These resources are only accessible from the core; other system
masters do not have access to them.
Table 3-3. PPB memory map for CM4
System 32-bit address range Resource
0xE000_0000–0xE000_0FFF Instrumentation Trace Macrocell (ITM)
0xE000_1000–0xE000_1FFF Data Watchpoint and Trace (DWT)
0xE000_2000–0xE000_2FFF Flash Patch and Breakpoint (FPB)
0xE000_3000–0xE000_DFFF Reserved
0xE000_E000–0xE000_EFFF System Control Space (SCS) (for NVIC and FPU
0xE000_F000–0xE003_FFFF Reserved
0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU)
0xE004_1000–0xE004_1FFF Reserved
0xE004_2000–0xE004_2FFF Reserved
0xE004_3000–0xE004_3FFF Reserved
0xE004_4000–0xE007_FFFF Reserved
0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM)
0xE008_1000–0xE008_1FFF Reserved
0xE008_2000–0xE008_2FFF Cache Controller (LMEM)
0xE008_3000–0xE00F_EFFF Reserved
0xE00F_F000–0xE00F_FFFF Arm Core ROM Table1 - allows auto-detection of debug components

1. The Arm Core ROM table is optionally required by Arm CoreSight debug infrastructure to discover the components on the
chip. This ROM table has no any relationship with the MCU Boot ROM.

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 Chapter 3 Memory Map

Table 3-4. PPB memory map for CM0+

System 32-bit address range Resource
0xE000_0000–0xE000_0FFF Reserved 1
0xE000_1000–0xE000_1FFF Data Watchpoint and Trace (DWT)
0xE000_2000–0xE000_2FFF Arm Core ROM Table
0xE000_3000–0xE000_DFFF Reserved1
0xE000_E000–0xE000_EFFF System Control Space (SCS) (for NVIC)
0xE000_F000–0xE003_FFFF Reserved1
0xE004_0000–0xE004_0FFF Reserved1
0xE004_1000–0xE004_1FFF Reserved1
0xE004_2000–0xE004_2FFF Reserved1
0xE004_3000–0xE004_3FFF Reserved1
0xE004_4000–0xE007_FFFF Reserved1
0xE008_0000–0xE008_0FFF Reserved1
0xE008_1000–0xE008_1FFF Reserved1
0xE008_2000–0xE008_2FFF Reserved1
0xE008_3000–0xE00F_EFFF Reserved1
0xE00F_F000–0xE00F_FFFF Reserved1
0xE010_0000-0xEFFF_FFFF Reserved1

1. Reserved area return transfer error. Reserved is Unknown/Should be 0. Software must not rely on reading as all 0s, and it
must treat the value as if it is unknown.

3.6 Aliased bit-band regions for CM4 core

The SRAM_U, AIPS-Lite, and general purpose input/output (GPIO) module resources
reside in the Cortex-M4F processor bit-band regions.
The processor also includes two 32 MB aliased bit-band regions associated with the two
1 MB bit-band spaces. Each 32-bit location in the 32 MB space maps to an individual bit
in the bit-band region. A 32-bit write in the alias region has the same effect as a read-
modify-write operation on the targeted bit in the bit-band region.
Bit 0 of the value written to the alias region determines what value is written to the target
bit:
• Writing a value with bit 0 set writes a 1 to the target bit.
• Writing a value with bit 0 clear writes a 0 to the target bit.
A 32-bit read in the alias region returns either:
• a value of 0x0000_0000 to indicate the target bit is clear
• a value of 0x0000_0001 to indicate the target bit is set

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Aliased bit-band regions for CM4 core
Bit-band region Alias bit-band region

31 0 31 0

1 MB

32 MB
Figure 3-2. Alias bit-band mapping

NOTE
Each bit in a bit-band region has an equivalent bit that can be
manipulated through bit 0 in a corresponding long word in the
alias bit-band region.
NOTE
Do not use bit banding for w1c status bits.
CAUTION
The S32K product series and the software drivers support bit-
banding, but Arm no longer promotes its usage. Therefore, we
recommend that bit-banding should not be used.

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Chapter 4
Signal Multiplexing and Pin Assignment

4.1 Introduction
The signal multiplexing enables the sharing of single pad for multiple functions.
The signal multiplexing unit comprises of control signals from GPIO, PORT and pad
interface logic. The signal multiplexing unit consists of several individual sub-units, each
handling the signal multiplexing of one pad.
The Port Control block controls the module specific pad settings (pull up etc) and the
signal present on the external pin. See PORT_PCR for the description of control signals.
For reset values per port, see IO Signal Description Input Multiplexing sheet(s) attached
to the Reference Manual.

4.2 Functional description

The signal multiplexing architectural implementation is as shown in the following figure.

ind ind ind

GPIO

Pad controls

do Signal do Functional
Padring Multiplexing Modules/
Unit Peripherals
obe obe

ibe ibe

Figure 4-1. Signal Multiplexing

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Pad description

4.3 Pad description

Following figure shows the basic representation of a GPIO Pad.
obe

do Output
Driver
Pad

pue

pus

ibe Pull logic

ind Input
Receiver

Figure 4-2. GPIO pad representation

Table 4-1. Pad Signal description

Signal name Direction Descriprtion
pad I/O I/O to external world
do I Data coming from the core into the pad
obe I Enable output driver
pue I 0: Disable internal pullup or pulldown resistor 1: Enable internal pullup or
pulldown resistor
pus I 0: Enable internal pulldown resistor if pue is set 1: Enable internal pullup
resistor if pue is set
ibe I Enable input receiver
ind O Data coming out of the pad into the core

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 Chapter 4 Signal Multiplexing and Pin Assignment

Table 4-2. Truth table

obe do pad Description
0 X Z Output buffer disabled, pad hi-Z (If not configured as input)
1 0/1 0/1 Output buffer enable, pad = do

pue pus pad Description

0 X - Weak pull disabled. Pad retains previous state
1 0 0 Weak pull down enabled
1 1 1 Weak pull up enabled

ibe pad ind Description

0 X 0 Input buffer disabled, ind gets low
1 0/1 0/1 Input buffer enabled, ind = pad

NOTE
The device does not support open drain on all the pins. Only
pins that are configured for a protocol that requires open-drain
(e.g;, LPI2C, LPUART single-wire) will work in open-drain
mode.

4.4 Default pad state

The default pad configurations out of reset are as follows. For PTA4, PTA5, PTC4 and
PTC5, the default configurations are as per protocol specifications/requirements.
Table 4-3. Default pad configurations
Pin Default Default pad ibe obe pue pus
function state1
PTA4 JTAG_TMS Weak pull-up 1 0 1 1
enabled
PTA5 2 RESET_b Weak pull-up 1 0 1 1
enabled
PTC4 JTAG_TCK Weak pull-down 1 0 1 0
enabled
PTC5 JTAG_TDI Weak pull-up 1 0 1 1
enabled
Others Disabled High impedance 0 0 0 0

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Signal Multiplexing sheet

1. The IO pad states are undefined until VDD rises sufficiently to enable the POR circuits. The level at which this occurs will
vary from device to device, but for reference it is approximately 700 mV. After POR circuits are enabled, the IO pad states
are high impedance with weak pull devices disabled until POR release.
2. While in reset, the pin behavior is same apart from reset pin. Chip drives pad low via obe=1, pue=0, till reset sequence is
complete to indicate reset to off-chip connected devices.

4.5 Signal Multiplexing sheet

IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual
contains information on pins/balls of this device.
The 'IO Signal Table' and 'Input Muxing' tabs in the sheet correspond to the signal
multiplexing information. The 'IO Signal Table' consists of all the pin muxing details and
the 'Input Muxing' specifies the priority for the input muxing where an input path is
driven by more than one pad.
S32K1xx variant specific IO Signal Description Input Multiplexing sheets attached to the
Reference Manual contains information about the pins/balls of the particular variant.
Module functionality is dependent on the availability of functional pins in a particular
package. For example LPI2C HREQ pin is not available in 48-LQFP and 32-QFN
package.

4.5.1 IO Signal Table

Following is an example snippet of IO Signal Table. For selecting any functionality, the
pad PCR register (refer to PORT_PCRn) needs to be configured accordingly.

Figure 4-3. IO signal table snippet

The columns of the above figure are described below:

• Port: This field in IO Signal Table specifies the PAD names of the device.
• CR(Control Register): This field specifies the name of PCR corresponding to the Port
field. On this device there are five PORT instances, namely, PTA, PTB, PTC, PTD
and PTE. Each pad has a corresponding Control Register, referred to as PCR_PTXn

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 Chapter 4 Signal Multiplexing and Pin Assignment

in the IO Signal Table, where X refers to PORT instance and n refers to

corresponding pin of that PORT instance. Refer PORT_PCR for description of PCR
fields.
• SSS: This field specifies the ALT mode of operation as per PCR[Mux_mode]. Not
all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved.
The corresponding pin is configured in the following pin muxing slot as follows:
• 000: Alternative 0 (Signal path disabled)
• 001: Alternative 1 (GPIO)
• 010: Alternative 2 (chip-specific)
• 011: Alternative 3 (chip-specific)
• 100: Alternative 4 (chip-specific)
• 101: Alternative 5 (chip-specific)
• 110: Alternative 6 (chip-specific)
• 111: Alternative 7 (chip-specific)
The analog functionalities are specified with '-' in this field. Here ADC_SE0 and
CMP_IN0 represent analog functions.
By default, ALT0 mode (configured by PTXn_PCR[SSS] as 3’b000)
corresponds to disabled functionality and pad represents disabled (high-
impedance) state. In case if the pad consists of analog functions, the ALT0 mode
corresponds to analog functionality once the analog module is configured to
enable corresponding channel/input.
For example, PTA0 supports ADC0 channel 0 and CMP channel 0. By default
the pad is disabled. After ADC0 is configured to enable channel0 using
ADC0_SC1n[ADCH], the pad functions as ADC input channel. Alternatively if
CMP is configured to enable channel 0 using CMP_C1[PSEL] or
CMP_C1[MSEL], the pad functions as CMP input channel. The software must
ensure to enable only one function at a time.
• Function: This field specifies the functionality of the pad as per the corresponding
ALT mode specified by SSS field.
• Module: The Module field contains the module which is governing the pad for the
ALT mode.
• Description: This field mentions a short description of pad functionality.
• Direction: This field specifies the direction (Input, Output or Inout) of the pad for the
concerned functionality.
• The next columns specify the pin number in the supported packages for the device.
• PCR: This field specifies the default PCR value for corresponding pad. Refer
PORT_PCR for description of PCR fields.

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Signal Multiplexing sheet

• The next two columns specify the reset value and the configurable bit fields of PCR
corresponding to pad.
• Pad Type: This field mentions the pad type of the corresponding pad.
• GPIO: General Purpose IO Pad (Standard)
• GPIO-HD: General Purpose IO Pad that support high drive functionality
(Strong)
• GPIO-FAST: General Purpose IO Pad that support High Speed (applicable for
S32K148 only)
NOTE
If oscillator is enabled then enabling the GPIO or LPI2C
function for EXTAL/XTAL pins can lead to device damage.
This must be avoided by software.

4.5.2 Input muxing table

As the same function can be multiplexed to several pads by configuring their respective
PCRs, there is priority input muxing. In case of same input being driven from multiple
pads, the one with highest priority (1 being the highest) will drive the input. Following is
a snippet of Input Muxing Table.

Figure 4-4. Input muxing table snippet

The columns of the figure are briefly described below:

• Destination Instance: This field contains the instance name of the input path to where
the signal will propagate from padring.
• Destination Function: This field mentions the function name of the input path.
• Priority: This field specifies the priority of the path. Priority level 1 is highest and it
decreases onwards.
• SSS: This field specifies the PCR[Mux_mode] value corresponding to the pad
specified in source signal column. A blank is mentioned for the default source when
none pad is driving the input path.
• Source Instance: This field specifies the source pad type. A blank is mentioned for
the default source when none pad is driving the input path.
• Source Signal: This field mentions the pad name. A ‘disable low’/’disable high’
specifies the signal behavior when none of the pads are driving the input path.

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4.6 Pinout diagrams

See IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual
for pinout diagrams corresponding to available packages.

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Pinout diagrams

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Chapter 5
Security Overview

5.1 Introduction
All chips of this S32K1xx product series have a comprehensive set of customer-
configurable security features designed to protect code and data from unauthorized
access.

5.2 Device security

Flash memory security is available to both CSEc and non-CSEc parts. SIM_SDID[7]
indicates whether CSEc is available on your device.
Both CSEc and non CSEc users need to run PGMPART command to configure the Key
Size for the device. For more information, see Program Partition command. This process
involves configuring a number of user keys. For non CSEc users, Key Size will be 00.
• The total size of EEERAM is reduced by the space required to store the user keys.
(See Introduction chapter for available EEERAM.)
• The user key space effectively becomes un-addressable space in the EEERAM.
• For non-CSEc parts and CSEc parts with key size=00, CSEc_PRAM access is not
guaranteed.

5.2.1 Flash memory security

The flash memory module provides security information to the MCU based on the state
held by the FSEC[SEC] field. The MCU, in turn, confirms the security request and limits
access to flash memory resources. During reset, the flash memory module initializes the
FSEC register using data read from the security byte of the flash memory configuration
field.

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Device security

NOTE
The security features apply only to external accesses via debug.
CPU accesses to the flash memory are not affected by the status
of FSEC.
In the unsecured state, all flash memory commands are available to the programming
interfaces (SWD (Serial Wire Debug) and JTAG (Joint Test Access Group)), as are user
code execution of Flash Memory Controller commands. When the flash memory is
secured (FSEC[SEC] = 00b, 01b, or 11b), programmer interfaces are allowed to launch
only mass erase operations and have no access to memory locations.
Further information regarding the flash memory security options and enabling/disabling
flash security is available in the Flash Memory Module.

5.2.1.1 Flash memory security interactions with debug

When flash memory security is active, the JTAG port cannot access the memory
resources of the MCU. Boundary scan chain operations work, but debugging capabilities
are disabled so that the debug port cannot read flash memory contents.
When flash memory security is active, the SWD port cannot access the memory resources
of the MCU.
Although most debug functions are disabled, the debugger can write to the Flash Mass
Erase in Progress bit in the MDM-AP Control register to trigger a mass erase (Erase All
Blocks) command provided that MEEN (mass erase) is enabled. Running the mass erase
de -asserts the FSEC and after that JTAG port can access the memory resources. A mass
erase via the debugger is allowed even when some memory locations are protected.
When mass erase is disabled, mass erase via the debugger is blocked. Hence, you will not
be able to connect the debugger in a secure device (MEEN disabled). An alternative in
that case would be to run verify backdoor key access through any communication
interface.
The FTFC_FCSESTAT[EDB] bit clear status is as follows:
• If the debugger has switched to SWD mode, the FTFC_FCSESTAT[EDB] bit can be
reset only through POR.
• If the debugger remains in JTAG mode, the FTFC_FCSESTAT[EDB] bit is reset on
pin_reset if correct debugger disconnection takes place or on POR.

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 Chapter 5 Security Overview

5.2.2 Cryptographic Services Engine (CSEc) security features

The FTFC module's Cryptographic Services Engine (CSEc) implements a comprehensive
set of cryptographic functions as described in the SHE Functional Specification,
including:
• >10 general purpose keys
• AES-128, CBC, ECB, CMAC
• Sequential, Parallel, and Strict Boot mode
• AES-128 CMAC calculation and authentication
• Pseudo random number generation (PRNG) and true random number generation
(TRNG)

5.2.3 Device Boot modes

In parallel secure boot mode, secure boot and application boot shall happen in parallel.
Also even if the secure boot fails, the application shall boot. But Keys having
BOOT_PROT attribute set to one, would be disabled. Application can make use of rest of
the keys and encryption/decryption/SHE functions. However, application code should
poll the Busy Flag FCSESTAT[BSY] , before attempting to actuate any SHE command.
Additionally, during parallel secure boot, any mode transition initiated by Core will be
aborted and secure boot will proceed.
During parallel boot operation FLASH_CLK must be the default FIRC_CLK and should
not be changed until boot operation is complete. Once the boot operation is complete it
can be changed to any value including its maximum value of 26.6 MHz in RUN mode
and 28 MHz in HSRUN mode.
In Sequential Secure boot, Application shall boot only after successful completion of
Secure boot. And, Application can actuate any command without bothering for
FCSESTAT[BSY] flag. However, in Strict boot mode, the chip will not boot at all and
will remain stuck in reset, if secure boot fails.

5.3 Security use case examples

5.3.1 Secure boot: check bootloader for integrity and

authenticity
The following diagram illustrates a use case for detecting and preventing bootloader
modification.

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Security use case examples

Figure 5-1. Bootloader integrity and authencity

The MAC protects against modification of the bootloader and depends on the (secret)
boot key.
Only if the calculated MAC value matches the stored boot MAC value: a successful
secure boot occurs, and keys become unlocked for further use.

5.3.2 Chain of trust: check flash memory for integrity and

authenticity
In this use case:
• The bootloader is protected by the secure boot process.
• MACs stored in the bootloader provide integrity and authenticity of the related parts
in flash memory.
• Part-by-part checking of flash memory ensures each part's integrity and authenticity
before executing it. Critical parts of flash memory (for example, MCU
configuration/IRQ table) are checked and then executed as soon as possible.

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 Chapter 5 Security Overview

Figure 5-2. Flash memory integrity and authenticity

5.3.3 Secure communication

This use case demonstrates how to prevent illegal messages sent by ECUs.
• Random number generation and checking protect against replay attacks.
• Encryption protects against eavesdropping.
• Random number generation/checking and encryption ensure data integrity and
authenticity.

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Security use case examples

Figure 5-3. Secure communication

5.3.4 Component protection

The replacement or modification of ECU <n> will change its unique ID and/or keys. This
use case shows how both changes are detected.

Figure 5-4. Component protection

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 Chapter 5 Security Overview

5.3.5 Message-authentication example

This use case consists of an Rx-CAN message authentication scenario:
1. CAN data stored in local buffer
2. FlexCAN triggers interrupt to core/DMA
3. Transfer data to CSEc memory (maximum 12 CAN messages of 8 bytes + 16-byte
CMAC)
4. Trigger CSEc CMAC calculation/verification
5. CSEc triggers interrupt to core
6. Core reads processed message data

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Steps required before failure analysis

CSEc
System Memory Input Output
16 Bytes Blocks 0x06 0x00 0x01 KeyID MAC Len MSG Len
n
CMD Word Length CMD Word Length
n-1 n-1 Ver Status n-1
n-2 n-2
n-3 function n-3
n-2
n processing n
n-3 MAC time MAC

n-4
MAC

0x06 0x00 0x01 KeyID MAC Len MSG Len

19
CMD Word Length CMD Word Length
18 15 15
16 16
17 17 17
18 18
16 19 function 19
20 processing 20
15 21 time 21

14
0x06 0x00 0x01 KeyID MAC Len MSG Len
13
CMD Word Length CMD Word Length
12 8 8
9 9
10 10 10
11 11
9 12 function 12
13 processing 13
8 14 time 14

6 0x06 0x00 0x00 KeyID MAC Len MSG Len

5 CMD Word Length CMD Word Length

1 1
4 2 2
3 3
3 4 4
5 function 5
2 6 processing 6
7 time 7
1
Parameter RAM Parameter RAM

Figure 5-5. Message authentication

5.4 Steps required before failure analysis

Before returning a device to NXP for failure analysis, the user must run the
CMD_DBG_CHAL and CMD_DBG_AUTH commands and ensure that all keys stored
in NVM memory are deleted. This is a mandatory step to enable failure analysis at NXP.
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 Chapter 5 Security Overview

NOTE
If WRITE_PROTECTION flag is set for any key then the user
will be unable to delete that key with DEBUG_CHAL and
DEBUG_AUTH commands and failure analysis would not be
possible.

5.5 Security programming flow example (Secure Boot)

1. Run PGMPART to configure desired number of keys and other parameters
2. Program code section in Pflash to be checked in secure boot
3. LOAD_KEY(BOOT_MAC_KEY)
4. CMD_BOOT_DEFINE to select the flavor of boot and size of data to validate in
Pflash
Then optionally reset the part to "auto calculate" and program the BOOT_MAC or
the user loads the BOOT_MAC by external calculation.

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Security programming flow example (Secure Boot)

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Chapter 6
Safety Overview

6.1 Introduction
The S32K1xx series is developed according to ISO 26262 and has an integrated safety
concept targeting an ISO26262 ASIL-B integrity level. The following documentation
supports the integration of an S32K1xx chip into safety-related systems:
• Reference Manual (S32K1XXRM): describes the programming model and
functionality of S32K1xx chips
• Data Sheet (S32K1XX): describes S32K1xx operating conditions as well as timing
and electrical characteristics
• Safety Manual (S32K1XXSM): describes the S32K1xx safety concept and possible
safety mechanisms (integrated in S32K1xx, system-level hardware, or system-level
software) as well as measures to reduce dependent failures
• Dynamic FMEDA: inductive analysis enabling customization of system-level safety
mechanisms, including the resulting safety metrics for ISO 26262 (SPFM, LFM &
PMHF) and IEC 61508 (SFF & Beta IC Factor)
• FMEDA Report: describes the FMEDA methodology and safety mechanisms
supported in the FMEDA, including source of failure rates, failure modes, and
assumptions during the analysis
The S32K1xx series is a SafeAssure™ solution. For more information regarding
functional safety at NXP, visit http://www.nxp.com/safeassure.

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S32K1xx safety concept

Figure 6-1. Functional safety overview

6.2 S32K1xx safety concept

The S32K1xx series has an integrated safety concept targeting safety-related systems that
require an ASIL-B safety integrity level. In general, safety integrity is achieved by using
and applying S32K1xx safety features as described in the Safety Manual.
The following diagram provides an overview of integrated S32K1xx architecture and
safety features.

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 Chapter 6 Safety Overview

Arm Cortex NVIC AWIC Clock Generation

Async M0+ / M4F Core Power
LPO SIRC FIRC supply
trace TPIU PPB ITM 8 MHz SOSC
port 128 kHz 48 MHz monitoring
Core FPU FPB 4-40 MHz 8-40 MHz
JTAG &
self test serial SWJ-DP AHB-AP Clock
wire DSP DWT monitoring

DCODE

System
ICODE
SPLL

Main
SRAM2 Mux DMA
mux
System MPU1

ECC on Upper
SRAM Region

Lower
Region eDMA TCD
512B
Code Cache

ENET
M0 M1 M2 M3
S1 S2 Crossbar switch (AXBS-Lite) S3 S0 System
memory
System MPU1 System MPU1 protection
unit
Mux iahb_gasket

Flash memory
GPIO controller
QuadSPI

Peripheral FlexRAM/
Peripheral bus controller SRAM
protection

Internal SW Low power

watchdog WDOG 12-bit ADC LPI2C FlexIO SAI
timer
Code flash Data flash ECC on
External SW CMP memory memory flash
watchdog EWM 8-bit DAC LPUART FlexCAN FlexTimer LPIT memory

QuadSPI CSEc
CRC CRC TRGMUX LPSPI PDB RTC

Register Diversity of digital Diversity of

protection analog signal paths communication channels

1: On this device, NXP’s system MPU implements the safety mechanisms to Key: Device architectural IP on all
prevent masters from accessing restricted memory regions. This system MPU S32K devices.
provides memory protection at the level of the Crossbar Switch. Each Crossbar Peripherals present on all
master (Core, DMA, Ethernet) can be assigned different access rights to each S32K devices.
protected memory region. The Arm M4 core version in this family does not
integrate the Arm Core MPU, which would concurrently monitor only core-initiated Peripherals present on selected
memory accesses. In this document, the term MPU refers to NXP’s system MPU.
S32K devices. See section
Feature Comparison.
2: See Memories and Memory Interfaces chapter: On-chip SRAM sizes table for Device specific sizes

Figure 6-2. S32K1xx safety block diagram

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S32K1xx safety concept

6.2.1 Cortex-M4/M0+ Structural Core Self Test (SCST)

Cortex-M4/M0+ Structural Core Self Test (SCST) is a software product from NXP. It
was developed for detecting hardware permanent faults in a core by executing machine
opcodes with a fixed set of operands and comparing their execution results. This library
is considered a Safety Element out of context and was developed according to ASIL-B.
The SCST delivery contains the SCST library, a quality package, and a safety package.
• The quality package contains code coverage analysis, a MISRA report, a software
requirements specification, and a Test Specification.
• The safety package consists of the SCST fault coverage estimation, the Safety
Analysis and Concept, and the SCST Safety Manual.
The Safety Manual for Structural Core Self Test Library contains a list of
recommendations and assumptions that should be fulfilled and verified by a user for the
proper use of the SCST library for a Cortex-M4/M0+ core.

6.2.2 ECC on RAM and flash memory

Error correcting codes are used to protect transfers from a CPU core to flash memory and
from a CPU core to system memory. Error Correcting Code (ECC) is implemented with
Single-Error Correction, Double-Error Detection (SECDED).
References:
• Functional description: in this Reference Manual, see MCM, EIM, ERM, LMEM,
and FTFC
• ECC on RAM and flash memory in safety concept: see Safety Manual

6.2.3 Power supply monitoring

S32K1xx includes a system for managing low-voltage conditions to protect memory
contents and control MCU system states during supply voltage variations.
• Power-on reset (POR)
• Low-voltage detection (LVD)
References:
• Functional description: in this Reference Manual, see Power Management
• Power supply monitoring in safety concept: see Safety Manual chapter

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 Chapter 6 Safety Overview

6.2.4 Clock monitoring

Clocks in the S32K1xx are supervised by clock monitor units.
• System PLL clock monitor1 : monitors the loss of PLL clock
• System Oscillator (SOSC) clock monitor 2 : monitors the loss of oscillator clock
• CMU monitor3 FIRC clock for:
• Loss of clock
• Out of high and low range
References:
• Functional description: in this Reference Manual, see Clock Distribution
• Clock monitoring in safety concept: see Safety Manual chapter

6.2.5 Temporal protection

In a safety concept, watchdog timers provide temporal protection and monitor the
operation of the system by expecting periodic communication from the software.
S32K1xx offers two watchdog timers:
• Watchdog timer (WDOG) 4 : An independent timer that is available for system use. It
provides a safety feature to ensure that software is executing as planned and that the
CPU is not stuck in an infinite loop.
• External Watchdog Monitor (EWM) 5 : A redundant watchdog system for safety. The
EWM provides an independent output signal. It does not reset the MCU and
peripherals.
References:
• Functional description: in this Reference Manual, see WDOG and EWM
• Temporal protection in safety concept: see Safety Manual chapter

6.2.6 Operational interference protection

S32K1xx provides safety mechanisms to:

1. Available in S32K14x variants only

2. Available in all S32K1xx variants
3. Available in S32K11x only
4. Available in all S32K1xx variants
5. Available in S32K14x variants only

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S32K1xx safety concept

• prevent non-safety masters from interfering with the operation of the Safety Core
• manage the concurrent execution of software with different (lower) ASIL
A hierarchical memory protection scheme, which includes the following, protects against
interference:
• System Memory Protection Unit (MPU)
• Peripheral Bridge (AIPS-Lite)
• Register protection

6.2.6.1 System Memory Protection Unit (MPU)

For ASIL-B applications, the system Memory Protection Unit (MPU) is used for
execution control. It assigns access rights and ensures that only authorized software tasks
can configure modules and access their allocated resources.
• The system MPU6 provides memory protection at the Crossbar Switch. It splits the
physical memory into 16 different regions.
• Each XBAR master (core, DMA, Ethernet) can be assigned different access rights to
each region.
• The system MPU can be used to prevent non-safety masters (including DMA or
Ethernet Controller) from accessing restricted memory regions.
References:
• Functional description: in this Reference Manual, see MPU
• MPU in safety concept: see Safety Manual chapter

6.2.6.2 Peripheral protection

Peripheral protection is based on the Peripheral Bridge (AIPS-Lite) module. It provides
memory protection functionality by defining bus masters' access rights to various
peripherals on the chip.
References:
• Functional description: in this Reference Manual, see AIPS-Lite
• Peripheral protection in safety concept: see Safety Manual chapter

6. On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from accessing
restricted memory regions. This system MPU provides memory protection at the level of the Crossbar Switch. Each
Crossbar master (Core, DMA, Ethernet) can be assigned different access rights to each protected memory region.
The Arm M4 core version in this family does not integrate the Arm Core MPU, which would concurrently monitor
only core-initiated memory accesses. In this document, the term MPU refers to NXP’s system MPU.

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 Chapter 6 Safety Overview

6.2.6.3 Register protection

S32K1xx offers register protection for safety-critical registers. This protection is based on
CPU program execution mode—User vs. Supervisor (privileged) mode—as well as
another type of access restriction based on a lock feature implemented for certain
registers. The lock-based access restriction inhibits a register update until the next system
reset or requires a special key to unlock access.
References:
• Functional description: in this Reference Manual, see notes about register protection
features for a specific register or a group of registers in the register-description
sections for SIM, SCG, ERM, RCM, MSCM, and others
• Register protection in safety concept: see Safety Manual

6.2.7 CRC
The CRC unit supports the detection of accidental alteration of data in memory or
configuration registers by calculating its CRC signature and comparing it to a previously
calculated CRC. The CRC module can also detect erroneous corruption of data during
transmission or storage.
References:
• Functional description: in this Reference Manual, see CRC
• CRC in safety concept: see Safety Manual chapter

6.2.8 Diversity of system resources

Features that are relevant to functional safety usually have redundant support in the
system. S32K1xx offers a diversity of system resources to provide this support.
• Digital inputs can be replicated to acquire safety-critical inputs redundantly
• Safety-critical digital outputs can always be written redundantly or in combination
with a read-back operation
• Analog inputs can operate in oversampling mode to detect transient faults affecting
the ADC channel, and two ADC units can acquire and digitize redundant copies of
an analog signal connected to a safety-relevant signal
• For cases of communication-channel redundancy for safety reasons, S32K1xx offers
redundant instances of communication peripherals:
• Synchronous Serial Communication Controller (LPSPI) modules

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S32K1xx safety concept

• FlexIO module: capable of supporting a wide range of protocols (UART, I2C,

SPI, I2S) and PWM/waveform generation
• UART modules: support UART and LIN communication
References:
• Functional description: in this Reference Manual, see SIM, LPSPI, LPI2C, FlexIO,
and LPUART
• Diversity of system resources in safety concept: see Safety Manual

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Chapter 7
CM4 Overview

7.1 Arm Cortex-M4F core configuration

This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by Arm and can be found at arm.com.

Debug Interrupts

Crossbar Arm Cortex-M4 PPB

PPB
switch core modules

Figure 7-1. Core configuration

Table 7-1. Reference links to related information

Topic Related module Reference
Full description Arm Cortex-M4F core Arm Cortex-M4F Technical Reference Manual
— ARM Cortex-M4 ARM Cortex-M4 Devices Generic User Guide
Devices Generic User
Guide
System memory map — See the S32K1xx_memory_map.xlsx attached to this document.
Clocking — Clock distribution
Power management — Power management
System/instruction/data Crossbar switch Crossbar switch
bus module
Debug IEEE 1149.1 JTAG Debug
Serial Wire Debug
(SWD)
Arm Real-Time Trace
Interface

Table continues on the next page...

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Arm Cortex-M4F core configuration

Table 7-1. Reference links to related information (continued)

Topic Related module Reference
Interrupts Nested Vectored NVIC
Interrupt Controller
(NVIC)
Private Peripheral Bus Miscellaneous Control MCM
(PPB) module Module (MCM)
Private Peripheral Bus Single-precision floating FPU
(PPB) module point unit (FPU)

7.1.1 Buses, interconnects, and interfaces

The Arm Cortex-M4 core has four buses as described in the following table.
Table 7-2. Arm core buses
Bus name Description
Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is
connected to the crossbar switch via a single master port.
Data code (DCODE) bus
System bus The system bus is connected to a separate master port on the crossbar.
Private peripheral (PPB) bus The PPB provides access to these modules:
• Arm modules such as the NVIC, ITM, DWT, FBP, and ROM table
• NXP Miscellaneous Control Module (MCM)

7.1.2 System Tick Timer

The System Tick Timer's clock source is always the core clock, CORE_CLK. This results
in the following:
• The CLKSOURCE bit in SysTick Control and Status register is always set to select
the core clock.
• Because the timing reference (CORE_CLK) is a variable frequency, the TENMS bit
in the SysTick Calibration Value Register is always zero.
• The NOREF bit in SysTick Calibration Value Register is always set, implying that
CORE_CLK is the only available source of reference timing.

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 Chapter 7 CM4 Overview

7.1.3 Debug facilities

This chip has extensive debug capabilities including run control and tracing capabilities.
This is a standard Arm debug port that supports JTAG and SWD interfaces.

7.1.4 Caches
This device includes one 4 KB code cache to minimize the performance impact of
memory access latencies. The code cache exists on the I/D bus, and there is no cache on
the system bus.
Features of the cache are:
• 2-way set associative
• 4 word lines
• Lines can be individually flushed
• Entire cache can be flushed at once

7.1.4.1 Control
For control purposes, the cache can be in one of these states:
1. Write Back / Write Allocate (WBWA)
2. Write Through
3. No cache
For each defined region there will be 2 bits allocated on the control register (see
PCCRMR that determines the cache state for the memory region associated with this
section. The user can only "lower" the cache attribute, given the fixed relationship of
WBWA > WT > NC - so, you can demote a WBWA region to either WT or NC, you can
demote a WT space to NC. In order to change the state upwards a system reset is
required.
NOTE
See LMEM for the cache reset states.

7.1.5 Core privilege levels

The Arm documentation uses different terms than this document to distinguish between
privilege levels.

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Nested Vectored Interrupt Controller (NVIC) Configuration

Table 7-3. Terms used

If you see this term... it also means this term...
Privileged Supervisor
Unprivileged or user User

7.2 Nested Vectored Interrupt Controller (NVIC)

Configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by Arm and can be found at arm.com.
Interrupts
Module

Arm PPB
Nested Vectored
Module
Cortex-M4 Interrupt Controller
core (NVIC)
Module

Figure 7-2. NVIC configuration

Table 7-4. Reference links to related information

Topic Related module Reference
Full description Nested Vectored Arm Cortex-M4F Technical Reference Manual - Nested Vectored Interrupt
Interrupt Controller Controller
(NVIC)
System memory map — Refer to the S32K1xx_memory_map.xlsx attached to this document.
Clocking — Clock distribution
Power management — Power management
Private Peripheral Bus Arm Cortex-M4 core Arm Cortex-M4F Technical Reference Manual - Private Peripheral Bus
(PPB) (PPB)

7.2.1 Interrupt priority levels

This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source
in the IPR registers contains 4 bits. For example, the IPR0 diagram is shown below.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IRQ3 IRQ2 IRQ1 IRQ0
W

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 Chapter 7 CM4 Overview

7.2.2 Non-maskable interrupt

The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin on which the NMI signal is multiplexed must be configured for the NMI function
in order to generate the non-maskable interrupt request.
See IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual
for details on NMI pad.

7.2.3 Determining the bitfield and register location for

configuring a particular interrupt
Suppose you need to configure the low-power timer (LPTMR) interrupt. The following
table is an excerpt of the LPTMR row from the file
'S32K1xx_DMA_INT_mapping.xlsm' attached to this Reference Manual.
Table 7-6. LPTMR interrupt vector assignment
Address Vector IRQ1 NVIC non-IPR NVIC IPR register Source module
register number2 number3
0x0000_0128 74 58 1 14 Low Power Timer

1. Indicates the NVIC's interrupt source number.

2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this
value is: IRQ div 32
3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4

The NVIC registers you would use to configure the interrupt are:
• NVICISER1
• NVICICER1
• NVICISPR1
• NVICICPR1
• NVICIABR1
• NVICIPR14
To determine the particular IRQ's bitfield location within these particular registers:
• NVICISER1, NVICICER1, NVICISPR1, NVICICPR1, NVICIABR1 bit location =
IRQ mod 32 = 26
• NVICIPR14 bitfield starting location = 8 × (IRQ mod 4) + 4 = 20
Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR14
bitfield range is 20-23

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Asynchronous Wake-up Interrupt Controller (AWIC) Configuration

Therefore, the following bitfield locations are used to configure the LPTMR interrupts:
• NVICISER1[26]
• NVICICER1[26]
• NVICISPR1[26]
• NVICICPR1[26]
• NVICIABR1[26]
• NVICIPR14[23:20]

7.3 Asynchronous Wake-up Interrupt Controller (AWIC)

Configuration
Clock logic

Wake-up
requests

Asynchronous
Nested vectored Module
interrupt controller Wake-up Interrupt
(NVIC) Controller (AWIC)
Module

Figure 7-3. Asynchronous Wake-up Interrupt Controller configuration

Table 7-7. Reference links to related information

Topic Related module Reference
System memory map — Refer to the S32K1xx_memory_map.xlsx attached to Reference Manual
for details.
Clocking — Clock distribution
Power management — Power management
Nested Vectored — NVIC
Interrupt Controller
(NVIC)
Wake-up requests — AWIC wake-up sources

7.3.1 Wake-up sources

Table 7-8. AWIC stop and VLPS wake-up sources
Wake-up source Description
Available system resets RESET pin, WDOG, JTAG

Table continues on the next page...

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 Chapter 7 CM4 Overview

Table 7-8. AWIC stop and VLPS wake-up sources (continued)

Wake-up source Description
Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system
ADCx (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
CMP (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
LPI2C0 (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
LPUART (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3)Functional in VLPS mode with
SIRC as clock source
LPSPI (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
LPTMR0 (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
RTC (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) RTC running in VLPS from
either LPO or RTC_CLKIN. Wakeup from alarm interrupt
CAN PNET is supported in STOP1/2 modes and will cause wake up. Only CAN0 supports PNET
feature.
NMI Non-maskable interrupt
WDOG (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
FlexIO (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
LPIT (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source.
EWM Module off in STOP1 and VLPS. Can cause wakeup through sync Interrupt in STOP2.
CRC Module off in STOP1 and VLPS. Can cause wakeup through sync Interrupt in STOP2.
SCG (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2

7.4 FPU configuration

This section summarizes how the module has been configured in the chip.
Arm Cortex M4

PPB
FPU
core

transfers

Figure 7-4. FPU configuration

Table 7-9. Reference links to related information

Topic Related module Reference
Full description FPU Arm Cortex-M4 Technical Reference Manual - Floating-Point Unit

Table continues on the next page...

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JTAG controller configuration

Table 7-9. Reference links to related information (continued)

Topic Related module Reference
System memory map — Refer to the S32K1xx_memory_map.xlsx attached to this document.
Clocking — Clock Distribution
Power Management — Power Management
Transfers Arm Cortex M4 core Arm Cortex-M4 Technical Reference Manual - Private Peripheral Bus
Private Peripheral Bus
(PPB)

7.5 JTAG controller configuration

This section summarizes how the module has been configured in the chip.

Signal
JTAG controller multiplexing

Figure 7-5. JTAG controller configuration

Table 7-10. Reference links to related information

Topic Related module Reference
Full description JTAGC JTAGC
Signal multiplexing Port control See IO Signal Description Input Multiplexing sheet(s) attached to the
Reference Manual attached to this document for details.

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Chapter 8
CM0+ Overview

8.1 Arm Cortex-M0+ core introduction

The enhanced Arm Cortex M0+ is the member of the Cortex-M Series of processors
targeting microcontroller cores focused on very cost sensitive, low power applications. It
has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also
has hardware debug functionality including support for simple program trace capability.
The processor supports the Armv6-M instruction set (Thumb) architecture including all
but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It is upward
compatible with other Cortex-M profile processors.
Table 8-1. Reference links to related information
Topic Related module Reference
Full description Arm Cortex-M0+ core Arm Cortex-M0+ Technical Reference Manual
— ARM Cortex-M0 ARM Cortex-M0 Devices Generic User Guide
Devices Generic User
Guide
System memory map — See the S32K1xx_memory_map.xlsx attached to this document.
Clocking — Clock distribution
Power management — Power management
System/instruction/data Crossbar switch Crossbar switch
bus module
Debug IEEE 1149.1 JTAG Debug
Serial Wire Debug
(SWD)
MTB
Arm Real-Time Trace
Interface
Interrupts Nested Vectored NVIC
Interrupt Controller
(NVIC)

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Arm Cortex-M0+ core introduction

8.1.1 Buses, interconnects, and interfaces

The Arm Cortex-M0+ core has two bus interfaces:
• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to
peripherals and all system memory, which includes flash memory and RAM
• Single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores

8.1.2 System tick timer

The CLKSOURCE field in SysTick Control and Status register selects either the core
clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS
field in the SysTick Calibration Value Register is always 0.

8.1.3 Debug facilities

This device supports standard Arm 2-pin SWD debug port.

8.1.4 Core privilege levels

The core on this device is implemented with both privileged and unprivileged levels. The
Arm documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term... it also means this term...
Privileged Supervisor
Unprivileged or user User

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8.2 Nested vectored interrupt controller (NVIC)

8.2.1 Interrupt priority levels

This device supports four priority levels for interrupts. Therefore, in the NVIC, each
source in the IPR registers contains two bits. For example, IPR0 is shown below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IRQ3 IRQ2 IRQ1 IRQ0
W

8.2.2 Non-maskable interrupt

The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin the NMI signal is multiplexed on, must be configured for the NMI function to
generate the non-maskable interrupt request. See IO Signal Description Input
Multiplexing sheet(s) attached to the Reference Manual for details on NMI pad.

8.2.3 Determining the bitfield and register location for

configuring a particular interrupt
Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the
FlexCAN row from the file 'S32K1xx_DMA_INT_mapping.xlsm' attached to this
Reference Manual.
Table 8-3. Interrupt vector assignments
Address Vector IRQ1 NVIC IPR register Source module
number2
0x0000_006C 27 11 2 FlexCAN

1. Indicates the NVIC's interrupt source number.

2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4.

• The NVIC registers you would use to configure the interrupt are:
• NVICIPR2
• To determine the particular IRQ's field location within these particular registers:
• NVICIPR2 field starting location = 8 * (IRQ mod 4) + 6 = 22

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AWIC introduction

Since the NVICIPR fields are 2-bit wide (4 priority levels), the NVICIPR2 field
range is 22–23.

Therefore, the following field locations are used to configure the FlexCAN interrupts:
• NVICIPR2[23:22]

8.3 AWIC introduction

The primary function of the AWIC block is to detect asynchronous wake-up events in
stop modes and signal to clock control logic to resume system clocking. After clock
restart, the NVIC observes the pending interrupt and performs the normal interrupt or
event processing.
Table 8-4. Reference links to related information
Topic Related module Reference
System memory map — Refer to the S32K1xx_memory_map.xlsx attached to Reference Manual
for details.
Clocking — Clock distribution
Power management — Power management
Nested Vectored — NVIC
Interrupt Controller
(NVIC)
Wake-up requests — AWIC wake-up sources

8.3.1 Wake-up sources

The device uses the following internal and external inputs to the AWIC module.
Table 8-5. AWIC stop and VLPS wake-up sources
Wake-up source Description
Available system resets RESET pin, WDOG, JTAG
Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system
ADCx (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
CMP (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
LPI2C0 (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
LPUART (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source

Table continues on the next page...

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Table 8-5. AWIC stop and VLPS wake-up sources (continued)

Wake-up source Description
LPSPI (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
LPTMR0 (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
RTC (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3 )RTC running in VLPS from
either LPO or RTC_CLKIN. Wakeup from alarm interrupt
CAN PNET is supported in STOP1/2 modes and will cause wake up. Only CAN0 supports PNET
feature.
NMI Non-maskable interrupt
WDOG (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS modes
and will cause async Interrupt for wake up
FlexIO (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2
LPIT (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 (3) Functional in VLPS mode with
SIRC as clock source
CRC Module off in STOP1 and VLPS. Can cause wakeup through sync Interrupt in STOP2.
SCG (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2

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Micro Trace Buffer (MTB)

9.1 Introduction
Microcontrollers using the Cortex-M0+ processor core include support for a CoreSight
Micro Trace Buffer to provide program trace capabilities.
The proper name for this function is the CoreSight Micro Trace Buffer for the Cortex-
M0+ Processor; in this document, it is simply abbreviated as the MTB.
The simple program trace function creates instruction address change-of-flow data
packets in a user-defined region of the system RAM. Accordingly, the system RAM
controller manages requests from two sources:
• AMBA-AHB reads and writes from the system bus
• program trace packet writes from the processor
As part of the MTB functionality, there is a MTB_DWT (Data Watchpoint and Trace)
module that allows the user to define watchpoint addresses, or optionally, an address and
data value, that when triggered, can be used to start or stop the program trace recording.

9.1.1 Overview
As shown in the main block diagram, the platform RAM (PRAM) controller connects to
two input buses:
• the crossbar slave port for system bus accesses
• a "private execution MTB port" from the core
The logical paths from the crossbar master input ports to the PRAM controller are
highlighted along with the private execution trace port from the processor core. The
private MTB port signals the instruction address information needed for the 64-bit
program trace packets written into the system RAM. The PRAM controller output
interfaces to the attached RAM array. In this document, the PRAM controller is the
MTB_RAM controller.

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The following information is taken from the ARM CoreSight Micro Trace Buffer
documentation.
"The execution trace packet consists of a pair of 32-bit words that the MTB generates
when it detects the processor PC value changes non-sequentially. A non-sequential PC
change can occur during branch instructions or during exception entry.
The processor can cause a trace packet to be generated for any instruction.
The following figure shows how the execution trace information is stored in memory as a
sequence of packets.
31 1 0
Nth destination address S Odd word address
Nth source address A Even word address

Incrementing
SRAM memory
address 31 1 0
2nd destination address S Start bit
2nd source address A
1st destination address S Odd word address
1st source address A Even word address

Atom bit

Figure 9-1. MTB execution trace storage format

The first, lower addressed, word contains the source of the branch, the address it
branched from. The value stored only records bits[31:1] of the source address, because
Thumb instructions are at least halfword aligned. The least significant bit of the value is
the A-bit. The A-bit indicates the atomic state of the processor at the time of the branch,
and can differentiate whether the branch originated from an instruction in a program, an
exception, or a PC update in Debug state. When it is zero the branch originated from an
instruction, when it is one the branch originated from an exception or PC update in
Debug state. This word is always stored at an even word location.
The second, higher addressed word contains the destination of the branch, the address it
branched to. The value stored only records bits[31:1] of the branch address. The least
significant bit of the value is the S-bit. The S-bit indicates where the trace started. An S-
bit value of 1 indicates where the first packet after the trace started and a value of 0 is
used for other packets. Because it is possible to start and stop tracing multiple times in a
trace session, the memory might contain several packets with the S-bit set to 1. This word
is always stored in the next higher word in memory, an odd word address.

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When the A-bit is set to 1, the source address field contains the architecturally-preferred
return address for the exception. For example, if an exception was caused by an SVC
instruction, then the source address field contains the address of the following instruction.
This is different from the case where the A-bit is set to 0. In this case, the source address
contains the address of the branch instruction.
For an exception return operation, two packets are generated:
• The first packet has the:
• Source address field set to the address of the instruction that causes the exception
return, BX or POP.
• Destination address field set to bits[31:1] of the EXC_RETURN value. See the
ARM v6-M Architecture Reference Manual.
• The A-bit set to 0.
• The second packet has the:
• Source address field set to bits[31:1] of the EXC_RETURN value.
• Destination address field set to the address of the instruction where execution
commences.
• A-bit set to 1."
Given the recorded change-of-flow trace packets in system RAM and the memory image
of the application, a debugger can read out the data and create an instruction-by-
instruction program trace. In keeping with the low area and power implementation cost
design targets, the MTB trace format is less efficient than other CoreSight trace modules,
for example, the ETM (Embedded Trace Macrocell). Since each branch packet is 8 bytes
in size, a 1 KB block of system RAM can contain 128 branches. Using the Dhrystone 2.1
benchmark's dynamic runtime as an example, this corresponds to about 875 instructions
per KB of trace RAM, or with a zero wait state memory, this corresponds to
approximately 1600 processor cycles per KB. This metric is obviously very sensitive to
the runtime characteristics of the user code.
The MTB_DWT function (not shown in the core platform block diagram) monitors the
processor address and data buses so that configurable watchpoints can be detected to
trigger the appropriate response in the MTB recording.

9.1.2 Features
The key features of the MTB_RAM and MTB_DWT include:
• Memory controller for system RAM and Micro Trace Buffer for program trace
packets
• Read/write capabilities for system RAM accesses, write-only for program trace
packets

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Memory map and register definition

• Supports zero wait state response to system bus accesses when no trace data is being
written
• Can buffer two AHB address phases and one data write for system RAM accesses
• Supports 64-bit program trace packets including source and destination instruction
addresses
• Program trace information in RAM available to MCU's application code or external
debugger
• Program trace watchpoint configuration accessible by MCU's application code or
debugger
• Location and size of RAM trace buffer is configured by software
• Two DWT comparators (addresses or address + data) provide programmable start/
stop recording
• CoreSight compliant debug functionality

9.1.3 Modes of operation

The MTB_RAM and MTB_DWT functions do not support any special modes of
operation. The MTB_RAM controller, as a memory-mapped device located on the
platform's slave AHB system bus, responds strictly on the basis of memory addresses for
accesses to its attached RAM array. The MTB private execution bus provides program
trace packet write information to the RAM controller. Both the MTB_RAM and
MTB_DWT modules are memory-mapped, so their programming models can be
accessed.
All functionality associated with the MTB_RAM and MTB_DWT modules resides in the
core platform's clock domain; this includes its connections with the RAM array.

9.2 Memory map and register definition

The MTB_RAM and MTB_DWT modules each support a sparsely-populated 4 KB
address space for their programming models. For each address space, there are a variety
of control and configurable registers near the base address, followed by a large unused
address space and finally a set of CoreSight registers to support dynamic determination of
the debug configuration for the device.
Accesses to the programming model follow standard ARM conventions. Taken from the
ARM CoreSight Micro Trace Buffer documentation, these are:
• Do not attempt to access reserved or unused address locations. Attempting to access
these locations can result in UNPREDICTABLE behavior.

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• The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN

reset values are not programmed prior to enabling trace.
• Unless otherwise stated in the accompanying text:
• Do not modify reserved register bits
• Ignore reserved register bits on reads
• All register bits are reset to a logic 0 by a system or power-on reset
• Use only word size, 32-bit, transactions to access all registers

9.2.1 MTB_DWT Memory Map

The MTB_DWT programming model supports a very simplified subset of the v7M debug
architecture and follows the standard ARM DWT definition.
MTB_DWT memory map
Address Width Section/
Register name Access Reset value
offset (hex) (in bits) page
0 MTB DWT Control Register (MTB_DWT_CTRL) 32 R 2F00_0000h 9.2.1.1/130
20 MTB_DWT Comparator Register (MTB_DWT_COMP0) 32 R/W 0000_0000h 9.2.1.2/131
MTB_DWT Comparator Mask Register
24 32 R/W 0000_0000h 9.2.1.3/131
(MTB_DWT_MASK0)
MTB_DWT Comparator Function Register 0
28 32 R/W 0000_0000h 9.2.1.4/132
(MTB_DWT_FCT0)
30 MTB_DWT Comparator Register (MTB_DWT_COMP1) 32 R/W 0000_0000h 9.2.1.2/131
MTB_DWT Comparator Mask Register
34 32 R/W 0000_0000h 9.2.1.3/131
(MTB_DWT_MASK1)
MTB_DWT Comparator Function Register 1
38 32 R/W 0000_0000h 9.2.1.5/134
(MTB_DWT_FCT1)
MTB_DWT Trace Buffer Control Register
200 32 R/W 2000_0000h 9.2.1.6/135
(MTB_DWT_TBCTRL)
FC8 Device Configuration Register (MTB_DWT_DEVICECFG) 32 R 0000_0000h 9.2.1.7/137
FCC Device Type Identifier Register (MTB_DWT_DEVICETYPID) 32 R 0000_0004h 9.2.1.8/137
FD0 Peripheral ID Register (MTB_DWT_PERIPHID4) 32 R Undefined 9.2.1.9/138
FD4 Peripheral ID Register (MTB_DWT_PERIPHID5) 32 R Undefined 9.2.1.9/138
FD8 Peripheral ID Register (MTB_DWT_PERIPHID6) 32 R Undefined 9.2.1.9/138
FDC Peripheral ID Register (MTB_DWT_PERIPHID7) 32 R Undefined 9.2.1.9/138
FE0 Peripheral ID Register (MTB_DWT_PERIPHID0) 32 R Undefined 9.2.1.9/138
FE4 Peripheral ID Register (MTB_DWT_PERIPHID1) 32 R Undefined 9.2.1.9/138
FE8 Peripheral ID Register (MTB_DWT_PERIPHID2) 32 R Undefined 9.2.1.9/138
FEC Peripheral ID Register (MTB_DWT_PERIPHID3) 32 R Undefined 9.2.1.9/138
9.2.1.10/
FF0 Component ID Register (MTB_DWT_COMPID0) 32 R Undefined
138
9.2.1.10/
FF4 Component ID Register (MTB_DWT_COMPID1) 32 R Undefined
138
Table continues on the next page...

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Memory map and register definition

MTB_DWT memory map (continued)

Address Width Section/
Register name Access Reset value
offset (hex) (in bits) page
9.2.1.10/
FF8 Component ID Register (MTB_DWT_COMPID2) 32 R Undefined
138
9.2.1.10/
FFC Component ID Register (MTB_DWT_COMPID3) 32 R Undefined
138

9.2.1.1 MTB DWT Control Register (MTB_DWT_CTRL)

The MTBDWT_CTRL register provides read-only information on the watchpoint
configuration for the MTB_DWT.
Address: 0h base + 0h offset = 0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R NUMCMP DWTCFGCTRL
W

Reset 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MTB_DWT_CTRL field descriptions

Field Description
31–28 Number of comparators
NUMCMP
The MTB_DWT implements two comparators.
DWTCFGCTRL DWT configuration controls

This field is hardwired to 0xF00_0000, disabling all the remaining DWT functionality. The specific fields
and their state are:
MTBDWT_CTRL[27] = NOTRCPKT = 1, trace sample and exception trace is not supported
MTBDWT_CTRL[26] = NOEXTTRIG = 1, external match signals are not supported
MTBDWT_CTRL[25] = NOCYCCNT = 1, cycle counter is not supported
MTBDWT_CTRL[24] = NOPRFCNT = 1, profiling counters are not supported
MTBDWT_CTRL[22] = CYCEBTENA = 0, no POSTCNT underflow packets generated
MTBDWT_CTRL[21] = FOLDEVTENA = 0, no folded instruction counter overflow events
MTBDWT_CTRL[20] = LSUEVTENA = 0, no LSU counter overflow events
MTBDWT_CTRL[19] = SLEEPEVTENA = 0, no sleep counter overflow events
MTBDWT_CTRL[18] = EXCEVTENA = 0, no exception overhead counter events
MTBDWT_CTRL[17] = CPIEVTENA = 0, no CPI counter overflow events
MTBDWT_CTRL[16] = EXCTRCENA = 0, generation of exception trace disabled
MTBDWT_CTRL[12] = PCSAMPLENA = 0, no periodic PC sample packets generated
MTBDWT_CTRL[11:10] = SYNCTAP = 0, no synchronization packets
MTBDWT_CTRL[9] = CYCTAP = 0, cycle counter is not supported
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MTB_DWT_CTRL field descriptions (continued)

Field Description
MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported
MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported
MTBDWT_CTRL[0] = CYCCNTENA = 0, cycle counter is not supported

9.2.1.2 MTB_DWT Comparator Register (MTB_DWT_COMPn)

The MTBDWT_COMPn registers provide the reference value for comparator n.
Address: 0h base + 20h offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
COMP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MTB_DWT_COMPn field descriptions

Field Description
COMP Reference value for comparison

If MTBDWT_COMP0 is used for a data value comparator and the access size is byte or halfword, the data
value must be replicated across all appropriate byte lanes of this register. For example, if the data is a
byte-sized "x" value, then COMP[31:24] = COMP[23:16] = COMP[15:8] = COMP[7:0] = "x". Likewise, if the
data is a halfword-size "y" value, then COMP[31:16] = COMP[15:0] = "y".

9.2.1.3 MTB_DWT Comparator Mask Register (MTB_DWT_MASKn)

The MTBDWT_MASKn registers define the size of the ignore mask applied to the
reference address for address range matching by comparator n. Note the format of this
mask field is different than the MTB_MASTER[MASK].
Address: 0h base + 24h offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MTB_DWT_MASKn field descriptions

Field Description
31–5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
MASK MASK
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MTB_DWT_MASKn field descriptions (continued)

Field Description
The value of the ignore mask, 0-31 bits, is applied to address range matching. MASK = 0 is used to
include all bits of the address in the comparison, except if MASK = 0 and the comparator is configured to
watch instruction fetch addresses, address bit [0] is ignored by the hardware since all fetches must be at
least halfword aligned. For MASK != 0 and regardless of watch type, address bits [x-1:0] are ignored in the
address comparison.
Using a mask means the comparator matches on a range of addresses, defined by the unmasked most
significant bits of the address, bits [31:x]. The maximum MASK value is 24, producing a 16 Mbyte mask.
An attempted write of a MASK value > 24 is limited by the MTBDWT hardware to 24.
If MTBDWT_COMP0 is used as a data value comparator, then MTBDWT_MASK0 should be programmed
to zero.

9.2.1.4 MTB_DWT Comparator Function Register 0 (MTB_DWT_FCT0)

The MTBDWT_FCTn registers control the operation of comparator n.
Address: 0h base + 28h offset = 28h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCHED

R 0 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0
DATAVMATCH

DATAVADDR0 DATAVSIZE FUNCTION

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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MTB_DWT_FCT0 field descriptions

Field Description
31–25 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Comparator match
MATCHED
If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since
the last read of the register. Reading the register clears this bit.

0 No match.
1 Match occurred.
23–20 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
19–16 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
15–12 Data Value Address 0
DATAVADDR0
Since the MTB_DWT implements two comparators, the DATAVADDR0 field is restricted to values {0,1}.
When the DATAVMATCH bit is asserted, this field defines the comparator number to use for linked
address comparison.
If MTBDWT_COMP0 is used as a data watchpoint and MTBDWT_COMP1 as an address watchpoint,
DATAVADDR0 must be set.
11–10 Data Value Size
DATAVSIZE
For data value matching, this field defines the size of the required data comparison.

00 Byte.
01 Halfword.
10 Word.
11 Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
9 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
8 Data Value Match
DATAVMATCH
When this field is 1, it enables data value comparison. For this implementation, MTBDWT_COMP0
supports address or data value comparisons; MTBDWT_COMP1 only supports address comparisons.

0 Perform address comparison.

1 Perform data value comparison.
7–4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
FUNCTION Function

Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and
MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero. For this
configuration, MTBDWT_MASK1 can be set to a non-zero value, so the combined comparators match on
a range of addresses.

0000 Disabled.
0100 Instruction fetch.
0101 Data operand read.
0110 Data operand write.
0111 Data operand (read + write).
others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.

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MTB_DWT_FCT0 field descriptions (continued)

Field Description

9.2.1.5 MTB_DWT Comparator Function Register 1 (MTB_DWT_FCT1)

The MTBDWT_FCTn registers control the operation of comparator n. Since the
MTB_DWT only supports data value comparisons on comparator 0, there are several
fields in the MTBDWT_FCT1 register that are RAZ/WI (bits 12, 11:10, 8).
Address: 0h base + 38h offset = 38h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MATCHED
R 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0

FUNCTION

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MTB_DWT_FCT1 field descriptions

Field Description
31–25 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

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MTB_DWT_FCT1 field descriptions (continued)

Field Description
24 Comparator match
MATCHED
If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since
the last read of the register. Reading the register clears this bit.

0 No match.
1 Match occurred.
23–4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
FUNCTION Function

Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and
MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero. For this
configuration, MTBDWT_MASK1 can be set to a non-zero value, so the combined comparators match on
a range of addresses.

0000 Disabled.
0100 Instruction fetch.
0101 Data operand read.
0110 Data operand write.
0111 Data operand (read + write).
others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.

9.2.1.6 MTB_DWT Trace Buffer Control Register

(MTB_DWT_TBCTRL)
The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the
actual trace buffer operation.
Recall the MTB supports starting and stopping the program trace based on the watchpoint
comparisons signaled via TSTART and TSTOP. The watchpoint comparison signals are
enabled in the MTB's control logic by setting the appropriate enable bits,
MTB_MASTER[TSTARTEN, TSTOPEN]. In the event of simultaneous assertion of
both TSTART and TSTOP, TSTART takes priority. There are two signals formed by the
MTB_DWT module and driven to the MTB_RAM controller: TSTART (trace start) and
TSTOP (trace stop). These signals can be configured using the trace watchpoints to
define programmable addresses and data values to affect the program trace recording
state.

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Address: 0h base + 200h offset = 200h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R NUMCOMP 0

Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0

ACOMP1

ACOMP0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MTB_DWT_TBCTRL field descriptions

Field Description
31–28 Number of Comparators
NUMCOMP
This read-only field specifies the number of comparators in the MTB_DWT. This implementation includes
two registers.
27–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
1 Action based on Comparator 1 match
ACOMP1
When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address compare has
triggered and the trace buffer's recording state is changed.

0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].

1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
0 Action based on Comparator 0 match
ACOMP0
When the MTBDWT_FCT0[MATCHED] is set, it indicates MTBDWT_COMP0 address compare has
triggered and the trace buffer's recording state is changed. The assertion of MTBDWT_FCT0[MATCHED]
is caused by the following conditions:
• Address match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH] = 0
• Data match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,0}
• Data match in MTBDWT_COMP0 and address match in MTBDWT_COMP1 when
MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,1}

0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].

1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].

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9.2.1.7 Device Configuration Register (MTB_DWT_DEVICECFG)

This register indicates the device configuration. It is hardwired to specific values used
during the auto-discovery process by an external debug agent.
Address: 0h base + FC8h offset = FC8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R DEVICECFG
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MTB_DWT_DEVICECFG field descriptions

Field Description
DEVICECFG DEVICECFG

Hardwired to 0x0000_0000.

9.2.1.8 Device Type Identifier Register (MTB_DWT_DEVICETYPID)

This register indicates the device type ID. It is hardwired to specific values used during
the auto-discovery process by an external debug agent.
Address: 0h base + FCCh offset = FCCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R DEVICETYPID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

MTB_DWT_DEVICETYPID field descriptions

Field Description
DEVICETYPID DEVICETYPID

Hardwired to 0x0000_0004.

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9.2.1.9 Peripheral ID Register (MTB_DWT_PERIPHIDn)

These registers indicate the peripheral IDs. They are hardwired to specific values used
during the auto-discovery process by an external debug agent. See bit field descriptions
for the reset values.
Address: 0h base + FD0h offset + (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R PERIPHID
W

Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

* Notes:
• x = Undefined at reset.

MTB_DWT_PERIPHIDn field descriptions

Field Description
PERIPHID PERIPHID

Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000.

9.2.1.10 Component ID Register (MTB_DWT_COMPIDn)

These registers indicate the component IDs. They are hardwired to specific values used
during the auto-discovery process by an external debug agent. See bit field descriptions
for the reset values.
Address: 0h base + FF0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R COMPID
W

Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

* Notes:
• x = Undefined at reset.

MTB_DWT_COMPIDn field descriptions

Field Description
COMPID Component ID

Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to

0x0000_00B1.

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MTB_DWT_COMPIDn field descriptions (continued)

Field Description

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Miscellaneous Control Module (MCM)

10.1 Chip-specific MCM information

The following table summarizes the chip-specific register reset values of this module for
each chip in the product series.
Table 10-1. MCM register reset values
Register S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
MCM_LMDR0 8104_0000 8104_0000 8504_0003 8604_0003 8704_0003 8804_0003
MCM_LMDR1 8504_2003 9604_2003 8504_2003 8604_2003 8704_2003 8804_2003
MCM_LMDR2 NA NA 8424_40A0 8424_40A0 8424_40A0 8424_40A0
MCM_PLASC 0007 0007 0007 0007 0007 000F
MCM_PLAMC 0005 0005 0007 0007 0007 000F

NOTE
• For S32K11x , LMDR information can be inferred for
SRAM size as below:
• S32K116: LMDR1[LMSZH]=0,
LMDR1[LMSZH]=0x5 , so SRAM_U size 1*(16) KB
= 16 KB. Actual size is 16 KB – 2 KB = 14 KB
• S32K118: LMDR1[LMSZH]=1,
LMDR1[LMSZH]=0x6 , so SRAM_U size 0.75*(32)
KB = 24 KB. Actual size is 24 KB – 2 KB = 22 KB
• For S32K14x variants SRAM is the tightly coupled SRAM
(TCM), while for S32K11x variants SRAM is at the
crossbar slave side.

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Address offset of LMPEIR register varies between S32K14x and S32K11x as given
below.
Table 10-2. MCM register offset
Register S32K14x offset S32K11x offset
MCM_LMPEIR 0x488 0x484

10.2 Introduction
The Miscellaneous Control Module (MCM) provides miscellaneous control functions.
NOTE
• Cache write buffer is not supported on S32K1xx.
• ECC on SRAML/MTB, FPU, and Cache is not supported
on S32K11x.

10.2.1 Features
The MCM includes the following feature:
• Program-visible information on the platform configuration and revision

10.3 Memory map/register descriptions

The memory map and register descriptions below describe the Miscellaneous Control
Module registers.
NOTE
• All registers are accessible only in Supervisor mode. User
mode accesses will generate an error.
• Writing to read-only MCM_PLASC and MCM_PLAMC
registers, would generate a bus error.
MCM memory map
Address Width Section/
Register name Access Reset value
offset (hex) (in bits) page
Crossbar Switch (AXBS) Slave Configuration
8 16 R 0007h 10.3.1/143
(MCM_PLASC)
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MCM memory map (continued)

Address Width Section/
Register name Access Reset value
offset (hex) (in bits) page
Crossbar Switch (AXBS) Master Configuration
A 16 R 0007h 10.3.2/144
(MCM_PLAMC)
C Core Platform Control Register (MCM_CPCR) 32 R/W See section 10.3.3/145
10 Interrupt Status and Control Register (MCM_ISCR) 32 R 0002_0000h 10.3.4/148
30 Process ID Register (MCM_PID) 32 R/W 0000_0000h 10.3.5/151
40 Compute Operation Control Register (MCM_CPO) 32 R/W 0000_0000h 10.3.6/152
400 Local Memory Descriptor Register (MCM_LMDR0) 32 R/W See section 10.3.7/153
404 Local Memory Descriptor Register (MCM_LMDR1) 32 R/W See section 10.3.7/153
408 Local Memory Descriptor Register2 (MCM_LMDR2) 32 R/W 8424_40A0h 10.3.8/156
480 LMEM Parity and ECC Control Register (MCM_LMPECR) 32 R/W 0000_0000h 10.3.9/160
488 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR) 32 R/W 0000_0000h 10.3.10/161
490 LMEM Fault Address Register (MCM_LMFAR) 32 R 0000_0000h 10.3.11/162
494 LMEM Fault Attribute Register (MCM_LMFATR) 32 R 0000_0000h 10.3.12/163
4A0 LMEM Fault Data High Register (MCM_LMFDHR) 32 R 0000_0000h 10.3.13/164
4A4 LMEM Fault Data Low Register (MCM_LMFDLR) 32 R 0000_0000h 10.3.14/164

10.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)

PLASC is a 16-bit read-only register identifying the presence/absence of bus slave

connections to the device’s crossbar switch.
Address: 0h base + 8h offset = 8h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read 0 ASC

Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

MCM_PLASC field descriptions

Field Description
15–8 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's
slave input port.

0 A bus slave connection to AXBS input port n is absent

1 A bus slave connection to AXBS input port n is present

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10.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)

PLAMC is a 16-bit read-only register identifying the presence/absence of bus master

connections to the device's crossbar switch.
Address: 0h base + Ah offset = Ah

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read 0 AMC

Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

MCM_PLAMC field descriptions

Field Description
15–8 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input
port.

0 A bus master connection to AXBS input port n is absent

1 A bus master connection to AXBS input port n is present

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10.3.3 Core Platform Control Register (MCM_CPCR)

CPCR defines the arbitration and protection schemes for the two system RAM arrays.
Address: 0h base + Ch offset = Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 SRAMUWP
SRAMLWP
Reserved

SRAMLAP SRAMUAP Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AXBS_HLT_REQ
PBRIDGE_IDLE

FMC_PF_IDLE

AXBS_HLTD
HLT_FSM_
R
ST

Reserved
CBR
Reserved Reserved
R

Reset 0 0 0 0 0 0 0 0 0 x* 0 x* 0 0 0 0

* Notes:
• x = Undefined at reset.

MCM_CPCR field descriptions

Field Description
31 This field is reserved.
Reserved
30 SRAM_L Write Protect
SRAMLWP
When this field is set, writes to SRAM_L array generate a bus error.

NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
29–28 SRAM_L Arbitration Priority
SRAMLAP
Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the
SRAM_L array.

NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.

00 Round robin
01 Special round robin (favors SRAM backdoor accesses over the processor)
10 Fixed priority. Processor has highest, backdoor has lowest
11 Fixed priority. Backdoor has highest, processor has lowest

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MCM_CPCR field descriptions (continued)

Field Description
27 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
26 SRAM_U Write Protect
SRAMUWP
When this field is set, writes to SRAM_U array generate a bus error.

NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
25–24 SRAM_U Arbitration Priority
SRAMUAP
Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the
SRAM_U array.

NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.

00 Round robin
01 Special round robin (favors SRAM backdoor accesses over the processor)
10 Fixed priority. Processor has highest, backdoor has lowest
11 Fixed priority. Backdoor has highest, processor has lowest
23–10 This field is reserved.
Reserved
9 Crossbar Round-robin Arbitration Enable
CBRR
Configures the crossbar slave ports to fixed-priority or round-robin arbitration.

NOTE: Highly recommended to configure this bit field to round-robin mode before configuring any other
master, for example: DMA, ENET etc., as fixed arbitration may generate stalls or under runs on
low priority master.

0 Fixed-priority arbitration
1 Round-robin arbitration
8–7 This field is reserved.
Reserved
6 Peripheral Bridge Idle
PBRIDGE_IDLE
This field indicates if the Peripheral Bridge is idle.

0 PBRIDGE is not idle

1 PBRIDGE is currently idle
5 This field is reserved.
Reserved
4 Flash Memory Controller Program Flash Idle
FMC_PF_IDLE
This field indicates if the program portion of the flash memory is idle.

0 FMC program flash is not idle

1 FMC program flash is currently idle
3 AXBS Halted
AXBS_HLTD
This field indicates if AXBS is in a halted state.

0 AXBS is not currently halted

1 AXBS is currently halted

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MCM_CPCR field descriptions (continued)

Field Description
2 AXBS Halt Request
AXBS_HLT_REQ
This field indicates if AXBS has received a halt request.

0 AXBS is not receiving halt request

1 AXBS is receiving halt request
HLT_FSM_ST AXBS Halt State Machine Status

This field indicates the state of an AXBS halt.

00 Waiting for request

01 Waiting for platform idle
11 Platform stalled
10 Unused state

10.3.4 Interrupt Status and Control Register (MCM_ISCR)

ISCR defines the configuration and reports status for a number of core-related interrupt
exception conditions. It includes the enable and status fields associated with the core’s
floating-point exceptions and the bus errors associated with the core’s cache write buffer.
The individual event indicators are first qualified with their exception enables and then
logically summed to form an interrupt request sent to the core’s NVIC.
Bits 15-8 are read-only indicator flags based on the processor’s FPSCR. Attempted writes
to these fields are ignored. After the flags are set, they remain asserted until software
clears the corresponding FPSCR field.
NOTE
This register is Reserved for S32K11x variants.
Address: 0h base + 10h offset = 10h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 1 0
Reserved
FOFCE
FUFCE

FDZCE

FIOCE
FIDCE

FIXCE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
FOFC
FUFC

FDZC

FIOC
FIDC

FIXC
R 0 0 0

W w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCM_ISCR field descriptions

Field Description
31 FPU Input Denormal Interrupt Enable
FIDCE
0 Disable interrupt
1 Enable interrupt
30–29 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
28 FPU Inexact Interrupt Enable
FIXCE
0 Disable interrupt
1 Enable interrupt
27 FPU Underflow Interrupt Enable
FUFCE
0 Disable interrupt
1 Enable interrupt
26 FPU Overflow Interrupt Enable
FOFCE
0 Disable interrupt
1 Enable interrupt
25 FPU Divide-by-Zero Interrupt Enable
FDZCE
0 Disable interrupt
1 Enable interrupt
24 FPU Invalid Operation Interrupt Enable
FIOCE
0 Disable interrupt
1 Enable interrupt
23–21 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
20 This field is reserved.
Reserved
19–18 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

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MCM_ISCR field descriptions (continued)

Field Description
17 This field is reserved.
Reserved This read-only field is reserved and always has the value 1.
16 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
15 FPU Input Denormal Interrupt Status
FIDC
This field is a copy of the core’s FPSCR[IDC] field and signals input denormalized number has been
detected in the processor’s FPU. After the field is set, it remains set until software clears FPSCR[IDC].

0 No interrupt
1 Interrupt occurred
14–13 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
12 FPU Inexact Interrupt Status
FIXC
This field is a copy of the core’s FPSCR[IXC] field and signals an inexact number has been detected in the
processor’s FPU. Once set, this field remains set until software clears FPSCR[IXC].

0 No interrupt
1 Interrupt occurred
11 FPU Underflow Interrupt Status
FUFC
This field is a copy of the core’s FPSCR[UFC] field and signals an underflow has been detected in the
processor’s FPU. After this field is set, it remains set until software clears FPSCR[UFC].

0 No interrupt
1 Interrupt occurred
10 FPU Overflow Interrupt Status
FOFC
This field is a copy of the core’s FPSCR[OFC] field and signals an overflow has been detected in the
processor’s FPU. After this field is set, it remains set until software clears FPSCR[OFC].

0 No interrupt
1 Interrupt occurred
9 FPU Divide-by-Zero Interrupt Status
FDZC
This field is a copy of the core’s FPSCR[DZC] field and signals a divide by zero has been detected in the
processor’s FPU. After this field is set, it remains set until software clears FPSCR[DZC].

0 No interrupt
1 Interrupt occurred
8 FPU Invalid Operation Interrupt Status
FIOC
This field is a copy of the core’s FPSCR[IOC] field and signals an illegal operation has been detected in
the processor’s FPU. After this field is set, it remains set until software clears FPSCR[IOC].

0 No interrupt
1 Interrupt occurred
7–5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

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MCM_ISCR field descriptions (continued)

Field Description
4 This field is reserved.
Reserved
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.

10.3.5 Process ID Register (MCM_PID)

This register drives the M0_PID and M1_PID values in the Memory Protection Unit
(MPU). System software loads this register before passing control to a given user mode
process. If the PID of the process does not match the value in this register, a bus error
occurs. See the MPU chapter for more details.
Address: 0h base + 30h offset = 30h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 PID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCM_PID field descriptions

Field Description
31–8 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
PID M0_PID and M1_PID for MPU

Drives the M0_PID and M1_PID values in the MPU.

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10.3.6 Compute Operation Control Register (MCM_CPO)

This register controls the compute operation.
Address: 0h base + 40h offset = 40h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CPOACK
R 0

CPOREQ
CPOWOI
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCM_CPO field descriptions

Field Description
31–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2 Compute Operation Wakeup On Interrupt
CPOWOI
0 No effect.
1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
1 Compute Operation Acknowledge
CPOACK
0 Compute operation entry has not completed or compute operation exit has completed.
1 Compute operation entry has completed or compute operation exit has not completed.
0 Compute Operation Request
CPOREQ
This field is auto-cleared by vector fetching if CPOWOI = 1.
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MCM_CPO field descriptions (continued)

Field Description
0 Request is cleared.
1 Request Compute Operation.

10.3.7 Local Memory Descriptor Register (MCM_LMDRn)

The LMDRn registers mapping to the LMEMs is as follows:
• LMDR0: SRAM_L
• LMDR1: SRAM_U
This section of the programming model is an array of 32-bit generic on-chip memory
descriptor registers that provide static information on the attached memories as well as
configurable controls (where appropriate).
Privileged 32-bit reads from a processor core or the debugger return the appropriate
processor information. Reads from any other bus master return all zeroes. Privileged
writes from a processor core or the debugger to writeable registers update the appropriate
fields. Privileged writes from other bus masters are ignored. Attempted user mode
accesses or any access with a size other than 32 bits are terminated with an error.

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Address: 0h base + 400h offset + (4d × i), where i=0d to 1d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

R V LMSZH LMSZ WY DPW

Reserved

LOCK
W

Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R MT
Reserved

Reserved Reserved CF0

Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

* Notes:

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• The reset values are different for the individual LMDR registers. LMDR0: 0x8804_0003; LMDR1: 0x8804_2003. x =
Undefined at reset.

MCM_LMDRn field descriptions

Field Description
31 Local Memory Valid
V
This field defines the validity (presence) of the local memory.

0 LMEMn is not present.

1 LMEMn is present.
30 This field is reserved.
Reserved
29 This field is reserved.
Reserved
28 LMEM Size Hole
LMSZH
For local memories that are not fully populated, that is, include a memory hole in the upper 25% of the
address range, this field is used.

0 LMEMn is a power-of-2 capacity.

1 LMEMn is not a power-of-2, with a capacity is 0.75 × LMSZ.
27–24 LMEM Size
LMSZ
This field provides an encoded value of the local memory size. The capacity of the memory is expressed
as Size [bytes] = 2(9+LMSZ) where LMSZ is non-zero; a LMSZ = 0 indicates the memory is not present.

0000 no LMEMn (0 KB)

0001 1 KB LMEMn
0010 2 KB LMEMn
0011 4 KB LMEMn
0100 8 KB LMEMn
0101 16 KB LMEMn
0110 32 KB LMEMn
0111 64 KB LMEMn
1000 128 KB LMEMn
1001 256 KB LMEMn
1010 512 KB LMEMn
1011 1024 KB LMEMn
1100 2048 KB LMEMn
1101 4096 KB LMEMn
1110 8192 KB LMEMn
1111 16384 KB LMEMn
23–20 Level 1 Cache Ways
WY
0000 No Cache
0010 2-Way Set Associative
0100 4-Way Set Associative
19–17 LMEM Data Path Width. This field defines the width of the local memory.
DPW
000-001 Reserved
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MCM_LMDRn field descriptions (continued)

Field Description
010 LMEMn 32-bits wide
011 LMEMn 64-bits wide
100-111 Reserved
16 LOCK
LOCK
Lock bit.
This field provides a mechanism to lock the configuration state defined by LMDRn[7:0]. Once asserted,
attempted writes to the LMDRn[7:0] register are ignored until the next reset clears the flag. Along with
LMDRn[7:0], this bit locks itself. Once locked, only reset can clear this bit.

NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.

0 Writes to the LMDRn[7:0] are allowed.

1 Writes to the LMDRn[7:0] are ignored.
15–13 Memory Type
MT
This field defines the type of the local memory.

000 SRAM_L
001 SRAM_U
12 This field is reserved.
Reserved
11–8 This field is reserved.
Reserved
7–4 This field is reserved.
Reserved
CF0 Control Field 0
NOTE
LMDR0[CF0] bit field is Reserved and Read-Only 0 for S32K11x
variants.

This field is used for TCM ECC control functions.

• CF0[3] - Reserved
• CF0[2] - Reserved
• CF0[1] - EERC = ECC Enable Read Check
• CF0[0] - EEWG = ECC Enable Write Generation

10.3.8 Local Memory Descriptor Register2 (MCM_LMDR2)

The LMDR2 registers mapping to the LMEMs representing PC CACHE.
NOTE
This value represents the maximum available cache within the
entire family. See Figure 2-3 to view the specific amount of
cache for a particular device.

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This section of the programming model is an array of 32-bit generic on-chip memory
descriptor registers that provide static information on the attached memories as well as
configurable controls (where appropriate).
Privileged 32-bit reads from a processor core or the debugger return the appropriate
processor information. Reads from any other bus master return all zeroes. Privileged
writes from a processor core or the debugger to writeable registers update the appropriate
fields. Privileged writes from other bus masters are ignored. Attempted user mode
accesses or any access with a size other than 32 bits are terminated with an error.
Address: 0h base + 408h offset = 408h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved

LMSZH

R V LMSZ WY DPW
Reserved

LOCK
W

Reset 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0

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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R MT

Reserved Reserved CF1 Reserved

Reset 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0

MCM_LMDR2 field descriptions

Field Description
31 Local Memory Valid
V
This field defines the validity (presence) of the local memory.

0 LMEMn is not present.

1 LMEMn is present.
30 This field is reserved.
Reserved
29 This field is reserved.
Reserved
28 LMEM Size Hole
LMSZH
For local memories that are not fully populated, that is, include a memory hole in the upper 25% of the
address range, this field is used.

0 LMEMn is a power-of-2 capacity.

1 LMEMn is not a power-of-2, with a capacity is 0.75 × LMSZ.
27–24 LMEM Size
LMSZ
This field provides an encoded value of the local memory size; a LMSZ = 0 indicates the memory is not
present.

0100 4 KB LMEMn
23–20 Level 1 Cache Ways
WY
0000 No Cache
0010 2-Way Set Associative
0100 4-Way Set Associative

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MCM_LMDR2 field descriptions (continued)

Field Description
19–17 LMEM Data Path Width. This field defines the width of the local memory.
DPW
000-001 Reserved
010 LMEMn 32-bits wide
011 LMEMn 64-bits wide
100-111 Reserved
16 LOCK
LOCK
Lock bit
This field provides a mechanism to lock the configuration state defined by LMDRn[7:0]. Once asserted,
attempted writes to the LMDRn[7:0] register are ignored until the next reset clears the flag. Along with
LMDRn[7:0], this bit locks itself. Once locked, only reset can clear this bit.

NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.

0 Writes to the LMDRn[7:0] are allowed.

1 Writes to the LMDRn[7:0] are ignored.
15–13 Memory Type
MT
This field defines the type of the local memory.

010 PC Cache
12 This field is reserved.
Reserved
11–8 This field is reserved.
Reserved
7–4 Control Field 1
CF1
This field is used for cache parity control functions.
• CF1[3]-PCPFE = PC Parity Fault Enable
• CF1[2]-Reserved
• CF1[1]-PCPME = PC Parity Miss Enable
• CF1[0]-Reserved
Reserved This field is reserved.

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10.3.9 LMEM Parity and ECC Control Register (MCM_LMPECR)

Address: 0h base + 480h offset = 480h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0
ECPR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0

ERNCR
ER1BR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCM_LMPECR field descriptions

Field Description
31–21 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
20 Enable Cache Parity Reporting
ECPR

NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.

0 Reporting disabled
1 Reporting enabled
19–17 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
16 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
15–9 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
8 Enable RAM ECC 1 Bit Reporting
ER1BR
NOTE
This bit field is Reserved and Read-Only 0 for S32K11x variants. This
bit field cannot mask ECC reporting, as a result the ECC would
always be reported.

0 Reporting disabled
1 Reporting enabled
7–1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

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MCM_LMPECR field descriptions (continued)

Field Description
0 Enable RAM ECC Noncorrectable Reporting
ERNCR
NOTE
This bit field is Reserved and Read-Only 0 for S32K11x variants. This
bit field cannot mask ECC reporting, as a result the ECC would
always be reported.

0 Reporting disabled
1 Reporting enabled

10.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR)

NOTE
Writes of 1 to the error bit in LMPEIR[23:0] can clear the
interrupt flag. For S32K11x variants, MCM interrupt for ECC
is not supported and this register only captures the event.
Address: 0h base + 488h offset = 488h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R V 0 PEELOC PE
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R E1B ENC
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCM_LMPEIR field descriptions

Field Description
31 Valid Bit
V
30–29 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
28–24 Parity or ECC Error Location
PEELOC
00 Non-correctable ECC event from SRAM_L
01 Non-correctable ECC event from SRAM_U
08 1-bit correctable ECC event from SRAM_L
09 1-bit correctable ECC event from SRAM_U
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MCM_LMPEIR field descriptions (continued)

Field Description
14 PC tag parity error
15 PC data parity error
23–16 Cache Parity Error
PE

• [21] - PC Data Parity Error

• [20] - PC Tag Parity Error
• [19] - Reserved
• [18] - Reserved

NOTE: This bit field is Reserved and Read-Only 0 for S32K11x variants.
15–8 E1Bn = ECC 1-bit Error n
E1B

• PEIR[15:10] - Reserved
• PEIR[9] - 1-bit Error detected on SRAM_U
• PEIR[8] - 1-bit Error detected on SRAM_L. (This is Reserved for S32K11x variants.)
ENC ENCn = ECC Noncorrectable Error n

• PEIR[7:2] - Reserved
• PEIR[1] - Noncorrectable Error detected on SRAM_U
• PEIR[0] - Noncorrectable Error detected on SRAM_L (This is Reserved for S32K11x variants.)

10.3.11 LMEM Fault Address Register (MCM_LMFAR)

Address: 0h base + 490h offset = 490h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R EFADD
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCM_LMFAR field descriptions

Field Description
EFADD ECC Fault Address

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10.3.12 LMEM Fault Attribute Register (MCM_LMFATR)

Address: 0h base + 494h offset = 494h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVR

R 0 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEFW

R PEFMST PEFSIZE PEFPRT

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCM_LMFATR field descriptions

Field Description
31 Overrun
OVR
30 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
29–24 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
23–16 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
15–8 Parity/ECC Fault Master Number
PEFMST
7 Parity/ECC Fault Write
PEFW

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MCM_LMFATR field descriptions (continued)

Field Description
6–4 Parity/ECC Fault Master Size
PEFSIZE
000 8-bit access
001 16-bit access
010 32-bit access
011 64-bit access
1xx Reserved
PEFPRT Parity/ECC Fault Protection

• FATR[3] - Cacheable: 0=Non-cacheable, 1=Cacheable

• FATR[2] - Bufferable: 0=Non-bufferable, 1=Bufferable
• FATR[1] - Mode: 0=User mode, 1=Supervisor mode
• FATR[0] - Type: 0=I-Fetch, 1=Data

10.3.13 LMEM Fault Data High Register (MCM_LMFDHR)

Address: 0h base + 4A0h offset = 4A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R PEFDH
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCM_LMFDHR field descriptions

Field Description
PEFDH Parity or ECC Fault Data High

10.3.14 LMEM Fault Data Low Register (MCM_LMFDLR)

Address: 0h base + 4A4h offset = 4A4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R PEFDL
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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MCM_LMFDLR field descriptions

Field Description
PEFDL Parity or ECC Fault Data Low

10.4 Functional description

This section describes the functional description of MCM module.

10.4.1 Interrupts
The MCM interrupt is generated if any of the following is true:
• FPU input denormal interrupt is enabled (FIDCE) and an input is denormalized
(FIDC)
• FPU inexact interrupt is enabled (FIXCE) and a number is inexact (FIXC)
• FPU underflow interrupt is enabled (FUFCE) and an underflow occurs (FUFC)
• FPU overflow interrupt is enabled (FOFCE) and an overflow occurs (FOFC)
• FPU divide-by-zero interrupt is enabled (FDZCE) and a divide-by-zero occurs
(FDZC)
• FPU invalid operation interrupt is enabled (FIOCE) and an invalid occurs (FIOC)
• SRAM_L correctable (1-bit) ECC error
• SRAM_L uncorrectable ECC error
• SRAM_U correctable (1-bit) ECC error
• SRAM_U uncorrectable ECC error
• PC data parity error
• PC tag parity error
• Cache write buffer error
NOTE
The above interrupt is not applicable for S32K11x variants.

10.4.1.1 Determining source of the interrupt

These steps can be used to determine the exact source of the interrupt:
1. Logical AND the interrupt status flags with the corresponding interrupt enable bits:
ISCR[31:16] and ISCR[15:0].
2. Search the result for asserted bits which indicate the exact interrupt sources.

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NOTE
ECC and Parity interrupts are determined by LMPECR
(interrupt enable) and LMPEIR (interrupt source).

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System Integration Module (SIM)

11.1 Chip-specific SIM information

Some aspects of the SIM vary across the products in the S32K1xx series.

11.1.1 SIM register bitfield implementation

Not all register bitfields shown in the SIM memory map are implemented in every
S32K1xx variant. Register/ register bit field availability vary accordingly to the
availability of a module/the number of module instances present in a variant. See Figure
2-3 for details on module and instance information.
NOTE
• PLATCGC register has CGCGPIO bit field at position 5
for GPIO Clock Gating Control. This bit is available in
S32K11x variants only.

11.2 Introduction
The System Integration Module (SIM) provides system control and chip configuration
registers.

11.2.1 Features
Features of the SIM include:
• System clocking configuration
• Flash memory and system RAM size configuration
• FlexTimer clock channel and configuration

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• ADC trigger selection

• LPO clock source selection
• ENET clock control
• Flash memory configuration
• System device identification (ID)

11.3 Memory map and register definition

The SIM contains many fields for selecting the clock source and dividers for various
module clocks. See section: Clock Distribution chapter for more information, including
block diagrams and clock definitions.
NOTE
The SIM registers can only be written in supervisor mode. In
user mode, write accesses are blocked and will result in a bus
error.
NOTE
Writing to Read-Only registers may /may not generate Transfer
error.

11.3.1 SIM register descriptions

11.3.1.1 SIM Memory map

SIM base address: 4004_8000h
Offset Register Width Access Reset value
(In bits)
4h Chip Control register (CHIPCTL) 32 RW 0030_0000h
Ch FTM Option Register 0 (FTMOPT0) 32 RW 0000_0000h
10h LPO Clock Select Register (LPOCLKS) 32 RW 0000_0003h
18h ADC Options Register (ADCOPT) 32 RW 0000_0000h
1Ch FTM Option Register 1 (FTMOPT1) 32 RW 0000_0000h
20h Miscellaneous control register 0 (MISCTRL0) 32 RW 0000_0000h
24h System Device Identification Register (SDID) 32 RO Table 11-
40h Platform Clock Gating Control Register (PLATCGC) 32 RW 0000_001Fh
4Ch Flash Configuration Register 1 (FCFG1) 32 RW Table 11-

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Offset Register Width Access Reset value

(In bits)
54h Unique Identification Register High (UIDH) 32 RO Table 11-
58h Unique Identification Register Mid-High (UIDMH) 32 RO Table 11-
5Ch Unique Identification Register Mid Low (UIDML) 32 RO Table 11-
60h Unique Identification Register Low (UIDL) 32 RO Table 11-
68h System Clock Divider Register 4 (CLKDIV4) 32 RW 1000_0000h
6Ch Miscellaneous Control register 1 (MISCTRL1) 32 RW 0000_0000h

11.3.1.2 Chip Control register (CHIPCTL)

11.3.1.2.1 Offset
Register Offset
CHIPCTL 4h

11.3.1.2.2 Function
SIM_CHIPCTL contains the controls for selecting ADC COCO trigger, trace clock,
clock out source, PDB back-to-back mode, and ADC interleave channel.
NOTE
Bits 31:16 are reset on POR.

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11.3.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADC_SUPPLYEN

ADC_SUPPLY
SRAMU_RETE
SRAML_RETE
Reserved

Reserved
W

N
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADC_INTERLEAVE_EN
TRACECLK_SE

CLKOUTSEL
PDB_BB_SE

CLKOUTEN

CLKOUTDIV
Reserved

W
L

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

11.3.1.2.4 Fields
Field Function
31-24 Reserved
—
23-22 Reserved
—
21 SRAML_RETEN
SRAML_RETEN SRAML retention

NOTE: For S32K11x devices, SRAML refers to MTB RAM.

0b - SRAML contents are retained across resets
1b - No SRAML retention
20 SRAMU_RETEN
SRAMU_RETE SRAMU retention
N 0b - SRAMU contents are retained across resets
1b - No SRAMU retention
19 ADC_SUPPLYEN
ADC_SUPPLYE Enable for internal supply monitoring on ADC0 internal channel 0 (configured by selecting
N ADC0_SC1n[ADCH] as 010101b).
0b - Disable internal supply monitoring
1b - Enable internal supply monitoring
18-16 ADC_SUPPLY
ADC_SUPPLY
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Field Function
Internal supplies monitored on ADC0 internal channel 0 (configured by selecting ADC0_SC1n[ADCH] as
010101b)
000b - 5 V input VDD supply (VDD)
001b - 5 V input analog supply (VDDA)
010b - ADC Reference Supply (VREFH)
011b - 3.3 V Oscillator Regulator Output (VDD_3V)
100b - 3.3 V flash regulator output (VDD_flash_3V)
101b - 1.2 V core regulator output (VDD_LV)
110b - Reserved
111b - Reserved
15-14 Reserved
—
13 PDB back-to-back select
PDB_BB_SEL Selects ADC COCO source as pdb back-to-back mode, see section Back-to-back acknowledgement
connections for details.

NOTE: This bit field is Reserved and Read-Only Zero for S32K11x variants.
0b - PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-
back operation with ADC1 COCO[7:0]
1b - Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1.
12 Debug trace clock select
TRACECLK_SE Selects core clock or platform clock as the trace clock source.
L
NOTE: This bit field is Reserved and Read-Only Zero for S32K11x variants.
0b - Core clock
1b - Reserved
11 CLKOUT enable
CLKOUTEN NOTE: The below sequence should be followed while CLKOUT configuration:
1. Configure SIM_CHIPCTL[CLKOUTSEL]
2. Configure SIM_CHIPCTL[CLKOUTDIV]
3. Enable SIM_CHIPCTL[CLKOUTEN]

(While switching, CLKOUTEN should be first cleared and then the above sequence should be
followed)
0b - Clockout disable
1b - Clockout enable
10-8 CLKOUT Divide Ratio
CLKOUTDIV NOTE: The below sequence should be followed while CLKOUT configuration:
1. Configure SIM_CHIPCTL[CLKOUTSEL]
2. Configure SIM_CHIPCTL[CLKOUTDIV]
3. Enable SIM_CHIPCTL[CLKOUTEN]

(While switching, CLKOUTEN should be first cleared and then the above sequence should be
followed)
000b - Divide by 1
001b - Divide by 2
010b - Divide by 3
011b - Divide by 4
100b - Divide by 5
101b - Divide by 6
110b - Divide by 7
111b - Divide by 8
7-4 CLKOUT Select
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Field Function
CLKOUTSEL NOTE: The below sequence should be followed while CLKOUT configuration:
1. Configure SIM_CHIPCTL[CLKOUTSEL]
2. Configure SIM_CHIPCTL[CLKOUTDIV]
3. Enable SIM_CHIPCTL[CLKOUTEN]

(While switching, CLKOUTEN should be first cleared and then the above sequence should be
followed)
NOTE: For QuadSPI clocks, see QuadSPI clocking diagram in table 'Peripheral module clocking'
Selects the clock to output on the CLKOUT pin.
0000b - SCG CLKOUT
0001b - Reserved
0010b - SOSC DIV2 CLK
0011b - Reserved
0100b - SIRC DIV2 CLK
0101b - For S32K148: QSPI_SFIF_CLK_HYP_PREMUX: Divide by 2 clock (configured through
SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved
0110b - FIRC DIV2 CLK
0111b - HCLK
1000b - For S32K14x: SPLL DIV2 CLK For S32K11x: Reserved
1001b - BUS_CLK
1010b - LPO128K_CLK
1011b - For S32K148: QSPI_Module clock; For others: Reserved
1100b - LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]
1101b - For S32K148: QSPI_SFIF_CLK; For others: Reserved
1110b - RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]
1111b - For S32K148: QSPI_2xSFIF_CLK; For others: Reserved
3-0 ADC interleave channel enable
ADC_INTERLE Select ADC interleave pins. See section ADC Hardware Interleaved Channels for more information.
AVE_EN
NOTE: This bit field is Reserved and Read-Only Zero for S32K11x variants.
0000b - Interleaving disabled. No channel pair interleaved. Interleaved channels are individually
connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is
connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4.
PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to
ADC1_SE9.
1xxxb - PTB14 to ADC1_SE9 and ADC0_SE9
x1xxb - PTB13 to ADC1_SE8 and ADC0_SE8
xx1xb - PTB1 to ADC0_SE5 and ADC1_SE15
xxx1b - PTB0 to ADC0_SE4 and ADC1_SE14

11.3.1.3 FTM Option Register 0 (FTMOPT0)

11.3.1.3.1 Offset
Register Offset
FTMOPT0 Ch

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11.3.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
FTM3CLKSEL

FTM2CLKSEL

FTM1CLKSEL

FTM0CLKSEL

FTM7CLKSEL

FTM6CLKSEL

FTM5CLKSEL

FTM4CLKSEL
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
FTM3FLTxSEL

FTM2FLTxSEL

FTM1FLTxSEL

FTM0FLTxSEL
0

0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

11.3.1.3.3 Fields
Field Function
31-30 FTM3 External Clock Pin Select
FTM3CLKSEL Selects the external pin used to drive the FTM3 module clock.

NOTE: The selected pin must also be configured for the FTM3 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM3 external clock driven by TCLK0 pin.
01b - FTM3 external clock driven by TCLK1 pin.
10b - FTM3 external clock driven by TCLK2 pin.
11b - No clock input
29-28 FTM2 External Clock Pin Select
FTM2CLKSEL Selects the external pin used to drive the FTM2 module clock.

NOTE: The selected pin must also be configured for the FTM2 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM2 external clock driven by TCLK0 pin.
01b - FTM2 external clock driven by TCLK1 pin.
10b - FTM2 external clock driven by TCLK2 pin.
11b - No clock input
27-26 FTM1 External Clock Pin Select
FTM1CLKSEL Selects the external pin used to drive the FTM1 module clock.

NOTE: The selected pin must also be configured for the FTM1 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM1 external clock driven by TCLK0 pin.
01b - FTM1 external clock driven by TCLK1 pin.
10b - FTM1 external clock driven by TCLK2 pin.
11b - No clock input
25-24 FTM0 External Clock Pin Select
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Field Function
FTM0CLKSEL Selects the external pin used to drive the FTM0 module clock.

NOTE: The selected pin must also be configured for the FTM0 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM0 external clock driven by TCLK0 pin.
01b - FTM0 external clock driven by TCLK1 pin.
10b - FTM0 external clock driven by TCLK2 pin.
11b - No clock input
23-22 FTM7 External Clock Pin Select
FTM7CLKSEL Selects the external pin used to drive the FTM7 module clock.

NOTE: The selected pin must also be configured for the FTM7 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM7 external clock driven by TCLK0 pin.
01b - FTM7 external clock driven by TCLK1 pin.
10b - FTM7 external clock driven by TCLK2 pin.
11b - No clock input
21-20 FTM6 External Clock Pin Select
FTM6CLKSEL Selects the external pin used to drive the FTM6 module clock.

NOTE: The selected pin must also be configured for the FTM6 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM6 external clock driven by TCLK0 pin.
01b - FTM6 external clock driven by TCLK1 pin.
10b - FTM6 external clock driven by TCLK2 pin.
11b - No clock input
19-18 FTM5 External Clock Pin Select
FTM5CLKSEL Selects the external pin used to drive the FTM5 module clock.

NOTE: The selected pin must also be configured for the FTM5 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM5 external clock driven by TCLK0 pin.
01b - FTM5 external clock driven by TCLK1 pin.
10b - FTM5 external clock driven by TCLK2 pin.
11b - No clock input
17-16 FTM4 External Clock Pin Select
FTM4CLKSEL Selects the external pin used to drive the FTM4 module clock.

NOTE: The selected pin must also be configured for the FTM4 external clock function through the
appropriate Pin Control Register in the Port Control module.
00b - FTM4 external clock driven by TCLK0 pin.
01b - FTM4 external clock driven by TCLK1 pin.
10b - FTM4 external clock driven by TCLK2 pin.
11b - No clock input
15 Reserved
—
14-12 FTM3 Fault X Select
FTM3FLTxSEL Selects the source of the FTM3 fault. Every bit means one fault input, respectively.

NOTE: The pin source of the fault must be configured for FTM3 fault function through the appropriate
PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM3 SELx
corresponds to the FTM3 Fault x input.
000b - FTM3_FLTx pin
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Field Function
001b - TRGMUX_FTM3 out
11 Reserved
—
10-8 FTM2 Fault X Select
FTM2FLTxSEL Selects the source of the FTM2 fault. Every bit means one fault input, respectively.

NOTE: The pin source of the fault must be configured for FTM2 fault function through the appropriate
PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM2 SELx
corresponds to the FTM2 Fault x input.
000b - FTM2_FLTx pin
001b - TRGMUX_FTM2 out
7 Reserved
—
6-4 FTM1 Fault X Select
FTM1FLTxSEL Selects the source of the FTM1 fault. Every bit means one fault input, respectively.

NOTE: The pin source of the fault must be configured for FTM1 fault function through the appropriate
PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM1 SELx
corresponds to the FTM1 Fault x input.
000b - FTM1_FLTx pin
001b - TRGMUX_FTM1 out
3 Reserved
—
2-0 FTM0 Fault X Select
FTM0FLTxSEL Selects the source of the FTM0 fault. Every bit means one fault input, respectively.

NOTE: The pin source of the fault must be configured for FTM0 fault function through the appropriate
PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM0 SELx
corresponds to the FTM0 Fault x input.
000b - FTM0_FLTx pin
001b - TRGMUX_FTM0 out

11.3.1.4 LPO Clock Select Register (LPOCLKS)

11.3.1.4.1 Offset
Register Offset
LPOCLKS 10h

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11.3.1.4.2 Function
NOTE
The LPOCLKS register is a write-once register, and is reset
only on POR or LVD.

11.3.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
0

LPO32KCLKEN

LPO1KCLKEN
LPOCLKSEL
RTCCLKSE
W

L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

11.3.1.4.4 Fields
Field Function
31-6 Reserved
—
5-4 32 kHz clock source select
RTCCLKSEL Selects 32 kHz clock source for peripherals
00b - SOSCDIV1_CLK
01b - 32 kHz LPO_CLK
10b - 32 kHz RTC_CLKIN clock
11b - FIRCDIV1_CLK
3-2 LPO clock source select
LPOCLKSEL Selects LPO clock source for peripherals
00b - 128 kHz LPO_CLK
01b - No clock
10b - 32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK
11b - 1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK
1 32 kHz LPO_CLK enable
0b - Disable 32 kHz LPO_CLK output
LPO32KCLKEN
1b - Enable 32 kHz LPO_CLK output
0 1 kHz LPO_CLK enable
0b - Disable 1 kHz LPO_CLK output
LPO1KCLKEN
1b - Enable 1 kHz LPO_CLK output

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11.3.1.5 ADC Options Register (ADCOPT)

11.3.1.5.1 Offset
Register Offset
ADCOPT 18h

11.3.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
ADC1SWPRETRG

ADC0SWPRETRG
0

0
ADC1PRETRGSE

ADC0PRETRGSE
ADC1TRGSEL

ADC0TRGSEL
W
L

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

11.3.1.5.3 Fields
Field Function
31-16 Reserved
—
15-14 Reserved
—
13-12 ADC1 pretrigger source select
ADC1PRETRG Selects pretrigger source for ADC1.
SEL 00b - PDB pretrigger (default)
01b - TRGMUX pretrigger
10b - Software pretrigger
11b - Reserved
11-9
ADC1 software pretrigger sources
000b - Software pretrigger disabled
ADC1SWPRET
001b - Reserved (do not use)
RG
010b - Reserved (do not use)
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Field Function
011b - Reserved (do not use)
100b - Software pretrigger 0
101b - Software pretrigger 1
110b - Software pretrigger 2
111b - Software pretrigger 3
8 ADC1 trigger source select
ADC1TRGSEL Selects trigger source for ADC1.

NOTE: Each PDB supports two ADC channels, and each channel has 8 pretriggers. If needed, the
trigger of two ADC channels are OR'ed together to support up to 16 pretriggers.
0b - PDB output
1b - TRGMUX output
7-6 Reserved
—
5-4 ADC0 pretrigger source select
ADC0PRETRG Selects pretrigger source for ADC0.
SEL 00b - PDB pretrigger (default)
01b - TRGMUX pretrigger
10b - Software pretrigger
11b - Reserved
3-1 ADC0 software pretrigger sources
000b - Software pretrigger disabled
ADC0SWPRET
001b - Reserved (do not use)
RG
010b - Reserved (do not use)
011b - Reserved (do not use)
100b - Software pretrigger 0
101b - Software pretrigger 1
110b - Software pretrigger 2
111b - Software pretrigger 3
0 ADC0 trigger source select
ADC0TRGSEL Selects trigger source for ADC0.

NOTE: Each PDB supports two ADC channels, and each channel has 8 pretriggers. If needed, the
trigger of two ADC channels are OR'ed together to support up to 16 pretriggers.
0b - PDB output
1b - TRGMUX output

11.3.1.6 FTM Option Register 1 (FTMOPT1)

11.3.1.6.1 Offset
Register Offset
FTMOPT1 1Ch

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11.3.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
FTM3_OUTSEL FTM0_OUTSEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0
FTM7SYNCBIT

FTM6SYNCBIT

FTM5SYNCBIT

FTM4SYNCBIT

FTM3SYNCBIT

FTM2SYNCBIT

FTM1SYNCBIT

FTM0SYNCBIT
FTM2CH1SEL

FTM2CH0SEL

FTM1CH0SEL
FTMGLDOK

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

11.3.1.6.3 Fields
Field Function
31-24 FTM3 channel modulation select with FTM2_CH1
FTM3_OUTSEL Bits 7 to 0 of this field are for channel 7 to 0, respectively.
00000000b - No modulation with FTM2_CH1
00000001b - Modulation with FTM2_CH1
23-16 FTM0 channel modulation select with FTM1_CH1
FTM0_OUTSEL Bits 7 to 0 of this field are for channel 7 to 0, respectively.
00000000b - No modulation with FTM1_CH1
00000001b - Modulation with FTM1_CH1
15 FTM global load enable
FTMGLDOK This bit is not self-clearing. For subsequent reload operations, it should be cleared and then set.
0b - FTM Global load mechanism disabled.
1b - FTM Global load mechanism enabled
14 FTM7 Sync Bit
FTM7SYNCBIT This is used as trigger source for FTM7. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
13 FTM6 Sync Bit
FTM6SYNCBIT This is used as trigger source for FTM6. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
12 FTM5 Sync Bit
FTM5SYNCBIT This is used as trigger source for FTM5. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
11 FTM4 Sync Bit
FTM4SYNCBIT This is used as trigger source for FTM4. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
10-9 Reserved
—

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Field Function
8 FTM2 CH1 Select
FTM2CH1SEL Selects FTM2 CH1 input
0b - FTM2_CH1 input
1b - exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1
7-6 FTM2 CH0 Select
FTM2CH0SEL Selects FTM2 CH0 input
00b - FTM2_CH0 input
01b - CMP0 output
10b - Reserved
11b - Reserved
5-4 FTM1 CH0 Select
FTM1CH0SEL Selects FTM1 CH0 input
00b - FTM1_CH0 input
01b - CMP0 output
10b - Reserved
11b - Reserved
3 FTM3 Sync Bit
FTM3SYNCBIT This is used as trigger source for FTM3. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
2 FTM2 Sync Bit
FTM2SYNCBIT This is used as trigger source for FTM2. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
1 FTM1 Sync Bit
FTM1SYNCBIT This is used as trigger source for FTM1. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.
0 FTM0 Sync Bit
FTM0SYNCBIT This is used as trigger source for FTM0. See section FTM Hardware Triggers and Synchronization for
details on FTM hardware triggering.

11.3.1.7 Miscellaneous control register 0 (MISCTRL0)

11.3.1.7.1 Offset
Register Offset
MISCTRL0 20h

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11.3.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FTM7_OBE_CTRL

FTM6_OBE_CTRL

FTM5_OBE_CTRL

FTM4_OBE_CTRL

FTM3_OBE_CTRL

FTM2_OBE_CTRL

FTM1_OBE_CTRL

FTM0_OBE_CTRL
RMII_CLK_SEL

RMII_CLK_OBE
QSPI_CLK_SE
Reserved

L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W1C STOP2_MONITOR

W1C STOP1_MONITOR
FTM_GTB_SPLIT_EN

R
Reserved

Reserved

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

11.3.1.7.3 Fields
Field Function
31-27 Reserved
—
26 QSPI CLK Select bit
QSPI_CLK_SEL QSPI asynchronous clock gating enable
0b - QuadSPI internal reference clock is gated.
1b - QuadSPI internal reference clock is enabled.
25 RMII CLK Select bit
RMII_CLK_SEL Set this bit to enable SOSCDIV1_CLK as ENET RMII clock in Internal loopback mode.
24 RMII CLK OBE bit
RMII_CLK_OBE Output Buffer Enable for ENET RMII clock in internal loopback mode
23 FTM7 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
FTM7_OBE_CT
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
RL
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
22 FTM6 OBE CTRL bit
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Field Function
FTM6_OBE_CT 0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
RL channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
21 FTM5 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
FTM5_OBE_CT
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
RL
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
20 FTM4 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
FTM4_OBE_CT
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
RL
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
19 FTM3 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
FTM3_OBE_CT
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
RL
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
18 FTM2 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
FTM2_OBE_CT
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
RL
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
17 FTM1 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
FTM1_OBE_CT
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
RL
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].
16 FTM0 OBE CTRL bit
0b - The FTM channel output is put to safe state when the FTM counter is enabled and the FTM
FTM0_OBE_CT
channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and
RL
FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the
channel output is tristated.
1b - The FTM channel output state is retained when the channel is in output mode. The output
channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0,
MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].

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Field Function
15 Reserved
—
14 FTM GTB split enable/disable bit
FTM_GTB_SPLI Split time base enable/disable.
T_EN 0b - All the FTMs have a single global time-base
1b - FTM0-3 have a common time-base and others have a different common time-base. Please
refer 'FTM global time base' in FTM chapter for implementation details.
13-11 Reserved
—
10 STOP2 monitor bit
STOP2_MONIT This status bit monitors system clock status on STOP2 mode entry and can be used for monitoring
OR whether STOP2 entry was successful or aborted (In STOP2, system clock is disabled and bus clock is
enabled). This bit needs to be W1C after wakeup from STOP2 mode.

NOTE: This bit is reset on POR.

0b - System clock enabled or STOP2 entry aborted
1b - STOP2 entry successful
9 STOP1 monitor bit
STOP1_MONIT This status bit monitors bus clock status on STOP1 mode entry and can be used for monitoring whether
OR STOP1 entry was successful or aborted (In STOP1, both system and bus clocks are disabled). This bit
needs to be W1C after wakeup from STOP1 mode.

NOTE: This bit is reset on POR.

0b - Bus clock enabled or STOP1 entry aborted
1b - STOP1 entry successful
8-0 Reserved
—

11.3.1.8 System Device Identification Register (SDID)

11.3.1.8.1 Offset
Register Offset
SDID 24h

11.3.1.8.2 Function
NOTE
This register's reset value is loaded during system reset from
flash memory IFR.

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Memory map and register definition

11.3.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R GENERATION SUBSERIES DERIVATE RAMSIZE

W
Reset u u u u u u u u u u u u u u u u

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R REVID PACKAGE FEATURES

W
Reset u u u u u u u u u u u u u u u u

11.3.1.8.4 Fields
Field Function
31-28 S32K product series generation
GENERATION Specifies the generation of the S32K product series of chips. Generation for this chip is 1.
27-24 Subseries
SUBSERIES Specifies the sub-series of the chip. The value is 4 (S32K14x chip) or 1 (S32K11x chip).
23-20 Derivate
DERIVATE Specifies the derivate of the chip. The value is 8 (S32K148), 6 (S32K146), 4 (S32K144), 2 (S32K142), 8
(S32118), or 6 (S32K116).
19-16 RAM size
RAMSIZE This field specifies the total amount of system RAM available on the chip, including FlexRAM.
0000b - Reserved
0001b - Reserved
0010b - Reserved
0011b - Reserved
0100b - Reserved
0101b - Reserved
0110b - Reserved
0111b - Reserved
1000b - Reserved
1001b - Reserved
1010b - Reserved
1011b - 192 KB (S32K148), 96 KB (S32K146), Reserved (others)
1100b - Reserved
1101b - 48 KB (S32K144), Reserved (others)
1110b - Reserved
1111b - 256 KB (S32K148), 128 KB (S32K146), 64 KB (S32K144), 32 KB (S32K142), 25 KB
(S32K118), 17 KB (S32K116)
15-12 Device revision number
REVID Specifies the silicon implementation number for the chip. The value is 0 (for S32K148, S32K146,
S32K142, S32K118, and S32K116) and 1 (for S32K144).
11-8 Package
PACKAGE Specifies the available package options for the chip.
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Field Function
0000b - Reserved
0001b - 32 QFN
0010b - 48 LQFP
0011b - 64 LQFP
0100b - 100 LQFP
0101b - Reserved
0110b - 144 LQFP
0111b - 176 LQFP
1000b - 100 MAP BGA
1001b - Reserved
1010b - Reserved
1011b - Reserved
1100b - Reserved
1101b - Reserved
1110b - Reserved
1111b - Reserved
7-0 Features
FEATURES Specifies the supported features of the chip.

NOTE: • While trying to access memory map region of un-available feature with corresponding
module clock enabled through PCC CGC bit, there will not be any transfer error
termination.
• This bit field overrides the PCC.PR status for the chip.
1 Feature is present
0 Feature is not present
Each bit in this field represents the following:
• Bit 7: Security
• Bit 6: ISO CAN-FD
• Bit 5: FlexIO
• Bit 4: QuadSPI
• Bit 3: ENET
• Bit 2: ISELED
• Bit 1: SAI
• Bit 0: Reserved

11.3.1.9 Platform Clock Gating Control Register (PLATCGC)

11.3.1.9.1 Offset
Register Offset
PLATCGC 40h

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11.3.1.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
0

CGCMSCM
CGCERM

CGCMPU
CGCDMA
CGCEIM
W

Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1

11.3.1.9.3 Fields
Field Function
31-6 Reserved
—
5 Reserved
—
4 EIM Clock Gating Control
CGCEIM Controls the clock gating to the EIM.
0b - Clock disabled
1b - Clock enabled
3 ERM Clock Gating Control
CGCERM Controls the clock gating to the ERM.
0b - Clock disabled
1b - Clock enabled
2 DMA Clock Gating Control
CGCDMA Controls the clock gating to the DMA module.
0b - Clock disabled
1b - Clock enabled
1 MPU Clock Gating Control
CGCMPU Controls the clock gating to the MPU module.
0b - Clock disabled
1b - Clock enabled
0 MSCM Clock Gating Control
CGCMSCM Controls the clock gating to the MSCM.
0b - Clock disabled
1b - Clock enabled

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11.3.1.10 Flash Configuration Register 1 (FCFG1)

11.3.1.10.1 Offset
Register Offset
FCFG1 4Ch

11.3.1.10.2 Function
NOTE
The reset value of DEPART field of this register is loaded
during system reset from flash memory IFR.
NOTE
Attempted writes to this register may result in unpredictable
behavior.

11.3.1.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R Reserved Reserved 0 EEERAMSIZE

W
Reset u u u u u u u u u u u u u u u u

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEPART

Reserved

Reserved
R
0

W
Reset u u u u u u u u u u u u u u u u

11.3.1.10.4 Fields
Field Function
31-28 Reserved
—
27-24 Reserved
—
23-20 Reserved
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Memory map and register definition

Field Function
—
19-16 EEE SRAM SIZE
EEERAMSIZE EEE SRAM data size.
0000b - Reserved
0001b - Reserved
0010b - 4 KB
0011b - 2 KB
0100b - 1 KB
0101b - 512 Bytes
0110b - 256 Bytes
0111b - 128 Bytes
1000b - 64 Bytes
1001b - 32 Bytes
1111b - 0 Bytes
15-12 FlexNVM partition
DEPART Data flash memory / emulated EEPROM backup split. See DEPART field description in FTFC chapter.
11-2 Reserved
—
1 Reserved
—
0 Reserved
—

11.3.1.11 Unique Identification Register High (UIDH)

11.3.1.11.1 Offset
Register Offset
UIDH 54h

11.3.1.11.2 Function
NOTE
• UID127_96, UID95_64, UID63_32, and UID31_0 together
represents 128-bit unique identification number for this
device.
• This register's reset value is loaded during system reset
from flash memory IFR.

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11.3.1.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R UID127_96
W
Reset u u u u u u u u u u u u u u u u

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R UID127_96
W
Reset u u u u u u u u u u u u u u u u

11.3.1.11.4 Fields
Field Function
31-0 Unique Identification
UID127_96 Unique identification for the chip.

11.3.1.12 Unique Identification Register Mid-High (UIDMH)

11.3.1.12.1 Offset
Register Offset
UIDMH 58h

11.3.1.12.2 Function
NOTE
This register's reset value is loaded during system reset from
flash memory IFR.

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11.3.1.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R UID95_64
W
Reset u u u u u u u u u u u u u u u u

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R UID95_64
W
Reset u u u u u u u u u u u u u u u u

11.3.1.12.4 Fields
Field Function
31-0 Unique Identification
UID95_64 Unique identification for the chip.

11.3.1.13 Unique Identification Register Mid Low (UIDML)

11.3.1.13.1 Offset
Register Offset
UIDML 5Ch

11.3.1.13.2 Function
NOTE
This register's reset value is loaded during system reset from
flash memory IFR.

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11.3.1.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R UID63_32
W
Reset u u u u u u u u u u u u u u u u

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R UID63_32
W
Reset u u u u u u u u u u u u u u u u

11.3.1.13.4 Fields
Field Function
31-0 Unique Identification
UID63_32 Unique identification for the chip.

11.3.1.14 Unique Identification Register Low (UIDL)

11.3.1.14.1 Offset
Register Offset
UIDL 60h

11.3.1.14.2 Function
NOTE
This register's reset value is loaded during system reset from
flash memory IFR.

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11.3.1.14.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R UID31_0
W
Reset u u u u u u u u u u u u u u u u

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R UID31_0
W
Reset u u u u u u u u u u u u u u u u

11.3.1.14.4 Fields
Field Function
31-0 Unique Identification
UID31_0 Unique identification for the chip.

11.3.1.15 System Clock Divider Register 4 (CLKDIV4)

11.3.1.15.1 Offset
Register Offset
CLKDIV4 68h

11.3.1.15.2 Function
NOTE
This register is Reserved for S32K11x variants.

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11.3.1.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TRACEDIVEN
0

0
W

Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TRACEFRAC
0

TRACEDIV
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

11.3.1.15.4 Fields
Field Function
31-29 Reserved
—
28 Debug Trace Divider control
TRACEDIVEN This field controls the Debug Trace Divider.
0b - Debug trace divider disabled
1b - Debug trace divider enabled
27-4 Reserved
—
3-1 Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it
after setting TRACEDIV.
TRACEDIV
This field sets the divide value for the fractional clock divider used as a source for trace clock. The source
clock for the trace clock is set by the SIM_CHIPCTL[TRACECLK_SEL]. Divider output clock = Divider
input clock * [(TRACEFRAC+1)/(TRACEDIV+1)].

NOTE: TRACEFRAC should be ≤ TRACEDIV

0 Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear
TRACEDIVEN to disable the trace clock divide function.
TRACEFRAC
This field sets the divide value for the fractional clock divider used as a source for trace clock. The source
clock for the trace clock is set by the SIM_CHIPCTL[TRACECLK_SEL]. Divider output clock = Divider
input clock * [(TRACEFRAC+1)/(TRACEDIV+1)].

NOTE: TRACEFRAC should be ≤ TRACEDIV

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11.3.1.16 Miscellaneous Control register 1 (MISCTRL1)

11.3.1.16.1 Offset
Register Offset
MISCTRL1 6Ch

11.3.1.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
0

SW_TR
W

G
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

11.3.1.16.3 Fields
Field Function
31-1 Reserved
—
0 Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through
TRGMUX (Refer to Figure: Trigger interconnectivity).
SW_TRG

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Port Control and Interrupts (PORT)

12.1 Chip-specific PORT information

Not all pin control settings mentioned in PORT_PCRn register are configurable for all
pins. Refer 'Bits Configurable' field in 'IO Signal Table' tab of IO Signal Description
Input Multiplexing sheet(s) attached to the Reference Manual. The bits apart from 'Bit
Configurable' fields are reserved and should not be varied from the reset values.
PCR bits corresponding to reset pad are non-sticky bits and on a functional reset, reset
functionality on this pin will be resumed. Prior to entering any ALT functionality, PCR of
corresponding pad should be properly configured.
On this chip, the pullup and pulldown enables are controllable in analog or disabled pin
muxing mode (corresponding to PORT_PCRn[MUX]=3’b000). Before entering Analog
mode (ALT0 corresponding to PORT_PCRn[MUX]=3'b000 for corresponding pads for
which Analog functionality is available), PUE and PUS should be configured as 0 in
corresponding PCR register.
PORT_PCRn[PFE] is configurable for only PTA5 and PTD3. See IO Signal Description
Input Multiplexing sheet(s) attached to the Reference Manual. PFE for these should be
configured in ALT7 mode only. For other modes, PFE should be kept 0.
The corresponding PAD should be configured for disabled mode(ALT0) prior to
configuring PORT_DFER register.
Any pad configuration done in RUN/VLPR mode is retained in low power
modes(STOP1,STOP2/VLPS).
Wait mode is not supported on this device.
See Module operation in available power modes for details on available power modes.

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12.1.1 Number of PCRs

The number of PCRs for each PORT varies across the products in the S32K1xx series.
The following table shows the number of PCRs for each PORT on each product. Memory
map and register definition documents the superset number of implemented ports. PCR
registers corresponding to ports which are not present in a particular device are read only
0. See the RM attachments IO Signal Description Input Multiplexing sheet(s) for details
on the count of PCRs on each product.
Table 12-1. PCRs on each product
PORT Number of PCRs1
S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
PORT A 11 12 18 18 25 32
PORT B 9 10 18 18 27 32
PORT C 12 14 18 18 25 32
PORT D 7 10 18 18 27 32
PORT E 4 12 17 17 24 28

1. See the attachments IO Signal Description Input Multiplexing sheet(s) for details.

12.1.2 Finding address for PORTx_PCRn

For example, in order to write to the PORT register of PTC3 (PTxn), the corresponding
mapped register is PORTC_PCR3 (PORTx_PCRn):
• To find PORTC base address, look up the 'Start address' of "Port C" in "Peripheral
Memory Map" tab in the attached S32K1xx_Memory_Map.xls. This is referred
henceforth as PORTC_Base_address.
• To reach PCRn, refer to address 'PORTx_Base_address + n*4d'. For PCR3 of
PORTC, this refers to 'PORTC_Base_address + 3*4d'. The attachmented IO Signal
Description Input Muxing sheet(s) for each device provides the fields available in
PCR per PORTx_PCRn (For each PTxn pin) in the tab IO Signal Table.

12.1.3 I/O configuration sequence

1. Ensure pins for the peripheral are in tristate sate (default out of reset).
2. Initialize peripheral clock in the Peripheral Clock Controller register(PCC) and
peripheral specific clocking configurations.
3. Configure the peripheral
4. Initialize port clock for the peripheral pins in the Peripheral Clock Controller register
(PCC_PORTx).

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5. Configure the peripheral pins mux and features in the Port Control and Interrupts
register (PORTx_PCRn).
6. Start communication

12.1.4 Digital input filter configuration sequence

1. Configure digital pin filtering controls for the corresponding pin using
PORTx_DFCR and PORTx_DFWR
2. Enable PORTx_DFER[DFE]
3. Configure PORTx_PCRn[MUX] for GPIO mode
4. Wait for delay equivalent to PORTx_DFWR for filter enabling glitches to propagate
5. Enable the corresponding function of the pin by configuring PORTx_PCRn[MUX]

12.1.4.1 Digital input filter configuration sequence while using GPIO

interrupt
1. Configure digital pin filtering controls for the corresponding pin using
PORTx_DFCR and PORTx_DFWR
2. Enable PORTx_DFER[DFE]
3. Configure PORTx_PCRn[MUX] for GPIO mode
4. Wait for delay equivalent to PORTx_DFWR for filter enabling glitches to propagate
5. Enable the interrupt on the corresponding pin by configuring PORTx_PCRn[IRQC]

12.1.4.2 Digital input filter configuration sequence while using NMI

1. Configure digital pin filtering controls for NMI pin using PORTD_DFCR and
PORTD_DFWR
2. Enable PORTD_DFER[3]
3. Configure PORTD_PCR3[MUX] for GPIO mode
4. Wait for delay equivalent to PORTD_DFWR for filter enabling glitches to propagate
5. Configure the pin for NMI mode using PORTD_PCR3[MUX]
Before entering STOP/VLPS modes, filter clock should be configured as
LPO128K_CLK and reconfigured on wakeup, if required.
If filtering is not required in STOP/VLPS modes, filtering should be disabled using
PORTx_DFER and reconfigured on wakeup, if required. If filtering is not required in
STOP/VLPS modes and is required wakeup onwards without reconfiguring
PORTx_DFER (with bus clock as filter clock), it should be ensured that:
cycles_tISR >> (PORTx_DFWR+3)*(SCG_xCCR[DIVBUS]+1)

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Introduction

where cycles_tISR: Core clock cycles in Interrupt Service Routine (ISR) from system
entering RUN mode till PORTx_PCRn[ISF] clearing for corresponding pin.
(Sufficient delay should be added in ISR, if required, to achieve the above)

12.1.5 Reset pin configuration

The reset pin on device can be configured for alternative functionalities via
PORTA_PCR5[SSS] (see IO Signal Description Input Multiplexing sheet(s) attached to
the Reference Manual). Before configuring this, FOPT[3] bit must be configured to
disable reset pin configuration for reset functionality. See FOPT[3] for details.

12.2 Introduction

12.3 Overview
The Port Control and Interrupt (PORT) module provides support for port control, digital
filtering, and external interrupt functions.
Most functions can be configured independently for each pin in the 32-bit port and affect
the pin regardless of its pin muxing state.
There is one instance of the PORT module for each port. Not all pins within each port are
implemented on a specific device.

12.3.1 Features
The PORT module has the following features:
• Pin interrupt
• Interrupt flag and enable registers for each pin
• Support for edge sensitive (rising, falling, both) or level sensitive (low, high)
configured per pin
• Support for interrupt or DMA request configured per pin
• Asynchronous wake-up in low-power modes
• Pin interrupt is functional in all digital pin muxing modes
• Digital input filter
• Digital input filter for each pin, usable by any digital peripheral muxed onto the
pin
• Individual enable or bypass control field per pin
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• Selectable clock source for digital input filter with a five bit resolution on filter
size
• Functional in all digital pin multiplexing modes
• Port control
• Individual pull control fields with pullup, pulldown, and pull-disable support
• Individual drive strength field supporting high and low drive strength
• Individual input passive filter field supporting enable and disable of the
individual input passive filter
• Individual mux control field supporting analog or pin disabled, GPIO, and up to
six chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.

12.3.2 Modes of operation

12.3.2.1 Run mode

In Run mode, the PORT operates normally.

12.3.2.2 Wait mode

In Wait mode, PORT continues to operate normally and may be configured to exit the
Low-Power mode if an enabled interrupt is detected. DMA requests are still generated
during the Wait mode, but do not cause an exit from the Low-Power mode.

12.3.2.3 Stop mode

In Stop mode, the PORT can be configured to exit the Low-Power mode via an
asynchronous wake-up signal if an enabled interrupt is detected.
In Stop mode, the digital input filters are bypassed unless they are configured to run from
the LPO clock source.

12.3.2.4 Debug mode

In Debug mode, PORT operates normally.

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External signal description

12.4 External signal description

The table found here describes the PORT external signal.
Table 12-2. Signal properties
Name Function I/O Reset Pull
PORTx[31:0] External interrupt I/O 0 -

NOTE
Not all pins within each port are implemented on each device.

12.5 Detailed signal description

The table found here contains the detailed signal description for the PORT interface.
Table 12-3. PORT interface—detailed signal description
Signal I/O Description
PORTx[31:0] I/O External interrupt.
State meaning Asserted—pin is logic 1.
Negated—pin is logic 0.
Timing Assertion—may occur at any time and can assert
asynchronously to the system clock.
Negation—may occur at any time and can assert
asynchronously to the system clock.

12.6 Memory map and register definition

Any read or write access to the PORT memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states.
PORT memory map
Address Width Section/
Register name Access Reset value
offset (hex) (in bits) page
0 Pin Control Register n (PORT_PCR0) 32 R/W See section 12.6.1/203
4 Pin Control Register n (PORT_PCR1) 32 R/W See section 12.6.1/203
8 Pin Control Register n (PORT_PCR2) 32 R/W See section 12.6.1/203
C Pin Control Register n (PORT_PCR3) 32 R/W See section 12.6.1/203
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PORT memory map (continued)

Address Width Section/
Register name Access Reset value
offset (hex) (in bits) page
10 Pin Control Register n (PORT_PCR4) 32 R/W See section 12.6.1/203
14 Pin Control Register n (PORT_PCR5) 32 R/W See section 12.6.1/203
18 Pin Control Register n (PORT_PCR6) 32 R/W See section 12.6.1/203
1C Pin Control Register n (PORT_PCR7) 32 R/W See section 12.6.1/203
20 Pin Control Register n (PORT_PCR8) 32 R/W See section 12.6.1/203
24 Pin Control Register n (PORT_PCR9) 32 R/W See section 12.6.1/203
28 Pin Control Register n (PORT_PCR10) 32 R/W See section 12.6.1/203
2C Pin Control Register n (PORT_PCR11) 32 R/W See section 12.6.1/203
30 Pin Control Register n (PORT_PCR12) 32 R/W See section 12.6.1/203
34 Pin Control Register n (PORT_PCR13) 32 R/W See section 12.6.1/203
38 Pin Control Register n (PORT_PCR14) 32 R/W See section 12.6.1/203
3C Pin Control Register n (PORT_PCR15) 32 R/W See section 12.6.1/203
40 Pin Control Register n (PORT_PCR16) 32 R/W See section 12.6.1/203
44 Pin Control Register n (PORT_PCR17) 32 R/W See section 12.6.1/203
48 Pin Control Register n (PORT_PCR18) 32 R/W See section 12.6.1/203
4C Pin Control Register n (PORT_PCR19) 32 R/W See section 12.6.1/203
50 Pin Control Register n (PORT_PCR20) 32 R/W See section 12.6.1/203
54 Pin Control Register n (PORT_PCR21) 32 R/W See section 12.6.1/203
58 Pin Control Register n (PORT_PCR22) 32 R/W See section 12.6.1/203
5C Pin Control Register n (PORT_PCR23) 32 R/W See section 12.6.1/203
60 Pin Control Register n (PORT_PCR24) 32 R/W See section 12.6.1/203
64 Pin Control Register n (PORT_PCR25) 32 R/W See section 12.6.1/203
68 Pin Control Register n (PORT_PCR26) 32 R/W See section 12.6.1/203
6C Pin Control Register n (PORT_PCR27) 32 R/W See section 12.6.1/203
70 Pin Control Register n (PORT_PCR28) 32 R/W See section 12.6.1/203
74 Pin Control Register n (PORT_PCR29) 32 R/W See section 12.6.1/203
78 Pin Control Register n (PORT_PCR30) 32 R/W See section 12.6.1/203
7C Pin Control Register n (PORT_PCR31) 32 R/W See section 12.6.1/203
W
80 Global Pin Control Low Register (PORT_GPCLR) 32 (always 0000_0000h 12.6.2/206
reads 0)
W
84 Global Pin Control High Register (PORT_GPCHR) 32 (always 0000_0000h 12.6.3/206
reads 0)
W
88 Global Interrupt Control Low Register (PORT_GICLR) 32 (always 0000_0000h 12.6.4/207
reads 0)
W
8C Global Interrupt Control High Register (PORT_GICHR) 32 (always 0000_0000h 12.6.5/207
reads 0)
A0 Interrupt Status Flag Register (PORT_ISFR) 32 w1c 0000_0000h 12.6.6/208
Table continues on the next page...

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PORT memory map (continued)

Address Width Section/
Register name Access Reset value
offset (hex) (in bits) page
C0 Digital Filter Enable Register (PORT_DFER) 32 R/W 0000_0000h 12.6.7/209
C4 Digital Filter Clock Register (PORT_DFCR) 32 R/W 0000_0000h 12.6.8/209
C8 Digital Filter Width Register (PORT_DFWR) 32 R/W 0000_0000h 12.6.9/210

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12.6.1 Pin Control Register n (PORT_PCRn)

NOTE
See the Signal Multiplexing and Pin Assignment chapter for the
reset value of this device.
See the GPIO Configuration section for details on the available
functions for each pin.
Do not modify pin configuration registers associated with pins
that are not available in a reduced-pin package offering.
Unbonded pins not available in a package are disabled by
default to prevent them from consuming power.
Address: 0h base + 0h offset + (4d × i), where i=0d to 31d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 ISF 0

IRQC

W w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0
Reserved

Reserved

LK MUX DSE PFE PE PS

Reset 0 0 0 0 0 * * * 0 * 0 * 0 0 * *

* Notes:
• MUX field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
• DSE field: Varies by port. See the Signal Multiplexing and Signal Descriptions chapter for reset values per port.
• PFE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
• PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
• PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.

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PORT_PCRn field descriptions

Field Description
31–25 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Interrupt Status Flag
ISF
The pin interrupt configuration is valid in all digital pin muxing modes.

0 Configured interrupt is not detected.

1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
23–20 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
19–16 Interrupt Configuration
IRQC
The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured
to generate interrupt/DMA request as follows:

0000 Interrupt Status Flag (ISF) is disabled.

0001 ISF flag and DMA request on rising edge.
0010 ISF flag and DMA request on falling edge.
0011 ISF flag and DMA request on either edge.
0100 Reserved.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 ISF flag and Interrupt when logic 0.
1001 ISF flag and Interrupt on rising-edge.
1010 ISF flag and Interrupt on falling-edge.
1011 ISF flag and Interrupt on either edge.
1100 ISF flag and Interrupt when logic 1.
1101 Reserved.
1110 Reserved.
1111 Reserved.
15 Lock Register
LK
0 Pin Control Register fields [15:0] are not locked.
1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
14–11 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
10–8 Pin Mux Control
MUX
Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in
configuring the pin for a different pin muxing slot.
The corresponding pin is configured in the following pin muxing slot as follows:

000 Pin disabled (Alternative 0) (analog).

001 Alternative 1 (GPIO).
010 Alternative 2 (chip-specific).
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PORT_PCRn field descriptions (continued)

Field Description
011 Alternative 3 (chip-specific).
100 Alternative 4 (chip-specific).
101 Alternative 5 (chip-specific).
110 Alternative 6 (chip-specific).
111 Alternative 7 (chip-specific).
7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
6 Drive Strength Enable
DSE
Drive strength configuration is valid in all digital pin muxing modes.

0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
5 This field is reserved.
Reserved
4 Passive Filter Enable
PFE
Passive filter configuration is valid in all digital pin muxing modes.

0 Passive input filter is disabled on the corresponding pin.

1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer
to the device data sheet for filter characteristics.
3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2 This field is reserved.
Reserved
1 Pull Enable
PE
Pull configuration is valid in all digital pin muxing modes.

0 Internal pullup or pulldown resistor is not enabled on the corresponding pin.

1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a
digital input.
0 Pull Select
PS
Pull configuration is valid in all digital pin muxing modes.

0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

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12.6.2 Global Pin Control Low Register (PORT_GPCLR)

Only 32-bit writes are supported to this register.
Address: 0h base + 80h offset = 80h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0
W GPWE GPWD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PORT_GPCLR field descriptions

Field Description
31–16 Global Pin Write Enable
GPWE
Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD. If a
selected Pin Control Register is locked then the write to that register is ignored.

0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
GPWD Global Pin Write Data

Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.

12.6.3 Global Pin Control High Register (PORT_GPCHR)

Only 32-bit writes are supported to this register.
Address: 0h base + 84h offset = 84h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0
W GPWE GPWD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PORT_GPCHR field descriptions

Field Description
31–16 Global Pin Write Enable
GPWE
Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. If a
selected Pin Control Register is locked then the write to that register is ignored.

0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
GPWD Global Pin Write Data
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PORT_GPCHR field descriptions (continued)

Field Description
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.

12.6.4 Global Interrupt Control Low Register (PORT_GICLR)

Only 32-bit writes are supported to this register.
Address: 0h base + 88h offset = 88h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0
W GIWD GIWE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PORT_GICLR field descriptions

Field Description
31–16 Global Interrupt Write Data
GIWD
Write value that is written to all Pin Control Registers bits [31:16] that are selected by GIWE.
GIWE Global Interrupt Write Enable

Selects which Pin Control Registers (15 through 0) bits [31:16] update with the value in GIWD.

0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.

12.6.5 Global Interrupt Control High Register (PORT_GICHR)

Only 32-bit writes are supported to this register.
Address: 0h base + 8Ch offset = 8Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0
W GIWD GIWE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PORT_GICHR field descriptions

Field Description
31–16 Global Interrupt Write Data
GIWD
Write value that is written to all Pin Control Registers bits [31:16] that are selected by GIWE.

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Memory map and register definition

PORT_GICHR field descriptions (continued)

Field Description
GIWE Global Interrupt Write Enable

Selects which Pin Control Registers (31 through 16) bits [31:16] update with the value in GIWD.

0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.

12.6.6 Interrupt Status Flag Register (PORT_ISFR)

The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt
Status Flag for each pin is also visible in the corresponding Pin Control Register, and
each flag can be cleared in either location.
Address: 0h base + A0h offset = A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ISF
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PORT_ISFR field descriptions

Field Description
ISF Interrupt Status Flag

Each bit in the field indicates the detection of the configured interrupt of the same number as the field.

0 Configured interrupt is not detected.

1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.

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12.6.7 Digital Filter Enable Register (PORT_DFER)

The digital filter configuration is valid in all digital pin muxing modes.
Address: 0h base + C0h offset = C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DFE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PORT_DFER field descriptions

Field Description
DFE Digital Filter Enable

The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is
reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the
digital filter of the same number as the field.

0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.

12.6.8 Digital Filter Clock Register (PORT_DFCR)

The digital filter configuration is valid in all digital pin muxing modes.
Address: 0h base + C4h offset = C4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PORT_DFCR field descriptions

Field Description
31–1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 Clock Source
CS
Table continues on the next page...

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PORT_DFCR field descriptions (continued)

Field Description
The digital filter configuration is valid in all digital pin muxing modes. Configures the clock source for the
digital input filters. Changing the filter clock source must be done only when all digital filters are disabled.

0 Digital filters are clocked by the bus clock.

1 Digital filters are clocked by the LPO clock.

12.6.9 Digital Filter Width Register (PORT_DFWR)

The digital filter configuration is valid in all digital pin muxing modes.
Address: 0h base + C8h offset = C8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 FILT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PORT_DFWR field descriptions

Field Description
31–5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
FILT Filter Length

The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the
glitches, in clock cycles, that the digital filter absorbs for the enabled digital filters. Glitches that are longer
than this register setting will pass through the digital filter, and glitches that are equal to or less than this
register setting are filtered. Changing the filter length must be done only after all filters are disabled.

12.7 Functional description

12.7.1 Pin control

Each port pin has a corresponding Pin Control register, PORT_PCRn, associated with it.
The upper half of the Pin Control register configures the pin's capability to either
interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as
well as a logic level occurring on the port pin. It also includes a flag to indicate that an
interrupt has occurred.

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The lower half of the Pin Control register configures the following functions for each pin
within the 32-bit port.
• Pullup or pulldown enable
• Drive strength
• Passive input filter enable
• Pin Muxing mode
The functions apply across all digital pin muxing modes and individual peripherals do not
override the configuration in the Pin Control register. For example, if an I2C function is
enabled on a pin, that does not override the pullup configuration for that pin.
When the Pin Muxing mode is configured for analog or is disabled, all the digital
functions on that pin are disabled. This includes the pullup and pulldown enables, output
buffer enable, input buffer enable, and passive filter enable.
The LK bit (bit 15 of Pin Control Register PCRn) allows the configuration for each pin to
be locked until the next system reset. When locked, writes to the lower half of that pin
control register are ignored, although a bus error is not generated on an attempted write to
a locked register.
The configuration of each Pin Control register is retained when the PORT module is
disabled.
Whenever a pin is configured in any digital pin muxing mode, the input buffer for that
pin is enabled allowing the pin state to be read via the corresponding GPIO Port Data
Input Register (GPIO_PDIR) or allowing a pin interrupt or DMA request to be generated.
If a pin is ever floating when its input buffer is enabled, then this can cause an increase in
power consumption and must be avoided. A pin can be floating due to an input pin that is
not connected or an output pin that has tri-stated (output buffer is disabled).
Enabling the internal pull resistor (or implementing an external pull resistor) will ensure a
pin does not float when its input buffer is enabled; note that the internal pull resistor is
automatically disabled whenever the output buffer is enabled allowing the Pull Enable bit
to remain set. Configuring the Pin Muxing mode to disabled or analog will disable the
pin’s input buffer and results in the lowest power consumption.

12.7.2 Global pin control

The two global pin control registers allow a single register write to update the lower half
of the pin control register on up to 16 pins, all with the same value. Registers that are
locked cannot be written using the global pin control registers.

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The global pin control registers are designed to enable software to quickly configure
multiple pins within the one port for the same peripheral function. However, the interrupt
functions cannot be configured using the global pin control registers.
The global pin control registers are write-only registers, that always read as 0.

12.7.3 Global interrupt control

The two global interrupt control registers allow a single register write to update the upper
half of the pin control register on up to 16 pins, all with the same value.
The global interrupt control registers are designed to enable software to quickly configure
multiple pins within the one port for the same interrupt configuration. However, the pin
control functions cannot be configured using the global interrupt control registers.
The global interrupt control registers are write-only registers and always read as 0.

12.7.4 External interrupts

The external interrupt capability of the PORT module is available in all digital pin
muxing modes provided the PORT module is enabled.
Each pin can be individually configured for any of the following external interrupt
modes:
• Interrupt disabled, default out of reset
• Active high level sensitive interrupt
• Active low level sensitive interrupt
• Rising edge sensitive interrupt
• Falling edge sensitive interrupt
• Rising and falling edge sensitive interrupt
• Rising edge sensitive DMA request
• Falling edge sensitive DMA request
• Rising and falling edge sensitive DMA request
The interrupt status flag is set when the configured edge or level is detected on the pin or
at the output of the digital input filter, if the digital input digital filter is enabled. When
not in Stop mode, the input is first synchronized to the bus clock to detect the configured
level or edge transition.

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The PORT module generates a single interrupt that asserts when the interrupt status flag
is set for any enabled interrupt for that port. The interrupt negates after the interrupt status
flags for all enabled interrupts have been cleared by writing a logic 1 to the ISF flag in
either the PORT_ISFR or PORT_PCRn registers.
The PORT module generates a single DMA request that asserts when the interrupt status
flag is set for any enabled DMA request in that port. The DMA request negates after the
DMA transfer is completed, because that clears the interrupt status flags for all enabled
DMA requests.
During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously
set if the required level or edge is detected. This also generates an asynchronous wake-up
signal to exit the Low-Power mode.

12.7.5 Digital filter

The digital filter capabilities of the PORT module are available in all digital Pin Muxing
modes if the PORT module is enabled.
The clock used for all digital filters within one port can be configured between the bus
clock or the LPO clock. This selection must be changed only when all digital filters for
that port are disabled. If the digital filters for a port are configured to use the bus clock,
then the digital filters are bypassed for the duration of Stop mode. While the digital filters
are bypassed, the output of each digital filter always equals the input pin, but the internal
state of the digital filters remains static and does not update due to any change on the
input pin.
The filter width in clock size is the same for all enabled digital filters within one port and
must be changed only when all digital filters for that port are disabled.
The output of each digital filter is logic zero after system reset and whenever a digital
filter is disabled. After a digital filter is enabled, the input is synchronized to the filter
clock, either the bus clock or the LPO clock. If the synchronized input and the output of
the digital filter remain different for a number of filter clock cycles equal to the filter
width register configuration, then the output of the digital filter updates to equal the
synchronized filter input.
The maximum latency through a digital filter equals three filter clock cycles plus the
filter width configuration register.

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General-Purpose Input/Output (GPIO)

13.1 Chip-specific GPIO information

13.1.1 Instantiation information

Port control and interrupt module features are supported, each 32-pin port will support a
single interrupt. Not all pins are available on each package supported. See IO Signal
Description Input Multiplexing sheet(s) attached to the Reference Manual for the details
on which pins are supported in different packages. See Port Control and Interrupts
(PORT) for details of how to control the ports.
See Module operation in available power modes for details on available power modes.

13.1.2 GPIO ports memory map

This chip implements five instances of GPIOs GPIOA to GPIOE. The GPIO register
descriptions in this chapter are generic. Refer to the table below to see how addresses are
allocated to every instance of GPIO in the device memory map.
Table 13-1. GPIO ports memory map
Start address Port
Base + 0h Port A
Base + 40h Port B
Base + 80h Port C
Base + C0h Port D
Base + 100h Port E

NOTE
• In S32K14x, GPIO can only be accessed by the core
through the cross bar interface at 0x400F_F000.

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• In S32K11x, GPIO is multi-ported and can be accessed

directly by the core with zero wait states at base address
[0xF800_0000 + 0x40*n (n: 0 to 4)]. It can also be
accessed by the core through the cross bar/AIPS interface
at [0x400F_F000 + 0x40*n (n: 0 to 4)] and at an aliased
slot (15) at address [0x4000_F000 + 0x40*n (n: 0 to 4)].
• In S32K11x, when in GPIO mode (PORT_PCRn[MUX]
programmed to 0x1), the register PIDR cannot be written to
0x1. This programming helps to disable the input mode and
this is not possible to achieve in S32K11x. The implication
of this is that when the GPIO is configured in output mode
(PDDR[n] programmed to 1), the data written on PDOR
register would be reflected on PDIR after some delay if the
output does not toggle to often. If the pad needs to be tri-
stated, the PORT_PCRn[MUX] needs to be 00.
GPIO at 0x400FF000 GPIO at 0x4000F000 GPIO at 0xF8000000
S32K14x Accessible in CPO mode NA NA
S32K11x Not accessible in CPO mode Not accessible in CPO mode Accessible in CPO mode

13.1.3 GPIO register reset values

Following table defines the chip-specific register reset value.
Table 13-2. GPIO register reset values
Register Reset value
PDIR 0000_0020

13.2 Introduction
The general-purpose input and output (GPIO) module communicates to the processor
core via a zero wait state interface for maximum pin performance. The GPIO registers
support 8-bit, 16-bit or 32-bit accesses.
The GPIO data direction and output data registers control the direction and output data of
each pin when the pin is configured for the GPIO function. The GPIO input data register
displays the logic value on each pin when the pin is configured for any digital function,
provided the corresponding Port Control and Interrupt module for that pin is enabled.

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Efficient bit manipulation of the general-purpose outputs is supported through the

addition of set, clear, and toggle write-only registers for each port output data register.

13.2.1 Features
Features of the GPIO module include:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
• Port Data Direction register
NOTE
The GPIO module is clocked by system clock.

13.2.2 Modes of operation

The following table depicts different modes of operation and the behavior of the GPIO
module in these modes.
Table 13-3. Modes of operation
Modes of operation Description
Run The GPIO module operates normally.
Stop The GPIO module is disabled.
Debug The GPIO module operates normally.

13.2.3 GPIO signal descriptions

Table 13-4. GPIO signal descriptions
GPIO signal descriptions Description I/O
PORTA31–PORTA0 General-purpose input/output I/O
PORTB31–PORTB0 General-purpose input/output I/O
PORTC31–PORTC0 General-purpose input/output I/O
PORTD31–PORTD0 General-purpose input/output I/O
PORTE31–PORTE0 General-purpose input/output I/O

NOTE
Not all pins within each port are implemented on each device.
See the chapter on signal multiplexing for the number of GPIO
ports available in the device.

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13.2.3.1 Detailed signal description

Table 13-5. GPIO interface-detailed signal descriptions
Signal I/O Description
PORTA31–PORTA0 I/O General-purpose input/output
PORTB31–PORTB0 State meaning Asserted: The pin is logic 1.
PORTC31–PORTC0 Deasserted: The pin is logic 0.
PORTD31–PORTD0 Timing Assertion: When output, this
signal occurs on the rising-
PORTE31–PORTE0 edge of the system clock. For
input, it may occur at any time
and input may be asserted
asynchronously to the system
clock.
Deassertion: When output,
this signal occurs on the
rising-edge of the system
clock. For input, it may occur
at any time and input may be
asserted asynchronously to
the system clock.

NOTE
Not all pins within each port are implemented on each device.
See the chapter on signal multiplexing for the number of GPIO
ports available in the device.

13.3 Memory map and register definition

The registers for each GPIO port occupy 64-byte of the memory map. Any read or write
access to the GPIO slot outside this space results in a bus error.
NOTE
For simplicity, each GPIO port's registers appear with the same
width of 32 bits, corresponding to 32 pins. The actual number
of pins per port (and therefore the number of usable control bits
per port register) is chip-specific. Refer to the chip-specific
GPIO information to see the exact control bits for each port.

13.3.1 GPIO register descriptions

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13.3.1.1 GPIO Memory map

GPIOA base address: 400F_F000h
GPIOB base address: 400F_F040h
GPIOC base address: 400F_F080h
GPIOD base address: 400F_F0C0h
GPIOE base address: 400F_F100h
Offset Register Width Access Reset value
(In bits)
0h Port Data Output Register (PDOR) 32 RW 0000_0000h
4h Port Set Output Register (PSOR) 32 WORZ 0000_0000h
8h Port Clear Output Register (PCOR) 32 WORZ 0000_0000h
Ch Port Toggle Output Register (PTOR) 32 WORZ 0000_0000h
10h Port Data Input Register (PDIR) 32 RO 0000_0000h
14h Port Data Direction Register (PDDR) 32 RW 0000_0000h
18h Port Input Disable Register (PIDR) 32 RW 0000_0000h

13.3.1.2 Port Data Output Register (PDOR)

13.3.1.2.1 Offset
Register Offset
PDOR 0h

13.3.1.2.2 Function
This register configures the logic levels that are driven on each general-purpose output
pin.
NOTE
Do not modify pin configuration registers associated with pins
not available in your selected package. All unbonded pins not
available in your package will default to DISABLE state for
lowest power consumption.

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13.3.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
PDO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
PDO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

13.3.1.2.4 Fields
Field Function
31-0 Port Data Output
PDO Register bits for unbonded pins return an undefined value when read.
0b - Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1b - Logic level 1 is driven on pin, provided pin is configured for general-purpose output.

13.3.1.3 Port Set Output Register (PSOR)

13.3.1.3.1 Offset
Register Offset
PSOR 4h

13.3.1.3.2 Function
This register configures whether to set the fields of the PDOR.

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13.3.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W PTSO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0
W PTSO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

13.3.1.3.4 Fields
Field Function
31-0 Port Set Output
PTSO Writing to this register updates the contents of the corresponding bit in the PDOR as follows:
0b - Corresponding bit in PDORn does not change.
1b - Corresponding bit in PDORn is set to logic 1.

13.3.1.4 Port Clear Output Register (PCOR)

13.3.1.4.1 Offset
Register Offset
PCOR 8h

13.3.1.4.2 Function
This register configures whether to clear the fields of PDOR.

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13.3.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W PTCO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0
W PTCO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

13.3.1.4.4 Fields
Field Function
31-0 Port Clear Output
PTCO Writing to this register updates the contents of the corresponding bit in the Port Data Output Register
(PDOR) as follows:
0b - Corresponding bit in PDORn does not change.
1b - Corresponding bit in PDORn is cleared to logic 0.

13.3.1.5 Port Toggle Output Register (PTOR)

13.3.1.5.1 Offset
Register Offset
PTOR Ch

13.3.1.5.2 Function
This register toggles the logic levels that are driven on each general-purpose output pin.

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13.3.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W PTTO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0
W PTTO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

13.3.1.5.4 Fields
Field Function
31-0 Port Toggle Output
PTTO Writing to this register updates the contents of the corresponding bit in the PDOR as follows:
0b - Corresponding bit in PDORn does not change.
1b - Corresponding bit in PDORn is set to the inverse of its existing logic state.

13.3.1.6 Port Data Input Register (PDIR)

13.3.1.6.1 Offset
Register Offset
PDIR 10h

13.3.1.6.2 Function
This register captures the logic levels that are driven into each general-purpose input pin.
NOTE
Do not modify pin configuration registers associated with pins
not available in your selected package. All unbonded pins not
available in your package will default to DISABLE state for
lowest power consumption.

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13.3.1.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R PDI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R PDI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

13.3.1.6.4 Fields
Field Function
31-0 Port Data Input
PDI Reads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digital
function read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR
does not update.
0b - Pin logic level is logic 0, or is not configured for use by digital function.
1b - Pin logic level is logic 1.

13.3.1.7 Port Data Direction Register (PDDR)

13.3.1.7.1 Offset
Register Offset
PDDR 14h

13.3.1.7.2 Function
The PDDR configures the individual port pins for input or output.

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13.3.1.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
PDD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
PDD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

13.3.1.7.4 Fields
Field Function
31-0 Port Data Direction
PDD Configures individual port pins for input or output.
0b - Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the
port input is disabled in GPIOx_PIDR register.
1b - Pin is configured as general-purpose output, for the GPIO function.

13.3.1.8 Port Input Disable Register (PIDR)

13.3.1.8.1 Offset
Register Offset
PIDR 18h

13.3.1.8.2 Function
This register disables each general-purpose pin from acting as an input.

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13.3.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
PID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
PID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

13.3.1.8.4 Fields
Field Function
31-0 Port Input Disable
PID 0b - Pin is configured for General Purpose Input, provided the pin is configured for any digital
function.
1b - Pin is not configured as General Purpose Input. Corresponding Port Data Input Register bit will
read zero.

13.4 Functional description

13.4.1 General-purpose input

The logic state of each pin is available via the Port Data Input registers, provided the
corresponding bit in the port input enable register is set, the pin is configured for a digital
function and the corresponding Port Control and Interrupt module is enabled.
The input pin synchronizers are shared with the Port Control and Interrupt module, so
that if the corresponding Port Control and Interrupt module is disabled, then
synchronizers are also disabled. This reduces power consumption when a port is not
required for general-purpose input functionality.

13.4.2 General-purpose output

The logic state of each pin can be controlled via the port data output registers and port
data direction registers, provided the pin is configured for the GPIO function. The
following table depicts the conditions for a pin to be configured as input/output.
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If Then
A pin is configured for the GPIO function and the The pin is configured as an input.
corresponding port data direction register bit is clear.
A pin is configured for the GPIO function and the The pin is configured as an output and the logic state of the
corresponding port data direction register bit is set. pin is equal to the corresponding port data output register.

To facilitate efficient bit manipulation on the general-purpose outputs, pin data set, pin
data clear, and pin data toggle registers exist to allow one or more outputs within one port
to be set, cleared, or toggled from a single register write.
The corresponding Port Control and Interrupt module does not need to be enabled to
update the state of the port data direction registers and port data output registers including
the set/clear/toggle registers.

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Crossbar Switch Lite (AXBS-Lite)

14.1 Chip-specific AXBS-Lite information

14.1.1 Crossbar Switch master assignments

The following table identifies the masters connected to the Crossbar Switch and their
priority order in fixed-priority mode.
Table 14-1. Master port assignments and priority order for fixed-priority arbitration
Chips Master port number 0 Master port number 1 Master port number 2 Master port number 3
Priority 3 1 Priority 21 Priority 11 Priority 41
S32K148 Arm core code bus Arm core system bus DMA ENET
S32K146 Arm core code bus Arm core system bus DMA -
S32K144 Arm core code bus Arm core system bus DMA
S32K142 Arm core code bus Arm core system bus DMA
S32K116 Arm core master bus - DMA
S32K118 Arm core master bus - DMA

1. Priority in fixed-priority mode. MCM controls mode selection for global slave port arbitration. For fixed priority, set
MCM_CPCR[CBRR] to 0. For round robin, set MCM_CPCR[CBRR] to 1. The arbitration setting applies to all slave ports.

NOTE
For configuring the bit field MCM_CPCR[CBRR], see the note
present in the CBRR.

14.1.2 Crossbar Switch slave assignments

The following table identifies the slaves connected to the Crossbar Switch and whether
the system MPU protects them.

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Table 14-2. Slave port assignments and system MPU protection

Chips Slave port number 0 Slave port number 1 Slave port number 2 Slave port number 3
S32K148 Flash memory SRAM controllers 1 Peripheral Bridge 0/ QuadSPI 1
controller1 GPIO 2
S32K146 Flash memory SRAM controllers 1 Peripheral Bridge 0/ -
controller1 GPIO 2
S32K144 Flash memory SRAM controllers 1 Peripheral Bridge 0/
controller 1 GPIO 2
S32K142 Flash memory SRAM controllers 1 Peripheral Bridge 0/
controller 1 GPIO 2
S32K116 Flash memory SRAM controllers 1 Peripheral Bridge 0/
controller 1 GPIO 2
S32K118 Flash memory SRAM controllers 1 Peripheral Bridge 0/
controller 1 GPIO2

1. Protected by system MPU

2. Not protected by system MPU: System MPU does not protect access to peripheral registers, including system MPU's own
registers. Protection is built into Peripheral Bridge (AIPS-Lite).

14.2 Introduction
The information found here provides information on the layout, configuration, and
programming of the crossbar switch.
The crossbar switch connects bus masters and bus slaves using a crossbar switch
structure. This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access the
same slave.

14.2.1 Features
The crossbar switch includes these features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• Up to single-clock 32-bit transfer
• Programmable configuration for fixed-priority or round-robin slave port arbitration
(see the chip-specific information).

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14.3 Functional Description

Information about general operation and arbitration can be found here.

14.3.1 General operation

When a master accesses the crossbar switch, the access is immediately taken. If the
targeted slave port of the access is available, then the access is immediately presented on
the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar.
If the targeted slave port of the access is busy or parked on a different master port, the
requesting master simply sees wait states inserted until the targeted slave port can service
the master's request. The latency in servicing the request depends on each master's
priority level and the responding slave's access time.
Because the crossbar switch appears to be just another slave to the master device, the
master device has no knowledge of whether it actually owns the slave port it is targeting.
While the master does not have control of the slave port it is targeting, it simply waits.
After the master has control of the slave port it is targeting, the master remains in control
of the slave port until it relinquishes the slave port by running an IDLE cycle or by
targeting a different slave port for its next access.
The master can also lose control of the slave port if another higher-priority master makes
a request to the slave port.
The crossbar terminates all master IDLE transfers, as opposed to allowing the termination
to come from one of the slave buses. Additionally, when no master is requesting access to
a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default
master may be granted access to the slave port.
When a slave bus is being idled by the crossbar, it remains parked with the last master to
use the slave port. This is done to save the initial clock of arbitration delay that otherwise
would be seen if the same master had to arbitrate to gain control of the slave port.

14.3.2 Arbitration
The crossbar switch supports two arbitration algorithms:
• Fixed priority
• Round-robin

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Functional Description

The selection of the global slave port arbitration algorithm is described in the crossbar
switch chip-specific information.

14.3.2.1 Arbitration during undefined length bursts

Undefined length bursts can be interrupted.

14.3.2.2 Fixed-priority operation

When operating in fixed-priority mode, each master is assigned a unique priority level
with the highest numbered master having the highest priority (for example, in a system
with 5 masters, master 1 has lower priority than master 3). If two masters request access
to the same slave port, the master with the highest priority gains control over the slave
port.
NOTE
In this arbitration mode, a higher-priority master can
monopolize a slave port, preventing accesses from any lower-
priority master to the port.
When a master makes a request to a slave port, the slave port checks whether the new
requesting master's priority level is higher than that of the master that currently has
control over the slave port, unless the slave port is in a parked state. The slave port
performs an arbitration check at every clock edge to ensure that the proper master, if any,
has control of the slave port.
The following table describes possible scenarios based on the requesting master port:
Table 14-3. How the Crossbar Switch grants control of a slave port to a master
When Then the Crossbar Switch grants control to the
requesting master
Both of the following are true: At the next clock edge
• The current master is not running a transfer.
• The new requesting master's priority level is higher than
that of the current master.
Both of the following are true: At the next arbitration point for the undefined length burst
• The current master is running an undefined length burst transfer
transfer.
• The requesting master's priority level is higher than that
of the current master.
The requesting master's priority level is lower than the current At the conclusion of one of the following cycles:
master. • An IDLE cycle
• A non-IDLE cycle to a location other than the current
slave port

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14.3.2.3 Round-robin priority operation

When operating in round-robin mode, each master is assigned a relative priority based on
the master port number. This relative priority is compared to the master port number (ID)
of the last master to perform a transfer on the slave bus. The highest priority requesting
master becomes owner of the slave bus at the next transfer boundary. Priority is based on
how far ahead the ID of the requesting master is to the ID of the last master.
After granted access to a slave port, a master may perform as many transfers as desired to
that port until another master makes a request to the same slave port. The next master in
line is granted access to the slave port at the next transfer boundary, or possibly on the
next clock cycle if the current master has no pending access request.
As an example of arbitration in round-robin mode, assume the crossbar is implemented
with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and
master 0, 4, and 5 make simultaneous requests, they are serviced in the order: 4 then 5
then 0.
The round-robin arbitration mode generally provides a more fair allocation of the
available slave-port bandwidth (compared to fixed priority) as the fixed master priority
does not affect the master selection.

14.4 Initialization/application information

No initialization is required for the crossbar switch.

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Chapter 15
Memory Protection Unit (MPU)

15.1 Chip-specific MPU information

On this device, NXP's system MPU implements the safety mechanisms to prevent
masters from accessing restricted memory regions. This system MPU provides memory
protection at the level of the Crossbar Switch. Each Crossbar master (Core, DMA,
Ethernet) can be assigned different access rights to each protected memory region. The
Arm M4 and M0+ core version in this family does not integrate the Arm Core MPU,
which would concurrently monitor only core-initiated memory accesses. In this
document, the term MPU refers to NXP's system MPU.

15.1.1 MPU Slave Port Assignments

The memory-mapped resources protected by the MPU are:
Table 15-1. MPU Slave Port Assignments For S32K14x series
Source MPU Slave Port Assignment Destination
Crossbar slave port 0 MPU slave port 0 Flash Controller
Crossbar slave port 1 MPU slave port 1 SRAM backdoor
Code Bus MPU slave port 2 SRAM_L frontdoor
System Bus MPU slave port 3 SRAM_U frontdoor
Crossbar slave port 3 MPU Slave port 4 QuadSPI

Table 15-2. MPU Slave Port Assignments for S32K11x series

Source MPU Slave Port Assignment Destination
Crossbar slave port 0 MPU slave port 0 Flash Controller
Crossbar slave port 1 MPU slave port 1 SRAM controller/MTB_RAM/MCM

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15.1.2 MPU Logical Bus Master Assignments

The logical bus master assignments for the MPU are:
Table 15-3. MPU Logical Bus Master Assignments
MPU Bus Possible access types PID
Logical Master avaialable
User Supervisor Data Instruction Read Write Execute
Bus
Master
ID
0 Core ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
1 Debugger ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
2 DMA - ✓ ✓ - ✓ ✓ - -
3 ENET ✓ - ✓ - ✓ ✓ - -
4-7 Not implemented. The region descriptor register fields for these master IDs are Reserved.

15.1.3 Current PID

Current PID is configured at Miscellaneous Control Module Process ID register
(MCM_PID).

15.1.4 Region descriptors and slave port configuration

For each chip in the product series, the following table shows the numbers of region
descriptors and slave ports as well as the reset value of Control/Error Status Register
(CESR) that reflects those numbers.
Table 15-4. MPU configurations
Chips Region descriptors Slave ports CESR reset value
S32K116 8 2 0081_2001
S32K118 8 2 0081_2001
S32K142 8 4 0081_4001h
S32K144 8 4 0081_4001h
S32K146 8 4 0081_4001h
S32K148 16 5 0081_5201h

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 Chapter 15 Memory Protection Unit (MPU)

15.2 Introduction
The memory protection unit (MPU) provides hardware access control for all memory
references generated in the device.

15.3 Overview
The MPU concurrently monitors all system bus transactions and evaluates their
appropriateness using pre-programmed region descriptors that define memory spaces and
their access rights. Memory references that have sufficient access control rights are
allowed to complete, while references that are not mapped to any region descriptor or
have insufficient rights are terminated with a protection error response.

15.3.1 Block diagram

A simplified block diagram of the MPU module is shown in the following figure.
Slave Port n Internal
Address Phase Signals Peripheral Bus

Access Region
Evaluation
Descriptor 0
Macro

Access Region
Evaluation
Descriptor 1
Macro

Access Region
Evaluation
Descriptor x
Macro

MPU_EARn MPU_EDRn

Mux

Figure 15-1. MPU block diagram

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Overview

The hardware's two-dimensional connection matrix is clearly visible with the basic access
evaluation macro shown as the replicated submodule block. The crossbar switch slave
ports are shown on the left, the region descriptor registers in the middle, and the
peripheral bus interface on the right side. The evaluation macro contains two magnitude
comparators connected to the start and end address registers from each region descriptor
as well as the combinational logic blocks to determine the region hit and the access
protection error. For details of the access evaluation macro, see Access evaluation macro.

15.3.2 Features
The MPU implements a two-dimensional hardware array of memory region descriptors
and the crossbar slave ports to continuously monitor the legality of every memory
reference generated by each bus master in the system.
The feature set includes:
• 16 program-visible 128-bit region descriptors, accessible by four 32-bit words each
• Each region descriptor defines a modulo-32 byte space, aligned anywhere in
memory
• Region sizes can vary from 32 bytes to 4 Gbytes
• Two access control permissions defined in a single descriptor word
• Masters 0–3: read, write, and execute attributes for supervisor and user
accesses
• Masters 4–7: read and write attributes
• Hardware-assisted maintenance of the descriptor valid bit minimizes coherency
issues
• Alternate programming model view of the access control permissions word
• Priority given to granting permission over denying access for overlapping region
descriptors
• Detects access protection errors if a memory reference does not hit in any memory
region, or if the reference is illegal in all hit memory regions. If an access error
occurs, the reference is terminated with an error response, and the MPU inhibits the
bus cycle being sent to the targeted slave device.

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• Error registers, per slave port, capture the last faulting address, attributes, and other
information
• Global MPU enable/disable control bit

15.4 MPU register descriptions

The programming model is partitioned into three groups:

• Control/status registers
• The data structure containing the region descriptors
• The alternate view of the region descriptor access control values
The programming model can be referenced using only 32-bit accesses. The programming
model can be accessed only in supervisor mode.
Attempted references of the following types generate an error termination:
• Non-32-bit references
• Accesses in user mode
• References to undefined—that is, reserved—addresses
• References with a non-supported access type, such as a write access to a read-only
register or a read access of a write-only register

15.4.1 MPU Memory map

MPU base address: 4000_D000h
Offset Register Width Access Reset value
(In bits)
0h Control/Error Status Register (CESR) 32 RW 0081_5201h
10h Error Address Register, slave port 0 (EAR0) 32 RO 0000_0000h
14h Error Detail Register, slave port 0 (EDR0) 32 RO 0000_0000h
18h Error Address Register, slave port 1 (EAR1) 32 RO 0000_0000h
1Ch Error Detail Register, slave port 1 (EDR1) 32 RO 0000_0000h
20h Error Address Register, slave port 2 (EAR2) 32 RO 0000_0000h
24h Error Detail Register, slave port 2 (EDR2) 32 RO 0000_0000h
28h Error Address Register, slave port 3 (EAR3) 32 RO 0000_0000h
2Ch Error Detail Register, slave port 3 (EDR3) 32 RO 0000_0000h

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MPU register descriptions

Offset Register Width Access Reset value

(In bits)
30h Error Address Register, slave port 4 (EAR4) 32 RO 0000_0000h
34h Error Detail Register, slave port 4 (EDR4) 32 RO 0000_0000h
400h Region Descriptor 0, Word 0 (RGD0_WORD0) 32 RW 0000_0000h
404h Region Descriptor 0, Word 1 (RGD0_WORD1) 32 RW FFFF_FFFFh
408h Region Descriptor 0, Word 2 (RGD0_WORD2) 32 RW 0061_F7DFh
40Ch Region Descriptor 0, Word 3 (RGD0_WORD3) 32 RW 0000_0001h
410h Region Descriptor 1, Word 0 (RGD1_WORD0) 32 RW 0000_0000h
414h Region Descriptor 1, Word 1 (RGD1_WORD1) 32 RW 0000_001Fh
418h Region Descriptor 1, Word 2 (RGD1_WORD2) 32 RW 0000_0000h
41Ch Region Descriptor 1, Word 3 (RGD1_WORD3) 32 RW 0000_0000h
420h Region Descriptor 2, Word 0 (RGD2_WORD0) 32 RW 0000_0000h
424h Region Descriptor 2, Word 1 (RGD2_WORD1) 32 RW 0000_001Fh
428h Region Descriptor 2, Word 2 (RGD2_WORD2) 32 RW 0000_0000h
42Ch Region Descriptor 2, Word 3 (RGD2_WORD3) 32 RW 0000_0000h
430h Region Descriptor 3, Word 0 (RGD3_WORD0) 32 RW 0000_0000h
434h Region Descriptor 3, Word 1 (RGD3_WORD1) 32 RW 0000_001Fh
438h Region Descriptor 3, Word 2 (RGD3_WORD2) 32 RW 0000_0000h
43Ch Region Descriptor 3, Word 3 (RGD3_WORD3) 32 RW 0000_0000h
440h Region Descriptor 4, Word 0 (RGD4_WORD0) 32 RW 0000_0000h
444h Region Descriptor 4, Word 1 (RGD4_WORD1) 32 RW 0000_001Fh
448h Region Descriptor 4, Word 2 (RGD4_WORD2) 32 RW 0000_0000h
44Ch Region Descriptor 4, Word 3 (RGD4_WORD3) 32 RW 0000_0000h
450h Region Descriptor 5, Word 0 (RGD5_WORD0) 32 RW 0000_0000h
454h Region Descriptor 5, Word 1 (RGD5_WORD1) 32 RW 0000_001Fh
458h Region Descriptor 5, Word 2 (RGD5_WORD2) 32 RW 0000_0000h
45Ch Region Descriptor 5, Word 3 (RGD5_WORD3) 32 RW 0000_0000h
460h Region Descriptor 6, Word 0 (RGD6_WORD0) 32 RW 0000_0000h
464h Region Descriptor 6, Word 1 (RGD6_WORD1) 32 RW 0000_001Fh
468h Region Descriptor 6, Word 2 (RGD6_WORD2) 32 RW 0000_0000h
46Ch Region Descriptor 6, Word 3 (RGD6_WORD3) 32 RW 0000_0000h
470h Region Descriptor 7, Word 0 (RGD7_WORD0) 32 RW 0000_0000h
474h Region Descriptor 7, Word 1 (RGD7_WORD1) 32 RW 0000_001Fh
478h Region Descriptor 7, Word 2 (RGD7_WORD2) 32 RW 0000_0000h
47Ch Region Descriptor 7, Word 3 (RGD7_WORD3) 32 RW 0000_0000h
480h Region Descriptor 8, Word 0 (RGD8_WORD0) 32 RW 0000_0000h
484h Region Descriptor 8, Word 1 (RGD8_WORD1) 32 RW 0000_001Fh
488h Region Descriptor 8, Word 2 (RGD8_WORD2) 32 RW 0000_0000h
48Ch Region Descriptor 8, Word 3 (RGD8_WORD3) 32 RW 0000_0000h
490h Region Descriptor 9, Word 0 (RGD9_WORD0) 32 RW 0000_0000h
494h Region Descriptor 9, Word 1 (RGD9_WORD1) 32 RW 0000_001Fh

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Offset Register Width Access Reset value

(In bits)
498h Region Descriptor 9, Word 2 (RGD9_WORD2) 32 RW 0000_0000h
49Ch Region Descriptor 9, Word 3 (RGD9_WORD3) 32 RW 0000_0000h
4A0h Region Descriptor 10, Word 0 (RGD10_WORD0) 32 RW 0000_0000h
4A4h Region Descriptor 10, Word 1 (RGD10_WORD1) 32 RW 0000_001Fh
4A8h Region Descriptor 10, Word 2 (RGD10_WORD2) 32 RW 0000_0000h
4ACh Region Descriptor 10, Word 3 (RGD10_WORD3) 32 RW 0000_0000h
4B0h Region Descriptor 11, Word 0 (RGD11_WORD0) 32 RW 0000_0000h
4B4h Region Descriptor 11, Word 1 (RGD11_WORD1) 32 RW 0000_001Fh
4B8h Region Descriptor 11, Word 2 (RGD11_WORD2) 32 RW 0000_0000h
4BCh Region Descriptor 11, Word 3 (RGD11_WORD3) 32 RW 0000_0000h
4C0h Region Descriptor 12, Word 0 (RGD12_WORD0) 32 RW 0000_0000h
4C4h Region Descriptor 12, Word 1 (RGD12_WORD1) 32 RW 0000_001Fh
4C8h Region Descriptor 12, Word 2 (RGD12_WORD2) 32 RW 0000_0000h
4CCh Region Descriptor 12, Word 3 (RGD12_WORD3) 32 RW 0000_0000h
4D0h Region Descriptor 13, Word 0 (RGD13_WORD0) 32 RW 0000_0000h
4D4h Region Descriptor 13, Word 1 (RGD13_WORD1) 32 RW 0000_001Fh
4D8h Region Descriptor 13, Word 2 (RGD13_WORD2) 32 RW 0000_0000h
4DCh Region Descriptor 13, Word 3 (RGD13_WORD3) 32 RW 0000_0000h
4E0h Region Descriptor 14, Word 0 (RGD14_WORD0) 32 RW 0000_0000h
4E4h Region Descriptor 14, Word 1 (RGD14_WORD1) 32 RW 0000_001Fh
4E8h Region Descriptor 14, Word 2 (RGD14_WORD2) 32 RW 0000_0000h
4ECh Region Descriptor 14, Word 3 (RGD14_WORD3) 32 RW 0000_0000h
4F0h Region Descriptor 15, Word 0 (RGD15_WORD0) 32 RW 0000_0000h
4F4h Region Descriptor 15, Word 1 (RGD15_WORD1) 32 RW 0000_001Fh
4F8h Region Descriptor 15, Word 2 (RGD15_WORD2) 32 RW 0000_0000h
4FCh Region Descriptor 15, Word 3 (RGD15_WORD3) 32 RW 0000_0000h
800h Region Descriptor Alternate Access Control 0 (RGDAAC0) 32 RW 0061_F7DFh
804h Region Descriptor Alternate Access Control 1 (RGDAAC1) 32 RW 0000_0000h
808h Region Descriptor Alternate Access Control 2 (RGDAAC2) 32 RW 0000_0000h
80Ch Region Descriptor Alternate Access Control 3 (RGDAAC3) 32 RW 0000_0000h
810h Region Descriptor Alternate Access Control 4 (RGDAAC4) 32 RW 0000_0000h
814h Region Descriptor Alternate Access Control 5 (RGDAAC5) 32 RW 0000_0000h
818h Region Descriptor Alternate Access Control 6 (RGDAAC6) 32 RW 0000_0000h
81Ch Region Descriptor Alternate Access Control 7 (RGDAAC7) 32 RW 0000_0000h
820h Region Descriptor Alternate Access Control 8 (RGDAAC8) 32 RW 0000_0000h
824h Region Descriptor Alternate Access Control 9 (RGDAAC9) 32 RW 0000_0000h
828h Region Descriptor Alternate Access Control 10 (RGDAAC10) 32 RW 0000_0000h
82Ch Region Descriptor Alternate Access Control 11 (RGDAAC11) 32 RW 0000_0000h
830h Region Descriptor Alternate Access Control 12 (RGDAAC12) 32 RW 0000_0000h
834h Region Descriptor Alternate Access Control 13 (RGDAAC13) 32 RW 0000_0000h

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MPU register descriptions

Offset Register Width Access Reset value

(In bits)
838h Region Descriptor Alternate Access Control 14 (RGDAAC14) 32 RW 0000_0000h
83Ch Region Descriptor Alternate Access Control 15 (RGDAAC15) 32 RW 0000_0000h

15.4.2 Control/Error Status Register (CESR)

15.4.2.1 Offset
Register Offset
CESR 0h

15.4.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W1C SPERR

W1C SPERR

W1C SPERR

W1C SPERR

W1C SPERR

HRL
R
0

0
0

Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R NSP NRGD 0
VLD
W
Reset 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1

15.4.2.3 Fields
Field Function
31 Slave Port 0 Error
SPERR0 Indicates a captured error in EAR0 and EDR0. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 0.
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Field Function
1b - An error has occurred for slave port 0.
30 Slave Port 1 Error
SPERR1 Indicates a captured error in EAR1 and EDR1. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 1.
1b - An error has occurred for slave port 1.
29 Slave Port 2 Error
SPERR2 Indicates a captured error in EAR2 and EDR2. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 2.
1b - An error has occurred for slave port 2.
28 Slave Port 3 Error
SPERR3 Indicates a captured error in EAR3 and EDR3. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 3.
1b - An error has occurred for slave port 3.
27 Slave Port 4 Error
SPERR4 Indicates a captured error in EAR4 and EDR4. This bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at
the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can
detect the presence of a captured error.
0b - No error has occurred for slave port 4.
1b - An error has occurred for slave port 4.
26 Reserved
—
25 Reserved
—
24 Reserved
—
23 Reserved
—
22-20 Reserved
—
19-16 Hardware Revision Level
HRL Specifies the MPU’s hardware and definition revision level. It can be read by software to determine the
functional definition of the module.
15-12 Number Of Slave Ports
NSP Specifies the number of slave ports connected to the MPU.
11-8 Number Of Region Descriptors
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MPU register descriptions

Field Function
NRGD Indicates the number of region descriptors implemented in the MPU.
0000b - 8 region descriptors
0001b - 12 region descriptors
0010b - 16 region descriptors
7-1 Reserved
—
0 Valid
VLD Global enable/disable for the MPU.
0b - MPU is disabled. All accesses from all bus masters are allowed.
1b - MPU is enabled

15.4.3 Error Address Register, slave port n (EAR0 - EAR4)

15.4.3.1 Offset
Register Offset
EAR0 10h
EAR1 18h
EAR2 20h
EAR3 28h
EAR4 30h

15.4.3.2 Function
When the MPU detects an access error on slave port n, the 32-bit reference address is
captured in this read-only register and the corresponding bit in CESR[SPERRn] is set.
Additional information about the faulting access is captured in the corresponding EDRn
at the same time. This register and the corresponding EDRn contain the most recent
access error; there are no hardware interlocks with CESR[SPERRn], as the error registers
are always loaded upon the occurrence of each protection violation.

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15.4.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R EADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R EADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15.4.3.4 Fields
Field Function
31-0 Error Address
EADDR Indicates the reference address from slave port n that generated the access error

15.4.4 Error Detail Register, slave port n (EDR0 - EDR4)

15.4.4.1 Offset
Register Offset
EDR0 14h
EDR1 1Ch
EDR2 24h
EDR3 2Ch
EDR4 34h

15.4.4.2 Function
When the MPU detects an access error on slave port n, 32 bits of error detail are captured
in this read-only register and the corresponding bit in CESR[SPERRn] is set. Information
on the faulting address is captured in the corresponding EARn register at the same time.
This register and the corresponding EARn register contain the most recent access error;
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MPU register descriptions

there are no hardware interlocks with CESR[SPERRn] as the error registers are always
loaded upon the occurrence of each protection violation.

15.4.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R EACD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R EPID EMN EATTR ERW

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15.4.4.4 Fields
Field Function
31-16 Error Access Control Detail
EACD Indicates the region descriptor with the access error.
• If EDRn contains a captured error and EACD is cleared, an access did not hit in any region
descriptor.
• If only a single EACD bit is set, the protection error was caused by a single non-overlapping region
descriptor.
• If two or more EACD bits are set, the protection error was caused by an overlapping set of region
descriptors.
15-8 Error Process Identification
EPID Records the process identifier of the faulting reference. The process identifier is typically driven only by
processor cores; for other bus masters, this field is cleared.
7-4 Error Master Number
EMN Indicates the bus master that generated the access error.
3-1 Error Attributes
EATTR Indicates attribute information about the faulting reference.
NOTE: All other encodings are reserved.
000b - User mode, instruction access
001b - User mode, data access
010b - Supervisor mode, instruction access
011b - Supervisor mode, data access
0 Error Read/Write
ERW Indicates the access type of the faulting reference.
0b - Read
1b - Write

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15.4.5 Region Descriptor n, Word 0 (RGD0_WORD0 - RGD15_WO

RD0)

15.4.5.1 Offset
For n = 0 to 15:
Register Offset
RGDn_WORD0 400h + (n × 10h)

15.4.5.2 Function
The first word of the region descriptor defines the 0-modulo-32 byte start address of the
memory region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).

15.4.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
SRTADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0
SRTADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15.4.5.4 Fields
Field Function
31-5 Start Address
SRTADDR Defines the most significant bits of the 0-modulo-32 byte start address of the memory region.
4-0 Reserved
—

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15.4.6 Region Descriptor 0, Word 1 (RGD0_WORD1)

15.4.6.1 Offset
Register Offset
RGD0_WORD1 404h

15.4.6.2 Function
The second word of the region descriptor defines the 31-modulo-32 byte end address of
the memory region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).

15.4.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
ENDADDR
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R Reserved
ENDADDR
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15.4.6.4 Fields
Field Function
31-5 End Address
ENDADDR Defines the most significant bits of the 31-modulo-32 byte end address of the memory region.
NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR.
4-0 Reserved
—

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15.4.7 Region Descriptor 0, Word 2 (RGD0_WORD2)

15.4.7.1 Offset
Register Offset
RGD0_WORD2 408h

15.4.7.2 Function
The third word of the region descriptor defines the access control rights of the memory
region. The access control privileges depend on two broad classifications of bus masters:
• Bus masters 0–3 have a 5-bit field defining separate privilege rights for user and
supervisor mode accesses. Each of these bus masters optionally includes a process
identification field (if implemented for the master) within the definition.
• Bus masters 4–7 are limited to separate read and write permissions.
For the privilege rights of bus masters 0–3, there are three flags associated with this
function:
• Read (r) refers to accessing the referenced memory address using an operand (data)
fetch
• Write (w) refers to updating the referenced memory address using a store (data)
instruction
• Execute (x) refers to reading the referenced memory address using an instruction
fetch
Writes to RGDn_WORD2 clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn
instead because stores to these locations do not affect the descriptor’s valid bit.

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15.4.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reserved
M7WE

M6WE

M5WE

M4WE
M7RE

M6RE

M5RE

M4RE

M3SM

M2SM
M3UM
W

Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
M2SM

M1PE

M1SM

M0PE

M0SM
M2UM

M1UM

M0UM
W
Reset 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1

15.4.7.4 Fields
Field Function
31 Bus Master 7 Read Enable
0b - Bus master 7 reads terminate with an access error and the read is not performed
M7RE
1b - Bus master 7 reads allowed
30 Bus Master 7 Write Enable
0b - Bus master 7 writes terminate with an access error and the write is not performed
M7WE
1b - Bus master 7 writes allowed
29 Bus Master 6 Read Enable
0b - Bus master 6 reads terminate with an access error and the read is not performed
M6RE
1b - Bus master 6 reads allowed
28 Bus Master 6 Write Enable
0b - Bus master 6 writes terminate with an access error and the write is not performed
M6WE
1b - Bus master 6 writes allowed
27 Bus Master 5 Read Enable
0b - Bus master 5 reads terminate with an access error and the read is not performed
M5RE
1b - Bus master 5 reads allowed
26 Bus Master 5 Write Enable
0b - Bus master 5 writes terminate with an access error and the write is not performed
M5WE
1b - Bus master 5 writes allowed
25 Bus Master 4 Read Enable
0b - Bus master 4 reads terminate with an access error and the read is not performed
M4RE
1b - Bus master 4 reads allowed
24 Bus Master 4 Write Enable
0b - Bus master 4 writes terminate with an access error and the write is not performed
M4WE
1b - Bus master 4 writes allowed
23 Reserved
— This bit must be written with a zero.
22-21 Bus Master 3 Supervisor Mode Access Control
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Field Function
M3SM Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18 Bus Master 3 User Mode Access Control
M3UM Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17 Reserved
— This bit must be written with a zero.
16-15 Bus Master 2 Supervisor Mode Access Control
M2SM Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M2UM
14-12 Bus Master 2 User Mode Access control
M2UM Defines the access controls for bus master 2 in User mode. M2UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M2UM[2:0]: M2UM[2] controls read
permissions, M2UM[1] controls write permissions, and M2UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
11 Bus Master 1 Process Identifier enable
0b - Do not include the process identifier in the evaluation
M1PE
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
10-9 Bus Master 1 Supervisor Mode Access Control
M1SM Defines the access controls for bus master 1 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M1UM
8-6 Bus Master 1 User Mode Access Control
M1UM Defines the access controls for bus master 1 in User mode. M1UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M1UM[2:0]: M1UM[2] controls read
permissions, M1UM[1] controls write permissions, and M1UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
5 Bus Master 0 Process Identifier enable
0b - Do not include the process identifier in the evaluation
M0PE
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
4-3 Bus Master 0 Supervisor Mode Access Control
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Field Function
M0SM Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0 Bus Master 0 User Mode Access Control
M0UM Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur

15.4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)

15.4.8.1 Offset
Register Offset
RGD0_WORD3 40Ch

15.4.8.2 Function
The fourth word of the region descriptor contains the optional process identifier and
mask, plus the region descriptor’s valid bit.

15.4.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
PID PIDMASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0
VLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

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15.4.8.4 Fields
Field Function
31-24 Process Identifier
PID Specifies the process identifier that is included in the region hit determination if RGDn_WORD2[MxPE] is
set. PIDMASK can mask individual bits in this field.
23-16 Process Identifier Mask
PIDMASK Provides a masking capability so that multiple process identifiers can be included as part of the region hit
determination. If a bit in PIDMASK is set, then the corresponding PID bit is ignored in the comparison.
This field and PID are included in the region hit determination if RGDn_WORD2[MxPE] is set. For more
information on the handling of the PID and PIDMASK, see “Access Evaluation - Hit Determination.”
15-1 Reserved
—
0 Valid
VLD Signals the region descriptor is valid. Any write to RGDn_WORD0–2 clears this bit.
0b - Region descriptor is invalid
1b - Region descriptor is valid

15.4.9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WO

RD1)

15.4.9.1 Offset
For n = 1 to 15:
Register Offset
RGDn_WORD1 404h + (n × 10h)

15.4.9.2 Function
The second word of the region descriptor defines the 31-modulo-32 byte end address of
the memory region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).

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15.4.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
ENDADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R Reserved
ENDADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1

15.4.9.4 Fields
Field Function
31-5 End Address
ENDADDR Defines the most significant bits of the 31-modulo-32 byte end address of the memory region.
NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR.
4-0 Reserved
—

15.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_

WORD2)

15.4.10.1 Offset
For n = 1 to 15:
Register Offset
RGDn_WORD2 408h + (n × 10h)

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15.4.10.2 Function
The third word of the region descriptor defines the access control rights of the memory
region. The access control privileges depend on two broad classifications of bus masters:
• Bus masters 0–3 have a 5-bit field defining separate privilege rights for user and
supervisor mode accesses. Each of these bus masters optionally includes a process
identification field (if implemented for the master) within the definition.
• Bus masters 4–7 are limited to separate read and write permissions.
For the privilege rights of bus masters 0–3, there are three flags associated with this
function:
• Read (r) refers to accessing the referenced memory address using an operand (data)
fetch
• Write (w) refers to updating the referenced memory address using a store (data)
instruction
• Execute (x) refers to reading the referenced memory address using an instruction
fetch
Writes to RGDn_WORD2 clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn
instead because stores to these locations do not affect the descriptor’s valid bit.

15.4.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved

Reserved
M7WE

M6WE

M5WE

M4WE
M7RE

M6RE

M5RE

M4RE

M3SM

M2SM
M3UM

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
M2SM

M1PE

M1SM

M0PE

M0SM
M2UM

M1UM

M0UM

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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15.4.10.4 Fields
Field Function
31 Bus Master 7 Read Enable
0b - Bus master 7 reads terminate with an access error and the read is not performed
M7RE
1b - Bus master 7 reads allowed
30 Bus Master 7 Write Enable
0b - Bus master 7 writes terminate with an access error and the write is not performed
M7WE
1b - Bus master 7 writes allowed
29 Bus Master 6 Read Enable
0b - Bus master 6 reads terminate with an access error and the read is not performed
M6RE
1b - Bus master 6 reads allowed
28 Bus Master 6 Write Enable
0b - Bus master 6 writes terminate with an access error and the write is not performed
M6WE
1b - Bus master 6 writes allowed
27 Bus Master 5 Read Enable
0b - Bus master 5 reads terminate with an access error and the read is not performed
M5RE
1b - Bus master 5 reads allowed
26 Bus Master 5 Write Enable
0b - Bus master 5 writes terminate with an access error and the write is not performed
M5WE
1b - Bus master 5 writes allowed
25 Bus Master 4 Read Enable
0b - Bus master 4 reads terminate with an access error and the read is not performed
M4RE
1b - Bus master 4 reads allowed
24 Bus Master 4 Write Enable
0b - Bus master 4 writes terminate with an access error and the write is not performed
M4WE
1b - Bus master 4 writes allowed
23 Reserved
— This bit must be written with a zero.
22-21 Bus Master 3 Supervisor Mode Access Control
M3SM Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18 Bus Master 3 User Mode Access Control
M3UM Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17 Reserved
— This bit must be written with a zero.
16-15 Bus Master 2 Supervisor Mode Access Control
M2SM Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
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Field Function
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M2UM
14-12 Bus Master 2 User Mode Access control
M2UM Defines the access controls for bus master 2 in User mode. M2UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M2UM[2:0]: M2UM[2] controls read
permissions, M2UM[1] controls write permissions, and M2UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
11 Bus Master 1 Process Identifier enable
0b - Do not include the process identifier in the evaluation
M1PE
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
10-9 Bus Master 1 Supervisor Mode Access Control
M1SM Defines the access controls for bus master 1 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M1UM
8-6 Bus Master 1 User Mode Access Control
M1UM Defines the access controls for bus master 1 in User mode. M1UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M1UM[2:0]: M1UM[2] controls read
permissions, M1UM[1] controls write permissions, and M1UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
5 Bus Master 0 Process Identifier enable
0b - Do not include the process identifier in the evaluation
M0PE
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
4-3 Bus Master 0 Supervisor Mode Access Control
M0SM Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0 Bus Master 0 User Mode Access Control
M0UM Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur

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15.4.11 Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_

WORD3)

15.4.11.1 Offset
For n = 1 to 15:
Register Offset
RGDn_WORD3 40Ch + (n × 10h)

15.4.11.2 Function
The fourth word of the region descriptor contains the optional process identifier and
mask, plus the region descriptor’s valid bit.

15.4.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
PID PIDMASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0
VLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15.4.11.4 Fields
Field Function
31-24 Process Identifier
PID Specifies the process identifier that is included in the region hit determination if RGDn_WORD2[MxPE] is
set. PIDMASK can mask individual bits in this field.
23-16 Process Identifier Mask
PIDMASK Provides a masking capability so that multiple process identifiers can be included as part of the region hit
determination. If a bit in PIDMASK is set, then the corresponding PID bit is ignored in the comparison.
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Field Function
This field and PID are included in the region hit determination if RGDn_WORD2[MxPE] is set. For more
information on the handling of the PID and PIDMASK, see “Access Evaluation - Hit Determination.”
15-1 Reserved
—
0 Valid
VLD Signals the region descriptor is valid. Any write to RGDn_WORD0–2 clears this bit.
0b - Region descriptor is invalid
1b - Region descriptor is valid

15.4.12 Region Descriptor Alternate Access Control 0 (RGDA

AC0)

15.4.12.1 Offset
Register Offset
RGDAAC0 800h

15.4.12.2 Function
Because software may adjust only the access controls within a region descriptor
(RGDn_WORD2) as different tasks execute, an alternate programming view of this 32-
bit entity is available. Writing to this register does not affect the descriptor’s valid bit.

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15.4.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reserved
M7WE

M6WE

M5WE

M4WE
M7RE

M6RE

M5RE

M4RE

M3SM

M2SM
M3UM
W

Reset
0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1
1

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
M2SM

M1PE

M1SM

M0PE

M0SM
M2UM

M1UM

M0UM
W
Reset 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1

1. RGDAAC0 resets to 61F7DFh. Other RGDAACn registers reset to 0h.

15.4.12.4 Fields
Field Function
31 Bus Master 7 Read Enable
0b - Bus master 7 reads terminate with an access error and the read is not performed
M7RE
1b - Bus master 7 reads allowed
30 Bus Master 7 Write Enable
0b - Bus master 7 writes terminate with an access error and the write is not performed
M7WE
1b - Bus master 7 writes allowed
29 Bus Master 6 Read Enable
0b - Bus master 6 reads terminate with an access error and the read is not performed
M6RE
1b - Bus master 6 reads allowed
28 Bus Master 6 Write Enable
0b - Bus master 6 writes terminate with an access error and the write is not performed
M6WE
1b - Bus master 6 writes allowed
27 Bus Master 5 Read Enable
0b - Bus master 5 reads terminate with an access error and the read is not performed
M5RE
1b - Bus master 5 reads allowed
26 Bus Master 5 Write Enable
0b - Bus master 5 writes terminate with an access error and the write is not performed
M5WE
1b - Bus master 5 writes allowed
25 Bus Master 4 Read Enable
0b - Bus master 4 reads terminate with an access error and the read is not performed
M4RE
1b - Bus master 4 reads allowed
24 Bus Master 4 Write Enable
0b - Bus master 4 writes terminate with an access error and the write is not performed
M4WE
1b - Bus master 4 writes allowed
23 Reserved
— This bit must be written with a zero.

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Field Function
22-21 Bus Master 3 Supervisor Mode Access Control
M3SM Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18 Bus Master 3 User Mode Access Control
M3UM Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17 Reserved
— This bit must be written with a zero.
16-15 Bus Master 2 Supervisor Mode Access Control
M2SM Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M2UM
14-12 Bus Master 2 User Mode Access Control
M2UM Defines the access controls for bus master 2 in User mode. M2UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M2UM[2:0]: M2UM[2] controls read
permissions, M2UM[1] controls write permissions, and M2UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
11 Bus Master 1 Process Identifier Enable
M1PE NOTE: For RGDAAC0: Only bus master 1 can write to M1PE.
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
10-9 Bus Master 1 Supervisor Mode Access Control
M1SM Defines the access controls for bus master 1 in Supervisor mode.

NOTE: For RGDAAC0: Only bus master 1 can write to M1SM.

00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M1UM
8-6 Bus Master 1 User Mode Access Control
M1UM Defines the access controls for bus master 1 in User mode. M1UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M1UM[2:0]: M1UM[2] controls read
permissions, M1UM[1] controls write permissions, and M1UM[0] controls execute permissions.

NOTE: For RGDAAC0: Only bus master 1 can write to M1UM.

For each bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
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Field Function
1b - Allows the given access type to occur
5 Bus Master 0 Process Identifier Enable
0b - Do not include the process identifier in the evaluation
M0PE
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
4-3 Bus Master 0 Supervisor Mode Access Control
M0SM Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0 Bus Master 0 User Mode Access Control
M0UM Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur

15.4.13 Region Descriptor Alternate Access Control n (RGDA

AC1 - RGDAAC15)

15.4.13.1 Offset
For n = 1 to 15:
Register Offset
RGDAACn 800h + (n × 4h)

15.4.13.2 Function
Because software may adjust only the access controls within a region descriptor
(RGDn_WORD2) as different tasks execute, an alternate programming view of this 32-
bit entity is available. Writing to this register does not affect the descriptor’s valid bit.

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15.4.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reserved
M7WE

M6WE

M5WE

M4WE
M7RE

M6RE

M5RE

M4RE

M3SM

M2SM
M3UM
W

Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
M2SM

M1PE

M1SM

M0PE

M0SM
M2UM

M1UM

M0UM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1. RGDAAC0 resets to 61F7DFh. Other RGDAACn registers reset to 0h.

15.4.13.4 Fields
Field Function
31 Bus Master 7 Read Enable
0b - Bus master 7 reads terminate with an access error and the read is not performed
M7RE
1b - Bus master 7 reads allowed
30 Bus Master 7 Write Enable
0b - Bus master 7 writes terminate with an access error and the write is not performed
M7WE
1b - Bus master 7 writes allowed
29 Bus Master 6 Read Enable
0b - Bus master 6 reads terminate with an access error and the read is not performed
M6RE
1b - Bus master 6 reads allowed
28 Bus Master 6 Write Enable
0b - Bus master 6 writes terminate with an access error and the write is not performed
M6WE
1b - Bus master 6 writes allowed
27 Bus Master 5 Read Enable
0b - Bus master 5 reads terminate with an access error and the read is not performed
M5RE
1b - Bus master 5 reads allowed
26 Bus Master 5 Write Enable
0b - Bus master 5 writes terminate with an access error and the write is not performed
M5WE
1b - Bus master 5 writes allowed
25 Bus Master 4 Read Enable
0b - Bus master 4 reads terminate with an access error and the read is not performed
M4RE
1b - Bus master 4 reads allowed
24 Bus Master 4 Write Enable
0b - Bus master 4 writes terminate with an access error and the write is not performed
M4WE
1b - Bus master 4 writes allowed
23 Reserved
— This bit must be written with a zero.

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MPU register descriptions

Field Function
22-21 Bus Master 3 Supervisor Mode Access Control
M3SM Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18 Bus Master 3 User Mode Access Control
M3UM Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17 Reserved
— This bit must be written with a zero.
16-15 Bus Master 2 Supervisor Mode Access Control
M2SM Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M2UM
14-12 Bus Master 2 User Mode Access Control
M2UM Defines the access controls for bus master 2 in User mode. M2UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M2UM[2:0]: M2UM[2] controls read
permissions, M2UM[1] controls write permissions, and M2UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
11 Bus Master 1 Process Identifier Enable
M1PE NOTE: For RGDAAC0: Only bus master 1 can write to M1PE.
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
10-9 Bus Master 1 Supervisor Mode Access Control
M1SM Defines the access controls for bus master 1 in Supervisor mode.

NOTE: For RGDAAC0: Only bus master 1 can write to M1SM.

00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M1UM
8-6 Bus Master 1 User Mode Access Control
M1UM Defines the access controls for bus master 1 in User mode. M1UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M1UM[2:0]: M1UM[2] controls read
permissions, M1UM[1] controls write permissions, and M1UM[0] controls execute permissions.

NOTE: For RGDAAC0: Only bus master 1 can write to M1UM.

For each bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
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Field Function
1b - Allows the given access type to occur
5 Bus Master 0 Process Identifier Enable
0b - Do not include the process identifier in the evaluation
M0PE
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
4-3 Bus Master 0 Supervisor Mode Access Control
M0SM Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0 Bus Master 0 User Mode Access Control
M0UM Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur

15.5 Functional description

In this section, the functional operation of the MPU is detailed, including the operation of
the access evaluation macro and the handling of error-terminated bus cycles.

15.5.1 Access evaluation macro

The basic operation of the MPU is performed in the access evaluation macro, a hardware
structure replicated in the two-dimensional connection matrix. As shown in the following
figure, the access evaluation macro inputs the crossbar bus address phase signals and the
contents of a region descriptor (RGDn) and performs two major functions:
• Region hit determination
• Detection of an access protection violation
The following figure shows a functional block diagram.

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Functional description
RGDn
Address start end
r,w,x

≥ ≤

hit_b error

≥ ≥

MPU_EDRn Access not allowed

(hit AND error) (no hit OR error)

Figure 15-2. MPU access evaluation macro

15.5.1.1 Hit determination

To determine whether the current reference hits in the given region, two magnitude
comparators are used with the region's start and end addresses. The boolean equation for
this portion of the hit determination is:
region_hit = ((addr[31:5] >= RGDn_Word0[SRTADDR]) & (addr[31:5] <= RGDn_Word1[ENDADDR])) &
RGDn_Word3[VLD]

where addr is the current reference address, RGDn_Word0[SRTADDR] and

RGDn_Word1[ENDADDR] are the start and end addresses, and RGDn_Word3[VLD] is
the valid bit.
NOTE
The MPU does not verify that ENDADDR ≥ SRTADDR.
In addition to the comparison of the reference address versus the region descriptor's start
and end addresses, the optional process identifier is examined against the region
descriptor's PID and PIDMASK fields. A process identifier hit term is formed as follows:
pid_hit = ~RGDn_Word2[MxPE] |
((current_pid |
RGDn_Word3[PIDMASK]) == (RGDn_Word3[PID] | RGDn_Word3[PIDMASK]))

where the current_pid is the selected process identifier from the current bus master, and
RGDn_Word3[PID] and RGDn_Word3[PIDMASK] are the process identifier fields from
region descriptor n. For bus masters that do not output a process identifier, the MPU
forces the pid_hit term to assert.

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15.5.1.2 Privilege violation determination

While the access evaluation macro is determining region hit, the logic is also evaluating
if the current access is allowed by the permissions defined in the region descriptor. Using
the master and supervisor/user mode signals, a set of effective permissions is generated
from the appropriate fields in the region descriptor. The protection violation logic then
evaluates the access against the effective permissions as shown in the following table.
Table 15-5. Protection violation definition
MxUM
Description Protection violation?
r w x
— — 0 Yes, no execute permission
Instruction fetch read
— — 1 No, access is allowed
0 — — Yes, no read permission
Data read
1 — — No, access is allowed
— 0 — Yes, no write permission
Data write
— 1 — No, access is allowed

15.5.2 Putting it all together and error terminations

For each slave port monitored, the MPU performs a reduction-AND of all the individual
terms from each access evaluation macro. This expression then terminates the bus cycle
with an error and reports a protection error for three conditions:
• If the access does not hit in any region descriptor, a protection error is reported.
• If the access hits in a single region descriptor and that region signals a protection
violation, a protection error is reported.
• If the access hits in multiple (overlapping) regions and all regions signal protection
violations, a protection error is reported.

As shown in the third condition, granting permission is a higher priority than denying
access for overlapping regions. This approach is more flexible to system software in
region descriptor assignments. For an example of the use of overlapping region
descriptors, see Application information.

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Initialization information

15.5.3 Power management

Disabling the MPU by clearing CESR[VLD] minimizes power dissipation. To minimize
the power dissipation of an enabled MPU, invalidate unused region descriptors by
clearing the associated RGDn_Word3[VLD] bits.

15.6 Initialization information

At system startup, load the appropriate number of region descriptors, including setting
RGDn_Word3[VLD]. Setting CESR[VLD] enables the module.
If the system requires that all the loaded region descriptors be enabled simultaneously,
first ensure that the entire MPU is disabled (CESR[VLD]=0).
Note
If the MPU registers are protected by the MPU, a region
descriptor must be set to allow access to the MPU registers if
further changes are needed.

15.7 Application information

In an operational system, interfacing with the MPU is generally classified into the
following activities:
• Creating a new memory region—Load the appropriate region descriptor into an
available RGDn, using four sequential 32-bit writes. The hardware assists in the
maintenance of the valid bit, so if this approach is followed, there are no coherency
issues with the multi-cycle descriptor writes. (Clearing RGDn_Word3[VLD] deletes/
removes an existing memory region.)
• Altering only access privileges—To not affect the valid bit, write to the alternate
version of the access control word (RGDAACn), so there are no coherency issues
involved with the update. When the write completes, the memory region's access
rights switch instantaneously to the new value.
• Changing a region's start and end addresses—Write a minimum of three words to the
region descriptor (RGDn_Word{0,1,3}). Word 0 and 1 redefine the start and end
addresses, respectively. Word 3 re-enables the region descriptor valid bit. In most
situations, all four words of the region descriptor are rewritten.

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• Accessing the MPU—Allocate a region descriptor to restrict MPU access to

supervisor mode from a specific master.
• Detecting an access error—The current bus cycle is terminated with an error
response and EARn and EDRn capture information on the faulting reference. The
error-terminated bus cycle typically initiates an error response in the originating bus
master. For example, a processor core may respond with a bus error exception, while
a data movement bus master may respond with an error interrupt. The processor can
retrieve the captured error address and detail information simply by reading
E{A,D}Rn. CESR[SPERR] signals which error registers contain captured fault data.
• Overlapping region descriptors—Applying overlapping regions often reduces the
number of descriptors required for a given set of access controls. In the overlapping
memory space, the protection rights of the corresponding region descriptors are
logically summed together (the boolean OR operator).
The following dual-core system example contains four bus masters:
• The two processors: CP0, CP1
• Two DMA engines: DMA1, a traditional data movement engine transferring data
between RAM and peripherals and DMA2, a second engine transferring data to/
from the RAM only
Consider the following region descriptor assignments:

Table 15-6. Overlapping region descriptor example

Region description RGDn CP0 CP1 DMA1 DMA2
CP0 code 0 rwx r-- — —
Flash
CP1 code 1 r-- rwx — —
CP0 data & stack 2 rw- — — —
CP0 → CP1 shared data 2
3 r-- r-- — —
CP1 → CP0 shared data 4 RAM
CP1 data & stack 4 — rw- — —
Shared DMA data 5 rw- rw- rw rw
MPU 6 rw- rw- — — Peripheral
Peripherals 7 rw- rw- rw — space

In this example, there are eight descriptors used to span nine regions in the three main
spaces of the system memory map: flash, RAM, and peripheral space. Each region
indicates the specific permissions for each of the four bus masters and this definition
provides an appropriate set of shared, private and executable memory spaces.
Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4.

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Application information

The space defined by RGD2 with no overlap is a private data and stack area that provides
read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines
a shared data space for passing data from CP0 to CP1 and the access controls are defined
by the logical OR of the two region descriptors. Thus, CP0 has (rw- | r--) = (rw-)
permissions, while CP1 has (--- | r--) = (r--) permission in this space. Both DMA engines
are excluded from this shared processor data region. The overlapping spaces between
RGD3 and RGD4 defines another shared data space, this one for passing data from CP1
to CP0. For this overlapping space, CP0 has (r-- | ---) = (r--) permission, while CP1 has
(rw- | r--) = (rw-) permission. The non-overlapped space of RGD4 defines a private data
and stack area for CP1 only.
The space defined by RGD5 is a shared data region, accessible by all four bus masters.
Finally, the slave peripheral space mapped onto the IPS bus is partitioned into two
regions:
• One containing the MPU's programming model accessible only to the two processor
cores
• The remaining peripheral region accessible to both processors and the traditional
DMA1 master
This example shows one possible application of the capabilities of the MPU in a typical
system.

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Chapter 16
Peripheral Bridge (AIPS-Lite)

16.1 Chip-specific AIPS information

16.1.1 Instantiation information

This device contains one peripheral bridge. The peripheral access protection is supported
by AIPS. The MPU will not cover peripheral access protection.

16.1.2 Memory maps

The peripheral bridge is used to access the registers of most of the modules on this
device. See S32K1xx_memory_map.xlsx attached to Reference Manual for the memory
slot assignment.
AIPS_PACR0 – PACR31 refer to on platform peripherals with corresponding AIPS
Peripheral bridge slot numbers from 0 -31. AIPS_OPACR0 – OPACR95 refer to off
platform peripherals with corresponding AIPS Peripheral bridge slot numbers from 32
-127. For logical master ID assignments see MPU Logical Bus Master Assignments.

16.1.2.1 Register reset values

The following table shows chip-specific reset values for AIPS registers:
Table 16-1. Register reset values
Register S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
MPRA 7770_0000 7770_0000 7770_0000 7770_0000 7770_0000 7777_0000
PACRA 5400_0000 5400_0000 5400_0000 5400_0000 5400_0000 5400_0000
PACRB 4400_0404 4400_0404 4400_0400 4400_0400 4400_0400 4400_0400
PACRD 4400_0000 4400_0000 4400_0000 4400_0000 4400_0000 4400_0000

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Introduction

Table 16-1. Register reset values (continued)

Register S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
OPACRA 4400_4000 4400_4000 4400_4444 4400_4444 4400_4444 4400_4444
OPACRB 0000_4000 0000_4400 0000_4400 0000_4400 0000_4400 0004_4440
OPACRC 0040_0044 0040_0044 0440_0044 0440_0044 0440_0044 0440_0044
OPACRD 4404_0444 4404_0444 4444_0400 4444_0400 4444_0400 4444_0400
OPACRE 4000_0040 4000_0040 4000_0040 4000_0040 4000_0040 4000_0040
OPACRF 4444_4400 4444_4400 4444_4400 4444_4400 4444_4400 4444_4400
OPACRG 0040_0000 0040_0000 0040_0000 0040_0000 0040_0000 0040_4400
OPACRH 0040_0000 0040_0000 0040_0000 0040_0000 0040_0000 0040_0000
OPACRI 0004_4440 0004_4440 0404_4440 0404_4440 0404_4440 0404_4444
OPACRJ 0044_0000 0044_0000 0044_0000 0044_0000 0044_4044 0044_4044
OPACRK 0004_0000 0004_0000 0004_0000 0004_0000 0004_0000 4404_0040
OPACRL 0000_0444 0000_0444 0000_0444 0000_0444 0000_0444 0400_0444

16.1.2.2 Register information

In S32K11x, CMU0 and CMU1 reside on Off-platform slots 30 and 31 respectively, and
access of the same is controlled by bits OPACRD[0:7] shown below. In S32K14x these
bits are Reserved as show in AIPS register descriptions.
Table 16-2. OPARCD register
Bit fields S32K14x S32K11x
Bitfiled[0:7] Reserved Bit 0: TP7 (Trusted Protect 7)
Bit 1: WP7 (Write Protect 7)
Bit 2: SP7 (Supervisor Protect 7)
Bit 3: Reserved
Bit 4: TP6 (Trusted Protect 6)
Bit 5: WP6 (Write Protect 6)
Bit 6: SP6 (Supervisor Protect 6)
Bit 7: Reserved

16.2 Introduction
The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip.

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The peripheral bridge occupies 64 MB of the address space, which is divided into
peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used.
See the memory map chapter for details on slot assignments.) The bridge includes
separate clock enable inputs for each of the slots to accommodate slower peripherals.

16.2.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
• Programming model provides memory protection functionality

16.2.2 General operation

The slave devices connected to the peripheral bridge are modules which contain a
programming model of control and status registers. The system masters read and write
these registers through the peripheral bridge.
The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is
allocated one or more 4-KB block(s) of the memory map.

16.3 Memory map/register definition

The 32-bit peripheral bridge registers can be accessed only in supervisor mode by trusted
bus masters. Additionally, these registers must be read from or written to only by a 32-bit
aligned access. The peripheral bridge registers are mapped into the Peripheral Access
Control Register A PACRA[PACR0] address space.

16.3.1 AIPS register descriptions

16.3.1.1 AIPS Memory map

AIPS_Lite base address: 4000_0000h

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Memory map/register definition

Offset Register Width Access Reset value

(In bits)
0h Master Privilege Register A (MPRA) 32 RW 2C36_0000h
20h Peripheral Access Control Register (PACRA) 32 RW 5400_0000h
24h Peripheral Access Control Register (PACRB) 32 RW 4400_0400h
2Ch Peripheral Access Control Register (PACRD) 32 RW 4400_0000h
40h Off-Platform Peripheral Access Control Register (OPACRA) 32 RW 4400_4444h
44h Off-Platform Peripheral Access Control Register (OPACRB) 32 RW 0004_4440h
48h Off-Platform Peripheral Access Control Register (OPACRC) 32 RW 0440_0044h
4Ch Off-Platform Peripheral Access Control Register (OPACRD) 32 RW 4444_0400h
50h Off-Platform Peripheral Access Control Register (OPACRE) 32 RW 4000_0040h
54h Off-Platform Peripheral Access Control Register (OPACRF) 32 RW 4444_4400h
58h Off-Platform Peripheral Access Control Register (OPACRG) 32 RW 0040_4400h
5Ch Off-Platform Peripheral Access Control Register (OPACRH) 32 RW 0040_0000h
60h Off-Platform Peripheral Access Control Register (OPACRI) 32 RW 0404_4444h
64h Off-Platform Peripheral Access Control Register (OPACRJ) 32 RW 0044_4044h
68h Off-Platform Peripheral Access Control Register (OPACRK) 32 RW 4404_0040h
6Ch Off-Platform Peripheral Access Control Register (OPACRL) 32 RW 0400_0444h

16.3.1.2 Master Privilege Register A (MPRA)

16.3.1.2.1 Offset
Register Offset
MPRA 0h

16.3.1.2.2 Function
The MPRA specifies identical 4-bit fields defining the access-privilege level associated
with a bus master to various peripherals on the chip. The register provides one field per
bus master.
A register field that maps to an unimplemented master or peripheral behaves as read-
only-zero.
Each master is assigned a logical ID from 0 to 15. See the master logical ID assignment
table in the chip-specific AIPS information.

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16.3.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
0

0
MTW0

MTW1

MTW2

MTW3
MTR0

MTR1

MTR2

MTR3
MPL0

MPL1

MPL2

MPL3
W
Reset 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
Reserved Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

16.3.1.2.4 Fields
Field Function
31 Reserved
—
30 Master 0 Trusted For Read
MTR0 Determines whether the master is trusted for read accesses.
0b - This master is not trusted for read accesses.
1b - This master is trusted for read accesses.
29 Master 0 Trusted For Writes
MTW0 Determines whether the master is trusted for write accesses.
0b - This master is not trusted for write accesses.
1b - This master is trusted for write accesses.
28 Master 0 Privilege Level
MPL0 Specifies how the privilege level of the master is determined.
0b - Accesses from this master are forced to user-mode.
1b - Accesses from this master are not forced to user-mode.
27 Reserved
—
26 Master 1 Trusted for Read
MTR1 Determines whether the master is trusted for read accesses.
0b - This master is not trusted for read accesses.
1b - This master is trusted for read accesses.
25 Master 1 Trusted for Writes
MTW1 Determines whether the master is trusted for write accesses.
0b - This master is not trusted for write accesses.
1b - This master is trusted for write accesses.
24 Master 1 Privilege Level
MPL1 Specifies how the privilege level of the master is determined.
0b - Accesses from this master are forced to user-mode.
1b - Accesses from this master are not forced to user-mode.

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Memory map/register definition

Field Function
23 Reserved
—
22 Master 2 Trusted For Read
MTR2 Determines whether the master is trusted for read accesses.
0b - This master is not trusted for read accesses.
1b - This master is trusted for read accesses.
21 Master 2 Trusted For Writes
MTW2 Determines whether the master is trusted for write accesses.
0b - This master is not trusted for write accesses.
1b - This master is trusted for write accesses.
20 Master 2 Privilege Level
MPL2 Specifies how the privilege level of the master is determined.
0b - Accesses from this master are forced to user-mode.
1b - Accesses from this master are not forced to user-mode.
19 Reserved
—
18 Master 3 Trusted For Read
MTR3 Determines whether the master is trusted for read accesses.
0b - This master is not trusted for read accesses.
1b - This master is trusted for read accesses.
17 Master 3 Trusted For Writes
MTW3 Determines whether the master is trusted for write accesses.
0b - This master is not trusted for write accesses.
1b - This master is trusted for write accesses.
16 Master 3 Privilege Level
MPL3 Specifies how the privilege level of the master is determined.
0b - Accesses from this master are forced to user-mode.
1b - Accesses from this master are not forced to user-mode.
15 Reserved
—
14-12 Reserved
—
11 Reserved
—
10-8 Reserved
—
7 Reserved
—
6-4 Reserved
—
3 Reserved
—
2-0 Reserved

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Field Function
—

16.3.1.3 Peripheral Access Control Register (PACRA)

16.3.1.3.1 Offset
Register Offset
PACRA 20h

16.3.1.3.2 Function
Each PACR register consists of eight 4-bit PACR fields. Each PACR field defines the
access levels for a particular on-platform peripheral. The peripheral assignment to each
PACR field is defined by the memory map slot of the peripheral. See the chip-specific
AIPS information for the field assignment of a particular peripheral.
Every PACR field to which no peripheral is assigned is reserved. Reads to reserved
locations return zeros, and writes are ignored.

16.3.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP0 WP0 TP0 SP1 WP1 TP1
W
Reset 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

16.3.1.3.4 Fields
Field Function
31 Reserved
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Field Function
—
30 Supervisor Protect
SP0 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29 Write Protect
WP0 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28 Trusted Protect
TP0 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27 Reserved
—
26 Supervisor Protect
SP1 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20 Reserved
—
19-16 Reserved
—
15-12 Reserved
—
11-8 Reserved
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Field Function
—
7-4 Reserved
—
3-0 Reserved
—

16.3.1.4 Peripheral Access Control Register (PACRB)

16.3.1.4.1 Offset
Register Offset
PACRB 24h

16.3.1.4.2 Function
Each PACR register consists of eight 4-bit PACR fields. Each PACR field defines the
access levels for a particular on-platform peripheral. The peripheral assignment to each
PACR field is defined by the memory map slot of the peripheral. See the chip-specific
AIPS information for the field assignment of a particular peripheral.
Every PACR field to which no peripheral is assigned is reserved. Reads to reserved
locations return zeros, and writes are ignored.

16.3.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP0 WP0 TP0 SP1 WP1 TP1
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP5 WP5 TP5
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

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16.3.1.4.4 Fields
Field Function
31 Reserved
—
30 Supervisor Protect
SP0 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29 Write Protect
WP0 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28 Trusted Protect
TP0 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27 Reserved
—
26 Supervisor Protect
SP1 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20 Reserved
—
19-16 Reserved
—
15-12 Reserved
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Field Function
—
11 Reserved
—
10 Supervisor Protect
SP5 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9 Write Protect
WP5 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8 Trusted Protect
TP5 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7-4 Reserved
—
3-0 Reserved
—

16.3.1.5 Peripheral Access Control Register (PACRD)

16.3.1.5.1 Offset
Register Offset
PACRD 2Ch

16.3.1.5.2 Function
Each PACR register consists of eight 4-bit PACR fields. Each PACR field defines the
access levels for a particular on-platform peripheral. The peripheral assignment to each
PACR field is defined by the memory map slot of the peripheral. See the chip-specific
AIPS information for the field assignment of a particular peripheral.

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Every PACR field to which no peripheral is assigned is reserved. Reads to reserved

locations return zeros, and writes are ignored.

16.3.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP0 WP0 TP0 SP1 WP1 TP1
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

16.3.1.5.4 Fields
Field Function
31 Reserved
—
30 Supervisor Protect
SP0 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29 Write Protect
WP0 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28 Trusted Protect
TP0 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27 Reserved
—
26 Supervisor Protect
SP1
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Field Function
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20 Reserved
—
19-16 Reserved
—
15-12 Reserved
—
11-8 Reserved
—
7-4 Reserved
—
3-0 Reserved
—

16.3.1.6 Off-Platform Peripheral Access Control Register (OPACRA)

16.3.1.6.1 Offset
Register Offset
OPACRA 40h

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16.3.1.6.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP0 WP0 TP0 SP1 WP1 TP1
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP4 WP4 TP4 SP5 WP5 TP5 SP6 WP6 TP6 SP7 WP7 TP7
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

16.3.1.6.4 Fields
Field Function
31 Reserved
—
30 Supervisor Protect
SP0 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29 Write Protect
WP0 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28 Trusted Protect
TP0 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27 Reserved
—

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Field Function
26 Supervisor Protect
SP1 Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20 Reserved
—
19-16 Reserved
—
15 Reserved
—
14 Supervisor Protect
SP4 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13 Write Protect
WP4 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12 Trusted Protect
TP4 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11 Reserved
—
10 Supervisor Protect
SP5
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Field Function
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9 Write Protect
WP5 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8 Trusted Protect
TP5 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7 Reserved
—
6 Supervisor Protect
SP6 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5 Write Protect
WP6 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4 Trusted Protect
TP6 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3 Reserved
—
2 Supervisor Protect
SP7 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
1 Write Protect
WP7
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Field Function
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0 Trusted Protect
TP7 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.

16.3.1.7 Off-Platform Peripheral Access Control Register (OPACRB)

16.3.1.7.1 Offset
Register Offset
OPACRB 44h

16.3.1.7.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP3 WP3 TP3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP4 WP4 TP4 SP5 WP5 TP5 SP6 WP6 TP6
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0

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16.3.1.7.4 Fields
Field Function
31-28 Reserved
—
27-24 Reserved
—
23-20 Reserved
—
19 Reserved
—
18 Supervisor Protect
SP3 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17 Write Protect
WP3 Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16 Trusted Protect
TP3 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15 Reserved
—
14 Supervisor Protect
SP4 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13 Write Protect
WP4 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12 Trusted Protect
TP4 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
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Field Function
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11 Reserved
—
10 Supervisor Protect
SP5 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9 Write Protect
WP5 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8 Trusted Protect
TP5 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7 Reserved
—
6 Supervisor Protect
SP6 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5 Write Protect
WP6 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4 Trusted Protect
TP6 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3-0 Reserved
—

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16.3.1.8 Off-Platform Peripheral Access Control Register (OPACRC)

16.3.1.8.1 Offset
Register Offset
OPACRC 48h

16.3.1.8.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP1 WP1 TP1 SP2 WP2 TP2
W
Reset 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP6 WP6 TP6 SP7 WP7 TP7
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0

16.3.1.8.4 Fields
Field Function
31-28 Reserved
—
27 Reserved
—
26 Supervisor Protect
SP1 Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.

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Field Function
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23 Reserved
—
22 Supervisor Protect
SP2 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21 Write Protect
WP2 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20 Trusted Protect
TP2 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19-16 Reserved
—
15-12 Reserved
—
11-8 Reserved
—
7 Reserved
—
6 Supervisor Protect
SP6 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.

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Field Function
5 Write Protect
WP6 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4 Trusted Protect
TP6 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3 Reserved
—
2 Supervisor Protect
SP7 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
1 Write Protect
WP7 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0 Trusted Protect
TP7 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.

16.3.1.9 Off-Platform Peripheral Access Control Register (OPACRD)

16.3.1.9.1 Offset
Register Offset
OPACRD 4Ch

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16.3.1.9.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP0 WP0 TP0 SP1 WP1 TP1 SP2 WP2 TP2 SP3 WP3 TP3
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP5 WP5 TP5
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

16.3.1.9.4 Fields
Field Function
31 Reserved
—
30 Supervisor Protect
SP0 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29 Write Protect
WP0 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28 Trusted Protect
TP0 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27 Reserved
—

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Field Function
26 Supervisor Protect
SP1 Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23 Reserved
—
22 Supervisor Protect
SP2 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21 Write Protect
WP2 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20 Trusted Protect
TP2 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19 Reserved
—
18 Supervisor Protect
SP3 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.

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Field Function
17 Write Protect
WP3 Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16 Trusted Protect
TP3 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15-12 Reserved
—
11 Reserved
—
10 Supervisor Protect
SP5 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9 Write Protect
WP5 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8 Trusted Protect
TP5 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7-4 Reserved
—
3-0 Reserved
—

16.3.1.10 Off-Platform Peripheral Access Control Register (OPACRE)

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16.3.1.10.1 Offset
Register Offset
OPACRE 50h

16.3.1.10.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP0 WP0 TP0
W
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP6 WP6 TP6
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

16.3.1.10.4 Fields
Field Function
31 Reserved
—
30 Supervisor Protect
SP0 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29 Write Protect
WP0 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.

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Field Function
28 Trusted Protect
TP0 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27-24 Reserved
—
23-20 Reserved
—
19-16 Reserved
—
15-12 Reserved
—
11-8 Reserved
—
7 Reserved
—
6 Supervisor Protect
SP6 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5 Write Protect
WP6 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4 Trusted Protect
TP6 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3-0 Reserved
—

16.3.1.11 Off-Platform Peripheral Access Control Register (OPACRF)

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16.3.1.11.1 Offset
Register Offset
OPACRF 54h

16.3.1.11.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP0 WP0 TP0 SP1 WP1 TP1 SP2 WP2 TP2 SP3 WP3 TP3
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP4 WP4 TP4 SP5 WP5 TP5
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0

16.3.1.11.4 Fields
Field Function
31 Reserved
—
30 Supervisor Protect
SP0 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29 Write Protect
WP0 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.

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Field Function
28 Trusted Protect
TP0 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27 Reserved
—
26 Supervisor Protect
SP1 Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23 Reserved
—
22 Supervisor Protect
SP2 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21 Write Protect
WP2 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20 Trusted Protect
TP2 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19 Reserved
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Field Function
—
18 Supervisor Protect
SP3 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17 Write Protect
WP3 Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16 Trusted Protect
TP3 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15 Reserved
—
14 Supervisor Protect
SP4 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13 Write Protect
WP4 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12 Trusted Protect
TP4 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11 Reserved
—
10 Supervisor Protect
SP5 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.

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Field Function
9 Write Protect
WP5 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8 Trusted Protect
TP5 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7-4 Reserved
—
3-0 Reserved
—

16.3.1.12 Off-Platform Peripheral Access Control Register (OPACRG)

16.3.1.12.1 Offset
Register Offset
OPACRG 58h

16.3.1.12.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

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16.3.1.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP2 WP2 TP2
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP4 WP4 TP4 SP5 WP5 TP5
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0

16.3.1.12.4 Fields
Field Function
31-28 Reserved
—
27-24 Reserved
—
23 Reserved
—
22 Supervisor Protect
SP2 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21 Write Protect
WP2 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20 Trusted Protect
TP2 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19-16 Reserved
—
15 Reserved
—
14 Supervisor Protect
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Field Function
SP4 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13 Write Protect
WP4 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12 Trusted Protect
TP4 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11 Reserved
—
10 Supervisor Protect
SP5 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9 Write Protect
WP5 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8 Trusted Protect
TP5 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7-4 Reserved
—
3-0 Reserved
—

16.3.1.13 Off-Platform Peripheral Access Control Register (OPACRH)

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16.3.1.13.1 Offset
Register Offset
OPACRH 5Ch

16.3.1.13.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP2 WP2 TP2
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

16.3.1.13.4 Fields
Field Function
31-28 Reserved
—
27-24 Reserved
—
23 Reserved
—
22 Supervisor Protect
SP2 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.

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Field Function
21 Write Protect
WP2 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20 Trusted Protect
TP2 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19-16 Reserved
—
15-12 Reserved
—
11-8 Reserved
—
7-4 Reserved
—
3-0 Reserved
—

16.3.1.14 Off-Platform Peripheral Access Control Register (OPACRI)

16.3.1.14.1 Offset
Register Offset
OPACRI 60h

16.3.1.14.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

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16.3.1.14.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP1 WP1 TP1 SP3 WP3 TP3
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP4 WP4 TP4 SP5 WP5 TP5 SP6 WP6 TP6 SP7 WP7 TP7
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

16.3.1.14.4 Fields
Field Function
31-28 Reserved
—
27 Reserved
—
26 Supervisor Protect
SP1 Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20 Reserved
—
19 Reserved
—
18 Supervisor Protect
SP3
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Field Function
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17 Write Protect
WP3 Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16 Trusted Protect
TP3 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15 Reserved
—
14 Supervisor Protect
SP4 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13 Write Protect
WP4 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12 Trusted Protect
TP4 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11 Reserved
—
10 Supervisor Protect
SP5 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9 Write Protect
WP5
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Field Function
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8 Trusted Protect
TP5 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7 Reserved
—
6 Supervisor Protect
SP6 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5 Write Protect
WP6 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4 Trusted Protect
TP6 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3 Reserved
—
2 Supervisor Protect
SP7 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
1 Write Protect
WP7 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0 Trusted Protect
TP7

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Field Function
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.

16.3.1.15 Off-Platform Peripheral Access Control Register (OPACRJ)

16.3.1.15.1 Offset
Register Offset
OPACRJ 64h

16.3.1.15.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP2 WP2 TP2 SP3 WP3 TP3
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP4 WP4 TP4 SP6 WP6 TP6 SP7 WP7 TP7
W
Reset 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0

16.3.1.15.4 Fields
Field Function
31-28 Reserved
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Field Function
—
27-24 Reserved
—
23 Reserved
—
22 Supervisor Protect
SP2 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21 Write Protect
WP2 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20 Trusted Protect
TP2 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
19 Reserved
—
18 Supervisor Protect
SP3 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17 Write Protect
WP3 Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16 Trusted Protect
TP3 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15 Reserved
—
14 Supervisor Protect
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Field Function
SP4 Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
13 Write Protect
WP4 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
12 Trusted Protect
TP4 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
11-8 Reserved
—
7 Reserved
—
6 Supervisor Protect
SP6 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5 Write Protect
WP6 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4 Trusted Protect
TP6 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3 Reserved
—
2 Supervisor Protect
SP7 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.

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Field Function
1 Write Protect
WP7 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0 Trusted Protect
TP7 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.

16.3.1.16 Off-Platform Peripheral Access Control Register (OPACRK)

16.3.1.16.1 Offset
Register Offset
OPACRK 68h

16.3.1.16.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.16.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP0 WP0 TP0 SP1 WP1 TP1 SP3 WP3 TP3
W
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP6 WP6 TP6
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

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16.3.1.16.4 Fields
Field Function
31 Reserved
—
30 Supervisor Protect
SP0 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
29 Write Protect
WP0 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
28 Trusted Protect
TP0 Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
27 Reserved
—
26 Supervisor Protect
SP1 Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20 Reserved
—
19 Reserved
—

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Memory map/register definition

Field Function
18 Supervisor Protect
SP3 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
17 Write Protect
WP3 Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
16 Trusted Protect
TP3 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
15-12 Reserved
—
11-8 Reserved
—
7 Reserved
—
6 Supervisor Protect
SP6 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
5 Write Protect
WP6 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4 Trusted Protect
TP6 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3-0 Reserved
—

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16.3.1.17 Off-Platform Peripheral Access Control Register (OPACRL)

16.3.1.17.1 Offset
Register Offset
OPACRL 6Ch

16.3.1.17.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.

16.3.1.17.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0 0 0
SP1 WP1 TP1
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0
SP5 WP5 TP5 SP6 WP6 TP6 SP7 WP7 TP7
W
Reset 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0

16.3.1.17.4 Fields
Field Function
31-28 Reserved
—
27 Reserved
—
26 Supervisor Protect
SP1 Determines whether the peripheral requires supervisor privilege level for access. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.

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Memory map/register definition

Field Function
25 Write Protect
WP1 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
24 Trusted Protect
TP1 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
23-20 Reserved
—
19-16 Reserved
—
15-12 Reserved
—
11 Reserved
—
10 Supervisor Protect
SP5 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
9 Write Protect
WP5 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
8 Trusted Protect
TP5 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
7 Reserved
—
6 Supervisor Protect
SP6 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.

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Field Function
5 Write Protect
WP6 Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
4 Trusted Protect
TP6 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.
3 Reserved
—
2 Supervisor Protect
SP7 Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPRx[MPLn] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
1 Write Protect
WP7 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
0 Trusted Protect
TP7 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0b - Accesses from an untrusted master are allowed.
1b - Accesses from an untrusted master are not allowed.

16.4 Functional description

The peripheral bridge functions as a bus protocol translator between the crossbar switch
and the slave peripheral bus.
The peripheral bridge manages all transactions destined for the attached slave devices and
generates select signals for modules on the peripheral bus by decoding accesses within
the attached address space.

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Functional description

16.4.1 Access support

Aligned and misaligned 32-bit, 16-bit, and byte accesses are supported for 32-bit
peripherals. Misaligned accesses are supported to allow memory to be placed on the slave
peripheral bus. Peripheral registers must not be misaligned, although no explicit checking
is performed by the peripheral bridge. All accesses are performed with a single transfer.
All accesses to the peripheral slots must be sized less than or equal to the designated
peripheral slot size. If an access is attempted that is larger than the targeted port, an error
response is generated.

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Direct Memory Access Multiplexer (DMAMUX)

17.1 Chip-specific DMAMUX information

17.1.1 Number of channels

The number of channels across S32K1xx series varies across variants. See below table
for the same.
Table 17-1. Number of channles
Chips Number of channels
S32K116 4
S32K118 4
S32K142 16
S32K144 16
S32K146 16
S32K148 16

17.1.2 DMA transfers via TRGMUX trigger

The triggers from TRGMUX module can trigger a DMA transfer on the first four DMA
channels, for example, the LPIT can trigger DMA via TRGMUX. See Figure 19-2 for
module interconnectivity details. The LPIT/DMA periodic trigger assignments are
detailed at LPIT/DMA Periodic Trigger Assignments.
Asynchronous DMA operation does not support trigger options.
In cases where multiple DMA request are routed to DMAMUX source, software needs to
make sure that only one DMA request is enabled at a time. For example DMA request of
one Ethernet timer can be enabled at a particular time, while others can enable interrupt
during that time.

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Introduction

17.2 Introduction

17.2.1 Overview
The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots,
to any of the 16 DMA channels. See the chip-specific information to know the detailed
source numbers. This process is illustrated in the following figure.

DMA channel #0
Source #1 DMAMUX
DMA channel #1
Source #2

Source #3

Source #x

Always #1

Always #y

Trigger #1

DMA channel #n

Trigger #z

Figure 17-1. DMAMUX block diagram

17.2.2 Features
The DMAMUX module provides these features:
• Up to 61 peripheral slots and up to 2 always-on slots can be routed to 16 channels.
• 16 independently selectable DMA channel routers.

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• The first 4 channels additionally provide a trigger functionality.

• Each channel router can be assigned to one of the possible peripheral DMA slots or
to one of the always-on slots.

17.2.3 Modes of operation

The following operating modes are available:
• Disabled mode
In this mode, the DMA channel is disabled. Because disabling and enabling of DMA
channels is done primarily via the DMA configuration registers, this mode is used
mainly as the reset state for a DMA channel in the DMA channel MUX. It may also
be used to temporarily suspend a DMA channel while reconfiguration of the system
takes place, for example, changing the period of a DMA trigger.
• Normal mode
In this mode, a DMA source is routed directly to the specified DMA channel. The
operation of the DMAMUX in this mode is completely transparent to the system.
• Periodic Trigger mode
In this mode, a DMA source may only request a DMA transfer, such as when a
transmit buffer becomes empty or a receive buffer becomes full, periodically.
Configuration of the period is done by an external periodic interrupt timer (for
example, PIT). This mode is available only for channels 0–3.

17.3 Memory map/register definition

This section provides a detailed description of all memory-mapped registers in the
DMAMUX.

17.3.1 DMAMUX register descriptions

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Memory map/register definition

17.3.1.1 DMAMUX Memory map

DMAMUX base address: 4002_1000h
Offset Register Width Access Reset value
(In bits)
0h - Fh Channel Configuration register (CHCFG0 - CHCFG15) 8 RW 00h

17.3.1.2 Channel Configuration register (CHCFG0 - CHCFG15)

17.3.1.2.1 Offset
For a = 0 to 15:
Register Offset
CHCFGa 0h + (a × 1h)

17.3.1.2.2 Function
Each of the DMA channels can be independently enabled/disabled and associated with
one of the DMA slots (peripheral slots or always-on slots) in the system.
NOTE
Setting multiple CHCFG registers with the same source value
will result in unpredictable behavior. This is true, even if a
channel is disabled (ENBL==0).
Before changing the trigger or source settings, a DMA channel
must be disabled via CHCFGn[ENBL].

17.3.1.2.3 Diagram
Bits 7 6 5 4 3 2 1 0

R
SOURC
TRIG
ENB

W
L

Reset 0 0 0 0 0 0 0 0

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17.3.1.2.4 Fields
Field Function
7 DMA Channel Enable
ENBL Enables the DMA channel.
0b - DMA channel is disabled. This mode is primarily used during configuration of the DMAMux.
The DMA has separate channel enables/disables, which should be used to disable or reconfigure a
DMA channel.
1b - DMA channel is enabled
6 DMA Channel Trigger Enable
TRIG Enables the periodic trigger capability for the triggered DMA channel.
0b - Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply
route the specified source to the DMA channel. (Normal mode)
1b - Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic
Trigger mode.
5-0 DMA Channel Source (Slot)
SOURCE Specifies which DMA source, if any, is routed to a particular DMA channel. See the chip-specific
DMAMUX information for details about the peripherals and their slot numbers.

17.4 Functional description

The primary purpose of the DMAMUX is to provide flexibility in the system's use of the
available DMA channels.
As such, configuration of the DMAMUX is intended to be a static procedure done during
execution of the system boot code. However, if the procedure outlined in Enabling and
configuring sources is followed, the configuration of the DMAMUX may be changed
during the normal operation of the system.
Functionally, the DMAMUX channels may be divided into two classes:
• Channels that implement the normal routing functionality plus periodic triggering
capability
• Channels that implement only the normal routing functionality

17.4.1 DMA channels with periodic triggering capability

Besides the normal routing functionality, the first 4 channels of the DMAMUX provide a
special periodic triggering capability that can be used to provide an automatic mechanism
to transmit bytes, frames, or packets at fixed intervals without the need for processor
intervention.

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Functional description

The trigger is generated by an external periodic interrupt timer (for example, PIT); as
such, the configuration of the periodic triggering interval is done via configuring the
external periodic timer.
Note
Because of the dynamic nature of the system (due to DMA
channel priorities, bus arbitration, interrupt service routine
lengths, etc.), the number of clock cycles between a trigger and
the actual DMA transfer cannot be guaranteed.

Source #1

Source #2

Source #3
DMA channel #0
Trigger #1

Source #x
DMA channel #m-1
Trigger #m
Always #1

Always #y

Figure 17-2. DMAMUX triggered channels

The DMA channel triggering capability allows the system to schedule regular DMA
transfers, usually on the transmit side of certain peripherals, without the intervention of
the processor. This trigger works by gating the request from the peripheral to the DMA
until a trigger event has been seen. This is illustrated in the following figure.

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Peripheral request

Trigger

DMA request

Figure 17-3. DMAMUX channel triggering: normal operation

After the DMA request has been serviced, the peripheral will negate its request,
effectively resetting the gating mechanism until the peripheral reasserts its request and
the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not
requesting a transfer, then that trigger will be ignored. This situation is illustrated in the
following figure.

Peripheral request

Trigger

DMA request

Figure 17-4. DMAMUX channel triggering: ignored trigger

This triggering capability may be used with any peripheral that supports DMA transfers,
and is most useful for two types of situations:
• Periodically polling external devices on a particular bus
As an example, the transmit side of an SPI is assigned to a DMA channel with a
trigger, as described above. After it has been set up, the SPI will request DMA
transfers, presumably from memory, as long as its transmit buffer is empty. By using
a trigger on this channel, the SPI transfers can be automatically performed every 5 μs
(as an example). On the receive side of the SPI, the SPI and DMA can be configured
to transfer receive data into memory, effectively implementing a method to
periodically read data from external devices and transfer the results into memory
without processor intervention.
• Using the GPIO ports to drive or sample waveforms
By configuring the DMA to transfer data to one or more GPIO ports, it is possible to
create complex waveforms using tabular data stored in on-chip memory. Conversely,
using the DMA to periodically transfer data from one or more GPIO ports, it is
possible to sample complex waveforms and store the results in tabular form in on-
chip memory.

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Functional description

17.4.2 DMA channels with no triggering capability

The other channels of the DMAMUX provide the normal routing functionality as
described in Modes of operation.

17.4.3 Always-enabled DMA sources

In addition to the peripherals that can be used as DMA sources, there are 2 additional
DMA sources that are always enabled. Unlike the peripheral DMA sources, where the
peripheral controls the flow of data during DMA transfers, the sources that are always
enabled provide no such "throttling" of the data transfers. These sources are most useful
in the following cases:
• Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO
pins, either unthrottled (that is, as fast as possible), or periodically (using the DMA
triggering capability).
• Performing DMA transfers from memory to memory—Moving data from memory to
memory, typically as fast as possible, sometimes with software activation.
• Performing DMA transfers from memory to the external bus, or vice-versa—Similar
to memory to memory transfers, this is typically done as quickly as possible.
• Any DMA transfer that requires software activation—Any DMA transfer that should
be explicitly started by software.

In cases where software should initiate the start of a DMA transfer, an always-enabled
DMA source can be used to provide maximum flexibility. When activating a DMA
channel via software, subsequent executions of the minor loop require that a new start
event be sent. This can either be a new software activation, or a transfer request from the
DMA channel MUX. The options for doing this are:
• Transfer all data in a single minor loop.
By configuring the DMA to transfer all of the data in a single minor loop (that is,
major loop counter = 1), no reactivation of the channel is necessary. The
disadvantage to this option is the reduced granularity in determining the load that the
DMA transfer will impose on the system. For this option, the DMA channel must be
disabled in the DMA channel MUX.
• Use explicit software reactivation.

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In this option, the DMA is configured to transfer the data using both minor and major
loops, but the processor is required to reactivate the channel by writing to the DMA
registers after every minor loop. For this option, the DMA channel must be disabled
in the DMA channel MUX.
• Use an always-enabled DMA source.
In this option, the DMA is configured to transfer the data using both minor and major
loops, and the DMA channel MUX does the channel reactivation. For this option, the
DMA channel should be enabled and pointing to an "always enabled" source. Note
that the reactivation of the channel can be continuous (DMA triggering is disabled)
or can use the DMA triggering capability. In this manner, it is possible to execute
periodic transfers of packets of data from one source to another, without processor
intervention.

17.5 Initialization/application information

This section provides instructions for initializing the DMA channel MUX.

17.5.1 Reset
The reset state of each individual bit is shown in Memory map/register definition. In
summary, after reset, all channels are disabled and must be explicitly enabled before use.

17.5.2 Enabling and configuring sources

To enable a source with periodic triggering:
1. Determine with which DMA channel the source will be associated. Note that only the
first 4 DMA channels have periodic triggering capability.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel
may be enabled at this point.
4. Configure the corresponding timer.
5. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are
set.

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Initialization/application information

NOTE
The following is an example. See the chip-specific information
for the number of this device's DMA channels that have
triggering capability.
To configure source #5 transmit for use with DMA channel 1, with periodic triggering
capability:
1. Write 0x00 to CHCFG1.
2. Configure channel 1 in the DMA, including enabling the channel.
3. Configure a timer for the desired trigger interval.
4. Write 0xC5 to CHCFG1.
The following code example illustrates steps 1 and 4 above:
void DMAMUX_Init(uint8_t DMA_CH, uint8_t DMAMUX_SOURCE)
{
DMAMUX_0.CHCFG[DMA_CH].B.SOURCE = DMAMUX_SOURCE;
DMAMUX_0.CHCFG[DMA_CH].B.ENBL = 1;
DMAMUX_0.CHCFG[DMA_CH].B.TRIG = 1;
}

To enable a source, without periodic triggering:

1. Determine with which DMA channel the source will be associated. Note that only the
first 4 DMA channels have periodic triggering capability.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel
may be enabled at this point.
4. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that CHCFG[ENBL] is setwhile CHCFG[TRIG] is
cleared.
NOTE
The following is an example. See the chip configuration details
for the number of this device's DMA channels that have
triggering capability.
To configure source #5 transmit for use with DMA channel 1, with no periodic triggering
capability:
1. Write 0x00 to CHCFG1.
2. Configure channel 1 in the DMA, including enabling the channel.
3. Write 0x85 to CHCFG1.
The following code example illustrates steps 1 and 3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */
/* Following example assumes char is 8-bits */
volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000);

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volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001);
volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);
volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003);
volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004);
volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005);
volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006);
volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007);
volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008);
volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009);
volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A);
volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B);
volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C);
volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D);
volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E);
volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);

In File main.c:
#include "registers.h"
:
:
*CHCFG1 = 0x00;
*CHCFG1 = 0x85;

To disable a source:
A particular DMA source may be disabled by not writing the corresponding source value
into any of the CHCFG registers. Additionally, some module-specific configuration may
be necessary. See the appropriate section for more details.
To switch the source of a DMA channel:
1. Disable the DMA channel in the DMA and reconfigure the channel for the new
source.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel.
3. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are
set.
To switch DMA channel 8 from source #5 transmit to source #7 transmit:
1. In the DMA configuration registers, disable DMA channel 8 and reconfigure it to
handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't
have triggering capability.
2. Write 0x00 to CHCFG8.
3. Write 0x87 to CHCFG8. (In this example, setting CHCFG[TRIG] would have no
effect due to the assumption that channel 8 does not support the periodic triggering
functionality.)
The following code example illustrates steps 2 and 3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */
/* Following example assumes char is 8-bits */
volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000);
volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001);
volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);
volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003);

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Initialization/application information
volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004);
volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005);
volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006);
volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007);
volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008);
volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009);
volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A);
volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B);
volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C);
volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D);
volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E);
volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);

In File main.c:
#include "registers.h"
:
:
*CHCFG8 = 0x00;
*CHCFG8 = 0x87;

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Chapter 18
Enhanced Direct Memory Access (eDMA)

18.1 Chip-specific eDMA information

Wait mode is not supported. See Module operation in available low power modes for
details on available power modes.
16-byte burst and 32-byte burst is not supported on S32K11x variants.

18.1.1 Seamless eDMA transfer

For S32K11x variants, there are two options to make DMA transfers seamless:
Option 1: When executing a large, zero wait-stated memory-to-memory transfer (as an
example transfers greater than 16 MB of transfer size), insert bandwidth control using the
TCD_CSR[BWC] bits to avoid:
• Starvation of another master accessing the memory
• Any delay in writing a TCD during the transfer
NOTE
• This option always adds wait states for every DMA
transfer.
• Without following this option, the software code working
properly on S32K14x devices might fail on S32K11x
devices.
Option 2: For S32K11x devices, crossbar must be programmed to round-robin
arbitration (configuring MCM_CPCR[CBRR] as '1' ) for seamless DMA transfers. This
option affects all master configurations on the crossbar.
NOTE
• No bandwidth control insertion is needed in this option.
• This option works seamlessly for S32K14x devices also.

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Introduction

18.1.2 Number of channels

The number of channels across S32K1xx series varies across variants. See below table
for the same.
Table 18-1. Number of channles
Chips Number of channels
S32K116 4
S32K118 4
S32K142 16
S32K144 16
S32K146 16
S32K148 16

18.2 Introduction
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data transfers with minimal intervention from a host
processor. The hardware microarchitecture includes:
• A DMA engine that performs:
• Source address and destination address calculations
• Data-movement operations
• Local memory containing transfer control descriptors for each of the 16 channels

18.2.1 eDMA system block diagram

Figure 18-1 illustrates the components of the eDMA system, including the eDMA
module ("engine").

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eDMA system Write Address

Write Data

0
1
2

Internal Peripheral Bus

To/From Crossbar Switch

Transfer Control
Descriptor (TCD) n-1
64

eDMA e ngine
Program Model/
Read Data
Channel Arbitration
Read Data

Address Path
Control
Data Path

Write Data
Address

eDMA Peripheral
eDMA Done
Request

Figure 18-1. eDMA system block diagram

18.2.2 Block parts

The eDMA module is partitioned into two major modules: the eDMA engine and the
transfer-control descriptor local memory.
The eDMA engine is further partitioned into four submodules:
Table 18-2. eDMA engine submodules
Submodule Function
Address path This block implements registered versions of two channel transfer control descriptors, channel x
and channel y, and manages all master bus-address calculations. All the channels provide the
same functionality. This structure allows data transfers associated with one channel to be
preempted after the completion of a read/write sequence if a higher priority channel activation is
asserted while the first channel is active. After a channel is activated, it runs until the minor loop is
completed, unless preempted by a higher priority channel. This provides a mechanism (enabled
by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time
another channel is blocked from execution.
When any channel is selected to execute, the contents of its TCD are read from local memory and
loaded into the address path channel x registers for a normal start and into channel y registers for
a preemption start. After the minor loop completes execution, the address path hardware writes
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Introduction

Table 18-2. eDMA engine submodules (continued)

Submodule Function
the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major
iteration count is exhausted, additional processing is performed, including the final address pointer
updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as
part of a scatter/gather operation.
Data path This block implements the bus master read/write datapath. It includes a data buffer and the
necessary multiplex logic to support any required data alignment. The internal read data bus is the
primary input, and the internal write data bus is the primary output.
The address and data path modules directly support the 2-stage pipelined internal bus. The
address path module represents the 1st stage of the bus pipeline (address phase), while the data
path module implements the 2nd stage of the pipeline (data phase).
Program model/channel This block implements the first section of the eDMA programming model as well as the channel
arbitration arbitration logic. The programming model registers are connected to the internal peripheral bus.
The eDMA peripheral request inputs and interrupt request outputs are also connected to this block
(via control logic).
Control This block provides all the control functions for the eDMA engine. For data transfers where the
source and destination sizes are equal, the eDMA engine performs a series of source read/
destination write operations until the number of bytes specified in the minor loop byte count has
moved. For descriptors where the sizes are not equal, multiple accesses of the smaller size data
are required for each reference of the larger size. As an example, if the source size references 16-
bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write.

The transfer-control descriptor local memory is further partitioned into:

Table 18-3. Transfer control descriptor memory
Submodule Description
Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA
engine as well as references from the internal peripheral bus. As noted earlier, in the event of
simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is
stalled.
Memory array TCD storage for each channel's transfer profile.

18.2.3 Features
The eDMA is a highly programmable data-transfer engine optimized to minimize any
required intervention from the host processor. It is intended for use in applications where
the data size to be transferred is statically known and not defined within the transferred
data itself. The eDMA module features:
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes

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• 16-channel implementation that performs complex data transfers with minimal

intervention from a host processor
• Internal data buffer, used as temporary storage to support 16- and 32-byte
transfers
• Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
• One interrupt per channel, which can be asserted at completion of major iteration
count
• Programmable error terminations per channel and logically summed together to
form one error interrupt to the interrupt controller
• Programmable support for scatter/gather DMA processing
• Support for complex data structures

In the discussion of this module, n is used to reference the channel number.

18.3 Modes of operation

The eDMA operates in the following modes:

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Memory map/register definition

Table 18-4. Modes of operation

Mode Description
Normal In Normal mode, the eDMA transfers data between a source and a destination. The source and
destination can be a memory block or an I/O block capable of operation with the eDMA.
A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the
transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that
transfers these NBYTES per service request. Each service request executes one iteration of the
major loop, which transfers NBYTES of data.
Debug DMA operation is configurable in Debug mode via the control register:
• If CR[EDBG] is cleared, the DMA continues to operate.
• If CR[EDBG] is set, the eDMA stops transferring data. If Debug mode is entered while a
channel is active, the eDMA continues operation until the channel retires.
Wait Before entering Wait mode, the DMA attempts to complete its current transfer. After the transfer
completes, the device enters Wait mode.

18.4 Memory map/register definition

The eDMA's programming model is partitioned into two regions:
• The first region defines a number of registers providing control functions
• The second region corresponds to the local transfer control descriptor (TCD)
memory

18.4.1 TCD memory

Each channel requires a 32-byte transfer control descriptor for defining the desired data
movement operation. The channel descriptors are stored in the local memory in
sequential order: channel 0, channel 1, ... channel 15. Each TCDn definition is presented
as 11 registers of 16 or 32 bits.

18.4.2 TCD initialization

Prior to activating a channel, you must initialize its TCD with the appropriate transfer
profile.

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18.4.3 TCD structure

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000h SADDR

0004h SMOD SSIZE DMOD DSIZE SOFF

0008h
{ NBYTES {
{
DMA_CR[EMLM] disabled
DMLOE
SMLOE

MLOFF or NBYTES NBYTES DMA_CR[EMLM] enabled

000Ch SLAST

0010h DADDR
CITER.E_LINK

CITER or
0014h CITER DOFF
CITER.LINKCH

0018h DLAST_SGA

MAJOR.E_LINK
BITER.E_LINK

MAJOR.LINKCH

INT_HALF
Reserved

INT_MAJ
ACTIVE

D_REQ

START
DONE

E_SG
BITER or
001Ch BITER BWC
BITER.LINKCH

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

18.4.4 Reserved memory and bit fields

• Reading reserved bits in a register returns the value of zero.
• Writes to reserved bits in a register are ignored.
• Reading or writing a reserved memory location generates a bus error.

18.4.5 DMA register descriptions

18.4.5.1 DMA Memory map

DMA base address: 4000_8000h
Offset Register Width Access Reset value
(In bits)
0h Control Register (CR) 32 RW Table 18-4
4h Error Status Register (ES) 32 RO 0000_0000h

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Memory map/register definition

Offset Register Width Access Reset value

(In bits)
Ch Enable Request Register (ERQ) 32 RW 0000_0000h
14h Enable Error Interrupt Register (EEI) 32 RW 0000_0000h
18h Clear Enable Error Interrupt Register (CEEI) 8 WORZ 00h
19h Set Enable Error Interrupt Register (SEEI) 8 WORZ 00h
1Ah Clear Enable Request Register (CERQ) 8 WORZ 00h
1Bh Set Enable Request Register (SERQ) 8 WORZ 00h
1Ch Clear DONE Status Bit Register (CDNE) 8 WORZ 00h
1Dh Set START Bit Register (SSRT) 8 WORZ 00h
1Eh Clear Error Register (CERR) 8 WORZ 00h
1Fh Clear Interrupt Request Register (CINT) 8 WORZ 00h
24h Interrupt Request Register (INT) 32 W1C 0000_0000h
2Ch Error Register (ERR) 32 W1C 0000_0000h
34h Hardware Request Status Register (HRS) 32 RO 0000_0000h
44h Enable Asynchronous Request in Stop Register (EARS) 32 RW 0000_0000h
100h Channel Priority Register (DCHPRI3) 8 RW 03h
101h Channel Priority Register (DCHPRI2) 8 RW 02h
102h Channel Priority Register (DCHPRI1) 8 RW 01h
103h Channel Priority Register (DCHPRI0) 8 RW 00h
104h Channel Priority Register (DCHPRI7) 8 RW 07h
105h Channel Priority Register (DCHPRI6) 8 RW 06h
106h Channel Priority Register (DCHPRI5) 8 RW 05h
107h Channel Priority Register (DCHPRI4) 8 RW 04h
108h Channel Priority Register (DCHPRI11) 8 RW 0Bh
109h Channel Priority Register (DCHPRI10) 8 RW 0Ah
10Ah Channel Priority Register (DCHPRI9) 8 RW 09h
10Bh Channel Priority Register (DCHPRI8) 8 RW 08h
10Ch Channel Priority Register (DCHPRI15) 8 RW 0Fh
10Dh Channel Priority Register (DCHPRI14) 8 RW 0Eh
10Eh Channel Priority Register (DCHPRI13) 8 RW 0Dh
10Fh Channel Priority Register (DCHPRI12) 8 RW 0Ch
1000h - TCD Source Address (TCD0_SADDR - TCD15_SADDR) 32 RW Table 18-4
11E0h
1004h - TCD Signed Source Address Offset (TCD0_SOFF - TCD15_SOFF) 16 RW Table 18-4
11E4h
1006h - TCD Transfer Attributes (TCD0_ATTR - TCD15_ATTR) 16 RW Table 18-4
11E6h
1008h - TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBY 32 RW Table 18-4
11E8h TES_MLNO - TCD15_NBYTES_MLNO)
1008h - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and 32 RW Table 18-4
11E8h Offset Disabled) (TCD0_NBYTES_MLOFFNO - TCD15_NBYTES_
MLOFFNO)

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Offset Register Width Access Reset value

(In bits)
1008h - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset 32 RW Table 18-4
11E8h Enabled) (TCD0_NBYTES_MLOFFYES - TCD15_NBYTES_MLO
FFYES)
100Ch - TCD Last Source Address Adjustment (TCD0_SLAST - TCD15_SL 32 RW Table 18-4
11ECh AST)
1010h - 11F0h TCD Destination Address (TCD0_DADDR - TCD15_DADDR) 32 RW Table 18-4
1014h - 11F4h TCD Signed Destination Address Offset (TCD0_DOFF - TCD15_DO 16 RW Table 18-4
FF)
1016h - 11F6h TCD Current Minor Loop Link, Major Loop Count (Channel Linking 16 RW Table 18-4
Disabled) (TCD0_CITER_ELINKNO - TCD15_CITER_ELINKNO)
1016h - 11F6h TCD Current Minor Loop Link, Major Loop Count (Channel Linking 16 RW Table 18-4
Enabled) (TCD0_CITER_ELINKYES - TCD15_CITER_ELINKYES)
1018h - 11F8h TCD Last Destination Address Adjustment/Scatter Gather Address 32 RW Table 18-4
(TCD0_DLASTSGA - TCD15_DLASTSGA)
101Ch - TCD Control and Status (TCD0_CSR - TCD15_CSR) 16 RW Table 18-4
11FCh
101Eh - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking 16 RW Table 18-4
11FEh Disabled) (TCD0_BITER_ELINKNO - TCD15_BITER_ELINKNO)
101Eh - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking 16 RW Table 18-4
11FEh Enabled) (TCD0_BITER_ELINKYES - TCD15_BITER_ELINKYES)

18.4.5.2 Control Register (CR)

18.4.5.2.1 Offset
Register Offset
CR 0h

18.4.5.2.2 Function
The CR defines the basic operating configuration of the DMA.
Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For
fixed-priority arbitration, the highest priority channel requesting service is selected to
execute. The channel priority registers assign the priorities; see the DCHPRIn registers.
For round-robin arbitration, the channel priorities are ignored and channels are cycled
through (from high to low channel number) without regard to priority.

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NOTE
For correct operation, writes to the CR register must be
performed only when the DMA channels are inactive; that is,
when TCDn_CSR[ACTIVE] bits are cleared.
Minor loop offsets are address offset values added to the final source address
(TCDn_SADDR) or destination address (TCDn_DADDR) upon minor loop completion.
When minor loop offsets are enabled, the minor loop offset (MLOFF) is added to the
final source address (TCDn_SADDR), to the final destination address (TCDn_DADDR),
or to both prior to the addresses being written back into the TCD. If the major loop is
complete, the minor loop offset is ignored and the major loop address offsets
(TCDn_SLAST and TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR
and TCDn_DADDR values.
When minor loop mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion
of TCDn word2 is used to specify multiple fields: a source enable bit (SMLOE) to
specify the minor loop offset should be applied to the source address (TCDn_SADDR)
upon minor loop completion, a destination enable bit (DMLOE) to specify the minor loop
offset should be applied to the destination address (TCDn_DADDR) upon minor loop
completion, and the sign extended minor loop offset value (MLOFF). The same offset
value (MLOFF) is used for both source and destination minor loop offsets. When either
minor loop offset is enabled (SMLOE set or DMLOE set), the NBYTES field is reduced
to 10 bits. When both minor loop offsets are disabled (SMLOE cleared and DMLOE
cleared), the NBYTES field is a 30-bit vector.
When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
assigned to the NBYTES field.

18.4.5.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
ACTIVE

R
0

CX

EC
X

W
Reset 0 u u u u u u u 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
0

Reserved

Reserved
ERCA
EMLM

HALT

HOE
CLM

EDB

W
G

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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18.4.5.2.4 Fields
Field Function
31 DMA Active Status
0b - eDMA is idle.
ACTIVE
1b - eDMA is executing a channel.
30-24 eDMA version number
— Reserved
23-18 Reserved
—
17 Cancel Transfer
0b - Normal operation
CX
1b - Cancel the remaining data transfer. Stop the executing channel and force the minor loop to
finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit
clears itself after the cancel has been honored. This cancel retires the channel normally as if the
minor loop was completed.
16 Error Cancel Transfer
0b - Normal operation
ECX
1b - Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing
channel and force the minor loop to finish. The cancel takes effect after the last write of the current
read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling
the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register
(DMAx_ES) and generating an optional error interrupt.
15-8 Reserved
—
7 Enable Minor Loop Mapping
0b - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
EMLM
1b - Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the
NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source
address, the destination address, or both. The NBYTES field is reduced when either offset is
enabled.
6 Continuous Link Mode
CLM NOTE: Do not use continuous link mode with a channel linking to itself if there is only one minor loop
iteration per service request, for example, if the channel's NBYTES value is the same as either
the source or destination size. The same data transfer profile can be achieved by simply
increasing the NBYTES value, which provides more efficient, faster processing.
0b - A minor loop channel link made to itself goes through channel arbitration before being
activated again.
1b - A minor loop channel link made to itself does not go through channel arbitration before being
activated again. Upon minor loop completion, the channel activates again if that channel has a
minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop
offsets and restarts the next minor loop.
5 Halt DMA Operations
0b - Normal operation
HALT
1b - Stall the start of any new channels. Executing channels are allowed to complete. Channel
execution resumes when this bit is cleared.
4 Halt On Error
0b - Normal operation
HOE
1b - Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the
HALT bit is cleared.

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Field Function
3 Reserved
— Reserved
2 Enable Round Robin Channel Arbitration
0b - Fixed priority arbitration is used for channel selection .
ERCA
1b - Round robin arbitration is used for channel selection .
1 Enable Debug
0b - When in debug mode, the DMA continues to operate.
EDBG
1b - When in debug mode, the DMA stalls the start of a new channel. Executing channels are
allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG
bit is cleared.
0 Reserved
— Reserved

18.4.5.3 Error Status Register (ES)

18.4.5.3.1 Offset
Register Offset
ES 4h

18.4.5.3.2 Function
The ES provides information concerning the last recorded channel error. Channel errors
can be caused by:
• A configuration error, that is:
• An illegal setting in the transfer-control descriptor, or
• An illegal priority register setting in fixed-arbitration
• An error termination to a bus master read or write cycle
• A cancel transfer with error bit that will be set when a transfer is canceled via the
corresponding cancel transfer control bit
See Fault reporting and handling for more details.

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18.4.5.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R VLD 0 ECX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 CPE 0 ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

18.4.5.3.4 Fields
Field Function
31 VLD
VLD Logical OR of all ERR status bits
0b - No ERR bits are set.
1b - At least one ERR bit is set indicating a valid error exists that has not been cleared.
30-17 Reserved
—
16 Transfer Canceled
0b - No canceled transfers
ECX
1b - The last recorded entry was a canceled transfer by the error cancel transfer input
15 Reserved
—
14 Channel Priority Error
0b - No channel priority error
CPE
1b - The last recorded error was a configuration error in the channel priorities . Channel priorities
are not unique.
13-12 Reserved
—
11-8 Error Channel Number or Canceled Channel Number
ERRCHN The channel number of the last recorded error, excluding CPE errors, or last recorded error canceled
transfer.
7 Source Address Error
0b - No source address configuration error.
SAE
1b - The last recorded error was a configuration error detected in the TCDn_SADDR field.
TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
6 Source Offset Error
0b - No source offset configuration error
SOE
1b - The last recorded error was a configuration error detected in the TCDn_SOFF field.
TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
5 Destination Address Error
0b - No destination address configuration error
DAE
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Field Function
1b - The last recorded error was a configuration error detected in the TCDn_DADDR field.
TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
4 Destination Offset Error
0b - No destination offset configuration error
DOE
1b - The last recorded error was a configuration error detected in the TCDn_DOFF field.
TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
3 NBYTES/CITER Configuration Error
0b - No NBYTES/CITER configuration error
NCE
1b - The last recorded error was a configuration error detected in the TCDn_NBYTES or
TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and
TCDn_ATTR[DSIZE], orTCDn_CITER[CITER] is equal to zero, orTCDn_CITER[ELINK] is not equal
to TCDn_BITER[ELINK]
2 Scatter/Gather Configuration Error
0b - No scatter/gather configuration error
SGE
1b - The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This
field is checked at the beginning of a scatter/gather operation after major loop completion if
TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
1 Source Bus Error
0b - No source bus error
SBE
1b - The last recorded error was a bus error on a source read
0 Destination Bus Error
0b - No destination bus error
DBE
1b - The last recorded error was a bus error on a destination write

18.4.5.4 Enable Request Register (ERQ)

18.4.5.4.1 Offset
Register Offset
ERQ Ch

18.4.5.4.2 Function
The ERQ register provides a bit map for the 16 channels to enable the request signal for
each channel. The state of any given channel enable is directly affected by writes to this
register; it is also affected by writes to the SERQ and CERQ registers. These registers are
provided so the request enable for a single channel can easily be modified without
needing to perform a read-modify-write sequence to this register.
DMA request input signals and this enable request flag must be asserted before a
channel's hardware service request is accepted. The state of the DMA enable request flag
does not affect a channel service request made explicitly through software or a linked
channel request.
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NOTE
Disable a channel's hardware service request at the source
before clearing the channel's ERQ bit.

18.4.5.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
ERQ15

ERQ14

ERQ13

ERQ12

ERQ11

ERQ10

ERQ9

ERQ8

ERQ7

ERQ6

ERQ5

ERQ4

ERQ3

ERQ2

ERQ1

ERQ0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

18.4.5.4.4 Fields
Field Function
31-16 Reserved
—
15 Enable DMA Request 15
0b - The DMA request signal for the corresponding channel is disabled
ERQ15
1b - The DMA request signal for the corresponding channel is enabled
14 Enable DMA Request 14
0b - The DMA request signal for the corresponding channel is disabled
ERQ14
1b - The DMA request signal for the corresponding channel is enabled
13 Enable DMA Request 13
0b - The DMA request signal for the corresponding channel is disabled
ERQ13
1b - The DMA request signal for the corresponding channel is enabled
12 Enable DMA Request 12
0b - The DMA request signal for the corresponding channel is disabled
ERQ12
1b - The DMA request signal for the corresponding channel is enabled
11 Enable DMA Request 11
0b - The DMA request signal for the corresponding channel is disabled
ERQ11
1b - The DMA request signal for the corresponding channel is enabled
10 Enable DMA Request 10
0b - The DMA request signal for the corresponding channel is disabled
ERQ10
1b - The DMA request signal for the corresponding channel is enabled
9 Enable DMA Request 9
0b - The DMA request signal for the corresponding channel is disabled
ERQ9
1b - The DMA request signal for the corresponding channel is enabled
8 Enable DMA Request 8
0b - The DMA request signal for the corresponding channel is disabled
ERQ8
1b - The DMA request signal for the corresponding channel is enabled

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Field Function
7 Enable DMA Request 7
0b - The DMA request signal for the corresponding channel is disabled
ERQ7
1b - The DMA request signal for the corresponding channel is enabled
6 Enable DMA Request 6
0b - The DMA request signal for the corresponding channel is disabled
ERQ6
1b - The DMA request signal for the corresponding channel is enabled
5 Enable DMA Request 5
0b - The DMA request signal for the corresponding channel is disabled
ERQ5
1b - The DMA request signal for the corresponding channel is enabled
4 Enable DMA Request 4
0b - The DMA request signal for the corresponding channel is disabled
ERQ4
1b - The DMA request signal for the corresponding channel is enabled
3 Enable DMA Request 3
0b - The DMA request signal for the corresponding channel is disabled
ERQ3
1b - The DMA request signal for the corresponding channel is enabled
2 Enable DMA Request 2
0b - The DMA request signal for the corresponding channel is disabled
ERQ2
1b - The DMA request signal for the corresponding channel is enabled
1 Enable DMA Request 1
0b - The DMA request signal for the corresponding channel is disabled
ERQ1
1b - The DMA request signal for the corresponding channel is enabled
0 Enable DMA Request 0
0b - The DMA request signal for the corresponding channel is disabled
ERQ0
1b - The DMA request signal for the corresponding channel is enabled

18.4.5.5 Enable Error Interrupt Register (EEI)

18.4.5.5.1 Offset
Register Offset
EEI 14h

18.4.5.5.2 Function
The EEI register provides a bit map for the 16 channels to enable the error interrupt
signal for each channel. The state of any given channel's error interrupt enable is directly
affected by writes to this register; it is also affected by writes to the SEEI and CEEI.
These registers are provided so that the error interrupt enable for a single channel can
easily be modified without the need to perform a read-modify-write sequence to the EEI
register.

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The DMA error indicator and the error interrupt enable flag must be asserted before an
error interrupt request for a given channel is asserted to the interrupt controller.

18.4.5.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
EEI15

EEI14

EEI13

EEI12

EEI11

EEI10

EEI

EEI

EEI

EEI

EEI

EEI

EEI

EEI

EEI

EEI
W

0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

18.4.5.5.4 Fields
Field Function
31-16 Reserved
—
15 Enable Error Interrupt 15
0b - The error signal for corresponding channel does not generate an error interrupt
EEI15
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
14 Enable Error Interrupt 14
0b - The error signal for corresponding channel does not generate an error interrupt
EEI14
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
13 Enable Error Interrupt 13
0b - The error signal for corresponding channel does not generate an error interrupt
EEI13
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
12 Enable Error Interrupt 12
0b - The error signal for corresponding channel does not generate an error interrupt
EEI12
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
11 Enable Error Interrupt 11
0b - The error signal for corresponding channel does not generate an error interrupt
EEI11
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
10 Enable Error Interrupt 10
0b - The error signal for corresponding channel does not generate an error interrupt
EEI10
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
9 Enable Error Interrupt 9
0b - The error signal for corresponding channel does not generate an error interrupt
EEI9
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
8 Enable Error Interrupt 8
0b - The error signal for corresponding channel does not generate an error interrupt
EEI8
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
7 Enable Error Interrupt 7
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Field Function
EEI7 0b - The error signal for corresponding channel does not generate an error interrupt
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
6 Enable Error Interrupt 6
0b - The error signal for corresponding channel does not generate an error interrupt
EEI6
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
5 Enable Error Interrupt 5
0b - The error signal for corresponding channel does not generate an error interrupt
EEI5
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
4 Enable Error Interrupt 4
0b - The error signal for corresponding channel does not generate an error interrupt
EEI4
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
3 Enable Error Interrupt 3
0b - The error signal for corresponding channel does not generate an error interrupt
EEI3
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
2 Enable Error Interrupt 2
0b - The error signal for corresponding channel does not generate an error interrupt
EEI2
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
1 Enable Error Interrupt 1
0b - The error signal for corresponding channel does not generate an error interrupt
EEI1
1b - The assertion of the error signal for corresponding channel generates an error interrupt request
0 Enable Error Interrupt 0
0b - The error signal for corresponding channel does not generate an error interrupt
EEI0
1b - The assertion of the error signal for corresponding channel generates an error interrupt request

18.4.5.6 Clear Enable Error Interrupt Register (CEEI)

18.4.5.6.1 Offset
Register Offset
CEEI 18h

18.4.5.6.2 Function
The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI
to disable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global
clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.

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Reads of this register return all zeroes.

18.4.5.6.3 Diagram
Bits 7 6 5 4 3 2 1 0

R
0

0
NOP

CEE
CAE
W

0
E

I
Reset 0 0 0 0 0 0 0 0

18.4.5.6.4 Fields
Field Function
7 No Op enable
0b - Normal operation
NOP
1b - No operation, ignore the other bits in this register
6 Clear All Enable Error Interrupts
0b - Clear only the EEI bit specified in the CEEI field
CAEE
1b - Clear all bits in EEI
5-4 Reserved
—
3-0 Clear Enable Error Interrupt
CEEI Clears the corresponding bit in EEI

18.4.5.7 Set Enable Error Interrupt Register (SEEI)

18.4.5.7.1 Offset
Register Offset
SEEI 19h

18.4.5.7.2 Function
The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to
enable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set
function, forcing the entire EEI contents to be set.

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If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.

18.4.5.7.3 Diagram
Bits 7 6 5 4 3 2 1 0

R
NOP 0

0
SAE

SE
0

EI
E

Reset 0 0 0 0 0 0 0 0

18.4.5.7.4 Fields
Field Function
7 No Op enable
0b - Normal operation
NOP
1b - No operation, ignore the other bits in this register
6 Sets All Enable Error Interrupts
0b - Set only the EEI bit specified in the SEEI field.
SAEE
1b - Sets all bits in EEI
5-4 Reserved
—
3-0 Set Enable Error Interrupt
SEEI Sets the corresponding bit in EEI

18.4.5.8 Clear Enable Request Register (CERQ)

18.4.5.8.1 Offset
Register Offset
CERQ 1Ah

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18.4.5.8.2 Function
The CERQ provides a simple memory-mapped mechanism to clear a given bit in the
ERQ to disable the DMA request for a given channel. The data value on a register write
causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a
global clear function, forcing the entire contents of the ERQ to be cleared, disabling all
DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.
NOTE
Disable a channel's hardware service request at the source
before clearing the channel's ERQ bit.

18.4.5.8.3 Diagram
Bits 7 6 5 4 3 2 1 0

R
0

CAER 0

CERQ 0
NOP

W
0

Reset 0 0 0 0 0 0 0 0

18.4.5.8.4 Fields
Field Function
7 No Op enable
0b - Normal operation
NOP
1b - No operation, ignore the other bits in this register
6 Clear All Enable Requests
0b - Clear only the ERQ bit specified in the CERQ field
CAER
1b - Clear all bits in ERQ
5-4 Reserved
—
3-0 Clear Enable Request
CERQ Clears the corresponding bit in ERQ.

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18.4.5.9 Set Enable Request Register (SERQ)

18.4.5.9.1 Offset
Register Offset
SERQ 1Bh

18.4.5.9.2 Function
The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ
to enable the DMA request for a given channel. The data value on a register write causes
the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set
function, forcing the entire contents of ERQ to be set.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.

18.4.5.9.3 Diagram
Bits 7 6 5 4 3 2 1 0

R
0

0
NOP

SAE

SER

W
0
R

Reset 0 0 0 0 0 0 0 0

18.4.5.9.4 Fields
Field Function
7 No Op enable
0b - Normal operation
NOP
1b - No operation, ignore the other bits in this register
6 Set All Enable Requests
0b - Set only the ERQ bit specified in the SERQ field
SAER
1b - Set all bits in ERQ
5-4 Reserved
—

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Field Function
3-0 Set Enable Request
SERQ Sets the corresponding bit in ERQ.

18.4.5.10 Clear DONE Status Bit Register (CDNE)

18.4.5.10.1 Offset
Register