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FSM - High Level Coding

The document discusses finite state machines (FSM) including their design, implementation in VHDL, and use for modeling synchronous sequential logic and digital systems. It describes FSM objectives like synthesis and analysis. FSM design style separates combinational and sequential logic. Standard coding styles can infer FSMs. Examples show FSMs for a multiplexer and string detector. FSM-based testbenches include stimulus generators and interface to DUTs. Work involves coding a VHDL model of a vending machine controller FSM and simulating it.

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Camilo Perez
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67 views39 pages

FSM - High Level Coding

The document discusses finite state machines (FSM) including their design, implementation in VHDL, and use for modeling synchronous sequential logic and digital systems. It describes FSM objectives like synthesis and analysis. FSM design style separates combinational and sequential logic. Standard coding styles can infer FSMs. Examples show FSMs for a multiplexer and string detector. FSM-based testbenches include stimulus generators and interface to DUTs. Work involves coding a VHDL model of a vending machine controller FSM and simulating it.

Uploaded by

Camilo Perez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

MEME LYFE CICLE STATE MACHINE

SYNCHRONOUS SEQUENTIAL
LOGIC
Finite State Machines
High level coding style

Digital Systems Design


OBJECTIVES
The objectives of the chapter are to describe:
• Synchronous sequential design
• Synthesis of a finite-state machine
• Analysis of a finite-state machine
• State assignment
• State optimization
• FSM VHDL programming
Finite State Machine (FSM)
Finite State Machine (FSM)
Finite State Machine (FSM)

Will require a
PROCESS
Finite State Machine (FSM)

can also be
implemented
using a PROCESS.

Will require a
PROCESS
Finite State Machine: Design Style

• The design of the sequential logic of


the state machine (is completely
separated from that of the
combinational logic section.

• All states of the machine are always


explicitly declared using an
enumerated data type.

• Standard coding style to infer a Finite


State Machine
Finite State Machine: Design Style
Finite State Machine: Design Style
Finite State Machine: Design Style
Finite State Machine: Design Style
Finite State Machine: Design Style
Finite State Machine: Design Style
Finite State Machine: Template
Finite State Machine: Template
Finite State Machine: Template
Finite State Machine: Template
FSM example: Synchronous Multiplexor

d=1

d=0
FSM example: Synchronous Multiplexor
FSM example: Synchronous Multiplexor
FSM example: Synchronous Multiplexor
FSM example: String Detector
outputs a ‘1’ whenever the sequence ‘‘111’’ occurs
FSM example: String Detector
FSM example: String Detector
FSM example: String Detector
Testbench with FSM
Traditional testbech A higher entity is created which
clk includes:
• Stimuli generator (Built-in Self Test BIST),
DUT
reset Output
Input and • PLL
signals test • DUT
signals

FSM-based testbech
BIST is a FSM-based
clk circuit
BIST DUT
reset Output
and
Input signals test
signals
Work in class: Vending Machine Controller
• Create project “vendingMachine”

• Complete the code of “[Link]”

• Read and understand the code of “test_signal_generator.vhd”

• Include a PLL module named “my_pll.vhd”

• Simulate using “vendingMachine_tb.vhd”

• Download the circuit to the board. Use SignalTab to verify operation


Work in class: Vending Machine Controller
ni => nickel_in (5c)
di => dime_in (10c)
qi => quarter_in (25c)
no => nickel_out
do =>dime_out
co => candy_out
Work in class: Vending Machine Controller
Work in class: Vending Machine Controller
Work in class: Vending Machine Controller
Test signal generator
Test signal generator
Test signal generator
Test signal generator
Test signal generator
Test signal generator
Test signal generator

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