Chapter 5




Flip-Flops, Registers, and Counters



 Set
Sensor
Memory On ⁄ Off
Alarm
element
Reset

Figure 5.1. Control of an alarm system.

 A B

Figure 5.2. A simple memory element.

Reset

Set Q

Figure 5.3. A memory element with NOR gates.

 R S R Qa Qb
Qa
0 0 0/1 1/0 (no change)
0 1 0 1
1 0 1 0
Qb 1 1 0 0
S

(a) Circuit (b) Truth table

t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time
(c) Timing diagram

Figure 5.4. A basic latch built with NOR gates.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.5. Gated SR latch.

 S
Q

Clk

Q
R

Figure 5.6. Gated SR latch with NAND gates.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.7. Gated D latch.

 t su
th

Clk

Figure 5.8. Setup and hold times.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.9. Master-slave D flip-flop.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.10. Comparison of level-sensitive and edge-triggered

D storage elements.
 1 P3

P1
2
5 Q

Clock

P2 6 Q
3

D Q

4 P4 Clock Q
D

(a) Circuit (b) Graphical symbol

Figure 5.11. A positive-edge-triggered D flip-flop.

Figure 5.12. Master-slave D flip-flop with Clear and Preset.
Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.13. Positive-edge-triggered D flip-flop with Clear

and Preset.
Figure 5.14. Timing for a flip-flop.
Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.15. T flip-flop.

 J
D Q Q
K Q Q

Clock

(a) Circuit

J K Q ( t + 1)
0 0 Q (t) J Q
0 1 0
1 0 1
K Q
1 1 Q (t )

(b) Truth table (c) Graphical symbol

Figure 5.16. JK flip-flop.

 Q1 Q2 Q3 Q4
In D Q D Q D Q D Q Out

Clock Q Q Q Q

(a) Circuit

In Q1 Q2 Q3 Q4 = Out
t0 1 0 0 0 0
t1 0 1 0 0 0
t2 1 0 1 0 0
t3 1 1 0 1 0
t4 1 1 1 0 1
t5 0 1 1 1 0
t6 0 0 1 1 1
t7 0 0 0 1 1

(b) A sample sequence

Figure 5.17. A simple shift register.

Figure 5.18. Parallel-access shift register.
 1 T Q T Q T Q

Clock Q Q Q

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 6 7 0

(b) Timing diagram

Figure 5.19. A three-bit up-counter.

 1 T Q T Q T Q

Clock Q Q Q

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 7 6 5 4 3 2 1 0

(b) Timing diagram

Figure 5.20. A three-bit down-counter.

 Clock cycle Q2 Q1 Q0
Q1 changes
0 0 0 0
1 0 0 1 Q2 changes
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

Table 5.1. Derivation of the synchronous up-counter.

 1 T Q T Q T Q T Q
Q0 Q1 Q2 Q3
Clock Q Q Q Q

(a) Circuit

Clock

Q0

Q1

Q2

Q3

Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

(b) Timing diagram

Figure 5.21. A four-bit synchronous up-counter.

 Enable T Q T Q T Q T Q

Clock Q Q Q Q

Clear_n

Figure 5.22. Inclusion of Enable and Clear capability.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.23. A four-bit counter with D flip-flops.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.24. A counter with parallel-load capability.

 1 Enable
0 D0 Q0
0 D1 Q1
0 D2 Q2
Load
Clock
Clock

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1

(b) Timing diagram

Figure 5.25. A modulo-6 counter with synchronous reset.

 1 T Q T Q T Q
Q0 Q1 Q2

Clock Q Q Q

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1 2

(b) Timing diagram

Figure 5.26. A modulo-6 counter with asynchronous reset.

Figure 5.27. A two-digit BCD counter.
Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.28. Ring counter.

Figure 5.29. Johnson counter.
Figure 5.30. Three types of storage elements in a schematic.
 Data
Clock

Latch

Figure 5.31. Gated D latch generated by CAD tools.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.32. Implementation of the schematic in Figure 5.30 in a CPLD.

Figure 5.33. Timing simulation of storage elements in Figure 5.30.
module D_latch (D, Clk, Q);
input D, Clk;
output reg Q;

always @(D, Clk)

if (Clk)
Q = D;

endmodule

Figure 5.34. Code for a gated D latch.

 module flipflop (D, Clock, Q);
input D, Clock;
output reg Q;

always @(posedge Clock)

Q = D;

endmodule

Figure 5.35. Code for a D flip-flop.

 module example5_3 (D, Clock, Q1, Q2);
input D, Clock;
output reg Q1, Q2;

always @(posedge Clock)

begin
Q1 = D;
Q2 = Q1;
end

endmodule

Figure 5.36. Incorrect code for two cascaded flip-flops.

 D D Q Q1

Clock Q

D Q Q2

Figure 5.37. Circuit for Example 5.3.

module example5_4 (D, Clock, Q1, Q2);
input D, Clock;
output reg Q1, Q2;

always @(posedge Clock)

begin
Q1 <= D;
Q2 <= Q1;
end

endmodule

Figure 5.38. Code for two cascaded flip-flops.

 Q1 Q2
D D Q D Q

Clock Q Q

Figure 5.39. Circuit defined in Figure 5.38.

module example5_5 (x1, x2, x3, Clock, f, g);
input x1, x2, x3, Clock;
output reg f, g;

always @(posedge Clock)

begin
f = x1 & x2;
g = f | x3;
end

endmodule

Figure 5.40. Code for Example 5.5.

 x3

x1 D Q g
x2
Q

D Q f

Clock Q

Figure 5.41. Circuit for Example 5.5.

module example5_6 (x1, x2, x3, Clock, f, g);
input x1, x2, x3, Clock;
output reg f, g;

always @(posedge Clock)

begin
f <= x1 & x2;
g <= f | x3;
end

endmodule

Figure 5.42. Code for Example 5.6.

 x3
D Q g

x1
D Q f
x2

Clock Q

Figure 5.43. Circuit for Example 5.6.

module flipflop (D, Clock, Resetn, Q);
input D, Clock, Resetn;
output reg Q;

always @(negedge Resetn, posedge Clock)

if (!Resetn)
Q <= 0;
else
Q <= D;

endmodule

Figure 5.44. D flip-flop with asynchronous reset.

module flipflop (D, Clock, Resetn, Q);
input D, Clock, Resetn;
output reg Q;

always @(posedge Clock)

if (!Resetn)
Q <= 0;
else
Q <= D;

endmodule

Figure 5.45. D flip-flop with synchronous reset.

module regn (D, Clock, Resetn, Q);
parameter n = 16;
input [n-1:0] D;
input Clock, Resetn;
output reg [n-1:0] Q;

always @(negedge Resetn, posedge Clock)

if (!Resetn)
Q <= 0;
else
Q <= D;

endmodule

Figure 5.46. Code for an n-bit register with asynchronous clear.

 module muxdff (D0, D1, Sel, Clock, Q);
input D0, D1, Sel, Clock;
output reg Q;

always @(posedge Clock)

if (!Sel)
Q <= D0;
else
Q <= D1;

endmodule

Figure 5.47. Code for a D flip-flop with a 2-to-1 multiplexer on the D input.
 module muxdff (D0, D1, Sel, Clock, Q);
input D0, D1, Sel, Clock;
output reg Q;
!
wire D;
assign D = Sel ? D1 : D0;
!
always @(posedge Clock)
Q <= D;

endmodule

Figure 5.48. Alternative code for a D flip-flop with a 2-to-1 multiplexer on the D input.
module shift4 (R, L, w, Clock, Q);
input [3:0] R;
input L, w, Clock;
output [3:0] Q;
wire [3:0] Q;

muxdff Stage3 (w, R[3], L, Clock, Q[3]);

muxdff Stage2 (Q[3], R[2], L, Clock, Q[2]);
muxdff Stage1 (Q[2], R[1], L, Clock, Q[1]);
muxdff Stage0 (Q[1], R[0], L, Clock, Q[0]);

endmodule

Figure 5.49. Hierarchical code for a four-bit shift register.

 module shift4 (R, L, w, Clock, Q);
input [3:0] R;
input L, w, Clock;
output reg [3:0] Q;

always @(posedge Clock)

if (L)
Q <= R;
else
begin
Q[0] <= Q[1];
Q[1] <= Q[2];
Q[2] <= Q[3];
Q[3] <= w;
end

endmodule

Figure 5.50. Alternative code for a four-bit shift register.

module shiftn (R, L, w, Clock, Q);
parameter n = 16;
input [n-1:0] R;
input L, w, Clock;
output reg [n-1:0] Q;
integer k;

always @(posedge Clock)

if (L)
Q <= R;
else
begin
for (k = 0; k < n-1; k = k+1)
Q[k] <= Q[k+1];
Q[n-1] <= w;
end

endmodule

Figure 5.51. An n-bit shift register.

module upcount (Resetn, Clock, E, Q);
input Resetn, Clock, E;
output reg [3:0] Q;

always @(negedge Resetn, posedge Clock)

if (!Resetn)
Q <= 0;
else if (E)
Q <= Q + 1;

endmodule

Figure 5.52. Code for a four-bit up-counter.

 module upcount (R, Resetn, Clock, E, L, Q);
input [3:0] R;
input Resetn, Clock, E, L;
output reg [3:0] Q;

always @(negedge Resetn, posedge Clock)

if (!Resetn)
Q <= 0;
else if (L)
Q <= R;
else if (E)
Q <= Q + 1;

endmodule

Figure 5.53. A four-bit up-counter with parallel load.

 module downcount (R, Clock, E, L, Q);
parameter n = 8;
input [n-1:0] R;
input Clock, L, E;
output reg [n-1:0] Q;

always @(posedge Clock)

if (L)
Q <= R;
else if (E)
Q <= Q - 1;

endmodule

Figure 5.54. A down-counter with a parallel load.

module updowncount (R, Clock, L, E, up_down, Q);
parameter n = 8;
input [n-1:0] R;
input Clock, L, E, up_down;
output reg [n-1:0] Q;
always @(posedge Clock)
if (L)
Q <= R;
else if (E)
Q <= Q + (up_down ? 1 : -1);

endmodule

Figure 5.55. Code for an up/down counter.

Figure 5.56. Providing an enable input for a D flip-flop.
module rege (D, Clock, Resetn, E, Q);
input D, Clock, Resetn, E;
output reg Q;

always @(posedge Clock, negedge Resetn)

if (Resetn == 0)
Q <= 0;
else if (E)
Q <= D;

endmodule

Figure 5.57. Code for a D flip-flop with enable.

module regne (R, Clock, Resetn, E, Q);
parameter n = 8;
input [n-1:0] R;
input Clock, Resetn, E;
output reg [n-1:0] Q;

always @(posedge Clock, negedge Resetn)

if (Resetn == 0)
Q <= 0;
else if (E)
Q <= R;

endmodule

Figure 5.58. An n-bit register with an enable input.

Figure 5.59. A shift register with parallel load and enable control inputs.
 module shiftrne (R, L, E, w, Clock, Q);
parameter n = 4;
input [n-1:0] R;
input L, E, w, Clock;
output reg [n-1:0] Q;
integer k;

always @(posedge Clock)

begin
if (L)
Q <= R;
else if (E)
begin
Q[n-1] <= w;
for (k = n-2; k >= 0; k = k-1)
Q[k] <= Q[k+1];
end
end
endmodule

Figure 5.60. A left-to-right shift register with an enable input.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.61. A reaction-timer circuit.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.62. Code for the two-digit BCD counter in Figure 5.27.
Figure 5.63. Code for the BCD-to-7-segment decoder.
Figure 5.64. Code for the reaction timer.
Figure 5.65. Simulation of the reaction-timer circuit.
Figure 5.66. A simple flip-flop circuit.
Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.67. A 4-bit counter.

Figure 5.68. A general example of clock skew.
Figure 5.69. A modified version of the reaction-timer circuit.
Figure 5.70. Circuit for Example 5.18.
Figure 5.71. Circuit for Example 5.19.
Figure 5.72. Summary of the behavior of the circuit in Figure 5.71.
Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.73. Circuit for Example 5.20.

module vend (N, D, Q, Resetn, Coin, Z);
input N, D, Q, Resetn, Coin;
output Z;
wire [4:0] X;
reg [5:0] S;
!
assign X[0] = N | Q;
assign X[1] = D;
assign X[2] = N;
assign X[3] = D | Q;
assign X[4] = Q;
assign Z = S[5] | (S[4] & S[3] & S[2] & S[1]);
always @(negedge Coin, negedge Resetn)
if (Resetn = = 1’b0)
S <= 5’b00000;
else
S <= {1’b0, X} + S;
end

endmodule

Figure 5.74. Code for Example 5.21.

Please see “portrait orientation” PowerPoint file for Chapter 5

Figure 5.75. A faster 4-bit counter.

Figure 5.76. A circuit with clock skews.
Clock

Figure P5.1. Timing diagram for Problem 5.1.

Figure P5.2. Circuit for Problem 5.8.
 Q0 Q1 Q2

1 T Q T Q T Q

Clock Q Q Q

Figure P5.3. The circuit for Problem 5.17.

 J S Q S Q Q
Clock Clk Clk

K R Q R Q Q

Figure P5.4. Circuit for Problem 5.18.

 f

Figure P5.5. A ring oscillator.

 Reset

Interval
100 ns

Figure P5.6. Timing of signals for Problem 5.24.

 D
Q

Clock

Q
A

Clock 1
0

1
D
0

A 1
0

Q 1
0

Figure P5.7. Circuit and timing diagram for Problem 5.25.

Clock 1
0

1
Start
0

1
f
0

1
g
0

Figure P5.8. Timing diagram for Problem 5.26.

module lfsr (R, L, Clock, Q);
input [0:2] R;
input L, Clock;
output reg [0:2] Q;

always @(posedge Clock)

if (L)
Q <= R;
else
Q <= {Q[2], Q[0] ^ Q[2], Q[1]};

endmodule

Figure P5.9. Code for a linear-feedback shift register.

module lfsr (R, L, Clock, Q);
input [0:2] R;
input L, Clock;
output reg [0:2] Q;

always @(posedge Clock)

if (L)
Q <= R;
else
Q <= {Q[2], Q[0], Q[1] ^ Q[2]};

endmodule

Figure P5.10. Code for a linear-feedback shift register.

 module lfsr (R, L, Clock, Q);
input [0:2] R;
input L, Clock;
output reg [0:2] Q;

always @(posedge Clock)

if (L)
Q <= R;
else
begin
Q[0] = Q[2];
Q[1] = Q[0] ^ Q[2];
Q[2] = Q[1];
end

endmodule

Figure P5.11. Code for Problem 7.30.

module lfsr (R, L, Clock, Q);
input [0:2] R;
input L, Clock;
output reg [0:2] Q;

always @(posedge Clock)

if (L)
Q <= R;
else
begin
Q[0] = Q[2];
Q[1] = Q[0];
Q[2] = Q[1] ^ Q[2];
end

endmodule

Figure P5.12. Code for Problem 5.31.