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Clock Generator Function

The document discusses the clock generator and driver chip 8284 used with the 8086 CPU. It provides clock signals, reset logic, and ready logic. The 8284 uses a quartz crystal oscillator operating at 3 times the CPU frequency to generate precise clock signals. It also describes the pins and interfacing of the 8284 to the 8086 CPU to provide timing functions.

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Bala Gopal
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0% found this document useful (0 votes)
305 views16 pages

Clock Generator Function

The document discusses the clock generator and driver chip 8284 used with the 8086 CPU. It provides clock signals, reset logic, and ready logic. The 8284 uses a quartz crystal oscillator operating at 3 times the CPU frequency to generate precise clock signals. It also describes the pins and interfacing of the 8284 to the 8086 CPU to provide timing functions.

Uploaded by

Bala Gopal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

 Clock Generator Functions

 Crystal Oscillator
 8284 Pins
 8284 Interfacing to the 8086
 RC Circuit Charging
 The 8086 CPU has 16 data lines and 20 address
lines.
 The CPU uses time multiplexing for the Address,
data, and some status lines.
 The Clock Generator and Driver 8284 is a device
capable of providing the CPU with
−Clock
−Reset Logic
−Ready Logic
 The 8284 clock generator uses a crystal oscillator
that must be 3 times the frequency of the CPU
(15 MHz Crystal).
 A crystal oscillator (See Figure 1) is an electronic
oscillator circuit that uses the mechanical
resonance of a vibrating crystal of piezoelectric
material to create an electrical signal with a very
precise frequency.
 The most common type of piezoelectric
resonator used is the quartz crystal (See Figure
2), so oscillator circuits incorporating them
became known as crystal oscillators
Figure 1: Two types of crystal oscillator.
Figure 2: Cluster of natural quartz crystals.
 When a crystal of quartz is properly cut and
mounted (See Figure 3), it can be made to distort in
an electric field by applying a voltage to an electrode
near or on the crystal.
 This property is known as electrostriction or inverse
piezoelectricity.
 When the field is removed, the quartz will generate
an electric field as it returns to its previous shape,
and this can generate a voltage.
 The result is that a quartz crystal behaves like a
circuit composed of an inductor, capacitor and
resistor, with a precise resonant frequency (See RLC
circuit in Figure 4)
Figure 3: Internal construction of quartz crystal oscillators.
Figure 4: Schematic symbol and equivalent circuit for a quartz crystal in an oscillator
 X1 & X2 (Crystal In):
−X1 and X2 are the pins to which
a crystal is attached.
−The crystal frequency is 3 times
the desired processor clock
frequency.
 F/C (Frequency/Crystal
Select):
−When LOW  CLK is generated
by the crystal.
−When HIGH  CLK is generated
by the EFI input
 EFI (External Frequency
Input):
−When F/C is HIGH, CLK is
generated from the input
frequency appearing on this
pin.
−The input signal is a square
wave 3 times the frequency of
the desired CLK output.
 CLK (Processor Clock):
−CLK is the clock output used by
the processor and all devices
which directly connect to the
processor’s local bus.
−CLK has an output frequency
which is 1/3 of the crystal or EFI
input frequency and a 1/3 duty
cycle.
 PCLK (Peripheral Clock):
−PCLK is a peripheral clock signal
whose output frequency is 1/2
that of CLK and has a 50% duty
cycle.
 OSC (Oscillator Output):
−OSC is the output of the
internal oscillator circuitry.
−Its frequency is equal to that of
the crystal.
 RES (Reset In):
−It is an active LOW signal which is
used to generate RESET.
−The 82C84A provides a trigger
input so that an RC connection can
be used to establish the power-up
reset of proper duration.
 RESET:
−It is an active HIGH signal which is
used to reset the 80C86 family
processors.
−Its timing characteristics are
determined by RES.
 AEN1’, AEN2’(address
enable) : provided
−to qualify bus ready signal
RDY1, RDY2
 RDY1, RDY2(bus ready) :
provided,
−in conjunction with
AEN1’,AEN2’ pins, to cause
wait states
 Reset Logic:
−Initially the capacitor is uncharged.
−When power is switched on, the RES signal is at logic 0
(RESET signal is at logic 1).
−The capacitor starts charging with time constant
(RC=10Kx10uF).
−When the voltage across the capacitor becomes equal to
the minimum High voltage of the 8284 (2V), the RES signal
goes to logic 1 (RESET signal goes to logic 0).
−If the Reset button is pressed, the capacitor is discharged
through the switch.
−When the Button is released, the capacitor starts charging
as before.
−The diode is used to short circuit the resistor during switch
off, thus discharge the capacitor fast.

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