ACPL-331J

1.5 Amp Output Current IGBT Gate Driver Optocoupler

with Integrated (VCE) Desaturation Detection, UVLO,
Fault Status Feedback and Active Miller Clamping

Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product

Description Features
The ACPL-331J is an advanced 1.5 A output current, easy- • Under Voltage Lock-Out Protection (UVLO)
to-use, intelligent gate driver which makes IGBT VCE fault with Hysteresis
protection compact, affordable, and easy-to implement. • Desaturation Detection
Features such as integrated VCE detection, under
voltage lockout (UVLO), “soft” IGBT turn-off, isolated • Miller Clamping
open collector fault feedback and active Miller clamping • Open Collector Isolated fault feedback
provide maximum design flexibility and circuit protec- • “Soft” IGBT Turn-off
tion.
• Fault Reset by next LED turn-on (low to high) after
The ACPL-331J contains a GaAsP LED. The LED is optically fault mute period
coupled to an integrated circuit with a power output
• Available in SO-16 package
stage. ACPL-331J is ideally suited for driving power IGBTs
and MOSFETs used in motor control inverter applications. • Safety approvals: UL approved, 3750 VRMS for 1
The voltage and current supplied by these optocouplers minute, CSA approved, IEC/EN/DIN-EN 60747-5-2
make them ideally suited for directly driving IGBTs with approved VIORM = 891 VPEAK
ratings up to 1200 V and 100 A. For IGBTs with higher
ratings, the ACPL-331J can be used to drive a discrete
Specifications
power stage which drives the IGBT gate. The ACPL-331J • 1.5 A maximum peak output current
has an insulation voltage of VIORM = 891 VPEAK. • 1.0 A minimum peak output current
Block Diagram • 250 ns maximum propagation delay over
13
temperature range
VCC2
UVLO
• 100 ns maximum pulse width distortion (PWD)
ANODE
6, 7 D
R
• 15 kV/µs minimum common mode rejection (CMR)
5, 8 I 11
VOUT
at VCM = 1500 V
CATHODE V
DESAT
LED1 E
14 • ICC(max) < 5 mA maximum supply current
R
DESAT

9, 12
• Wide VCC operating range: 15 V to 30 V over
SHIELD
VEE temperature range
VCLAMP • 1.0 A Miller Clamp. Clamp pin short to VEE if not used
2
VCC1
10
VCLAMP • Wide operating temperature range: –40°C to 100°C
LED2
3 VE
FAULT 16 Applications
• Isolated IGBT/Power MOSFET gate drive
1, 4
VS
SHIELD
15
VLED • AC and brushless DC motor drives
• Industrial inverters and Uninterruptible Power Supply
(UPS)

CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Pin Description Pin Symbol Description
1 VS Input Ground
1 VS VE 16 2 VCC1 Positive input supply voltage. (4.5 V to 5.5 V)
3 FAULT Fault output. FAULT changes from a high impedance state
2 VCC1 VLED 15 to a logic low output within 5 µs of the voltage on the
DESAT pin exceeding an internal reference voltage of 6.5 V.
3 FAULT
FAULT output is an open collector which allows the FAULT
DESAT 14
outputs from all ACPL-331J in a circuit to be connected
together in a “wired OR” forming a single fault bus for inter-
4 VS VCC2 13 facing directly to the micro-controller.
4 VS Input Ground
5 CATHODE VEE 12
5 CATHODE Cathode
6 ANODE Anode
6 ANODE VOUT 11
7 ANODE Anode
7 ANODE VCLAMP 10 8 CATHODE Cathode
9 VEE Output supply voltage.
8 CATHODE VEE 9 10 VCLAMP Miller clamp
11 VOUT Gate drive voltage output
12 VEE Output supply voltage.
13 VCC2 Positive output supply voltage
14 DESAT Desaturation voltage input. When the voltage on DESAT
exceeds an internal reference voltage of 6.5 V while the
IGBT is on, FAULT output is changed from a high impedance
state to a logic low state within 5 µs.
15 VLED LED anode. This pin must be left unconnected for guaran-
teed data sheet performance. (For optical coupling testing
only)
16 VE Common (IGBT emitter) output supply voltage.

Ordering Information
ACPL-331J is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option Surface IEC/EN/DIN EN
Part number RoHS Compliant Package Mount Tape& Reel 60747-5-2 Quantity
ACPL-331J -000E SO-16 X X 45 per tube
-500E X X X 850 per reel

To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-331J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-2 Safety Approval in RoHS compliant.
Example 2:
ACPL-331J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-
2 Safety Approval and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.


Package Outline Drawings
0.018 0.050
(0.457) (1.270) LAND PATTERN RECOMMENDATION

16 15 14 13 12 11 10 9

TYPE NUMBER
DATE CODE
A 332J
YYWW 0.295 ± 0.010 0.458 (11.63)
(7.493 ± 0.254)

0.085 (2.16)
1 2 3 4 5 6 7 8
0.406 ± 0.10
(10.312 ± 0.254) 0.025 (0.64)

0.345 ± 0.010
9° (8.763 ± 0.254) ALL LEADS
TO BE
COPLANAR
± 0.002

0.138 ± 0.005
0.018 0- 8° 0.008 ± 0.003
(3.505 ± 0.127)
(0.457) 0.025 MIN. (0.203 ± 0.076)
STANDOFF
0.408 ± 0.010
(10.363 ± 0.254)

ACPL-331J 16-Lead Surface Mount Package

Dimensions in inches (millimeters)

Notes: Initial and continued variation in the color of the ACPL-
331J’s white mold compound is normal and does note affect device
performance or reliability.
Floating Lead Protrusion is 0.25 mm (10 mils) max.


Solder Reflow Thermal Profile
300
PREHEATING RATE 3 ° C + 1 ° C/ - 0.5 ° C/SEC.
REFLOW HEATING RATE 2.5 ° C ± 0.5 ° C/SEC. PEAK
PEAK
TEMP.
TEMP.
245 ° C
240 ° C
PEAK
TEMP.
230 ° C
200
TEMPERATURE ( ° C)

2.5 ° C ± 0.5 ° C/SEC.

SOLDERING
30 TIME
160 ° C
150 ° C SEC. 200 ° C
140 ° C
30
3 ° C + 1 ° C/ - 0.5 ° C SEC.

100
PREHEATING TIME
150 ° C, 90 + 30 SEC. 50 SEC.

TIGHT
ROOM TYPICAL
TEMPERATURE LOOSE

0
0 50 100 150 200 250

TIME (SECONDS)

Note: Non-halide flux should be used.

Recommended Pb-Free IR Profile

TIME WITHIN 5°C of ACTUAL
PEAK TEMPERATURE
tp
20-40 SEC.
260 +0/-5 °C
Tp
217 °C
TL
RAMP-UP
3 ° C/SEC. MAX. RAMP-DOWN
TEMPERATURE

150 - 200 °C 6 °C/SEC. MAX.

T smax
T smin
ts tL
PREHEAT 60 to 150 SEC.
60 to 180 SEC.

25
t 25 °C to PEAK
TIME
NO TES:
THE TIME FROM 25°C to PEAK TEMPERATURE = 8 MINUTES MAX.
T smax = 200 °C, Tsmin = 150 °C

Note: Non-halide flux should be used.


Regulatory Information
The ACPL-331J is approved by the following organizations:
IEC/EN/DIN EN 60747-5-2 UL
Approval under: Approval under UL 1577, component recognition
IEC 60747-5-2 :1997 + A1:2002 program up to VISO = 3750 VRMS. File E55361.
EN 60747-5-2:2001 + A1:2002 CSA
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
Approval under CSA Component Acceptance Notice #5,
File CA 88324.

Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*

Description Symbol Characteristic Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms I – IV
for rated mains voltage ≤ 300 Vrms I – IV
for rated mains voltage ≤ 600 Vrms I – III
Climatic Classification 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 891 Vpeak
Input to Output Test Voltage, Method b**, VPR 1670 Vpeak
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5
pC
Input to Output Test Voltage, Method a**, VPR 1336 Vpeak
VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec, Partial discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage tini = 10 sec) VIOTM 6000 Vpeak
Safety-limiting values – maximum values allowed in the event of a failure
Case Temperature TS 175 °C
Input Current IS, INPUT 400 mA
Output Power PS, OUTPUT 1200 mW
Insulation Resistance at TS, VIO = 500 V RS >109 W

* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.
Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)

1400
P S , OUTPUT
1200 P S , INPUT

1000
PS - POWER - mW

800

600

400

200

0
0 25 50 75 100 125 150 175 200
TS - CASE TEMPERATURE - °C


Table 2. Insulation and Safety Related Specifications
Parameter Symbol ACPL-331J Units Conditions
Minimum External Air L(101) 8.3 Mm Measured from input terminals to output terminals,
Gap (Clearance) shortest distance through air.
Minimum External L(102) 8.3 Mm Measured from input terminals to output terminals,
Tracking (Creepage) shortest distance path along body.
Minimum Internal 0.5 Mm Through insulation distance conductor to conductor,
Plastic Gap (Internal usually the straight line distance thickness between the
Clearance) emitter and detector.
Tracking Resistance CTI >175 V DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking
Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Table 3. Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note
Storage Temperature TS -55 125 °C
Operating Temperature TA -40 100 °C 2
Output IC Junction Temperature TJ 125 °C 2
Average Input Current IF(AVG) 25 mA 1
Peak Transient Input Current IF(TRAN) 1.0 A
(<1 µs pulse width, 300pps)
Reverse Input Voltage VR 5 V
“High” Peak Output Current IOH(PEAK) 1.5 A 3
“Low” Peak Output Current IOL(PEAK) 1.5 A 3
Positive Input Supply Voltage VCC1 -0.5 5.5 V
FAULT Output Current IFAULT 8.0 mA
FAULT Pin Voltage VFAULT -0.5 VCC1 V
Total Output Supply Voltage (VCC2 - VEE) -0.5 33 V
Negative Output Supply Voltage (VE - VEE) -0.5 15 V 6
Positive Output Supply Voltage (VCC2 - VE) -0.5 33 - (VE - VEE) V
Gate Drive Output Voltage VO(PEAK) -0.5 VCC2 V
Peak Clamping Sinking Current IClamp 1.0 A
Miller Clamping Pin Voltage VClamp -0.5 VCC2 V
DESAT Voltage VDESAT VE VE + 10 V
Output IC Power Dissipation PO 600 mW 2
Input IC Power Dissipation PI 150 mW 2
Solder Reflow Temperature Profile See Package Outline Drawings section

Table 4. Recommended Operating Conditions

Parameter Symbol Min. Max. Units Note
Operating Temperature TA - 40 100 °C 2
Total Output Supply Voltage (VCC2 - VEE) 15 30 V 7
Negative Output Supply Voltage (VE - VEE) 0 15 V 4
Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE) V
Input Current (ON) IF(ON) 8 12 mA
Input Voltage (OFF) VF(OFF) - 3.6 0.8 V


Table 5. Electrical Specifications (DC)
Unless otherwise noted, all typical values at TA = 25°C, VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specifications are at Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
FAULT Logic Low VFAULTL 0.1 V IFAULT = 1.1 mA, VCC1 = 5.5V
Output Voltage 0.1 V IFAULT = 1.1 mA, VCC1 = 3.3V
FAULT Logic High IFAULTH 0.003 µA VFAULT = 5.5 V, VCC1 = 5.5V
Output Current 0.003 µA VFAULT = 3.3 V, VCC1 = 3.3V
High Level IOH -0.3 -0.75 A VO = VCC2 – 4 4, 18 5
Output Current -1.0 A VO = VCC2 – 15 3
Low Level IOL 0.3 0.75 A VO = VEE + 2.5 5, 19 5
Output Current
1.0 A VO = VEE + 15 3
Low Level Output Current IOLF 90 140 230 mA VOUT - VEE = 14 V 6
During Fault Condition
High Level VOH VCC-3.5 VCC-2.5 V IO = 100 mA 2, 4, 7, 8,9
Output Voltage VCC-2.9 VCC-2.0 V IO = -650 µA 20 23
Low Level VOL 0.17 0.5 V IO = 100 mA 3, 5,
Output Voltage 21
Clamp Pin Threshold VtClamp 2.0 V
Voltage
Clamp Low Level ICL 0.21 0.7 A VO = VEE + 2.5
Sinking Current
High Level Supply Current ICC2H 2.5 5 mA IO = 0 mA 6, 7, 9
Low Level Supply Current ICC2L 2.5 5 mA IO = 0 mA 23

Blanking Capacitor ICHG 0.13 -0.24 -0.33 mA VDESAT = 2 V 8, 24 9, 10

Charging Current
Blanking Capacitor IDSCHG 10 30 mA VDESAT = 7.0 V 25
Discharge Current
DESAT Threshold VDESAT 6 6.5 7.5 V VCC2 -VE >VUVLO- 9, 27 9
UVLO Threshold VUVLO+ 10.5 11.6 12.5 V VO > 5 V 7, 9, 11
VUVLO- 9.2 10.3 11.1 V VO < 5 V 7, 9, 12
UVLO Hysteresis (VUVLO+ 0.4 1.3 V
- VUVLO-)
Threshold Input Current IFLH 2.0 8 mA IO = 0 mA, VO > 5 V
Low to High
Threshold Input Voltage VFHL 0.8 V
High to Low
Input Forward Voltage VF 1.2 1.6 1.95 V IF = 10 mA
Temperature Coefficient DVF/DTA -1.3 mV/°C
of Input Forward Voltage
Input Reverse Breakdown BVR 5 V IR = 10 µA
Voltage
Input Capacitance CIN 70 pF f = 1 MHz, VF = 0 V


Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values at TA = 25°C, VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specifications are at Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay Time tPLH 100 180 250 ns Rg = 20 W, Cg = 5 nF, 1, 10, 13, 15
to High Output Level f = 10 kHz, 11, 12,
Propagation Delay Time tPHL 100 180 250 ns Duty Cycle = 50%, 13, 26
to Low Output Level IF = 10 mA, VCC2 = 30 V

Pulse Width Distortion PWD -100 20 100 ns 14, 17

Propagation Delay Difference (tPHL - tPLH) -350 350 ns 17, 16
Between Any Two Parts or PDD
Channels
Rise Time tR 50 ns
Fall Time tF 50 ns
DESAT Sense to 90% VO Delay tDESAT(90%) 0.15 0.3 µs CDESAT = 100pF, RF=2.1kΩ, 14, 27, 19
Rg = 20 W, Cg = 5 nF, 34
VCC2 = 30 V
DESAT Sense to 10% VO Delay tDESAT(10%) 1.1 1.5 µs CDESAT = 100pF, RF=2.1kΩ , 15, 16,
Rg = 20 W, Cg = 5 nF, 17, 27,
VCC2 = 30 V 34
DESAT Sense to Low Level tDESAT(FAULT) 0.25 0.5 µs CDESAT = 100pF, RF = 2.1 27, 34 18
FAULT Signal Delay kW,
Rg = 20 W, Cg = 5 nF,
VCC2 = 30 V
DESAT Sense to DESAT tDESAT(LOW) 0.25 µs CDESAT = 100pF, RF = 2.1 27, 34 19
Low Propagation Delay kW,
Rg = 20 W, Cg = 5 nF,
VCC2 = 30 V
DESAT Input Mute tDESAT(MUTE) 5 µs 34 20
RESET to High Level FAULT tRESET(FAULT) 0.3 1 2.0 µs CDESAT = 100pF,
Signal Delay RF = 2.1 kW,
Rg = 20 W, Cg = 5 nF,
VCC1 = 5.5V, VCC2 = 30 V
0.8 1.5 2.5 µs CDESAT = 100pF,
RF = 2.1 kW,
Rg = 20 W, Cg = 5 nF,
VCC1 = 3.3V, VCC2 = 30 V
Output High Level Common |CMH| 15 25 kV/µs TA = 25°C, IF = 10 mA 28, 29, 21
Mode Transient Immunity VCM = 1500 V, VCC2 = 30 V 30, 31
Output Low Level Common |CML| 15 25 kV/µs TA = 25°C, VF = 0 V 28, 29, 22
Mode Transient Immunity VCM = 1500 V, VCC2 = 30 V 30, 31

Table 7. Package Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary VISO 3750 Vrms RH < 50%, t = 1 min., 6, 7
Withstand Voltage TA = 25°C
Input-Output Resistance RI-O > 109 W VI-O = 500 V 7
Input-Output Capacitance CI-O 1.3 pF freq=1 MHz
Output IC-to-Pins 9 &10 q09-10 30 °C/W TA = 25°C
Thermal Resistance


Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require derating.
3. Maximum pulse width = 10 µs. This value is intended to allow for component tolerances for designs with IO peak minimum = 1.0 A.
Derate linearly from 2.0 A at +25°C to 1.5 A at +100°C. This compensates for increased IOPEAK due to changes in VOL over temperature.
4. This supply is optional. Required only when negative gate drive is implemented.
5. Maximum pulse width = 50 µs.
6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
7. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 12.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will
approach VCC as IOH approaches zero units.
8. Maximum pulse width = 1.0 ms.
9. Once VO of the ACPL-331J is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the ACPL-331J will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 12.5 V, DESAT will remain functional until VUVLO- < 9.2 V. Thus, the
DESAT detection and UVLO features of the ACPL-331J work in conjunction to ensure constant IGBT protection.
10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.
11. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE
12. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE
13. This load condition approximates the gate load of a 1200 V/75A IGBT.
14. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.
15. As measured from IF to VO.
16. The difference between tPHL and tPLH between any two ACPL-331J parts under the same test conditions.
17. As measured from ANODE, CATHODE of LED to VOUT
18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
19. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. This is supply
voltage dependent.
20. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation
(Auto Reset) topic in the application information section.
21. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 2.1 kΩ pull-up resistor is needed in fault detection mode.
22. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
23. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 µA
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.


Figure 1. Timing Curve

0 0.25
(VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V

VOL - OUTPUT LOW VOLTAGE - V

------I OUT = -100mA
-0.5 0.2
____I OUT = -650uA

-1
0.15
-1.5
0.1
-2

0.05
-2.5

-3 0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TA - TEMPERATURE - oC
TA - TEMPERATURE - o C

Figure 2. VOH vs. temperature Figure 3. VOL vs. temperature

30.0 4
(VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V

_ _ _ _ 100 o C _ _ _ _ 100 o C
______ 25 o C ______ 25 o C
VOL - OUTPUT LOW VOLTAGE - V

29.5 3 --------- -40 o C

--------- -40 o C

29.0 2

28.5
1

28.0
0 0.2 0.4 0.6 0.8 1 0
0 0.5 1 1.5
IOH - OUTPUT HIGH CURRENT - A
IOL - OUTPUT LOW CURRENT - A

Figure 4. VOH vs. IOH Figure 5. VOL vs. IOL

10
 3.50 2.65

ICC2 - OUTPUT SUPPLY CURRENT - mA

ICC2 - OUTPUT SUPPLY CURRENT - mA
--------- I CC2 H
3.25 - ---- ---- I CC2 H _________ I CC2 L
2.55
_________ I CC2 L
3.00

2.75 2.45

2.50
2.35
2.25

2.00 2.25
-40 -20 0 20 40 60 80 100 15 20 25 30
TA - TEMPERATURE - o C VCC2 - SUPPLY VOLTAGE - V

Figure 6. ICC2 vs. temperature Figure 7. ICC2 vs. VCC2

-0.20 7.5

VDESAT - DESAT THRESHOLD - V

ICH - BLANKING CAPACITOR
CHARGING CURRENT - mA

-0.25 7.0

-0.30 6.5

-0.35 6.0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
T A -TEMPERATURE - o C TA - TEMPERATURE - o C

Figure 8. ICHG vs. temperature Figure 9. DESAT threshold vs. temperature

300 300
---------- t PLH ---------- t PLH
_______t PHL _______t PHL
TP - PROPAGATION DELAY - ns

TP - PROPAGATION DELAY - ns

250 250

200 200

150 150

100 100
-40 -20 0 20 40 60 80 100 15 20 25 30
TA - TEMPERATURE - oC Vcc - SUPPLY VOLTAGE - V

Figure 10. Propagation delay vs. temperature Figure 11. Propagation delay vs. supply voltage

11
 300 300
---------- t PLH
---------- t PLH

TP - PROPAGATION DELAY - ns
TP - PROPAGATION DELAY - ns

_______t PHL
_______ t PHL
250
200

200

100
150

100 0
0 10 20 30 40 50 0 10 20 30 40 50
LOAD RESISTANCE - ohm LOAD CAPACITANCE - nF

Figure 12. Propagation delay vs. load resistance Figure 13. Propagation delay vs. load capacitance

250 2.0

TDESAT10% - DESAT Sense to 10% Vo Delay - ns

TDESAT90% - DESAT Sense to 90% Vo Delay - ns

------- V cc2 =15V

_____ V cc2 =30V
1.5
200

1.0

150
0.5

100 0.0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
T A - TEMPERATURE - o C T A - TEMPERATURE - o C

Figure 14. DESAT sense to 90% VOUT delay vs. temperature Figure 15. DESAT sense to 10% VOUT delay vs. temperature

4.0 0.012
TDESAT10% - DESAT Sense to 10% Vo Delay - ns
TDESAT10% - DESAT Sense to 10% Vo Delay - ns

------- V cc2 =15V

------- V cc2 =15V _____ V cc2 =30V
3.0 _____ V cc2 =30V
0.008

2.0

0.004
1.0

0.000
0.0 0 10 20 30 40 50
10 20 30 40 50
LOAD CAPACITANCE-nF
LOAD RESISTANCE-ohm

Figure 16. DESAT sense to 10% VOUT delay vs. load resistance Figure 17. DESAT sense to 10% VOUT delay vs. load capacitance

12
 1 VS VE 16

2 VCC1 VLED 15

3 FAULT DESAT 14 0.1µF

4 VS VCC2 13
15V Pulsed
5 CATHODE VEE 12 +_
IOUT
6 ANODE VOUT 11 30V
0.1µF
+_
7 ANODE VCLAMP 10
10mA
8 CATHODE VEE 9

Figure 18. IOH Pulsed test circuit

1 VS VE 16

2 VCC1 VLED 15

3 FAULT DESAT 14 0.1µF

4 VS VCC2 13
15V Pulsed
5 CATHODE VEE 12
IOUT
6 ANODE VOUT 11 30V
0.1µF
+_
7 ANODE VCLAMP 10 +_
8 CATHODE VEE 9

Figure 19. IOL Pulsed test circuit

1 VS VE 16

2 VCC1 VLED 15

3 FAULT DESAT 14 0.1µF

4 VS VCC2 13

5 CATHODE VEE 12
VOUT
6 ANODE VOUT 11 30V
0.1µF
+_
7 ANODE VCLAMP 10
10mA 100mA
8 CATHODE VEE 9

Figure 20. VOH Pulsed test circuit

13
 1 VS VE 16

2 VCC1 VLED 15

3 FAULT DESAT 14 0.1µF

4 VS VCC2 13
100mA
5 CATHODE VEE 12
VOUT
6 ANODE VOUT 11 30V
0.1µF
+_
7 ANODE VCLAMP 10

8 CATHODE VEE 9

Figure 21. VOL Pulsed test circuit

1 VS VE 16

2 VCC1 VLED 15

3 FAULT DESAT 14 0.1µF

4 VS VCC2 13

ICC2
5 CATHODE VEE 12

6 ANODE VOUT 11 30V

0.1µF
+_
7 ANODE VCLAMP 10
10mA
8 CATHODE VEE 9

Figure 22. ICC2H test circuit

1 VS VE 16

2 VCC1 VLED 15

3 FAULT DESAT 14 0.1µF

4 VS VCC2 13

ICC2
5 CATHODE VEE 12

6 ANODE VOUT 11 30V

0.1µF
+_
7 ANODE VCLAMP 10

8 CATHODE VEE 9

Figure 23. ICC2L test circuit

14
 1 VS VE 16
ICHG
2 VCC1 VLED 15

3 FAULT DESAT 14 0.1µF

4 VS VCC2 13

5 CATHODE VEE 12

6 ANODE VOUT 11 30V

0.1µF
+_
7 ANODE VCLAMP 10
10mA
8 CATHODE VEE 9

Figure 24. ICHG Pulsed test circuit

1 VS VE 16

+_ 7V
2 VCC1 VLED 15

3 FAULT DESAT 14 0.1µF

IDSCHG
4 VS VCC2 13

5 CATHODE VEE 12

6 ANODE VOUT 11 30V

0.1µF
+_
7 ANODE VCLAMP 10

8 CATHODE VEE 9

Figure 25. IDSCHG test circuit

1 VS VE 16

2 VCC1 VLED 15

3 FAULT DESAT 14 0.1µF

4 VS VCC2 13

5 CATHODE VEE 12
VOUT
6 ANODE VOUT 11 30V
20Ω 0.1µF
+_
7 ANODE VCLAMP 10
5nF

8 CATHODE VEE 9
10mA, 10kHz,
50% Duty Cycle

Figure 26. tPLH, tPHL, tf, tr, test circuit

15
 1 VS VE 16

2 VCC1 VLED 15 VIN

2.1kΩ
VFAULT 3 FAULT DESAT 14 0.1µF

4 VS VCC2 13
5V +_
5 CATHODE VEE 12
VOUT
6 ANODE VOUT 11 30V
20Ω 0.1µF
+_
7 ANODE VCLAMP 10
10mA 5nF
8 CATHODE VEE 9

Figure 27. tDESAT fault test circuit

1 VS VE 16
5V
2 VCC1 VLED 15
2.1kΩ

3 FAULT DESAT 14
15pF
30V
4 VS VCC2 13
SCOPE
0.1µF
5 CATHODE VEE 12
20Ω
6 ANODE VOUT 11
0.1µF
430Ω
7 ANODE VCLAMP 10
5nF

8 CATHODE VEE 9

VCM
Figure 28. CMR Test circuit LED2 off

1 VS VE 16
5V
2 VCC1 VLED 15
2.1kΩ

3 FAULT DESAT 14
15pF
30V
4 VS VCC2 13
SCOPE
0.1µF
5 CATHODE VEE 12
20Ω
6 ANODE VOUT 11
0.1µF
430Ω
7 ANODE VCLAMP 10
5nF

8 CATHODE VEE 9

VCM
Figure 29. CMR Test Circuit LED2 on
16
 1 VS VE 16
5V
2 VCC1 VLED 15
2.1kΩ

3 FAULT DESAT 14
15pF
F
30V
4 VS VCC2 13
0.1µF
µ
5 CATHODE VEE 12 SCOPE
20Ω
6 ANODE VOUT 11
0.1µF
µ
430Ω
7 ANODE VCLAMP 10
5nF

8 CATHODE VEE 9

VCM
Figure 30. CMR Test circuit LED1 off

1 VS VE 16
5V
2 VCC1 VLED 15
2.1kΩ

3 FAULT DESAT 14
15pF
30V
4 VS VCC2 13
0.1µF
5 CATHODE VEE 12 SCOPE
20Ω
6 ANODE VOUT 11
0.1µF
430Ω
7 ANODE VCLAMP 10
5nF

8 CATHODE VEE 9

VCM

Figure 31. CMR Test Circuit LED1 on

17
Application Information 13
VCC2
UVLO
Product Overview Description ANODE
6, 7 D
R
11
The ACPL-331J is a highly integrated power control 5, 8 I
V
VOUT
CATHODE
DESAT
device that incorporates all the necessary components LED1 E
14
R
for a complete, isolated IGBT / MOSFET gate drive circuit DESAT

with fault protection and feedback into one SO-16 9, 12

VEE
SHIELD
package. Active Miller clamp function eliminates the need
of negative gate drive in most application and allows the VCLAMP
2
use of simple bootstrap supply for high side driver. An VCC1
10
VCLAMP
optically isolated power output stage drives IGBTs with 3
LED2
VE
FAULT
power ratings of up to 100 A and 1200 V. A high speed 16

internal optical link minimizes the propagation delays

between the microcontroller and the IGBT while allowing 1, 4 15
VS
the two systems to operate at very large common mode SHIELD VLED

voltage differences that are common in industrial motor

drives and other power switching applications. An output Figure 32. Block Diagram of ACPL-331J
IC provides local protection for the IGBT to prevent
damage during over current, and a second optical link
provides a fully isolated fault status feedback signal for Recommended Application Circuit
the microcontroller. A built in “watchdog” circuit, UVLO The ACPL-331J has an LED input gate control, and an
monitors the power stage supply voltage to prevent IGBT open collector fault output suitable for wired ‘OR’ ap-
caused by insufficient gate drive voltages. This integrated plications. The recommended application circuit shown
IGBT gate driver is designed to increase the performance in Figure 33 illustrates a typical gate drive implementa-
and reliability of a motor drive without the cost, size, and tion using the ACPL-331J. The following describes about
complexity of a discrete design. driving IGBT. However, it is also applicable to MOSFET.
Two light emitting diodes and two integrated circuits Depending upon the MOSFET or IGBT gate threshold re-
housed in the same SO-16 package provide the input quirements, designers may want to adjust the VCC supply
control circuitry, the output power stage, and two optical voltage (Recommended VCC = 17.5V for IGBT and 12.5V
channels. The output Detector IC is designed manufac- for MOSFET).
tured on a high voltage BiCMOS/Power DMOS process. The two supply bypass capacitors (0.1 µF) provide the
The forward optical signal path, as indicated by LED1, large transient currents necessary during a switching
transmits the gate control signal. The return optical signal transition. Because of the transient nature of the charging
path, as indicated by LED2, transmits the fault status currents, a low current (5mA) power supply suffices. The
feedback signal. desaturation diode DDESAT 600V/1200V fast recovery type,
Under normal operation, the LED1 directly controls the trr below 75ns (e.g. ERA34-10) and capacitor CBLANK are
IGBT gate through the isolated output detector IC, and necessary external components for the fault detection
LED2 remains off. When an IGBT fault is detected, the circuitry. The gate resistor RG serves to limit gate charge
output detector IC immediately begins a “soft” shutdown current and controls the IGBT collector voltage rise
sequence, reducing the IGBT current to zero in a con- and fall times. The open collector fault output has a
trolled manner to avoid potential IGBT damage from passive pull-up resistor RF (2.1 kW) and a 330 pF filtering
inductive over voltages. Simultaneously, this fault status capacitor, CF. A 47 kW pull down resistor RPULL-DOWN on
is transmitted back to the input via LED2, where the fault VOUT provides a predictable high level output voltage
latch disables the gate control input and the active low (VOH). In this application, the IGBT gate driver will shut
fault output alerts the microcontroller. down when a fault is detected and fault reset by next
cycle of IGBT turn on. Application notes are mentioned at
During power-up, the Under Voltage Lockout (UVLO) the end of this datasheet.
feature prevents the application of insufficient gate
voltage to the IGBT, by forcing the ACPL-331J’s output
low. Once the output is in the high state, the DESAT (VCE)
detection feature of the ACPL-331J provides IGBT pro-
tection. Thus, UVLO and DESAT work in conjunction to
provide constant IGBT protection.

18
 1 VS VE 16
0.1µF 0.1µF
2 VCC1 VLED 15 CBLANK
0.1µF RF DDESAT
+
_ 3 FAULT DESAT 14
100 Ω

CF
4 VS VCC2 13

5 CATHODE VEE 12
+
_ + HVDC
RG +
6 ANODE VOUT 11 VCE
R Q1 -
3-PHASE
7 ANODE VCLAMP 10 RPULL--DOWN AC
+
_ +
8 CATHODE VEE 9 Q2 VCE
-
- HVDC

Figure 33. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp

Description of Operation
Normal Operation
During normal operation, VOUT of the ACPL-331J is con- Figure 34. Fault Timing diagramactivated is an internal
trolled by input LED current IF (pins 5, 6, 7 and 8), with feedback channel which brings the FAULT output low for
the IGBT collector-to-emitter voltage being monitored the purpose of notifying the micro-controller of the fault
through DDESAT. The FAULT output is high. See Figure 34. condition.

Fault Condition Fault Reset

The DESAT pin monitors the IGBT Vce voltage. When the Once fault is detected, the output will be muted for 5 μs
voltage on the DESAT pin exceeds 6.5 V while the IGBT is (minimum). All input LED signals will be ignored during
on, VOUT is slowly brought low in order to “softly” turn-off the mute period to allow the driver to completely soft
the IGBT and prevent large di/dt induced voltages. Also shut-down the IGBT. The fault mechanism can be reset by
the next LED turn-on after the 5us (minimum) mute time.
See Figure 34.

IF tDESAT(LOW) Reset done

during the
next LED
turn-on
6.5V
VDESAT 50%

tDESAT(10%)

90%
VOUT
10% tRESET(FAULT)
tDESAT(90%)

FAULT 50% 50%

tDESAT(FAULT)
tDESAT(MUTE))
Figure 34. Fault Timing diagram

19
Output Control Slow IGBT Gate Discharge during Fault Condition
The outputs (VOUT and FAULT) of the ACPL-331J are con- When a desaturation fault is detected, a weak pull-down
trolled by the combination of IF, UVLO and a detected device in the ACPL-331J output drive stage will turn on
IGBT Desat condition. Once UVLO is not active (VCC2 - VE > to ‘softly’ turn off the IGBT. This device slowly discharges
VUVLO), VOUT is allowed to go high, and the DESAT (pin 14) the IGBT gate to prevent fast changes in drain current
detection feature of the ACPL-331J will be the primary that could cause damaging voltage spikes due to lead
source of IGBT protection. UVLO is needed to ensure and wire inductance. During the slow turn off, the large
DESAT is functional. Once VUVLO+ > 10.5V, DESAT will output pull-down device remains off until the output
remain functional until VUVLO- < 11.1V. Thus, the DESAT voltage falls below VEE + 2 Volts, at which time the large
detection and UVLO features of the ACPL-331J work in pull down device clamps the IGBT gate to VEE.
conjunction to ensure constant IGBT protection.
DESAT Fault Detection Blanking Time
Desaturation Detection and High Current Protection The DESAT fault detection circuitry must remain disabled
The ACPL-331J satisfies these criteria by combining a for a short time period following the turn-on of the IGBT
high speed, high output current driver, high voltage to allow the collector voltage to fall below the DESAT
optical isolation between the input and output, local IGBT threshold. This time period, called the DESAT blanking
desaturation detection and shut down, and an optically time is controlled by the internal DESAT charge current,
isolated fault status feedback signal into a single 16-pin the DESAT voltage threshold, and the external DESAT
surface mount package. capacitor.
The fault detection method, which is adopted in the The nominal blanking time is calculated in terms of
ACPL-331J is to monitor the saturation (collector) external capacitance (CBLANK), FAULT threshold voltage
voltage of the IGBT and to trigger a local fault shutdown (VDESAT ), and DESAT charge current (ICHG) as tBLANK =
sequence if the collector voltage exceeds a predeter- CBLANK x VDESAT / ICHG. The nominal blanking time with
mined threshold. A small gate discharge device slowly the recommended 100pF capacitor is 100pF * 6.5 V / 240
reduces the high short circuit IGBT current to prevent µA = 2.7 µsec.
damaging voltage spikes. Before the dissipated energy
The capacitance value can be scaled slightly to adjust the
can reach destructive levels, the IGBT is shut off. During
blanking time, though a value smaller than 100 pF is not
the off state of the IGBT, the fault detect circuitry is simply
recommended. This nominal blanking time represents
disabled to prevent false ‘fault’ signals.
the longest time it will take for the ACPL-331J to respond
The alternative protection scheme of measuring IGBT to a DESAT fault condition. If the IGBT is turned on while
current to prevent desaturation is effective if the short the collector and emitter are shorted to the supply rails
circuit capability of the power device is known, but (switching into a short), the soft shut-down sequence
this method will fail if the gate drive voltage decreases will begin after approximately 3 µsec. If the IGBT collector
enough to only partially turn on the IGBT. By directly and emitter are shorted to the supply rails after the IGBT
measuring the collector voltage, the ACPL-331J limits is already on, the response time will be much quicker due
the power dissipation in the IGBT even with insufficient to the parasitic parallel capacitance of the DESAT diode.
gate drive voltage. Another more subtle advantage of the The recommended 100pF capacitor should provide
desaturation detection method is that power dissipation adequate blanking as well as fault response times for
in the IGBT is monitored, while the current sense method most applications.
relies on a preset current threshold to predict the safe
limit of operation. Therefore, an overly conservative over
current threshold is not needed to protect the IGBT.

IF UVLO (VCC2 – VE) Desat Condition Detected on Pin 14 Pin 3 (FAULT) Output VOUT
X Active X X Low
X X Yes Low Low
OFF X X X Low
ON Not Active No High High

20
Under Voltage Lockout
1 VS VE 16
The ACPL-331J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate 2 VCC1 VLED 15

voltage to the IGBT by forcing the ACPL-331J output

3 FAULT DESAT 14 VCC
low during power-up. IGBTs typically require gate
voltages of 15 V to achieve their rated VCE(ON) voltage. 4 VS VCC2 13
At gate voltages below 13 V typically, the VCE(ON) voltage
increases dramatically, especially at higher currents. At 5 CATHODE VEE 12
very low gate voltages (below 10 V), the IGBT may operate RG
in the linear region and quickly overheat. The UVLO 6 ANODE VOUT 11

function causes the output to be clamped whenever in-

7 ANODE VCLAMP 10 RPULL-DOWN
sufficient operating supply (VCC2) is applied. Once VCC2
exceeds VUVLO+ (the positive-going UVLO threshold), the 8 CATHODE VEE 9
UVLO clamp is released to allow the device output to turn
on in response to input signals. As VCC2 is increased from
0 V (at some level below VUVLO+), first the DESAT protec-
tion circuitry becomes active. As VCC2 is further increased Figure 35. Output pull-down resistor.
(above VUVLO+), the UVLO clamp is released. Before the
time the UVLO clamp is released, the DESAT protection DESAT Pin Protection Resistor
is already active. Therefore, the UVLO and DESAT Fault The freewheeling of flyback diodes connected across
detection feature work together to provide seamless pro- the IGBTs can have large instantaneous forward voltage
tection regardless of supply voltage (VCC2). transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
Active Miller Clamp voltage spike on the DESAT pin which will draw substan-
A Miller clamp allows the control of the Miller current tial current out of the driver if protection is not used. To
during a high dV/dt situation and can eliminate the use limit this current to levels that will not damage the driver
of a negative supply voltage in most of the applications. IC, a 100 ohm resistor should be inserted in series with
During turn-off, the gate voltage is monitored and the the DESAT diode. The added resistance will not alter the
clamp output is activated when gate voltage goes below DESAT threshold or the DESAT blanking time.
2V (relative to VEE). The clamp voltage is VOL+2.5V typ
1 VS VE 16
for a Miller current up to 1100mA. The clamp is disabled
when the LED input is triggered again.
2 VCC1 VLED 15 100pF
DDESAT
Other Recommended Components 3 FAULT DESAT 14
100 Ω

VCC
The application circuit in Figure 33 includes an output
4 VS VCC2 13
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor, and a FAULT pin pullup resistor and 5 CATHODE VEE 12
Active Miller Clamp connection. RG
6 ANODE VOUT 11
Output Pull-Down Resistor
7 ANODE VCLAMP 10
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of VCC2. If the output 8 CATHODE VEE 9
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly VCC2-3(VBE)
to VCC2 within a period of several microseconds. To limit
Figure 36. DESAT pin protection.
the output voltage to VCC2-3(VBE), a pull-down resistor,
RPULL-DOWN between the output and VEE is recommended
to sink a static current of several 650 µA while the output
is high. Pull-down resistor values are dependent on the
amount of positive supply and can be adjusted according
to the formula, Rpull-down = [VCC2-3 * (VBE)] / 650 µA.

21
Capacitor on FAULT Pin for High CMR Pull-up Resistor on FAULT Pin
Rapid common mode transients can affect the fault pin The FAULT pin is an open collector output and therefore
voltage while the fault output is in the high state. A 330 requires a pull-up resistor to provide a high-level signal.
pF capacitor should be connected between the fault pin Also the FAULT output can be wire ‘OR’ed together with
and ground to achieve adequate CMOS noise margins at other types of protection (e.g. over-temperature, over-
the specified CMR value of 15 kV/µs. The added capaci- voltage, over-current ) to alert the microcontroller.
tance does not increase the fault output delay when a
desaturation condition is detected.

Other Possible Application Circuit (Output Stage)

1 VS VE 16
0.1µF 0.1µF
2 VCC1 VLED 15

3 FAULT DESAT 14

4 VS VCC2 13
0.1µF Optional R2
5 CATHODE VEE 12
+_ + HVDC
Optional R1 RG +
6 ANODE VOUT 11 VCE
Q1 -
3-PHASE
7 ANODE VCLAMP 10
AC
RPULL-DOWN +_
+
8 CATHODE VEE 9
* Q2 VCE
-
- HVDC

Figure 37. IGBT drive with negative gate drive, external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used) VCLAMP is
used as secondary gate discharge path. * indicates component required for negative gate drive topology

1 VS VE 16
0.1µF 0.1µF
2 VCC1 VLED 15

3 FAULT DESAT 14

4 VS VCC2 13
0.1µF Optional R2
5 CATHODE VEE 12
+_ + HVDC
Optional R1 RG +
6 ANODE VOUT 11 VCE
Q1 -
3-PHASE
7 ANODE VCLAMP 10
AC
RPULL-DOWN +_
+
* VCE
8 CATHODE VEE 9 Q2
-
- HVDC
R3

Figure 38. Large IGBT drive with negative gate drive, external booster. VCLAMP control secondary discharge path for higher power application.

22
Related Application Notes
AN5314 – Active Miller Clamp (Year 2007)
AN5315 – “Soft” Turn-off Feature (Year 2007)
AN1087 – Thermal Data for Optocouplers
AN1043 – Common-Mode Noise : Sources and Solutions

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Data subject to change. Copyright © 2005-2008 Avago Technologies Limited. All rights reserved.
AV02-0119EN - April 24, 2008