CEP02N65D/CEB02N65D

CEF02N65D
PRELIMINARY
N-Channel Enhancement Mode Field Effect Transistor

FEATURES
Type VDSS RDS(ON) ID @VGS
CEP02N65D 650V 6.9Ω 2A 10V
CEB02N65D 650V 6.9Ω 2A 10V
CEF02N65D 650V 6.9Ω 2A d 10V

Super high dense cell design for extremely low RDS(ON). D

High power and current handing capability.

Lead free product is acquired.

D G

G G
G D D
S S S S
CEB SERIES CEP SERIES CEF SERIES
TO-263(DD-PAK) TO-220 TO-220F

ABSOLUTE MAXIMUM RATINGS Tc = 25 C unless otherwise noted

Limit
Parameter Symbol Units
TO-220/263 TO-220F
Drain-Source Voltage VDS 650 V
Gate-Source Voltage VGS ±30 V
Drain Current-Continuous ID 2 2 d
A
Drain Current-Pulsed a
IDM e
8 8 d
A
Maximum Power Dissipation @ TC = 25 C 41 27 W
PD
- Derate above 25 C 0.33 0.22 W/ C
Operating and Store Temperature Range TJ,Tstg -55 to 150 C

Thermal Characteristics
Parameter Symbol Limit Units
Thermal Resistance, Junction-to-Case RθJC 3 4.5 C/W
Thermal Resistance, Junction-to-Ambient RθJA 62.5 65 C/W

This is preliminary information on a new product in development now . Rev 1. [Link]

Details are subject to change without notice . [Link]
1
 CEP02N65D/CEB02N65D
CEF02N65D
Electrical Characteristics Tc = 25 C unless otherwise noted

Parameter Symbol Test Condition Min Typ Max Units 4

Off Characteristics
Drain-Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA 650 V
Zero Gate Voltage Drain Current IDSS VDS = 650V, VGS = 0V 1 µA
Gate Body Leakage Current, Forward IGSSF VGS = 30V, VDS = 0V 100 nA
Gate Body Leakage Current, Reverse IGSSR VGS = -30V, VDS = 0V -100 nA
On Characteristics b
Gate Threshold Voltage VGS(th) VGS = VDS, ID = 250µA 2.5 4.5 V
Static Drain-Source
RDS(on) VGS = 10V, ID = 0.8A 5.6 6.9 Ω
On-Resistance
Forward Transconductance gFS VDS = 10V, ID = 0.6A 0.8 S
Dynamic Characteristics c

Input Capacitance Ciss 270 pF

VDS = 25V, VGS = 0V,
Output Capacitance Coss f = 1.0 MHz 55 pF
Reverse Transfer Capacitance Crss 25 pF
Switching Characteristics c
Turn-On Delay Time td(on) 11 14.3 ns
Turn-On Rise Time tr VDD = 300V, ID = 1.3A, 10 13 ns
VGS = 10V, RGEN =4.7Ω
Turn-Off Delay Time td(off) 27 35.1 ns
Turn-Off Fall Time tf 7.5 9.75 ns
Total Gate Charge Qg 15.5 20.1 nC
VDS = 480V, ID = 1.3A,
Gate-Source Charge Qgs VGS = 10V 1 nC
Gate-Drain Charge Qgd 10 nC
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current IS f 1.3 A
Drain-Source Diode Forward Voltage b
VSD VGS = 0V, IS = 0.6A g 1.5 V
Notes :
[Link] Rating : Pulse width limited by maximum junction temperature .
[Link] Test : Pulse Width < 300µs, Duty Cycle < 2% .
[Link] by design, not subject to production testing.
[Link] only by maximum temperature allowed .
[Link] width limited by safe operating area .
.

2
 CEP02N65D/CEB02N65D
CEF02N65D
1.5 0.5
VGS=10,9,8V 25 C

1.2 0.4
ID, Drain Current (A)

ID, Drain Current (A)

VGS=6V
0.9 0.3

0.6 0.2

0.3 0.1
VGS=5V TJ=125 C -55 C

0.0 0.0
0 5 10 15 20 25 1 2 3 4 5 6 7

VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V)

Figure 1. Output Characteristics Figure 2. Transfer Characteristics

300 3.0
Ciss ID=0.8A
RDS(ON), On-Resistance(Ohms)

VGS=10V
250 2.5
C, Capacitance (pF)

RDS(ON), Normalized

200 2.0

150 1.5

100 1.0
Coss
50 Crss 0.5

0 0.0
0 5 10 15 20 25 -100 -50 0 50 100 150 200

VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature( C)

Figure 3. Capacitance Figure 4. On-Resistance Variation

with Temperature
1.3
VDS=VGS VGS=0V
Gate-Source Threshold Voltage

ID=250µA
IS, Source-drain current (A)

1.2
0
1.1 10
VTH, Normalized

1.0

0.9
-1
10
0.8

0.7

-2
0.6 10
-50 -25 0 25 50 75 100 125 150 0.2 0.6 1.0 1.4 1.8 2.2

TJ, Junction Temperature( C) VSD, Body Diode Forward Voltage (V)

Figure 5. Gate Threshold Variation Figure 6. Body Diode Forward Voltage

with Temperature Variation with Source Current

3
 CEP02N65D/CEB02N65D
CEF02N65D
1
10 10
VDS=480V
VGS, Gate to Source Voltage (V)

8
ID=1.3A RDS(ON)Limit
4

ID, Drain Current (A)

0
10
1ms
6 10ms
-1 100ms
10 1s
4 DC
-2
2 10
TA=25 C
TJ=150 C
Single Pulse
0 -3
10
0 3 6 9 12 15 18 10
0
10
1
10
2
10
3

Qg, Total Gate Charge (nC) VDS, Drain-Source Voltage (V)

Figure 7. Gate Charge Figure 8. Maximum Safe

Operating Area

VDD
t on toff
RL td(on) tr td(off) tf
V IN 90%
90%
D VOUT
VGS VOUT 10% INVERTED 10%
RGEN G
90%
50% 50%
S VIN
10%

PULSE WIDTH

Figure 9. Switching Test Circuit Figure 10. Switching Waveforms

Transient Thermal Impedance

0
10
r(t),Normalized Effective

D=0.5

0.2

-1 0.1 PDM
10
0.05 t1
0.02 t2
0.01 1. RθJC (t)=r (t) * RθJC
Single Pulse 2. RθJC=See Datasheet
3. TJM-TC = P* RθJC (t)
-2
4. Duty Cycle, D=t1/t2
10
-2 -1 0 1 2 3 4
10 10 10 10 10 10 10

Square Wave Pulse Duration (msec)

Figure 11. Normalized Thermal Transient Impedance Curve