Synthesizable Verilog Coding

for RTL design

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Let’s start from RTL design
What is RTL design
 RTL: Register Transfer Level (Language)
 a standard method to design any digital IC
 Feature:
 designer specify rules to transfer data from one register to another
register
 EDA (electronic design automation) tool synthesis RTL code to
real hardware B C

Verilog code
+
reg [3:0] A, B, C;

always @(posedge clk) begin

clk register
A <= B+C;
end
A
 Goal of this lecture
 let you do RTL design using Verilog

 Step 1: always starts from the

general framework
 control signals: the order sent from
control unit
 status signals: reports from data
path
 Step 2: specify the behavior of
each part
 control unit: state-diagram
 data path: micro-operation
 Step 3: design circuits from
behavior specification
 control unit: state-diagram to K: A=B+C
circuit (Chapter 5)
by EDA tool (if (K==1) then A=B+C;)
 data path: micro-operation to
circuit (Sec. 7.3 – 7.6)
How to make a (digital) chip
VLSI Design Flow in SoC Era
application algorithm

video motion
DCT
frames estimation

entropy
Q
cod ing ESL design
(Electronic System Level)
RTL design
(Register Transfer Level)

gate-level design

circuit-level design
(transistor-level)

physical layout
 The basic device to build a chip:
MOS transistor

ESL design
(Electronic System Level)
RTL design
(Register Transfer Level)

gate-level design

circuit-level design D
(transistor-level)
G
physical layout X X=0 X=1

S
 Physical Layout

ESL design
(Electronic System Level)
RTL design
(Register Transfer Level)

gate-level design

circuit-level design
(transistor-level)

physical layout
Physical layout of a chip
 The image you find
in fully-custom
design
 Gate-level to Circuit-level
Transform

ESL design
(Electronic System Level)
RTL design
(Register Transfer Level)

gate-level design

circuit-level design
(transistor-level)

physical layout
 RTL to Gate-level transform
reg A, B, C, D, E;
ESL design
(Electronic System Level) always @(*)
RTL design E = A&B | C&D;
(Register Transfer Level)

gate-level design

circuit-level design
(transistor-level)

physical layout
State-of-art chip design

always @(posedge clk)

A <= B+C;

RTL design
(Register Transfer Level)

gate-level design

circuit-level design automatically

(transistor-level) processed by EDA
tools
physical layout
Still some comments before we
begin
Common error of beginners
 non-synthesizable coding style
 a wrong code may result in correct simulation
wave-form/FPGA outcome

 synthesizable but without concrete imagine

on hardware generated
 long path delay
 extremely large chip area
Correct method of doing RTL
coding
 Step 1: draw the block diagram of your hardware
 be aware of combinational and sequential circuit
 Step 2: translate each block into Verilog/VHDL
code
 follow fixed coding style

 always have a hardware block diagram in your

minds!
Suggestion to beginners
 do “synthesis” for each small piece of your
code
 synthesis means: translate a higher level design
to a lower level design (e.g. RTL=> gate-level)

 use “Tools->Net List Viewer -> RTL view”

of Quartus II
Now we begin to talk about
Verilog coding
 Verilog coding
 structural description
 describe the hardware directly

 behavior description input A [3:0];

input B [3:0];
 the “register transfer” rules input clock;
reg S [3:0];
 most of beginners error
always @(posedge clock)
S <= #1 A+B;
Structural description (1)

describing a hardware with block

diagram in minds
What is structural description
 describing a hardware with detailed block diagram
in minds
A “module”
 the basic unit for Verilog hardware design is a
“module”
 the hardware you designed is a module
 you may have sub-modules in your design
 structural description to describe the hardware
architecture of a module:
 Step 1: module declaration with input/output
specifications
 Step 2: instance sub-modules
 Step 3: declare wires and make connections
Example of structural description
Example of structural description

module declaration

the module you designed

Example of structural description
input/output specification
Example of structural description
Example of structural description
A “module”
 the basic unit for Verilog hardware design is a
“module”
 the hardware you designed is a module
 you may have sub-modules in your design
 structural description to describe the hardware
architecture of a module:
 Step 1: module declaration with input/output
specifications
 Step 2: instance sub-modules
 Step 3: declare wires and make connections
Instance Sub-Modules
Instance Sub-Modules

type of this sub-module

Instance Sub-Modules

name of this block

(you can give any name as you want)
A sub-module with detailed
design
A “module”
 the basic unit for Verilog hardware design is a
“module”
 the hardware you designed is a module
 you may have sub-modules in your design
 structural description to describe the hardware
architecture of a module:
 Step 1: module declaration with input/output
specifications
 Step 2: instance sub-modules
 Step 3: declare wires and make connections
Declare wires
Connecting ports of modules
 Lab Exercise
A
 Write a Verilog module for 8 8
this accumulator circuit
in1 in0
 provided that the following 0 adder
sub-modules are given
 adder
 MUX S MUX
 register with load enable 8
D
L Load
Register R
Q
8
Caution
 always use “wire” to declare signals in
structural description

 no “always @(…)” in structural description

Structural Description (2)

describe the hardware with

Boolean/arithmetic equations
The “assign” statement
 the “assign” a wire as driven by some combinational
circuit
 Example 1: the Boolean equation
 Example 2: the arithmetic equation
 Example 3: the multiplexer (MUX)
The “assign” statement
 the “assign” a wire as driven by some combinational circuit
 Example 1: the Boolean equation
 Example 2: the arithmetic equation
 Example 3: the multiplexer (MUX)

module my_circuit (A, B, C, E);

input A;
input B;
input C;
output E;
E
wire D;

assign D = A&B;
assign E = C | D;
endmodule the same operators to C/C++
The “assign” statement
 the “assign” a wire as driven by some combinational circuit
 Example 1: the Boolean equation
 Example 2: the arithmetic equation
 Example 3: the multiplexer (MUX)

module my_circuit (A, B, C, E);

input A;
input B;
input C;
output E;
E
assign E = (A&B)|C;
endmodule
you may write a longer equation
 The “assign” statement
 the “assign” a wire as driven by some combinational circuit
 Example 1: the Boolean equation
 Example 2: the arithmetic equation
 Example 3: the multiplexer (MUX)

A module my_circuit (A, B, C);

B
input [7:0] A;
8 8 input [7:0] B;
output [7:0] C;
adder
assign C = A+B;
8 endmodule
arithmetic equation in C
C
 The “assign” statement
 the “assign” a wire as driven by some combinational circuit
 Example 1: the Boolean equation
 Example 2: the arithmetic equation
 Example 3: the multiplexer (MUX)
C A B
8 8 module my_circuit (A, B, C, E);
input [7:0] A;
8 input [7:0] B;
adder input [7:0] C;
output [7:0] E;
8 D
wire [7:0] D;
adder
assign D = A+B;
8 assign E = C+D;
endmodule
E
 The “assign” statement
 the “assign” a wire as driven by some combinational circuit
 Example 1: the Boolean equation
 Example 2: the arithmetic equation
 Example 3: the multiplexer (MUX)
C A B
8 8 module my_circuit (A, B, C, E);
input [7:0] A;
8 input [7:0] B;
adder input [7:0] C;
output [7:0] E;
8 D
wire [7:0] D;
adder
assign E = C+D;
8 assign D = A+B;
endmodule re-order yields the same result
E
 The “assign” statement
 the “assign” a wire as driven by some combinational circuit
 Example 1: the Boolean equation
 Example 2: the arithmetic equation
 Example 3: the multiplexer (MUX)
C A B
8 8
module my_circuit (A, B, C, E);
8 input [7:0] A;
adder
input [7:0] B;
D input [7:0] C;
8
output [7:0] E;

adder assign E = A+B+C;

endmodule
8

E
 The “assign” statement
 the “assign” a wire as driven by some combinational circuit
 Example 1: the Boolean equation
 Example 2: the arithmetic equation
 Example 3: the multiplexer (MUX)

A B module MUX (A, B, S, C);

input [7:0] A;
8 8
input [7:0] B;
input S;
S MUX
output [7:0] C;
8
assign C = (S)? A: B;
C
endmodule C-style expression
Rule of thumb to use “assign”
 describe a combinational circuit with
Boolean or arithmetic equations
 an equation from inputs to outputs
 the same operators/expressions to C/C++
A B C
…

combinational D = f ( A, B, C ,...)
circuit

D
Lab Exercise
 Design the circuit with “assign” statements
 write the Boolean equations
Behavior description
General Semantics of Behavior
Description
 specify the rules for event-driven simulation
 Remark: Verilog is originally for hardware simulation, not
for hardware synthesis

reg D, E; //declare variables but

A B C //not necessary synthesis registers

always @(event_list) begin

hardware to be
simulated …
// C code to compute D and E from A, B, C
…
D E
end
Inferring combinational circuit
with behavior description
Inferring combinational circuit
 general coding style:
 always @(all signal list)
 always @(*)
 use blocking assignment “=“
 do not use “<= “
 you have to enumerate all cases to determine
the output value
 Example: a combinational circuit
 semantics from event-driven simulation
time

module demo_circuit (A, B, C, E); clock

input A, B, C;
output E;
A 0 1
reg E;
B 1
always @(A or B or C) begin
E = (A&B)|C;
C 0
end
endmodule
E 0 1
 Example: a combinational circuit
 semantics from event-driven simulation
time

module demo_circuit (A, B, C, E); clock

input A, B, C;
output E; events to trigger A
0 1
the simulation
reg E;
B 1
always @(A or B or C) begin
E = (A&B)|C;
C 0
end
endmodule
E 0 1
 Example: a combinational circuit
 semantics from event-driven simulation
time

module demo_circuit (A, B, C, E); clock

input A, B, C;
output E;
A 0 1
reg E;
B 1
always @(A or B or C) begin
E = (A&B)|C;
C 0
end
endmodule
C-like statements to
simulate E 0 1
 Example: a combinational circuit
 semantics from event-driven simulation
time
signal change causes
the simulation
module demo_circuit (A, B, C, E); clock
input A, B, C;
output E;
A 0 1
reg E;
B 1
always @(A or B or C) begin the simulated output value
E = (A&B)|C;
C 0
end
endmodule
E 0 1
 Example: a combinational circuit
 semantics from event-driven simulation
time

module demo_circuit (A, B, C, E); clock

input A, B, C;
output E;
A 0 1
reg E;
B 1
always @(A or B or C) begin
E = (A&B)|C;
C 0
end
endmodule
E 0 1

signal change not waiting for a clock

 Example: a combinational circuit
 the synthesized circuit

module demo_circuit (A, B, C, E);

input A, B, C;
output E;

reg E; E
always @(A or B or C) begin
E = (A&B)|C;
end
endmodule
 Example: a combinational circuit
 the synthesized circuit

declared
module demo_circuit (A,asB,a C,
register
E); but
input A, B, not
C; register synthesized
output E;

reg E; E
always @(A or B or C) begin
E = (A&B)|C;
end
endmodule
More Examples of inferring
combinational circuits
(1) design by specifying the Boolean
equations
(2) design by specifying the truth table
(3) inferring a data path with case
statement
(4) inferring a data path with if-then-else
Example 1 (a)
 design by specifying Boolean equations

module demo_circuit (A, B, C, E);

input A, B, C;
output E;

reg E;
E
always @(A or B or C) begin
E = (A&B)|C;
end
endmodule
Example 1 (b)
 design by specifying Boolean equations

module demo_circuit (A, B, C, E);

input A, B, C; simulation triggered by any
output E; change on input signals
reg E;
E
always @(*) begin
E = (A&B)|C;
end
endmodule
Example 1 (c)
 design by specifying Boolean equations
module demo_circuit (A, B, C, E);
input A, B, C;
output E;

reg D;
reg E;
E
always @(*) begin
D = A&B;
end

always @(*) begin

E = D|C;
end
endmodule
Example 1 (d)
 design by specifying Boolean equations
module demo_circuit (A, B, C, E);
input A, B, C;
output E;

reg D;
reg E;
E
always @(*) begin
E = D|C;
end
exchange yields the same result
always @(*) begin
D = A&B;
end
endmodule
More Examples of inferring
combinational circuits
(1) design by specifying the Boolean
equations
(2) design by specifying the truth table
(3) inferring a data path with case
statement
(4) inferring a data path with if-then-else
 Example 2 module demo_circuit (A, B, C, E);
input A, B, C;
output E;
 inferring combinational circuit
by specifying the truth table reg E;

always @(*) begin

case ({A, B, C})
3’b000: E = 1’b0;
3’b001: E = 1’b1;
3’b010: E = 1’b0;
3’b011: E = 1’b1;
3’b100: E = 1’b0;
E 3’b101: E = 1’b1;
3’b110: E = 1’b1;
3’b111: E = 1’b1;
endcase
end
endmodule
 Example 2 module demo_circuit (A, B, C, E);
input A, B, C;
output E;
 inferring combinational circuit
by specifying the truth table reg E;

always @(*) begin the truth table

case ({A, B, C})
3’b000: E = 1’b0;
3’b001: E = 1’b1;
3’b010: E = 1’b0;
3’b011: E = 1’b1;
3’b100: E = 1’b0;
E 3’b101: E = 1’b1;
3’b110: E = 1’b1;
3’b111: E = 1’b1;
endcase
end
endmodule
Constant Representation
 binary number:
 [width]’bnumber
 Example 1: ‘b101
 Example 2: 3’b101
 hexdecimal number
 [width]’hnumber
 Example 1: ‘h09a2
 Example 2: 16’h09a2
 decimal:
 Example: 1234
 Example: ‘d1234
 Example: 32’d1234
 Example 2 module demo_circuit (A, B, C, E);
input A, B, C;
output E;
 inferring combinational circuit
by specifying the truth table reg E;

always @(*) begin

case ({A, B, C})
3’b000: E = 1’b0;
E = 1 if {A,B,C}==001 3’b001: E = 1’b1;
3’b010: E = 1’b0;
3’b011: E = 1’b1;
3’b100: E = 1’b0;
E 3’b101: E = 1’b1;
3’b110: E = 1’b1;
3’b111: E = 1’b1;
endcase
end
endmodule
More Examples of inferring
combinational circuits
(1) design by specifying the Boolean
equations
(2) design by specifying the truth table
(3) inferring a data path with case
statement
(4) inferring a data path with if-then-else
Example: combinational circuit
Example: combinational circuit

register is not a register!

Example: combinational circuit

C-like code to compute output from inputs

Example: combinational circuit

specify a don’t-care
More Examples of inferring
combinational circuits
(1) design by specifying the Boolean
equations
(2) design by specifying the truth table
(3) inferring a data path with case
statement
(4) inferring a data path with if-then-else
Example: combinational circuit

if-then-else rules also work!

Example: combinational circuit

This line is necessary to enforce

a combinational circuit
Example: combinational circuit

Verilog 2001 standard:

depends on all input signals
Inferring sequential circuit with
behavior description
 The general scheme
 for sequential circuit
 only simulate when clock triggered

A B C
always @(posedge clk) begin

hardware to be …
clk simulated // C code to compute D and E
…

end
D E
Inferring sequential circuit
 coding style:
 always @(posedge clk)
 use non-blocking assignment “<=“
Example 1:
 parallel D-FFs triggered by clock
time

rin 1010 0110

acc_reg
1010 0110

rin acc_reg

clock
Example 1
 parallel D-FFs triggered by clock
time

rin 1010 0110

acc_reg
1010 0110

simulation triggered by clock

rin acc_reg

clock
 Example 1
 parallel D-FFs triggered by clock
time

rin 1010 0110

acc_reg
1010 0110

Caution: You have to use non-blocking assignment rin acc_reg

to generate registers!

clock
Example 2: sequential circuit
 with combinational circuit for computation
Example 3: realizing finite-state
machine
 realize the finite-state machine with
behavior description reg S;
always @(posedge clock) begin
case (S)
1’b0:
X=0 T=1 begin
if (X==0)
X=1
S <= 1’b0;
0 1 else
T=0 S <= 1’b1;
end

1’b1: S <= (T)? 1’b1: 1’b0;

endcase
end
 I believe that most of you are confused with
 combinational circuit vs.
 sequential circuit
Example: the adder

combinational vs. sequential circuit

What’s the difference?
reg [3:0] A, B, C; reg [3:0] A, B, C;

always @(*) begin always @(posedge clk) begin

A = B+C; A <= B+C;
end end
What’s the difference?
reg [3:0] A, B, C; reg [3:0] A, B, C;

always @(*) begin always @(posedge clk) begin

A = B+C; A <= B+C;
end end

B C
B C

+
+

clk register
A

A
 What’s the difference?
reg [3:0] A, B, C; reg [3:0] A, B, C;

always @(*) begin always @(posedge clk) begin

A = B+C; A <= B+C;
end end

clk clk

B 10 1 5 B 10 1 5

5 2 7 C 5 2 7
C

A 15 3 12 A 15 3 12
Caution on behavior description
 Be aware of which part is combinational
circuit and which part is sequential circuit

 use fixed coding style for

 combinational circuit
 sequential circuit

 Do not try other coding styles!

Rule of thumb
 declaration on “variables”
 structural description: wire
 behavior description: reg
Rule of thumb for behavior
description
 for combinational circuit:
 always @(all signals used)
 always @(*)
 use “=“ (blocking assignment)
 for sequential circuit
 always @(posedge clock)
 use “<=“ (non-blocking assignment)