uP6103

5V/12V Synchronous-Rectified
Buck Controller with Reference Input
General Description Features
The uP6103 is a compact synchronous-rectified buck † Operate from 5V or 12V Supply Voltage
controller specifically designed to operate from 5V or 12V † 3.3V to 12V VIN Input Range
supply voltage and to deliver high quality output voltage as
† 0.6 VREF with 1.5% Accuracy
low as 0.4V. These SOP-8 and PSOP-8 devices operate at
fixed 200/300 kHz frequency and provide an optimal level † Output Range from VREF to 80% of VIN
of integration to reduce size and cost of the power supply. † Support Tracking Mode and Stand Alone Mode
The uP6103 supports both tracking mode and stand-alone Operation
mode operation. The output voltage is tightly regulated to † Simple Single-Loop Control Design
the external reference voltage from 0.4V to 3.0V at tracking † Voltage-Mode PWM Control
mode or to internal 0.6V reference at stand-alone mode.
† Fast Transient Response
This controller integrates internal MOSFET drivers that
† High-Bandwidth Error Amplifier
support 12V+12V bootstrapped voltage for high efficiency
power conversion. The bootstrap diode is built-in to simplify † 0% to 80% Duty Cycle
the circuit design and minimize external part count. † Lossless, Programmable Overcurrent Protection
Other features include internal softstart, undervoltage † Uses Lower MOSFET RDS(ON)
protection, overcurrent protection and shutdown function. † 200/300 kHz Fixed Frequency Oscillator
With aforementioned functions, this part provides
† Internal Soft Start
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part is available in SOP-8 and † Integrated Bootstrap Diode
PSOP-8 packages. † RoHS Compliant and Halogen Free

Ordering Information Applications

† Power Supplies for Microprocessors or
Order Number P a cka g e Top Marking Remark Subsystem Power Supplies
uP6103S8 SOP-8L uP6103S8 200kHz † Cable Modems, Set Top Boxes, and xDSL
uP6103AS8 SOP-8L uP6103AS8 300kHz Modems
uP6103ASU8 PSOP-8L uP6103ASU8 300kHz † Industrial Power Supplies; General Purpose
Supplies
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 requirements. They are halogen-free, † 5V or 12V Input DC-DC Regulators
RoHS compliant and 100% matte tin (Sn) plating that are † Low Voltage Distributed Power Supplies
suitable for use in SnPb or Pb-free soldering processes.

Pin Configuration & Typical Application Circuit

VIN

BOOT 1 8 PHASE VCC

5
UGATE 2 7 REFIN Reference REFIN BOOT
7 1
Input
GND 3 6 FB
Disable

LGATE 4 5 VCC UGATE

uP6103

Enable 2

SOP-8 PHASE VOUT

8

FB LGATE
BOOT 1 8 PHASE 6 4

UGATE 2 7 REFIN 3
GND GND
GND 3 6 FB
Option
LGATE 4 5 VCC

PSOP-8

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Functional Pin Description
N o. Pin Name Pin Function
B ootstrap Supply for the floati ng upper gate dri ver. C onnect the bootstrap capaci tor C BOOT
between BOOT pi n and the PHASE pi n to form a bootstrap ci rcui t. The bootstrap capaci tor
1 BOOT
provides the charge to turn on the upper MOSFET. Typical values for CBOOT range from 0.1uF to
0.47uF. Ensure that CBOOT is placed near the IC.
Upper Gate Driver Output. Connect this pin to the gate of upper MOSFET. This pin is monitored
2 UGATE by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has
turned off.
Signal and Pow er Ground for the IC. All voltages levels are measured with respect to this pin.
3 GND
Tie this pin to the ground island/plane through the lowest impedance connection available.
Low er Gate Driver Output. Connect this pin to the gate of lower MOSFET. This pin is monitored
4 LGATE by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turn
off.
Supply Voltage. This pin provides the bias supply for the uP6103 and the lower gate driver. The
supply voltage is internally regulated to 4VDD for internal control circuit. Connect a well-decoupled
5 VC C
4.5V to 13.2V supply voltage to this pin. Ensure that a decoupling capacitor is placed near the
IC.
Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from
6 FB the output to GND is used to set the regulation voltage. Use this pin in combination with the
COMP/EN pin to compensate the voltage control feedback loop of the converter.
External R eference Input for Tracking Mode Operation. Thi s pi n recei ves a voltage wi th
range from 0.4V to 3.0V as the reference voltage at the non-inverting input of the error amplifier.
7 REFIN
Pulli ng thi s pi n lower than 0.3V di sables the controller and causes the osci llator to stop, the
UGATE and LGATE outputs to be held low. Let this pin open for internal 0.6V reference use.
PHASE Sw itch Node. Connect this pin to the source of the upper MOSFET and the drain of
the lower MOSFET. This pin is used as the sink for the UGATE driver, and to monitor the voltage
drop across the lower MOSFET for over current protection. This pin is also monitored by the
8 PHASE
adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off.
A Schottky diode between this pin and ground is recommended to reduce negative transient
voltage which is common in a power supply system.
For PSOP-8 package. The exposed pad should be well soldered to PC B for effecti ve heat
Exposed Pad
conduction. Connect the exposed pad the ground.

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Functional Block Diagram
VCC
5

Internal
1 BOOT
4VDD Regulator

2 UGATE
VOCP
Soft
POR
Start OCP
SS Comparator

FB 6 PWM
Error Gate
Amplifier Control 8 PHASE
VREF
Logic
Reference VCC
Selection

Oscillator 4 LGATE
0.6V

REFIN 7 Enable
0.3V

3
GND

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Functional Description
The uP6103 is a compact synchronous-rectified buck the 100uA current source. As the REFIN voltage acrosses
controller specifically designed to operate from 5V or 12V 0.3V threshold level, the Enable Comparator initiates the
supply voltage and to deliver high quality output voltage as operation of the uP6103. The REFIN voltage is compared
low as 0.4V. These SOP-8 and PSOP-8 devices operate at with 3.0V voltage to select the reference voltage with 1ms
fixed 200/300 kHz frequency and provide an optimal level time delay after chip enabling. The internal 0.6V reference
of integration to reduce size and cost of the power supply. voltage is selected as the REFIN pulled high to internal
3.3VDD. The softstart cycle is initiated after reference
The uP6103 supports both tracking mode and stand-alone
selection is completed.
mode operation. The output voltage is tightly regulated to
the external reference voltage from 0.4V to 3.0V at tracking To Select External Reference Voltage, connect REFIN
mode or to internal 0.6V reference at stand-alone mode. to a voltage source range from 0.4V to 3V. As Q1 is turn
off, the REFIN voltage is aligned to the external reference
Supply Voltage
input. As the REFIN voltage acrosses 0.3V threshold level,
The VCC pin receives a well-decoupled 4.5V to 13.2V the Enable Comparator initiates the operation of the
supply voltage to power the uP6103 control circuit, the uP6103. The REFIN voltage is compared with 3.0V voltage
lower gate driver and the bootstrap circuit for the higher to select the reference voltage with 1ms time delay after
gate driver. A minimum 0.1uF ceramic capacitor is chip enabling. The external reference input is selected as
recommended to bypass the supply voltage. Place the the REFIN voltage is lower than 3.0V. The 100uA current
bypassing capacitor physically near the IC. source is turn off if the external reference input is select to
An internal linear regulator regulates supply voltage into a eliminate the load effect on the reference input. The softstart
4.5V voltage 4.5VDD for internal control logic circuit. No cycle is initiated after reference selection is completed.
external bypass capacitor is required for filtering the 4.5VDD Note that the 100uA current source will induces load
voltage. effect on the external reference input and causes the
The uP6103 integrates MOSFET gate drives that are REFIN voltage slightly higher than the external
powered from the VCC pin and support 12V+12V driving reference input during the reference selection. Make
capability. A bootstrap diode is embedded to facilitates PCB sure that the external reference input is strong enough
design and reduce the total BOM cost. No external so that REFIN voltage will not be higher than 3.0V.
Schottky diode is required. Converters that consist of
uP6103 feature high efficiency without special consideration
uP6103
on the selection of MOSFETs. 4.5VDD
Reference
Note: The embedded bootstrap diode is not a Schottky Voltage Reference
diode having a 0.7V forward voltage. External Selection

Schottky diode is highly recommended if the VCC 100uA

voltage is expected to be lower than 5.0V. Otherwise VREF

the bootstrap diode may be too low for the device to (0.6V)

work normally. Reference REFIN

Input 7
Power On Reset and Chip Enable 3.0V
Disable
A power on reset (POR) circuitry continuously monitors Enable
Q1 1ms
the supply voltage at VCC pin. Once the rising POR Chip Delay
0.3V Enable
threshold is exceeded, the uP6103 sets itself to active
state and is ready to accept chip enable command. The
rising POR threshold is typically 4.2V at VCC rising.
Figure 1. Chip Enable and Reference Selection Function
The REFIN is a multifunctional pin: external reference input
SoftStart
and chip enable as shown in Figure 1. To Select Internal
0.6V Reference Voltage, just let the REFIN open. A 100uA A built-in Soft Start is used to prevent surge current from
current source tries to pull high the REFIN voltage after power supply input during turn on (referring to the Functional
POR that is monitored by the Enable Comparator monitors Block Diagram). The error amplifier is a three-input device.
for chip enable. A signal level transistor is adequate to pull Reference voltage VREF or the internal soft start voltage SS
this pin down to ground and shut down the uP6103. As Q1 whichever is smaller dominates the behavior of the non-
is turned off, the REFIN voltage is pulled high to 3.3VDD by inverting input of the error amplifier. SS internally ramps up

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Functional Description
to 5VDD in 66ms after the softstart cycle is intiated (for uP6103, 300kHz for uP6103A. Higher switching frequncy
uP6103). The ramp is created digitally, so there will be 100 allows higher control bandwidth and faster transient
small discrete steps. Accordingly, the output voltage will response. However higher swithcing frequency results in
follow the SS signal and ramp up smoothly to its target higher power loss in both controller and power MOSFETs.
level. The uP6103 detects PHASE voltage for the existence of
The SS signal keeps ramping up after it execeeds the power input when the UGATE turns on the first time. If the
internal reference VREF. However, the reference voltage VREF PHASE voltage does not exceed 3.0V when the UGATE
takes over the behavior of error amplifier after SS > VREF. turns on, the uP6103 asserts that power input in not ready
When the SS signal climb to its ceiling voltage (5V), the and stops the softstart cycle. However, the internal SS
uP6103 claims the end of softstart cyclce and enable the continues ramping up to 3.3VDD. Another softstart is
under voltage protection of the output voltage. initiated after SS ramps up to 3.3VDD. The hiccup period
For internal reference voltage, the effective ramp-up time of is about 6.4ms. Figure 3 shows the start up interval where
the output voltage is about 3.6ms. For external reference VIN does not present initially.
voltage, the effective ramp up time output voltage is
calculated as:

TSS = 6 × VREF (ms)

Figure 2 shows a typical start up interval where the REFIN V IN
pin has been released from a grounded (system shutdown) 5V/Div
state.
V OUT
5V/Div

V IN
5V/Div LGATE
V OUT
0.5V/Div 5V/Div

1ms/Div

LGATE Figure 3. Softstart where VIN does not Present Initially.

5V/Div

Overcurrent Protection (OCP)

IX
2.5/Div
The uP6103 detects voltage drop across the lower MOSFET
(VPHASE) for overcurrent protection when it is turn on. If VPHASE
2ms/Div is lower than VOCP = -375mV, the uP6103 asserts OCP and
Figure 2. Softstart Behavior. shuts down the converter.

Power Input Detection Another factor should taken into consideration is the ripple
of the inductor current. The current near the valley of the
The uP6103 detects PHASE voltage for the present of power
ripple current is used for OCP, resulting the averaged OCP
input when the UGATE turns on the first time. If the PHASE
level a little higher than the calculated value.
voltage does not exceed 3.0V when the UGATE turns on,
the uP6103 asserts that power input in not ready and stops Undervoltage Protection (UVP)
the softstart cycle. However, the internal SS continues The FB voltage is monitored for undervoltage protection.
ramping up to 5VDD. Another softstart is initiated after SS The UVP threshold level is typical 0.4V for both stand-
ramps up to 5VDD. The hiccup period is about 12ms. Figure alone and tracking mode. The uP6103 shuts down upon
3 shows the start up interval where VIN does not present the detection of UVP and can be reset only by POR or
initially. toggling REFIN pin.
Switching Frequency
The switching frequency is fixed and can not be changed
externally. Typical switching frequency is 200kHz for

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Absolute Maximum Rating
Supply Input Voltage, VCC (Note 1) ------------------------------------------------------------------------------------------------ -0.3V to +15V
PHASE to GND
DC ------------------------------------------------------------------------------------------------------------------------------------- -5V to 15V
< 200ns ---------------------------------------------------------------------------------------------------------------------------- -10V to 30V
BOOT to GND
DC ------------------------------------------------------------------------------------------------------------------------- -0.3V to PHASE +15V
< 200ns -------------------------------------------------------------------------------------------------------------------------- -0.3V to 42V
LGATE to GND
DC ------------------------------------------------------------------------------------------------------------------------------------- -1V to 15V
< 200ns ---------------------------------------------------------------------------------------------------------------------------- -5V to 30V
UGATE to PHASE
DC ------------------------------------------------------------------------------------------------------------------------------------- -0.3V to 15V
< 200ns ---------------------------------------------------------------------------------------------------------------------------- -2V to 20V
Input, Output or I/O Voltage ---------------------------------------------------------------------------------------------------------- -0.3V to +6V
Storage Temperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V
Thermal Information
Package Thermal Resistance (Note 3)
SOP-8 θJA ---------------------------------------------------------------------------------------------------------------------------------- 160°C/W
SOP-8 θJC ----------------------------------------------------------------------------------------------------------------------------------- 39°C/W
PSOP-8 θJA---------------------------------------------------------------------------------------------------------------------------------- 50°C/W
PSOP-8 θJC------------------------------------------------------------------------------------------------------------------------------------ 5°C/W
Power Dissipation, PD @ TA = 25°C
SOP-8 ------------------------------------------------------------------------------------------------------------------------------------------- 0.625W
PSOP-8 ------------------------------------------------------------------------------------------------------------------------------------------------- 2W
Recommended Operation Conditions
Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C
Operating Ambient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C
Supply Input Voltage, VCC ---------------------------------------------------------------------------------------------------------------- +4.5V to 13.2V
Electrical Characteristics
(VCC = 12V, TA = 25OC, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Units
Supply Input
Supply Voltage VC C 4.5 -- 13.2 V
Supply Current IC C UGATE, LGATE Open; VC C = 12V, Switching -- 3 -- mA
Quiescent Supply Current IC C _ Q VF B = 0.7V, No Switching -- 2 -- mA
Power Input Voltage VIN 3.0 -- 13.2 V
Pow er On Reset
POR Threshold VC C R T H VC C rising 4.0 4.2 4.4 V
POR Hysteresis V C C H YS -- 0.5 -- V

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Units
Oscillator
uP6103 170 200 230 kHz
Free Running Frequency fOSC
uP6103A 255 300 345 kHz
Ramp Amplitude ∆VOSC V C C = 12V -- 1.0 -- VP-P
Error Amplifier
Open Loop DC Gain AO Guaranteed by Design 55 70 -- dB
Gain-Bandwidth Product GBW Guaranteed by Design -- 10 -- MHz
Slew Rate SR Guaranteed by Design 3 6 -- V/us
Transconductance Guaranteed by Design -- -- 0.7 mS
PWM Controller Gate Drivers
Upper Gate Sourcing Current IUG_SRC VBOOT - VPHASE = 12V, VBOOT - VUGATE = 6V -- -1 -- A
Upper Gate Sinking Current IUG_SNK VBOOT - VPHASE = 12V, VUGATE - VPHASE= 6V -- 1.5 -- A
Upper Gate RDS(ON) Sinking RUG_SNK VUGATE - VPHASE = 0.1V -- 2 4 Ω
Lower Gate Sourcing Current ILG_SRC VCC - VLGATE = 6V -- -1 -- A
Lower Gate Sinking Current ILG_SNK VLGATE = 6V -- 2 -- A
Lower Gate RDS(ON) Sinking RLG_SNK VLGATE = 0.1V -- 2 4 Ω
PHASE Falling to LGATE
VCC = 12V; VPHASE < 1.2V to VLGATE > 1.2V -- 30 90 ns
Rising Delay
LGATE Falling to UGATE VCC = 12V; VLGATE < 1.2V to (VUGATE - VPHASE ) >
-- 30 90 ns
Rising Delay 1.2V
Reference Voltage
Nominal Feedback Voltage V FB Stand Alone Mode 0.591 0.6 0.609 V
| VFB - VREFIN |, VREFIN = 0.4V ~ 1.0V, Tracking
-- -- 15 mV
Mode
Output Voltage Accuracy
| VFB - VREFIN | / VREFIN, VREFIN = 1.0V ~ 3.0V,
-- -- 1.5 %
Tracking Mode
REFIN Enable Threshold VREFIN -- 0.3 0.35 V
Protection
Under Voltage Protection VFB_UVP 0.3 0.4 0.5 V
Over Current Threshold VPHASE RLGATE Open -- -375 -- mV
Soft-Start Interval TSS Stand Alone Mode 2.4 3.6 4.8 ms
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Typical Operation Characteristics
Power On Waveforms Turn On from REFIN

VIN REFIN
5V/Div 2V/Div VOUT
V OUT
0.5V/Div 0.5V/Div

LGATE LGATE
5V/Div 5V/Div

IX
2.5/Div IX
2.5A/Div

2ms/Div 2ms/Div
VIN =12V, VOUT = 1.2V, COUT = 1500uF, No Load VIN =12V, VOUT = 1.2V, COUT = 1500uF, No Load

Turn OFf from REFIN Switching Waveforms: UGATE Turn On

UGATE
5V/Div
VOUT
0.5V/Div
LGATE
10V/Div LGATE PHASE
5V/Div 5V/Div

IX
10A/Div UGATE - PHASE
5V/Div

REFIN
5V/Div

10us/Div 25ns/Div
VIN = 12V, VOUT = 1.2V, COUT = 1500uF, IOUT = 6A VIN = 12V, IOUT = 10A

Switching Waveforms: UGATE Trun Off REFIN Operation

UGATE
LGATE
5V/Div
5V/Div
UGATE - PHASE
LGATE
5V/Div
5V/Div

PHASE
5V/Div

REFIN
0.5V/Div VOUT
0.5V/Div

25ns/Div 10ms/Div
VIN = 12V, IOUT = 10A VIN = 12V, COUT = 1500uF, IOUT = 6A

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Typical Operation Characteristics
Power Sequencing Operation Load Transient Response

IOUT
10A/Div

VIN
5V/Div
VOUT
5V/Div
VOUT
5V/Div

PHASE
10V/Div
LGATE
5V/Div

1ms/Div 10us/Div
VCC =12V Ready, VOUT = 1.2V, COUT = 1500uF, No Load VIN =12V, VOUT = 1.2V, COUT = 1500uF

Over Current Protection Over Current Protection

VOUT VOUT
0.5V/Div 0.5V/Div

PHASE PHASE
5V/Div 5V/Div

IX IX
20A/Div 20A/Div

5ms/Div, VIN = 12V, VOUT = 1.2V, COUT = 1500uF, 5ms/Div, VIN = 12V, VOUT = 1.2V, COUT = 1500uF,
Output Short to Ground Turn On to Short Circuit

Load Regulation Line Regulation

0.3
0.5
0.2 0.4
Output Voltage Deviation (%)

Output Voltage Deviation (%)

0.1 0.3
0 0.2
-0.1 0.1
-0.2 0
-0.3 -0.1
-0.4 -0.2

-0.5 -0.3

-0.6 -0.4
-0.5
-0.7
4 6 8 10 12 14
0 5 10 15 20 25 30

Output Current (A) Input Voltage (V)

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Typical Operation Characteristics
Switching Frequency vs. Input Voltage Switching Frequency vs. Junction Temperature
225 225
220 220
Switching Frequency (kHz)

Switching Frequency (kHz)

215 215
210 210
205 205
200 200
195 195
190 190
185 185
180 180
175 175
4 6 8 10 12 14 -50 -25 0 25 50 75 100 125

Input Voltage (V) Junction Temperature (OC)

Output Voltage vs. Junction Temperature

3
2.5
2
Output Voltage Varition (%)

1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-50 -25 0 25 50 75 100 125

Junction Temperature (OC)

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Application Information
Power MOSFET Selection Both MOSFETs have I2R losses and the top MOSFET
External component selection is primarily determined by includes an additional term for switching losses, which are
the maximum load current and begins with the selection of largest at high input voltages. The bottom MOSFET losses
power MOSFET switches. The uP6103 requires two are greatest when the bottom duty cycle is near 100%,
external N-channel power MOSFETs for upper (controlled) during a short-circuit or at high input voltage. These
and lower (synchronous) switches. Important parameters equations assume linear voltage current transitions and do
for the power MOSFETs are the breakdown voltage V(BR)DSS, not adequately model power loss due the reverse-recovery
on-resistance RDS(ON), reverse transfer capacitance CRSS, of the lower MOSFET’s body diode. Ensure that both
maximum current IDS(MAX), gate supply requirements, and MOSFETs are within their maximum junction temperature
thermal management requirements. at high ambient temperature by calculating the temperature
rise according to package thermal-resistance
The gate drive voltage is powered by VCC pin that receives specifications. A separate heatsink may be necessary
4.5V~13.2V supply voltage. When operating with a 12V depending upon MOSFET power, package type, ambient
power supply for VCC (or down to a minimum supply temperature and air flow.
voltage of 8V), a wide variety of NMOSFETs can be used.
Logic-level threshold MOSFET should be used if the input The gate-charge losses are dissipated by the uP6103 and
voltage is expected to drop below 8V. Since the lower don’t heat the MOSFETs. However, large gate charge
MOSFET is used as the current sensing element, particular increases the switching interval, TSW that increases the
attention must be paid to its on-resistance. Look for RDS(ON) MOSFET switching losses. The gate-charge losses are
ratings at lowest gate driving voltage. calculated as:

Special cautions should be exercised on the lower switch PG = VCC × ( VCC × (CISS _ UP + CISS _ LO ) + VIN × CRSS ) × fOSC
exhibiting very low threshold voltage VGS(TH). The shoot-
through protection present aboard the uP6103 may be where CISS_UP is the input capacitance of the upper
circumvented by these MOSFETs if they have large MOSFET, CISS_LO is the input capacitance of the lower
parasitic impedences and/or capacitances that would inhibit MOSFET, and CRSS_UP is the reverse transfer capacitance
the gate of the MOSFET from being discharged below its of the upper MOSFET. Make sure that the gate-charge loss
threshold level before the complementary MOSFET is will not cause over temperature at uP6103, especially with
turned on. Also avoid MOSFETs with excessive switching large gate capacitance and high supply voltage.
times; the circuitry is expecting transitions to occur in under Output Inductor Selection
50 nsec or so.
Output inductor selection usually is based the
In high-current applications, the MOSFET power considerations of inductance, rated current, size
dissipation, package selection and heatsink are the requirement, and DC resistance (DC)
dominant design factors. The power dissipation includes
Given the desired input and output voltages, the inductor
two loss components; conduction loss and switching loss.
value and operating frequency determine the ripple current:
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs. 1 V
∆IL = × VOUT × (1 − OUT )
These losses are distributed between the two MOSFETs fOSC × L OUT VIN
according to duty cycle. Since the uP6103 is operating in
Lower ripple current reduces core losses in the inductor,
continuous conduction mode, the duty cycles for the
ESR losses in the output capacitors and output voltage
MOSFETs are:
ripple. Highest efficiency operation is obtained at low
VOUT VIN − VOUT frequency with small ripple current. However, achieving this
DUP = DLO = requires a large inductor. There is a tradeoff between
VIN VIN
; component size, efficiency and operating frequency. A
The resulting power dissipation in the MOSFETs at reasonable starting point is to choose a ripple current that
maximum output current are: is about 40% of IOUT(MAX).
2
PUP = IOUT × RDS(ON) × DUP + 0.5 × IOUT × VIN × TSW × fOSC There is another tradeoff between output ripple current/
voltage and response time to a transient load. Increasing
2
PLO = IOUT × RDS(ON) × DLO the value of inductance reduces the output ripple current
and voltage. However, the large inductance values reduce
where TSW is the combined switch ON and OFF time. the converter’s response time to a load transient.

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Application Information
Maximum current ratings of the inductor are generally manufacturer’s ripple current ratings are often based on
specified in two methods: permissible DC current and 2000 hours of life. This makes it advisable to further derate
saturation current. Permissible DC current is the allowable the capacitor, or choose a capacitor rated at a higher
DC current that causes 40OC temperature raise. The temperature than required. Always consult the manufacturer
saturation current is the allowable current that causes 10% if there is any question.
inductance loss. Make sure that the inductor will not For a through-hole design, several electrolytic capacitors
saturate over the operation conditions including temperature may be needed. For surface mount designs, solid tantalum
range, input voltage range, and maximum output current. capacitors can also be used, but caution must be exercised
The size requirements refer to the area and height with regard to the capacitor surge current rating. These
requirement for a particular design. For better efficiency, capacitors must be capable of handling the surge-current
choose a low DC resistance inductor. DCR is usually at power-up. Some capacitor series available from reputable
inversely proportional to size. manufacturers are surge current tested.
Different core materials and shapes will change the size/ Output Capacitor Selection
current and price/current relationship of an inductor. Toroid An output capacitor is required to filter the output and supply
or shielded pot cores in ferrite or permalloy materials are the load transient current. The selection of COUT is primarily
small and don’t radiate much energy, but generally cost determined by the ESR required to minimize voltage ripple
more than powdered iron core inductors with similar electrical and load step transients. The output ripple ∆VOUT is
characteristics. The choice of which style inductor to use approximately bounded by:
often depends more on the price vs. size requirements
and any radiated field/EMI requirements. 1
∆VOUT ≤ ∆IL (ESR + )
Input Capacitor Selection 8 × fOSC × C OUT

The synchronous-rectified buck converter draws pulsed Since ∆IL increases with input voltage, the output ripple is
current with sharp edges from the input capacitor resulting highest at maximum input voltage. Typically, once the ESR
in ripples and spikes at the input supply voltage. Use a requirement is satisfied, the capacitance is adequate for
mix of input bypass capacitors to control the voltage filtering and has the necessary RMS current rating. Multiple
overshoot across the MOSFETs. Use small ceramic capacitors placed in parallel may be needed to meet the
capacitors for high frequency decoupling and bulk capacitors ESR and RMS current handling requirements. Dry tantalum,
to supply the current needed each time upper MOSFET special polymer, aluminum electrolytic and ceramic
turns on. Place the small ceramic capacitors physically capacitors are all available in surface mount packages.
close to the MOSFETs and between the drain of upper Special polymer capacitors offer very low ESR but have
MOSET and the source of lower MOSFET to avoid the lower capacitance density than other types.
stray inductance along the connection trace. The load transient requirements are a function of the slew
The important parameters for the bulk input capacitor are rate (di/dt) and the magnitude of the transient load current.
the voltage rating and the RMS current rating. For reliable These requirements are generally met with a mix of
operation, select the bulk capacitor with voltage and current capacitors and careful layout. Modern components and
ratings above the maximum input voltage and largest RMS loads are capable of producing transient load rates above
1A/ns. High frequency capacitors initially supply the
current required by the circuit. The capacitor voltage rating
transient and slow the current load rate seen by the bulk
should be at least 1.25 times greater than the maximum
capacitors. The bulk filter capacitor values are generally
input voltage and a voltage rating of 1.5 times is a
determined by the ESR (Effective Series Resistance) and
conservative guideline. The RMS current rating requirement
voltage rating requirements rather than actual capacitance
for the input capacitor of a buck converter is calculated as:
requirements.
VOUT ( VIN − VOUT ) High frequency decoupling capacitors should be placed as
IIN(RMS) = IOUT(MAX ) close to the power pins of the load as physically possible.
VIN
Be careful not to add inductance in the circuit board wiring
This formula has a maximum at VIN = 2VOUT, where IIN(RMS) that could cancel the usefulness of these low inductance
= I OUT(RMS) /2. This simple worst-case condition is components. Consult with the manufacturer of the load on
commonly used for design because even significant specific decoupling requirements.
deviations do not offer much relief. Note that the capacitor

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Application Information
Use only specialized low-ESR capacitors intended for 2 Place the power components as physically close as
switching-regulator applications for the bulk capacitors. The possible.
bulk capacitor’s ESR will determine the output ripple 2.1 Place the input capacitors, especially the high-
voltage and the initial voltage drop after a high slew-rate frequency ceramic decoupling capacitors, directly
transient. An aluminum electrolytic capacitor’s ESR value to the drain of upper MOSFET ad the source of the
is related to the case size with lower ESR available in lower MOSFET. To reduce the ESR replace the
larger case sizes. single input capacitor with two parallel units
However, the Equivalent Series Inductance (ESL) of these 2.2 Place the output capacitor between the converter
capacitors increases with case size and can reduce the and load.
usefulness of the capacitor to high slew-rate transient
loading. 3 Place the uP6103 near the upper and lower MOSFETs
with pins 1 to 4 facing the power components. Keep
Unfortunately, ESL is not a specified parameter. Work with the components connected to pins 4 to 8 close to the
your capacitor supplier and measure the capacitor’s uP6103 and away from the inductor and other noise
impedance with frequency to select a suitable component. sources (noise sensitive components).
In most cases, multiple electrolytic capacitors of small case
size perform better than a single large case capacitor. 4 Use a dedicated grounding plane and use vias to ground
all critical components to this layer. The ground plane
Bootstrap Capacitor Selection layer should not have any traces and it should be as
An external bootstrap capacitor CBOOT connected to the close as possible to the layer with power MOSFETs.
BOOT pin supplies the gate drive voltage for the upper Use an immediate via to connect the components to
MOSFET. This capacitor is charged through the internal ground plane including GND of uP6103. Use several
diode when the PHASE node is low. When the upper bigger vias for power components.
MOSFET turns on, the PHASE node rises to VIN and the 5 Apply another solid layer as a power plane and cut this
BOOT pin rises to approximately VIN + VCC. The boot plane into smaller islands of common voltage levels.
capacitor needs to store about 100 times the gate charge The power plane should support the input power and
required by the upper MOSFET. In most applications 0.1uF output power nodes to maintain good voltage filtering
to 0.47uF, X5R or X7R dielectric capacitor is adequate. and to keep power losses low. Also, for higher currents,
PCB Layout Considerations it is recommended to use a multilayer board to help
High speed switching and relatively large peak currents in with heat sinking power components.
a synchronous-rectified buck converter make the PCB layout 6 The PHASE node is subject to very high dV/dt voltages.
a very important part of design. Fast current switching from Stray capacitance between this island and the
one device to another in a synchronous-rectified buck surrounding circuitry tend to induce current spike and
converter causes voltage spikes across the interconnecting capacitive noise coupling. Keep the sensitive circuit
impedances and parasitic circuit elements. The voltage away from the PHASE node and keep the PCB
spikes can degrade efficiency and radiate noise that result areasmall to limit the capacitive coupling. However, the
in overvoltage stress on devices. Careful component PCB area should be kept moderate since it also acts
placement layout and printed circuit design minimizes the as main heat convection path of the lower MOSFET.
voltage spikes induced in the converter. 7 uP6103 sources/sinks impulse current with 2A peak to
Follow the layout guidelines for optimal performance of turn on/off the upper and lower MOSFETs. The
uP6103 connecting trance between the controller and gate/
1 The upper and lower MOSFETs turn on/off and conduct source of the MOSFET should be wide and short to
pulsed current alternatively with high slew rate transition. minimize the parasitic inductance along the traces.
Any inductance in the switched current path generates 8 Flood all unused areas on all layers with copper.
a large voltage spike during the switching. The Flooding with copper will reduce the temperature rise
interconnecting wires indicated by red heavy lines of power component.
conduct pulsed current with sharp transient and should 9 Provide local VCC decoupling between VCC and GND
be part of a ground or power plane in a printed circuit pins. Locate the capacitor, CBOOT as close as practical
board to minimize the voltage spike. Make all the to the BOOT and PHASE pins.
connection the top layer with wide, copper filled areas.

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Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Package Information
SOP - 8L

0.70 ± 0. 10 1.27 ± 0.10

4.80 - 5.00

1.50 ± 0.10
4.00 ± 0. 10
7.00 ± 0.10
5.50 ± 0.10

5.80 - 6.20
3.80 - 4.00
1.27 BSC 0.32 - 0.52

Recommended Solder Pad Layout

1.45 - 1.60

0.18 - 0.25 1.75 MAX

0.10 - 0.25

0.41 - 0.89 3.81 BSC

Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.

uPI Semiconductor Corp., http://www.upi-semi.com 14

Rev. F00, File Name: uP6103-DS-F0000
 uP6103
Package Information
PSOP - 8L

0.70 ± 0. 10 4.80 - 5.00

1.27 ± 0.10
1.80 - 2.30

1.50 ± 0. 10
2.20 ± 0. 10

4.00 ± 0. 10
2.20 ± 0. 10
7.00 ± 0.10
5.50 ± 0.10

5.80 - 6.20
3.80 - 4.00

1.80 - 2.30
1.27 BSC 0.32 - 0.52

Recommended Solder Pad Layout

1.45 - 1.60

0.18 - 0.25 1.75 MAX

0.05 - 0.25

0.40 - 0.90 3.81 BSC

Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.

uPI Semiconductor Corp., http://www.upi-semi.com 15

Rev. F00, File Name: uP6103-DS-F0000