U s e r ’ s M a nu a l , V2 .

0 , J u l y 2 0 0 7

TC1796
3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r
V o l u m e 1 ( o f 2 ) : S y s t e m U n i ts
V o l u m e 2 ( o f 2 ): P e r i p h e r a l U n i t s

M i c r o c o n t r o l l e rs
Edition 2007-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.

Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.

Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
 U s e r ’ s M a nu a l , V2 . 0 , J u l y 2 0 0 7

TC1796
3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r
V o l u m e 1 ( o f 2 ) : S y s t e m U n i ts
V o l u m e 2 ( o f 2 ): P e r i p h e r a l U n i t s

M i c r o c o n t r o l l e rs
 TC1796
System and Peripheral Units (Vol. 1 and 2)

TC1796 User’s Manual

Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units
Revision History: V2.0, 2007-07
Previous Version: V1.0 2005-06
Page Subjects (major changes since last revision)
TC1796 User’s Manual Version 2.0 includes the contents of the TC1796 Documentation
Addendum, V1.2, Apr. 2007. Furthermore, the complete document and especially the
register description have been updated to allow document-automation processes based
on XML technologies.
Volume 1: System Units
1-20 MSC baud rate feature item is updated.
1-25 Figure 1-7 is updated.
1-34 Figure 1-11 is updated.
1-37, 1-38 Footnote marking for EBU pins is removed; pad driver class for BFCLKI
is added.
1-53 Pad driver classes for several System I/O pins are updated/added.
1-58 Table 1-6 is added.
2-10 CPU_ID is added.
2-12 MMU_CON long register name is updated.
2-13 CPS_ID is added.
2-14 CPU_SRCn.TOS bit description is updated.
2-21 Offset addresses in Table 2-6 are updated by absolute addresses.
2-26, 2-27 PMI_ID is added.
2-34, 2-35 DMI_ID is added.
3-18 Sequence of setting up the PLL after reset is updated.
4-1 Attention paragraph at the bottom is added.
4-10 Tuning Protection Section is removed.
4-24 Figure 4-6 is updated.
5-20, 5-22 Bit description of RENx is updated.
5-49 Figure 5-11 is updated.
5-61, 5-69 SCU_ID is added.
5-68 Bit description of PARAV is updated.
5-59 Bit description of ENON is updated.

User’s Manual V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)

TC1796 User’s Manual

Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units
Revision History: V2.0, 2007-07
6-4 Figure 6-2 is updated.
6-7, 6-8 DBCU_ID and PBCU_ID are added.
6-9 Bit description of LEC is updated.
6-16, 6-17 LFI_ID is added.
6-21 Section 6.4.3 is updated.
6-22 Figure 6-7 is updated.
6-30 BCU breakpoint Trigger Combination Logic in Figure 6-12 is updated.
6-34, 6-36 SBCU_ID and RBCU_ID are added.
7-16 DFLASH addresses in Table 7-7 are updated
7-40, 7-41, FLASH_ID and PMU_ID are added.
7-42
7-43 Bit description of FABUSY is updated.
7-58 Footnote is added to FLASH_CON register.
8-7 Section 8.5.2 is updated.
8-10, 8-11 DMU_ID is added.
9-5, 9-7, 9-9 Short name for SBRAM and SPRAM is updated.
11-52, 11-54 PCP_ID is added.
11-59 PCP_ES bit 5 is updated.
11-74 Counter Reload Value (COPY) in Table 11-13 is updated.
11-78 Figure 11-14 is updated.
11-103 Syntax description of ST.PI is updated.
12-9 Figure 12-5 is updated.
12-10 Figure 12-6 is updated.
12-16 Section 12.1.4.5 is updated.
12-29 Figure 12-20 is updated.
12-30 Figure 12-21 is updated.
12-34 The pattern detection description in Section 12.1.9 is updated.
12-42, 12-43, DMA_ID is added.
12-45
12-52, 12-53 Bit descriptions of CH0x/CH1x and HTRE0x/HTRE1x are updated.

User’s Manual V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)

TC1796 User’s Manual

Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units
Revision History: V2.0, 2007-07
12-99 Address range for AEN21 is updated.
12-111, MCHK_ID is added.
12-112
13-3 Section 13.2.1 is updated.
13-24 CONF32BIT description is updated.
13-72 BFCLKO configurations in Figure 13-27 are updated.
13-75 Burst Flash Read Cycle diagram in Figure 13-29 is added.
13-79, 13-81 EBU_ID is added.
14-13 NMI trap handler in Figure 14.5 is updated.
15-7, 15-8, STM_ID is added.
15-10
18-16 Access modes in Table 18-7 are updated.
18-122 DBCU register adresses in Table 18-38 are updated.
Volume 2: Peripheral Units
19-19, 19-20 ASC0_ID and ASC1_ID register are added.
20-21 Note in Figure 20-11 corrected; TB write operation in
Section 20.1.2.11 is updated.
20-24, 20-31, SSC error interrupt control in Section 20.1.2.12 and bit description
20-33 STIP, EN are updated.
20-27, 20-29 SSC0_ID and SSC1_ID registers are added.
20-37, 20-39, Notes below register SSOC and SSOTC are updated.
21-26 Figure 21-18 is updated (sampling start).
21-36, 21-38 MSC0_ID and MSC1_ID registers are added.
21-42 Bit description of NDBH is updated.
21-21, 21-25, Values for baud rate selections corrected at several locations and
21-66 equations.
22-53 Usage of bit RXEN in Section 22.3.11.5 is updated.
22-54 First paragraph of Section 22.3.11.6 is updated.
22-59 Offset addresses for registers MSIMASK, PANCTR, MCR, and MITR in
Table 22-5 corrected.

User’s Manual V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)

TC1796 User’s Manual

Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units
Revision History: V2.0, 2007-07
22-58, 22-59, CAN_ID register is added.
22-61
22-60 Figure 22-24 is updated.
22-79 CPU write to LEC in last row of Table 22-7 is updated.
22-90 CAN Bus State for of NoBit and NewBit in Table 22-9 is corrected.
22-201 Configuration of CAN_FDR.DM for Equation (22.1) and
Equation (22.2) is updated.
Chapter 23 The functional description of the MLI , the module kernel description,
and operation the MLI module is completely reworked.
23-75, 23-76, MLI0_ID and MLI1_ID registers are added.
23-78
23-3 Programmable baud rate in Section 23.1.1.1 is updated.
23-115 Register description of RPxBAR (x = 0-3) is updated.
23-129 Equation (23.6) is added.
23-142 Selected address range for AEN21 corrected.
24-31, 24-32, Figure 24-20, Figure 24-21, Figure 24-22, and Figure 24-23 are
24-33, 24-34 updated.
24-61, 24-77 Cell Enabling on Event sections for GTC and LTC are updated.
24-76 Header of Table 24-4 is updated.
24-150, GPTA0_ID and GPTA1_ID registers are added.
24-151,
24-154
24-233, LTCA2_ID register is added.
24-235
24-125, Section 24.2.6.3 “Check_Input()” and Section 24.2.6.6
24-131 “Manage_Mux()“ are updated.
24-253 Table 24-26 is updated.
24-263 Figure 24-91 is updated.
24-266 Attention paragraph at the bottom is updated.
25-9 Equation (25.1) is updated.
25-37 The reference voltage Section 25.1.5 is updated.

User’s Manual V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)

TC1796 User’s Manual

Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units
Revision History: V2.0, 2007-07
25-57, 25-58, ADC0_ID register is added.
25-59
26-8 Equation (26.1) is updated.
26-27, 26-28, FADC_ID register is added.
26-29

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User’s Manual V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)
Table of Contents

Table of Contents
This “Table of Contents” section refers to page numbers in both parts of the TC1796
User’s Manual, the “System Units” (volume 1 with marking “[1]”) and the “Peripheral
Units” (volume 2 with marking “[2]”) parts.

System Units (Vol. 1 of 2)

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]
1.1 About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]
1.1.1 Related Documentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]
1.1.2 Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]
1.1.3 Reserved, Undefined, and Unimplemented Terminology . . . . . . . . 1-3 [1]
1.1.4 Register Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 [1]
1.1.5 Abbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 [1]
1.2 System Architecture of the TC1796 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 [1]
1.2.1 TC1796 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 [1]
1.2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 [1]
1.3 On-Chip Peripheral Units of the TC1796 . . . . . . . . . . . . . . . . . . . . . . 1-14 [1]
1.3.1 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 [1]
1.3.1.1 Asynchronous/Synchronous Serial Interfaces . . . . . . . . . . . . . . 1-15 [1]
1.3.1.2 High-Speed Synchronous Serial Interfaces . . . . . . . . . . . . . . . . 1-17 [1]
1.3.1.3 Micro Second Channel Interfaces . . . . . . . . . . . . . . . . . . . . . . . 1-19 [1]
1.3.1.4 MultiCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 [1]
1.3.1.5 Micro Link Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 [1]
1.3.2 General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 [1]
1.3.2.1 Functionality of GPTA0 and GPTA1 . . . . . . . . . . . . . . . . . . . . . 1-27 [1]
1.3.2.2 Functionality of LTCA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 [1]
1.3.3 Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 [1]
1.3.3.1 Analog-to-Digital Converters (ADC0 and ADC1) . . . . . . . . . . . . 1-30 [1]
1.3.3.2 Fast Analog-to-Digital Converter Unit (FADC) . . . . . . . . . . . . . . 1-32 [1]
1.4 TC1796 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . 1-34 [1]
1.4.1 TC1796 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 [1]
1.4.2 Pad Driver Classes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 [1]
1.4.3 Pull-Up/Pull-Down Behavior of the Pins . . . . . . . . . . . . . . . . . . . . 1-58 [1]
2 CPU Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1]
2.1 TC1796 Processor Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1]
2.2 Central Processing Unit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 [1]
2.2.1 CPU Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 [1]
2.2.2 Instruction Fetch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 [1]
2.2.3 Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 [1]

User’s Manual L-1 V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)
Table of Contents

2.2.4 General Purpose Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 [1]

2.3 Implementation-specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 [1]
2.3.1 Context Save Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 [1]
2.3.2 Fast Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 [1]
2.3.3 Reset System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 [1]
2.3.4 Program Counter Register - PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 [1]
2.3.5 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 [1]
2.3.6 Trap System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 [1]
2.4 TC1796 CPU Subsystem Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 [1]
2.4.1 Core Special Function Registers (CSFR) . . . . . . . . . . . . . . . . . . . 2-10 [1]
2.4.1.1 Implementation-specific Core Special Function Registers . . . . 2-11 [1]
2.4.2 CPU Slave Interface (CPS) Registers . . . . . . . . . . . . . . . . . . . . . . 2-13 [1]
2.4.2.1 Implementation-specific CPU Slave Interface Registers . . . . . . 2-14 [1]
2.4.3 CPU General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 [1]
2.4.4 Core Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 [1]
2.4.4.1 Implementation-specific Core Debug Registers . . . . . . . . . . . . 2-18 [1]
2.4.5 Memory Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 [1]
2.4.5.1 Implementation-specific Memory Protection Registers . . . . . . . 2-23 [1]
2.5 Program Memory Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 [1]
2.5.1 PMI Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 [1]
2.5.2 Parity Protection for PMI Memories . . . . . . . . . . . . . . . . . . . . . . . . 2-25 [1]
2.5.3 PMI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 [1]
2.5.3.1 PMI Module Identification Register . . . . . . . . . . . . . . . . . . . . . . 2-27 [1]
2.5.3.2 PMI Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 [1]
2.5.3.3 PMI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1]
2.5.3.4 PMI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 [1]
2.6 Data Memory Interface (DMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 [1]
2.6.1 DMI Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 [1]
2.6.2 Dual-Ported Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1]
2.6.2.1 CPU Buffer Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1]
2.6.3 Parity Protection for DMI Memories . . . . . . . . . . . . . . . . . . . . . . . . 2-33 [1]
2.6.4 DMI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 [1]
2.6.4.1 DMI Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 [1]
2.7 Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 [1]
2.7.1 Integer-Pipeline Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 [1]
2.7.1.1 Simple Arithmetic Instruction Timings . . . . . . . . . . . . . . . . . . . . 2-41 [1]
2.7.1.2 Multiply Instruction Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 [1]
2.7.1.3 MAC Instruction Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 [1]
2.7.1.4 Control Flow Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 [1]
2.7.2 Load-Store Pipeline Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 [1]
2.7.2.1 Address Arithmetic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 [1]
2.7.2.2 Control Flow Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 [1]
2.7.2.3 Load Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 [1]

User’s Manual L-2 V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)
Table of Contents

2.7.2.4 Store Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 [1]

2.8 Floating Point Pipeline Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 [1]
3 Clock System and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1]
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1]
3.2 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1]
3.2.1 Main Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1]
3.2.1.1 Oscillator Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 [1]
3.2.1.2 Oscillator Run Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 [1]
3.2.1.3 Oscillator Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 [1]
3.2.1.4 Oscillator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 [1]
3.2.2 Phase Looked Loop (PLL) Circuitry . . . . . . . . . . . . . . . . . . . . . . . . 3-10 [1]
3.2.2.1 Clock Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 [1]
3.2.2.2 PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 [1]
3.2.2.3 PLL Clock Control and Status Register . . . . . . . . . . . . . . . . . . . 3-16 [1]
3.2.2.4 Changing PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1]
3.2.2.5 Setting up the PLL after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1]
3.2.2.6 Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 [1]
3.2.2.7 Loss-of-Lock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 [1]
3.2.3 Power-on Startup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 [1]
3.3 Module Power Management and Clock Gating . . . . . . . . . . . . . . . . . 3-22 [1]
3.3.1 Module Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 [1]
3.3.2 Clock Control Register CLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 [1]
3.3.3 Fractional Divider Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 [1]
3.3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 [1]
3.3.3.2 Fractional Divider Operating Modes . . . . . . . . . . . . . . . . . . . . . 3-32 [1]
3.3.3.3 Fractional Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 [1]
3.3.4 Module Clock Register Implementations . . . . . . . . . . . . . . . . . . . . 3-39 [1]
3.3.5 Fractional Divider Register Implementations . . . . . . . . . . . . . . . . . 3-40 [1]
3.4 System Clock Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 [1]
3.4.1 System Clock Fractional Divider Register . . . . . . . . . . . . . . . . . . . 3-42 [1]
4 Reset and Boot Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1]
4.1 Reset and Boot Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1]
4.1.1 Reset Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 4-3 [1]
4.1.1.1 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 [1]
4.1.1.2 Reset Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 [1]
4.2 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1]
4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1]
4.2.2 External Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1]
4.2.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 [1]
4.2.4 Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 [1]
4.2.5 Debug System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 [1]
4.2.6 Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 [1]

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Table of Contents

4.2.7 Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 [1]

4.2.7.1 Normal Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 [1]
4.2.7.2 Debug Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 [1]
4.3 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 [1]
4.3.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 [1]
4.3.2 Program Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 [1]
4.3.3 Initial State after Boot ROM Exit . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 [1]
4.4 Bootstrap Loader (BSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 [1]
4.4.1 Bootstrap Loader Mode 1 - ASC Boot via ASC0 Pins . . . . . . . . . . 4-21 [1]
4.4.2 Bootstrap Loader Mode 2 - CAN Boot via CAN Pins . . . . . . . . . . . 4-24 [1]
4.4.3 Bootstrap Loader Mode 3 - ASC Boot via CAN Pins . . . . . . . . . . . 4-28 [1]
4.4.4 Alternate Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 [1]
5 System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1]
5.1 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 [1]
5.1.1 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 [1]
5.1.2 Power Management Control and Status Register, PMG_CSR . . . . 5-3 [1]
5.1.3 Power Management Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 [1]
5.1.3.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 [1]
5.1.3.2 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 [1]
5.1.3.3 States of TC1796 Units in Power Management Modes . . . . . . . . 5-7 [1]
5.2 Configuration Input Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 [1]
5.3 External Request Unit (ERU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 [1]
5.3.1 Input Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 [1]
5.3.2 Output Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 [1]
5.3.3 External Request Unit Implementation . . . . . . . . . . . . . . . . . . . . . 5-14 [1]
5.3.4 External Request Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 [1]
5.4 Special System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 [1]
5.4.1 FPU Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 [1]
5.4.2 Flash Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 [1]
5.4.3 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 [1]
5.5 SRAM Parity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 [1]
5.5.1 Parity Error Trap Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 [1]
5.6 Pad Driver Temperature Compensation Control . . . . . . . . . . . . . . . . 5-41 [1]
5.6.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 [1]
5.6.2 Temperature Compensation Registers . . . . . . . . . . . . . . . . . . . . . 5-44 [1]
5.7 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48 [1]
5.8 GPTA1 Input IN1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 [1]
5.9 Pad Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 [1]
5.9.1 Pad Test Mode Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 [1]
5.9.2 Pad Test Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 [1]
5.10 Emergency Stop Output Control for GPTA and MSC . . . . . . . . . . . . 5-57 [1]
5.10.1 GPTA Output Emergency Control in the GPIO Ports . . . . . . . . . . 5-58 [1]

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5.10.2 MSC Emergency Control Selection . . . . . . . . . . . . . . . . . . . . . . . . 5-58 [1]

5.10.3 Emergency Stop Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59 [1]
5.11 Analog Input 7 Testmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 [1]
5.12 SCU Registers and Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-61 [1]
5.13 Miscellaneous SCU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 [1]
5.13.1 SCU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 [1]
5.13.2 SCU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 [1]
5.13.3 Device Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 [1]
6 On-Chip System Buses and Bus Bridges . . . . . . . . . . . . . . . . . . . . 6-1 [1]
6.1 Program and Data Local Memory Buses . . . . . . . . . . . . . . . . . . . . . . 6-2 [1]
6.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 [1]
6.1.2 Transaction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]
6.1.2.1 Single Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]
6.1.2.2 Block Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]
6.1.2.3 Atomic Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]
6.1.3 Address Alignment Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]
6.1.4 Reaction of a Busy Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]
6.1.5 LMB Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 [1]
6.2 Local Memory Bus Controller Units . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 [1]
6.2.1 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 [1]
6.2.2 LMB Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 [1]
6.2.2.1 LMB Bus Default Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 [1]
6.2.3 LMB Bus Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 [1]
6.2.4 DLMB and PLMB Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 [1]
6.3 Local Memory to FPI Bus Interface (LFI Bridge) . . . . . . . . . . . . . . . . 6-15 [1]
6.3.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 [1]
6.3.2 LFI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 [1]
6.4 System and Remote Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 [1]
6.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 [1]
6.4.2 Bus Transaction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 [1]
6.4.3 Reaction of a Busy Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 [1]
6.4.4 Address Alignment Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 [1]
6.4.5 FPI Bus Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 [1]
6.5 FPI Bus Control Units (SBCU and RBCU) . . . . . . . . . . . . . . . . . . . . . 6-24 [1]
6.5.1 FPI Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 [1]
6.5.1.1 Arbitration on the System Peripheral Bus . . . . . . . . . . . . . . . . . 6-24 [1]
6.5.1.2 Arbitration on the Remote Peripheral Bus . . . . . . . . . . . . . . . . . 6-24 [1]
6.5.1.3 Starvation Prevention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 [1]
6.5.2 FPI Bus Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 [1]
6.5.3 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 [1]
6.5.4 BCU Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 [1]
6.5.4.1 Address Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 [1]

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Table of Contents

6.5.4.2 Signal Status Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 [1]

6.5.4.3 Grant Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 [1]
6.5.4.4 Combination of Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 [1]
6.5.4.5 BCU Breakpoint Generation Examples . . . . . . . . . . . . . . . . . . . 6-31 [1]
6.5.5 SBCU and RBCU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 [1]
6.5.5.1 BCU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1]
6.5.5.2 BCU Error Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 [1]
6.5.5.3 OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 [1]
6.5.5.4 BCU Service Request Control Register . . . . . . . . . . . . . . . . . . . 6-58 [1]
7 Program Memory Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1]
7.1 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1]
7.2 Program & Data Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1]
7.2.1 Program Flash Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 [1]
7.2.2 Data Flash Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 [1]
7.2.3 User Configuration Blocks Overview . . . . . . . . . . . . . . . . . . . . . . . . 7-9 [1]
7.2.4 Basic Flash Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 [1]
7.2.4.1 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 [1]
7.2.4.2 Command Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 [1]
7.2.4.3 Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 [1]
7.2.5 Command Sequence Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 [1]
7.2.5.1 Reset-to-Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 [1]
7.2.5.2 Enter Page Mode Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 [1]
7.2.5.3 Load Page Buffer Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 [1]
7.2.5.4 Write Page Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 [1]
7.2.5.5 Write User Configuration Page Command . . . . . . . . . . . . . . . . 7-19 [1]
7.2.5.6 Erase Sector Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 [1]
7.2.5.7 Erase User Configuration Block Command . . . . . . . . . . . . . . . . 7-22 [1]
7.2.5.8 Disable Write Protection Command . . . . . . . . . . . . . . . . . . . . . . 7-23 [1]
7.2.5.9 Disable Read Protection Command . . . . . . . . . . . . . . . . . . . . . 7-24 [1]
7.2.5.10 Resume Protection Command . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 [1]
7.2.5.11 Clear Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 [1]
7.2.6 Data Flash and EEPROM Emulation . . . . . . . . . . . . . . . . . . . . . . . 7-26 [1]
7.2.7 Read and Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 [1]
7.2.7.1 User Configuration Block Definitions . . . . . . . . . . . . . . . . . . . . . 7-27 [1]
7.2.7.2 Write and OTP Protection for PFLASH . . . . . . . . . . . . . . . . . . . 7-30 [1]
7.2.7.3 Read Protection for PFLASH and DFLASH . . . . . . . . . . . . . . . . 7-32 [1]
7.2.7.4 Password Check Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 [1]
7.2.8 Error Correction and Margin Control . . . . . . . . . . . . . . . . . . . . . . . 7-34 [1]
7.2.8.1 Dynamic Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 [1]
7.2.8.2 Margin Check Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35 [1]
7.2.9 Flash Interrupt Generation and Control . . . . . . . . . . . . . . . . . . . . . 7-36 [1]
7.2.10 Flash Power Supply, Power Saving and Reset . . . . . . . . . . . . . . . 7-38 [1]

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Table of Contents

7.2.10.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 [1]

7.2.10.2 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 [1]
7.2.10.3 Shut-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 [1]
7.2.10.4 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39 [1]
7.2.11 Flash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 [1]
7.2.11.1 Flash and PMU Module Identification Registers . . . . . . . . . . . . 7-41 [1]
7.2.11.2 Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43 [1]
7.2.11.3 Margin Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 [1]
7.2.11.4 Flash Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53 [1]
7.2.11.5 Protection Configuration Registers . . . . . . . . . . . . . . . . . . . . . . 7-59 [1]
7.3 Emulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-61 [1]
8 Data Memory Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1]
8.1 DLMB/PLMB Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 [1]
8.2 SBRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 [1]
8.3 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 [1]
8.4 Parity Protection for DMU Memories . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 [1]
8.5 Data Access Overlay Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 [1]
8.5.1 Internal Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 [1]
8.5.2 Emulation Memory Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 [1]
8.5.3 Switching between Internal and Emulation Memory Overlay . . . . . 8-7 [1]
8.5.4 Region Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 [1]
8.5.5 Access Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 [1]
8.6 Program Local Memory Bus Interface (LMI) . . . . . . . . . . . . . . . . . . . . 8-8 [1]
8.6.1 Data Read Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 [1]
8.7 DMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 [1]
9 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]
9.1 How to Read the Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]
9.2 Contents of the Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]
9.3 Address Map of the FPI Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 [1]
9.3.1 Segments 0 to 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 [1]
9.3.2 Segment 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]
9.4 Address Map of the Program Local Memory Bus (PLMB) . . . . . . . . . 9-15 [1]
9.5 Address Map of the Data Local Memory Bus (DLMB) . . . . . . . . . . . . 9-19 [1]
9.6 Memory Module Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 [1]
10 General Purpose I/O Ports and Peripheral I/O Lines . . . . . . . . . . 10-1 [1]
10.1 Basic Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]
10.2 Port Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 [1]
10.2.1 Port Input/Output Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 10-7 [1]
10.2.2 Pad Driver Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 [1]
10.2.3 Port Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 [1]
10.2.4 Port Output Modification Register . . . . . . . . . . . . . . . . . . . . . . . . 10-14 [1]

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10.2.5 Emergency Stop Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 [1]

10.2.6 Port Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 [1]
10.3 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 [1]
10.3.1 Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 [1]
10.3.2 Port 0 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 [1]
10.3.3 Port 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 [1]
10.3.3.1 Port 0 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-23 [1]
10.3.3.2 Port 0 Software Configuration Selection . . . . . . . . . . . . . . . . . 10-24 [1]
10.3.3.3 Reserved SWOPT Bits of SCU_SCLIR Register . . . . . . . . . . . 10-25 [1]
10.4 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 [1]
10.4.1 Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 [1]
10.4.2 Port 1 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 [1]
10.4.3 Port 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 [1]
10.4.3.1 Port 1 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-31 [1]
10.5 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 [1]
10.5.1 Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 [1]
10.5.2 Port 2 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 [1]
10.5.3 Port 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37 [1]
10.5.3.1 Port 2 Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37 [1]
10.5.3.2 Port 2 Output Modification Register . . . . . . . . . . . . . . . . . . . . . 10-37 [1]
10.5.3.3 Port 2 Input/Output Control Register 0 . . . . . . . . . . . . . . . . . . 10-38 [1]
10.5.3.4 Port 2 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38 [1]
10.5.3.5 Port 2 Emergency Stop Register . . . . . . . . . . . . . . . . . . . . . . . 10-38 [1]
10.5.3.6 Port 2 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-39 [1]
10.6 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40 [1]
10.6.1 Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40 [1]
10.6.2 Port 3 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-41 [1]
10.6.3 Port 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-45 [1]
10.6.3.1 Port 3 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-46 [1]
10.7 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47 [1]
10.7.1 Port 4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47 [1]
10.7.2 Port 4 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48 [1]
10.7.3 Port 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-51 [1]
10.7.3.1 Port 4 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-53 [1]
10.8 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-54 [1]
10.8.1 Port 5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-54 [1]
10.8.2 Port 5 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-55 [1]
10.8.3 Port 5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-57 [1]
10.8.3.1 Port 5 Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-57 [1]
10.8.3.2 Port 5 Output Modification Register . . . . . . . . . . . . . . . . . . . . . 10-57 [1]
10.8.3.3 Port 5 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-57 [1]
10.8.3.4 Port 5 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-58 [1]
10.9 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-59 [1]

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10.9.1 Port 6 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-59 [1]

10.9.2 Port 6 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-60 [1]
10.9.3 Port 6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-63 [1]
10.9.3.1 Port 6 Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-63 [1]
10.9.3.2 Port 6 Output Modification Register . . . . . . . . . . . . . . . . . . . . . 10-63 [1]
10.9.3.3 Port 6 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-63 [1]
10.9.3.4 Port 6 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-64 [1]
10.10 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65 [1]
10.10.1 Port 7 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65 [1]
10.10.2 Port 7 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-66 [1]
10.10.3 Port 7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-68 [1]
10.10.3.1 Port 7 Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-68 [1]
10.10.3.2 Port 7 Output Modification Register . . . . . . . . . . . . . . . . . . . . . 10-68 [1]
10.10.3.3 Port 7 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-68 [1]
10.10.3.4 Port 7 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-69 [1]
10.11 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-70 [1]
10.11.1 Port 8 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-70 [1]
10.11.2 Port 8 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-71 [1]
10.11.3 Port 8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-73 [1]
10.11.3.1 Port 8 Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-73 [1]
10.11.3.2 Port 8 Output Modification Register . . . . . . . . . . . . . . . . . . . . . 10-73 [1]
10.11.3.3 Port 8 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-73 [1]
10.11.3.4 Port 8 Emergency Stop Register . . . . . . . . . . . . . . . . . . . . . . . 10-73 [1]
10.11.3.5 Port 8 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-74 [1]
10.12 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-75 [1]
10.12.1 Port 9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-75 [1]
10.12.2 Port 9 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-76 [1]
10.12.3 Port 9 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-78 [1]
10.12.3.1 Port 9 Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-78 [1]
10.12.3.2 Port 9 Output Modification Register . . . . . . . . . . . . . . . . . . . . . 10-78 [1]
10.12.3.3 Port 9 Input/Output Control Register 8 . . . . . . . . . . . . . . . . . . 10-79 [1]
10.12.3.4 Port 9 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-79 [1]
10.12.3.5 Port 9 Emergency Stop Register . . . . . . . . . . . . . . . . . . . . . . . 10-79 [1]
10.12.3.6 Port 9 Pad Driver Mode Register and Pad Classes . . . . . . . . . 10-80 [1]
10.13 Port 10 (Hardware Select Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-81 [1]
10.13.1 Port 10 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-81 [1]
10.13.2 Port 10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-82 [1]
10.13.2.1 Port 10 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-82 [1]
10.14 Dedicated Peripheral I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-83 [1]
10.14.1 Dedicated I/O Lines for SSC0 and SSC1 . . . . . . . . . . . . . . . . . . 10-83 [1]
10.14.2 LVDS Outputs of MSC0 and MSC1 . . . . . . . . . . . . . . . . . . . . . . . 10-85 [1]

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11 Peripheral Control Processor (PCP) . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]

11.1 Peripheral Control Processor Overview . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]
11.2 PCP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 [1]
11.2.1 PCP Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 [1]
11.2.2 PCP Code Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 [1]
11.2.3 PCP Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 [1]
11.2.4 FPI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 [1]
11.2.5 PCP Interrupt Control Unit and Service Request Nodes . . . . . . . 11-5 [1]
11.3 PCP Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 [1]
11.3.1 General Purpose Register Set of the PCP . . . . . . . . . . . . . . . . . . 11-6 [1]
11.3.1.1 Register R0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1]
11.3.1.2 Registers R1, R2, and R3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1]
11.3.1.3 Registers R4 and R5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1]
11.3.1.4 Register R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 [1]
11.3.1.5 Register R7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 [1]
11.3.2 Contexts and Context Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 [1]
11.3.2.1 Context Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 [1]
11.3.2.2 Context Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 [1]
11.3.2.3 Context Restore Operation for CR6 and CR7 . . . . . . . . . . . . . 11-17 [1]
11.3.2.4 Context Save Operation for CR6 and CR7 . . . . . . . . . . . . . . . 11-21 [1]
11.3.2.5 Initialization of the Contexts . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 [1]
11.3.2.6 Context Save Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 [1]
11.3.3 Channel Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 [1]
11.3.3.1 Channel Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 [1]
11.3.3.2 Channel Resume Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 [1]
11.4 PCP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 [1]
11.4.1 PCP Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 [1]
11.4.2 Channel Invocation and Context Restore Operation . . . . . . . . . . 11-28 [1]
11.4.3 Channel Exit and Context Save Operation . . . . . . . . . . . . . . . . . 11-29 [1]
11.4.3.1 Normal Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 [1]
11.4.3.2 Error Condition Channel Exit . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 [1]
11.4.3.3 Debug Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 [1]
11.5 PCP Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 [1]
11.5.1 Issuing Service Requests to CPU or PCP . . . . . . . . . . . . . . . . . . 11-32 [1]
11.5.2 PCP Interrupt Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 [1]
11.5.3 PCP Service Request Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 [1]
11.5.4 Issuing PCP Service Requests . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 [1]
11.5.4.1 Service Request on EXIT Instruction . . . . . . . . . . . . . . . . . . . . 11-35 [1]
11.5.4.2 Service Request on Suspension of Interrupt . . . . . . . . . . . . . . 11-35 [1]
11.5.4.3 Service Request on Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 [1]
11.5.4.4 Queue Full Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 [1]
11.6 PCP Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 [1]
11.6.1 Enforced PRAM Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 [1]

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11.6.2 Channel Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 [1]

11.6.3 Invalid Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 [1]
11.6.4 Instruction Address Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 [1]
11.7 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40 [1]
11.7.1 DMA Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40 [1]
11.7.2 Load and Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 [1]
11.7.3 Arithmetic and Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . 11-42 [1]
11.7.4 Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 [1]
11.7.5 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 [1]
11.7.6 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 [1]
11.7.6.1 FPI Bus Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 [1]
11.7.6.2 PRAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 [1]
11.7.6.3 Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 [1]
11.7.6.4 Flow Control Destination Addressing . . . . . . . . . . . . . . . . . . . . 11-46 [1]
11.8 Accessing PCP Resources from the FPI Bus . . . . . . . . . . . . . . . . . 11-48 [1]
11.8.1 Access to the PCP Control Registers . . . . . . . . . . . . . . . . . . . . . 11-48 [1]
11.8.2 Access to the PRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 [1]
11.8.3 Access to the CMEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49 [1]
11.9 Debugging the PCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50 [1]
11.10 PCP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-52 [1]
11.10.1 Module Identification Register, PCP_ID . . . . . . . . . . . . . . . . . . . 11-54 [1]
11.10.2 PCP Clock Control Register, PCP_CLC . . . . . . . . . . . . . . . . . . . 11-55 [1]
11.10.3 PCP Control and Status Register, PCP_CS . . . . . . . . . . . . . . . . 11-56 [1]
11.10.4 PCP Error/Debug Status Register, PCP_ES . . . . . . . . . . . . . . . . 11-59 [1]
11.10.5 PCP Interrupt Control Register, PCP_ICR . . . . . . . . . . . . . . . . . 11-61 [1]
11.10.6 PCP Interrupt Threshold Register, PCP_ITR . . . . . . . . . . . . . . . 11-63 [1]
11.10.7 PCP Interrupt Configuration Register, PCP_ICON . . . . . . . . . . . 11-64 [1]
11.10.8 PCP Stall Status Register, PCP_SSR . . . . . . . . . . . . . . . . . . . . . 11-66 [1]
11.10.9 PCP Service Request Control Registers, PCP_SRC[1:0] . . . . . . 11-67 [1]
11.10.10 PCP Service Request Control Registers, PCP_SRC[3:2] . . . . . . 11-68 [1]
11.10.11 PCP Service Request Control Registers, PCP_SRC[8:4] . . . . . . 11-69 [1]
11.10.12 PCP Service Request Control Registers, PCP_SRC[11:9] . . . . . 11-70 [1]
11.11 PCP Instruction Set Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-72 [1]
11.11.1 Instruction Codes and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-72 [1]
11.11.1.1 Conditional Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-73 [1]
11.11.1.2 Instruction Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-74 [1]
11.11.2 Counter Operation for COPY Instruction . . . . . . . . . . . . . . . . . . . 11-77 [1]
11.11.3 Counter Operation for BCOPY Instruction . . . . . . . . . . . . . . . . . . 11-78 [1]
11.11.4 Divide and Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 11-79 [1]
11.11.5 ADD, 32-Bit Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-80 [1]
11.11.6 BCOPY, DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-81 [1]
11.11.7 AND, 32-Bit Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-82 [1]
11.11.8 CHKB, Check Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-83 [1]

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11.11.9 CLR, Clear Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-83 [1]

11.11.10 COMP, 32-Bit Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-84 [1]
11.11.11 COPY, DMA Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-85 [1]
11.11.12 DEBUG, Debug Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-86 [1]
11.11.13 DINIT, Divide Initialization Instruction . . . . . . . . . . . . . . . . . . . . . 11-87 [1]
11.11.14 DSTEP, Divide Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-88 [1]
11.11.15 INB, Insert Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-88 [1]
11.11.16 EXIT, Exit Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-89 [1]
11.11.17 JC, Jump Conditionally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-90 [1]
11.11.18 JL, Jump Long Unconditional . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-91 [1]
11.11.19 LD, Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-91 [1]
11.11.20 LDL, Load 16-bit Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-93 [1]
11.11.21 Multiply Initialization Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 11-93 [1]
11.11.22 MOV, Move Register to Register . . . . . . . . . . . . . . . . . . . . . . . . . 11-94 [1]
11.11.23 Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-95 [1]
11.11.24 NEG, Negate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-96 [1]
11.11.25 NOP, No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-96 [1]
11.11.26 NOT, Logical NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-96 [1]
11.11.27 OR, Logical OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-97 [1]
11.11.28 PRI, Prioritize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-98 [1]
11.11.29 PRAM Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-99 [1]
11.11.30 RL, Rotate Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-100 [1]
11.11.31 RR, Rotate Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-100 [1]
11.11.32 SET, Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-101 [1]
11.11.33 SHL, Shift Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-101 [1]
11.11.34 SHR, Shift Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-102 [1]
11.11.35 ST, Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-103 [1]
11.11.36 SUB, 32-Bit Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-104 [1]
11.11.37 XCH, Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-105 [1]
11.11.38 XOR, 32-Bit Logical Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . 11-106 [1]
11.11.39 Flag Updates of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-107 [1]
11.11.40 Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-108 [1]
11.12 Programming of the PCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-112 [1]
11.12.1 Initial PC of a channel program . . . . . . . . . . . . . . . . . . . . . . . . . 11-112 [1]
11.12.1.1 Channel Entry Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-112 [1]
11.12.1.2 Channel Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113 [1]
11.12.2 Channel Management for Small and Minimum Contexts . . . . . 11-114 [1]
11.12.3 Unused Registers as Globals or Constants . . . . . . . . . . . . . . . . 11-114 [1]
11.12.4 Dispatch of Low Priority Tasks . . . . . . . . . . . . . . . . . . . . . . . . . 11-115 [1]
11.12.5 Code Reuse Across Channels (Call and Return) . . . . . . . . . . . 11-115 [1]
11.12.6 Case-like Code Switches (Computed Go-To) . . . . . . . . . . . . . . 11-116 [1]
11.12.7 Simple DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-116 [1]
11.12.7.1 COPY Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-116 [1]

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11.12.7.2 BCOPY Instruction (Burst Copy) . . . . . . . . . . . . . . . . . . . . . . 11-117 [1]

11.13 PCP Programming Notes and Tips . . . . . . . . . . . . . . . . . . . . . . . . 11-118 [1]
11.13.1 Notes on PCP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-118 [1]
11.13.2 General Purpose Register Use . . . . . . . . . . . . . . . . . . . . . . . . . 11-119 [1]
11.13.3 Use of Channel Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-120 [1]
11.13.3.1 Dynamic Interrupt Masking . . . . . . . . . . . . . . . . . . . . . . . . . . 11-120 [1]
11.13.3.2 Control of Channel Priority (CPPN) . . . . . . . . . . . . . . . . . . . . 11-120 [1]
11.13.4 Implementing Divide Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 11-122 [1]
11.13.5 Implementing Multiply Algorithms . . . . . . . . . . . . . . . . . . . . . . . 11-123 [1]
11.14 Implementation of the PCP in the TC1796 . . . . . . . . . . . . . . . . . . 11-125 [1]
11.14.1 PCP Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-125 [1]
11.14.2 Parity Protection for PCP Memories . . . . . . . . . . . . . . . . . . . . . 11-125 [1]
11.14.3 PCP Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-126 [1]
11.14.4 BCOPY Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-127 [1]
12 Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1]
12.1 DMA Controller Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 [1]
12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 [1]
12.1.2 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 [1]
12.1.3 DMA Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 [1]
12.1.4 DMA Channel Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 [1]
12.1.4.1 Shadowed Source or Destination Address . . . . . . . . . . . . . . . . 12-6 [1]
12.1.4.2 DMA Channel Request Control . . . . . . . . . . . . . . . . . . . . . . . . 12-10 [1]
12.1.4.3 DMA Channel Operation Modes . . . . . . . . . . . . . . . . . . . . . . . 12-11 [1]
12.1.4.4 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 [1]
12.1.4.5 Channel Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 [1]
12.1.4.6 Transfer Count and Move Count . . . . . . . . . . . . . . . . . . . . . . . 12-17 [1]
12.1.4.7 Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 [1]
12.1.5 Transaction Control Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 [1]
12.1.6 Bus Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 [1]
12.1.7 On-Chip Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 [1]
12.1.7.1 Hard-suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 [1]
12.1.7.2 Soft-suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 [1]
12.1.7.3 Break Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24 [1]
12.1.7.4 Trace Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25 [1]
12.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 [1]
12.1.8.1 Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 [1]
12.1.8.2 Transaction Lost Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 [1]
12.1.8.3 Move Engine Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 [1]
12.1.8.4 Wrap Buffer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 [1]
12.1.8.5 Interrupt Request Compressor . . . . . . . . . . . . . . . . . . . . . . . . 12-33 [1]
12.1.9 Pattern Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34 [1]
12.1.9.1 Pattern Compare Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35 [1]

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12.1.9.2 Pattern Detection for 8-bit Data Width . . . . . . . . . . . . . . . . . . . 12-36 [1]

12.1.9.3 Pattern Detection for 16-bit Data Width . . . . . . . . . . . . . . . . . . 12-37 [1]
12.1.9.4 Pattern Detection for 32-bit Data Width . . . . . . . . . . . . . . . . . . 12-39 [1]
12.1.9.5 Access Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40 [1]
12.2 DMA Module Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 [1]
12.2.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45 [1]
12.2.2 General Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . 12-51 [1]
12.2.3 Move Engine Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-69 [1]
12.2.4 Channel Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . 12-76 [1]
12.2.5 Channel Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-88 [1]
12.3 DMA Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-91 [1]
12.3.1 DMA Request Wiring Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-92 [1]
12.3.2 Access Protection Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 12-98 [1]
12.3.3 Implementation-specific DMA Registers . . . . . . . . . . . . . . . . . . 12-103 [1]
12.3.3.1 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-105 [1]
12.3.3.2 DMA Service Request Control Registers . . . . . . . . . . . . . . . . 12-106 [1]
12.3.3.3 MLI Service Request Control Registers . . . . . . . . . . . . . . . . . 12-107 [1]
12.3.3.4 System Interrupt Service Request Control Register . . . . . . . 12-108 [1]
12.3.4 DMA Controller Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . 12-109 [1]
12.4 Memory Checker Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-110 [1]
12.4.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-110 [1]
12.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-111 [1]
12.4.2.1 Memory Checker Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 12-112 [1]
13 LMB External Bus Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1]
13.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 [1]
13.2 EBU Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 [1]
13.2.1 Data Bus, D[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 [1]
13.2.2 Address Bus, A[23:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 [1]
13.2.3 Chip Selects, CS[3:0], CSCOMB . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 [1]
13.2.4 Burst Flash Clock Output/Input, BFCLKO/BFCLKI . . . . . . . . . . . . 13-4 [1]
13.2.5 Read/Write Control Lines, RD, RD/WR and MR/W . . . . . . . . . . . . 13-4 [1]
13.2.6 Address Valid, ADV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 [1]
13.2.7 Byte Controls, BC[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 [1]
13.2.8 Wait Input, WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 [1]
13.2.9 Burst Address Advance, BAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 [1]
13.2.10 Bus Arbitration Signals, HOLD, HLDA, and BREQ . . . . . . . . . . . . 13-6 [1]
13.2.11 EBU Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 [1]
13.3 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 [1]
13.3.1 External Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 [1]
13.3.2 Arbitration Signals and Parameters . . . . . . . . . . . . . . . . . . . . . . . . 13-7 [1]
13.3.3 Arbitration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 [1]
13.3.3.1 No Bus Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 [1]

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13.3.3.2 Sole Master Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 [1]

13.3.3.3 Arbiter Mode Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 [1]
13.3.3.4 “Participant Mode” Arbitration Mode . . . . . . . . . . . . . . . . . . . . 13-14 [1]
13.3.4 Arbitration Input Signal Sampling . . . . . . . . . . . . . . . . . . . . . . . . 13-17 [1]
13.3.5 Locking the External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 [1]
13.3.6 Reaction to an PLMB Access to the External Bus . . . . . . . . . . . . 13-18 [1]
13.3.6.1 Pending Access Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 [1]
13.4 Start-Up/Boot Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 [1]
13.4.1 Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 [1]
13.4.2 Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 [1]
13.4.3 External Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 [1]
13.4.3.1 Boot Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 [1]
13.4.3.2 Boot Configuration Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 [1]
13.5 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 [1]
13.5.1 External Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26 [1]
13.5.2 Chip Select Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28 [1]
13.5.3 Address Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30 [1]
13.5.4 Access Parameter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35 [1]
13.5.5 Little-/Big-Endian Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . 13-36 [1]
13.5.6 PLMB Bus Width Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-37 [1]
13.5.7 Address Alignment During Bus Accesses . . . . . . . . . . . . . . . . . . 13-38 [1]
13.6 PLMB Data Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39 [1]
13.6.1 Data Read Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39 [1]
13.6.2 Code Prefetch Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40 [1]
13.6.3 Data Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40 [1]
13.7 Standard Access Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-41 [1]
13.7.1 Address Phase (AP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-41 [1]
13.7.2 Command Delay Phase (CD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-43 [1]
13.7.3 Command Phase (CP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-43 [1]
13.7.4 Data Hold Phase (DH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-45 [1]
13.7.5 Burst Phase (BP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-46 [1]
13.7.6 Recovery Phase (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-47 [1]
13.7.7 Multiplication Factor for Access Phase Length . . . . . . . . . . . . . . 13-49 [1]
13.8 Asynchronous Read/Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . 13-50 [1]
13.8.1 Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50 [1]
13.8.2 Demultiplexed Device Configurations . . . . . . . . . . . . . . . . . . . . . 13-51 [1]
13.8.3 Standard Asynchronous Access Phases . . . . . . . . . . . . . . . . . . . 13-53 [1]
13.8.4 Programmable Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-53 [1]
13.8.5 Accesses to Demultiplexed Devices . . . . . . . . . . . . . . . . . . . . . . 13-55 [1]
13.8.6 Dynamic Command Delay and Wait State Insertion . . . . . . . . . . 13-57 [1]
13.8.6.1 External Extension of the Command Phase by WAIT . . . . . . . 13-57 [1]
13.8.6.2 Interfacing to INTEL-style Devices . . . . . . . . . . . . . . . . . . . . . 13-61 [1]
13.8.6.3 Interfacing to Motorola-style Devices . . . . . . . . . . . . . . . . . . . . 13-63 [1]

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13.9 Burst Mode Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-65 [1]

13.9.1 Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-65 [1]
13.9.2 Burst Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . 13-66 [1]
13.9.3 Burst Mode Access Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-68 [1]
13.9.4 Programmable Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-68 [1]
13.9.5 Support for two Burst Flash Device Types . . . . . . . . . . . . . . . . . 13-71 [1]
13.9.6 BFCLKO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-71 [1]
13.9.7 BFCLKI Input and Burst Flash Clock Feedback . . . . . . . . . . . . . 13-72 [1]
13.9.8 Burst Length Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-73 [1]
13.9.9 Control of ADV and BAA Delays During Burst Flash Access . . . 13-73 [1]
13.9.10 Burst Flash Access Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-74 [1]
13.9.11 External Cycle Control via the WAIT Input . . . . . . . . . . . . . . . . . 13-75 [1]
13.9.11.1 Wait for Page Load Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-76 [1]
13.9.11.2 Terminate and Start New Burst Mode . . . . . . . . . . . . . . . . . . . 13-77 [1]
13.9.12 Termination of a Burst Mode Read Access . . . . . . . . . . . . . . . . . 13-78 [1]
13.10 EBU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-79 [1]
13.10.1 Identification Register, ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-81 [1]
13.10.2 Clock Control Register, CLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-82 [1]
13.10.3 Configuration Register, CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-83 [1]
13.10.4 Burst Flash Control Register, BFCON . . . . . . . . . . . . . . . . . . . . . 13-86 [1]
13.10.5 Address Select Register, ADDRSELx . . . . . . . . . . . . . . . . . . . . . 13-90 [1]
13.10.6 Bus Configuration Register, BUSCONx . . . . . . . . . . . . . . . . . . . . 13-92 [1]
13.10.7 Bus Access Parameter Register, BUSAPx . . . . . . . . . . . . . . . . . 13-97 [1]
13.10.8 Emulator Address Select Register, EMUAS . . . . . . . . . . . . . . . 13-101 [1]
13.10.9 Emulator Bus Configuration Register, EMUBC . . . . . . . . . . . . . 13-102 [1]
13.10.10 Emulator Bus Access Parameter Register, EMUBAP . . . . . . . . 13-106 [1]
13.10.11 Emulator Overlay Register, EMUOVL . . . . . . . . . . . . . . . . . . . . 13-110 [1]
13.10.12 Test/Control Configuration Register, USERCON . . . . . . . . . . . 13-111 [1]
14 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [1]
14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [1]
14.2 Service Request Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 [1]
14.2.1 Service Request Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 14-3 [1]
14.2.1.1 General Service Request Control Register Layout . . . . . . . . . . 14-4 [1]
14.2.1.2 Request Set and Clear Bits (SETR, CLRR) . . . . . . . . . . . . . . . . 14-5 [1]
14.2.1.3 Enable Bit (SRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 [1]
14.2.1.4 Service Request Flag (SRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 [1]
14.2.1.5 Type-Of-Service Control (TOS) . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 [1]
14.2.1.6 Service Request Priority Number (SRPN) . . . . . . . . . . . . . . . . . 14-7 [1]
14.3 Interrupt Control Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 [1]
14.3.1 Interrupt Control Unit (ICU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 [1]
14.3.1.1 ICU Interrupt Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . 14-8 [1]
14.3.1.2 Operation of the Interrupt Control Unit (ICU) . . . . . . . . . . . . . . 14-10 [1]

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14.3.2 PCP Interrupt Control Unit (PICU) . . . . . . . . . . . . . . . . . . . . . . . . 14-11 [1]

14.4 Arbitration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 [1]
14.4.1 Controlling the Number of Arbitration Cycles . . . . . . . . . . . . . . . . 14-12 [1]
14.4.2 Controlling the Duration of Arbitration Cycles . . . . . . . . . . . . . . . 14-13 [1]
14.5 Entering an Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . 14-13 [1]
14.6 Exiting an Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . 14-14 [1]
14.7 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 [1]
14.8 Usage of the TC1796 Interrupt System . . . . . . . . . . . . . . . . . . . . . . 14-18 [1]
14.8.1 Spanning Interrupt Service Routines Across Vector Entries . . . . 14-18 [1]
14.8.2 Configuring Ordinary Interrupt Service Routines . . . . . . . . . . . . . 14-19 [1]
14.8.3 Interrupt Priority Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 [1]
14.8.4 Splitting Interrupt Service Across Different Priority Levels . . . . . 14-20 [1]
14.8.5 Using different Priorities for the same Interrupt Source . . . . . . . . 14-21 [1]
14.8.6 Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 [1]
14.8.7 Software-Initiated Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 [1]
14.8.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 [1]
14.9 Service Request Node Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 [1]
14.10 Non-Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 [1]
14.10.1 External NMI Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 [1]
14.10.2 Phase-Locked Loop NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 [1]
14.10.3 Watchdog Timer NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 [1]
14.10.4 SRAM Parity Error NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 [1]
14.10.5 NMI Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 [1]
14.10.6 NMI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 [1]
15 System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [1]
15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [1]
15.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [1]
15.2.1 Resolution and Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 [1]
15.2.2 Compare Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 [1]
15.2.3 Compare Match Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 [1]
15.3 Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 [1]
15.3.1 General Module Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 [1]
15.3.2 Timer/Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [1]
15.3.3 Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 [1]
15.3.4 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 [1]
16 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [1]
16.1 Watchdog Timer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [1]
16.2 Features of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 [1]
16.3 The Endinit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [1]
16.4 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 [1]
16.4.1 WDT Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 [1]
16.4.2 Operating Modes of the Watchdog Timer . . . . . . . . . . . . . . . . . . . 16-7 [1]

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16.4.2.1 Time-Out Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 [1]

16.4.2.2 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 [1]
16.4.2.3 Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 [1]
16.4.2.4 Prewarning Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 [1]
16.4.3 Password Access to WDT_CON0 . . . . . . . . . . . . . . . . . . . . . . . . 16-10 [1]
16.4.4 Modify Access to WDT_CON0 . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 [1]
16.4.5 Term Definitions for WDT_CON0 Accesses . . . . . . . . . . . . . . . . 16-12 [1]
16.4.6 Detailed Descriptions of the WDT Modes . . . . . . . . . . . . . . . . . . 16-13 [1]
16.4.6.1 Time-Out Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 [1]
16.4.6.2 Normal Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 [1]
16.4.6.3 Disable Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 [1]
16.4.6.4 Prewarning Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 [1]
16.4.6.5 WDT Operation During Power-Saving Modes . . . . . . . . . . . . . 16-17 [1]
16.4.6.6 WDT Operation in OCDS Suspend Mode . . . . . . . . . . . . . . . . 16-17 [1]
16.4.7 Determining WDT Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 [1]
16.4.7.1 Time-out Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 [1]
16.4.7.2 Normal Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 [1]
16.4.7.3 WDT Period During Power-Saving Modes . . . . . . . . . . . . . . . 16-21 [1]
16.5 Handling the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 [1]
16.5.1 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 [1]
16.5.2 Re-opening Access to Critical System Registers . . . . . . . . . . . . 16-23 [1]
16.5.3 Servicing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 [1]
16.5.4 Handling the User-Definable Password Field . . . . . . . . . . . . . . . 16-24 [1]
16.5.5 Determining the Required Values for a WDT Access . . . . . . . . . 16-27 [1]
16.6 Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 [1]
16.6.1 Watchdog Timer Control Register 0 . . . . . . . . . . . . . . . . . . . . . . 16-29 [1]
16.6.2 Watchdog Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . 16-31 [1]
16.6.3 Watchdog Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 16-32 [1]
17 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [1]
17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [1]
17.2 OCDS Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [1]
17.2.1 TriCore CPU Level 1 OCDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [1]
17.2.1.1 Basic Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 [1]
17.2.1.2 Debug Event Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 [1]
17.2.1.3 Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 [1]
17.2.1.4 TriCore OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 [1]
17.2.2 PCP OCDS Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 [1]
17.2.3 BCU OCDS Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 [1]
17.2.4 DMA OCDS Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 [1]
17.3 OCDS Level 2 Debugging via Trace Port . . . . . . . . . . . . . . . . . . . . 17-10 [1]
17.3.1 TriCore CPU and PCP OCDS Level 2 Trace . . . . . . . . . . . . . . . . 17-10 [1]
17.3.2 DMA OCDS Level 2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [1]

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17.3.3 Concurrent Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 [1]

17.4 Debug Interface (Cerberus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 [1]
17.4.1 RW Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 [1]
17.4.2 Communication Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 [1]
17.4.3 Triggered Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 [1]
17.4.4 Multi Core Break Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 [1]
17.5 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [1]
17.6 Cerberus and JTAG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 [1]
18 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 [1]
18.1 Address Map of Segment 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 [1]
18.2 Registers Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 [1]

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Peripheral Units (Vol. 2 of 2)

19 Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . 19-1 [2]
19.1 ASC Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2]
19.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 [2]
19.1.2 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 [2]
19.1.3 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 [2]
19.1.3.1 Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 [2]
19.1.3.2 Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 [2]
19.1.3.3 Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 [2]
19.1.3.4 RXD/TXD Data Path Selection in Asynchronous Modes . . . . . . 19-8 [2]
19.1.4 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 [2]
19.1.4.1 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 [2]
19.1.4.2 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 [2]
19.1.4.3 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 [2]
19.1.5 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2]
19.1.5.1 Baud Rates in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . 19-13 [2]
19.1.5.2 Baud Rates in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . 19-16 [2]
19.1.6 Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . 19-17 [2]
19.1.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17 [2]
19.2 ASC Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 [2]
19.2.1 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 [2]
19.2.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21 [2]
19.2.3 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28 [2]
19.3 ASC0/ASC1 Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . 19-30 [2]
19.3.1 Interfaces of the ASC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30 [2]
19.3.2 ASC0/ASC1 Module Related External Registers . . . . . . . . . . . . 19-31 [2]
19.3.2.1 ASC0 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 19-32 [2]
19.3.2.2 Peripheral Input Select Registers . . . . . . . . . . . . . . . . . . . . . . 19-34 [2]
19.3.2.3 Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36 [2]
19.3.2.4 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40 [2]
19.3.3 DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-42 [2]
20 Synchronous Serial Interface (SSC) . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2]
20.1 SSC Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2]
20.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 [2]
20.1.2 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 [2]
20.1.2.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 [2]
20.1.2.2 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 [2]
20.1.2.3 Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 [2]
20.1.2.4 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 [2]
20.1.2.5 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 [2]
20.1.2.6 Transmit FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2]

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20.1.2.7 Receive FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 [2]

20.1.2.8 FIFO Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 [2]
20.1.2.9 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 [2]
20.1.2.10 Slave Select Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 [2]
20.1.2.11 Slave Select Output Generation Unit . . . . . . . . . . . . . . . . . . . . 20-21 [2]
20.1.2.12 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 [2]
20.2 SSC Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 [2]
20.2.1 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29 [2]
20.2.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 [2]
20.2.3 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45 [2]
20.3 SSC0/SSC1 Module Implementation . . . . . . . . . . . . . . . . . . . . . . . 20-46 [2]
20.3.1 Interfaces of the SSC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 20-46 [2]
20.3.2 SSC0/SSC1 Module Related External Registers . . . . . . . . . . . . 20-47 [2]
20.3.2.1 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-48 [2]
20.3.2.2 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-52 [2]
20.3.2.3 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-59 [2]
20.3.3 DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-60 [2]
21 Micro Second Channel (MSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]
21.1 MSC Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 [2]
21.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 [2]
21.1.2 Downstream Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 [2]
21.1.2.1 Frame Formats and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 [2]
21.1.2.2 Shift Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 [2]
21.1.2.3 Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14 [2]
21.1.2.4 Downstream Counter and Enable Signals . . . . . . . . . . . . . . . . 21-19 [2]
21.1.2.5 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-20 [2]
21.1.2.6 Abort of Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-20 [2]
21.1.3 Upstream Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 [2]
21.1.3.1 Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22 [2]
21.1.3.2 Parity Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22 [2]
21.1.3.3 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 [2]
21.1.3.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25 [2]
21.1.3.5 Spike Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 [2]
21.1.4 I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 [2]
21.1.4.1 Downstream Channel Output Control . . . . . . . . . . . . . . . . . . . 21-27 [2]
21.1.4.2 Upstream Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30 [2]
21.1.5 MSC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 [2]
21.1.5.1 Data Frame Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 [2]
21.1.5.2 Command Frame Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 [2]
21.1.5.3 Time Frame Finished Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 21-33 [2]
21.1.5.4 Receive Data Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-34 [2]
21.1.5.5 Interrupt Request Compressor . . . . . . . . . . . . . . . . . . . . . . . . 21-35 [2]

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21.2 MSC Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-36 [2]

21.2.1 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-38 [2]
21.2.2 Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-39 [2]
21.2.3 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-59 [2]
21.3 MSC Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-62 [2]
21.3.1 Interface Connections of the MSC Modules . . . . . . . . . . . . . . . . 21-62 [2]
21.3.2 MSC0/MSC1 Module-Related External Registers . . . . . . . . . . . . 21-64 [2]
21.3.3 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-65 [2]
21.3.3.1 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-67 [2]
21.3.3.2 Fractional Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-68 [2]
21.3.4 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-70 [2]
21.3.4.1 Input/Output Function Selection . . . . . . . . . . . . . . . . . . . . . . . 21-70 [2]
21.3.4.2 Pad Driver Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-74 [2]
21.3.5 On-Chip Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-76 [2]
21.3.5.1 EMGSTOPMSC Signal (from SCU) . . . . . . . . . . . . . . . . . . . . . 21-76 [2]
21.3.5.2 ALTINH and ALTINL Connections . . . . . . . . . . . . . . . . . . . . . . 21-76 [2]
21.3.5.3 DMA Controller Service Requests . . . . . . . . . . . . . . . . . . . . . . 21-77 [2]
21.3.6 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-78 [2]
22 Controller Area Network (MultiCAN) Controller . . . . . . . . . . . . . . 22-1 [2]
22.1 CAN Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 [2]
22.1.1 Addressing and Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 [2]
22.1.2 CAN Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 [2]
22.1.2.1 Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 [2]
22.1.2.2 Remote Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 [2]
22.1.2.3 Error Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 [2]
22.1.3 The Nominal Bit Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 [2]
22.1.4 Error Detection and Error Handling . . . . . . . . . . . . . . . . . . . . . . . . 22-9 [2]
22.1.5 Different CAN Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 [2]
22.1.6 TTCAN Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 [2]
22.1.6.1 Time Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 [2]
22.1.6.2 Basic Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 [2]
22.1.6.3 Global System Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 [2]
22.1.6.4 The System Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 [2]
22.1.6.5 Generation of the Network Time Unit (NTU) . . . . . . . . . . . . . . 22-13 [2]
22.1.6.6 Global Time Generation and Drift Correction . . . . . . . . . . . . . 22-13 [2]
22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14 [2]
22.2.1 MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 [2]
22.2.2 Time-Triggered Extension (TTCAN) . . . . . . . . . . . . . . . . . . . . . . 22-17 [2]
22.3 MultiCAN Kernel Functional Description . . . . . . . . . . . . . . . . . . . . . 22-18 [2]
22.3.1 Module Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18 [2]
22.3.2 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20 [2]
22.3.3 Port Input Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 [2]

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22.3.4 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 [2]

22.3.5 CAN Node Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 [2]
22.3.5.1 Bit Timing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 [2]
22.3.5.2 Bitstream Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25 [2]
22.3.5.3 Error Handling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26 [2]
22.3.5.4 CAN Frame Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27 [2]
22.3.5.5 CAN Node Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27 [2]
22.3.6 Message Object List Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 [2]
22.3.6.1 Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 [2]
22.3.6.2 List of Unallocated Elements . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30 [2]
22.3.6.3 Connection to the CAN Nodes . . . . . . . . . . . . . . . . . . . . . . . . . 22-30 [2]
22.3.6.4 List Command Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-31 [2]
22.3.7 CAN Node Analysis Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34 [2]
22.3.7.1 Analyze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34 [2]
22.3.7.2 Loop-Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34 [2]
22.3.7.3 Bit Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-35 [2]
22.3.8 Message Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-37 [2]
22.3.8.1 Receive Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . 22-37 [2]
22.3.8.2 Transmit Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . 22-38 [2]
22.3.9 Message Postprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-40 [2]
22.3.9.1 Message Object Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-40 [2]
22.3.9.2 Pending Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-42 [2]
22.3.10 Message Object Data Handling . . . . . . . . . . . . . . . . . . . . . . . . . . 22-44 [2]
22.3.10.1 Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-44 [2]
22.3.10.2 Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-47 [2]
22.3.11 Message Object Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-50 [2]
22.3.11.1 Standard Message Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-50 [2]
22.3.11.2 Single Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-50 [2]
22.3.11.3 Single Transmit Trial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-50 [2]
22.3.11.4 Message Object FIFO Structure . . . . . . . . . . . . . . . . . . . . . . . 22-51 [2]
22.3.11.5 Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-53 [2]
22.3.11.6 Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-54 [2]
22.3.11.7 Gateway Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-55 [2]
22.3.11.8 Foreign Remote Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-57 [2]
22.4 MultiCAN Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-58 [2]
22.4.1 Module Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-61 [2]
22.4.2 Global Module Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-62 [2]
22.4.3 CAN Node Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-73 [2]
22.4.4 Message Object Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-91 [2]
22.5 Time-Triggered Extension (TTCAN Controller) . . . . . . . . . . . . . . . 22-114 [2]
22.5.1 Generation of the Local Time . . . . . . . . . . . . . . . . . . . . . . . . . . 22-114 [2]
22.5.2 Automatic TUR Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-115 [2]
22.5.3 Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-115 [2]

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22.5.3.1 Local Time and Synchronization Marks . . . . . . . . . . . . . . . . . 22-115 [2]

22.5.3.2 Time Marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-116 [2]
22.5.3.3 Watch Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-117 [2]
22.5.4 Master Reference Mark (Level 2 only) . . . . . . . . . . . . . . . . . . . . 22-117 [2]
22.5.5 Transmit Enable Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-117 [2]
22.5.6 Local Offset and Global Time . . . . . . . . . . . . . . . . . . . . . . . . . . 22-118 [2]
22.5.7 Transmit Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-119 [2]
22.5.8 Reference Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-120 [2]
22.5.8.1 Differences to Normal CAN Messages . . . . . . . . . . . . . . . . . 22-120 [2]
22.5.8.2 Transmit Trigger for a Reference Message . . . . . . . . . . . . . . 22-121 [2]
22.6 TTCAN Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-123 [2]
22.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-123 [2]
22.6.2 Scheduler Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-124 [2]
22.6.2.1 Scheduler Entry Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-125 [2]
22.6.2.2 Scheduler Entry Type Description . . . . . . . . . . . . . . . . . . . . . 22-126 [2]
22.6.2.3 End of Scheduler Memory Entry . . . . . . . . . . . . . . . . . . . . . . 22-141 [2]
22.6.3 Setup of the Scheduler Entries . . . . . . . . . . . . . . . . . . . . . . . . . 22-142 [2]
22.6.4 Reading the Scheduler Entries . . . . . . . . . . . . . . . . . . . . . . . . . 22-142 [2]
22.6.4.1 Instructions During a Basic Cycle . . . . . . . . . . . . . . . . . . . . . 22-142 [2]
22.6.4.2 Instructions at the End of a Basic Cycle . . . . . . . . . . . . . . . . 22-143 [2]
22.6.5 Scheduler Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . 22-145 [2]
22.6.5.1 BCC and CSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-145 [2]
22.6.5.2 General Instruction Sequence Rules . . . . . . . . . . . . . . . . . . . 22-146 [2]
22.6.5.3 Scheduler Sequence Example . . . . . . . . . . . . . . . . . . . . . . . 22-147 [2]
22.7 TTCAN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-148 [2]
22.7.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-148 [2]
22.7.2 Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-148 [2]
22.7.3 Synchronization Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-149 [2]
22.7.4 Time Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-149 [2]
22.7.4.1 State of a Time Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-149 [2]
22.7.4.2 Strictly Time-Triggered Behavior . . . . . . . . . . . . . . . . . . . . . . 22-149 [2]
22.7.5 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-150 [2]
22.7.6 Application Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-150 [2]
22.7.7 MSC Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-151 [2]
22.7.8 TTCAN Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-152 [2]
22.8 TTCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-154 [2]
22.8.1 TTCAN Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-157 [2]
22.8.2 TTCAN Control / Status / Configuration Registers . . . . . . . . . . 22-169 [2]
22.8.3 Scheduler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-192 [2]
22.9 MultiCAN Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 22-199 [2]
22.9.1 Interfaces of the MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . 22-199 [2]
22.9.2 MultiCAN Module External Registers . . . . . . . . . . . . . . . . . . . . 22-200 [2]
22.9.3 Module Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-201 [2]

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22.9.3.1 Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-202 [2]

22.9.4 Port and I/O Line Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-205 [2]
22.9.4.1 Input/Output Function Selection in Ports . . . . . . . . . . . . . . . . 22-205 [2]
22.9.4.2 CAN Related Input/Output Control Registers . . . . . . . . . . . . 22-206 [2]
22.9.4.3 Node Receive Input Selection . . . . . . . . . . . . . . . . . . . . . . . . 22-207 [2]
22.9.4.4 Pad Output Driver Register . . . . . . . . . . . . . . . . . . . . . . . . . . 22-208 [2]
22.9.4.5 External CAN Time Trigger Inputs . . . . . . . . . . . . . . . . . . . . . 22-209 [2]
22.9.4.6 DMA Request Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-209 [2]
22.9.5 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-210 [2]
22.9.5.1 Service Request Control Registers . . . . . . . . . . . . . . . . . . . . 22-212 [2]
22.9.6 Parity Protection for CAN Memories . . . . . . . . . . . . . . . . . . . . . 22-213 [2]
22.9.6.1 CAN Module Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . 22-214 [2]
23 Micro Link Interface (MLI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [2]
23.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 [2]
23.1.1 General Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 [2]
23.1.1.1 MLI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 [2]
23.1.1.2 Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 [2]
23.1.1.3 MLI Communication Principles . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 [2]
23.1.2 MLI Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 [2]
23.1.2.1 General Frame Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11 [2]
23.1.2.2 Copy Base Address Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 [2]
23.1.2.3 Write Offset and Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 [2]
23.1.2.4 Optimized Write Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14 [2]
23.1.2.5 Discrete Read Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15 [2]
23.1.2.6 Optimized Read Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 [2]
23.1.2.7 Command Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17 [2]
23.1.2.8 Answer Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-18 [2]
23.1.3 Handshake Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-19 [2]
23.1.3.1 Handshake Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21 [2]
23.1.3.2 Error-free Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21 [2]
23.1.3.3 Ready Delay Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 [2]
23.1.3.4 Non-Acknowledge Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 [2]
23.1.4 Parity Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24 [2]
23.1.5 Address Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24 [2]
23.2 Module Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25 [2]
23.2.1 Frame Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25 [2]
23.2.1.1 Copy Base Address Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 [2]
23.2.1.2 Write/Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-28 [2]
23.2.1.3 Read Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-32 [2]
23.2.1.4 Answer Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-37 [2]
23.2.1.5 Command Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-39 [2]
23.2.2 General MLI Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-42 [2]

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23.2.2.1 Parity Check and Parity Error Indication . . . . . . . . . . . . . . . . . 23-42 [2]

23.2.2.2 Non-Acknowledge Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-45 [2]
23.2.2.3 Address Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-45 [2]
23.2.2.4 Automatic Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-46 [2]
23.2.2.5 Memory Access Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-47 [2]
23.2.2.6 Transmit Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-48 [2]
23.2.2.7 Transmission Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-48 [2]
23.2.3 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-49 [2]
23.2.3.1 Transmitter I/O Line Control . . . . . . . . . . . . . . . . . . . . . . . . . . 23-51 [2]
23.2.3.2 Receiver I/O Line Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-51 [2]
23.2.3.3 Connecting Several MLI Modules . . . . . . . . . . . . . . . . . . . . . . 23-53 [2]
23.2.4 MLI Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . 23-55 [2]
23.2.5 Transmitter Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-57 [2]
23.2.5.1 Parity/Time-out Error Event . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-58 [2]
23.2.5.2 Normal Frame Sent x Event . . . . . . . . . . . . . . . . . . . . . . . . . . 23-58 [2]
23.2.5.3 Command Frame Sent Events . . . . . . . . . . . . . . . . . . . . . . . . 23-59 [2]
23.2.6 Receiver Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-60 [2]
23.2.6.1 Discarded Read Answer Event . . . . . . . . . . . . . . . . . . . . . . . . 23-60 [2]
23.2.6.2 Memory Access Protection/Parity Error Event . . . . . . . . . . . . . 23-61 [2]
23.2.6.3 Normal Frame Received/Move Engine Terminated Event . . . 23-62 [2]
23.2.6.4 Interrupt Command Frame Event . . . . . . . . . . . . . . . . . . . . . . 23-63 [2]
23.2.6.5 Command Frame Received Event . . . . . . . . . . . . . . . . . . . . . . 23-64 [2]
23.2.7 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-65 [2]
23.2.8 Automatic Register Overwrite . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-66 [2]
23.3 Operating the MLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-67 [2]
23.3.1 Connection Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-68 [2]
23.3.2 Local Transmitter and Pipe Setup . . . . . . . . . . . . . . . . . . . . . . . . 23-69 [2]
23.3.3 Remote Receiver Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-69 [2]
23.3.4 Remote Transmitter and Local Receiver Setup . . . . . . . . . . . . . . 23-70 [2]
23.3.5 Delay Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-71 [2]
23.3.6 Connection to DMA Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . 23-73 [2]
23.3.7 Connection of MLI to SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-73 [2]
23.4 MLI Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-75 [2]
23.4.1 General Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-78 [2]
23.4.2 General Status/Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 23-81 [2]
23.4.3 Access Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-88 [2]
23.4.4 Transmitter Status/Control Registers . . . . . . . . . . . . . . . . . . . . . . 23-90 [2]
23.4.5 Transmitter Data/Address Registers . . . . . . . . . . . . . . . . . . . . . 23-101 [2]
23.4.6 Transmitter Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . 23-105 [2]
23.4.7 Receiver Status/Control Registers . . . . . . . . . . . . . . . . . . . . . . . 23-110 [2]
23.4.8 Receiver Data/Address Registers . . . . . . . . . . . . . . . . . . . . . . . 23-114 [2]
23.4.9 Receiver Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-117 [2]
23.5 Implementation of the MLI0/MLI1 in TC1796 . . . . . . . . . . . . . . . . . 23-124 [2]

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23.5.1 Interfaces of the MLI Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 23-124 [2]

23.5.2 MLI Module External Registers . . . . . . . . . . . . . . . . . . . . . . . . . 23-127 [2]
23.5.2.1 Automatic Register Overwrite . . . . . . . . . . . . . . . . . . . . . . . . 23-127 [2]
23.5.3 Module Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-128 [2]
23.5.4 Port Control and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 23-130 [2]
23.5.4.1 Input/Output Function Selection . . . . . . . . . . . . . . . . . . . . . . 23-130 [2]
23.5.4.2 Input/Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . 23-133 [2]
23.5.4.3 Pad Driver Characteristics Selection . . . . . . . . . . . . . . . . . . . 23-137 [2]
23.5.5 On-Chip Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-139 [2]
23.5.5.1 Service Request Output Connections . . . . . . . . . . . . . . . . . . 23-139 [2]
23.5.5.2 Break Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-140 [2]
23.5.6 Access Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-141 [2]
23.5.6.1 Fixed Address Range Definition . . . . . . . . . . . . . . . . . . . . . . 23-141 [2]
23.5.6.2 Programmable Address Sub-Range Definitions . . . . . . . . . . 23-143 [2]
23.5.7 MLI0/MLI1 Transfer Window Address Maps . . . . . . . . . . . . . . . 23-146 [2]
24 General Purpose Timer Array (GPTA) . . . . . . . . . . . . . . . . . . . . . . 24-1 [2]
24.1 GPTA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 [2]
24.1.1 Functionality of GPTA0 and GPTA1 . . . . . . . . . . . . . . . . . . . . . . . 24-3 [2]
24.1.2 Functionality of LTCA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 [2]
24.2 GPTA0/GPTA1 Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 [2]
24.2.1 GTPA Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 [2]
24.2.2 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 [2]
24.2.2.1 Filter and Prescaler Cell (FPC) . . . . . . . . . . . . . . . . . . . . . . . . 24-10 [2]
24.2.2.2 Phase Discrimination Logic (PDL) . . . . . . . . . . . . . . . . . . . . . . 24-19 [2]
24.2.2.3 Duty Cycle Measurement Unit (DCM) . . . . . . . . . . . . . . . . . . . 24-24 [2]
24.2.2.4 Digital Phase Locked Loop Cell (PLL) . . . . . . . . . . . . . . . . . . . 24-28 [2]
24.2.2.5 Clock Distribution Unit (CDU) . . . . . . . . . . . . . . . . . . . . . . . . . 24-35 [2]
24.2.3 Signal Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37 [2]
24.2.3.1 Global Timers (GT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37 [2]
24.2.3.2 Global Timer Cell (GTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-55 [2]
24.2.3.3 Local Timer Cell (LTC00 to LTC62) . . . . . . . . . . . . . . . . . . . . 24-67 [2]
24.2.3.4 Local Timer Cell LTC63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-79 [2]
24.2.3.5 LTC Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-86 [2]
24.2.4 Input/Output Line Sharing Unit (IOLS) . . . . . . . . . . . . . . . . . . . . . 24-90 [2]
24.2.4.1 FPC Input Line Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-94 [2]
24.2.4.2 GTC and LTC Output Multiplexer Selection . . . . . . . . . . . . . . 24-95 [2]
24.2.4.3 GTC Input Multiplexer Selection . . . . . . . . . . . . . . . . . . . . . . 24-100 [2]
24.2.4.4 LTC Input Multiplexer Selection . . . . . . . . . . . . . . . . . . . . . . . 24-105 [2]
24.2.4.5 Multiplexer Register Array Programming . . . . . . . . . . . . . . . . 24-110 [2]
24.2.5 Interrupt Sharing Unit (IS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-112 [2]
24.2.6 Pseudo Code Description of GPTA Kernel Functionality . . . . . . 24-115 [2]
24.2.6.1 FPC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-115 [2]

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System and Peripheral Units (Vol. 1 and 2)
Table of Contents

24.2.6.2 PDL-Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-121 [2]

24.2.6.3 DCM-Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-125 [2]
24.2.6.4 PLL-Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-128 [2]
24.2.6.5 GT-Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-130 [2]
24.2.6.6 GTC-Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-131 [2]
24.2.6.7 LTC-Algorithm for Cells 0 to 62 . . . . . . . . . . . . . . . . . . . . . . . 24-137 [2]
24.2.6.8 LTC Algorithm for Cell 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-144 [2]
24.2.7 Programming of a GPTA Module . . . . . . . . . . . . . . . . . . . . . . . . 24-148 [2]
24.3 GPTA0/1 Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-150 [2]
24.3.1 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-154 [2]
24.3.2 FPC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-155 [2]
24.3.3 Phase Discriminator Registers . . . . . . . . . . . . . . . . . . . . . . . . . 24-159 [2]
24.3.4 Duty Cycle Measurement Registers . . . . . . . . . . . . . . . . . . . . . 24-161 [2]
24.3.5 Digital Phase Locked Loop Registers . . . . . . . . . . . . . . . . . . . . 24-165 [2]
24.3.6 Global Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-170 [2]
24.3.7 Clock Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-173 [2]
24.3.8 Global Timer Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-175 [2]
24.3.9 Local Timer Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-180 [2]
24.3.10 I/O Sharing Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-191 [2]
24.3.11 Multiplexer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-194 [2]
24.3.12 Service Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-206 [2]
24.4 LTCA2 Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-217 [2]
24.4.1 Local Timer Cell (LTC00 to LTC62) . . . . . . . . . . . . . . . . . . . . . . 24-218 [2]
24.4.2 Input/Output Line Sharing Unit (IOLS) . . . . . . . . . . . . . . . . . . . . 24-218 [2]
24.4.2.1 Output Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-221 [2]
24.4.2.2 LTC Input Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . 24-225 [2]
24.4.2.3 Multiplexer Register Array Programming . . . . . . . . . . . . . . . . 24-229 [2]
24.4.3 Interrupt Sharing Unit (IS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-231 [2]
24.5 LTCA2 Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-233 [2]
24.5.1 Bit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-234 [2]
24.5.2 Service Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-234 [2]
24.5.3 Local Timer Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-234 [2]
24.5.4 Module Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . 24-235 [2]
24.5.5 I/O Sharing Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-236 [2]
24.5.6 Multiplexer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-239 [2]
24.5.6.1 Output Multiplexer Control Registers . . . . . . . . . . . . . . . . . . . 24-239 [2]
24.5.6.2 LTC Input Multiplexer Control Registers . . . . . . . . . . . . . . . . 24-243 [2]
24.6 GPTA Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-247 [2]
24.6.1 Interconnections of the GPTA0/GPTA1/LTCA2 Modules . . . . . 24-247 [2]
24.6.2 GPTA Module External Registers . . . . . . . . . . . . . . . . . . . . . . . 24-249 [2]
24.6.3 Port Control and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 24-250 [2]
24.6.3.1 I/O Group to Port Line Assignment . . . . . . . . . . . . . . . . . . . . 24-250 [2]
24.6.3.2 Input/Output Function Selection . . . . . . . . . . . . . . . . . . . . . . 24-251 [2]

User’s Manual L-28 V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)
Table of Contents

24.6.3.3 Pad Driver Characteristics Selection . . . . . . . . . . . . . . . . . . . 24-253 [2]

24.6.3.4 Emergency Control of GPTA Output Ports Lines . . . . . . . . . 24-255 [2]
24.6.4 On-Chip Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-256 [2]
24.6.4.1 Clock Bus Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-256 [2]
24.6.4.2 MSC Controller Connections . . . . . . . . . . . . . . . . . . . . . . . . . 24-257 [2]
24.6.4.3 GPTA Connections with SCU, MultiCAN, FADC, DMA, Ports 24-263 [2]
24.6.5 Module Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-265 [2]
24.6.5.1 Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-267 [2]
24.6.6 Limits of Cascading GTCs and LTCs . . . . . . . . . . . . . . . . . . . . 24-272 [2]
24.6.7 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-273 [2]
24.6.8 GPTA Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . 24-274 [2]
25 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 [2]
25.1 ADC Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 [2]
25.1.1 Analog Input Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 [2]
25.1.2 Conversion Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 [2]
25.1.2.1 Parallel Conversion Request Sources . . . . . . . . . . . . . . . . . . . . 25-5 [2]
25.1.2.2 Sequential Conversion Request Sources . . . . . . . . . . . . . . . . . 25-6 [2]
25.1.2.3 Parallel Conversion Request Source “Timer” . . . . . . . . . . . . . . 25-8 [2]
25.1.2.4 Parallel Conversion Request Source “External Event” . . . . . . 25-11 [2]
25.1.2.5 Parallel Conversion Request Source “Software” . . . . . . . . . . . 25-14 [2]
25.1.2.6 Parallel Conversion Request Source “Auto-Scan” . . . . . . . . . . 25-15 [2]
25.1.2.7 Sequential Conversion Request Source “Channel Injection” . . 25-21 [2]
25.1.2.8 Sequential Conversion Request Source “Queue” . . . . . . . . . . 25-25 [2]
25.1.3 Conversion Request Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . 25-29 [2]
25.1.3.1 Source Arbitration Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30 [2]
25.1.3.2 Arbitration Participation Flags . . . . . . . . . . . . . . . . . . . . . . . . . 25-30 [2]
25.1.3.3 Cancel Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-31 [2]
25.1.3.4 Clear of Pending Conversion Requests . . . . . . . . . . . . . . . . . . 25-31 [2]
25.1.3.5 Arbitration and Synchronized Injection . . . . . . . . . . . . . . . . . . 25-32 [2]
25.1.3.6 Arbitration Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32 [2]
25.1.4 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33 [2]
25.1.4.1 Conversion Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34 [2]
25.1.4.2 Conversion Timing Control (CTC and CPS) . . . . . . . . . . . . . . 25-34 [2]
25.1.4.3 Sample Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35 [2]
25.1.4.4 Power-Up Calibration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36 [2]
25.1.5 Reference Voltages (VAREF and VAGND) . . . . . . . . . . . . . . . . . . . . 25-37 [2]
25.1.6 Error through Overload Conditions . . . . . . . . . . . . . . . . . . . . . . . 25-38 [2]
25.1.7 Limit Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39 [2]
25.1.8 Expansion of Analog Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41 [2]
25.1.8.1 Inverse Current Injection (Overload) Behavior . . . . . . . . . . . . 25-42 [2]
25.1.8.2 On Resistance of the External Multiplexer . . . . . . . . . . . . . . . . 25-42 [2]
25.1.8.3 Timing of the External Multiplexer . . . . . . . . . . . . . . . . . . . . . . 25-42 [2]

User’s Manual L-29 V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)
Table of Contents

25.1.8.4 Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42 [2]

25.1.9 Service Request Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43 [2]
25.1.9.1 Channel Request Source Control . . . . . . . . . . . . . . . . . . . . . . 25-45 [2]
25.1.9.2 Parallel/Serial Request Source Control . . . . . . . . . . . . . . . . . . 25-46 [2]
25.1.9.3 Service Request Compressor . . . . . . . . . . . . . . . . . . . . . . . . . 25-47 [2]
25.1.9.4 Service Request Flag Control . . . . . . . . . . . . . . . . . . . . . . . . . 25-48 [2]
25.1.10 Synchronization of Two ADC Modules . . . . . . . . . . . . . . . . . . . . 25-49 [2]
25.1.10.1 Synchronized Injection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25-50 [2]
25.1.10.2 Status Information During Synchronized Conversion . . . . . . . 25-51 [2]
25.1.10.3 Master-Slave Functionality for Synchronized Injection . . . . . . 25-51 [2]
25.1.10.4 Conversion Timing during Synchronized Conversion . . . . . . . 25-54 [2]
25.1.10.5 Service Request Generation in Synchronized Injection . . . . . . 25-54 [2]
25.1.10.6 Example for Synchronized Injection . . . . . . . . . . . . . . . . . . . . 25-55 [2]
25.2 ADC0/ADC1 Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-57 [2]
25.2.1 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-59 [2]
25.2.2 Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-60 [2]
25.2.3 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-65 [2]
25.2.4 Queue Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-69 [2]
25.2.5 External Trigger Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-73 [2]
25.2.6 Auto-Scan Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-75 [2]
25.2.7 Other Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 25-78 [2]
25.2.8 Channel Inject Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-90 [2]
25.2.9 Software Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-92 [2]
25.2.10 Service Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-94 [2]
25.3 Implementation of ADC0/ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-100 [2]
25.3.1 Interface Connections of the ADC Modules . . . . . . . . . . . . . . . . 25-100 [2]
25.3.2 ADC0/ADC1 Module Related External Registers . . . . . . . . . . . 25-102 [2]
25.3.3 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-103 [2]
25.3.3.1 ADC Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 25-105 [2]
25.3.3.2 ADC Fractional Divider Register . . . . . . . . . . . . . . . . . . . . . . 25-106 [2]
25.3.4 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-108 [2]
25.3.4.1 Input/Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . 25-109 [2]
25.3.4.2 Pad Output Driver Characteristics Selection . . . . . . . . . . . . . 25-110 [2]
25.3.5 Analog Input Line to Analog Input Channel Connections . . . . . 25-111 [2]
25.3.6 On-Chip Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-113 [2]
25.3.6.1 Reference Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . 25-113 [2]
25.3.6.2 Request/Gating Input Signal Connections . . . . . . . . . . . . . . . 25-114 [2]
25.3.6.3 Service Request Output Lines . . . . . . . . . . . . . . . . . . . . . . . . 25-119 [2]
25.3.6.4 Service Request Control Registers . . . . . . . . . . . . . . . . . . . . 25-120 [2]
25.3.6.5 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-120 [2]
26 Fast Analog-to-Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . 26-1 [2]
26.1 FADC Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 [2]

User’s Manual L-30 V2.0, 2007-07

 TC1796
System and Peripheral Units (Vol. 1 and 2)
Table of Contents

26.1.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 [2]

26.1.1.1 Analog Input Stage Configurations . . . . . . . . . . . . . . . . . . . . . . 26-5 [2]
26.1.2 Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 [2]
26.1.3 Channel Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9 [2]
26.1.4 Channel Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11 [2]
26.1.5 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12 [2]
26.1.5.1 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12 [2]
26.1.5.2 Static Channel Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12 [2]
26.1.5.3 Dynamic Priority Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12 [2]
26.1.5.4 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13 [2]
26.1.5.5 Suspend Mode Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13 [2]
26.1.6 Data Reduction Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13 [2]
26.1.6.1 Filter Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15 [2]
26.1.6.2 Filter Block Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-16 [2]
26.1.6.3 Filter Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-19 [2]
26.1.6.4 Width of Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-20 [2]
26.1.7 Neighbor Channel Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21 [2]
26.1.8 Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-22 [2]
26.1.8.1 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23 [2]
26.1.8.2 Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23 [2]
26.1.9 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24 [2]
26.2 FADC Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 [2]
26.2.1 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-29 [2]
26.2.2 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30 [2]
26.2.3 Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-41 [2]
26.2.4 Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-48 [2]
26.3 Implementation of FADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-56 [2]
26.3.1 Interfaces of the FADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . 26-56 [2]
26.3.2 FADC Module Related External Registers . . . . . . . . . . . . . . . . . 26-57 [2]
26.3.3 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-58 [2]
26.3.3.1 Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-59 [2]
26.3.4 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-61 [2]
26.3.5 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-63 [2]
26.3.6 On-Chip Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-64 [2]
26.3.6.1 Analog Input Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-64 [2]
26.3.6.2 Trigger/Gating Source Input Connections . . . . . . . . . . . . . . . . 26-64 [2]
26.3.6.3 Service Request Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-65 [2]
Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L-1 [1+2]
Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L-16 [1+2]

User’s Manual L-31 V2.0, 2007-07

 TC1796
System Units (Vol. 1 of 2)
Introduction

1 Introduction
This User’s Manual describes the Infineon TC1796, a 32-bit microcontroller DSP based
on the Infineon TriCore Architecture.

1.1 About this Document

This document is designed to be read primarily by design engineers and software
engineers who need a detailed description of the interactions of the TC1796 functional
units, registers, instructions, and exceptions.
This TC1796 User’s Manual describes the features of the TC1796 with respect to the
TriCore Architecture. Where the TC1796 directly implements TriCore architectural
functions, this manual simply refers to those functions as features of the TC1796. In all
cases where this manual describes a TC1796 feature without referring to the TriCore
Architecture, this means that the TC1796 is a direct implementation of the TriCore
Architecture.
Where the TC1796 implements a subset of TriCore architectural features, this manual
describes the TC1796 implementation, and then describes how it differs from the TriCore
Architecture. For example, where the TriCore Architecture specifies up to four Memory
Protection Register Sets, the TC1796 implements but two. Such differences between the
TC1796 and the TriCore Architecture are documented in the text covering each such
subject.

1.1.1 Related Documentations

A complete description of the TriCore architecture is found in the document entitled
“TriCore Architecture Manual”. The architecture of the TC1796 is described separately
this way because of the configurable nature of the TriCore specification: Different
versions of the architecture may contain a different mix of systems components. The
TriCore architecture, however, remains constant across all derivative designs in order to
preserve compatibility.
In addition to this “TC1796 System Units (Vol. 1 of 2) User’s Manual”, a second
document, the “TC1796 Peripheral Units (Vol. 2 of 2) User’s Manual”, is available. These
two User’s Manuals together with the “TriCore Architecture Manual” are required to
understand the complete TC1796 microcontroller functionality.
Implementation-specific details of the TC1796 such as electrical characteristics and
timing parameters are defined in the “TC1796 Data Sheet”.

1.1.2 Text Conventions

This document uses the following text conventions for named components of the
TC1796:

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• Functional units of the TC1796 are given in plain UPPER CASE. For example: “The
EBU provides an interface to external peripherals”.
• Pins using negative logic are indicated by an overline. For example: “The external
reset pin, HDRST, has a dual function.”.
• Bit fields and bits in registers are in general referenced as “Register name.Bit field”
or “Register name.Bit”. For example: “The Current CPU Priority Number bit field
ICR.CCPN is cleared”. Most of the register names contain a module name prefix,
separated by a underscore character “_” from the real register name (for example,
“ASC0_CON”, where “ASC0” is the module name prefix, and “CON” is the kernel
register name). In chapters describing the kernels of the peripheral modules, the
registers are mainly referenced with their kernel register names. The peripheral
module implementation sections mainly refer to the real register names with module
prefixes.
• Variables used to describe sets of processing units or registers appear in mixed
upper-and-lower-case font. For example, register name “MSGCFGn” refers to
multiple “MSGCFG” registers with variable n. The bounds of the variables are always
given where the register expression is first used (for example, “n = 31-0”), and are
repeated as needed in the rest of the text.
• The default radix is decimal. Hexadecimal constants are suffixed with a subscript
letter “H”, as in 100H. Binary constants are suffixed with a subscript letter “B”, as in
111B.
• When the extent of register fields, groups of signals, or groups of pins are collectively
named in the body of the document, they are given as “NAME[A:B]“, which defines a
range for the named group from B to A. Individual bits, signals, or pins are given as
“NAME[C]” where the range of the variable C is given in the text. For example:
CFG[2:0], and SRPN[0].
• Units are abbreviated as follows:
– MHz = Megahertz
– µs = Microseconds
– kBaud, kbit = 1000 characters/bits per second
– MBaud, Mbit = 1,000,000 characters/bits per second
– Kbyte = 1024 bytes of memory
– Mbyte = 1048576 bytes of memory
In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by
1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The
kBaud unit scales the expression preceding it by 1000. The M prefix scales by
1,000,000 or 1048576, and µ scales by .000001. For example, 1 Kbyte is
1024 bytes, 1 Mbyte is 1024 x 1024 bytes, 1 kBaud/kbit are 1000 characters/bits
per second, 1 MBaud/Mbit are 1000000 characters/bits per second, and 1 MHz is
1,000,000 Hz.
• Data format quantities are defined as follows:
– Byte = 8-bit quantity
– Half-word = 16-bit quantity

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– Word = 32-bit quantity

– Double-word = 64-bit quantity

1.1.3 Reserved, Undefined, and Unimplemented Terminology

In tables where register bit fields are defined, the following conventions are used to
indicate undefined and unimplemented functions. Furthermore, types of bits and bit
fields are defined using the abbreviations as shown in Table 1-1.

Table 1-1 Bit Function Terminology

Function of Bits Description
Unimplemented, Register bit fields named 0 indicate unimplemented functions
Reserved with the following behavior.
• Reading these bit fields returns 0.
• Writing these bit fields has no effect.
These bit fields are reserved. When writing, software should
always set such bit fields to 0 in order to preserve compatibility
with future products.
Undefined, Certain bit combinations in a bit field can be marked “Reserved”,
Reserved indicating that the behavior of the TC1796 is undefined for that
combination of bits. Setting the register to such undefined bit or
bit field combinations may lead to unpredictable results. Such bit
combinations are reserved. When writing, software must always
set such bit fields to legal values as defined for it.
rw The bit or bit field can be read and written.
rwh As rw, but bit or bit field can be also set or cleared by hardware.
r The bit or bit field can only be read (read-only).
w The bit or bit field can only be written (write-only).
rh The bit or bit field can only be read. It can be also set or cleared
by hardware (typical example: status flags).
s Bits with this attribute are “sticky” in one direction. If their reset
value is once overwritten by software, they can be switched
again into there reset state only by a reset operation. Software
cannot switch this type of bit into its reset state by writing the
register. This attribute can be combined to ‘rws’ or ‘rwhs’.
f Bits with this attribute are readable only when they are accessed
by an instruction fetch. Normal data read operations will return
other values.

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1.1.4 Register Access Modes

Read and write access to registers and memory locations are sometimes restricted. In
memory and register access tables, the terms as defined in Table 1-2 are used.

Table 1-2 Access Terms

Symbol Description
U Access Mode: Access permitted in User Mode 0 or 1.
Reset Value: Value or bit is not changed by a reset operation.
SV Access permitted in Supervisor Mode.
R Read-only register.
32 Only 32-bit word accesses are permitted to this register/address range.
E Endinit-protected register/address.
PW Password-protected register/address.
NC No change, indicated register is not changed.
BE Indicates that an access to this address range generates a Bus Error.
nBE Indicates that no Bus Error is generated when accessing this address
range, even though it is either an access to an undefined address or the
access does not follow the given rules.
nE Indicates that no Error is generated when accessing this address or
address range, even though the access is to an undefined address or
address range. True for CPU accesses (MTCR/MFCR) to undefined
addresses in the CSFR range.
X Undefined value or bit.

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1.1.5 Abbreviations and Acronyms

The following acronyms and termini are used in this document:

ABM Alternate Boot Mode

ADC Analog-to-Digital Converter
AGPR Address General Purpose Register
ALU Arithmetic and Logic Unit
ASC Asynchronous/Synchronous Serial Controller
BCU Bus Control Unit
BROM Boot ROM & Test ROM
BSL Bootstrap Loader
CAN Controller Area Network
CMEM PCP Code Memory
CISC Complex Instruction Set Computing
CPS CPU Slave Interface
CPU Central Processing Unit
CSA Context Save Area
CSFR Core Special Function Register
DBCU Data Local Memory Bus Control Unit
DFLASH Data Flash Memory
DGPR Data General Purpose Register
DMA Direct Memory Access
DMI Data Memory Interface
DMU Data Memory Unit
DPRAM Dual-Port RAM
EBU External Bus Unit
EMI Electro-Magnetic Interference
FADC Fast Analog-to-Digital Converter
FAM Flash Array Module
FCS Flash Command State Machine
FIM Flash Interface and Control Module
FPI Flexible Peripheral Interconnect (Bus)

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FPU Floating Point Unit

GPIO General Purpose Input/Output
GPR General Purpose Register
GPTA General Purpose Timer Array
ICACHE Instruction Cache
I/O Input / Output
LDRAM Local Data RAM
LFI Local Memory-to-FPI Bus Interface
LMB Local Memory Bus
LMI Local Memory Interface
LSB Least Significant Bit
LTCA Local Timer Cell Array
MLI Micro Link Interface
MMU Memory Management Unit
MSB Most Significant Bit
MSC Micro Second Channel
NMI Non-Maskable Interrupt
OCDS On-Chip Debug Support
OVRAM Code Overlay Memory
PBCU Program Local Memory Bus Control Unit
PCP Peripheral Control Processor
PFLASH Program Flash Memory
PMI Program Memory Interface
PMU Program Memory Unit
PLL Phase Locked Loop
PLMB Program Local Memory Bus
PMU Program Memory Unit
PRAM PCP Parameter RAM
RAM Random Access Memory
RBCU Remote Peripheral Bus Control Unit
RISC Reduced Instruction Set Computing
RPB Remote Peripheral Bus

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SBCU System Peripheral Bus Control Unit

SBRAM Stand-by Data Memory
SCU System Control Unit
SFR Special Function Register
SPB System Peripheral Bus
SPRAM Scratch-Pad RAM
SRAM Static Data Memory
SRN Service Request Node
SSC Synchronous Serial Controller
STM System Timer
WDT Watchdog Timer

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1.2 System Architecture of the TC1796

The TC1796 combines three powerful technologies within one silicon die, achieving new
levels of power, speed, and economy for embedded applications:
• Reduced Instruction Set Computing (RISC) processor architecture
• Digital Signal Processing (DSP) operations and addressing modes
• On-chip memories and peripherals
DSP operations and addressing modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1796 include:
• Program Memory Unit – instruction memory and instruction cache
• Data Memory Unit – data memory
• Serial communication interfaces – flexible synchronous and asynchronous modes
• Peripheral Control Processor – standalone data operations and interrupt servicing
• DMA Controller – DMA operations and interrupt servicing
• General-purpose timers
• High-performance on-chip buses
• On-chip debugging and emulation facilities
• Flexible interconnections to external components
• Flexible power-management
The TC1796 is a high-performance microcontroller with TriCore CPU, program and data
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor
and a DMA controller, several on-chip peripherals, and an external bus interface. The
TC1796 is designed to meet the needs of the most demanding embedded control
systems applications where the competing issues of price/performance, real-time
responsiveness, computational power, data bandwidth, and power consumption are key
design elements.
The TC1796 offers several versatile on-chip peripheral units such as serial controllers,
timer units, and Analog-to-Digital converters. Within the TC1796, all these peripheral
units are connected to the TriCore CPU/system via two Flexible Peripheral Interconnect
(FPI) Buses. Several I/O lines on the TC1796 ports are reserved for these peripheral
units to communicate with the external world.

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1.2.1 TC1796 Block Diagram

Figure 1-1 shows the block diagram of the TC1796.

FPU DMI
PMI
SPRAM: Scratch-Pad RAM
TriCore 56 KB LDRAM
48 KB SPRAM ICACHE: Instruction cache
16 KB ICACHE (TC1M) LDRAM Local data RAM
8 KB DPRAM
DPRAM: Dual-port RAM
CPS BROM: Boot ROM
Program Local Memory Bus Data Local Memory Bus PFLASH: Program Flash Memory
PBCU P LMB DLMB DBCU DFLASH: Data Flash Memory
SBRAM: Stand-by Data Memory
SRAM: Data Memory
PRAM: PCP Parameter Memory
PMU CMEM: PCP Code Memory
DMU
PLMB: Program Local Memory Bus
16 KB BROM
DLMB: Data Local Memory Bus
LMI

EBU 2 MB PFLASH
128 KB DFLASH 64 KB SRAM RPB: Remote Peripheral Bus
16 KB SBRAM SPB: System Peripheral Bus
Emulation Memory shaded: only available in TC1796ED
Interface LFI Bridge Remote Peripheral Bus

OCDS Debug
Interface
/JTAG 16 KB PRAM
SSC0
F PI-Bus Interface

ASC0
Interrupts

PCP2
Core STM SSC1
ASC1
System Peripheral Bus

Analog Input Assignment

RP B

32 KB CMEM SBCU ADC0

GPTA0
S PB

fCPU
SCU PLL Ports ADC1
GPTA1 fFPI
BI0

BI1

LTCA2 DMA FADC

SMIF
RBCU

MultiCAN
(with 4 MSC MSC
CAN 0 1 MLI MLI MEM
Nodes) 0 1 CHK
MCB05573_mod

Figure 1-1 TC1796 Block Diagram

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1.2.2 Features
The TC1796 has the following features:

High-performance 32-Bit CPU

• 32-bit architecture with 4 Gbyte unified data, program, and input/output address
space
• Fast automatic context-switching
• Multiply-accumulate unit
• Floating point unit
• Saturating integer arithmetic
• Two high-performance on-chip peripheral buses (FPI Bus)
• Register-based design with multiple variable register banks
• Bit handling
• Packed data operations
• Zero overhead loop
• Precise exceptions
• Flexible power management

High-efficiency Instruction Set

• 16/32-bit instructions for reduced code size
• Data types include: Boolean, array of bits, character, signed and unsigned integer,
integer with saturation, signed fraction, double-word integers, and IEEE-754 single-
precision floating point
• Data formats include: Bit, 8-bit byte, 16-bit half-word, 32-bit word, and 64-bit double-
word data formats
• Powerful instruction set
• Flexible and efficient addressing mode for high code density

External Bus Interface

• Programmable external bus interface for low-cost system implementation
• Glueless interface to a wide selection of external memories
• 8-/16-/32-bit data transfers
• Intel-style and Motorola-style peripheral/device support.
• Burst flash memory support
• Flexible address generation and access timing

Integrated On-Chip Memories

• Code memory
– 2 Mbyte on-chip Program Flash (PFLASH)
– 48 Kbyte Scratch-Pad RAM (SPRAM)

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– 16 Kbyte Instruction Cache (ICACHE)

– 16 Kbyte Boot ROM (BROM)
• Data memory
– 64 Kbyte Data Memory (SRAM)
– 16 Kbyte data memory (SBRAM) for standby operation during power-down
– 56 Kbyte Local Data RAM (LDRAM)
– 8 Kbyte Dual-port RAM (DPRAM)
– 128 Kbyte on-chip Data Flash (DFLASH)
• PCP
– 32 Kbyte PCP Code Memory (CMEM)
– 16 Kbyte PCP Data Memory (PRAM)
• On-chip SRAMs with parity error detection

Interrupt System
• Total of 181 Service Request Nodes (SRNs)
• Flexible interrupt-prioritizing scheme with 255 interrupt priority levels
• Fast interrupt response
• Service requests are serviced by CPU or PCP

Peripheral Control Processor (PCP)

• Data move between any two memory or I/O locations
• Data move until predefined limit reached supported
• Read-Modify-Write capabilities
• Full computation capabilities including basic MUL/DIV
• Read/move data and accumulate it to previously read data
• Read two data values and perform arithmetic or logical operation and store result
• Bit-handling capabilities (testing, setting, clearing)
• Flow-control instructions (conditional/unconditional jumps, breakpoint)

DMA Controller
• 16 independent DMA channels
• Programmable priority of the DMA sub-blocks on the bus interfaces
• Buffer capability for move actions on the buses (minimum of 1 move per bus is
buffered).
• Individually programmable operation modes for each DMA channel
• Full 32-bit addressing capability of each DMA channel
• Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
• Micro Link bus interface support
• One register set for each DMA channel
• Flexible interrupt generation

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• DMA Controller operates as bus bridge between System Peripheral Bus and Remote
Peripheral Bus

Parallel I/O Ports

• 127 digital General-Purpose Input/Output (GPIO) port lines
• Input/output functionality individually programmable for each port line
• Programmable input characteristics (pull-up, pull-down, no pull device)
• Programmable output driver strength for EMI minimization (weak, medium, strong)
• Programmable output characteristics (push-pull, open drain)
• Programmable alternate output functions
• Output lines of each port can be updated port-wise or set/cleared/toggled bit-wise

On-Chip Peripheral Units

• Two Asynchronous/Synchronous Serial Channels (ASC) with baud-rate generator,
parity, framing and overrun error detection
• Two Synchronous Serial Channels (SSC) with programmable data length and shift
direction
• Two Micro Second Channel Interfaces (MSC) for serial communication
• One CAN Module with four CAN nodes (MultiCAN) for high-efficiency data handling
via FIFO buffering and gateway data transfer
• Two Micro Link Serial Bus Interfaces (MLI) for serial multiprocessor communication
• Two General Purpose Timer Arrays (GPTA) with a powerful set of digital signal
filtering and timer functionality to accomplish autonomous and complex input/output
management
• One Local Timer Cell Array (LTCA) for signal generation purposes
• Two medium-speed Analog-to-Digital Converter Units (ADC) with 8-bit, 10-bit, or 12-
bit resolution and sixteen analog inputs each
• One fast Analog-to-Digital Converter Unit (FADC)

Package
• P-BGA-416 package, 1 mm pitch

Temperature Ranges
• Ambient temperature: -40 ° to +125 °C
• Maximum junction temperature: +150 °C

Clock Frequencies
• Maximum CPU clock frequency: 150 MHz
• Maximum system clock frequency: 75 MHz

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Complete Development Support

A variety of software and hardware development tools for the 32-bit microcontroller
TC1796 are available from experienced international tool suppliers. The development
environment for the Infineon 32-bit microcontroller includes the following tools:
• Embedded Development Environment for TriCore Products
• The TC1796 On-chip Debug Support (OCDS) provides a JTAG port for
communication between external hardware and the system.
• Two Flexible Peripheral Interconnect Buses (FPI Bus) for on-chip interconnections
and its FPI Bus control units (SBCU, RBCU).
• The System Timer (STM) with high-precision, long-range timing capabilities.
• The TC1796 includes a power management system, a watchdog timer as well as
reset logic.

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1.3 On-Chip Peripheral Units of the TC1796

The TC1796 microcontroller offers several versatile on-chip peripheral units such as
serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the
TC1796 ports are reserved for these peripheral units to communicate with the external
world.
The peripherals mentioned in this overview section are all described in detail in the
chapters of the “TC1796 Peripheral Units (Vol. 2 of 2) User’s Manual” part.

1.3.1 Serial Interfaces

The TC1796 includes eight + four (CAN) serial peripheral interface units:
• Two Asynchronous/Synchronous Serial Interfaces (ASC0 and ASC1)
• Two high-speed Synchronous Serial Interfaces (SSC0 and SSC1)
• Two Micro Second Channel Interfaces (MSC0 and MSC1)
• Two Micro Link Serial Bus Interfaces (MLI0 and MLI1) dedicated for the
communication between two controllers of the TriCore family.
• One MultiCAN Interface with 4 CAN nodes

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1.3.1.1 Asynchronous/Synchronous Serial Interfaces

Figure 1-2 shows a global view of the Asynchronous/Synchronous Serial Interface
(ASC)

Clock fASC
Control

RXD
Address RXD
ASC
Decoder Port
Module
TXD Control
(Kernel) TXD
EIR
TBIR
Interrupt
TIR
Control
RIR

To DMA MCB05574

Figure 1-2 General Block Diagram of the ASC Interface

The ASC provides serial communication between the TC1796 and other
microcontrollers, microprocessors, or external peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock that is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal which can be very accurately
adjusted by a prescaler implemented as a fractional divider.
Each ASC module, ASC0 and ASC1, communicates with the external world via two I/O
lines. The RXD line is the receive data input signal (in Synchronous Mode also output).
TXD is the transmit output signal. Clock control, address decoding, and interrupt service
request control are managed outside the ASC module kernel.

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Features
• Full-duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity-bit generation/checking
– One or two stop bits
– Baud rate from 4.69 MBaud to 1.12 Baud (@ 75 MHz clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
• Half-duplex 8-bit synchronous operating mode
– Baud rate from 9.38 Mbit/s to 763 Bit/s (@ 75 MHz clock)
• Double-buffered transmitter/receiver
• Interrupt generation
– On a transmit buffer empty condition
– On a transmit last bit of a frame condition
– On a receive buffer full condition
– On an error condition (frame, parity, overrun error)

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1.3.1.2 High-Speed Synchronous Serial Interfaces

Figure 1-3 shows a global view of the Synchronous Serial Interface (SSC).

MRSTA
Master MRSTB
fSSC
MTSR MTSR
Clock
Control fCLC MTSRA
MTSRB
Slave
MRST MRST
Address SSC
Decoder SCLKA Port
Module
Slave SCLKB Control
(Kernel)
SCLK SCLK
EIR Master
SLSI[7:1]
Interrupt TIR Slave
Control SLSO[7:0] SLSI
RIR Master
SSC Enabled SLSO[7:0]
M/S Selected
To DMA
MCB05575

Figure 1-3 General Block Diagram of the SSC Interface

The SSC supports full-duplex and half-duplex serial synchronous communication up to
37.5 MBaud (@ 75 MHz module clock) with Receive and Transmit FIFO support. The
serial clock signal can be generated by the SSC itself (Master Mode) or can be received
from an external master (Slave Mode). Data width, shift direction, clock polarity and
phase are programmable. This allows communication with SPI-compatible devices.
Transmission and reception of data are double-buffered. A shift clock generator provides
the SSC with a separate serial clock signal. One slave select input are available for Slave
Mode operation. Eight programmable slave select outputs (chip selects) are supported
in Master Mode.
Note: The SSC0 contains an 8-stage Receive and Transmit FIFO. The SSC1 does not
provide any FIFO functionality.

Features
• Master and Slave Mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first

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– Programmable clock polarity: Idle low or idle high state for the shift clock
– Programmable clock/data phase: Data shift with leading or trailing edge of the shift
clock
• Baud rate generation from 37.5 MBaud to 572.2 Baud (@ 75 MHz module clock)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
• Flexible SSC pin configuration
• Seven slave select inputs SLSI[7:1] in Slave Mode
• Eight programmable slave select outputs SLSO[7:0] in Master Mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
• SSC0 only: 8-stage Receive FIFO (RXFIFO) and 8-stage Transmit FIFO (TXFIFO)
– Independent control of RXFIFO and TXFIFO
– 2- to 16-bit FIFO data width
– Programmable receive/transmit interrupt trigger level
– Receive and Transmit FIFO filling level indication
– Overrun error generation
– Underflow error generation

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1.3.1.3 Micro Second Channel Interfaces

The Micro Second Channel (MSC) interfaces provide serial communication links
typically used to connect power switches or other peripheral devices. The serial
communication link includes a fast synchronous downstream channel and a slow
asynchronous upstream channel. Figure 1-4 shows a global view of the interface signals
of the MSC interface.

fMSC
Clock
Control fCLC
FCLP
FCLN
Address SOP
Downstream
Decoder
Channel SON
EN0
MSC
Interrupt SR[3:0] Module EN1
Control 4 (Kernel)
EN2
To DMA EN3
16
Upstream
Channel

ALTINL[15:0]
8
16 SDI[7:0]
ALTINH[15:0]

EMGSTOPMSC
MCB05576

Figure 1-4 General Block Diagram of the MSC Interface

The downstream and upstream channels of the MSC module communicate with the
external world via nine I/O lines. Eight output lines are required for the serial
communication of the downstream channel (clock, data, and enable signals). One out of
eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The
source of the serial data to be transmitted by the downstream channel can be MSC
register contents or data that is provided on the ALTINL/ALTINH input lines. These input
lines are typically connected to other on-chip peripheral units (for example with a timer
unit such as the GPTA). An emergency stop input signal makes it possible to set bits of
the serial data stream to dedicated values in an emergency case.
Clock control, address decoding, and interrupt service request control are managed
outside the MSC module kernel. Service request outputs are able to trigger an interrupt
or a DMA request.

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Features
• Fast synchronous serial interface to connect power switches in particular, or other
peripheral devices via serial buses
• High-speed synchronous serial transmission on downstream channel
– Serial output clock frequency: fFCL = fMSC/2
– Fractional clock divider for precise frequency control of serial clock fMSC
– Command, data, and passive frame types
– Start of serial frame: Software-controlled, timer-controlled, or free-running
– Programmable upstream data frame length (16 or 12 bits)
– Transmission with or without SEL bit
– Flexible chip select generation indicates status during serial frame transmission
– Emergency stop without CPU intervention
• Low-speed asynchronous serial reception on upstream channel
– Baud rate: fMSC divided by 4, 8, 16, 32, 64, 128, or 256
– Standard asynchronous serial frames
– Parity error checker
– 8-to-1 input multiplexer for SDI lines
– Built-in spike filter on SDI lines

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Introduction

1.3.1.4 MultiCAN Controller

The MultiCAN module contains four independent CAN nodes, representing four serial
communication interfaces.

MultiCAN Module Kernel

fCAN TXDC3
CAN
Clock Node 3 RXDC3
Control fCLC
Message TXDC2
CAN
Object Node 2 RXDC2
Linked
Address Buffer
List Port
Decoder Control TXDC1
128 CAN Control
Objects Node 1 RXDC1

TXDC0
CAN
Node 0 RXDC0

INT_O
Interrupt [15:0]
Control CAN Control

Timing Control and Synchronization

Scheduler
ECTT[7:1]
ScheduleTiming DataMemory

Time-Triggered Extension TTCAN

MCA05577

Figure 1-5 Overview of the MultiCAN Module with Time-Triggered Extension

The MultiCAN module contains four independently operating CAN nodes with Full-CAN
functionality that are able to exchange Data and Remote Frames via a gateway function.
Transmission and reception of CAN frames is handled in accordance with CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
All four CAN nodes share a common set of message objects. Each message object can
be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects can be combined to build
gateways between the CAN nodes or to set up a FIFO buffer.

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The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to the message object list of the CAN node, and it transmits
only messages belonging to this message object list. A powerful, command-driven list
controller performs all message object list operations.
The bit timings for the CAN nodes are derived from the module timer clock (fCAN), and
are programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected
to a CAN node via a pair of receive and transmit pins.

CAN Features
• Compliant with ISO 11898
• CAN functionality according to CAN specification V2.0 B active
• Dedicated control registers for each CAN node
• Data transfer rates up to 1 Mbit/s
• Flexible and powerful message transfer control and error handling capabilities
• Advanced CAN bus bit timing analysis and baud rate detection for each CAN node
via a frame counter
• Full-CAN functionality: A set of 128 message objects can be individually
– Allocated (assigned) to any CAN node
– Configured as transmit or receive object
– Set up to handle frames with 11-bit or 29-bit identifier
– Identified by a timestamp via a frame counter
– Configured to remote monitoring mode
• Advanced acceptance filtering
– Each message object provides an individual acceptance mask to filter incoming
frames.
– A message object can be configured to accept standard or extended frames or to
accept both standard and extended frames.
– Message objects can be grouped into four priority classes for transmission and
reception.
– The selection of the message to be transmitted first can be based on frame
identifier, IDE bit and RTR bit according to CAN arbitration rules, or on its order in
the list.
• Advanced message object functionality
– Message objects can be combined to build FIFO message buffers of arbitrary size,
limited only by the total number of message objects.
– Message objects can be linked to form a gateway that automatically transfers
frames between 2 different CAN buses. A single gateway can link any two CAN
nodes. An arbitrary number of gateways can be defined.
• Advanced data management
– The message objects are organized in double-chained lists.

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– List reorganizations can be performed at any time, even during full operation of the
CAN nodes.
– A powerful, command-driven list controller manages the organization of the list
structure and ensures consistency of the list.
– Message FIFOs are based on the list structure and can easily be scaled in size
during CAN operation.
– Static allocation commands offer compatibility with TwinCAN applications that are
not list-based.
• Advanced interrupt handling
– Up to 16 interrupt output lines are available. Interrupt requests can be routed
individually to one of the 16 interrupt output lines.
– Message post-processing notifications can be combined flexibly into a dedicated
register field of 256 notification bits.

Time-Triggered Extension (TTCAN)

In addition to the event-driven CAN functionality, a deterministic behavior can be
achieved for CAN node 0 by an extension module that supports TTCAN functionality.
The TTCAN protocol is compliant with the confirmed standardization proposal for
ISO 11898-4 and fully conforms to the existing CAN protocol.
The time-triggered functionality is added as higher-layer extension (session layer) to the
CAN protocol in order to be able to operate in safety-critical applications. The new
features allow for deterministic behavior of a CAN network and the synchronization of
networks. Global time information is available. The time-triggered extension is based on
a scheduler mechanism with a timing control unit and a dedicated timing data part.

TTCAN Features
• Full support of basic cycle and system matrix functionality
• Support of reference messages level 1 and level 2
• Usable as time master
• Arbitration windows supported in time-triggered mode
• Global time information available
• CAN node 0 can be configured either for event-driven or time-triggered mode
• Built-in scheduler mechanism and a timing synchronization unit
• Write protection for scheduler timing data memory
• Timing-related interrupt functionality

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1.3.1.5 Micro Link Serial Bus Interface

The Micro Link Interface is a fast synchronous serial interface that makes it possible to
exchange data between microcontrollers of the 32-bit AUDO microcontroller family
without intervention of a CPU or other bus masters. Figure 1-6 shows how two
microcontrollers are typically connected together via their MLI interfaces. The MLI
operates in both microcontrollers as a bus master on the system bus.

Controller 1 Controller 2

CPU CPU

Peripheral Peripheral Peripheral Peripheral

A B C D

Memory MLI MLI Memory

System Bus System Bus

MCA05578

Figure 1-6 Typical Micro Link Interface Connection

Features
• Synchronous serial communication between MLI transmitters and MLI receivers
located on the same or on different microcontroller devices
• Automatic data transfer/request transactions between local/remote controller
• Fully transparent read/write access supported (= remote programming)
• Complete address range of remote controller available
• Specific frame protocol to transfer commands, addresses and data
• Error control by parity bit
• 32-bit, 16-bit, and 8-bit data transfers
• Programmable baud rate: max. fMLI/2 (= 37.5 Mbit/s @ 75 MHz module clock)
• Multiple remote (slave) controllers supported

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Figure 1-7 shows a general block diagram of the MLI Module.

TREADY[D:A] 4
TVALID[D:A] 4
Fract . MLI I/O
Divider Transmitter Control TDATA
fSYS
TCLK

fML I Port
BRKOUT MLI Module
Control
RCLK[D:A] 4
SR[7:0] RREADY[D:A] 4
Move MLI I/O
Engine Receiver Control RVALID[D:A] 4
RDATA[D:A] 4

MCB05870_mod

Figure 1-7 General Block Diagram of the MLI Module

The MLI transmitter and MLI receiver communicate with other off-chip MLI receivers and
MLI transmitters via a four-line serial I/O bus each. Several I/O lines of these I/O buses
are available outside the MLI module kernel as four-line output or input buses with index
numbering A, B, C and D. The transmitter signals are named with the prefix “T” and the
receiver signals are named with the prefix “R”.
Data read and write operations from/to remote window areas can be handled by a Move
Engine that is able to operate as a bus master. Clock control, address decoding, and
interrupt service request control are managed outside the MLI module kernel. Eight
service request outputs can be used to trigger an interrupt or a DMA request.

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1.3.2 General Purpose Timer Array

The TC1796 contains two General Purpose Timer Arrays (GPTA0 and GPTA1) with
identical functionality, plus an additional Local Timer Cell Array (LTCA2). Figure 1-8
shows a global view of the GPTA modules.
The GPTA provides a set of timer, compare, and capture functionalities that can be
flexibly combined to form signal measurement and signal generation units. They are
optimized for tasks typical of engine, gearbox, and electrical motor control applications,
but can also be used to generate simple and complex signal waveforms needed in other
industrial applications.

GPTA0 GPTA1
Clock Generation Unit Clock Generation Unit
FPC0 DCM0 FPC0 DCM0
FPC1 PDL0 FPC1 PDL0
FPC2 DCM1 FPC2 DCM1
DIGITAL DIGITAL
FPC3 PLL FPC3 PLL
DCM2 DCM2
FPC4 PDL1 FPC4 PDL1
FPC5 DCM3 FPC5 DCM3

fGPTA
fGPTA Clock Distribution Unit Clock Distribution Unit
Clock
Conn.

Signal Signal
Clock Bus

Clock Bus

GT0 Generation Unit GT0 Generation Unit

GT1 GT1 LTCA2
GTC00 LTC00 GTC00 LTC00 LTC00
GTC01 LTC01 GTC01 LTC01 LTC01
GTC02 LTC02 GTC02 LTC02 LTC02
GTC03 LTC03 GTC03 LTC03 LTC03

Global Local Global Local Local

Timer Timer Timer Timer Timer
Cell Array Cell Array Cell Array Cell Array Cell Array

GTC30 LTC62 GTC30 LTC62 LTC62

GTC31 LTC63 GTC31 LTC63 LTC63

I/O Line
I/O Line Sharing Unit I/O Line Sharing Unit Sharing Unit

Interrupt
Interrupt Control Unit Interrupt Control Unit Control Unit
MCB05580

Figure 1-8 General Block Diagram of the GPTA Modules

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1.3.2.1 Functionality of GPTA0 and GPTA1

Each of the General Purpose Timer Arrays (GPTA0 and GPTA1) provides a set of
hardware modules required for high-speed digital signal processing:
• Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
• Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
• Duty Cycle Measurement Cells (DCM) provide pulse-width measurement
capabilities.
• A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
• Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated Global Timer Cells.
• Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an external or internal event. A GTC may also be used to control an external
port pin depending on the result of an internal compare operation. GTCs can be
logically concatenated to provide a common external port pin with a complex signal
waveform.
• Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs – enabled in Timer Mode or Capture Mode – can be clocked or
triggered by various external or internal events.
Input lines can be shared by an LTC and a GTC to trigger their programmed operation
simultaneously.
The following list summarizes the specific features of the GPTA units.

Clock Generation Unit

• Filter and Prescaler Cell (FPC)
– Six independent units
– Three basic operating modes:
Prescaler, Delayed Debounce Filter, Immediate Debounce Filter
– Selectable input sources:
Port lines, GPTA module clock, FPC output of preceding FPC cell
– Selectable input clocks:
GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or
uncompensated PLL clock.
– fGPTA/2 maximum input signal frequency in Filter Modes
• Phase Discriminator Logic (PDL)
– Two independent units
– Two operating modes (2- and 3-sensor signals)
– fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input
signal frequency in 3-sensor Mode

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• Duty Cycle Measurement (DCM)

– Four independent units
– 0 - 100% margin and time-out handling
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
• Digital Phase Locked Loop (PLL)
– One unit
– Arbitrary multiplication factor between 1 and 65535
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
• Clock Distribution Unit (CDU)
– One unit
– Provides eight clock output signals (clock bus):
fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock

Signal Generation Unit

• Global Timers (GT)
– Two independent units
– Two operating modes (Free-Running Timer and Reload Timer)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
• Global Timer Cell (GTC)
– 32 units related to the Global Timers
– Two operating modes (Capture, Compare and Capture after Compare)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
• Local Timer Cell (LTC)
– 64 independent units
– Three basic operating modes (Timer, Capture and Compare) for 63 units
– Special compare modes for one unit
– 16-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency

Interrupt Sharing Unit

• 286 interrupt sources, generating up to 92 service requests.

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I/O Sharing Unit

• Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and
MSC interface

1.3.2.2 Functionality of LTCA2

• 64 Local Timer Cells (LTCs)
– Three basic operating modes (Timer, Capture and Compare) for 63 units
– Special compare modes for one unit
– 16-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency

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1.3.3 Analog-to-Digital Converters

The TC1796 contains two medium-speed Analog-to-Digital Converters (ADC0 and
ADC1) with identical functionality and a third fast Analog-to-Digital Converter (FADC).
ADC0 and ADC1 provide 2-3 µs conversion time @ 10-bit resolution and are intended
mainly for single-ended signals. They offer a very flexible and comprehensive control for
monitoring a large number of relatively slow signals, including synchronous conversion
of both ADCs.
The FADC offers very fast conversion rates (280 ns @ 10-bit resolution) thus allowing
sampling of high-frequency signals. For slow and mid-range frequency signal heavy
oversampling can be performed and thus expensive filters can be avoided.

1.3.3.1 Analog-to-Digital Converters (ADC0 and ADC1)

The two on-chip ADC modules of the TC1796 are analog-to-digital converters with 8-bit,
10-bit, or 12-bit resolution including sample & hold functionality. The A/D converters
operate by the method of successive approximation. A multiplexer selects up to
32 analog inputs that can be connected to the 16 conversion channels in each ADC
module. An automatic self-calibration adjusts the ADC modules to changing
temperatures or process variations.

Features
• 8-bit, 10-bit, 12-bit A/D conversion
• Conversion time below 2.5 µs @ 10-bit resolution
• Extended channel status information on request source
• Successive approximation conversion method
• Total Unadjusted Error (TUE) of ±2 LSB @ 10-bit resolution
• Integrated sample & hold functionality
• Direct control of up to 16(32) analog input channels per ADC
• Dedicated control and status registers for each analog channel
• Powerful conversion request sources
• Selectable reference voltages for each channel
• Programmable sample and conversion timing schemes
• Limit checking
• Flexible ADC module service request control unit
• Synchronization of the two on-chip A/D Converters
• Automatic control of external analog multiplexers
• Equidistant samples initiated by timer
• External trigger and gating inputs for conversion requests
• Power reduction and clock control feature

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VDD VDDM
VAGND VSS VSSM VAREF

EMUX0
EMUX0
EMUX1 Port
EMUX1
GRPS Control
GRPS
fADC
Clock
16 Analog Input Channels
fCLC

Analog Input Multiplexer

Control
AIN0
Group 0

Address AIN15
Decoder ADC AIN16
Module
Kernel Group 1
AIN31
SR[7:0]
Interrupt
Control ASGT
SW0TR, SW0GT
ETR, EGT External
Request
To DMA QTR, QGT Unit
TTR, TGT

Synchronization Bridge MCB05581

Figure 1-9 General Block Diagram of the ADC Module

Each of the two ADC modules, ADC0 and ADC1 has 16 analog input channels. An
analog multiplexer selects the input line for the analog input channels from among
32 analog inputs. Additionally, an external analog multiplexer can be used for analog
input extension. External Clock control, address decoding, and service request
(interrupt) control are managed outside the ADC module kernel. A synchronization
bridge is used for synchronization of two ADC modules. External trigger conditions are
controlled by an External Request Unit. This unit generates the control signals for auto-
scan control (ASGT), software trigger control (SW0TR, SW0GT), the event trigger
control (ETR, EGT), queue control (QTR, QGT), and timer trigger control (TTR, TGT).

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1.3.3.2 Fast Analog-to-Digital Converter Unit (FADC)

The on-chip FADC module of the TC1796 is primarily a four-channel A/D converter with
10-bit resolution that operates by the method of successive approximation.

Features
• Extreme fast conversion, 21 cycles of fFADC (280 ns @ fFADC = 75 MHz)
• 10-bit A/D conversion
– Higher resolution by averaging of consecutive conversions is supported
• Successive approximation conversion method
• Four differential input channels
• Offset and gain calibration support for each channel
• Differential input amplifier with programmable gain of 1, 2, 4 and 8 for each channel
• Free-running (Channel Timers) or triggered conversion modes
• Trigger and gating control for external signals
• Built-in Channel Timers for internal triggering
• Channel timer request periods independently selectable for each channel
• Selectable, programmable antialiasing and data reduction filter block

VFAREF VDDAF VDDMF

VFAGND VSSAF VSSMF

fFADC
Clock Data
Control fCLC Reduction
Unit FAIN0P
FAIN0N
Address FAIN1P
A/D
Input Stage

Decoder
Control FAIN1N
A/D
Converter FAIN2P
SR[3:0] FAIN2N
Interrupt
Control FAIN3P
FAIN3N
To DMA

TS[7:0] Channel
Channel
Trigger
Timers
GS[7:0] Control

MCB05582

Figure 1-10 Block Diagram of the FADC Module

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As shown in Figure 1-10, the main FADC functional blocks are:

• The Input Stage – contains the differential inputs and the programmable amplifier
• The A/D Converter – is responsible for the analog-to-digital conversion
• The Data Reduction Unit – contains programmable antialiasing and data reduction
filters
• The Channel Trigger Control block – determines the trigger and gating conditions for
the four FADC channels.
• The Channel Timers – can independently trigger the conversion of each FADC
channel
• The A/D Control block is responsible for the overall FADC functionality.
The FADC module is supplied by the following power supply and reference voltage lines:
• VDDMF/VDDMF: FADC Analog Part Power Supply (3.3 V)
• VDDAF/VDDAF: FADC Analog Part Logic Power Supply (1.5 V)
• VFAREF/VFAGND: FADC Reference Voltage (3.3 V)/FADC Reference Ground

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1.4 TC1796 Pin Definitions and Functions

Figure 1-11 shows the logic symbol of the TC1796.

TSTRES
D[31:0]
TESTMODE
General HDRST A[23:0]
Control 5 Chip
PORST External Bus
Select Unit Interface
NMI 13
Control
BYPASS
BFCLKI
XTAL1
BFLCKO
XTAL2
Oscillator VD D OSC 16
Port 0 Alternate
VD D OSC3 Functions :
16
VSSOSC Port 1 MLI0 / SCU
14 SSC0 / SSC1 /
TRST Port 2
GPTA
TCK 16
Port 3
TDI 16 GPTA
TDO Port 4
JTAG / 8
TMS ASC0 / ASC1 /
OCDS Port 5 MSC0 / MSC1 /MLI0
BRKIN
TC1796 12 ASC0 / ASC1 /
BRKOUT Port 6
SSC1 / CAN
8
TR[15:0] Port 7 ADC0 / ADC1
TRCLK 8
Port 8 MLI 1 /
9 GPTA
VD DEBU 9 MSC0 / MSC1 /
11 Port 9
VD D P GPTA
13 4
Digital Circuitry VD D Port 10 HWCFG
Power Supply 2
VD DFL3
6 Dedicated
VDD SBR AM
62 SSC0 I/O Lines
VSS 8
LVDS MSC Outputs
V FAR EF
VFAGN D ADC
AN[43:0] Analog Inputs
FADC Analog VDD MF
2
Power Supply VSSMF VAR EFx
2 ADC0 /ADC1
VDD AF VAGN Dx
Analog
VSSAF VD D M Power Supply
10 VSSM
N.C.
MCA05583_mod

Figure 1-11 TC1796 Logic Symbol

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1.4.1 TC1796 Pin Configuration

Figure 1-11 shows the logic symbol of the TC1796.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

A SO FCL V HD BY A
N.C. P2.9 P2.13 P2.15 P0.14 P0.5 P0.2 P0.1 P0.0 P3.14 P3.5 P3.1 P5.1 P5.2 P5.7 DDFL3 P9.0 P9.3 P10.0 NMI VDDP VSS
N1 P1A RST PASS

B SO FCL V PO TEST V VSS VDD B

P2.6 P2.7 P2.10 P2.14 P0.9 P0.6 P0.4 P0.3 P3.15 P3.6 P3.3 P3.0 P5.0 P5.3 P5.6 DDFL3 P9.1 P9.2 P10.1
P1A N1 RST MODE DDP

C SO FCL FCL BRK C

P2.5 P2.8 P2.11 P2.12 P0.12 P0.10 P0.8 P0.7 P3.7 P3.10 P3.9 P3.4 P3.2 P5.5 P5.4 P9.6 P9.8 P10.2 N.C. VDDP VSS VDD
P0A N0 P0A IN

D SO BRK D
P2.4 P2.3 P2.2 P0.15 P0.13 P0.11 VDDP VSS VDD P3.8 P3.12 P3.13 P3.11 VDDP VSS VDD P9.4 P9.5 P9.7 P10.3 VDDP VSS VDD TDO
N0 OUT

E
VDD E
P6.12 P6.11 P6.6 P6.9 VDD TCK TDI
OSC3

VSS VDD
F P6.14 P6.10 P6.4 P6.8 TRST TMS F
OSC OSC

TST XTAL XTAL

G P6.15 P6.13 P6.7 P6.5 N.C. G
RES 2 1

H P8.1 P8.0 N.C. VDD VDDEBU VDDEBU VDDEBU VDDEBU H

J P8.4 P8.3 P8.2 VSS A5 A0 A1 A2 J

K P8.7 P8.5 P8.6 VDDP TR12 TR13 TR15 VSS VSS VSS VSS VSS A9 A6 A3 A4 K

L P1.15 P1.14 P1.13 P1.11 TR11 TR10 TR14 VSS VSS VSS VSS VSS VSS A13 A7 A8 L

M P1.10 P1.9 P1.8 P1.5 TR9 TR8 VSS VSS VSS VSS VSS VSS VDDEBU A12 A11 A10 M

N P1.3 P1.7 P1.6 P1.4 VSS VSS VSS VSS VSS VSS VSS VSS A15 A16 A17 A14 N

P P1.2 P1.1 P1.0 P1.12 VSS VSS VSS VSS VSS VSS VSS VSS VDD A19 A20 A18 P

R
VDD R
P7.1 P7.0 VDD TR6 TR7 TR5 VSS VSS VSS VSS VSS VSS A21 A23 A22
SBRAM

T VSS TR VSS VSS VSS VSS VSS VDDEBU T

P7.6 P7.5 P7.4 TR3 TR1 D1 D3 D0
CLK

U AN23 P7.7 P7.3 P7.2 TR4 TR2 TR0 VSS VSS VSS VSS VSS D6 D9 D5 D2 U

V AN22 AN21 AN19 AN16 VDD D13 D8 D4 V

W AN20 AN17 AN13 VDDM VSS D16 D12 D7 W

Y AN18 AN14 AN10 VSSM VDDEBU D18 D14 D10 Y

AA AN15 AN11 AN5 AN2 D19 D22 D17 D11 AA

AB AN12 AN9 AN3 AN7 VDD D21 D20 D15 AB

SLSO
AC AN8 AN4 AN32 AN38 AN42 VAGND1 AN26 AN24 VDDAF VSS VDD P4.4 P4.8 P4.12 VDDP VSS VDDEBU VSS VDD N.C. VDDEBU VSS D28 D25 D23 AC
1

AD AN6 AN1 AN34 AN40 AN35 VAREF1 AN27 AN25 VSSAF P4.0 P4.2 P4.5 P4.11 P4.15 SLSI0 VDDP BC1 HLDA CS3 CS2 CS1 BREQ N.C. D31 D27 D24 AD

SLSO MRST CS
AE AN0 AN33 AN36 AN41 VAREF0 AN28 AN30 VFAGND VDDMF P4.1 P4.3 P4.7 P4.13 VDDP BC0 BC3 WAIT CS0 N.C. N.C. D30 D29 D26 AE
0 0 COMB

SCLK MTSR RD/ BF BF

AF N.C. AN37 AN39 AN43 VAGND0 AN29 AN31 VFAREF VSSMF P4.6 P4.9 P4.10 P4.14 VDDP HOLD BC2 MR/W RD ADV BAA AF
0 0 WR CLKI CLKO N.C.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

MCA05584

Figure 1-12 TC1796 Pinning for P-BGA-416 Package (top view)

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Table 1-3 Pin Definitions and Functions

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
External Bus Interface (EBU)
D[31:0] I/O B1 VDDEBU EBU Data Bus Lines
The EBU Data Bus Lines D[31:0] serve as
external data bus.
D0 T26 I/O Data bus line 0
D1 T24 I/O Data bus line 1
D2 U26 I/O Data bus line 2
D3 T25 I/O Data bus line 3
D4 V26 I/O Data bus line 4
D5 U25 I/O Data bus line 5
D6 U23 I/O Data bus line 6
D7 W26 I/O Data bus line 7
D8 V25 I/O Data bus line 8
D9 U24 I/O Data bus line 9
D10 Y26 I/O Data bus line 10
D11 AA26 I/O Data bus line 11
D12 W25 I/O Data bus line 12
D13 V24 I/O Data bus line 13
D14 Y25 I/O Data bus line 14
D15 AB26 I/O Data bus line 15
D16 W24 I/O Data bus line 16
D17 AA25 I/O Data bus line 17
D18 Y24 I/O Data bus line 18
D19 AA23 I/O Data bus line 19
D20 AB25 I/O Data bus line 20
D21 AB24 I/O Data bus line 21
D22 AA24 I/O Data bus line 22
D23 AC26 I/O Data bus line 23
D24 AD26 I/O Data bus line 24
D25 AC25 I/O Data bus line 25
D26 AE26 I/O Data bus line 26
D27 AD25 I/O Data bus line 27
D28 AC24 I/O Data bus line 28
D29 AE25 I/O Data bus line 29
D30 AE24 I/O Data bus line 30
D31 AD24 I/O Data bus line 31

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
A[23:0] O B1 VDDEBU EBU Address Bus Lines A[23:0]
The EBU Address Bus Lines serve as
external address bus.
A0 J24 O Address bus line 0
A1 J25 O Address bus line 1
A2 J26 O Address bus line 2
A3 K25 O Address bus line 3
A4 K26 O Address bus line 4
A5 J23 O Address bus line 5
A6 K24 O Address bus line 6
A7 L25 O Address bus line 7
A8 L26 O Address bus line 8
A9 K23 O Address bus line 9
A10 M26 O Address bus line 10
A11 M25 O Address bus line 11
A12 M24 O Address bus line 12
A13 L24 O Address bus line 13
A14 N26 O Address bus line 14
A15 N23 O Address bus line 15
A16 N24 O Address bus line 16
A17 N25 O Address bus line 17
A18 P26 O Address bus line 18
A19 P24 O Address bus line 19
A20 P25 O Address bus line 20
A21 R24 O Address bus line 21
A22 R26 O Address bus line 22
A23 R25 O Address bus line 23
B1 VDDEBU Chip Select Output Lines
CS0 AE21 O Chip select output line 0
CS1 AD21 O Chip select output line 1
CS2 AD20 O Chip select output line 2
CS3 AD19 O Chip select output line 3
CS AE19 O B1 VDDEBU Combined Chip Select Output for Global
COMB Select / Emulator Memory Region /
Emulator Overlay Memory

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
BFCLKO AF25 O B2 VDDEBU Burst Mode Flash Clock Output (non-
differential)
BFCLKI AF24 I B1 Burst Mode Flash Clock Input
(feedback clock)
RD AF20 O B1 Read Control Line
RD/WR AF21 O B1 Write Control Line
ADV AF22 O B1 Address Valid Output
B1 Byte Control Lines
BC0 AE17 O Byte control line 0
BC1 AD17 O Byte control line 1
BC2 AF18 O Byte control line 2
BC3 AE18 O Byte control line 3
MR/W AF19 O B1 Motorola-style Read / Write Control
Signal
WAIT AE20 I – Wait Input for inserting Wait States
BAA AF23 O B1 Burst Address Advance Output
HOLD AF17 I – Hold Request Input
HLDA AD18 O B1 Hold Acknowledge Output
BREQ AD22 O B1 Bus Request Output

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
Parallel Ports
P0 I/O A1 Port 0
Port 0 is a 16-bit bi-directional general-purpose I/O
port.
P0.0 A9 I/O Port 0 I/O line 0
P0.1 A8 I/O Port 0 I/O line 1
P0.2 A7 I/O Port 0 I/O line 2
P0.3 B8 I/O Port 0 I/O line 3
P0.4 B7 I/O Port 0 I/O line 4
P0.5 A6 I/O Port 0 I/O line 5
P0.6 B6 I/O Port 0 I/O line 6
P0.7 C8 I/O Port 0 I/O line 7
P0.8 C7 I/O Port 0 I/O line 8
P0.9 B5 I/O Port 0 I/O line 9
P0.10 C6 I/O Port 0 I/O line 10
P0.11 D6 I/O Port 0 I/O line 11
P0.12 C5 I/O Port 0 I/O line 12
P0.13 D5 I/O Port 0 I/O line 13
P0.14 A5 I/O Port 0 I/O line 14
P0.15 D4 I/O Port 0 I/O line 15
The states of the Port 0 pins are latched into the
software configuration input register SCU_SCLIR at
the rising edge of HDRST.
In the different TC1796 device versions several Port 0
pins are reserved for device configuration purposes
(see Page 10-25).

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P1 I/O A1/A2 VDDP Port 1
Port 1 is a 16-bit bi-directional general-
purpose I/O port which can be alternatively
used for the MLI0 interface or as external
trigger input lines.
P1.0 P3 I A1 REQ0 External trigger input 0
P1.1 P2 I A1 REQ1 External trigger input 1
P1.2 P1 I A1 REQ2 External trigger input 3
P1.3 N1 I A1 REQ3 External trigger input 2
I A1 TREADY0B MLI0 transmit channel
ready input B
P1.4 N4 O A2 TCLK0 MLI0 transmit channel clock
output
P1.5 M4 I A1 TREADY0A MLI0 transmit channel
ready input A
P1.6 N3 O A2 TVALID0A MLI0 transmit channel valid
output A
P1.7 N2 O A2 TDATA0 MLI0 transmit channel data
output
P1.8 M3 I A1 RCLK0A MLI0 receive channel clock
input A
P1.9 M2 O A2 RREADY0A MLI0 receive channel ready
output A
P1.10 M1 I A1 RVALID0A MLI0 receive channel valid
input A
P1.11 L4 I A1 RDATA0A MLI0 receive channel data
input A
P1.12 P4 O A2 SYSCLK System clock output
P1.13 L3 I A1 RCLK0B MLI0 receive channel clock
input B
P1.14 L2 I A1 RVALID0B MLI0 receive channel valid
input B
P1.15 L1 I A1 RDATA0B MLI0 receive channel data
input B

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P2 I/O A1/A2 VDDP Port 2
Port 2 is a 14-bit bi-directional general-
purpose I/O port which can be used
alternatively for the six upper SSC slave
select outputs or for GPTA I/O lines.
P2.2 D3 O A2 SLSO2 Slave select output line 2
P2.3 D2 O A2 SLSO3 Slave select output line 3
P2.4 D1 O A2 SLSO4 Slave select output line 4
P2.5 C1 O A2 SLSO5 Slave select output line 5
P2.6 B1 O A2 SLSO6 Slave select output line 6
P2.7 B2 O A2 SLSO7 Slave select output line 7
P2.8 C2 I/O A1 IN0 / OUT0 line of GPTA
P2.9 A2 I/O A1 IN1 / OUT1 line of GPTA
P2.10 B3 I/O A1 IN2 / OUT2 line of GPTA
P2.11 C3 I/O A1 IN3 / OUT3 line of GPTA
P2.12 C4 I/O A1 IN4 / OUT4 line of GPTA
P2.13 A3 I/O A1 IN5 / OUT5 line of GPTA
P2.14 B4 I/O A1 IN6 / OUT6 line of GPTA
P2.15 A4 I/O A1 IN7 / OUT7 line of GPTA

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P3 I/O A1 VDDP Port 3
Port 3 is a 16-bit bi-directional general-
purpose I/O port which can be alternatively
used for GPTA I/O lines.
P3.0 B12 I/O IN8 / OUT8 line of GPTA
P3.1 A12 I/O IN9 / OUT9 line of GPTA
P3.2 C13 I/O IN10 / OUT10 line of GPTA
P3.3 B11 I/O IN11 / OUT11 line of GPTA
P3.4 C12 I/O IN12 / OUT12 line of GPTA
P3.5 A11 I/O IN13 / OUT13 line of GPTA
P3.6 B10 I/O IN14 / OUT14 line of GPTA
P3.7 C9 I/O IN15 / OUT15 line of GPTA
P3.8 D10 I/O IN16 / OUT16 line of GPTA
P3.9 C11 I/O IN17 / OUT17 line of GPTA
P3.10 C10 I/O IN18 / OUT18 line of GPTA
P3.11 D13 I/O IN19 / OUT19 line of GPTA
P3.12 D11 I/O IN20 / OUT20 line of GPTA
P3.13 D12 I/O IN21 / OUT21 line of GPTA
P3.14 A10 I/O IN22 / OUT22 line of GPTA
P3.15. B9 I/O IN23 / OUT23 line of GPTA

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P4 I/O A1/A2 VDDP Port 4
Port 4 is a 16-bit bi-directional general-
purpose I/O port which can be alternatively
used for GPTA I/O lines.
P4.0 AD10 I/O A21) IN24 / OUT24 line of GPTA
P4.1 AE10 I/O A21) IN25 / OUT25 line of GPTA
P4.2 AD11 I/O A21) IN26 / OUT26 line of GPTA
P4.3 AE11 I/O A21) IN27 / OUT27 line of GPTA
P4.4 AC12 I/O A21) IN28 / OUT28 line of GPTA
P4.5 AD12 I/O A21) IN29 / OUT29 line of GPTA
P4.6 AF10 I/O A21) IN30 / OUT30 line of GPTA
P4.7 AE12 I/O A21) IN31 / OUT31 line of GPTA
P4.8 AC13 I/O A1 IN32 / OUT32 line of GPTA
P4.9 AF11 I/O A1 IN33 / OUT33 line of GPTA
P4.10 AF12 I/O A1 IN34 / OUT34 line of GPTA
P4.11 AD13 I/O A1 IN35 / OUT35 line of GPTA
P4.12 AC14 I/O A1 IN36 / OUT36 line of GPTA
P4.13 AE13 I/O A1 IN37 / OUT37 line of GPTA
P4.14 AF13 I/O A1 IN38 / OUT38 line of GPTA
P4.15 AD14 I/O A1 IN39 / OUT39 line of GPTA

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P5 I/O A2 VDDP Port 5
Port 5 is an 8-bit bi-directional general-
purpose I/O port which can be alternatively
used for ASC0/1 or MSC0/1 lines.
P5.0 B13 I/O RXD0A ASC0 receiver input /
output A
P5.1 A13 O TXD0A ASC0 transmitter output A
P5.2 A14 I/O RXD1A ASC1 receiver input /
output A
P5.3 B14 O TXD1A ASC1 transmitter output A.
P5.3 is latched with the
rising edge of PORST if
BYPASS = 1 and stored in
inverted state as bit
OSC_CON.MOSC.
P5.4 C15 O EN00 MSC0 device select
output 0
O RREADY0B MLI0 receive channel ready
output B
P5.5 C14 I SDI0 MSC0 serial data input
P5.6 B15 O EN10 MSC1 device select
output 0
O TVALID0B MLI0 transmit channel valid
output B
P5.7 A15 I SDI1 MSC1 serial data input

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P6 I/O A2 VDDP Port 6
Port 6 is a 12-bit bi-directional general-
purpose I/O port which can be alternatively
used for SSC1, ASC0/1, and CAN I/O lines.
P6.4 F3 O MTSR1 SSC1 master transmit
I output / SSC1 slave receive
input
P6.5 G4 I MRST1 SSC1 master receive input /
O SSC1 slave transmit output
P6.6 E3 I/O SCLK1 SSC1 clock input/output
P6.7 G3 I SLSI1 SSC1 slave select input
P6.8 F4 I RXDCAN0 CAN node 0 receiver input
I/O RXD0B ASC0 receiver input /
output B
P6.9 E4 O TXDCAN0 CAN node 0 transmitter
output
O TXD0B ASC0 transmitter output B
P6.10 F2 I RXDCAN1 CAN node 1 receiver input
I/O RXD1B ASC1 receiver input /
output B
P6.11 E2 O TXDCAN1 CAN node 1 transmitter
output
O TXD1B ASC1 transmitter output B
P6.12 E1 I RXDCAN2 CAN node 2 receiver input
P6.13 G2 O TXDCAN2 CAN node 2 transmitter
output
P6.14 F1 I RXDCAN3 CAN node 3 receiver input
P6.15 G1 O TXDCAN3 CAN node 3 transmitter
output

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 TC1796
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Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P7 I/O A1 VDDP Port 7
Port 7 is a 8-bit bi-directional general-
purpose I/O port which can be alternatively
used as external trigger input lines and for
ADC0/1 external multiplexer control.
P7.0 R3 I REQ4 External trigger input 4
P7.1 R2 I REQ5 External trigger input 5
O AD0EMUX2 ADC0 external multiplexer
control output 2
P7.2 U4 O AD0EMUX0 ADC0 external multiplexer
control output 0
P7.3 U3 O AD0EMUX1 ADC0 external multiplexer
control output 1
P7.4 T3 I REQ6 External trigger input 6
P7.5 T2 I REQ7 External trigger input 7
P7.6 T1 O AD1EMUX0 ADC1 external multiplexer
control output 0
P7.7 U2 O AD1EMUX1 ADC1 external multiplexer
control output 1

User’s Manual 1-46 V2.0, 2007-07

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P8 I/O A1/A2 VDDP Port 8
Port 8 is an 8-bit bi-directional general-
purpose I/O port which can be alternatively
used for the MLI1 interface or as GPTA I/O
lines.
P8.0 H2 O A2 TCLK1 MLI1 transmit channel clock
output
I/O A2 IN40 / OUT40 line of GPTA
P8.1 H1 I A1 TREADY1A MLI1 transmit channel
ready input A
I/O A1 IN41 / OUT41 line of GPTA
P8.2 J3 O A2 TVALID1A MLI1 transmit channel valid
output A
I/O A2 IN42 / OUT42 line of GPTA
P8.3 J2 O A2 TDATA1 MLI1 transmit channel data
output A
I/O A2 IN43 / OUT43 line of GPTA
P8.4 J1 I A1 RCLK1A MLI1 receive channel clock
input A
I/O A1 IN44 / OUT44 line of GPTA
P8.5 K2 O A2 RREADY1A MLI1 receive channel ready
output A
I/O A2 IN45 / OUT45 line of GPTA
P8.6 K3 I A1 RVALID1A MLI1 receive channel valid
input A
I/O A1 IN46 / OUT46 line of GPTA
P8.7 K1 I A1 RDATA1A MLI1 receive channel data
input A
I/O A1 IN47 / OUT47 line of GPTA

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 TC1796
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Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P9 I/O A2 VDDP Port 9
Port 9 is a 9-bit bi-directional general-
purpose I/O port which can be alternatively
used as GPTA or MSC0/1 I/O lines.
P9.0 A19 I/O IN48 / OUT48 line of GPTA
O EN12 MSC1 device select
output 2
P9.1 B19 I/O IN49 / OUT49 line of GPTA
O EN11 MSC1 device select
output 1
P9.2 B20 I/O IN50 / OUT50 line of GPTA
O SOP1B MSC1 serial data output
P9.3 A20 I/O IN51 / OUT51 line of GPTA
O FCLP1B MSC1 clock output
P9.4 D18 I/O IN52 / OUT52 line of GPTA
O EN03 MSC0 device select
output 3
P9.5 D19 I/O IN53 / OUT53 line of GPTA
O EN02 MSC0 device select
output 2
P9.6 C19 I/O IN54 / OUT54 line of GPTA
O EN01 MSC0 device select
output 1
P9.7 D20 I/O IN55 / OUT55 line of GPTA
O SOP0B MSC0 serial data output
P9.8 C20 O FCLP0B MSC0 clock output

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 TC1796
System Units (Vol. 1 of 2)
Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
P10 I – VDDP Hardware Configuration Inputs / Port 10
These inputs are boot mode (hardware
configuration) control inputs. They are
latched with the rising edge of HDRST.
P10.0 A21 I Port 10 input line 0 / HWCFG0
P10.1 B21 I Port 10 input line 1 / HWCFG1
P10.2 C21 I Port 10 input line 2 / HWCFG2
P10.3 D21 I Port 10 input line 3 / HWCFG3
After reset (HDRST = 1), the state of the
Port 10 input pins may be modified from the
reset configuration state. Their actual state
can be read via software (P10_IN register).
During normal operation, input HWCFG1
serves as emergency shut-off control input
for certain I/O lines (e.g. GPTA-related
outputs).
Dedicated Peripheral I/Os
SLSO0 AE14 O A2 VDDP SSC0 Slave Select Output Line 0
SLSO1 AC15 O SSC0 Slave Select Output Line 1
MTSR0 AF15 O SSC0 Master Transmit Output /
I SSC0 Slave Receive Input
MRST0 AE15 I SSC0 Master Receive Input /
O SSC0 Slave Transmit Output
SCLK0 AF14 I/O SSC0 Clock Input/Output
SLSI0 AD15 I SSC0 Slave Select Input

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 TC1796
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Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
MSC Outputs
C VDDP LVDS MSC Clock and Data Outputs2)
FCLP0A C18 O MSC0 differential driver clock output
positive A
FCLN0 C17 O MSC0 differential driver clock output
negative
SOP0A C16 O MSC0 differential driver serial data output
positive A
SON0 D17 O MSC0 differential driver serial data output
negative
FCLP1A A17 O MSC1 differential driver clock output
positive A
FCLN1 B17 O MSC1 differential driver clock output
negative
SOP1A B16 O MSC1 differential driver serial data output
positive A
SON1 A16 O MSC1 differential driver serial data output
negative

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 TC1796
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Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
Analog Inputs
AN[43:0] I D – ADC Analog Input Port
The ADC Analog Input Port provides 44
analog input lines for the A/D converters
ADC0, ADC1, and FADC.
AN0 AE1 I Analog input 0
AN1 AD2 I Analog input 1
AN2 AA4 I Analog input 2
AN3 AB3 I Analog input 3
AN4 AC2 I Analog input 4
AN5 AA3 I Analog input 5
AN6 AD1 I Analog input 6
AN7 AB4 I Analog input 7
AN8 AC1 I Analog input 8
AN9 AB2 I Analog input 9
AN10 Y3 I Analog input 10
AN11 AA2 I Analog input 11
AN12 AB1 I Analog input 12
AN13 W3 I Analog input 13
AN14 Y2 I Analog input 14
AN15 AA1 I Analog input 15
AN16 V4 I Analog input 16
AN17 W2 I Analog input 17
AN18 Y1 I Analog input 18
AN19 V3 I Analog input 19
AN20 W1 I Analog input 20
AN21 V2 I Analog input 21
AN22 V1 I Analog input 22
AN23 U1 I Analog input 23
AN24 AC8 I Analog input 24
AN25 AD8 I Analog input 25
AN26 AC7 I Analog input 26
AN27 AD7 I Analog input 27
AN28 AE6 I Analog input 28
AN29 AF6 I Analog input 29
AN30 AE7 I Analog input 30
AN31 AF7 I Analog input 31

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 TC1796
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Introduction

Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
D – ADC Analog Input Port (cont’d)
AN32 AC3 I Analog input 32
AN33 AE2 I Analog input 33
AN34 AD3 I Analog input 34
AN35 AD5 I Analog input 35
AN36 AE3 I Analog input 36
AN37 AF2 I Analog input 37
AN38 AC4 I Analog input 38
AN39 AF3 I Analog input 39
AN40 AD4 I Analog input 40
AN41 AE4 I Analog input 41
AN42 AC5 I Analog input 42
AN43 AF4 I Analog input 43
TR[15:0] O A3 VDDP OCDS Level 2 Debug Trace Lines2)
(located on center balls)
TR0 U12 O Trace output line 0
TR1 T12 O Trace output line 1
TR2 U11 O Trace output line 2
TR3 T11 O Trace output line 3
TR4 U10 O Trace output line 4
TR5 R12 O Trace output line 5
TR6 R10 O Trace output line 4
TR7 R11 O Trace output line 7
TR8 M11 O Trace output line 8
TR9 M10 O Trace output line 9
TR10 L11 O Trace output line 10
TR11 L10 O Trace output line 11
TR12 K10 O Trace output line 12
TR13 K11 O Trace output line 13
TR14 L12 O Trace output line 14
TR15 K12 O Trace output line 15
TRCLK T10 O A4 VDDP Trace Clock for OCDS Level 2 Debug
Trace Lines2)
(located on a center ball)

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Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
System I/O
TRST F23 I A2 VDDP JTAG Module Reset/Enable Input3)
TCK E24 I A2 JTAG Module Clock Input3)
TDI E25 I A1 JTAG Module Serial Data Input
TDO D25 O A2 JTAG Module Serial Data Output
TMS F24 I A1 JTAG Module State Machine Control
Input
BRKIN C26 I/O A3 OCDS Break Input (Alternate Output)3)
BRK D26 I/O A3 OCDS Break Output (Alternate Input3)
OUT
NMI A22 I –4) Non-Maskable Interrupt Input
HDRST A23 I/O A25) Hardware Reset Input/
Reset Indication Output
PORST B22 I –4) Power-on Reset Input
BYPASS A24 I – PLL Bypass Select Input
This input has to be held stable between
two power-on resets. With BYPASS = 1 the
spike filters in the HDRST, PORST, and
NMI inputs are switched off.
TEST B23 I –6) Test Mode Select Input
MODE For normal operation of the TC1796, this pin
should be connected to high level.
TSTRES G24 I –6) Test Reset Input
For normal operation of the TC1796, this pin
must be connected to low level. Otherwise
an unpredictable reset behavior may occur.
XTAL1 G26 I n.a. VDD Oscillator / PLL / Clock Generator Input /
XTAL2 G25 O Output Pins3)

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Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
N.C. A1 – – – Not Connected
C22 These pins are reserved for future
G23 extension and should not be connected
H3 externally.
AF1
AF26
AC21
AD23
AE22
AE23
Power Supplies
VDDM W4 – – – ADC0/1 Analog Part Power Supply
(3.3 V)
VSSM Y4 – – – ADC0/1 Analog Part Ground for VDDM
VDDMF AE9 – – – FADC Analog Part Power Supply (3.3 V)
VSSMF AF9 – – – FADC Analog Part Ground for VDDAF
VDDAF AC9 – – – FADC Analog Part Logic Power Supply
(1.5 V)
VSSAF AD9 – – – FADC Analog Part Log Ground for VDDAF
VAREF0 AE5 – – – ADC0 Reference Voltage
VAGND0 AF5 – – – ADC0 Reference Ground
VAREF1 AD6 – – – ADC1 Reference Voltage
VAGND1 AC6 – – – ADC1 Reference Ground
VFAREF AF8 – – – FADC Reference Voltage
VFAGND AE8 – – – FADC Reference Ground
VDDOSC F26 – – – Main Oscillator Power Supply (1.5 V)
VDDOSC3 E26 – – – Main Oscillator Power Supply (3.3 V)
VSSOSC F25 – – – Main Oscillator Ground
VDDFL3 A18 – – – Power Supply for Flash (3.3 V)
B18
VDD R1 – – – Power Supply for Stand-by SRAM (1.5 V)
SBRAM

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Table 1-3 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad Power Functions
Driver Supply
Class
VDDEBU H23 – – – EBU Power Supply (2.3 - 3.3 V)
H24
H25
H26
M23
T23
Y23
AC18
AC22
VDD B26 – – – Core Power Supply (1.5 V)
C25
D9
D16
D24
E23
H4
P23
R4
V23
AB23
AC11
AC20
VDDP A25 – – – Port Power Supply (3.3 V)
B24 (also for OCDS)
C23
D7
D14
D22
K4
AC16
AD16
AE16
AF16
VSS see – – – Ground
Table 15 VSS lines are located on outer balls.
1-4 47 VSS lines are located on center balls.

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Introduction

1) In order to minimize noise coupling to the on-chip A/D converters, it is recommended to use these pins as less
as possible in strong driver mode.
2) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range),
an undefined output driving level may occur at these pins.
3) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range),
an undefined output driving level may occur at these pins even if they are input-only pins.
4) Input pad with input spike-filter.
5) Open drain pad with input spike-filter.
6) Input pad, test function only, without input spike-filter.

Table 1-4 VSS Balls

VSS Outer Balls VSS Center Balls
A26, B25, C24, D8, D15, D23, J4, L23, K[17:13], L[17:13], M[17:12],
R23, T4, W23, AC10, AC17, AC19, AC23 N[17:10], P[17:10],
R[17:13], T[17:13], U[17:13]

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Introduction

1.4.2 Pad Driver Classes Overview

Table 1-5 gives a overview of the pad driver classes of the TC1796. Further details can
be found in the “TC1796 Data Sheet“.

Table 1-5 Pad Driver and Input Classes Overview

Class Power Type Sub Class Speed Load Termination
Supply Grade
A 3.3 V LVTTL I/O, A1 6 MHz 100 pF No
LVTTL (e.g. GPIO)
outputs A2 40 MHz 50 pF Series
(e.g. serial I/Os) termination
recommended
A3 75 MHz 50 pF Series
(e.g. Trace outputs, termination
serial I/Os) recommended
(for f > 25 MHz)
A4 150 25 pF Series
(e.g. Trace Clock) MHz termination
recommended
B 2.375 / LVTTL B1 40 MHz 50 pF No
3.6 V1) I/O (e.g. Bus Interface)
B2 75 MHz 35 pF Series
(e.g. Bus Clock) termination
recommended
(for f > 25 MHz)
C 3.3 V LVDS – 50 MHz – Parallel
termination2),
100 Ω ± 10%
D – Analog input, reference voltage inputs.
1) AC characteristics for EBU pins are valid for 2.5 V ± 5% and 3.3 V ± 5%.
2) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected or
properly terminated with the differential parallel termination of 100 Ω ± 10%.

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Introduction

1.4.3 Pull-Up/Pull-Down Behavior of the Pins

Table 1-6 List of Pull-Up/Pull-Down Reset Behavior of the Pins

Pins PORST = 0 PORST = 1
TSTRES, Weak pull-up device active
TDI, TMS,
TESTMODE,
BRKOUT, BRKIN,
all GPIOs,
RD, RD/WR,
ADV, BC[3:0], MR/W,
WAIT, BAA, HOLD,
HLDA, BREQ,
D[31:0], A[23,0],
CS[3:0], CSCOMB
NMI, PORST Weak pull-down device active
BYPASS, Weak pull-up device active High-impedance
SLSO0, SLSO1,
MTSR0, MRST0,
SCLK0, SLSI0,
TDO,
BFCLKI
BFCLKO Weak pull-up device active Push-pull driver active
HDRST Open-drain device drives 0 Weak pull-up device active
(strong pull-down) Open-drain device active
TRST, TCK High-impedance Weak pull-down device active

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CPU Subsystem

2 CPU Subsystem
The TC1796 processor contains a TriCore 1 V1.3 CPU. This chapter describes the
implementation-specific options of the CPU, and should be read in conjunction with the
TriCore 1 Architecture Manual, which describes the complete TriCore Architecture
including the register and instruction set description.

2.1 TC1796 Processor Subsystem

The diagram below shows the block diagram of the TC1796 Processor subsystem. It
also shows the on-chip bus systems.

Floating Point Unit

Program Memory FPU Data Memory
Interface Interface
TriCore
PMI DMI
CPU
48 KB SPRAM 56 KB LDRAM
16 KB ICACHE CPU Slave Interface 8 KB DPRAM
CPS

Remote Peripheral Bus

Program Local Data Local
Memory Bus Memory Bus
PBCU DBCU
PLMB DLMB

RPB
Program Memory Data Memory
Unit Unit
LMI

EBU PMU DMU

16 KB BROM 16 KB SBRAM
Local Memory -to-
2 MB PFLASH FPI Bus Interface 64 KB SRAM
128 KB DFLASH
LFI-Bridge
Emulation Memory
Interface System
Peripheral Bus

To Emulation Memory SPB

(Emulation device only )
LDRAM = Local Data RAM EBU = External Bus Unit
DPRAM = Dual-Port RAM LMI = Local Memory Interface
SPRAM = Scratch-Pad RAM PBCU = Program Local Memory
ICACHE = Instruction Cache Bus Control Unit
SBRAM = Stand-by RAM DBCU = Data Local Memory
SRAM = Data RAM Bus Control Unit
PFLASH = Program Memory Flash
DFLASH = Data Memory Flash
BROM = Boot ROM & Test ROM MCB05585

Figure 2-1 Processor Subsystem Block Diagram

User’s Manual 2-1 V2.0, 2007-07

CPU, V2.0
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CPU Subsystem

2.2 Central Processing Unit Features

The 150 MHz TriCore TC1796 CPU includes:

Architecture
• 32-bit load/store architecture
• 4 Gbyte address range (232)
• 16-bit and 32-bit instructions for reduced code size
• Data types:
– Boolean, integer with saturation, bit array, signed fraction, character, double-word
integers, signed integer, unsigned integer, IEEE-754 single-precision floating point
• Data formats:
– Bit, byte (8-bit), half-word (16-bit), word (32-bit), double-word (64-bit)
• Byte and bit addressing
• Little-endian byte ordering for data, memory and CPU registers
• Multiply and Accumulate (MAC) instructions:
– Dual 16 x 16, 16 x 32, 32 x 32
• Saturation integer arithmetic
• Packed data
• Addressing modes:
– Absolute, circular, bit reverse, long + short, base + offset with pre and post-update
• Instruction types:
– Arithmetic, address arithmetic, comparison, address comparison, logical, MAC,
shift, coprocessor, bit logical, branch, bit field, load/store, packed data, system
• General Purpose Register Set (GPRS):
– Sixteen 32-bit data registers
– Sixteen 32-bit address registers
– Three 32-bit status and program counter registers (PSW, PC, PCXI)
• Core Debug support (OCDS):
– Level 1 and 2, supported in conjunction with the CPS block
– Level 3, supported

Implementation
• Most instructions executed in 1 cycle
• Branch instructions in 1, 2 or 3 cycles (using branch prediction)
• Shadow registers for fast context switch
• Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
• Two memory protection register sets
• Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
• Third pipeline for loop instruction only (zero overhead loop)
• Optional floating point instruction set implemented

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CPU Subsystem

• Optional Memory Management instruction set not implemented

(Memory management configuration registers are always read as MMU not present)

2.2.1 CPU Diagram

The Central Processing Unit (CPU) is comprised of an Instruction Fetch Unit, an
Execution Unit, a General Purpose Register File (GPR), a CPU Slave interface (CPS),
and optional Floating Point Unit (FPU).

To Program Memory Interface (PMI)

64

Instruction Fetch Unit

CPU Slave Interface (CPS)

System Control
Floating Point Unit (FPU)

Coprocessor Interface

Execution Unit Interrupts

Integer Load Store Loop
Pipeline Pipeline Pipeline Core Register
Access

General Purpose Register File (GPR) Debug/Emulation

Address Registers Data Registers Test

64 64

To Data Memory Interface (DMI) MCB05586

Figure 2-2 CPU Block Diagram

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CPU Subsystem

2.2.2 Instruction Fetch Unit

The Instruction Fetch Unit pre-fetches and aligns incoming instructions from the 64-bit
wide Program Memory Interface (PMI). The Issue Unit directs the instruction to the
appropriate pipeline. The Instruction Protection Unit checks the validity of accesses to
the PMI and also checks for instruction breakpoint conditions. The PC Unit is responsible
for updating the program counters.

Program Memory Interface

64

Instruction
Prefetch
Protection

PC Unit Align

Injection Debug

Issue Unit

To Integer To Load/Store To Loop

Pipeline Pipeline Pipeline
MCA05587

Figure 2-3 Instruction Fetch Unit

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CPU Subsystem

2.2.3 Execution Unit

The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop
Pipeline.
The Integer Pipeline and Load/Store Pipeline have four stages: Fetch, Decode, Execute,
and Write-back. The Execute stage may extend beyond one cycle to accommodate
multi-cycle operations such as load instructions.
The Loop Pipeline has two stages: Decode and Write-back.
All three pipelines operate in parallel, permitting up to three instructions to be executed
in one clock cycle.

Integer Pipeline Load/Store Pipeline Loop Pipeline

Load/Store Loop
Decode IP Decode
Decode Decode

MAC
Execute Bit Processor Address ALU
ALU EA Loop Exec.

To Register File
IP Decode = Instruction Prefetch and Decode
MAC = Multiply-Accumulate Unit
ALU = Arithmetic/Logic Unit
Loop Exec. = Loop Execution Unit
EA = Effective Address MCA05588

Figure 2-4 Execution Unit

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CPU Subsystem

2.2.4 General Purpose Register File

The CPU has a General Purpose Register (GPR) file, divided into an Address Register
File (registers A0 through A15) and a Data Register File (registers D0 through D15).
The data flow for instructions issued to the Load/Store Pipeline is steered through the
Address Register File.
The data flow for instructions issued to/from the Integer Pipeline and for data load/store
instructions issued to the Load/Store Pipeline is steered through the Data Register File.

To Pipelines

Data Register File Address Register File

General Purpose
Register File

64 64

Data Alignment

128

To Data Memory Interface

MCA05589

Figure 2-5 General Purpose Register File

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CPU Subsystem

2.3 Implementation-specific Features

This section describes the implementation-specific features of the TC1796 CPU. For a
full description of the TriCore architecture refer to the TriCore 1 Architecture Manual.

2.3.1 Context Save Areas

In the TC1796, Context Save Areas (CSA) must be placed in LDRAM. CSAs should not
be located in the DPRAM (dual-ported RAM).
Refer to the TriCore 1 Architecture Manual Chapter 5 - Tasks and Functions.

2.3.2 Fast Context Switching

The TC1796 uses a uniform context-switching method for function calls, interrupts and
traps. In all cases, the Upper Context of the task is automatically saved and restored by
hardware. Saving and restoring of the Lower Context may be performed optionally by
software.
Fast context switching is enhanced by the unique memory subsystem design. When they
are not full, the shadow registers allow a complete Upper Context to be saved in as few
as two clock cycles. When the shadow registers are full, the upper context save takes
up to five cycles. On the average, an upper context save takes 2.7 cycles. Shadow
registers are automatically restored from memory when required.

2.3.3 Reset System

Several events can cause the TC1796 system to be reset. The CPU does not differ in its
behavior on reset. The status register RST_SR allows the CPU to determine which event
caused the reset. Refer to Chapter 4 of this TC1796 User’s Manual.

2.3.4 Program Counter Register - PC

The Program Counter (PC) holds the address of the instruction that is currently fetched
and forwarded to the CPU pipelines. The CPU handles updates of the PC automatically.
Software can use the current value of the PC for various tasks, such as performing code
address calculations. Reading the PC through software executed by the CPU must only
be done with an MFCR instruction. Explicit writes to the PC through an MTCR instruction
must not be done due to possible unexpected behavior of the CPU.
The CPU must not perform Load/Store instructions to the mapped address of the PC in
Segment 15. A MEM trap will be generated in such a case.
Bit 0 of the PC register is read-only and hard-wired to 0.
Refer to the TriCore 1 Architecture Manual - Core Registers.

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2.3.5 Interrupt System

An interrupt request can be generated by the TC1796 on-chip peripheral units, or it can
be generated by external events. Requests can be targeted to either the CPU, or to the
Peripheral Control Processor (PCP).
The TC1796 interrupt system evaluates service requests for priority and to identify
whether the CPU or PCP should receive the request. The highest-priority service request
is then presented to the CPU (or PCP) by way of an interrupt.
The term “interrupt” is used generally to mean an event directed to the CPU, while the
term “service request” describes an event that can be directed to either the CPU or the
PCP. For more information, refer to Chapter 11 of this TC1796 User’s Manual.

2.3.6 Trap System

The following traps have implementation-specific properties. For a complete description
of the trap system, refer to the TriCore 1 Architecture Manual - Trap System.

UOPC - Unimplemented Opcode (TIN 2)

The TC1796 UOPC trap is raised on optional MMU instructions, coprocessor two and
coprocessor three instructions.

OPD - Invalid Operand (TIN 3)

The TC1796 CPU does not raise OPD traps.

DSE - Data Access Synchronous Error (TIN 2)

The Data Access Synchronous Bus Error (DSE) trap is generated by the DMI on a DMI
control register access error, LMB Bus access error, or a DMI scratch memory range
error. The exact cause of the error can be read in the DMI Synchronous Trap Flag
Register, DMI_STR. DSE traps occur on load accesses.

DAE - Data Access Asynchronous Error (TIN 3)

The Data Access Asynchronous Error Trap (DAE) is generated by the DMI on either a
DMI control register access error, LMB Bus access error, or a DMI scratch memory
range error. The exact cause of the error can be read via the DMI Asynchronous Trap
Flag Register, DMI_ATR. DAE traps occur on store accesses.

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CPU Subsystem

2.4 TC1796 CPU Subsystem Registers

This section only describes the implementation-specific features of the registers listed in
Table 2-1. For complete descriptions of all registers, please refer to the TriCore 1
Architecture Manual.
TC1796 implementation-specific CPU registers are referred directly in this section.

Table 2-1 CPU and Processor Subsystem Registers

Registers Purpose Description Address Map
Core Special Program state information, Architecture see
Function Registers context and stack management, Manual Page 18-108
(CSFRs) interrupt and trap control,
system control
CPU Slave Interface Software break control and see
Registers (CPSs) software service request control Page 18-104
Core General Address and data see
Purpose Registers Page 18-105
(GPRs)
Core Debug Debug control see
Registers (OCDS) Page 18-108
Memory Protection Memory protection control and see
Registers mode selection Page 18-105
Program Memory PMI instruction cache control and see see
Interface Registers status Page 2-26 Page 18-124
(PMI)
Data Memory DMI status and trap flags see see
Interface Registers Page 2-34 Page 18-123
(DMI)

The complete and detailed address map of the CPU and processor subsystem registers
shown in Table 2-1 above is located in Chapter 18. The entries in column “Address
Map” of Table 2-1 directly point to the corresponding pages.

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CPU Subsystem

2.4.1 Core Special Function Registers (CSFR)

Program State Context Stack

Information Management Management
Registers Registers Registers

PC FCX ISP
PSW LCX
Interrupt & Trap
PCXI Control
Registers
System Control
Registers
Identification ICR
Register
SYSCON BIV
CPU_ID MMUCON BTV
MCA05590_mod

Figure 2-6 CSFR Registers

Table 2-2 Core Special Function Registers

Register Register Long Name Address
Short Name
MMU_CON MMU Configuration Register F7E1 8000H
PCXI Previous Context Information Register F7E1 FE00H
PSW Program Status Word F7E1 FE04H
PC Program Counter F7E1 FE08H
SYSCON System Configuration Register F7E1 FE14H
CPU_ID CPU Identification Register F7E1 FE18H
BIV Interrupt Vector Table Pointer F7E1 FE20H
BTV Trap Vector Table Pointer F7E1 FE24H
ISP Interrupt Stack Pointer F7E1 FE28H
ICR ICU Interrupt Control Register F7E1 FE2CH
FCX Free Context List Head Pointer F7E1 FE38H
LCX Free Context List Limit Pointer F7E1 FE3CH

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CPU Subsystem

2.4.1.1 Implementation-specific Core Special Function Registers

This section describes the implementation-specific Program Status Word (PSW) which
is an extension of the PSW description in the TriCore 1 Architecture Manual.
The PSW status flags used for FPU operations overlay the status flags used for
Arithmetic Logic Unit (ALU) operations of the CPU. The non-shaded areas in the PSW
register description define the implementation-specific bits/bit fields.

PSW
Program Status Word (F7E1FE04H) Reset Value: 0000 0B80H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C V SV AV SAV
or or or or or FX RM 0
FS FI FV FZ FU
rwh rwh rwh rwh rwh rwh rw r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 PRS IO IS GW CDE CDC

r rwh rwh rwh rwh rwh rwh

Field Bits Type Description

RM [25:24] rw FPU Rounding Mode Selection
FX 26 rwh FPU Inexact Flag
SAV 27 rh Sticky Advance Overflow Flag
FU rwh FPU Underflow Flag
AV 28 rwh Advance Overflow Flag
FZ FPU Divide by Zero Flag
SV 29 rwh Sticky Overflow Flag
FV FPU Overflow Flag
V 30 rwh Overflow Flag
FI FPU Invalid Operation Flag
C 31 rwh Carry Flag
FS FPU Some Exception Flag

The Interrupt Control Register is also an implementation-specific CSFR. Its Arbitration

Cycle Control implementation-specific details are described on Page 14-8.

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CPU Subsystem

In the TC1796, the MMU_CON register indicates the non-availability of the TriCore 1’s
memory management unit (bit MXT is always set).

MMU_CON
MMU Configuration Register (F7E18000H) Reset Value: 0000 8000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NO
0 TSZ SZB SZA V
MMU
r r r rw rw rw

Field Bits Type Description

NOMMU 15 r No MMU Available
0B MMU is available
1B MMU is not available. All other bits of
MMU_CON are undefined.
0 [14:0], r Reserved
[31:16] Read as 0; should be written with 0.

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CPU Subsystem

2.4.2 CPU Slave Interface (CPS) Registers

In the TC1796, the CPU Slave Interface (CPS) of the TriCore CPU directly accesses the
interrupt service request registers in the CPU from the TC1796 System Peripheral Bus.
The CPS registers are described in detail in the TriCore 1 Architecture Manual - Core
Registers.

Module Software Breakpoint CPU Service

Identification Service Request Request Control
Register Control Register Registers
(n = 3-0)
CPS_ID CPU_SBSRC0 CPU_SRCn
MCA05591_mod

Figure 2-7 CPS Registers

The absolute register addresses are calculated by adding the offset addresses from
Table 2-3 to the CPS Base Address. The registers CPU_SBSRC0 and CPU_SRC[3:0]
are not bit-addressable.

Table 2-3 CPS Registers

Register Short Register Long Name Address
Name
CPS_ID CPS Module Identification Register F7E0 FF08H
CPU_SBSRC01) CPU Software Breakpoint Service Request Control F7E0 FFBCH
Register 0
CPU_SRC3 CPU Service Request Control Register 3 F7E0 FFF0H
CPU_SRC2 CPU Service Request Control Register 2 F7E0 FFF4H
CPU_SRC1 CPU Service Request Control Register 1 F7E0 FFF8H
CPU_SRC0 CPU Service Request Control Register 0 F7E0 FFFCH
1) CPU_SBSRC[3:1] are not implemented in the TC1796. Implementation-specific details see Page 2-19.

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2.4.2.1 Implementation-specific CPU Slave Interface Registers

All registers from Table 2-3 have a TC1796-specific implementation detail, the Type of
Service Control (TOS) bit/bit field. CPU_SBSRC0 is described on Page 2-19. The non-
shaded areas in the CPU_SRCn register description defines the implementation-specific
bits/bit fields.

CPU_SRCn (n = 0-3)
CPU Service Request Control Register n
(F7E0FFFCH-n*4H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET CLR
SRR SRE 0 TOS 0 SRPN
R R
w w rh rw r rw r rw

Field Bits Type Description

TOS 10 rw Type of Service Control
0B Service Provider = CPU
1B Service Provider = PCP
0 11 r Reserved
Read as 0; should be written with 0.

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2.4.3 CPU General Purpose Registers

Address General Data General

Purpose Registers Purpose
(AGPR) Registers (DGPR)

A15 (implicit address) D15 (implicit data)

E14
A14 D14
A13 D13
E12
A12 D12
A11 (return address) D11
E10
A10 (stack pointer) D10
A9 (global address) D9
E8
A8 (global address) D8 64-Bit Extended
A7 D7 Data Registers
E6
A6 D6
A5 D5
E4
A4 D4
A3 D3
E2
A2 D2
A1 (global address) D1
E0
A0 (global address) D0 MCA05592

Figure 2-8 GPR Registers

Table 2-4 GPR Registers

Register Short Register Long Name Address
Name
D0 Data Register 0 F7E1 FF00H
D1 Data Register 1 F7E1 FF04H
D2 Data Register 2 F7E1 FF08H
D3 Data Register 3 F7E1 FF0CH
D4 Data Register 4 F7E1 FF10H
D5 Data Register 5 F7E1 FF14H
D6 Data Register 6 F7E1 FF18H
D7 Data Register 7 F7E1 FF1CH
D8 Data Register 8 F7E1 FF20H
D9 Data Register 9 F7E1 FF24H
D10 Data Register 10 F7E1 FF28H

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Table 2-4 GPR Registers (cont’d)

Register Short Register Long Name Address
Name
D11 Data Register 11 F7E1 FF2CH
D12 Data Register 12 F7E1 FF30H
D13 Data Register 13 F7E1 FF34H
D14 Data Register 14 F7E1 FF38H
D15 Data Register 15 F7E1 FF3CH
A0 Address Register 0 (Global Address Register) F7E1 FF80H
A1 Address Register 1 (Global Address Register) F7E1 FF84H
A2 Address Register 2 F7E1 FF88H
A3 Address Register 3 F7E1 FF8CH
A4 Address Register 4 F7E1 FF90H
A5 Address Register 5 F7E1 FF94H
A6 Address Register 6 F7E1 FF98H
A7 Address Register 7 F7E1 FF9CH
A8 Address Register 8 (Global Address Register) F7E1 FFA0H
A9 Address Register 9 (Global Address Register) F7E1 FFA4H
A10 Address Register 10 (Stack Pointer) F7E1 FFA8H
A11 Address Register 11 (Return Address) F7E1 FFACH
A12 Address Register 12 F7E1 FFB0H
A13 Address Register 13 F7E1 FFB4H
A14 Address Register 14 F7E1 FFB8H
A15 Address Register 15 F7E1 FFBCH

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2.4.4 Core Debug Registers

In the TC1796, several Core Debug registers are available for debug purposes. These
Core Debug registers are described in detail in the TriCore 1 Architecture Manual
chapter - Core Debug Controller.

Core Debug
Registers

DBGSR
EXEVT
CREVT
SWEVT
TR0EVT
TR1EVT
DMS
DCX
CPU_SBSRC0
MCA05593

Figure 2-9 Core Debug Registers

Table 2-5 Core Debug Registers

Register Short Register Long Name Address
Name
DBGSR Debug Status Register F7E1 FD00H
EXEVT External Break Input Event Specifier Register F7E1 FD08H
CREVT Core SFR Access Break Event Specifier Register F7E1 FD0CH
SWEVT Software Break Event Specifier Register F7E1 FD10H
TR0EVT Trigger Event 0 Specifier Register F7E1 FD20H
TR1EVT Trigger Event 1 Specifier Register F7E1 FD24H
DMS Debug Monitor Start Address Register F7E1 FD40H
DCX Debug Context Save Area Pointer F7E1 FD44H
CPU_SBSCR0 CPU Software Breakpoint Service Request Control see Table 2-31)
Register 0
1) Located in the CPU slave (CPS) interface register area.

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2.4.4.1 Implementation-specific Core Debug Registers

This section describes the implementation-specific Core Debug Registers which differ
from the description in the TriCore 1 Architecture Manual. These are:
• Trigger Event 0 Specifier Register
• Trigger Event 1 Specifier Register
• Software Breakpoint Service Request Control Register 0
The non-shaded areas in the register description define the implementation-specific
bits/bit fields.

TR0EVT
Trigger Event 0 Specifier Register (F7E1 FD20H) Reset Value: 0000 0000H
TR1EVT
Trigger Event 1 Specifier Register (F7E1 FD20H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0 0

r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DU DU DLR DLR SU
0 0 0 0 BBM EVTA
_U _LR _U _LR SP
r r rw rw rw rw r rw r rw rw

Field Bits Type Description

0 [20:15] r Reserved
Read as 0; should be written with 0.

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CPU_SBSRC0
CPU Software Breakpoint Service Request Control Register 0
(F7E0 FFBCH) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET CLR
SRR SRE 0 TOS 0 SRPN
R R
w w rh rw r rw r rw

Field Bits Type Description

TOS 10 rw Type of Service Control
0B Service Provider = CPU
1B Reserved
0 11 r Reserved
Read as 0; should be written with 0.

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2.4.5 Memory Protection Registers

As shown in Figure 2-10, there are two Memory Protection Register Sets in the TC1796,
Set 0 and Set 1, which specify memory protection ranges and permissions for code and
data. Set 2 and Set 3 are not implemented in the TC1796. The PSW.PRS bit field
determines which of these sets is currently in use by the CPU.
The Memory Protection Registers are described in detail in the TriCore 1 Architecture
Manual chapter - Memory Protection System.

Data Memory Protection Set 0 Code Memory Protection Set 0

Range 0 Range 0
DPR0_0L DPR0_0U DPM0[7:0] CPR0_0L CPR0_0U CPM0[7:0]

Range 1 Range 1
DPR0_1L DPR0_1U DPM0[15:8] CPR0_1L CPR0_1U CPM0[15:8]

Range 2
DPR0_2L DPR0_2U DPM0[23:16] Data and Code Memory
Protection Sets 0
Range 3 are selected with
PSW.PRS = 00B
DPR0_3L DPR0_3U DPM0[31:24]

Data Memory Protection Set 1 Code Memory Protection Set 1

Range 0 Range 0
DPR1_0L DPR1_0U DPM1[7:0] CPR1_0L CPR1_0U CPM1[7:0]

Range 1 Range 1
DPR1_1L DPR1_1U DPM1[15:8] CPR1_1L CPR1_1U CPM1[15:8]

Range 2
DPR1_2L DPR1_2U DPM1[23:16] Data and Code Memory
Protection Sets 1
Range 3 are selected with
PSW.PRS = 01B
DPR1_3L DPR1_3U DPM1[31:24]
MCA05594

Figure 2-10 Memory Protection Register Sets of the TC1796

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Table 2-6 Memory Protection Registers

Register Register Long Name Address
Short Name
DPR0_0L Data Segment Protection Register Set 0, Range 0, F7E1 C000H
Lower Boundary
DPR0_0U Data Segment Protection Register Set 0, Range 0, F7E1 C004H
Upper Boundary
DPR0_1L Data Segment Protection Register Set 0, Range 1, F7E1 C008H
Lower Boundary
DPR0_1U Data Segment Protection Register Set 0, Range 1, F7E1 C00CH
Upper Boundary
DPR0_2L Data Segment Protection Register Set 0, Range 2, F7E1 C010H
Lower Boundary
DPR0_2U Data Segment Protection Register Set 0, Range 2, F7E1 C014H
Upper Boundary
DPR0_3L Data Segment Protection Register Set 0, Range 3, F7E1 C018H
Lower Boundary
DPR0_3U Data Segment Protection Register Set 0, Range 3, F7E1 C01CH
Upper Boundary
DPR1_0L Data Segment Protection Register Set 1, Range 0, F7E1 C400H
Lower Boundary
DPR1_0U Data Segment Protection Register Set 1, Range 0, F7E1 C404H
Upper Boundary
DPR1_1L Data Segment Protection Register Set 1, Range 1, F7E1 C408H
Lower Boundary
DPR1_1U Data Segment Protection Register Set 1, Range 1, F7E1 C40CH
Upper Boundary
DPR1_2L Data Segment Protection Register Set 1, Range 2, F7E1 C410H
Lower Boundary
DPR1_2U Data Segment Protection Register Set 1, Range 2, F7E1 C414H
Upper Boundary
DPR1_3L Data Segment Protection Register Set 1, Range 3, F7E1 C418H
Lower Boundary
DPR1_3U Data Segment Protection Register Set 1, Range 3, F7E1 C41CH
Upper Boundary

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Table 2-6 Memory Protection Registers (cont’d)

Register Register Long Name Address
Short Name
CPR0_0L Code Segment Protection Register Set 0, Range 0, F7E1 D000H
Lower Boundary
CPR0_0U Code Segment Protection Register Set 0, Range 0, F7E1 D004H
Upper Boundary
CPR0_1L Code Segment Protection Register Set 0, Range 1, F7E1 D008H
Lower Boundary
CPR0_1U Code Segment Protection Register Set 0, Range 1, F7E1 D00CH
Upper Boundary
CPR1_0L Code Segment Protection Register Set 1, Range 0, F7E1 D400H
Lower Boundary
CPR1_0U Code Segment Protection Register Set 1, Range 0, F7E1 D404H
Upper Boundary
CPR1_1L Code Segment Protection Register Set 1, Range 1, F7E1 D408H
Lower Boundary
CPR1_1U Code Segment Protection Register Set 1, Range 1, F7E1 D40CH
Upper Boundary
DPM0 Data Protection Mode Register Set 0 F7E1 E000H
DPM1 Data Protection Mode Register Set 1 F7E1 E080H
CPM0 Code Protection Mode Register Set 0 F7E1 E200H
CPM1 Code Protection Mode Register Set 1 F7E1 E280H

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2.4.5.1 Implementation-specific Memory Protection Registers

This section describes the implementation-specific Code Protection Mode Registers that
differ from the description in the TriCore 1 Architecture Manual. The non-shaded areas
in the CPMx register descriptions define the implementation-specific bits/bit fields.
Therefore, the uppermost 16 bits of CPMx are of type “0, r”.

CPMx (x = 0, 1)
Code Protection Mode Register Set x Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XE XS BL BU XE XS BL BU
0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0
rw rr rw rr rw rr rr rw rw rr rw r rw rr rr rw

Field Bits Type Description

0 [31:16] r Reserved
Read as 0; should be written with 0.
These bits refer to code memory ranges 2 and 3, which are
are not available in the TC1796.

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2.5 Program Memory Interface (PMI)

Program Memory
Interface (PMI)

Interface
64

CPU
PMEM
Tag 16 KB To/From
Data Switch
RAM ICACHE CPU
&
Data Alignment
128 &
Interface Control
48 KB
SPRAM
PMI
Control
Registers
128
Parity
Control/Check
Slave Master
PLMB Interface
PMEM = Program Memory in PMI
64
ICACHE = Instruction Cache
To SCU To/From Program SPRAM = Scratch-Pad RAM
(PMI Memory Parity Errors) Local Memory Bus PLMB = Program Local Memory Bus
MCB05595

Figure 2-11 PMI Block Diagram

2.5.1 PMI Features

The Program Memory Interface (PMI) has the following features:
• 64 Kbyte memory as:
– 16 Kbyte instruction cache (ICACHE)
– 48 Kbyte scratch-pad RAM (SPRAM)
• ICACHE operation features:
– Two-way set associative cache
– LRU (Least-Recently Used) replacement algorithm
– Cache line size = 256 bits (4 double-words)
– Validity granularity (4 double-words per cache line)
– ICACHE can be globally invalidated to provide support for software cache
coherency (to be handled by the programmer).
– ICACHE can be bypassed to provide a direct fetch from the CPU to on-chip and
off-chip resources.

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– ICACHE refill mechanism:

critical double-word first, no line wrap around, streaming to CPU
• CPU interface
– Supporting unaligned accesses (16-bit aligned) with a penalty of one cycle for
unaligned accesses crossing two lines (SPRAM or ICACHE lines)
• Program Local Memory Bus (PLMB) interface to PMU/EBU
• PMI memory cannot be accessed by the PCP using the BCOPY instruction (burst
transfers)
• PLMB slave interface cannot be byte-accessed but can be accessed by half-word,
word or double-word aligned functions only.
• PMI SRAMs (SPRAM, ICACHE, and Tag SRAM) are parity protected

2.5.2 Parity Protection for PMI Memories

In the TC1796, the PMI memory blocks SPRAM, ICACHE, and Tag RAM are equipped
with a parity error detection logic that makes it possible to detect parity errors separately
for SPRAM/ICACHE or the ICACHE Tag RAM. In case of a parity error a NMI is
generated.
Note that before using parity protection for PMI memory blocks the first time after a
power-on reset operation (before setting the corresponding parity error enable bit), the
SPRAM memory must be completely initialized by a user program that writes every
memory location of it once.
More details about the parity control for on-chip memories are described in Section 5.5
on Page 5-37.

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2.5.3 PMI Registers

Three control registers are implemented in the Program Memory Interface. These
registers and their bits are described in this section.

Module Identification Control Registers

Register

PMI_ID PMI_CON0
PMI_CON1
PMI_CON2
MCA05596_mod

Figure 2-12 PMI Registers

Table 2-7 PMI Registers

Register Register Long Name Address Description
Short Name
PMI_ID PMI Module Identification Register F87F FD08H Page 2-27
PMI_CON0 PMI Control Register 0 F87F FD10H Page 2-28
PMI_CON1 PMI Control Register 1 F87F FD14H Page 2-29
PMI_CON2 PMI Control Register 2 F87F FD18H Page 2-30

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2.5.3.1 PMI Module Identification Register

PMI_ID
PMI Module Identification Register
(F87FFD08H) Reset Value: 000B C0XXH
31 16 15 8 7 0

MODNUM MODTYPE MODREV

r r r

Field Bits Type Description

MODREV [7:0] r Module Revision Number
MODREV defines the module revision number. The value
of a module revision starts with 01H (first revision).
MODTYPE [15:8] r Module Type
This bit field defines the module as a 32-bit module: C0H
MODNUM [31:16] r Module Number Value
This bit field defines the module identification number for
the PMI: 000BH

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2.5.3.2 PMI Control Register 0

PMI_CON0
PMI Control Register 0 (F87FFD10H) Reset Value: 0000 0002H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC CC2
0
BYP SPR
r rw rw

Field Bits Type Description

CC2SPR 0 rw Code Cache Memory to SPR
This bit is used for cache test mode purposes.
CC2PR must be written with 0.
Setting it to 1 may lead to unpredictable program
behavior.
CCBYP 1 rw Code Cache Bypass
0B Cache enabled
1B Cache bypassed (disabled)
0 [31:2] r Reserved
Returns 0 when read; should be written with 0.

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2.5.3.3 PMI Control Register 1

PMI_CON1
PMI Control Register 1 (F87FFD14H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC
0
INV
r rw

Field Bits Type Description

CCINV 0 rw Code Cache Invalidate
0B Normal code cache (ICACHE) operation
1B All cache lines are invalidated
As long as CCINV is set, all instruction fetch
accesses generate a cache refill. It is recommended
that CCINV be kept set until ICACHE coherency is
guaranteed.
0 [31:1] r Reserved
Returns 0 when read; should be written with 0.

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2.5.3.4 PMI Control Register 2

PMI_CON2
PMI Control Register 2 (F87FFD18H) Reset Value: 0000 0073H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 PMEMSZ 0 PCSZ

r r r r

Field Bits Type Description

PCSZ [1:0] r Program Cache Size
This bit field indicates the ICACHE size and TAGRAM
configuration of the PMI.
The TC1796 has a fixed ICACHE size of 16 Kbyte.
Therefore, PCSZ is always read as 11B.
11B 16 Kbyte cache
PMEMSZ [6:4] r Program Memory Size (ICACHE + SPRAM)
This bit field indicates the ICACHE plus SPRAM size
of the PMI program memory.
The TC1796 has a fixed ICACHE and SPRAM size of
64 KB. PMEMSZ is always read as 111B.
111B 64 Kbyte program memory
0 [3:2], r Reserved
[31:7] Returns 0 when read; should be written with 0.

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2.6 Data Memory Interface (DMI)

Data Memory
Interface (DMI)
Interface

128 128 DMEM

CPU

8 KB
Data Switch DPRAM

Interface
&
32 32

BPI
Data Alignment
& 128
Interface Control To/From
56 KB
Remote
LDRAM
Periphera
DMI Interface
Control Bus
Registers (RPB)
128 Parity
Control/Check
Slave Master
DLMB Interface
DMEM = Data Memory in DMI
64
LDRAM = Local Data RAM
DPRAM = Dual-Port RAM To/From Data To SCU (DMI Memory
DLMB = Data Local Memory Bus Local Memory Bus Parity Errors)
MCB05597

Figure 2-13 DMI Block Diagrams

2.6.1 DMI Features

The Data Memory Interface (DMI) has the following features:
• 64 Kbyte data memory:
– 8 Kbyte Dual-Port data memory (DPRAM), accessible from CPU and Remote
Peripheral Bus
– 56 Kbyte local data memory (LDRAM)
– DPRAM and LDRAM are parity protected
• CPU interface:
– Supporting unaligned accesses (16-bit aligned) with a minimum penalty of one
cycle for unaligned accesses crossing 2 lines
• Data Local Memory Bus (DLMB) interface. Allows access to the rest of the system.

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2.6.2 Dual-Ported Memory Operation

The dual-ported memory (DPRAM) allows the CPU and Remote Peripheral Bus (RPB)
masters to access the same memory locations simultaneously, reading or writing invalid
data without conflict. In the case of simultaneous accesses to the same address, the
CPU has a higher priority than the RPB master. Table 2-8 defines DPRAM operations.

Table 2-8 DPRAM Access Conflict Handling

Actions CPU Access
Read Write
Read A simultaneous read access of The CPU write operation is
CPU and RPB master occurs. executed first and the RPB
RPB Both read the same memory master read access is delayed.
Master content. The data read is the value that
Access has been written by the CPU.
Write Bus data is transferred to CPU The CPU write operation is
and memory in parallel executed. The RPB master write
data is not written.

2.6.2.1 CPU Buffer Write Operation

Write accesses from the CPU to DMI memories using ST (store) or LDMST (load-modify-
store) instructions first store the write data in a buffer. The content of this buffer is written
to the memory when the CPU interface and DLMB (Data Local Memory Bus) are idle, or
when another CPU write operation to DMI memory follows. A read operation to the same
address (LD instruction) immediately following the write operation will read the data out
of the buffer and not from the DPRAM location. The same is true if a continuous
sequence of read operations to other DPRAM locations keep the CPU interface busy in
the meantime.
For DPRAM operations, such as semaphore handling, it is necessary to ensure that at
least two non-DMI-memory related instructions or another ST instruction are executed
between the ST/LDMST instruction and the following LD instruction to the semaphore
location.
If the data written to a DPRAM location has to be available immediately on the RPB bus
side of the DPRAM, two non-DMI-memory related instructions or another ST instruction
to the DMI memory must follow the critical store instruction.
The smallest memory unit that can be read from or written to the dual-ported memory is
a byte. The largest unit is a double-word. On the remote peripheral bus double-word
accesses are performed as two 32-bit RPB transfers. The conflict handling also operates
properly when CPU access width and RPB access width are different.

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Note: There is no support for locked read-modify-write operations in the dual ported
memory.

2.6.3 Parity Protection for DMI Memories

In the TC1796, the LDRAM and DPRAM memory blocks of the DMI are equipped with a
parity error detection logic that makes it possible to detect parity errors separately for
LDRAM or DPRAM. In case of a parity error a NMI is generated.
Note that before using parity protection for DMI memory blocks the first time after a
power-on reset operation (before setting the corresponding parity error enable bit), the
LDRAM and DPRAM memories must be completely initialized by a user program that
writes every memory location of it once.
More details about the parity control for on-chip memories are described in Section 5.5
on Page 5-37.

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2.6.4 DMI Registers

Two control registers and two trap flag registers are implemented in the DMI. These
registers and their bits are described in this section.

Module Identification Control Registers Trap Flag Registers

Register

DMI_ID DMI_CON DMI_STR

DMI_CON1 DMI_ATR
MCA05598_mod

Figure 2-14 DMI Registers

Table 2-9 DMI Registers

Register Register Long Name Address Description
Short Name
DMI_ID DMI Module Identification Register F87F FC08H Page 2-35
DMI_CON DMI Control Register F87F FC10H Page 2-36
DMI_STR DMI Synchronous Trap Flag Register F87F FC18H Page 2-38
DMI_ATR DMI Asynchronous Trap Flag Register F87F FC20H Page 2-39
DMI_CON1 DMI Control Register 1 F87F FC28H Page 2-37

Access to DMI control registers must only be made with double-word aligned word
accesses. An access not conforming to this rule, or an access that does not follow the
specified privilege mode (Supervisor mode, Endinit-protection), or a write access to a
read-only register, will lead to a bus error if the access was from the LMB Bus, or to a
trap, flagged in DMI_STR/DMI_ATR register in case of a CPU load/store access.

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2.6.4.1 DMI Register Description

The DMI Module Identification Register ID contains read-only information about the DMI
module version.

DMI_ID
DMI Module Identification Register
(F87FFC08H) Reset Value: 0008 C0XXH
31 16 15 8 7 0

MODNUM MODTYPE MODREV

r r r

Field Bits Type Description

MODREV [7:0] r Module Revision Number
MODREV defines the module revision number. The value
of a module revision starts with 01H (first revision).
MODTYPE [15:8] r Module Type
This bit field defines the module as a 32-bit module: C0H
MODNUM [31:16] r Module Number Value
This bit field defines the module identification number for
the DMI: 0008H

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The DMI control register indicates the DMI data memory size and data cache availability.

DMI_CON
DMI Control Register (F87FFC10H) Reset Value: 0000 0070H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 DMEMSZ 0 DCSZ

r rh r rh

Field Bits Type Description

DCSZ [1:0] r Data Cache Size
This bit field indicates the DMI data cache
configuration.
In the TC1796 no data cache is available, therefore
DCSZ is always read as 00B.
00B No cache available
DMEMSZ [6:4] r Data Memory Size
This bit field indicates the DMI data memory size.
In the TC1796 DMEMSZ is always read as 111B.
111B 64 Kbyte DMI data memory
0 [3:2], r Reserved
[31:7] Returns 0 when read.

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The DMI control register 1 is required for data cache test purposes. It is noted here for
the sake of completeness.

DMI_CON1
DMI Control Register 1 (F87FFC28H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DC2
0
SPR
r rw

Field Bits Type Description

DC2SPR 0 rw Cache Test Mode Enable
This bit must always be written with 0.
Setting to 1 will have no effect in TC1796.
0 [31:1] r Reserved
Returns 0 when read; should be written with 0.

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The DMI Synchronous Trap Flag Register, DMI_STR, holds the flags that identify the
root cause of a Data-access Synchronous Bus Error (DSE). Reading DMI_STR in
supervisor mode returns the register contents and then clears its contents. Reading
DMI_STR in user mode returns the contents of the register but does not clear its
contents.

DMI_STR
DMI Synchronous Trap Flag Register
(F87FFC18H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBE LRE
0 0
STF STF
r rh r rh

Field Bits Type Description

LRESTF 0 rh Load Range Synchronous Error
0B No error
1B Load range synchronous error has occurred
LBESTF 2 rh Bus Load Synchronous Error
0B No error
1B Bus load synchronous error has occurred
0 1, r Reserved
[31:3] Returns 0 when read.

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The DMI Asynchronous Trap Flag Register, DMI_ATR, holds the flags that inform about
the root cause of a Data Access Asynchronous Bus Error (ASE). Reading DMI_ATR in
supervisor mode returns the register contents and then clears its contents. Reading
DMI_ATR in user mode returns the contents of the register but does not clear its
contents.

DMI_ATR
DMI Asynchronous Trap Flag Register
(F87FFC20H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBE SRE
0 0 0
ATF ATF
r rh r rh r

Field Bits Type Description

SREATF 1 rh Store Range Asynchronous Error
0B No error
1B Store range asynchronous error has occurred
SBEATF 3 rh LMB Bus Store Asynchronous Error
0B No error
1B Bus store asynchronous error has occurred
0 0, 2, r Reserved
[31:4] Returns 0 when read.

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2.7 Instruction Timing

This section gives information on instruction timing by execution unit. The Integer
Pipeline and Load/Store Pipeline are always present, and the Floating Point Unit (FPU)
is optional. The Load/Store unit implements the optional TLB instructions.

Definition of Terms:
• Repeat Rate
Assuming the same instruction is being issued sequentially, repeat is the minimum
number of clock cycles between two consecutive issues. There may be additional
delays described elsewhere due to internal pipeline effects when issuing a different
subsequent instruction.
• Result Latency
The number of clock cycles from the cycle when the instruction is issued to the cycle
when the result value is available to be used as an operand to a subsequent
instruction or written into a GPR. Result latency is not meaningful for instructions that
do not write a value into a GPR.
• Address Latency
The number of clocks cycles from the cycle when the instruction is issued to the cycle
when the addressing mode updated value is available as an operand to a subsequent
instruction or written into an Address Register.
• Flow Latency
The number of clock cycles from the cycle when the instruction is issued to the cycle
when the next instruction (located at the target location or the next sequential
instruction if the control change is conditional) is issued.

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2.7.1 Integer-Pipeline Instructions

2.7.1.1 Simple Arithmetic Instruction Timings

Each instruction is single issued.

Table 2-10 Simple Arithmetic Instruction Timing

Instruction Result Repeat Instruction Result Repeat
Latency Rate Latency Rate
Integer Pipeline Arithmetic Instructions
ABS 1 1 MAX.H 1 1
ABS.B 1 1 MAX.HU 1 1
ABS.H 1 1 MAX.U 1 1
ABSDIF 1 1 MIN 1 1
ABSDIF.B 1 1 MIN.B 1 1
ABSDIF.H 1 1 MIN.BU 1 1
ABSDIFS 1 1 MIN.H 1 1
ABSDIFS.H 1 1 MIN.HU 1 1
ABSS 1 1 MIN.U 1 1
ABSS.H 1 1 RSUB 1 1
ADD 1 1 RSUBS 1 1
ADD.B 1 1 RSUBS.U 1 1
ADD.H 1 1 SAT.B 1 1
ADDC 1 1 SAT.BU 1 1
ADDI 1 1 SAT.H 1 1
ADDIH 1 1 SAT.HU 1 1
ADDS 1 1 SEL 1 1
ADDS.H 1 1 SELN 1 1
ADDS.HU 1 1 SUB 1 1
ADDS.U 1 1 SUB.B 1 1
ADDX 1 1 SUB.H 1 1
CADD 1 1 SUBC 1 1
CADDN 1 1 SUBS 1 1

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Table 2-10 Simple Arithmetic Instruction Timing (cont’d)

Instruction Result Repeat Instruction Result Repeat
Latency Rate Latency Rate
CSUB 1 1 SUBS.H 1 1
CSUBN 1 1 SUBS.HU 1 1
MAX 1 1 SUBS.U 1 1
MAX.B 1 1 SUBX 1 1
MAX.BU 1 1
Compare Instructions
EQ 1 1 LT.B 1 1
EQ.B 1 1 LT.BU 1 1
EQ.H 1 1 LT.H 1 1
EQ.W 1 1 LT.HU 1 1
EQANY.B 1 1 LT.U 1 1
EQANY.H 1 1 LT.W 1 1
GE 1 1 LT.WU 1 1
GE.U 1 1 NE 1 1
LT 1 1
Count Instructions
CLO 1 1 CLS.H 1 1
CLO.H 1 1 CLZ 1 1
CLS 1 1 CLZ.H 1 1
Extract Instructions
DEXTR 1 1 INS.T 1 1
EXTR 1 1 INSN.T 1 1
EXTR.U 1 1 INSERT 1 1
IMASK 1 1
Logical Instructions
AND 1 1 OR.EQ 1 1
AND.AND.T 1 1 OR.GE 1 1
AND.ANDN.T 1 1 OR.GE.U 1 1
AND.EQ 1 1 OR.LT 1 1
AND.GE 1 1 OR.LT.U 1 1

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CPU Subsystem

Table 2-10 Simple Arithmetic Instruction Timing (cont’d)

Instruction Result Repeat Instruction Result Repeat
Latency Rate Latency Rate
AND.GE.U 1 1 OR.NE 1 1
AND.LT 1 1 OR.NOR.T 1 1
AND.LT.U 1 1 OR.OR.T 1 1
AND.NE 1 1 OR.T 1 1
AND.NOR.T 1 1 ORN 1 1
AND.OR.T 1 1 ORN.T 1 1
AND.T 1 1 XNOR 1 1
ANDN 1 1 XNOR.T 1 1
ANDN.T 1 1 XOR 1 1
NAND 1 1 XOR.EQ 1 1
NAND.T 1 1 XOR.GE 1 1
NOR 1 1 XOR.GE.U 1 1
NOR.T 1 1 XOR.LT 1 1
OR 1 1 XOR.LT.U 1 1
OR.AND.T 1 1 XOR.NE 1 1
OR.ANDN.T 1 1 XOR.T 1 1
Move Instructions
CMOV 1 1 MOV.U 1 1
CMOVN 1 1 MOVH 1 1
MOV 1 1
Shift Instructions
SH 1 1 SH.NE 1 1
SH.AND.T 1 1 SH.NOR.T 1 1
SH.ANDN.T 1 1 SH.OR.T 1 1
SH.EQ 1 1 SH.ORN.T 1 1
SH.GE 1 1 SH.XNOR.T 1 1
SH.GE.U 1 1 SH.XOR.T 1 1
SH.H 1 1 SHA 1 1
SH.LT 1 1 SHA.H 1 1
SH.LT.U 1 1 SHAS 1 1

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CPU Subsystem

Table 2-10 Simple Arithmetic Instruction Timing (cont’d)

Instruction Result Repeat Instruction Result Repeat
Latency Rate Latency Rate
SH.NAND.T 1 1
Coprocessor 0 Instructions
BMERGE 1 1 DVINIT.WS 1 1
BSPLIT 1 1 DVINIT.WU 1 1
DVADJ 1 1 DVSTEP.S 4 4
DVINIT 1 1 DVSTEP.U 4 4
DVINIT.U 1 1 IXMAX 1 1
DVINIT.B 1 1 IXMAX.U 1 1
DVINIT.H 1 1 IXMIN 1 1
DVINIT.BS 1 1 IXMIN.U 1 1
DVINIT.BU 1 1 PACK 1 1
DVINIT.HS 1 1 PARITY 1 1
DVINIT.HU 1 1 UNPACK 1 1

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CPU Subsystem

2.7.1.2 Multiply Instruction Timings

Each instruction is single issued.

Table 2-11 Multiple Instruction Timing

Instruction Result Repeat Instruction Result Repeat
Latency Rate Latency Rate
IP Arithmetic Instructions
MUL 3 2 MUL.H 2 1
MUL.U 3 2 MUL.Q 1/2/3 1/1/2
MULS 3 2 MULM.H 2 1
MULS.U 3 2 MULR.H 2 1
MULR.Q 2 1

For MUL.Q Instruction:

Result Latency Repeat Rate

16 × 16 1 1
16 × 32 2 1
32 × 32 3 2

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2.7.1.3 MAC Instruction Timings

Each instruction is single issued.

Table 2-12 MAC Instruction Timing

Instruction Result Repeat Instruction Result Repeat
Latency Rate Latency Rate
IP Arithmetic Instructions
MADD 3 2 MSUB 3 2
MADD.U 3 2 MSUB.U 3 2
MADDS 3 2 MSUBS 3 2
MADDS.U 3 2 MSUBS.U 3 2
MADD.H 2 1 MSUB.H 2 1
MADD.Q 2/3 1/2 MSUB.Q 2/3 1/2
MADDM.H 2 1 MSUBM.H 2 1
MADDMS.H 2 1 MSUBMS.H 2 1
MADDR.H 2 1 MSUBR.H 2 1
MADDR.Q 2 1 MSUBR.Q 2 1
MADDRS.H 2 1 MSUBRS.H 2 1
MADDRS.Q 2 1 MSUBRS.Q 2 1
MADDS.H 2 1 MSUBS.H 2 1
MADDS.Q 2/3 1/2 MSUBS.Q 2/3 1/2
MADDSU.H 2 1 MSUBAD.H 2 1
MADDSUM.H 2 1 MSUBADM.H 2 1
MADDSUMS.H 2 1 MSUBADMS.H 2 1
MADDSUR.H 2 1 MSUBADR.H 2 1
MADDSURS.H 2 1 MSUBADRS.H 2 1
MADDSUS.H 2 1 MSUBADS.H 2 1

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CPU Subsystem

For MADD.Q, MADDS.Q, MSUB.Q, MSUBS.Q Instructions:

Result Latency Repeat Rate

16 × 16 2 1
16 × 32 2 1
32 × 32 3 2

2.7.1.4 Control Flow Instruction Timing

Note all Integer Pipeline Control flow instructions are conditional.
• Each instruction is single issued.
• All target locations yield a full instruction in one access
(i.e. not 16-bits of a 32-bit instruction).
• All code fetches take a single cycle.
• Timing is best case; no cache misses for context operations, no pending stores.

Table 2-13 Integer Pipeline Control Flow Instruction Timing

Instruction Flow Repeat Instruction Flow Repeat
Latency Rate Latency Rate
Branch Instructions
JEQ 1/2/3 1/2/3 JLTZ 1/2/3 1/2/3
JGE 1/2/3 1/2/3 JNE 1/2/3 1/2/3
JGE.U 1/2/3 1/2/3 JNED 1/2/3 1/2/3
JGEZ 1/2/3 1/2/3 JNEI 1/2/3 1/2/3
JGTZ 1/2/3 1/2/3 JNZ 1/2/3 1/2/3
JLEZ 1/2/3 1/2/3 JNZ.T 1/2/3 1/2/3
JLT 1/2/3 1/2/3 JZ 1/2/3 1/2/3
JLT.U 1/2/3 1/2/3 JZ.T 1/2/3 1/2/3

For All Control Flow Instructions:

Flow Latency Repeat Rate

Correctly predicted, not taken 1 1
Correctly predicted, taken 2 2
Wrongly predicted 3 3

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2.7.2 Load-Store Pipeline Instructions

2.7.2.1 Address Arithmetic Timing

Each instruction is single issued.

Table 2-14 Address Arithmetic Instruction Timing

Instruction Result Repeat Instruction Result Repeat
Latency Rate Latency Rate
LS Arithmetic Instructions
ADD.A 1 1 GE.A 1 1
ADDIH.A 1 1 LT.A 1 1
ADDSC.A 1 1 NE.A 1 1
ADDSC.AT 1 1 NEZ.A 1 1
EQ.A 1 1 SUB.A 1 1
EQZ.A 1 1 NOP 1 1
Trap and Interrupt Instructions
DEBUG – 1 TRAPSV1) – 1
DISABLE – 1 TRAPV3) – 1
ENABLE – 1 RSTV – 1
Move Instructions
MFCR 1 1 MOV.A 1 1
MTCR – 1 MOV.AA 1 1
MOVH.A 1 1 MOV.D 1 1
Sync Instructions
DSYNC2) – 1 ISYNC3) – 1
1) Execution cycles when no TRAP is taken. The execution timing in the case of raising these TRAPs is the same
as other TRAPs such as SYSCALL.
2) Repeat rate assumes that no shadow register write-back is pending, other wise the repeat rate will depend
upon the time for all delayed memory operation to occur.
3) Repeat rate assumes that code refetch takes a single cycle.

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2.7.2.2 Control Flow Instruction Timing

• Each instruction is single issued.
• All targets yield a full instruction in one access (not 16-bits of a 32-bit instruction).
• All code fetches take a single cycle.Timing is best case; no cache misses for context
operations, no pending stores.

Table 2-15 Load/Store Control Flow Instruction Timing

Instruction Flow Repeat Instruction Flow Repeat
Latency Rate Latency Rate
Branch Instructions
J 2 2 JLI 2 2
JA 2 2 JEQ.A 1/2/3 1/2/3
JI 2 2 JNE.A 1/2/3 1/2/3
JL 2 2 JNZ.A 1/2/3 1/2/3
JLA 2 2 JZ.A 1/2/3 1/2/3
CSA Instructions
CALL1) 2-5 2-5 SYSCALL1) – 2-5
CALLA1) 2-5 2-5 SVLCX1) – 4-9
CALLI1) 2-5 2-5 RSLCX1) – 4
RET1) – 2-5 RFE1) – 2-5
BISR1) – 4-9 RFM2) – –
Loop Instructions
LOOP3) 2/1/3 2/1/3 LOOPU3) 2/1/3 2/1/3
1) Latency of CSA related instructions varies according to preceding instruction and status of the shadow register
file. Average latency is ~2.7 cycles
2) Not strictly a CSA operation, but retrieves from memory a subset of context information and changes control
flow in a similar manner.
3) First time encountered executed in LS pipeline: Flow latency = 2, Repeat rate = 2
Successive time executed in Loop Pipeline: Flow latency = 1: Repeat rate = 1 (nested up to 2 deep)
Last time encountered: Flow latency = 3: Repeat rate = 3

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CPU Subsystem

For JLI, JEQ.A, JNE.A JNZ.A, JZ.A Instructions:

Flow Latency Repeat Rate

Correctly predicted, not taken 1 1
Correctly predicted, taken 2 2
Wrongly predicted 3 2

2.7.2.3 Load Instruction Timing

Load instructions can produce two results if they use the pre-increment, post-increment,
circular or bit-reverse addressing modes. Hence, in those cases there are two latencies
that must be specified, the result latency for the value loaded from memory and the
address latency for using the updated address register result.
• Each instruction is single issued.
• The memory references is naturally aligned.
• The memory accessed takes a single cycle to return a data item.
• Timing is best case; no cache misses, no pending stores.

Table 2-16 Load Instruction Timing

Instruction Addr. Result Repeat Instruction Addr. Result Repeat
Latency Latency Rate Latency Latency Rate
Load Instructions
LD.A 1 2 1 LD.Q 1 1 1
LD.B 1 1 1 LD.W 1 1 1
LD.BU 1 1 1 LDLCX 4 4 4
LD.D 1 1 1 LDUCX 4 4 4
LD.DA 1 2 1 SWAP.W 2 2 2
LD.H 1 1 1 LEA1) – 1 1
LD.HU 1 1 1
1) The addressing mode returning an updated address is not relevant for this instruction.

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2.7.2.4 Store Instruction Timing

Cache and Store instructions similar to Load instructions will have a result for the pre-
increment, post-increment, circular or bit-reverse addressing modes, but do not produce
a ‘memory’ result.
• Each instruction is single issued.
• The memory references is naturally aligned.
• The memory accessed takes a single cycle to accept a data item.
• Timing is best case; no cache misses, no pending stores.

Table 2-17 Cache and Store Instruction Timing

Instruction Addr. Repeat Instruction Address Repeat
Latency Rate Latency Rate
Cache Instructions
CACHEA.I 1 1 CACHEA.WI1) 1 1
CACHEA.W1) 1 1
Store Instructions
ST.A 1 1 ST.T 2 2
ST.B 1 1 ST.W 1 1
ST.D 1 1 STLCX 4 4
ST.DA 1 1 STUCX 4 4
ST.H 1 1
ST.Q 1 1 LDMST 2 2
1) Repeat rate assumes that no memory writeback operation occurs. Otherwise the repeat rate will depend upon
the time for the castout buffers to clear.

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2.8 Floating Point Pipeline Timings

These instructions are only valid if the optional Floating Point Unit is implemented.
• Each instruction is single issued.

Table 2-18 Floating Point Instruction Timing

Instruction Result Repeat Instruction Result Repeat
Latency Rate Latency Rate
Floating Point Instructions
ADDF 2 2 MSUB.F 3 3
CMP.F 1 1 MUL.F 2 2
DIV.F 15 15 Q31TOF 2 2
FTOI 2 2 QSEED.F 1 1
FTOQ31 2 2 SUBF 2 2
FTOU 2 2 UPDFL – 1
ITOF 2 2 UTOF 2 2
MADD.F 3 3

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Clock System and Control

3 Clock System and Control

3.1 Overview
This chapter describes the TC1796 clock system. Topics covered include clock gating,
clock domains, clock generation, the operation of clock circuitry, boot-time operation,
fail-safe operation, and clock control registers.
The TC1796 clock system performs the following functions:
• Acquires and buffers incoming clock signals to create a master clock frequency
• Distributes in-phase synchronized clock signals throughout the TC1796’s entire clock
tree
• Divides a system master clock frequency into lower frequencies required by the
different modules for operation
• Dynamically reduces power consumption during operation of functional units
• Statically reduces power consumption through programmable power-saving modes
• Reduces electromagnetic interference (EMI) by switching off unused modules
The clock system must be operational before the TC1796 can function, so it contains
special logic to handle power-up and reset operations. Its services are fundamental to
the operation of the entire system, so it contains special fail-safe logic.
Figure 3-1 shows the structure of the TC1796 clock system. The system clock fSYS is
generated by the oscillator circuit and the PLL (phase-locked loop) unit. Each peripheral
module operates with its module clocks fCLC and fMOD. Suffix “MOD” is a place holder for
the module name, e.g. fASC0.
The functionality of the control blocks shown in Figure 3-1 varies depending on the
functional unit being controlled. Some functional units such as the watchdog timer, are
directly driven by the system clock. The implemented clock control register options are
described for each unit on Table 3-9 on Page 3-39.
All clock control registers CLC and the fractional divider registers FDR are Endinit-
protected.

Features of the TC1796 Clock System

• PLL operation for multiplying clock source by different factors
• Direct drive capability for direct clocking
• Comfortable state machine for secure switching between basic PLL, direct or
prescaler operation
• Sleep and Power-Down Mode support

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Clock System and Control

fEBU fASC
EBU EBU_CLC ASC0_CLC ASC0

PBCU ASC1
DBCU
fCL C0
SSC0_CLC fSSC0
PMI / PMU LFI SSC0
SSC0_FDR
fCL C1
SSC1_CLC
TriCore fSSC1 SSC1
SSC1_FDR
CPU
fCL C0
MSC0_CLC fMSC 0 MSC0
DMI / DMU MSC0_FDR
fCL C1
MSC1_CLC fMSC 1
MSC1_FDR MSC1
XTAL1 fC PU
Main Oscillator fCL C
& PLL CPU Clock CAN_CLC fCAN MultiCAN
CAN_FDR
PLL_CLC fSYS fCL C
Register System CLK
XTAL2 fGPTA 0 GPTA0
GPTA_CLC
GPTA_FDR fGPTA 1
GPTA_EDCTR fL TCA2
ICU GPTA1

SBCU LTCA2
fCL C
ADC0_CLC fADC
RBCU ADC0_FDR ADC0

SCU ADC1
fCL C
FADC_CLC fFADC
WDT FADC
FADC_FDR
fSTM SCU_ fSYSC L K P1.12 /
STM STM_CLC
SCLKFDR SYSCLK

fPC P
PCP PCP_CLC MLI0_FDR fML I0 MLI 0

fDMA
DMA DMA_CLC MLI1_FDR fML I1 MLI 1

The module clock for these modules is For these modules fMOD = fSYS. Its module clock
switched off after reset (module is disabled ). can only be switched on or off (no clock divider ).
MCA05599_mod

Figure 3-1 TC1796 Clocking System

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Clock System and Control

3.2 Clock Generation Unit

The PLL can convert a low-frequency external clock signal to a high-speed internal clock
for maximum performance. The PLL also has fail-safe logic that detects degenerate
external clock behavior such as abnormal frequency deviations or a total loss of the
external clock. It can execute emergency actions if it loses its lock on the external clock.
The Clock Generation Unit (CGU) in the TC1796, shown in Figure 3-2, consists
basically of an oscillator circuit and a Phase-Locked Loop (PLL). The operation of the
CGU is controlled by two registers, OSC_CON and PLL_CLC, which are located in the
System Control Unit (SCU).

XTAL1

Main Clock Generation Unit (CGU) fCPU

fOSC
Osc. Clock
Circuit Output fSYS
Control
XTAL2 M
P- ≥1 fP U K-
Divider fVCO Divider
Phase X
fN VCO
Detect.

N-
Divider
PLL
Osc. PLL
Run Lock
Detect. Detect.
OSCDSIC
ORDRES

VCOBYP
VCOSEL

BYPPIN

SYSFS
MOSC

OSCR

LOCK

NDIV
PDIV

KDIV
OGC

BYPASS
Oscillator Control Register PLL Clock Control and Status Register
OSC_CON PLL_CLC

System Control Unit (SCU)

P5.3 /
TXD1A MCB05600

Figure 3-2 CGU Detailed Block Diagram

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Clock System and Control

3.2.1 Main Oscillator Circuit

The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal
oscillator or an external stable clock source. It basically consists of an inverting amplifier
and a feedback element with XTAL1 as input, and XTAL2 as output.
When using a crystal, a proper external oscillator circuitry must be connected to both
pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz
to 25 MHz. Additionally are necessary, two load capacitances CX1 and CX2, and
depending on the crystal type, a series resistor RX2 to limit the current. A test resistor RQ
may be temporarily inserted to measure the oscillation allowance (negative resistance)
of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1
and CX2 values shown in Figure 3-3 can be used as starting points for the negative
resistance evaluation and for non-productive systems. The exact values and related
operating range are dependent on the crystal frequency and have to be determined and
optimized together with the crystal vendor using the negative resistance method.
Oscillation measurement with the final target system is strongly recommended to verify
the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin
negative resistance) for the oscillator-crystal system.
When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is
left open (unconnected). The external clock frequency can be in the range of 0 - 40 MHz
if the PLL is bypassed, and 4 - 40 MHz if the PLL is used.
The oscillator can also be used in combination with a ceramic resonator. The final
circuitry must be also verified by the resonator vendor.
Figure 3-3 shows the recommended external oscillator circuits for both operating
modes, external crystal mode and external input clock mode.

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Clock System and Control

VDDOSC VDDOSC3 VDDOSC VDDOSC3

fOSC External Clock fOSC

XTAL1 XTAL1
4 - 25 Signal 41) - 40
MHz MHz
TC1796 TC1796
RQ Oscillator Oscillator
RX2
XTAL2 XTAL2
CX1 CX2

Fundamental
Mode Crystal VSSOSC VSSOSC
1) in case of PLL bypass 0 MHz
1) 1)
Crystal Frequency CX1, CX2 RX2
4 MHz 33 pF 0
8 MHz 18 pF 0
12 MHz 12 pF 0
16 - 25 MHz 10 pF 0
1) Note that these are evaluation start values! MCS05601

Figure 3-3 Main Oscillator Circuitry

3.2.1.1 Oscillator Bypass Mode

Especially for test purposes, the oscillator circuitry can be bypassed (disabled). In this
oscillator bypass mode, the clock line fOSC is disconnected from the oscillator circuitry
and directly connected to the XTAL1 pin. The oscillator bypass mode is controlled by bit
OSC_CON.MOSC.
• Normal Mode (OSC_CON.MOSC = 0):
fOSC is derived from the crystal or from an external clock signal
• Oscillator Bypass Mode (OSC_CON.MOSC = 1):
The oscillator is bypassed and fOSC is directly derived from an external clock signal
which is applied to XTAL1.
The MOSC bit can be set in two ways:
• By software: Writing a 1 to bit MOSC of register OSC_CON.
• By hardware at a power-on reset operation: If pin BYPASS = 1, the state of the pin
P5.3/TXD1A is latched with the rising edge of PORST and determines the inverted
state of the MOSC bit. If P5.3 = 0 at the rising edge of PORST, MOSC is set and the
oscillator bypass mode is enabled (see also Figure 3-1).

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Clock System and Control

3.2.1.2 Oscillator Run Detection

The oscillator run detection logic indicates during oscillator start-up after a power-on
operation whether the oscillator is already running or if an emergency operation with PLL
base frequency has to be started. When the oscillator run condition is met, bit
OSC_CON.OSCR is set and the output clock fOSC is enabled to supply the clock signal
to the rest of the system. Figure 3-4 shows the oscillator run detection logic.

OSC_CON
Main ≥1
Oscillator
fOSC Q D Q OSCR
Counter A
(3-Bit)
(4 - 25 MHz) R

OSC_CON
ORDRES ≥1

PLL fN
Counter B Q
(4 - 8 MHz) (5-Bit)
R
MCA05602

Figure 3-4 Oscillator Run Detection Circuitry

The oscillator run detection consists of two counters, Counter A and B. The 3-bit Counter
A is running with the oscillator frequency and stops at its terminal count value. The 5-bit
Counter B is running at fN, the divided (N-Divider) VCO clock frequency. Always at the
terminal count of Counter B the state of Counter A is latched in a flip-flop, bit OSCR is
updated, and both counters a reset. This means, if Counter A does not reaches its
terminal count value (8 fOSC clock periods) within a counter period of Counter B (32 fN
clock periods), the oscillator is designated as “not running” by OSCR = 0. If Counter A is
at its terminal count value at the end of the counter period of Counter B, the “running”
state (OSCR = 1) is detected.
The circuit can start without a reset and becomes defined after at least 32 pulses of
counter B. Setting bit OSC_CON.ORDRES makes it possible to start the oscillator run
detection during normal operation of the TC1796, e.g. in case of a PLL loss-of-lock
condition.

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Clock System and Control

3.2.1.3 Oscillator Gain Control

The oscillator starts with a high drive level (gain) during and after a power-on reset to
ensure safe start-up behavior in the beginning (force the crystal oscillation). When a
stable oscillation has been reached after oscillation start-up, the gain of the oscillator can
be reduced. This reduces the oscillator’s power consumption, which is especially
important in the power saving modes. This gain reduction is selected by
OSC_CON.OGC = 1.
Note: Oscillator measurement (margin or negative resistance and XTAL1 input
amplitude) for the oscillator crystal system must be executed also with reduced
gain.

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3.2.1.4 Oscillator Control Register

Note: Register OSC_CON is Endinit-protected.

OSC_CON
Oscillator Control Register (F0000018H) Reset Value: see Table 3-1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ORD OSC MOS
0 OGC 0
RES R C
r rw r rwh rh rwh

Field Bits Type Description

MOSC 0 rwh Main Oscillator Test Mode
This bit determines the mode of the main oscillator.
0B The oscillator is running. The oscillator signal
of the main oscillator or an external clock
input signal is used as fOSC.
1B The oscillator circuitry is bypassed. An
external clock input signal at XTAL1 must be
provided and is used as fOSC.
It is 1 if the BYPASS pin is high and TXD1A is zero.
Its state is latched with the rising edge of PORST.
OSCR 1 rh Oscillator Run Status Bit
This bit shows the state of the oscillator run state.
0B The oscillator is not running.
1B The oscillator is running.
The OSCR bit is valid always after a power-on reset
operation. After an oscillator run detection reset
(setting OSC_CON.ORDRES), OSCR is invalid up
to a maximum of 64 fN clock cycles.

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Clock System and Control

Field Bits Type Description

ORDRES 2 rwh Oscillator Run Detection Reset
This bit allows the oscillator run detection to start
during normal operating mode.
0B No operation
1B The oscillator run detection logic is reset and
restarted.
After ORDRES has been set, it becomes
automatically reset by hardware.
OGC 4 rw Oscillator Gain Control
This bit determines the main oscillator gain.
0B High gain is selected (default after reset).
1B Low gain is selected.
0 3, r Reserved
[31:5] Read as 0; should be written with 0.

Table 3-1 Reset Values of Register OSC_CON

Condition Function Reset
BYPASS TXD1A Values

0 X The system is driven by the PLL clock which is 0000 0000H

derived from the oscillator clock.
1 0 The system is driven directly by the external clock 0000 0001H
which is applied to XTAL1.
1 The system is driven by the crystal oscillator clock 0000 0000H
or the external clock passed through the oscillator.

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Clock System and Control

3.2.2 Phase Looked Loop (PLL) Circuitry

The PLL is a main component of the CGU that is dedicated to generate the CPU and
system clock inside the TC1796. The PLL basically converts a low-frequency external
clock signal into high-speed internal CPU and system clocks for maximum performance.
The PLL consists of a Voltage Controlled Oscillator (VCO) with a feedback path. A
divider in the feedback path (N-Divider) divides the VCO frequency down. The resulting
frequency is then compared with the externally provided and divided frequency (P-
Divider). The phase detection logic determines the difference between the two clock
signals and accordingly controls the frequency of the VCO (fVCO). During start-up, the
VCO increases its frequency until the divided feedback clock matches the external clock
frequency. A PLL lock detection unit monitors and signals this condition. The phase
detection logic continues to monitor the two clock signals and adjusts the VCO clock if
required. The CGU output clocks fCPU and fSYS are derived from the VCO clock by the K-
Divider.

3.2.2.1 Clock Source Control

The CPU clock fCPU and the system clock fSYS are generated from fOSC in one of four
hardware/software selectable modes:
• Direct Drive Mode (PLL Bypass Mode)
• VCO Bypass Mode (Prescaler Mode)
• PLL Mode
• PLL Base Mode

Direct Drive Mode (PLL Bypass Operation)

In Direct Drive Mode, the PLL is bypassed and the CGU clock outputs are directly fed
from the clock signal fOSC, i.e. fCPU = fOSC and fSYS = fOSC/2 or fOSC. This mode can be only
selected by hardware when pin BYPASS = 1 during the rising edge of PORST.

VCO Bypass Mode (Prescaler Mode)

In VCO Bypass Mode, fCPU and fSYS are derived from fOSC by the two divider stages, P-
Divider and K-Divider. This mode is selected by setting PLL_CLC.VCOBYP = 1. The
system clock fSYS can be equal to fCPU (PLL_CLC.SYSFS = 1) or equal to fCPU/2
(PLL_CLC.SYSFS = 0).

1
f CPU = -------------- × f OSC
P×K
(3.1)
fSYS = fCPU or fCPU/2

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PLL Mode
In PLL Mode, the PLL is running. The VCO clock fVCO is derived from fOSC, divided by the
P factor, multiplied by the PLL (N-Divider). This mode is selected by setting
PLL_CLC.VCOBYP = 0. Further, fCPU and fSYS are derived from fVCO by the K-Divider.
The system clock fSYS can be equal to fCPU (PLL_CLC.SYSFS = 1) or equal to fCPU/2
(PLL_CLC.SYSFS = 0).

N
f CPU = -------------- × f OSC
P×K (3.2)
fSYS = fCPU or fCPU/2

PLL Base Mode

In PLL Base Mode, the PLL is running at its VCO base frequency and fCPU and fSYS are
derived from fVCO only by the K-Divider. In this mode, PLL_CLC.VCOBYP must be 0 and
pin BYPASS must have been latched as 0 at the end of the last power-on reset
operation. In this mode, the system clock fSYS can be equal to fCPU
(PLL_CLC.SYSFS = 1) or equal to fCPU/2 (PLL_CLC.SYSFS = 0).

1
f CPU = ---- × f VCObase
K (3.3)
fSYS = fCPU or fCPU/2

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3.2.2.2 PLL Parameters

As shown in Equation (3.2) to Equation (3.3), the PLL operation depends on the setup
of up to four main PLL parameters: P-Divider, N-Divider, K-Divider, and VCO range
selection.

P-Divider
The P-Divider divides the oscillator clock fOSC by factor P for the PLL input clock fP.
Table 3-2 shows the P factor values of the P-Divider which are selected by programming
the PLL_CLC.PDIV bit field. It also lists the resulting fP frequency for some dedicated
values of fOSC but the complete range of 4 to 40 MHz can be applied and used for fOSC.
Note that the P-Divider factor is always PLL_CLC.PDIV+1.

Table 3-2 P-Divider Selections

PLL_CLC. P-Divider: Resulting fP Frequency (in MHz) for
PDIV P = PDIV+1 f fOSC = fOSC = fOSC = fOSC =
OSC =
4 MHz 10 MHz 20 MHz 30 MHz 40 MHz
0 1 4 10 20 30 40
1 2 2 5 10 15 20
2 3 1.33 3.33 6.67 10 13.3
… … … … … … …
6 7 0.57 1.43 2.857 4.286 5.7
7 8 0.5 1.25 2.5 3.75 5

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N-Divider
The N-Divider in the feedback path of the PLL divides the VCO clock fVCO by factor N for
the N-divider output clock fN. This feedback clock is used as input clock for the PLL
phase detection unit, which compares it with the PLL input clock fP. The phase detector
determines the difference between its two input clocks fP and fN and accordingly
regulates the frequency of the VCO output clock fVCO.
Table 3-3 shows the N factor values of the N-Divider which are selected by
programming the PLL_CLC.NDIV bit field. It also lists the resulting N-divider output clock
fN depending on N and dedicated VCO frequencies. Note that the N-Divider factor is
always PLL_CLC.NDIV+1. For proper operation of the PLL, only N-Divider values of 20
to 100 are allowed.

Table 3-3 N-Divider Selections

PLL_CLC. N-Divider: Resulting fN Frequency (in MHz) for
NDIV1) N = NDIV+11) f fVCO = fVCO = fVCO =
VCO =
400 MHz 500 MHz 600 MHz 700 MHz
≤ 18 ≤ 19 not allowed
19 20 20 25 30 35
20 21 19.05 23.81 28.57 33,33
21 22 18.18 22.73 27.27 31.82
… … … … … ...
97 98 4.08 5.10 6.12 7.14
98 99 4.04 5.05 6.06 7.07
992) 100 4 5 6 7
≥ 100 ≥ 101 not allowed
1) These columns include decimal values.
2) This is the default value after a power-on reset.

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K-Divider
The K-Divider divides the VCO clock fVCO by factor K for the CGU output clocks fCPU (and
fSYS). Table 3-4 shows the K factor values of the K-Divider that are selected by
programming the PLL_CLC.KDIV bit field. It also lists the resulting output clock fCPU
depending on K and dedicated VCO frequencies. Note that the K-Divider factor is always
PLL_CLC.KDIV+1. For odd K-Divider factors some restrictions for fCPUmax must be
regarded.

Table 3-4 K-Divider Selections

PLL_CLC. K-Divider: Resulting fCPU Frequency (in MHz) for fCPU
KDIV K = KDIV+1 f
VCO = 400 fVCO = fVCO = fVCO = Duty Max.
MHz 500 MHz 600 MHz 700 MHz Cycle Value
[%] [MHz]
1) 1)
0 1 400 500 600 700
1 2 200 250 300 350
2 3 133.33 166.67 200 233.33 33.33 1002)

3 4 100 125 150 175 50 150

4 5 80 100 120 140 40 1202)
5 6 66.67 83.33 100 116.67 50 150
6 7 57.14 71.43 85.71 100 42.86 1302)
7 8 50 62.5 75 87.5 50 150
8 9 44 55.56 66.67 77.78 44.44 1302)
9 10 40 50 60 70 50 150
10 11 36.36 45.45 54.55 63.64 45.45 1402)
11 12 33.33 41.67 50 58.33 50 150
12 13 30.77 38.46 46.15 53.85 46.15 1402)
13 14 28.57 35.71 42.86 50 50 150
14 15 26.67 33.33 40 46.67 46.67 1452)
153) 16 25 31.25 37.5 43.75 50 150
1) These KDIV selections are not allowed in PLL Mode of the TC1796.
2) This is a restriction in fCPUmax for odd K-divider factors.
3) This is the default value after a power-on reset.

Note: The shaded selections cannot be used because the maximum TC1796 fCPU
frequency of 150 MHz is exceeded.

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VCO Operating Range

The VCO can be selected for three operating ranges by programming the
PLL_CLC.VCOSEL bit field. Table 3-5 defines the min./max. fVCO frequency as well as
the VCO base frequency fVCObase. This is the base VCO frequency when no PLL input
clock fP is connected.

Table 3-5 VCO Operating Range Selection

Bit PLL_CLC. fVCOmin fVCOmax fVCObase1) fOSCmin2) Unit
VCOSEL
00B 400 500 approx. 140 - 320 1.5 MHz
01B 500 600 approx. 150 - 400 1.75 MHz
10B3) 600 700 approx. 200 - 480 2 MHz
11B Reserved, do not use this combination
1) fVCObase is the free-running operation frequency of the PLL when no input clock is available.
2) This is the minimum oscillator frequency to allow oscillator run detection to work properly.
3) This is the default value after a power-on reset.

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3.2.2.3 PLL Clock Control and Status Register

The PLL Clock Control and Status Register PLL_CLC is located in the address range of
the System Control Unit (see Page 5-62). It holds the hardware configuration bits of the
PLL and provides the control for the N, P and K-Dividers as well as the PLL lock status
bit. Register PLL_CLC is Endinit-protected.

PLL_CLC
PLL Clock Control Register (F0000040H) Reset Values: see Table 3-6
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYP OSC
0 0 0 NDIV
PIN DISC
r rh r rwh r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VCO SYS RES LO
PDIV 0 KDIV VCOSEL 0
BYP FS LD CK
rw r rw rw rw r rw rwh rh

Field Bits Type Description

LOCK 0 rh PLL Lock Status Flag
0B PLL is not locked (default after reset)
1B PLL is locked
RESLD 1 rwh Restart Lock Detection
Writing a 1 to this bit will clear the LOCK flag and
restart the PLL lock detection. After written with a 1,
this bit is reset automatically to 0 and therefore
always read back as 0. This bit becomes activated
with a power-on reset operation.
0B No operation
1B PLL lock detection is restarted.
SYSFS 2 rw System Frequency Select
Selects the fCPU-to-fSYS clock ratio.
0B Ratio fCPU/fSYS is 2/1 (default after reset).
1B The ratio fCPU/fSYS is 1/1.
VCOBYP 5 rw VCO Bypass Mode Selection
0B Normal operation (default after reset)
1B VCO Bypass Mode selected

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Field Bits Type Description

VCOSEL [7:6] rw VCO Range Selection
This bit field selects operating range of the VCO.
The coding is defined in Table 3-5.
KDIV [11:8] rw PLL K-Divider Selection
This bit field selects the K-Divider value. The coding
is defined in Table 3-4.
PDIV [15:13] rw PLL P-Divider Selection
This bit field selects the P-Divider value. The coding
is defined in Table 3-2.
NDIV [22:16] rw PLL N-Divider
This bit field selects the N-Divider value. The coding
is defined in Table 3-3.Note that only NDIV values
between 19D and 99D (means N-Divider values of
20D and 100D) are allowed.
OSCDISC 24 rwh Oscillator Disconnect
This bit is used to disconnect the divided fOSC clock
from the PLL in order to avoid unstable operation
due to noise or sporadic clock pulses coming from
the oscillator circuit while the PLL is still trying to
lock to invalid clock pulses.
0B Oscillator clock fOSC is connected to the PLL.
1B Oscillator clock fOSC is disconnected from the
PLL (default after reset)
This bit is set by hardware if a PLL loss-of-lock
failure is detected.
BYPPIN 29 rh Bypass Pin Status Flag
This bit indicates the state of the BYPASS input pin
as sampled with the last rising edge of PORST.
0 3, 4,12, r Reserved
23, Read as 0; should be written with 0.
[28:25],
[31:30]

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Table 3-6 Reset Values of Register PLL_CLC

Reset BYPASS Function Reset Values
Power-on 0 The system is driven by the PLL clock 0163 0F80H
reset based on the VCO base frequency.
1 The system is driven directly by the 2163 0F80H
oscillator clock output.
Other resets X Register content remains unmodified UUUU UUUUH1)
1) U = unchanged to previously programmed values.

3.2.2.4 Changing PLL Parameters

There are some restrictions that must be regarded when PLL parameters in register
PLL_CLC are modified.
• Only one parameter should be changed with a PLL_CLC register write operation
• SYSFS can be changed without precautions
• VCOBYP can be changed without precautions
• PDIV and KDIV can be switched at any time in VCO Bypass Mode. However, the
maximum operating frequency of the TC1796 must not be exceeded.
• Before changing VCOSEL, the VCO Bypass Mode must be selected.
• Before deselecting the VCO Bypass Mode, PLL lock detection must be restarted
(RESLD bit set) and then the LOCK flag must be checked for the PLL lock condition.
When LOCK is set, the VCO Bypass Mode can be deselected again.
Note: PDIV and NDIV can also be switched in PLL Mode. When changing NDIV, the
VCO clock fVCO may exceed the target frequency until the PLL becomes locked.
After changing PDIV or NDIV, wait for the PLL lock condition. This procedure is
typically used for increasing the VCO clock step-by-step.

3.2.2.5 Setting up the PLL after Reset

After reset, the system clock will be running at the VCO base frequency fVCObase divided
by factor K. Now the following actions must be executed next:
1. Wait until the oscillator is running (OSC_CON.OSCR = 1)
2. Selection of the VCO Bypass Mode (PLL_CLC.VCOBYP = 1)
3. Selecting the VCO band by programming PLL_CON.VCOSEL
4. Program the desired P, N and K values (PDIV, NDIV, and KDIV bit fields of register
PLL_CLC)
5. Connect the oscillator to the PLL, default after reset (PLL_CLC.OSCDISC = 0)
6. Wait until the PLL becomes locked (PLL_CLC.LOCK = 1)
7. Disable the VCO Bypass Mode (PLL_CLC.VCOBYP = 0)

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After this procedure, the device is operating on the PLL target frequency. The note in
Section 3.2.2.4 is also valid for this procedure.

3.2.2.6 Lock Detection

The PLL has the capability to detect a failure of its input clock fP and to bring the TC1796
into a safe state in such a case. This clock failure detection is done by the PLL lock
detection unit. This unit indicates whether the PLL has reached its target frequency
properly or not.
The lock detection unit operates as follows:
Two counters, A and B, count the clock pulses of the N-divider clock output fN and the
PLL reference clock fP. When the counter values differ by more than 2 during counting,
the counters are reset (meaning PLL is still unlocked). When the counter values reach
the end of a counting session (224 clock pulses) with a counting difference which is 2 or
less than 2, the PLL is locked (PLL_CLC.LOCK = 1).
When the PLL is locked, the two counters proceed to count clock pulses. After every
fourth clock pulse, the counter values are checked, and when the counter values differ
by more than 2, the unlocked state is entered (fast unlock check). If no unlock condition
is detected (counter difference less than or equal 2), the counters are further
incremented up to a maximum counter value of 232 clock pulses. After 232 clock pulses
with no unlock condition of the counter values, the two counters are reset (slow unlock
check).
The PLL may become unlocked, caused by a break of the crystal or the external clock
line. In such a case, an NMI trap is generated by setting the NMISR.PLLNMI flag.
Additionally, the PLL clock input fP is disconnected from the PLL to avoid unstable
operation due to noise or sporadic clock pulses coming from the oscillator circuit. Without
a clock input fP, the PLL gradually slows down to its VCO base frequency and remains
there. The TC1796 remains in this state until the next power-on reset through pin
PORST, after that the PLL tries to restart and lock to the external clock again. No other
reset cause can terminate this loss-of-clock state. This is done to avoid unstable
operation due to the PLL trying to lock again. The TC1796 remains in the PLL unlocked
state until the next power-on reset or a successful lock recovery occurs.
Note that the PLL unlock state can also be entered when the oscillator disconnect bit
PLL_CLC.DISC becomes set by software.

3.2.2.7 Loss-of-Lock Recovery

If PLL has lost the lock condition, user software can try to re-lock the PLL again by
executing the following sequence:
1. Restart the oscillator run detection by setting bit OSC_CON.ORDRES
2. Wait until OSCR is set

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3. If bit OSCR is set, then

Select the VCO Bypass Mode (PLL_CLC.VCOBYP = 1)
Re-connect the oscillator to the PLL (PLL_CLC.OSCDISC = 0)
Set the restart lock detection bit PLL_CLC.RESLD = 1
Wait until the PLL becomes locked (PLL_CLC.LOCK = 1)
When the PLL_CLC.LOCK is set again, the VCO Bypass Mode can be deselected
(PLL_CLC.VCOBYP = 0) and normal PLL operation is resumed.
The note in Section 3.2.2.4 is also valid for this procedure.

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3.2.3 Power-on Startup Operation

In order to support a wide range of input clock frequencies, the TC1796 requires a
generic procedure to start-up the system clock.
When the TC1796 is powered up, a low level (0) must be applied to the power-on reset
pin, PORST. While PORST is active (at low level), the device is asynchronously held in
reset and the state of the BYPASS pin controls the operation of the clock circuitry.
Therefore, BYPASS must be held at constant level during PORST active.
If the BYPASS pin is at a high level during power-on reset, Direct Drive Mode is selected
(see Page 3-10). The low level at pin PORST has to be held long enough to make sure
that a stable clock is provided to the TC1796. In case of an external crystal oscillator, it
can take several ms until the oscillator has started up and is stable. If the clock input is
provided by another clock source with faster startup characteristics, the PORST low level
can be released earlier.
If the BYPASS pin is at low level during power-on reset, PLL Mode is selected (see
Page 3-11) and the procedure to start-up the PLL is as described in the next paragraph.
With PORST = 0, the oscillator is disconnected from the PLL. The PLL starts running at
the VCO base frequency fVCObase. After deactivation of the PORST, the CPU and system
clock are provided internally with a frequency that is equal to fVCObase/K (K = 16 after
reset). This means that in the TC1796, the Boot ROM code execution is started with the
VCO base frequency. When the oscillator is running properly, bit OSCR becomes set
and the user software can setup the PLL by programming its parameters as described
in Section 3.2.2.4. If OSCR becomes not set, the user software has the possibility to run
an emergency program using the base frequency of the PLL divided by K. In this case,
K can be set to the minimum value, which results in the maximum possible CPU and
system frequency.
Note: See also Page 4-7 for further details on the power-on reset operation.

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3.3 Module Power Management and Clock Gating

Because power dissipation is related to the frequency of gate transitions, the TC1796
performs power management principally by clock gating – that is, controlling whether the
clock is supplied to its various functional units. Gating off the clock to unused functional
modules also reduces electro-magnetic interference (EMI) since EMI is related to both
the frequency and the number of gate transitions.
Clock gating is done either dynamically or statically. Dynamic clock gating in this context
means that the TC1796 itself enables or disables clock signals within some functional
modules to conserve power. Static gating means that software must enable or disable
clock signals to functional modules. Clock gating is performed differently at different
levels of system scope: Dynamic gating is generally performed at the lowest levels,
either within a small region of logic, or at functional-unit boundaries for uncomplicated
functions where hardware can dynamically determine whether that functionality is
required, and can enable or disable it appropriately without software intervention. Static
gating - which requires software intervention - is used to enable or disable clock delivery
to individual high-level functional units, or to disable clock delivery globally at the clock’s
source. When the clock to individual functional units is gated off, they are said to be in
Sleep Mode.
The TC1796 implements three levels of clock gating:
1. Gated dynamically at the register:
The clock is shut off to a particular local resource in a functional module when this
resource is not being used in that clock cycle. This operation is done primarily in the
CPU and the PCP data paths, where unused resources are easily identified and
controlled in each clock cycle.
2. Gated dynamically at the functional unit (Idle Mode):
The clock is shut off at the functional unit boundary when the unit has nothing useful
to do. This operation is done primarily in the CPU and the PCP. For the CPU, idle
mode is controlled via software. The PCP disables its own clock when no program is
running.
3. Gated statically at each functional unit (Sleep Mode):
Software can send a global sleep request to individual functional units requesting that
they enter Sleep Mode. Software must determine when conditions are such that
entering Sleep Mode is appropriate. The individual units can be programmed to
ignore or respond to this signal. If programmed to respond, units will first complete
pending operations, then will shut off their own clocks according to their own criteria.

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3.3.1 Module Clock Generation

As shown in Figure 3-5, module clock generation of the TC1796 on-chip modules have
two registers implemented:
• Clock Control Register CLC
• Fractional Divider Register FDR
The following sections describes the general functionality of CLC and FDR. The module-
specific implementation details are described in the corresponding module chapters.

Module Clock Generation

fCLC (CLC Clock)

fSYS Fractional fMOD (Module Clock)

Clock Control fCLC Divider
Sleep Mode Register Register Reset External
Request & Control Divider
Fast Shut-off Disable Req. MODDISREQ Kernel Disable
Request Request
Disable Ack. SPNDACK SPND

Kernel Disable
Debug
Acknowledge
Suspend
Request MCA05603

Figure 3-5 Module Clock Generation

Module clock and CLC clock are both derived from the system clock fSYS. The CLC
register provides the fCLC clock which acts as clock input for the fractional divider and
control logic. The CLC clock fCLC is typically used by a peripheral module for clocking its
FPI Bus interface and registers, while the module clock fMOD is dedicated for kernel
operation or timer clocks. The output signal RST_EXT_DIV makes it possible to
enable/disable external divider stages which are connected to the module clock fMOD.
The fractional divider divides the fCLC either by the factor 1/n or by a fraction of n/1024
for any value of n from 0 to 1023.
Furthermore, the module clock generation unit handles the sleep mode request signal,
the fast shut-off request signal, and the debug suspend request signal.

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3.3.2 Clock Control Register CLC

All CLC registers have basically the same bit and bit field layout. However, not all CLC
register functions are implemented for each peripheral unit. Table 3-9 defines in detail
which bits and bit fields of the CLC registers are implemented for each clock control
register.
The CLC register controls the generation of the peripheral module clock which is derived
from the system clock. The following functions for the module are associated with the
CLC register:

• Peripheral clock static on/off control

• Module clock behavior in Sleep Mode
• Operation during Debug Suspend Mode
• Fast Shut-off Mode control

MOD_CLC
Clock Control Register (00H) Reset Value: Module-specific
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS SB E SP DIS DIS
RMC 0
OE WE DIS EN S R
rw r rw w rw rw rh rw

Field Bits Type Description

DISR 0 rw Module Disable Request Bit
Used for enable/disable control of the module.
0B Module disable is not requested
1B Module disable is requested
DISS 1 rh Module Disable Status Bit
Bit indicates the current status of the module
0B Module is enabled
1B Module is disabled
If the RMC field is implemented and if it is 0, DISS is set
to 1 automatically.

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Field Bits Type Description

SPEN 2 rw Module Suspend Enable
Used for enabling the suspend mode.
0B Module cannot be suspended
(suspend is disabled).
1B Module can be suspended (suspend is enabled).
This bit can be written only if SBWE is set to 1 during
the same write operation.
EDIS 3 rw Sleep Mode Enable Control
Used for module sleep mode control.
0B Sleep mode request is regarded. Module is
enabled to go into sleep mode.
1B Sleep mode request is disregarded: Sleep mode
cannot be entered on a request.
SBWE 4 w Module Suspend Bit Write Enable for OCDS
Determines whether SPEN and FSOE are write-
protected.
0B Bits SPEN and FSOE are write-protected
1B Bits SPEN and FSOE are overwritten by
respective value of SPEN or FSOE
This bit is a write-only bit. The value written to this bit is
not stored. Reading this bit returns always 0.
FSOE 5 rw Fast Switch Off Enable
Used for fast clock switch-off in OCDS suspend mode.
0B Clock switch-off in OCDS suspend mode via
Disable Control Feature (Secure Clock Switch
Off) selected
01B Fast clock switch off in OCDS suspend mode
selected
This bit can be written only if SBWE is set to 1 during
the same write operation.
RMC [15:8] rw 8-Bit Clock Divider Value in RUN Mode
This is a maximum 8-bit divider value for clock fSYS.
If RMC is set to 0 the module is disabled.
0 7, 6, r Reserved
[31:16] Read as 0; should be written with 0.

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Module Enable/Disable Control

If a module is not used at all by an application, it can be completely shut off by setting bit
DISR in its CLC register. For peripheral modules with a run mode clock divider field
RMC, a second option to completely switch off the module is to set bit field RMC to 00H.
This also disables the module’s operation.
The status bit DISS always indicates whether a module is currently switched off
(DISS = 1) or switched on (DISS = 0). With a few exceptions (e.g. EBU_CLC), the
default state of a peripheral module after reset is “module disabled” with DISS set (see
Table 3-9).
Write operations to the registers of disabled modules are not allowed. However, the CLC
of a disabled module can be written. An attempt to write to any of the other writable
registers of a disabled module except CLC will cause the corresponding Bus Control Unit
(BCU) to generate a bus error.
A read operation of registers of a disabled module (except CAN) is allowed and does not
generate a bus error.
When a disabled module is switched on by writing an appropriate value to its MOD_CLC
register (DISR = 0 and RMC (if implemented) > 0), status bit DISS changes from 1 to 0.
During the phase in which the module becomes active, any write access to
corresponding module registers (when DISS is still set) will generate a bus error.
Therefore, when enabling a disabled module, application software should check after
activation of the module once (read back of the CLC register) to find out whether DISS
is already reset, before a module register (including the CLC register) will be written to.
Note: A read access occurring while a module is disabled is treated as a normal read
access. This means, if a module register or a bit of it is cleared as a side-effect of
a read access of an enabled module, it will not be cleared by this read access
while the module is disabled.

Sleep Mode Control

The EDIS bit in the CLC register controls whether or not a module is stopped during
sleep mode. If EDIS is 0 (default after reset), a sleep mode request can be recognized
by the module and, when received, its clock is shut off.
If EDIS is set to 1, a sleep mode request is disregarded by the module and the module
continues its operation.

Debug Suspend Mode Control

During emulation and debugging of TC1796 applications, the execution of an application
program can be suspended. When an application is suspended, normal operation of the
application’s program is halted, and the TC1796 begins (or resumes) executing a special
debug monitor program. When the application is suspended, a suspend request signal
is generated by the TC1796 and sent to all modules. If bit SPEN is set to 1, the operation

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of the peripheral module is stopped when the suspend signal is asserted. If SPEN is set
to 0, the module does not react to the suspend request signal but continues its normal
operation. This feature allows each peripheral module to be adapted to the unique
requirements of the application being debugged. Setting SPEN bits is usually performed
by a debugger.
This feature is necessary because application requirements typically determine whether
on-chip modules should be stopped or left running when an application is suspended for
debugging. For example, a peripheral unit that is controlling the motion of an external
device through motors in most cases must not be stopped so as to prevent damage of
the external device due to the loss of control through the peripheral. On the other hand,
it makes sense to stop the system timer while the debugger is actively controlling the chip
because it should only count the time when the user’s application is running.
Note that it is never appropriate for application software to set the SPEN bit. The debug
suspend mode should only be set by a debug software. To guard against application
software accidently setting SPEN, bit SPEN is specially protected by the mask bit
SBWE. The SPEN bit can only be written if, during the same write operation, SBWE is
set, too. Application software should never set SBWE to 1. In this way, user software can
not accidentally alter the value of the SPEN bit that has been set by a debugger.
Note: The operation of the Watchdog Timer is always automatically stopped in debug
suspend mode.

Entering Disabled Mode

Software can request that a peripheral unit be put into Disabled Mode by setting DISR.
A module will also be put into Disabled Mode if the sleep mode is requested and the
module is configured to allow Sleep Mode.
In Secure Shut-off Mode, a module first finishes any operation in progress, then
proceeds with an orderly shut down. When all sub-components of the module are ready
to be shut down, the module signals its clock control unit, which turns off the clock to this
peripheral unit, that it is now ready for shut down. The status bit DISS is updated by the
peripheral unit accordingly.
The kernel logic of the peripheral unit and its FPI Bus interface must both perform shut-
down operations before the clock can be shut off in Secure Shut-off Mode. This is
performed as follows. The peripheral module’s FPI Bus interface provides an internal
acknowledge signal as soon as any current bus interface operation is finished. For
example, if there is a DMA write access to a peripheral in progress when a disable
request is detected, the access will be terminated correctly. Similarly, the peripheral’s
kernel provides an internal acknowledge signal when it has entered a stable state. The
clock control unit for that peripheral module shuts off the module’s clock when it receives
both acknowledge signals.
During emulation and debugging, it may be necessary to monitor the instantaneous state
of the machine – including all or most of its modules – at the moment a software

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breakpoint is reached. In such cases, it may not be desired that the kernel of a module
finish whatever transaction is in progress before stopping, because that might cause
important states in this module to be lost. Fast Shut-off Mode, controlled by bit FSOE, is
available for this situation.
If FSOE = 0, modules are stopped as described above. This is called Secure Shut-off
Mode. The module kernel is allowed to finish whatever operation is in progress. The
clock to the unit is then shut off if both the bus interface and the module kernel have
finished their current activity. If Fast Shut-off Mode is selected (FSOE = 1), clock
generation to the unit is stopped as soon as any outstanding bus interface operation is
finished. The clock control unit does not wait until the kernel has finished its transaction.
This option stops the unit’s clock as fast as possible, and the state of the unit will be the
closest possible to the time of the occurrence of the software breakpoint.
Note: In all TC1796 modules except MultiCAN and DMA, the only shut down operating
mode that is available is the Fast Shut-off ModeTC1796, regardless of the state of
the FSOE bit.
Whether Secure Shut-off Mode or Fast Shut-off Mode is required depends on the
application, the needs of the debugger, and the type of unit. For example, the analog-to-
digital converter might allow the converter to finish a running analog conversion before
it can be suspended. Otherwise the conversion might be corrupted and a wrong value
could be produced when Debug Suspend Mode is exited and the unit is enabled again.
This would affect further emulation and debugging of the application’s program.
On the other hand, if a problem is observed to relate to the operation of the external
analog-to-digital converter itself, it might be necessary to stop the unit as fast as possible
in order to monitor its current instantaneous state. To do this, the Fast Shut-off Mode
option would be selected. Although proper continuation of the application’s program
might not be possible after such a step, this would most likely not matter in such a case.
Note that it is never appropriate for application software to set the FSOE bit. Fast Shut-
off Mode should only be set by debug software. To guard against application software
accidently setting FSOE, bit FSOE is specially protected by the mask bit SBWE. The
SPEN bit can only be written if, during the same write operation, SBWE is set, too.
Application software should never set SBWE to 1. In this way, user software can not
accidentally alter the value of the FSOE bit. Note that this is the same guard mechanism
used for the SPEN bit.

Module Clock Divider Control

Two peripheral modules of the TC1796, ASC0_CLC and STM_CLC, have a RMC control
bit field in their CLC registers. This Run Mode Clock control bit field makes it possible to
slow down the CLC clock via a programmable clock divider circuit.

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A value of 00H in RMC disables the clock signals to these modules (CLC clock is
switched off). If RMC is not equal to 00H, the CLC clock for a unit is generated as

fCLC = fSYS / RMCMOD (3.4)

where RMC is the content of its CLC register RMC field with a range of 1 to 255. If RMC
is not available in a CLC register, the CLC clock frequency fCLC is always equal to the
frequency of fSYS.
Note: The number of module clock cycles (wait states) that are required for a
“destructive read” access (means: flags/bits are set/cleared by a read access) to
a module register of a peripheral unit depends on the selected CLC clock
frequency.
Therefore, a slower CLC clock (selected via bit field RMC in the CLC register) may
result in a longer read cycle access time on the FPI Buses for peripheral units with
“destructive read” access (e.g. the ASC).

3.3.3 Fractional Divider Operation

This section describes the module clock generation using the Fractional Divider.

3.3.3.1 Overview
The fractional divider makes it possible to generate a module clock from an input clock
using a programmable divider. The fractional divider divides the input clock fIN either by
the factor 1/n or by a fraction of n/1024 for any value of n from 0 to 1023, and outputs the
clock signal, fOUT. The fractional divider is controlled by the FDR register. Figure 3-6
shows the fractional divider block diagram.
The adder logic of the fractional divider can be configured for two operating modes:
• Reload counter (addition of +1), generating an output clock pulse on counter overflow
• Adder that adds a STEP value to the RESULT value and generates an output clock
pulse on counter overflow

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STEP (10-bit)

Mux Fractional
Divider

Adder

Mux

&
RESULT (10-bit) fOUT

fIN fOUT
Enable
Debug Suspend Request Reset External
Debug Suspend Acknowledge Divider
Control
External Clock Enable Kernel Disable
Request
Module Disable Request

MCB05604

Figure 3-6 Fractional Divider Block Diagram

The adder logic of the fractional divider can be configured for two operating modes:
• Normal Mode: Reload counter (RESULT = RESULT + 1), generating an output
clock pulse on counter overflow.
• Fractional Divider Mode: Adder that adds a STEP value to the RESULT value and
generates an output clock pulse on counter overflow.
The fractional divider is further controlled by several input and output signals. The
purpose of these signals is described in Table 3-7.

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Table 3-7 Fractional Divider Control I/O Lines

Signal I/O Description
Debug Suspend Input This input becomes active when a general suspend
Request request is issued from the debug system to the on-chip
modules.
Debug Suspend This input is driven with the disable acknowledge signal
Acknowledge from the module kernel. This disable acknowledge signal
is activated by the module kernel as a response to a
suspend request that has been generated by the fractional
divider via the Kernel Disable Request signal.
External Clock This input can be used to synchronize the fractional
Enable divider clock generation to external events.
Module Disable This input is connected to the disable request output from
Request the CLC logic (see Figure 3-5). An active signal at this
input activates the Kernel Disable Request signal.
Kernel Disable Output This output signal becomes active when either the Module
Request Disable Request input or the Debug Suspend Request
input become active.
Reset External This output signal makes it possible to control (stop/reset)
Divider external divider stages which have fOUT as input.

Note: In the TC1796, the fractional divider input clock fIN is also referred to as fCLC and
the fractional divider input clock fOUT is also referred to as fMOD (see Figure 3-5).

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3.3.3.2 Fractional Divider Operating Modes

The fractional divider has two operating modes:
• Normal divider mode
• Fractional divider mode

Normal Divider Mode

In normal divider mode (FDR.DM = 01B), the fractional divider behaves as a reload
counter (addition of +1) that generates an output clock pulse at fOUT on the transition from
3FFH to 000H. FDR.RESULT represents the counter value and FDR.STEP determines
the reload value.
The output frequencies in normal divider mode are defined according to the following
formulas:

1 (3.5)
fOUT = fIN × --- , with n = 1024 - STEP
n

In order to get fOUT = fIN STEP must be programmed with 3FFH. Figure 3-7 shows the
operation of the normal divider mode with a reload value of FDR.STEP = 3FDH. The
clock signal fOUT is the AND combination of the fOUT Enable signal with fIN.

STEP 3FD 3FD 3FD

Reload Reload Reload

RESULT 3FF 3FD 3FE 3FF 3FD 3FE 3FF 3FD 3FE

fIN

fOUT
Enable

fOUT
MCT05605

Figure 3-7 Normal Mode Timing

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Fractional Divider Mode

When the fractional divider mode is selected (FDR.DM = 10B), the output clock fOUT is
derived from the input clock fIN by division of a fraction of n/1024 for any value of n from
0 to 1023. In general, the fractional divider mode makes it possible to program the
average output clock frequency with a higher accuracy than in normal divider mode.
In fractional divider mode, an output clock pulse at fOUT is generated depending on the
result of the addition FDR.RESULT + FDR.STEP. If the addition leads to an overflow
over 3FFH, a pulse is generated at fOUT. Note that in fractional divider mode the clock fOUT
can have a maximum period jitter of one fIN clock period.
The output frequencies in fractional divider mode are defined according to the following
formulas:

n
f OUT = f IN × ------------- , with n = 0-1023 (3.6)
1024

Figure 3-8 shows the operation of the fractional divider mode with a reload value of
FDR.STEP = 234H (= factor 564/1024 = 0.55). The clock signal fOUT is the AND
combination of the fOUT Enable signal with fIN.

STEP = 234 H : fOUT = 0.55 x fIN

fIN

RESULT 150 384 1B8 3EC 220 054 288 0BC 2F0 124 358 18C 3C0

+234 +234 +234 +234 +234 +234 +234 +234 +234 +234 +234 +234 +234

fOUT
Enable

fOUT
MCT05606

Figure 3-8 Fractional Divider Mode Timing

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Suspend Mode Control

The operation of the fractional divider can be controlled by the Debug Suspend Request
input. This input is activated in suspend mode by the on-chip debug control logic. In
suspend mode, module registers are accessible for read and write actions, but other
module internal functions are frozen. Suspend mode is entered one fIN clock cycle after
the Debug Suspend Request has been acknowledged by the Debug Suspend
Acknowledge signal (granted suspend mode) and FDR.SC is not equal 00B (clock output
signal disabled). Suspend mode is immediately entered when bit SM is set to 1 and
FDR.SC is not equal 00B (immediate suspend mode).
The state of the Debug Suspend Request and Debug Suspend Acknowledge signal is
latched in two status flags of register FDR, SUSREQ and SUSACK. Debug Suspend
Request and (Debug Suspend Acknowledge or bit SM) must remain set both to maintain
the suspend mode.

Debug Suspend
Acknowledge Fractional Divider
Debug Suspend
Request Register FDR
SUS SUS
REQ ACK SC SM

≥1
switch
& fOUT off
SC not
equal 00B &

≥1 Kernel Disable
Module Disable Request
Request

MCA05607

Figure 3-9 Suspend Mode Configuration

The Kernel Disable Request signal becomes always active when the Module Disable
Request signal is activated, independently of the suspend mode settings in the fractional
divider logic.

External Clock Enable

When the module clock generation has been disabled by software (setting
FDR.DISCLK = 1), the disable state can be exited (hardware controlled) when the
External Clock Enable input = 1. This feature is enabled when FDR.ENHW = 1.

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3.3.3.3 Fractional Divider Register

FDR
Fractional Divider Register Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS EN SUS SUS
0 RESULT
CLK HW REQ ACK
rwh rw rh rh r rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM SC SM 0 STEP

rw rw rw r rw

Field Bits Type Description

STEP [9:0] rw Step Value
In normal divider mode, STEP contains the reload
value for RESULT.
In fractional divider mode, this bit field determines
the 10-bit value that is added to RESULT with each
input clock cycle.
SM 11 rw Suspend Mode
SM selects between granted or immediate suspend
mode.
0B Granted suspend mode selected
1B Immediate suspend mode selected

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Field Bits Type Description

SC [13:12] rw Suspend Control
This bit field determines the behavior of the fractional
divider in suspend mode (bit SUSREQ and SUSACK
set).
00B Clock generation continues.
01B Clock generation is stopped and the clock
output signal is not generated. RESULT is not
changed except when writing bit field DM with
01B or 10B.
10B Clock generation is stopped and the clock
output signal is not generated. RESULT is
loaded with 3FFH.
11B Same as SC = 10B but signal Reset External
Divider is 1 (independently of bit field DM).
DM [15:14] rw Divider Mode
This bit fields determines the functionality of the
fractional divider block.
00B Fractional divider is switched off; no output
clock is generated. The Reset External Divider
signal is 1. RESULT is not updated (default
after reset).
01B Normal divider mode selected.
10B Fractional divider mode selected.
11B Fractional divider is switched off; no output
clock is generated. RESULT is not updated.
RESULT [25:16] rh Result Value
In normal divider mode, RESULT acts as reload
counter (addition +1).
In fractional divider mode, this bit field contains the
result of the addition RESULT + STEP.
If DM is written with 01B or 10B, RESULT is loaded
with 3FFH.
SUSACK 28 rh Suspend Mode Acknowledge
0B Suspend mode is not acknowledged.
1B Suspend mode is acknowledged.
Suspend mode is entered when SUSACK and
SUSREQ are set.

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Field Bits Type Description

SUSREQ 29 rh Suspend Mode Request
0B Suspend mode is not requested.
1B Suspend mode is requested.
Suspend mode is entered when SUSREQ and
SUSACK are set.
ENHW 30 rw Enable Hardware Clock Control
0B Bit DISCLK cannot be cleared by hardware by
a high level of the External Clock Enable input
signal.
1B Bit DISCLK is cleared by hardware while the
External Clock Enable input signal is at high
level.
DISCLK 31 rwh Disable Clock
0B Clock generation of fOUT is enabled according
to the setting of bit field DM.
1B Fractional divider is stopped. Signal fOUT
becomes inactive. No change except when
writing bit field DM.
In case of a conflict between hardware clearing and
software setting of DISCLK, the software setting
wins. Any write or read-modify-write action leads to
the described behavior. As a result, read-modify-
write operations should be avoided.
0 10, r Reserved
[27:26] Read as 0; should be written with 0.

Note: See also Table 3-8 for further functional behavior of FDR bit fields and module
operation.
Note: The Fractional Divider Registers are Endinit-protected.

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Table 3-8 Fractional Divider Function Table

Mode SC DM Reset Ext. Result fOUT Operation of
Divider Fractional
Signal Divider
Normal – 00B 1 unchanged inactive switched off
Mode 01B 0 continuously active normal divider
updated1) mode
10B fractional divider
mode
11B unchanged inactive switched off
Suspend 00B 00B 1 unchanged inactive switched off
Mode 01B 0 continuously active normal divider
updated1) mode
10B fractional divider
mode
11B unchanged inactive switched off
01B 00B 1 unchanged switched off
01B 0 loaded with halted
10B 3FFH

11B unchanged inactive switched off

10B 00B 1 loaded with inactive switched off
01B 0 3FFH halted
10B
11B switched off
11B – 1 loaded with inactive switched off
3FFH
1) Each write operation to FDR with DM = 01B or 10B sets RESULT to 3FFH.

Implementation
FDR registers are implemented for several modules of the TC1796. The name of these
FDR registers is always preceded by the module name (e.g. SSC0_FDR is the FDR
register for the SSC0 module). Table 3-9 defines which module is equipped with a FDR
register.
In the implementation parts of the modules using a fractional divider (see Table 3-9), the
signal fOUT is described as a clock signal and not as clock enable signal.

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3.3.4 Module Clock Register Implementations

Table 3-9 shows which of the CLC register bits/bit fields are implemented for each
peripheral module in the TC1796 and which modules are equipped with a fractional
divider.

Table 3-9 Clock Generation Implementation of the TC1796 Peripheral Modules

Module DISR DISS SPEN EDIS SBWE FSOE RMC Fract.
Name State Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Divider
1)
after
Reset
ADC0 off ✔ ✔ ✔ ✔ ✔ ✔ – ✔
ADC1
FADC off ✔ ✔ ✔ ✔ ✔ ✔ – ✔
ASC0 and off ✔ ✔ ✔ ✔ ✔ ✔ 8-bit –
ASC1
SSC0 off ✔ ✔ ✔ ✔ ✔ ✔ – ✔
SSC1 off ✔ ✔ ✔ ✔ ✔ ✔ – ✔
MultiCAN off ✔ ✔ ✔ ✔ ✔ ✔ – ✔
DMA on ✔ ✔ ✔ ✔ ✔ ✔ – –
EBU on ✔ ✔ – – – – – –
GPTA0 off ✔ ✔ ✔ ✔ ✔ ✔ – ✔
GPTA1
LTCA2
MLI0 off not implemented, MLI is connected to DMA_CLC ✔
MLI1 off not implemented, MLI is connected to DMA_CLC ✔
MSC0 off ✔ ✔ ✔ ✔ ✔ ✔ – ✔
MSC1 off ✔ ✔ ✔ ✔ ✔ ✔ – ✔
PCP2 off different bit definitions2)
PLL on different bit definitions – –
STM on ✔ ✔ ✔ ✔ ✔ ✔ 3-bit –
1) Further info on FDR implementations see Table 3-10.
2) Automatic clock switch-off capability if PCP is idle.

Note: The ports of the TC1796, SCU, and WDT do not provide CLC registers.

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3.3.5 Fractional Divider Register Implementations

Table 3-10 shows the implementations specific differences of the fractional divider
functionalities.

Table 3-10 FDR Register Implementations

FDR Register Suspend Mode Acknowledge ENHW2) Reset Ext.
Operation1) Divider3)
CAN_FDR Acknowledge depends on module state – –
ADC0_FDR Acknowledge depends on module – resets analog
states parts of
ADCs
FADC_FDR Acknowledge depends on module state – –
GPTA0_FDR Always immediately acknowledged; from –
independently from module states MultiCAN
MLI0_FDR Acknowledge depends on module state – –
MLI1_FDR Acknowledge depends on module state – –
MSC0_FDR Acknowledge depends on module state from –
MultiCAN
MSC1_FDR Acknowledge depends on module state from –
MultiCAN
SSC0_FDR Always immediately acknowledged; from –
independently from module state MultiCAN
SSC1_FDR Always immediately acknowledged; from –
independently from module state MultiCAN
SCU_SCLKFDR Always immediately acknowledged; – external
independently from module state divider-by-2
1) This column shows whether a suspend acknowledge from a FDR controlled module depends on the module’s
state or not. If a suspend acknowledge depends from the module state, typically module operations such as
serial transmissions are terminated before a suspend request is acknowledged back to the fractional divider.
Note that bit FDR.SM must be cleared (granted suspend mode selected) when using the suspend mode
acknowledge/grant functionality. If immediate suspend mode is selected (FDR.SM = 1), suspend mode is
entered at once (if FDR.SC not equal 00B) independently from the suspend acknowledge answer from the
module.
2) This column shows whether the External Clock Enable input of a fractional divider is controlled by on-chip
hardware (source module see comment) or not (“–”).
3) This column shows whether the Reset External Divider output of the fractional divider is used (purpose see
comment) or not (“–”).

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3.4 System Clock Output Control

The System Clock SYSCLK (alternate function of GPIO port line P1.12) is generated by
a fractional divider block with a subsequent divide-by-2 stage (see Figure 3-10). This
allows the SYSCLK frequency to be highly independent from the system frequency.
Furthermore, the SYSCLK signal has duty cycle of 50% (with a small period jitter). After
reset, SYSCLK is at low level when the Reset External Divider signal is at 1 (fractional
divider stopped).

SYSCLK Generation

fIN
fSYS Fractional fSYSCLK
P1.12 /
Divider fOUT 2
SYSCLK
Register
Enable
MultiCAN CAN_INT_O15 ECEN Reset Ext.
SCU_SCLKFDR
Module Divider

MCA05608

Figure 3-10 SYSCLK Generation

In normal divider mode, fSYSCLK has a duty cycle of approximately 50%. The output
frequency of fSYSCLK in normal divider mode is defined according to the following formula:

f
fSYSCLK = fOUT ⁄ 2 = SYS
------------------- , with n = 1024 - STEP (3.7)
2×n

In fractional divider mode, fOUT is derived from the input clock fIN by division of a fraction
of n/1024 for any value of n from 0 to 1023. In general, the fractional divider mode makes
it possible to program the average output clock frequency with a higher accuracy than in
normal divider mode. Note that in fractional divider mode, the clock fOUT can have a
maximum period jitter of one fIN clock period (fSYSCLK has a maximum period jitter of one
half fIN clock period).
The output frequency of fSYSCLK in fractional divider mode is defined according to the
following formula:

n -
fSYSCLK = fOUT ⁄ 2 = fSYS × --------------------------------- , with n = 0-1023 (3.8)
2 × 1024

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3.4.1 System Clock Fractional Divider Register

SCU_SCLKFDR
SCU System Clock Fractional Divider Register
(F000000CH) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS EN SUS SUS
0 RESULT
CLK HW REQ ACK
rwh rw rh rh r rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM SC SM 0 STEP

rw rw rw r rw

Field Bits Type Description

STEP [9:0] rw Step Value
Reload or addition value for RESULT.
SM 11 rw Suspend Mode
SM selects granted or immediate suspend mode.
DM [15:14] rw Divider Mode
DM selects normal or fractional divider mode.
SC [13:12] rw Suspend Control
SC determines the behavior of the fractional divider
in suspend mode.
RESULT [25:16] rh Result Value
Bit field for the addition result.
SUSACK 28 rh Suspend Mode Acknowledge
Indicates state of SPNDACK signal.
SUSREQ 29 rh Suspend Mode Request
Indicates state of SPND signal.
ENHW 30 rw Enable Hardware Clock Control
No function for SYSCLK generation. Should be
written with 0, will read back the last value written
DISCLK 31 rwh Disable Clock
Makes it possible to disable the clock generation
independently of the setting of the other functions

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Field Bits Type Description

0 10, r Reserved
[27:26] Read as 0; should be written with 0.

Note: This is only a short summary of the fractional divider behavior. The details on the
fractional divider register functionality are described on Page 3-29.

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Reset and Boot Operation

4 Reset and Boot Operation

This chapter describes the conditions under which the TC1796 will be reset, the reset
and boot operations, and the available boot options.

4.1 Reset and Boot Overview

When the TC1796 device is first powered up, several boot parameters such as the start
location of the code have to be defined to enable proper start operation of the device. To
accommodate this, the device has a separate Power-On Reset (PORST) pin and a
number of configuration pins which are sampled during the power-on reset sequence or
the hardware reset. At the end of this sequence, the sampled values are latched, and
can not be modified until the next power-on reset. This guarantees stable conditions
during the normal operation of the device.
To reset the device while it is operating, two options exist. For reset causes coming from
the external world, a reset input pin, HDRST, is provided. If software detects conditions
that require to reset the device, it can perform a software reset through writing to a
special register, the Reset Request (RST_REQ) register.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system. If the WDT is not serviced correctly and/or not serviced in
time, it first generates an NMI request to the CPU (this allows the CPU to gather debug
information), and then resets the device after a predefined time-out period.
After a reset has been executed, the Reset Status (RST_SR) register provides
information on the type of the last reset and the selected boot configuration.
The external reset pin, HDRST, has a double-function. It serves as a reset input from the
external world to reset the device, and it serves as a reset output to the external world to
indicate that the device has executed a reset. For this purpose, pin HDRST is
implemented as a bi-directional open-drain pin with an internal weak pull-up device.
Please note, that any reset pulse generated on HDRST will be prolonged to reach a
minimum pulse width. This ensures proper system reset, even it is caused by a very
short pulse on HDRST coming from the system.
The boot configuration information required by the device to perform the desired start
operation after a power-up reset includes the start location for the code execution, and
the activation of special modes. This information is supplied to the chip via a number of
dedicated input pins that are sampled and latched with the hardware reset HDRST or the
power-on reset PORST. However, the software reset provides the special option to alter
these parameters to allow a different start configuration after the software reset has
finished.
Attention: To ensure safe operation, the power-on reset operation must be
completed prior to utilisation of the chip. With a completed power-on
reset operation, a sequence of initialization of the chip is executed

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which includes the initialization of the ICACHE and TagRAM memories

in the PMI. In the emulation device, the EEC is initialized upon
thecompletion of a power-on reset. Therefore, activation of the HDRST
signal earlier than the maximum Power-on Reset Boot Time must be
prevented. Please refer to the maximum Power-on Reset Boot Time
defined in the Power, Pad and Reset Timing section of the TC1796 Data
Sheet.

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4.1.1 Reset Status and Control Registers

The Reset Status Register RST_SR indicates the cause of a reset and the selected boot
configuration. The Reset Request Register RST_REQ is used to cause a software reset.

4.1.1.1 Reset Status Register

After a reset, the reset status register RST_SR indicates the type of reset which has
occurred and which parts of the TC1796 were affected by the last reset operation.
RST_SR also holds the state of the boot configuration pins HWCFG[3:0] (Port 10) that
have been sampled with the HDRST inactive (low-to-high) transition. Register RST_SR
is a read-only register.

RST_SR
Reset Status Register (F0000014H) Reset Values: see Table 4-1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HW
WDT SFT HD PWO TMP
0 0 BRK 0 HWCFG
RST RST RST RST LS
IN
r rh rh rh rh r rh rh r rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RS RS
0 0
EXT STM
r rh r rh

Field Bits Type Description

RSSTM 0 rh System Timer Reset Status
0B The system timer was not reset.
1B The system timer was reset.
RSEXT 2 rh HDRST Input State during Last Reset
0B HDRST was not activated.
1B HDRST was activated.
HWCFG [19:16] rh Boot Configuration Selection Status
This bit field indicates the status of the configuration
pins HWCFG[3:0] at Port 10 that has been latched at
the rising edge of HDRST. HWCFG[3:0] is assigned to
P10.[3:0].

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Field Bits Type Description

HWBRKIN 21 rh Latched State of BRKIN Input
This bit indicates the logical state of the BRKIN input
that has been latched at the end of a power-on reset.
TMPLS 22 rh Latched State of TESTMODE Input
This bit indicates the logical state of the TESTMODE
input pin that has been latched at the end of a power-on
reset.
PWORST 27 rh Power-On Reset Status Flag
0B The last reset was not a power-on reset.
1B The last reset was a power-on reset.
HDRST 28 rh Hardware Reset Status Flag
0B The last reset was not a hardware reset.
1B The last reset was a hardware reset.
SFTRST 29 rh Software Reset Status Flag
0B The last reset was not a software reset.
1B The last reset was a software reset.
WDTRST 30 rh Watchdog Reset Status Flag
0B The last reset was not a watchdog reset.
1B The last reset was a watchdog reset.
0 1, r Reserved
[15:3], Read as 0.
20,
[26:23],
31

Table 4-1 defines the reset values of the RST_SR register depending on the reset
source.

Table 4-1 Reset Values of Register RST_SR

Reset Source Reset Values
Power-on Reset 0000 1000 0XX0 XXXX 0000 0000 0000 0101B
Hardware Reset 0001 0000 0XX0 XXXX 0000 0000 0000 0000B
Software Reset 0010 0000 0XX0 XXXX 0000 0000 0000 0X0XB
Watchdog Timer Reset 0100 0000 0XX0 XXXX 0000 0000 0000 0101B

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4.1.1.2 Reset Request Register

The reset request register RST_REQ is used to generate a software reset. Unlike the
other reset causes, the software reset can exclude functions (System Timer reset and
hardware reset (HDRST) generation) from the reset. Additionally, the boot configuration
information can be set by software.
RST_REQ is Endinit-protected, meaning that bit WDT_CON0.ENDINIT must be set to 0
first through the password-protected access scheme provided for the watchdog timer
register WDT_CON0. Once access is gained through the Endinit-protection scheme,
RST_REQ can be written, causing the requested software reset.

RST_REQ
Reset Request Register (F0000010H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SW SW
0 BO 0 BRK 0 SWCFG
OT IN
r rw r rw r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RR RR
0 0
EXT STM
r rw r rw

Field Bits Type Description

RRSTM 0 rw Reset Request for the System Timer
0B Do not reset the System Timer
1B Reset the System Timer
RREXT 2 rw Reset Request for External Devices
0B Do not activate hardware reset output HDRST
1B Activate hardware reset output HDRST
SWCFG [19:16] rw Software Boot Configuration
A software boot configuration different from the
external applied hardware configuration can be
specified with these bits. The encoding of this bit field
is equal to the RST_SR.HWCFG line encoding.
SWBRKIN 21 rw Software Break Signal Boot Value
This bit determines the desired value for the BRKIN
input signal to be used for software boot.

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Field Bits Type Description

SWBOOT 24 rw Software Boot Configuration Selection
0B The previously latched hardware configuration
stored in RST_SR.HWCFG is used as boot
selection.
1B The software configuration as programmed in bit
field SWCFG is used as boot selection.
0 1, 20, r Reserved
[15:3], Read as 0; should be written with 0.
[23:22],
[31:25]

Note: Please refer to the Table 4-3 in this chapter for detailed value configuration for the
SWCFG bit field as well as for SWBRKIN and SWBOOT bits.

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4.2 Reset Operations

4.2.1 Power-On Reset

The PORST pin performs a power-on reset, also called cold reset. Driving the PORST
pin low causes an asynchronous reset of the entire device. The device then enters its
power-on reset sequence.
The PLL has its own power-on reset circuitry and is not affected by any other reset
condition besides a low signal transition on the PORST pin. With an active power-on
reset, the PLL is disconnected from the oscillator and will start running at its base
frequency.
Simultaneously with PORST low, the reset circuitry drives the HDRST pin low and waits
for the following two conditions to occur:
1. The system clock is active
2. Pin PORST is put to inactive level (driven high)
When both of these conditions are met and HDRST is not further pulled low externally,
the power-on reset sequence is terminated synchronously with the next system clock
transition.
The rising edge of PORST causes the state of some of the configuration pins for the PLL
and the boot options to be latched into the appropriate registers. Others are latched with
the rising edge of HDRST. Fields in the Reset Status Register (RST_SR) are set to
inform the user about this complete reset of the device. The power-on reset indication
flag is set, while all other reset cause indication flags are cleared. Fields in this register
which are set include the power-on reset indication flag (PWORST), as well as the reset
status flags for the System Timer (RSSTM) and the reset output pin state (RSEXT).
The time PORST has to be active after the supply voltage is stable depends mainly on
the settling time of the power supply lines. It does not directly depend on the oscillator
start up time because a system clock signal will be provided already by the PLL in PLL
Base Mode as soon as the power supply lines are stable. This system clock signal is a
slow clock signal based on the VCO base frequency. More details on the PLL Base Mode
are discussed on Page 3-11.
PORST is equipped with a noise-suppression filter that suppresses glitches below 10 ns
pulse width. PORST pulses with a width above 100 ns are safely recognized as a valid
signal. The noise-suppression filter is switched-off when pin BYPASS = 1.

4.2.2 External Hardware Reset

The external hardware reset pin HDRST serves as an external reset input as well as a
reset output. It is an active-low, bi-directional open-drain pin with an internal weak pull-
up. An active-low signal at this pin causes the chip to enter its hardware reset sequence.

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The HDRST (output) pin is held low for 1024 fSYS clock cycles by the reset circuitry until
its internal reset sequence is terminated.
When the sequence is terminated, the reset circuitry then releases HDRST (that is, it
does not actively drive HDRST anymore, so that the weak pull-up can try to drive the pin
high). It then begins monitoring the level of the pin. If HDRST is still low (indicating that
it is still being driven low externally), the reset circuitry holds the chip in hardware reset
until a high level is detected. The hardware reset sequence is then terminated and flag
RST_SR.HDRST is set.
The PLL is not affected by an external hardware reset and continues to operate.
In order to safely recognize a valid hardware reset, HDRST must be active for at least
four fCPU clock cycles.
HDRST is equipped with a noise-suppression filter which suppresses glitches below
10 ns pulse width. HDRST pulses with a width above 100 ns are safely recognized as a
valid signal. The noise-suppression filter is switched-off when pin BYPASS = 1.

4.2.3 Software Reset

A software reset is invoked by writing the appropriate bits in the reset request register
RST_REQ. Unlike the other reset types, the software reset can include/exclude
optionally the system timer reset and the external reset output HDRST generation from
becoming active. To exclude one of these two system functions from software reset, the
corresponding bits in RST_REQ (RRSTM or RREXT) must be set to 0. Additionally, a
software reset can be executed with a programmable software boot configuration value
(bit field RST_REQ.SWCFG) instead of the last hardware boot configuration value (as
latched in bit field RST_SR.HWCFG).
To perform a software reset, the reset request register RST_REQ must be written.
However, RST_REQ is Endinit-protected to avoid triggering of an unintentional software
reset. Bit WDT_CON0.ENDINIT must be cleared via the password-protected access
scheme. When this is done, a write access to RST_REQ can then be performed.
After the write access to RST_REQ, the entering into the software reset takes some time
in which instructions can be still executed. Therefore, it is recommended not to execute
important instructions anymore after the instruction that writes to RST_REQ (e.g
entering a endless loop).

4.2.4 Watchdog Timer Reset

A Watchdog Timer overflow or access error occurs only in response to severe and/or
unknown malfunctions of the TC1796, either caused by software or hardware errors.
Therefore, a Watchdog Timer reset occurs when an overflow of the Watchdog Timer
takes place.
Before the Watchdog Timer generates its reset, it first indicates a Non-Maskable
Interrupt (NMI) at the beginning of a prewarning phase and enters a time-out mode. The

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NMI invokes the trap service routine and can save critical states of the microcontroller
for later examination to determine the cause of the Watchdog Timer failure. However, it
is not possible to stop or terminate the Watchdog Timer’s time-out mode or prevent the
pending watchdog reset.
However, software can prevent the Watchdog Timer by issuing a software reset on its
own. Since the cause of the system failure is presumably unknown at that time, and it is
presumably uncertain which functions of the TC1796 are operating properly, it is
recommended that the software reset is configured to reset all system functions
including the System Timer and external reset output HDRST, and to use the hardware
boot configuration bit field as boot configuration source indicator.
If the NMI trap handler does not perform a software reset, or if the system is so
compromised that the trap handler cannot be executed, the Watchdog Timer will cause
a Watchdog Timer reset to occur at the end of its time-out mode period. The actions
performed on a Watchdog Timer reset sequence are the same as are performed for an
external hardware reset. At the end of the Watchdog Timer reset sequence, bits
WDTRST, RSSTM, and RSEXT are set in register RST_SR. All other reset flags are
cleared.

Watchdog Timer Reset Lock

When the system emerges from any reset condition, the Watchdog Timer becomes
active, and, unless prevented by initialization software, will eventually time out.
Ordinarily, initialization software will configure the Watchdog Timer and commence
servicing it on a regular basis to indicate that it is functioning properly. Should the system
be malfunctioning such that initialization and service are not performed in a timely
fashion, the Watchdog Timer will time out, causing a Watchdog Timer reset.
If the TC1796 system is so corrupted that it is chronically unable to service the Watchdog
Timer, the danger could arise that the system would be continuously reset every time the
Watchdog Timer times out. This could lead to serious system instability, and to the loss
of information about the original cause of the failure.
However, the reset circuitry of the TC1796 is designed to detect this condition. If a
Watchdog Timer error occurs while one or both of the Watchdog Timer error flags
(WDT_SR.WDTAE and WDT_SR.WDTOE) are already set to 1, the reset circuitry locks
the TC1796 permanently in reset (Reset Lock, HDRST permanently active) until the next
power-on reset occurs by activation of the PORST pin.
This situation could arise, for example, if the connection to external code memory is lost
or memory becomes corrupt, such that no valid code can be executed, including the
initialization code. In this case, the initial time-out period of the Watchdog Timer cannot
be properly terminated by software. The Watchdog Timer error flag WDTOE will be set
when the Watchdog Timer overflows, and a Watchdog Timer reset will be triggered (after
the watchdog reset pre-warning phase). The error flag WDTOE is not cleared by the
Watchdog Timer reset that subsequently occurs. After finishing the Watchdog Timer

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reset sequence, the TC1796 will again attempt to execute the initialization code. If still
the code cannot be executed because of connection problems, the WDTOE bit will not
have been cleared by software. Again, the Watchdog Timer will time out and generate a
Watchdog Timer reset. However, this time the reset circuitry detects that WDTOE is still
set while a Watchdog Timer error has occurred, indicating danger of cyclic resets. The
reset circuitry then puts the TC1796 in Reset Lock. This state can only be deactivated
again through a power-on reset.

4.2.5 Debug System Reset

The debug system is not automatically reset by the regular resets except for the power-
on reset. It is not effected by a software resets and by a Watchdog Timer reset. A
hardware reset becomes only effective if at the same time the OCDS reset is active as
well.
Note: TriCore, PCP, DMA, RBCU and SBCU have integrated debug modules that are
part of the debug system.

4.2.6 Module Reset Behavior

Table 4-2 lists how the various functions of the TC1796 are affected through a reset
depending on the reset type. A black square means that this function/unit is reset to its
default state.

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Table 4-2 Effect of Reset on Device Functions

Module / Function Watchdog Software Hardware Power-On
Reset Reset Reset Reset
Boot Configuration Bit field Bit fields Bit field Bit field
taken from HWCFG HWCFG or HWCFG HWCFG
SWCFG
CPU
1) 1) 1) 1)
SCU
BCUs, Bus System
Peripherals, PCP
(except System Timer)
System Timer Optional2) Not affected
On-chip DMI, Not affected, Not affected, Not affected, Affected,
Static RAMs PMI reliable reliable reliable unreliable
DMU, Not affected, Not affected, Not affected, Affected,
PMU unreliable unreliable unreliable unreliable
PCP Not affected3) Not affected3) Not affected3) Affected,
Memory unreliable
On-Chip Caches4)
Flash
Oscillator, PLL Not affected Not affected Not affected
EBU
EBU Pins Depending on Reset Configuration
Port Pins Tri-stated, weak pull-up active5)
NMI Pin Not affected Disabled Disabled Disabled
Reset Out Pin HDRST Optional
OCDS L1 Debug Only if JTAG reset is also active6)
System
1) For two of the SCU registers (PLL_CLC, RST_SR), the reset value depends on the reset source.
2) “Affected” or “not affected” depends on bit RST_REQ.RRSTM.
3) If only the PCP accesses its memory, the contents are reliable. If an access from the FPI Bus is performed
while the reset is activated, the content is unreliable.
4) The actual data contents of the cache are not affected through a reset; however, the cache tag information is
cleared, resulting in an “empty” cache.
5) While PORST is active it is guaranteed that the pins are in tri-state mode even if the core supply is not applied.
Therefore the external power supply should activate PORST if any power failure is detected.
6) Default JTAG reset state (open JTAG pins) is active. A connected debugger tool controls the JTAG reset.

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4.2.7 Booting Scheme

When the TC1796 is reset, it needs an indication how it has to start after the reset
sequence is finished. The TC1796 internal state is usually cleared through a reset,
especially in the case of a power-up reset. Thus, boot configuration information needs to
be applied by the external hardware through input pins. The boot configuration
information is required for:
• The start location of the code execution, and
• Activation of special modes and conditions
For the start of code execution and activation of special mode, the TC1796 implements
two basic booting schemes: A hardware booting scheme which is invoked through
external pins; and a software booting scheme, where software can determine the boot
options, overriding the externally-applied options.

Boot Options
Inputs HWCFG[3:0] (Port P10.[3:0]) and input BRKIN determine the boot mode and boot
location. Table 4-3 shows the boot options/selections which are available in the TC1796.
The source for BRKIN and HWCFG[3:0] can be either the corresponding bits HWBRKIN
and HWCFG[3:0] from register RST_SR (sampled from configuration pins) or the
software configuration bits SWBRKIN and SWCFG[3:0] from register RST_REQ.
The target boot address (program counter start address DFFF FFFCH) is located at the
end of the Boot ROM space. The Boot ROM code then decides how to proceed for the
selected boot modes. When Boot ROM code is left, jump instructions to different
dedicated addresses are executed. Note that pin TESTMODE must be at high level for
all normal boot selection shown in Table 4-3.

Table 4-3 TC1796 Boot Selections

BRKIN HWCFG Type of Boot Boot ROM Exit
[3:0] Jump Address
Normal Boot Options
1 0000B Enter bootstrap loader mode 1: D400 0000H
Serial ASC0 boot via ASC0 pins
0001B Enter bootstrap loader mode 2:
Serial CAN boot via CAN pins
0010B Start from internal PFLASH A000 0000H
0011B Alternate Boot Mode (ABM): start from internal as defined in
PFLASH after CRC check is correctly executed; ABM header or
enter a serial bootstrap loader mode1) if CRC D400 0000H
check fails;

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Table 4-3 TC1796 Boot Selections (cont’d)

BRKIN HWCFG Type of Boot Boot ROM Exit
[3:0] Jump Address
1 0100B Start from external memory with EBU as master, A100 0000H
using CS0; automatic EBU configuration2);
0101B Alternate Boot Mode (ABM): start from external as defined in
memory with CRC check and EBU as master, ABM header or
using CS0; enter a serial bootstrap loader D400 0000H
1)
mode if CRC checks fails;
automatic EBU configuration2);
0110B Start from external memory with EBU as A100 0000H
participant, using CS0;
automatic EBU configuration2);
0111B Alternate Boot Mode (ABM): start from external as defined in
memory with CRC check and EBU as ABM header or
participant, using CS0; enter a serial bootstrap D400 0000H
loader mode1) if CRC checks fails;
automatic EBU configuration2);
1000B Start from emulation memory if emulation if TC1796ED:
device TC1796ED is available; in case of AFF0 0000H
TC1796 execute stop loop;
1111B Enter bootstrap loader mode 3: D400 0000H
Serial ASC0 boot via CAN pins
others Reserved; execute stop loop; –
Debug Boot Options
0 0000B Tri-state chip –
1000B Go to external emulator space with EBU as DE00 0000H)
master, using CSEMU/CSCOMB
others Reserved; execute stop loop; –
1) The type of bootstrap loader mode is selected by SCU_SCLIR.SWOPT[2:0] bit field.
2) The EBU fetches the boot configuration from address offset 4 using CS0.

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4.2.7.1 Normal Boot Options

The normal boot options are invoked when BRKIN is inactive (at high level). The TC1796
has three options for booting into normal operation:
• Starting code execution from external memory
• Starting code execution from internal PFLASH
• Starting code execution from internal SPRAM after a bootstrap loader program has
downloaded a program via a serial interface (ASC0 or CAN).
If a reserved boot selection is detected for HWCFG[3:0] with BRKIN = 1, the TC1796
stops further Boot ROM control operations and enters into an endless loop by executing
a jump instruction to itself (can be aborted by a WDT reset).

Serial Boot via Bootstrap Loader

The bootstrap loader (BSL) is a software part of the Boot ROM which provides a
mechanism to load a program code into the scratchpad RAM (SPRAM) of the PMI. The
program code to be loaded is received serially either via the ASC0 or CAN interfaces.
After loading of the code, the bootstrap loader program jumps directly to address
D400 0000H (start address of the PMI scratchpad RAM) and begins executing the
program code that has been loaded. Further details about the BSL are described in
Section 4.4.

External Boot
In external boot modes, code execution is started in external memory via the EBU at a
fixed address (A100 0000H). In Alternate Boot Modes, the code start address is defined
by one of the two ABM headers (see Page 4-30).
In order to access external memory after reset, the EBU must have information about the
type and access mechanism of the external memory. For this purpose, a special external
bus access is executed by the EBU in order to retrieve information about the external
code memory. This access is performed to address offset 0000 0004H of the memory
connected to CS0, using access parameters such that regardless of the type and
characteristics of the external memory, configuration information can be read from the
memory into the EBU. By examining this information, the EBU determines the exact
requirements for accesses to the external memory. It then configures the control
registers accordingly, and performs the first instruction fetch from address A100 0000H.
All further accesses to external memory during external boot will activate CS0 (until the
EBU becomes reprogrammed for example by a user program).

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Internal PFLASH Boot

After execution of the start-up code, two PFLASH boot options exist:
• PFLASH boot option 1 directly jumps to the internal flash.
• PFLASH boot option 2 (Alternate Boot Mode) first checks the flash via checksum
calculation, whether one of two pre-defined entry locations contain valid code and
jumps to a start address as defined by the ABM header.

4.2.7.2 Debug Boot Options

The debug boot options are invoked when BRKIN is active (at low level). The TC1796
has three options for booting into debug operation:
• Tri-state chip
• Starting code execution from external emulator memory
• Execution of an endless (stop) loop

Tri-state Chip
If HWCFG[3:0] = 0000B, all pins of the TC1796 are put into tri-state mode. In this mode,
all pins are deactivated, including the oscillator, and internal circuitry is held in a low-
power mode. This mode allows e.g. board level test equipment or emulator probes to
actively drive lines which are connected to TC1796 pins.

Emulator Memory Start

If HWCFG[3:0] = 1000B, the TC1796 starts execution out of the external memory space
using the EBU and the chip select line CSCOMB.

Execute Endless Loop

If a reserved boot selection is detected for HWCFG[3:0] with BRKIN = 0, the TC1796
stops further Boot ROM control operations and enters into an endless loop by executing
a jump instruction to itself (can be aborted by a WDT reset).

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4.3 Boot ROM

The internal 16 Kbyte Boot ROM (BROM) has two parts:
• 8 Kbyte reserved for boot code (Boot ROM)
• 8 Kbyte reserved for factory test routines (Test ROM).
Note: The expression “Boot ROM” in the text always refers to the 8 Kbyte boot code part
of the BROM.

4.3.1 Addressing
As the original architectural position of the BROM is on the FPI Bus and the boot vector
to the Boot ROM is hardwired in the CPU to this location. The internal BROM in the
TC1796 is visible from the PMI side at three different locations, as can be seen in the
memory map:
• In segment 8 (cached) starting at location 8FFF C000H
• In segment 10 (non-cached) starting at location AFFF C000H
• In segment 13 (FPI space) starting at location DFFF C000H.
From DMI side, the internal ROM is not visible in segment 13. Accesses to these
addresses will be routed to the FPI Bus and will cause a bus error.
The hardware-controlled start address after reset is address DFFF FFFCH. At this
location (within the BROM), a jump to start address AFFF F180H is programmed to
guarantee continuation of start program execution after reset.
Because the reset start address is fixed, the Boot ROM is mapped to the upper part of
the internal BROM, at locations ..E000 - ..FFFFH, and the TestROM is mapped to the
lower part of internal BROM (..C000 - ..DFFFH).

4.3.2 Program Structure

The different sections of the 8 Kbyte Boot ROM provide the following functionalities.

Startup Procedure
The startup procedure is the main control program in the Boot ROM which is always
started after every reset operation. It initializes the chip, checks the hardware or software
configuration selections, and branches to the corresponding boot routines. From a user
point of view, the startup procedure lengthens the reset time of the TC1796.
The startup procedure is responsible for the correct initialization of the on-chip
resources. For example, the startup procedure monitors the Flash ramp-up phase and
waits until the Flash memories are ready to be used. The startup procedure further
controls the Flash read protection, initializes SRAM redundancy settings, and copies the
unique chip identifier from Flash into the LDRAM memory.

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During the startup procedure, the NMI interrupt, the watchdog timer, and the debug
interfaces are disabled. The NMI interrupt has to be enabled by the user software
(SCU_CON.NMIEN bit set) after proper setup of the interrupt vector table.
The reset configuration indicated in register RST_SR is evaluated by the startup
procedure for selection of the configured operation and of program start memory.

Bootstrap Loader
The Bootstrap loader (BSL) is a software part of the Boot ROM which provides a
mechanism to load a program code into the Scratchpad RAM (SPRAM) of the PMI. The
program code to be loaded is received serially either via the ASC0 or CAN interfaces.
After loading of the code, the bootstrap loader jumps directly to address D400 0000H
(start address of SPRAM) and begins executing the program code that has been loaded.
Further details about the BSL are described in Section 4.4.

Alternate Boot Modes

The alternate boot modes will only branch to an user program in PFLASH or external
code memory if a CRC checksum test shows no error. If the CRC check fails, a bootstrap
loader mode is entered instead of user program execution.

Tuning Protection
Tuning protection is supported to protect user software in external Flash memory from
being manipulated and to safely detect changes of this user software.

Emulation Support
If the device currently used is an emulation device (TC1796ED), a boot capability from
emulation memory is supported. For the standard TC1796 this boot option cannot be
activated.

Test and Stress Routines

The 8 Kbyte TestROM is reserved for special routines, which are used for testing,
stressing and qualification of the component. This boot option should never be activated
by a user program.

Boot ROM Program Flow

Figure 4-1 shows the basic Boot ROM program flow. This flow diagram has one input
(reset address DFFF FFFCH) and several outputs that depend on the selected boot
option (as described in Table 4-3).

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TC1796 Reset Operation

Flash Ramp-up and Chip Initialization

Startup Procedure
Checking boot configuration selections: BRKIN pin,
HWCFG[3:0] pins, SWOPT[2:0], TESTMODE pin

yes Branch to test modes

TESTMODE = 0?
(Test ROM)
no

Check CFG data no yes Execute debug

BRKIN = 0?
boot options

yes
0000B? Execute bootstrap loader
Jump to D4000000H
mode 1 (ASC0)
no
yes
0001B? Execute bootstrap loader
mode 2 (CAN)
no
yes
1111B? Execute bootstrap loader
mode 3 (ASC0)
no
yes TC1796ED Boot from
1000B? Jump to AFF00000H
emulation memory
no
yes Boot from internal
0010B?
PFLASH Jump to A0000000H
no

yes Boot from ext. memory

01X0B? X = 0: EBU as master Jump to A1000000H
X = 1: EBU as participant
no

yes Alternate boot from yes Jump to address as

0011B? internal PFLASH CRC ok?
defined in ABM Headers
no after CRC check
no
yes Alternate boot from yes Jump to address as
01X1B? external memory CRC ok? defined in ABM Headers
X = 0: EBU as master
no after CRC check X = 1: EBU as participant
no
TC1796
SWOPT[2:0] = 111B
SWOPT[2:0] = 101B Check SCU_SCLIR.
Execute stop
SWOPT[2:0] = 110B SWOPT[2:0]
loop
MCA05609

Figure 4-1 Boot ROM Flow Diagram

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4.3.3 Initial State after Boot ROM Exit

The Boot ROM code is always executed after every reset operation. Depending on the
program flow through the Boot ROM code and the Boot ROM exit path, several
resources of the TC1796 on-chip hardware have been used and have been
programmed. This means that the state of on-chip hardware resources that have been
used by the Boot ROM code may differ from the device reset state as described by the
register reset values. This section describes which initial state of the on-chip hardware
resources is left after a specific Boot ROM exit.

Table 4-4 Hardware Status after Boot ROM Exit

Boot ROM Exit Path State of On-Chip Hardware Resources
For all boot modes CPU registers D[15:0] and A[15:0] are changed (note that its
reset values are XXXX XXXXH);
Memory locations in LDRAM are used:
D000 0000H - D000 000FH: updated with unique Chip ID
D000 0010H - D000 0107H: updated with Boot ROM data
SCU_STAT[15:13] are set to 001B. FLASH_MARP.TRAPDIS
and FLASH_MARD.TRAPDIS are cleared;
FLASH_FCON.WSWLHIT is set to 110B
Branch to test modes Only applicable for test purposes
Execute debug boot The following registers have been changed:
options CPR0_0L, CPM0, and TR0EVT
Exit of Bootstrap loader P5_IOCR0 has been changed (P5.1/TXD0A); ASC0 module
mode 1 (ASC0) is initialized and enabled; PLL_CLC has been changed
Exit of Bootstrap loader P6_IOCR8 has been changed (P6.9/TXDCAN0); MultiCAN
mode 2 (CAN) module is initialized and enabled; registers of CAN node 0,
message object 0, and message object 1 have been used;
PLL_CLC has been changed
Exit of Bootstrap loader P6_IOCR8 has been changed (P6.9/TXD0B); ASC0 module
mode 3 (ASC0) is initialized and enabled; PLL_CLC has been changed
Boot from emulation EBU_CON has been changed
memory
Boot from PFLASH No further changes
Alternate boot from Memory checker module has been used
PFLASH
Boot from EBU No further changes
Alternate boot from EBU Memory checker module has been used
Execute Stop Loop BTV has been changed

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4.4 Bootstrap Loader (BSL)

The bootstrap loader (BSL) is a software part which is integrated in the TC1796 Boot
ROM. The BSL provides a mechanism to load a program code via a serial interface (ASC
or CAN) into the scratchpad RAM (SPRAM) of the PMI. After loading of the code, the
BSL jumps directly to address D400 0000H (start address of the PMI scratchpad RAM)
and begins executing the program code that has been loaded. The BSL automatically
calculates the baud rate of the serial data streams.
Table 4-5 shows the three BSL modes with its parameters.

Table 4-5 Bootstrap Loader Selections

Bootstrap Loader Mode Selection1) Associated I/O Lines
BRKIN HWCFG Receive Transmit
[3:0]
Bootstrap Loader Mode 1 (BSL1): 1 0000B P5.0 / P5.1 /
ASC Boot via ASC0 Pins RXD0A TXD0A
Bootstrap Loader Mode 2 (BSL2): 0001B P6.8 / P6.9 /
CAN Boot RXDCAN0 TXDCAN0
Bootstrap Loader Mode 3 (BSL3): 1111B P6.8 / P6.9 /
ASC Boot via CAN Pins RXD0B TXD0B
1) The bootstrap loader mode selections in alternate boot modes see Table 4-3.

With the low-to-high signal transition of the hardware reset signal HDRST or the power-
on reset signal PORST, the input pins BRKIN and HWCFG[3:0] of the TC1796 are
latched. If one of the latched BRKIN/HWCFG[3:0] signal combination of Table 4-5 is
detected, the bootstrap loader is started and the selected bootstrap loader mode is
entered.
The bootstrap loader can also be started by a software reset. For this purpose, bit
RST_REQ.SWBRKIN and bit field RST_REQ.SWCFG must be loaded with the
corresponding BRKIN/HWCFG[3:0] code, and bit RST_REQ.SWBOOT must be set (see
also RST_REQ register description at Page 4-5).
When a boot option for a bootstrap loader mode is detected, the TC1796 jumps to
address DFFF FFFCH which is the last word address of the Boot ROM. During execution
of the bootstrap loader, the Watchdog Timer interrupts and NMI interrupts are disabled.

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4.4.1 Bootstrap Loader Mode 1 - ASC Boot via ASC0 Pins

The ASC boot mode of the bootstrap loader moves 128 bytes of program code/data into
the SPRAM and starts executing the loaded code from address D400 0000H (address of
the first transmitted byte). Most probably the initially-loaded program code will load
additional code or data. For that purpose, it can directly use the ASC0 interface that has
already been initialized during the bootstrap loader execution. Figure 4-2 shows the
actions that take place in bootstrap loader mode 1.

1
PORST or
HDRST

BRKIN
HWCFG[3:0]
2 3 5
Byte Byte Byte Byte
RXD0A 1 2 127 128 6
4

TXD0A D5H

Program Exec. Boot ROM ASC Bootstrap Loader Routine User Code
Location

1 Latching the input levels of BRKIN and HWCFG[3:0].

2 Bootstrap loader initialization and selection.
3 Reception of a zero byte (1 start bit, eight “0“ data bits, 1 stop bit)
4 Identifcation byte is sent to the external host. Receiver is disabled.
5 128 bytes of code/data are sent by the external host.
6 Last byte received; jump to D4000000 H executed.
MCT05610

Figure 4-2 ASC0 Bootstrap Loader Sequence (Mode 1)

As the first task, the ASC0 determines the baud rate at which the external host is
communicating. This task requires the external host to transmit an initialization byte to
the TC1796 at the RXD0A input line of the ASC0. The initialization byte is built up by one
low level start bit, eight low-level data bits, and 1 stop bit (a low pulse with a width of nine
serial bit cells). The bootstrap loader software measures the width of the initialization
byte, calculates the baud rate, and writes the corresponding ASC0 registers with the
values that select the detected baud rate.
After the baud rate calculation and initialization (receive pin remains disabled during this
time), an identification byte (D5H) is sent to the external host indicating that the TC1796
is ready to accept a data transfer from the host of exactly 128 bytes (32 words). After the

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identification byte has been transmitted, the ASC0 receive pin is enabled again. The
bootstrap loader software now enters two receive loops. The inner loop waits until it has
received four bytes. The outer loop writes one word (four bytes) to the scratchpad RAM
(SPRAM) program memory of the PMI. These loops are running until 128 bytes have
been received.
After the reception of the 128 bytes, the bootstrap loader software is finished and a jump
to address D400 0000H is executed. This address is the 32-bit word location in the
SPRAM at which the first four bytes of the transmitted 128 bytes have been written.

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Initialization of ASC0
Bootstrap Loader Mode 1

Transmit identification D5H

no
RXD0A pin = 1?
Ident. byte no
yes transmitted?
yes

no Enable receiver
RXD0A pin = 0?
Initialize data pointer
Byte counter = 4
yes
Word counter = 32
Read System Timer

Data byte no
Baud rate no
RXD0A pin = 1? received?
detection
yes
yes

Store data byte in buffer

Read System Timer
Decrement byte counter
Calculate difference

Byte no Data
Unlock WDT
counter = 0? receive
Enable ASC0 clock
loop
Lock WDT yes
Initialize ASC0 port pins
Baud rate Write word to SPRAM
calculation Increment data pointer
and ASC0 Calculate baud rate Byte counter = 4
setup (search for best values for Decrement word counter
FDV and BG registers)

Initialize ASC0 registers Word no

counter = 0?
yes

Execute jump to
address D4000000H
MCA05611

Figure 4-3 Flow Diagram of Bootstrap Loader ASC0 Boot Modes

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4.4.2 Bootstrap Loader Mode 2 - CAN Boot via CAN Pins

The CAN boot mode of the bootstrap loader provides a mechanism to load program
code/data via the MultiCAN module into the SPRAM, and start executing the loaded
code from address D400 0000H (address of the first transmitted byte). A single data
frame always transmits eight code/data bytes from the external host to the TC1796. The
number of data frames to be received in CAN boot mode is programmable and depends
on the required amount of code/data to be transmitted. The 16-bit data message count
value DMSGC determines the number of code/data bytes to be transmitted as
8 × MSGC with MSGC = 1 to 216. Therefore, the 48 Kbyte SPRAM of the TC1796 can
be loaded completely during CAN boot mode.
The communication between TC1796 and external host is based on the following three
CAN standard frames:
• Initialization frame - sent by the external host to the TC1796
• Acknowledge frame - sent by the TC1796 to the external host
• Data frame(s) - sent by the external host to the TC1796
The initialization frame is used in the TC1796 for baud rate detection. After a successful
baud rate detection is reported to the external host by the acknowledge frame, data is
transmitted by data frames. Table 4-6 shows the parameters and settings of the three
CAN standard frames used for CAN bootstrap loader.

Table 4-6 CAN Bootstrap Loader Frames

Frame Type Parameter Description
Initialization Identifier 11-bit, don’t care
Frame DLC = 8 Data length code, 8 bytes transmitted within CAN frame
Data byte 0 55H
Data byte 1 55H
Data byte 2 Acknowledge message identifier ACKID, low byte
Data byte 3 Acknowledge message identifier ACKID, high byte
Data byte 4 Data message count DMSGC, low byte
Data byte 5 Data message count DMSGC, high byte
Data byte 6 Data message identifier DMSGID, low byte
Data byte 7 Data message identifier DMSGID, high byte

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Table 4-6 CAN Bootstrap Loader Frames (cont’d)

Frame Type Parameter Description
Acknowledge Identifier Acknowledge message identifier ACKID as received by
Frame data bytes [3:2] of the initialization frame
DLC = 4 Data length code, 4 bytes transmitted within CAN frame
Data bytes Contents of bit-timing register
0/1
Data bytes Copy of acknowledge identifier from initialization frame
2/3
Data frame Identifier Data message identifier DMSGID as sent by data bytes
[7:6] of the initialization frame
DLC = 8 Data length code, 8 bytes transmitted within CAN frame
Data bytes Data bytes, assigned to increasing destination (SPRAM)
0 to 7 addresses

Initialization Phase
As in the ASC boot mode, as first task the CAN bootstrap loader has to determine the
CAN baud rate at which the external host is communicating. This task requires the
external host to send initialization frames continuously to the TC1796. The first two data
bytes of the initialization frame include a 2-byte 5555H baud rate detection pattern, an
11-bit (2-byte) identifier ACKID1) for the acknowledge frame, a 16-bit data message
count value DMSGC, and an 11-bit (2-byte) identifier DMSGID1) to be used by the data
frame.
When CAN boot mode is entered, the CAN bootstrap loader program starts measuring
signal pulses at the RXDCAN0 input. After reception and pulse measurements of a
5555H bit pattern (data bytes 0 and 1 of the initialization frame), the CAN bootstrap loader
program calculates the CAN baud rate and programs the baud rate registers of the
MultiCAN module. The TC1796 is now ready to receive CAN frames with the baud rate
of the external host.

Acknowledge Phase
In the acknowledge phase, the bootstrap loader waits until it receives the next correctly
recognized initialization frame from the external host, and acknowledges this frame by
generating a dominant bit in its ACK slot. Afterwards, the bootstrap loader transmits an
acknowledge frame back to the external host indicating that it is now ready to receive

1) The CAN bootstrap loader copies the two identifier bytes received in the initialization frame directly to register
MOAR. Therefore, the respective fields in the initialization frame must contain the intended identifier padded
with two dummy bits at the lower end and extended with bitfields IDE (=0B) and PRI (=01B) at the upper end.

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data frames. The acknowledge frame uses the message identifier ACKID that has been
received with the initialization frame. The eight data bytes of the acknowledge frame are
a copy of the data bytes of the recognized initialization frame.

Data Transmission Phase

In the data transmission phase, data frames are sent by the external host and received
by the TC1796. The data frame uses the 11-bit (2-byte) data message identifier DMSGID
that has been sent with the initialization frame. Eight data bytes are transmitted with each
data frame. The first data byte is stored in SPRAM at D400 0000H. Consecutive data
bytes are stored at incrementing addresses.
Both communication partners evaluate the data message count DMSGC until the
requested number of CAN data frames has been transmitted. After the reception of the
last CAN data frame, the bootstrap loader software is finished and executes a jump to
address D400 0000H. This address is the first 32-bit word location in the SPRAM.

Timing Parameters
There are no general restrictions for CAN timings of the external host. After a reset of
external host and TC1796, the external host can start transmitting initialization frames.
If no acknowledge frame is sent back within a certain time as defined in the external host
(e.g. after a dedicated number of initialization frame transmissions), the external host
can decide that the TC1796 is not able to establish the CAN boot communication link.

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MultiCAN Module in TC1796 External Host Controller

Initialization of CAN Defining parameters for

bootstrap loader mode 2 initialization frame

Sampling RXDCAN0 Sending Init. Frame

for 5555H pattern and checking ACK slot
Init.
Phase
Init. no Dominant bit no
Sampling sucessful?
Phase in ACK Slot?

yes yes

Programming of CAN
registers for detected
baud rate

no Error free Init.

frame rec. ?

Ack. yes
Phase Ack.
Setting dominant bit in Acknow. frame no
Phase
the ACK slot received?
yes
Sending acknow. frame
to the external host

Transmitting CAN
Waiting for reception of
message with eight
the next CAN message
data bytes

Data Transferring received Data

Phase data bytes to SPRAM Phase

no Last message Last message no

received? transmitted?

Execute jump to
End of data transfers
address D4000000H

MCA05612

Figure 4-4 Flow Diagram of CAN Bootstrap Loader Mode

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4.4.3 Bootstrap Loader Mode 3 - ASC Boot via CAN Pins

Except for different connections to serial port lines of ASC0, the bootstrap loader mode
3 is identical with bootstrap loader mode 1. The serial data input of the ASC0 is
connected to RXD0B which is an alternate function of P6.8/RXDCAN0 and the serial
data output of the ASC0 is connected to TXD0B which is an alternate function of
P6.9/TXDCAN0.

4.4.4 Alternate Boot Modes

The alternate boot modes (ABM) make it possible to execute a CRC check procedure
before jumping to the program start addresses in internal PFLASH or external memory
(with EBU as master or as participant). In case of a CRC error in the checked code, the
BSL is entered, and loading of serial (ASC or CAN) code/data can be initiated.
To use ABMs, the user has to define the parameters for the CRC checks in the two ABM
headers. These parameters are:
• The program start address in case of a positive CRC check
• The start address of the memory range which has to be checked with CRC checksum
• The end address of the memory range which has to be checked with CRC checksum
• The checksums for the checked memory range and for the ABM header itself.
Basically the CRC check procedure of the Boot ROM program consists of three steps:
Step 1: The first CRC check is executed with the parameters of the primary ABM header.
If the first CRC check passes, the user program is started at the address as defined in
the first word of the primary ABM header.
Step 2: If the first CRC check of the primary ABM header fails, a second CRC check with
the parameters of the secondary ABM header is performed. If this second CRC check
passes, the user program is started at an alternate start address as defined in the first
word of the secondary ABM header.
Step 3: If the second CRC check also fails, one of the three BSL modes is entered. The
BSL mode to be used is defined by the content of bit field SCU_SCLIR.SWOPT[2:0].
This bit field contains the state of the Port 0 pins P0.[2:0] that was latched at the last
rising edge of HDRST (further details on SCU_SCLIR see Page 10-24).

Table 4-7 ABM Bootstrap Loader Selections

SWOPT[2:0] Selected ABM Bootstrap Loader Mode
110B Bootstrap Loader Mode 1: ASC Boot via ASC0 Pins
101B Bootstrap Loader Mode 2: CAN Boot
111B1) Bootstrap Loader Mode 3: ASC Boot via CAN Pins
others Reserved; do not use these combinations

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1) This value is default after reset without connecting P0.[2:0] to a low or high level. Port 0 pins are inputs after
reset with a pull-up device connected.

Note: For CRC generation and error checking, the Boot ROM software uses the TC1796
on-chip memory checker module with an initial value of FFFF FFFFH for the
memory checker result register before the checksum is generated. Further details
about this module are described in Section 12.4 on Page 12-110.

Definition of the ABM Headers

There are two ABM headers defined, a primary and a secondary (alternate). The two
ABM headers have a size of 32 bytes (8 words) and are located at fix addresses in the
internal or external Flash, as shown in Table 4-8. Alternatively, cached addressing
(segment 8) or non-cached addressing (segment 10) can be used.

Table 4-8 ABM Header Locations

Internal Flash Memory (PFLASH) External Flash Memory
Base Address End Address Base Address End Address
Primary ABM Header
8001 FFE0H 8001 FFFFH 8100 FFE0H 8100 FFFFH
A001 FFE0H A001 FFFFH A100 FFE0H A100 FFFFH
Secondary ABM Header
8003 FFE0H 8003 FFFFH 8108 FFE0H 8108 FFFFH
A003 FFE0H A003 FFFFH A108 FFE0H A108 FFFFH

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Table 4-9 shows the structure of the ABM headers.

Table 4-9 Structure of ABM Headers

Address1) Value Function
XXXX XXE0H 32-bit start address Program/code start address
XXXX XXE4H DEAD BEEFH Identifier string
XXXX XXE8H 32-bit address 32-bit aligned start address of memory
(checksum start) range to be checked
XXXX XXECH 32-bit address 32-bit aligned end address (last word
(checksum end) address) of memory range to be checked
XXXX XXF0H 32-bit CRC value Expected 32-bit CRC result for memory
CRCRANGE range to be checked
XXXX XXF4H CRCRANGE inverted Inverted expected 32-bit CRC result for
memory range to be checked
XXXX XXF8H 32-bit CRC value CRC result of current ABM header from
CRCHEAD offset (byte) address E0H to F7H
XXXX XXFCH CRCHEAD inverted Inverted CRC result of current ABM header
from offset (byte) address E0H to F7H
1) XXXX XX is 8001 FFH/A001 FFH for primary ABM header and 8003 FFH/A003 FFH for secondary ABM header
(see also Table 4-8).

The time needed for CRC generation depends on the length of the memory range to be
checked. In case of internal PFLASH check, the duration can be roughly calculated as
follows:
• CRC of header: To be defined
• CRC of a Flash space of 400 bytes: To be defined

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5 System Control Unit

The System Control Unit (SCU) of the TC1796 handles system control tasks. All the
system functions described in this chapter are tightly coupled; thus, they are
conveniently handled by one unit, the SCU.
The system tasks of the SCU that are covered in this chapter are:
• Power Management (see Page 5-2)
• Configuration Input Sampling (see Page 5-8)
• External Request Unit (see Page 5-9)
• Special System Interrupts (see Page 5-35)
• On-chip SRAM Parity Control (see Page 5-37)
• Pad Driver Temperature Compensation Control (see Page 5-41)
• Die Temperature Sensor (see Page 5-48)
• GPTA1 Input IN1 Control (see Page 5-49)
• Pad Test Mode Control (see Page 5-50)
• Emergency Stop Output Control for GPTA and MSC (see Page 5-57)
• Analog Input 7 Testmode (see Page 5-60)
• Miscellaneous SCU Registers (see Page 5-64)
• SCU Registers and Address Map (see Page 5-61)

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5.1 Power Management

This section describes the power management system of the TC1796. Topics covered
here include the internal system interfaces, external interfaces, state diagrams, and the
operations of the CPU and peripherals. The power management state machine is also
described.

5.1.1 Power Management Overview

The TC1796 power-management system allows software to configure the various
processing units so that they automatically adjust to draw the minimum necessary power
for the application.
As shown in Table 5-1, there are three power management modes available:
• Run Mode
• Idle Mode
• Sleep Mode

Table 5-1 Power Management Mode Summary

Mode Description
Run The system is fully operational. All clocks and peripherals are enabled,
as determined by software.
Idle The CPU clock is disabled, waiting for a condition to return it to Run
Mode. Idle Mode can be entered by software when the processor has no
active tasks to perform. All peripherals remain powered and clocked.
Processor memory is accessible to peripherals. A reset, Watchdog Timer
event, a falling edge on the NMI pin, or any enabled interrupt event will
return the system to Run Mode.
Sleep The system clock signal is distributed only to those peripherals
programmed to operate in Sleep Mode. The other peripheral module will
be shut down by the suspend signal. Interrupts from operating
peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset
event will return the system to Run Mode. Entering this state requires an
orderly shut-down controlled by the Power Management State Machine.

The operation of each system component in each of these states can be configured by
software. The power-management modes provide flexible reduction of power
consumption through a combination of techniques, including:
• Stopping the CPU clock
• Stopping the clocks of other system components individually
• Clock-speed reduction of some peripheral components individually

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The Power Management State Machine (PMSM) controls the power management mode
of all system components during Run Mode, Idle Mode, and Sleep Mode. The PMSM
continues to operate in Idle Mode and Sleep Mode, even if all other system components
have been disabled, so that it can reawaken the system as needed. This flexibility in
power management provides minimum power consumption for any application.
Besides these explicit software-controlled power-saving modes, in the TC1796 special
attention has been paid to automatic power-saving in those operating units which are
currently not required or idle. In that case they are shut off automatically until their
operation is required again.
In typical operation, Idle Mode and Sleep Mode may be entered and exited frequently
during the run time of an application. For example, system software will typically cause
the CPU to enter Idle Mode each time it has to wait for an interrupt before continuing its
tasks. In Sleep Mode and Idle Mode, wake-up is performed automatically when any
enabled interrupt signal is detected, or if the Watchdog Timer signals the CPU an NMI
trap.

5.1.2 Power Management Control and Status Register, PMG_CSR

The set of registers used for power management is divided between central TC1796
components and peripheral components. The PMG_CSR register provides software
control and status information for the PMSM. There are individual clock control registers
for peripheral components because the Sleep Mode behavior of each peripheral
component is programmable. When entering Idle Mode and Sleep Mode, the PMSM
directly controls TC1796 components such as the CPU, but indirectly controls peripheral
components through their clock control registers.

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PMG_CSR
Power Management Control and Status Register
(F0000034H) Reset Value: 0000 0100H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 PMST 0 REQSLP

r rh r rwh

Field Bits Type Function

REQSLP [1:0] rwh Idle Mode and Sleep Mode Request
00B Normal Run Mode
01B Request Idle Mode
10B Request Sleep Mode
11B Reserved; do not use this combination
In Idle Mode or Sleep Mode, these bits are cleared in
response to an enabled interrupt, or when bit 15 of the
Watchdog Timer count register (the WDT_SR.TIM[15]
bit) changes from 0 to 1.
PMST [10:8] rh Power Management State Machine Status
000B Waiting for PLL lock condition
001B Normal Run Mode
010B Idle Mode requested
011B Idle Mode acknowledged
100B Sleep Mode
101B Undefined, reserved
110B Undefined, reserved
111B Undefined, reserved
0 [7:2], r Reserved
[31:11] Read as 0; should be written with 0.

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5.1.3 Power Management Modes

This section describes in more detail the power management modes, their operations,
and how power management modes are entered and exited. It also describes the
behavior of TC1796 system components in all power management modes.

5.1.3.1 Idle Mode

The Idle Mode is requested by software when writing to register PMG_CSR with bit field
REQSLP = 01B. After requesting the Idle Mode, the power management state machine
posts an idle request signal to the CPU. The CPU finishes its current operation, sends
an acknowledge signal back to the PMSM, and then enters an inactive state in which the
CPU clocks and the DMI and PMI memory units are shut off.
Other system components that are able to write to register PMG_CSR can also request
the Idle Mode. For example, the PCP or DMA controller can request Idle Mode by writing
to the PMG_CSR register.
During Idle Mode, memory accesses to the DMI and PMI via the local memory buses
(DLMB and PLMB) cause these units to awaken automatically to handle the
transactions. When memory transactions are complete, the DMI and PMI return to Idle
Mode again.
The system will return to Run Mode through the occurrence of any of the following
conditions:
• An interrupt signal is received from an enabled interrupt source.
• A NMI request is received either from an external source via the NMI pin, or from the
Watchdog Timer. The Watchdog Timer triggers an NMI trap request in Idle Mode
when its count value (WDT_SR.WDTTIM) changes from 7FFFH to 8000H.
• An external power-on reset signal (PORST), or hardware reset signal (HDRST) is
received.
• A software reset is requested by a FPI Bus agent by writing to the reset request
register RST_REQ.
If any of these conditions arise, the TC1796 immediately awakens and returns to Run
Mode. If it is awakened by a hardware or software reset signal, the TC1796 system
begins its reset sequence. If it is awakened by a Watchdog Timer overflow event, it
executes the instruction following the one that was last executed before Idle Mode was
entered. If it is awakened by an NMI signal or interrupt signal, the CPU will immediately
vector to the appropriate handler.

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5.1.3.2 Sleep Mode

The Idle Mode is requested by software when writing to register PMG_CSR with bit field
REQSLP = 10B.

Entering Sleep Mode

Sleep Mode is entered in two steps:
1. The CPU is put into Idle Mode as described in the previous section. When the PMSM
receives the Idle acknowledge signal back from the CPU, it proceeds with the second
step.
2. A sleep signal is broadcasted on the FPI Bus. Each FPI Bus interface unit receives
this signal. The response of each FPI Bus unit to the sleep signal is determined by
its clock control register. These clock control registers must have been previously
configured by software.

TC1796 State During Sleep Mode

Sleep Mode is disabled for a unit if its clock control register bit EDIS is set to 1. The sleep
signal is ignored in this case and the corresponding unit continues normal operation. If
EDIS = 0, Sleep Mode is enabled for this unit and the sleep signal will cause this unit to
enter Sleep Mode. Two actions then occur:
• The unit’s bus interface finishes whatever transaction was in progress when the
signal was received.
• The unit’s functions are suspended.
The TriCore architecture qualifies the actions in step 2 as follows. Depending on the
module’s clock control register Fast Shut-Off Enable bit, FSOE, the module’s clocks are
either immediately stopped (FSOE = 1), or the unit is allowed to finish ongoing
operations (FSOE = 0) before the clocks are stopped. For example, setting FSOE to 1
for a serial port will stop all actions in the serial port immediately when the sleep signal
is received. Ongoing transmissions or receptions will be aborted. If FSOE is 0, ongoing
transmissions or receptions will be completed, and then the clock will be shut off. The
purpose of setting FSOE = 1 is to allow a debugger to observe the internal state of a
peripheral unit immediately.

Exiting Sleep Mode

The system will be returned to Run Mode by the same events that exit Idle Mode. The
response of the CPU to being awakened is also the same as for Idle Mode. Peripheral
units that have entered Sleep Mode will switch back to their selected Run Mode
operation.

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5.1.3.3 States of TC1796 Units in Power Management Modes

Table 5-2 summarizes the state of the various units of the TC1796 during Run Mode,
Idle Mode, and Sleep Mode.

Table 5-2 States of TC1796 Units in Power Management Modes

Unit Run Mode Idle Mode Sleep Mode
Main Oscillator On On On
& PLL
CPU Executing Idle Idle
DMI & PMI Active Idle, but accessible Idle, but accessible
DMU & PMU Active Accessible Accessible
Flash Module Active Active Powered down
Watchdog Timer Functioning as Functioning as Functioning as
programmed programmed programmed
FPI Bus Functioning as Functioning as Peripherals with
Peripherals programmed programmed suspend enabled are
shut down
Debug Units Functioning Functioning Functioning
External Bus Functioning as Functioning as Functioning as
Controller (EBU) programmed programmed programmed
Ports Functioning as Functioning as Functioning as
programmed programmed programmed

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5.2 Configuration Input Sampling

Several device pins of the TC1796 are latched either by a hardware reset or power-on
reset operation. The latched states of such pins may directly determine the start-up
configuration and conditions of the TC1796. The latched pins are divided into two types:
• Software configuration inputs, which are latched into a register and have no direct
influence on the device start-up configuration
• Hardware configuration inputs, which directly influence the start-up behavior of the
TC1796
Table 5-3 determines which pins are latched either by a hardware or power-on reset
operation. The state of the corresponding signals is always latched at the rising edges
of HDRST or PORST.

Table 5-3 Configuration Input Sampling

Configuration Reset Signal Pins Remark
Type
Software HDRST P0.[15:0] The states of these pins are latched
Configuration in register SCU_SCLIR (see also
Section 10.3.3.2 on Page 10-24).
Hardware HDRST P10.[3:0] The states of these pins are used for
Configuration (HWFCG[3:0]) selection of the Boot option (see
Table 4-3 on Page 4-12). Its state is
latched in bit field RST_SR.HWCFG.
PORST BRKIN The state of this pin is used for
selection of the Boot option and for
debug purposes.
P5.3/TXD1A The state of this pin determines
whether oscillator bypass mode is
selected or not (see also Table 3-1
on Page 3-9)
BYPASS The state of this pin determines
whether P5.3/TXD1A is evaluated or
not. Additionally, the latched state of
BYPASS controls the noise
suppression filters of pins PORST,
HDRST, and NMI.
TESTMODE The state of this pin is used for device
test mode selection. For normal
device operation, this pin should be
always be set to 1 level.

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5.3 External Request Unit (ERU)

In many cases, external events are used to trigger actions inside a microcontroller. This
can be done by triggering external interrupts, which are then serviced by the CPU.
Another possibility is to activate module functions that are related to external signals,
such as the start of analog-to-digital conversions, counting control for a timer unit or to
start a DMA transfer.
Due to the large variety of possible conditions of external signals, the simple generation
of interrupt events after the detection of edges of the external signals might not be
enough. Therefore, it can become necessary to check for patterns (gating of functions)
or to reroute trigger events from one block to another.
In the TC1796, a flexible External Request Unit (ERU) makes it possible to generate
trigger events that are able to generate interrupts, trigger a DMA transfers, or start
analog-to-digital conversions.

Features
• Edge-detection of an input signal (rising, falling, or both edges)
• Event generation with combined conditions of input signals
• Pattern detection of input pins (e.g gating functionality)
• Flexible input signal selection
• Generation of multiple output trigger events possible
The block diagram of the ERU is shown in Figure 5-1.

External Request Unit (ERU)

External Request External Trigger Interrupt Gating

Selection Unit Logic Unit Logic Unit
(ERS) (ETL) (INTG)
4 Output
Input Channel 0
Channel 0
4 Output
Input Channel 1
External Channel 1 External
Request Request
Inputs 4 Output Outputs
Input Channel 2
Channel 2
4 Output
Input Channel 3
Channel 3

MCB05613

Figure 5-1 External Request Unit Block Diagram

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The External Request Select unit (ERS) has three parts:

• The External Request Selection unit (ERS) selects one input signal for each input
channel.
• The External Trigger Logic unit (ETL) selects the input channel’s input signal trigger
condition, and provides output signals to the output channel.
• The Interrupt Gating unit (INTG) combines the detected events of the ETL and
provides pattern recognition for each output channel, as well as triggering and gating
functions for A/D converters or DMA controller.
The functional blocks of the ERU are described in detail in the following sections.

5.3.1 Input Channel

Figure 5-2 shows the basic structure of an input channel. The input channel has two
parts, one part located in the ERS and one part located in the ETL. Two of the four input
channels are always controlled by one External Input Channel Register EICRn (n = 0, 1;
n = 0 applies to input channel 0 and 1, n = 1 applies to input channel 2 and 3). In the
following description, the index number “x” indicates the input channel number.

External Request EICRn EICRn

Selection Unit Event Trigger
Logic Unit EIENx INPx
(ERS)
(ETL)

EICRn INTx0
EICRn INTx1
LDENx RENx FENx
INTx2
EXISx
INTx3

INx0 EIFR FMR

INx Set Set
INx1 Synch. Edge FSx
INx2 Stage Detection INTFx
FCx
INx3 Clear Clear
INTFx

x = Number of input channel (n = 3-0) MCA05614

Figure 5-2 External Request Unit Input Channel

An input channel of the ERS contains an 4-to-1 input multiplexer (controlled by bit field
EICRn.EXISx) that selects one of four possible request input lines INx[3:0]. The selected
signal then becomes synchronized. This is required for further control purposes that are
done in the Event Trigger Logic Unit (ETL) of the input channel.

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The ETL of the input channel analyzes the synchronized output signal INx of the ERS by
an edge-detection logic. This edge-detection block generates a pulse (one clock cycle
long) when a signal transition is detected. The selection which signal transition (edge)
should generate a pulse (event) is done by two control bits, one for the rising edge
(EICRn.RENx) and one for the falling edge (EICRn.FENx). Therefore, only a rising or
falling edge, or both edges of the input signal can be detected. When a selected signal
transition is detected, the external interrupt flag EIFRn.INTFx becomes always set by
hardware, even it is has been set previously. The interrupt flag EIFRn.INTFx is available
as output signal INTFx of the ETL.
The hardware reset condition for EIFRn.INTFx can be controlled in two different ways.
These two modes are selected by bit EIFRn.LDENx.
• EIFRn.LDENx = 0:
Flag EIFRn.INTFx is used as a sticky bit, indicating that the selected signal transition
has been detected by the edge-detection logic at least once. In this mode, bit
EIFRn.INTFx can be cleared only by software.
• EIFRn.LDENx = 1:
In this mode, flag EIFRn.INTFx becomes cleared by hardware if an edge is detected
at the INx signal, that has not been selected. This means, EIFRn.INTFx is cleared by
hardware at a INx rising edge when EICRn.FENx = 1 and EIFRn.INTFx is cleared by
hardware at a INx falling edge when EICRn.RENx = 1. If both bits, EICRn.FENx and
EICRn.RENx, are set, flag EIFRn.INTFx becomes never cleared by hardware. In this
case, flag EIFRn.INTFx can be only cleared by software.
Flag EIFRn.INTFx can be set or cleared by software using the bits FSx or FCx in the flag
modification register FMR. Writing to FMR with bit FMR.FSx set sets flag EIFRn.INTFx.
Writing to FMR with bit FMR.FCx set clears flag EIFRn.INTFx. If both bits are set for one
input channel x, a set operation of the flag will be executed.
Each output pulse of the edge-detection block that sets the EIFRn.INTFx flag by
hardware can be routed also to one of the INTx[3:0] outputs of the ETL unit. The external
interrupt enable bit EICRn.EIENx = 1 enables the interrupt output pulse at the INTx[3:0]
outputs. Bit field EICRn.INPx controls which of the INTx[3:0] outputs is selected for the
output pulse.

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5.3.2 Output Channel

The output channel logic shown in Figure 5-3 is built in for each of the four output
channels.

IGCRn PDRR
IPENy3 IPENy2 IPENy1 IPENy0 GEENy IGPy PDRy
Interrupt Flags
from Input 2
Channels

INTF0
PDOUTy
INTF1 Pattern
Detection
INTF2 1 00
Logic
INTF3 0 01
GOUTy
10

11
Input Channel Output Channel y
Outputs Enable

INT0y
≥1 Edge
INT1y Detection
INT2y &
IOUTy
INT3y
≥1
TOUTy
INT0[3:0]
INT1[3:0]
INT2[3:0]
INT3[3:0]

x = Number of input channel (x = 0-3)

y = Number of output channel (y = 0-3)
MCA05615

Figure 5-3 Interrupt Gating Logic (Output Channel y)

The output signals of the output channel y can be used to trigger peripheral actions, DMA
requests, or interrupts.

PDOUTy Output Signal

The pattern detection output PDOUTy can be used to enable/disable peripheral
functions while a certain condition (pattern) is detected (level controlled output).
PDOUTy can be typically used to enable/disable analog-to-digital conversions. The
output PDOUTy is active as long as the programmed condition of input signals (INTFx)
is met.
Each INTFx output signal from input channel x is connected to each output channel y.
Bit IPENy[3:0] determine whether flag INTFx of input channel x takes part in the pattern
detection of output channel y. The output signal PDOUTy is an AND combination of all
INTFx inputs that are enabled by IPENyx = 1. In other words, the PDOUTy signal

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becomes active (high) when the selected input channel interrupt flags are at active (high)
level. The state of flag PDRR.PDRy indicates the actual state of the PDOUTy signal.

GOUTy Output Signal

The gating output GOUTy represents the programmable level of PDOUTy. This output
signal is not connected/used in TC1796 but referred in the register descriptions.

TOUTy Output Signal

The trigger output TOUTy combines all related event trigger sources. This output can be
used to request ADC conversions or to start other peripheral actions. TOUTy outputs
pulses.
The incoming high-level active interrupt request pulses INT0y to INT3y from the event
trigger logic are combined to one common interrupt request for the corresponding output
channel. The incoming signals remain inactive when an event has been detected but
another output channel has been selected by INPx in the channel event trigger logic. As
a result, only those interrupt requests are taken into account, that are targeting this
output channel (y).

IOUT Output Signal

The interrupt output IOUTy can be connected to an interrupt node, and combines the
gating functionality GOUTy (programmed level of PDOUTy) and the trigger functionality
of TOUTy. It can also be used to trigger module actions, such as DMA requests or GPTA
actions. IOUTy outputs pulses.

Output Channel Control Logic

A very useful additional feature is the possibility to gate the incoming interrupt requests
with the indication flags INTFx (x = 0-3) coming from the Event Trigger Logic of the Input
Channel x. This allows more gating capability for the interrupt generation. The output
channel can be activated when a trigger event occurs while a certain pattern is detected
(IGP = 10B), or while this pattern is not detected (IGP = 11B). If an indication flag should
not be taken into account for the gating of the interrupt requests, the related IPENyx bit
has to be 0.
Bit GEENy = 1enables the generation of a trigger event for output channel y when the
result of the pattern detection changes. When using this feature, a trigger (e.g. for an
interrupt) is generated during the first clock cycle when a pattern is detected or when it
is no longer detected.
The output of the gating AND of all interrupts request are also delayed by one clock cycle
to detect a change of the gating status (XOR), corresponding to the pattern detection.
The bit GEENy (gating edge enable) makes it possible to generate a pulse whenever the
gating status changes. Combined with the bit field IGPy, an event can be generated

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when a pattern is detected, when a pattern is no longer detected, or if both conditions

are true.

5.3.3 External Request Unit Implementation

This section describes how the ERU is interconnected within other on-chip modules.
The connections of the ERU input lines and the connections between input and output
channels are shown in Figure 5-4. Figure 5-5 shows how the outputs of the output
channels are connected to the A/D converters ADC0 and ADC1, to the DMA controller,
and to the GPTA modules.

External Request Unit (ERU)

P1.0 / REQ0 INT00
IN00
INT01
P7.0 / REQ4 IN01 Input Output
INT02 Channel
IN02 Channel
0 INT03 0
FCLP IN03
MSC0
INTF0 INTF[3:0]

INT10
P1.1 / REQ1 IN10
INT11
IN11 Input Output
P7.1 / REQ5 INT12 Channel
IN12 Channel
1 INT13 1
IN13
FCLP INTF1 INTF[3:0]
MSC1

INT20
IN20
P1.2 / REQ2 INT21
IN21 Input Output
INT22 Channel
P7.4 / REQ6 IN22 Channel
2 INT23 2
IN23
P1.3 / REQ3 INTF2 INTF[3:0]
P7.5 / REQ7
INT30
IN30
INT31
OUT0 IN31 Input Output
INT32 Channel
OUT8 IN32 Channel
3 INT33 3
OUT16 IN33
GPTA0 OUT17 INTF3 INTF[3:0]
OUT24
OUT25
MCA05616

Figure 5-4 Input Connections of External Request Unit

As shown in Figure 5-5, additional trigger lines ROUT are generated by the GPTA0
module. These lines detect rising edges at three dedicated GPTA0 outputs and can be
used to trigger ADC actions, for example. The GPTA0 outputs are connected to an edge-
detection logic to obtain a trigger pulse each time a rising edge is detected.

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ERU TGADCx.SW0GTSEL
SW0GT
0

Gating Inputs
PDOUT0 EGT
GOUT0 ASGT
Output N.C.
Channel 0 IOUT0 1
TOUT0 QGT
1
TGADCx.EGTSEL TGT
1
PDOUT1 0
GOUT1 TGADCx.
Output N.C.
Channel 1 IOUT1 ETRSEL
TOUT1
0

ETR
PDOUT2
GOUT2
Output N.C.
Channel 2 IOUT2
TOUT2 TGADCx.
SW0TRSEL

0
PDOUT3 SW0 ADCx
GOUT3 TR (x = 0, 1)
Output N.C.
Channel 3 IOUT3
TOUT3

0123
PDOUT TGADCx.
TTRSEL
SCU_REQ0
DMA SCU_REQ1 0
Controller SCU_REQ2
SCU_REQ3 TTR
DMA_
SYSSRC2

DMA_
SYSSRC3 TGADCx.
QTRSEL
GPTA_INT1 0
GPTA_INT2
GPTA_INT3 QTR
GPTA GPTA0_OUT3
GPTA0_OUT11
GPTA0_OUT28
rising edge detection

CAN
ECTT4
TTCAN ECTT5
0123 0123 012
IOUT TOUT ROUT MCA05617

Figure 5-5 Output Connections of External Request Unit

Note: The trigger and gating selection is independent for ADC0 and ADC1 (index “x”).

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5.3.4 External Request Unit Registers

Table 5-4 refer to the registers associated with the ERU Kernel as well as the two
TC1796 implementation-specific ERU registers, which control the ERU connections with
the A/D converters ADC0 and ADC1.

Table 5-4 External Trigger Request Unit Kernel Registers

Register Short Name Register Long Name Description
see
ERU Kernel Registers
EICR0 External Input Channel Register 0 Page 5-17
EICR1 External Input Channel Register 1 Page 5-20
EIFR External Input Flag Register Page 5-23
FMR Flag Modification Register Page 5-24
PDRR Pattern Detection Result Register Page 5-25
IGCR0 Interrupt Gating Register 0 Page 5-26
IGCR1 Interrupt Gating Register 1 Page 5-29
Implementation-specific ERU Registers
TGADC0 Trigger Gating ADC0 Register Page 5-32
TGADC1 Trigger Gating ADC1 Register Page 5-32

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The External Input Channel Register EICR0 and EICR1 for the external input channels
0 to 3 contain bits to configure the input gating logic IGL and the event trigger logic ETL.
A maximum of 12 input channels are supported by one input unit (defined by the
maximum number of IGCRy.IPENx bits).

EICR0
External Input Channel Register 0
(F0000080H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EI LD R F
0 INP1 0 EXIS1 0
EN1 EN1 EN1 EN1
r rw rw rw rw rw r rw r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EI LD R F
0 INP0 0 EXIS0 0
EN0 EN0 EN0 EN0
r rw rw rw rw rw r rw r

Field Bits Type Description

EXIS0 [5:4] rw External Input Selection 0
This bit field determines which input line is selected
for signal IN0.
00B Input IN00 is selected.
01B Input IN01 is selected.
10B Input IN02 is selected.
11B Input IN03 is selected.
FEN0 8 rw Falling Edge Enable 0
This bit determines if the falling edge of signal IN0 is
used to set bit INTF0.
0B The falling edge is not used.
1B The detection of a falling edge of IN0 generates
a trigger event (INTF0 becomes set).
REN0 9 rw Rising Edge Enable 0
This bit determines if the rising edge of signal IN0 is
used to set bit INTF0.
0B The rising edge is not used.
1B The detection of a rising edge of IN0 generates
a trigger event (INTF0 becomes set).

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Field Bits Type Description

LDEN0 10 rw Level Detection Enable 0
This bit determines if bit INTF0 is cleared
automatically if an edge of the input signal IN0 is
detected, which has not been selected (rising edge
with REN0 = 0 or falling edge with FEN0 = 0).
0B Bit INTF0 will not be cleared.
1B Bit INTF0 will be cleared.
EIEN0 11 rw External Interrupt Enable 0
This bit enables the generation of a trigger event for
request channel 0 (e.g. for interrupt generation) when
a selected edge is detected.
0B The trigger event is disabled.
1B The trigger event is enabled.
INP0 [14:12] rw Interrupt Node Pointer
This bit field determines the destination (output
channel) for trigger event 0 (if enabled by EIEN0).
X00B The event of input channel 0 triggers output
channel 0 (signal INT00).
X01B The event of input channel 0 triggers output
channel 1 (signal INT01).
X10B The event of input channel 0 triggers output
channel 2 (signal INT02).
X11B The event of input channel 0 triggers output
channel 3 (signal INT03).
EXIS1 [21:20] rw External Input Selection 1
This bit field determines which input line is selected
for signal IN1.
00B Input IN10 is selected.
01B Input IN11 is selected.
10B Input IN12 is selected.
11B Input IN13 is selected.
FEN1 24 rw Falling Edge Enable 1
This bit determines if the falling edge of signal IN1 is
used to set bit INTF1.
0B The falling edge is not used.
1B The detection of a falling edge of IN1 generates
a trigger event (INTF1 becomes set).

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Field Bits Type Description

REN1 25 rw Rising Edge Enable 1
This bit determines if the rising edge of signal IN1 is
used to set bit INTF1.
0B The rising edge is not used.
1B The detection of a rising edge of IN1 generates
a trigger event (INTF1 becomes set).
LDEN1 26 rw Level Detection Enable 1
This bit determines if bit INTF1 is cleared
automatically if an edge of the input signal IN1 is
detected, which has not been selected (rising edge
with REN1 = 0 or falling edge with FEN1 = 0).
0B Bit INTF1 will not be cleared.
1B Bit INTF1 will be cleared.
EIEN1 27 rw External Interrupt Enable 1
This bit enables the generation of a trigger event for
request channel 1 (e.g. for interrupt generation) when
a selected edge is detected.
0B The trigger event is disabled.
1B The trigger event is enabled.
INP1 [30:28] rw Interrupt Node Pointer
This bit field determines the destination (output
channel) for trigger event 1 (if enabled by EIEN1).
X00B The event of input channel 1 triggers output
channel 0 (signal INT10).
X01B The event of input channel 1 triggers output
channel 1 (signal INT11).
X10B The event of input channel 1 triggers output
channel 2 (signal INT12).
X11B The event of input channel 1 triggers output
channel 3 (signal INT13).
0 [3:0], r Reserved
[7:6], Read as 0; should be written with 0.
[19:15],
[23:22],
31

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EICR1
External Input Channel Register 1
(F0000084H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EI LD R F
0 INP3 0 EXIS3 0
EN3 EN3 EN3 EN3
r rw rw rw rw rw r rw r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EI LD R F
0 INP2 0 EXIS2 0
EN2 EN2 EN2 EN2
r rw rw rw rw rw r rw r

Field Bits Type Description

EXIS2 [5:4] rw External Input Selection 2
This bit field determines which input line is selected
for signal IN2.
00B Input IN20 is selected.
01B Input IN21 is selected.
10B Input IN22 is selected.
11B Input IN23 is selected.
FEN2 8 rw Falling Edge Enable 2
This bit determines if the falling edge of signal IN2 is
used to set bit INTF2.
0B The falling edge is not used.
1B The detection of a falling edge of IN2 generates
a trigger event (INTF3 becomes set).
REN2 9 rw Rising Edge Enable 2
This bit determines if the rising edge of signal IN2 is
used to set bit INTF2.
0B The rising edge is not used.
1B The detection of a rising edge of IN2 generates
a trigger event (INTF2 becomes set).

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System Units (Vol. 1 of 2)
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Field Bits Type Description

LDEN2 10 rw Level Detection Enable 2
This bit determines if bit INTF2 is cleared
automatically if an edge of the input signal IN2 is
detected, which has not been selected (rising edge
with REN2 = 0 or falling edge with FEN2 = 0).
0B Bit INTF2 will not be cleared.
1B Bit INTF2 will be cleared.
EIEN2 11 rw External Interrupt Enable 2
This bit enables the generation of a trigger event for
request channel 2 (e.g. for interrupt generation) when
a selected edge is detected.
0B The trigger event is disabled.
1B The trigger event is enabled.
INP2 [14:12] rw Interrupt Node Pointer
This bit field determines the destination (output
channel) for trigger event 2 (if enabled by EIEN2).
X00B The event of input channel 2 triggers output
channel 0 (signal INT20).
X01B The event of input channel 2 triggers output
channel 1 (signal INT21).
X10B The event of input channel 2 triggers output
channel 2 (signal INT22).
X11B The event of input channel 2 triggers output
channel 3 (signal INT23).
EXIS3 [21:20] rw External Input Selection 3
This bit field determines which input line is selected
for signal IN3.
00B Input IN30 is selected.
01B Input IN31 is selected.
10B Input IN32 is selected.
11B Input IN33 is selected.
FEN3 24 rw Falling Edge Enable 3
This bit determines if the falling edge of signal IN3 is
used to set bit INTF3.
0B The falling edge is not used.
1B The detection of a falling edge of IN3 generates
a trigger event (INTF3 becomes set).

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System Units (Vol. 1 of 2)
System Control Unit

Field Bits Type Description

REN3 25 rw Rising Edge Enable 3
This bit determines if the rising edge of signal IN3 is
used to set bit INTF3.
0B The rising edge is not used.
1B The detection of a rising edge of IN3 generates
a trigger event (INTF3 becomes set).
LDEN3 26 rw Level Detection Enable 3
This bit determines if bit INTF3 is cleared
automatically if an edge of the input signal IN3 is
detected, which has not been selected (rising edge
with REN3 = 0 or falling edge with FEN3 = 0).
0B Bit INTF3 will not be cleared.
1B Bit INTF3 will be cleared.
EIEN3 27 rw External Interrupt Enable 3
This bit enables the generation of a trigger event for
request channel 3 (e.g. for interrupt generation) when
a selected edge is detected.
0B The trigger event is disabled.
1B The trigger event is enabled.
INP3 [30:28] rw Interrupt Node Pointer
This bit field determines the destination (output
channel) for trigger event 3 (if enabled by EIEN3).
X00B The event of input channel 3 triggers output
channel 0 (signal INT30).
X01B The event of input channel 3 triggers output
channel 1 (signal INT31).
X10B The event of input channel 3 triggers output
channel 2 (signal INT32).
X11B The event of input channel 3 triggers output
channel 3 (signal INT33).
0 [3:0], r Reserved
[7:6], Read as 0; should be written with 0.
[19:15],
[23:22],
31

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System Units (Vol. 1 of 2)
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The External Input Flag Register EIFR contains all interrupt flags for the external input
channels. The bits in this register can be cleared by software by setting FMR.FCx, and
set by setting FMR.FSx.

EIFR
External Input Flag Register (F0000088H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT INT INT INT
0
F3 F2 F1 F0
r rh rh rh rh

Field Bits Type Description

INTFx x rh External Interrupt Flag of Channel x
(x = 0-3) This bit monitors the status flag of the event trigger
condition for the input channel x. This bit is
automatically cleared when the selected condition
(see RENx, FENx) is no longer met (if LDENx = 1) or
remains set until it is cleared by SW (if LDENx = 0).
0 [31:4] r Reserved
Read as 0; should be written with 0.

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System Units (Vol. 1 of 2)
System Control Unit

The Flag Modification Register is a write-only register that is used to set and to clear the
bits INTFx in register EIFR. If a set event and a clear event (hardware or software) for bit
INTFx occur at the same time, the set event is taken into account.

FMR
Flag Modification Register (F000008CH) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FC FC FC FC
0
3 2 1 0
r w w w w

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS FS FS FS
0
3 2 1 0
r w w w w

Field Bits Type Description

FSx x w Set Flag INTFx for Channel x
(x = 0-3) Setting this bit will set the corresponding bit INTFx in
register EIFR. Reading this bit always delivers a 0.
0B The bit x in register EIFR is not modified.
1B The bit x in register EIFR is set.
FCx 16 + x w Reset Flag INTFx for Channel x
(x = 0-3) Setting this bit will clear the corresponding bit INTFx
in register EIFR. Reading this bit always delivers a 0.
0B The bit x in register EIFR is not modified.
1B The bit x in register EIFR is reset.
0 [15:4], r Reserved
[31:20] Read as 0; should be written with 0.

Note: This register is virtual and does not contain any flip-flop.

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System Units (Vol. 1 of 2)
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The Pattern Detection Result Register monitors the combinatorial output status of the
pattern detection units.

PDRR
Pattern Detection Result Register (F0000090H) Reset Value: 0000 000FH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDR PDR PDR PDR
0
3 2 1 0
r rh rh rh rh

Field Bits Type Description

PDRy y rh Pattern Detection Result of Channel y
(y = 0-3) This bit monitors the output status of the pattern
detection for the output channel y.
0 [31:4] r Reserved
Read as 0; should be written with 0.

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System Units (Vol. 1 of 2)
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The Interrupt Gating Control Registers IGCR0 and IGCR1 contain bits to enable the
pattern detection and to control the gating for output channel 0 to 3 (e.g. for interrupt
nodes or peripherals).

IGCR0
Interrupt Gating Register 0 (F0000094H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GE IPEN IPEN IPEN IPEN
IGP1 0
EN1 13 12 11 10
rw rw r rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GE IPEN IPEN IPEN IPEN
IGP0 0
EN0 03 02 01 00
rw rw r rw rw rw rw

Field Bits Type Description

IPEN0x x rw Interrupt Pattern Enable for Channel 0
(x = 0-3) Bit IPEN0x determines the flag INTFx of channel x
takes part in the pattern detection for the gating of the
requests for the output signals GOUTy and IOUTy.
0B The bit INTFx does not take part in the pattern
detection.
1B The bit INTFx is taken into consideration for the
pattern detection.
GEEN0 13 rw Generate Event Enable 0
Bit GEEN0 enables the generation of a trigger event
for output channel 0 when the result of the pattern
detection changes. When using this feature, a trigger
(e.g. for an interrupt) is generated during the first
clock cycle when a pattern is detected or when it is no
longer detected.
0B The trigger generation at a change of the
pattern detection result is disabled.
1B The trigger generation at a change of the
pattern detection result is enabled.

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Field Bits Type Description

IGP0 [15:14] rw Interrupt Gating Pattern 0
Bit field IGP0 determines how the pattern detection
influences the output lines GOUT0 and IOUT0.
00B The detected pattern is not taken into account.
An activation of IOUT0 is always possible due
to a trigger event.
01B The detected pattern is not taken into account.
An activation of IOUT0 is not possible.
10B The detected pattern is taken into account. An
activation of IOUT0 is only possible due to a
trigger event while the pattern is detected.
11B The detected pattern is taken into account. An
activation of IOUT0 is only possible due to a
trigger event while the pattern is not detected.
IPEN1x 16+x rw Interrupt Pattern Enable for Channel 1
(x = 0-3) Bit IPEN1x determines if the flag INTFx of channel x
takes part in the pattern detection for the gating of the
requests for the output signals GOUTy and IOUTy.
0B The bit INTFx does not take part in the pattern
detection.
1B The bit INTFx is taken into consideration for the
pattern detection.
GEEN1 29 rw Generate Event Enable 1
Bit GEEN1 enables the generation of a trigger event
for output channel 1 when the result of the pattern
detection changes. When using this feature, a trigger
(e.g. for an interrupt) is generated during the first
clock cycle when a pattern is detected, or when it is
no longer detected.
0B The trigger generation at a change of the
pattern detection result is disabled.
1B The trigger generation at a change of the
pattern detection result is enabled.

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System Units (Vol. 1 of 2)
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Field Bits Type Description

IGP1 [31:30] rw Interrupt Gating Pattern 1
Bit field IGP1 determines how the pattern detection
influences the output lines GOUT1 and IOUT1.
00B The detected pattern is not taken into account.
An activation of IOUT1 is always possible due
to a trigger event.
01B The detected pattern is not taken into account.
An activation of IOUT1 is not possible.
10B The detected pattern is taken into account. An
activation of IOUT1 is only possible due to a
trigger event while the pattern is detected.
11B The detected pattern is taken into account. An
activation of IOUT1 is only possible due to a
trigger event while the pattern is not detected.
0 [12:4], r Reserved
[28:20] Read as 0; should be written with 0.

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System Units (Vol. 1 of 2)
System Control Unit

IGCR1
Interrupt Gating Register 1 (F0000098H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GE IPEN IPEN IPEN IPEN
IGP3 0
EN3 33 32 31 30
rw rw r rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GE IPEN IPEN IPEN IPEN
IGP2 0
EN2 23 22 21 20
rw rw r rw rw rw rw

Field Bits Type Description

IPEN2x x rw Interrupt Pattern Enable for Channel 2
(x = 0-3) Bit IPEN2x determines if the flag INTFx of channel x
takes part in the pattern detection for the gating of the
requests for the output signals GOUTy and IOUTy.
0B The bit INTFx does not take part in the pattern
detection.
1B The bit INTFx is taken into consideration for the
pattern detection.
GEEN2 13 rw Generate Event Enable 2
Bit GEEN2 enables the generation of a trigger event
for output channel 2 when the result of the pattern
detection changes. When using this feature, a trigger
(e.g. for an interrupt) is generated during the first
clock cycle when a pattern is detected, or when it is
no longer detected.
0B The trigger generation at a change of the
pattern detection result is disabled.
1B The trigger generation at a change of the
pattern detection result is enabled.

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System Units (Vol. 1 of 2)
System Control Unit

Field Bits Type Description

IGP2 [15:14] rw Interrupt Gating Pattern 2
Bit field IGP2 determines how the pattern detection
influences the output lines GOUT2 and IOUT2.
00B The detected pattern is not taken into account.
An activation of IOUT2 is always possible due
to a trigger event.
01B The detected pattern is not taken into account.
An activation of IOUT2 is not possible.
10B The detected pattern is taken into account. An
activation of IOUT2 is only possible due to a
trigger event while the pattern is detected.
11B The detected pattern is taken into account. An
activation of IOUT2 is only possible due to a
trigger event while the pattern is not detected.
IPEN3x 16+x rw Interrupt Pattern Enable for Channel 3
(x = 0-3) Bit IPEN3x determines if the flag INTFx of channel x
takes part in the pattern detection for the gating of the
requests for the output signals GOUTy and IOUTy.
0B The bit INTFx does not take part in the pattern
detection.
1B The bit INTFx is taken into consideration for the
pattern detection.
GEEN3 29 rw Generate Event Enable 3
Bit GEEN3 enables the generation of a trigger event
for output channel 3 when the result of the pattern
detection changes. When using this feature, a trigger
(e.g. for an interrupt) is generated during the first
clock cycle when a pattern is detected, or when it is
no longer detected.
0B The trigger generation at a change of the
pattern detection result is disabled.
1B The trigger generation at a change of the
pattern detection result is enabled.

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System Units (Vol. 1 of 2)
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Field Bits Type Description

IGP3 [31:30] rw Interrupt Gating Pattern 3
Bit field IGP3 determines how the pattern detection
influences the output lines GOUT3 and IOUT3.
00B The detected pattern is not taken into account.
An activation of IOUT3 is always possible due
to a trigger event.
01B The detected pattern is not taken into account.
An activation of IOUT3 is not possible.
10B The detected pattern is taken into account. An
activation of IOUT3 is only possible due to a
trigger event while the pattern is detected.
11B The detected pattern is taken into account. An
activation of IOUT3 is only possible due to a
trigger event while the pattern is not detected.
0 [12:4], r Reserved
[28:20] Read as 0; should be written with 0.

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System Units (Vol. 1 of 2)
System Control Unit

The Trigger Gating ADC0 Register TGADC0 contains bit fields that determine the
assignment of the output signals of the external request unit to the trigger and gating
inputs of ADC0. The Trigger Gating ADC1 Register TGADC1 contains bit fields that
determine the assignment of the output signals of the external request unit to the trigger
and gating inputs of ADC1. Suffix “x” (x = 0,1) in the bit descriptions refers to the
corresponding A/D converter, ADC0 or ADC1.

TGADC0
Trigger Gating ADC0 Register (F000009CH) Reset Value: 0000 0000H
TGADC1
Trigger Gating ADC1 Register (F00000A0H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0 SW0GTSEL 0 EGTSEL

r rw r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 TTRSEL 0 QTRSEL 0 SW0TRSEL 0 ETRSEL

r rw r rw r rw r rw

Field Bits Type Description

ETRSEL [2:0] rw External Trigger Request Selection
This bit determines which trigger source will be used
for the external trigger request input ETR of ADCx.
000B ETR is constant at 0 level (trigger function
switched off).
001B ROUT0 is connected to ETR.
010B ROUT1 is connected to ETR.
011B ROUT2 is connected to ETR.
100B TOUT0 is connected to ETR.
101B TOUT1 is connected to ETR.
110B TOUT2 is connected to ETR.
111B TOUT3 is connected to ETR.

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Field Bits Type Description

SW0TRSEL [6:4] rw SW0 Trigger Request Selection
This bit determines which trigger source will be used
for the SW0 trigger request input SW0TR of ADCx.
000B SW0TR is constant at 0 level (trigger function
switched off).
001B ROUT0 is connected to SW0TR.
010B ROUT1 is connected to SW0TR.
011B ROUT2 is connected to SW0TR.
100B TOUT0 is connected to SW0TR.
101B TOUT1 is connected to SW0TR.
110B TOUT2 is connected to SW0TR.
111B TOUT3 is connected to SW0TR.
QTRSEL [10:8] rw Queue Trigger Request Selection
This bit determines which trigger source will be used
for the queue trigger request input QTR of ADCx.
000B QTR is constant at 0 level (trigger function
switched off).
001B ROUT0 is connected to QTR.
010B ROUT1 is connected to QTR.
011B ROUT2 is connected to QTR.
100B TOUT0 is connected to QTR.
101B TOUT1 is connected to QTR.
110B TOUT2 is connected to QTR.
111B TOUT3 is connected to QTR.
TTRSEL [14:12] rw Timer Trigger Request Selection
This bit determines which trigger source will be used
for the timer trigger request input TTR of ADCx.
000B TTR is constant at 0 level (trigger function
switched off).
001B ROUT0 is connected to TTR.
010B ROUT1 is connected to TTR.
011B ROUT2 is connected to TTR.
100B TOUT0 is connected to TTR.
101B TOUT1 is connected to TTR.
110B TOUT2 is connected to TTR.
111B TOUT3 is connected to TTR.

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System Units (Vol. 1 of 2)
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Field Bits Type Description

EGTSEL [18:16] rw External Gating Selection
This bit determines which trigger source will be used
for the external gating input EGT of ADCx.
000B EGT is constant at 0 level (externally triggered
conversions permanently disabled).
001B PDOUT1 is connected to EGT.
010B PDOUT2 is connected to EGT.
011B PDOUT3 is connected to EGT.
100B EGT is constant at 1 level (externally triggered
conversions permanently enabled).
101B PDOUT1 is connected to EGT.
110B PDOUT2 is connected to EGT.
111B PDOUT3 is connected to EGT.
SW0GTSEL [22:20] rw SW0 Gating Selection
This bit determines which trigger source will be used
for the SW0 gating input SW0GT of ADCx.
000B SW0GT is constant at 0 level (SW0 triggered
conversions permanently disabled).
001B PDOUT0 is connected to SW0GT.
010B PDOUT2 is connected to SW0GT.
011B PDOUT3 is connected to SW0GT.
100B SW0GT is constant at 1 level (SW0 triggered
conversions permanently enabled).
101B PDOUT0 is connected to SW0GT.
110B PDOUT2 is connected to SW0GT.
111B PDOUT3 is connected to SW0GT.
0 3, 7, 11, r Reserved
15, 19, Read as 0; should be written with 0.
[31:23]

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System Units (Vol. 1 of 2)
System Control Unit

5.4 Special System Interrupts

For some of the possible interrupts in the system, the interrupt control logic is not directly
controlled in the module, but via the SCU, e.g. for the FPU interrupts, which are
generated in the CPU, but have to be processed outside the CPU.

5.4.1 FPU Interrupts

The FPU provides two interrupts outputs that are activated in case of error conditions:
• Signal FPU_Exception1, which is activated if any of the error flags including the
inexact flag FX is set
• Signal FPU_Exception2, which is activated if any of the error flags excluding the
inexact flag FX is set
Both interrupts are combined to one interrupt request output that is controlled by register
DMA_SYSSCR0 in the DMA controller. Bit SCU_CON.FIEN determines whether an
inexact condition will lead to an interrupt or not.
When an FPU interrupt is generated, the related FPU status flags are latched into the
corresponding bits of the SCU Status Register SCU_STAT (see Page 5-67). Thus, the
status of the last floating point instruction that caused an interrupt can be read from
SCU_STAT.
The exception status information at the FPU output bus FPU_Exception_PSW is
connected to the bits in the SCU_STAT register as shown in Figure 5-6.

FPU_Exception_PSW
To PSW
30 29 28 27 26

SCU_STAT
Latch
FII FVI FZI FUI FXI
4 3 2 1 0

SCU_CON
FPU
FIEN
0
&
FPU_Exception1
To interrupt
≥1 node
FPU_Exception2 in the DMA
Controller

MCA05618

Figure 5-6 FPU Interrupt Control

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The FPU interrupt uses the system interrupt node DMA_SYSSRC0 located in the DMA
controller. A description of this register can be found on Page 12-108. Note that
DMA_SYSSRC0.TOS should be written with 00B because FPU interrupt should only be
serviced by the CPU (and not by the PCP).

5.4.2 Flash Interrupt

The flash module can generate an interrupt when the following conditions occur:
• End-of-busy state
• Protection error
• Sequence error
• Single-bit ECC error
Each source can be individually enabled and disabled. The detailed description of the
flash interrupt generation can be found at “Flash Interrupt Generation and Control”
on Page 7-36. The Flash interrupt uses the system interrupt node DMA_SYSSRC1
located in the DMA module.

5.4.3 External Interrupts

As shown in Figure 5-5 on Page 5-15, the External Request Unit provides two interrupt
sources for events on external pins. The interrupt events can be defined by programming
the corresponding registers in the ERU.
The two ERU interrupts are controlled by the system interrupt nodes DMA_SYSSRC2
and DMA_SYSSRC3 located in the DMA module. A description of this register can be
found on Page 12-108.

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System Units (Vol. 1 of 2)
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5.5 SRAM Parity Control

In TC1796, several on-chip memory blocks are equipped with a parity error detection
logic. Each memory block as defined in Table 5-5 provides a parity error detection logic.
This logic asserts a parity error signal when a parity error is detected in the related
memory block. An active parity error signal sets a parity error flag, PFLx (x = 0-6). If
enabled by the specific parity enable control bit PENx, a non-maskable (NMI) is
generated.
The bits PENx (parity error x enable) and PFLx (parity error flag) are located in the
registers SCU_PETCR and SCU_PETSR respectively.

Table 5-5 On-chip SRAM with Parity Error Detection

Module Memory Block Parity Error Parity
Flag Enable Bit
DMI Data Memory (LDRAM, DPRAM) PFL0 PEN0
PMI Code Scratchpad RAM & Instruction Cache PFL1 PEN1
(SPRAM, ICACHE)
Program Cache Tag RAM PFL2 PEN2
DMU Data Memory (SBRAM, SRAM) PFL3 PEN3
PCP Parameter RAM (PRAM) PFL4 PEN4
Code Memory (CMEM) PFL5 PEN5
CAN Module memories PFL6 PEN6

After a Boot ROM exit, the parity logic is generally enabled (initial value of
SCU_STAT.PARAV = 1), but all specific parity enable control bits PENx are cleared
(parity disabled). During normal operation of the TC1796, the SRAM parity error logic
can be generally disabled only once (PARAV clear) when the SCU_CON.RPARAV bit is
written with 1. Note that if PARAV = 0, the SRAM parity error logic cannot be enabled
anymore except by a power-on reset operation.
Before the parity logic of an SRAM memory block can be used the first time after a
power-on reset operation (before setting its SCU_PETCR.PENx enable bit), the
corresponding memories must be completely initialized by writing every memory location
of it once (exceptions: MultiCAN module memories, Program Cache Tag RAM, and
ICACHE). Otherwise, unpredictable parity errors may occur after setting its
SCU_PETCR.PENx enable bit.
Furthermore, before setting any SCU_PETCR.PENx enable bit after a power-on reset,
register SCU_PETSR should be read once to clear parity error flags, that could have
been set by parity logic tests during the Boot ROM code execution.
Figure 5-7 shows the functionality of the SRAM parity error control in the SCU.

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SCU_PETSR SCU_PETCR

PFL0 PEN0
Set
Data Memory ≥1
Parity Error
. .
. .
. .
. .
Non-Maskable
Interrupt
SCU_PETSR SCU_PETCR
PFL6 PEN6
Set
CAN Module
Memory
Parity Error
MCA06448

Figure 5-7 Control of SRAM Parity Error Detection in SCU

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System Units (Vol. 1 of 2)
System Control Unit

5.5.1 Parity Error Trap Registers

Additional details about the NMI handling of SRAM parity errors are described in section
“SRAM Parity Error NMI” on Page 14-26.

SCU_PETCR
SCU Parity Error Trap Control Register
(F00000D0H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEN PEN PEN PEN PEN PEN PEN
0
6 5 4 3 2 1 0
r rw rw rw rw rw rw rw

Field Bits Type Description

PENx x rw Parity Error Trap Enable for SRAM Module x
(x = 0-6) These bits determine whether an NMI trap is
generated if a parity error is detected in the
associated SRAM memory module. The assignment
of the enable bits to the SRAM modules is defined in
Table 5-5.
0B NMI parity error trap is disabled.
1B NMI parity error trap is enabled.
0 [31:7] r Reserved
Read as 0; should be written with 0.

Note: SFR SCU_PETCR is Endinit-protected for write operations.

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SCU_PETSR
SCU Parity Error Trap Status Register
(F00000D4H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFL PFL PFL PFL PFL PFL PFL
0
6 5 4 3 2 1 0
r rh rh rh rh rh rh rh

Field Bits Type Description

PFLx x rh Parity Error Flag for SRAM Module x
(x = 0-6) These bits indicate whether a parity error has been
detected in the associated SRAM memory module.
The assignment of the error flags to the SRAM
modules is defined in Table 5-5.
0B No parity error detected.
1B Parity error is detected.
The PFLx bits are cleared by hardware after a read
access.
0 [31:7] r Reserved
Read as 0.

Note: SCU_PETSR is a read-only register. Writing to SCU_PETSR results in a bus

error.

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System Units (Vol. 1 of 2)
System Control Unit

5.6 Pad Driver Temperature Compensation Control

In the TC1796, two groups of pads can be controlled separately by a temperature
compensation control logic:
• Class B1/B2 pads of the EBU interface when used as outputs
• Class A2 pads in strong-driver mode (see Table 5-6 on Page 5-43)

5.6.1 Functional Description

The temperature compensation for the pad output drivers makes it possible to get stable
driver output characteristics within dedicated portions of the specified temperature
range. As shown in Figure 5-8, the temperature compensation requires a 100 kHz
reference input clock signal that is derived from the bus clock fSYS by a programmable
divider (TCDIV). This reference input clock fREF is fed into a 12-bit free-running counter
(SCOUNT). After each overflow of SCOUNT, the pad oscillator circuit (fPOSC), which is
located in the pad area, and an 8-bit counter (THCOUNT) are enabled for one clock
period of the reference clock. The oscillator circuit is temperature-sensitive and typically
has a much higher frequency (8 - 16 MHz) than fREF. The 8-bit counter counts the fPOSC
pulses and its count value THCOUNT when stopped again is compared against three
threshold values stored in THMAX, THMED, and THMIN. These thresholds must be set
accordingly to the application needs for proper operation of the temperature
compensation.
The temperature compensation can be controlled for two separate groups: All outputs at
GPIO ports (Port 0 to 10), and all EBU output lines.
The clock divider TCDIV is programmed via bit field SCU_TCCON.TCDIV. TCDIV can
be calculated using the following formula:

TCDIV = RoundDown (2.5 × fSYS ) - 1 (5.1)

The resulting divide factor is TCDIV + 1 and leads to an update of the temperature
compensation approximately every 41 ms.
Example: for fSYS = 75 MHz, TCDIV = RoundDown (2.5 × 75) - 1 = 186D (= BAH).

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System
Control TCE1 TCS1
Unit THMIN1
2
THMED1 To Pad
M
THMAX1 2 Logic of
11B M U
U EBU
X
8 X Outputs
fSYS 100 KHz Control
4:1 1/TCDIV POSCEN
fREF TCV1 TCC1
THCOUNT

8 TCV0 TCC0

THMAX0
2 M To Pad
THMED0 U M Logic of
Pad 2
THMIN0 11B X U Class A2
fPOSC X GPIO
OSC Temperature Outputs
Enable
Compensation
TCE0 TCS0
Control

MCB05619

Figure 5-8 Pad Driver Temperature Compensation Block Diagram

Generally, temperature compensation is a transparent feature. Bit field
SCU_TCLRx.THCOUNT (x = 0, 1) of both temperature compensation x level registers
provides direct access to the actual compensation (counter) value and allows software
adjustment control of the port temperature compensation logic. This is useful for two
situations:
1. Device testing: The function of the compensation mechanism can be verified during
production testing or characterization.
2. User control: During operation the device can be controlled via externally provided
compensation values rather than via the internal mechanism.
Temperature compensation is initialized by programming register SCU_TCCON (enable
and prescaler for 100 kHz reference clock) and register SCU_TCLR0 and SCU_TCLR1
(levels values).
The temperature-dependent counter value THCOUNT is compared against three
thresholds values (correspond to a certain temperature level) at which the 2-bit output
signals to the pad logic are switched (see Figure 5-9). The three threshold values are
defined by three bit fields in the port temperature compensation 0/1 level registers
SCU_TCLR0 and SCU_TCLR1. The pads support different driving levels and are
controlled via the 2-bit output signals.

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The switching thresholds are evaluated hierarchically (see Table 5-6). For proper
operation the relationship THMIN > THMED > THMAX must be true. With increasing
temperature, the compensation value SCU_TCLRx.THCOUNT decreases.

Table 5-6 Switching Threshold Hierarchy

Output Driver Control Relationship between
THCOUNT and THMAX, THMED, THMIN
Maximum Level THCOUNT < THMAX
High Level THMED ≥ THCOUNT > THMAX
Low Level THMIN ≥ THCOUNT > THMED
Minimum Level THCOUNT > THMIN

Note: The reset value FFH for the thresholds ensures that the drivers operate on
maximum level if the threshold values have not been initialized.
Note: Reprogramming of the threshold levels in registers SCU_TCLR0 and
SCU_TCLR1 should only be executed while the temperature compensation is
disabled.

Driver THCOUNT
Level
TCV = 11B
Max

THMIN
TCV = 10B
High
THMED

THMAX
TCV = 01B
Low
Count
= function of Temp.

TCV = 00B
Min Thresholds

Temp.
-40 °C 0 °C 40 °C 80 °C 125 °C
MCD05620

Figure 5-9 Temperature Compensation Switching Thresholds

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5.6.2 Temperature Compensation Registers

Note: Control/status bits with index 0 are assigned for output control of class A2 GPIO
output lines. Control/status bits with index 1 are assigned for EBU output control.

SCU_TCCON
SCU Temperature Compensation Control Register
(F0000048H) Reset Value: 0003 0003H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCS TCC TCE TCV
0 0 0
1 1 1 1
r rw r rw rw r rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCS TCC TCE TCV
TCDIV 0 0
0 0 0 0
rw rw r rw rw r rh

Field Bits Type Description

TCV0 [1:0] rh Temperature Compensation 0 Value
This bit field indicates the compensation value that is
generated for the temperature compensation logic 0.
TCV0 is fed to the temperature compensation logic 0
outputs while bit TCS0 = 0.
00B Minimum driving strength required, i.e. very
low temperature.
...B ...
11B Maximum driving strength required, i.e. very
high temperature (default after reset).
TCE0 3 rw Temperature Compensation 0 Enable
0B Temperature compensation logic 0 is
deactivated (default after reset). The port
drivers are at maximum driver level.
1B Temperature compensation logic 0 is active.
THCOUNT is periodically updated.
TCC0 [5:4] rw Temperature Compensation 0 Control
This 2-bit value is fed to the temperature
compensation logic 0 outputs while bit TCS0 = 1.
Encoding of TCC0 is equal to TCV0.

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Field Bits Type Description

TCS0 7 rw Temperature Compensation 0 Source
0B Temperature compensation logic 0 is
controlled by the temperature compensation
control hardware.
1B Temperature compensation logic 0 is
controlled by software via bit field TCC0.
TCDIV [15:8] rw Temperature Compensation Clock Divider
This value controls the input clock divider for the
temperature compensation logic.
TCV1 [17:16] rh Temperature Compensation 1 Value
This bit field indicates the compensation value which
is generated for the temperature compensation
logic 1. TCV0 is fed to the temperature
compensation logic 0 outputs while bit TCS1 = 0.
00B Minimum driving strength required, i.e. very
low temperature.
...B ...
11B Maximum driving strength required, i.e. very
high temperature (default after reset).
TCE1 19 rw Temperature Compensation 1 Enable
0B Temperature compensation logic 1 is
deactivated (default after reset). The port
drivers are at maximum driver level.
1B Temperature compensation logic 1 is active.
THCOUNT is periodically updated.
TCC1 [21:20] rw Temperature Compensation 1 Control
This 2-bit value is fed to the temperature
compensation logic 1 outputs while bit TCS1 = 1.
Encoding of TCC1 is equal to TCV1.
TCS1 23 rw Temperature Compensation 1 Source
0B Temperature compensation logic 1 is
controlled by the temperature compensation
control hardware.
1B Temperature compensation logic 1 is
controlled by software via bit field TCC1.
0 2, 6, r Reserved
18, 22, Read as 0; should be written with 0.
[31:24]

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SCU_TCLR0
SCU Temperature Compensation 0 Level Register
(F0000058H) Reset Value: 02FF FFFFH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

THCOUNT THMAX0

rh rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

THMED0 THMIN0

rw rw

Field Bits Type Description

THMIN0 [7:0] rw Minimum Threshold for Temp. Compensation 0
Driver level = Low or Min
THMED0 [15:8] rw Medium Threshold for Temp. Compensation 0
Driver level = High or Low
THMAX0 [23:16] rw Maximum Threshold for Temp. Compensation 0
Driver level = Max or High
THCOUNT [31:24] rh Threshold Counter
Returns the actual count value of the counter that
counts the fPOSC clock pulses. THCOUNT is only
updated when temperature compensation is enabled
(TCE0 or TCE1 or both set).

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SCU_TCLR1
SCU Temperature Compensation 1 Level Register
(F000005CH) Reset Value: 02FF FFFFH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

THCOUNT THMAX1

rh rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

THMED1 THMIN1

rw rw

Field Bits Type Description

THMIN1 [7:0] rw Minimum Threshold for Temp. Compensation 1
Driver level = Low or Min
THMED1 [15:8] rw Medium Threshold for Temp. Compensation 1
Driver level = High or Low
THMAX1 [23:16] rw Maximum Threshold for Temp. Compensation 1
Driver level = Max or High
THCOUNT [31:24] rh Threshold Counter
Returns the actual count value of the counter that
counts the fPOSC clock pulses. THCOUNT is only
updated when temperature compensation is enabled
(TCE0 or TCE1 or both set).

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5.7 Die Temperature Sensor

The TC1796 provides an on-chip Die Temperature Sensor (DTS). The output voltage of
the DTS can be measured using analog input AIN31 of the ADC1 module. For measuring
the DTS output voltage, the following conditions must be met:
• The DTS circuitry has to be enabled by setting SCU_CON.DTSON = 1. After
enabling the DTS, a settling time of about 10 µs has to be respected before starting
a DTS measurement.
• Bit ADC1_CHCON15.EMUX[0] has to be set to 1 for channel 15 of ADC1.
• The analog input AIN31 of ADC1 has to be requested for conversion (corresponding
GRPS = 1). With this request, the reference voltages of the DTS (VAREF_DTS,
VANGD_DTS) and the sensor output signal (VDTS) are connected to ADC1 for AD
conversion.

SCU_CON ADC1_CHCON15
DTSON EMUX
=1 = X1B &
Analog
channel 31
requested for
conversion

Enable VSSM 0 M
U AIN31
VDTS X
1

ADC1
Die VAREF1 0 M
Temp. U VAREF
Sensor VAREF_DTS X
DTS 1

VAGND1 0 M
VAGND_DTS
U VAGND
1
X

MCA05621

Figure 5-10 Die Temperature Sensor Selection

The die temperature can be determined according to the equation:

temp_ao[V] = 1.0 V + (die temperature + 40 °C) / 190 (5.2)

The DTS operates with an accuracy of ±10 °C.

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5.8 GPTA1 Input IN1 Control

In the TC1796, the input line IN1 of the GPTA0, GPTA1, and LTCA2 module can be used
to measure the baud rate of an ASC0 or ASC1 receiver input signal with GPTA1. This
feature is controlled by a bit of the SCU, SCU_CON.GIN1S. Bit GIN1S controls a 4-to-1
multiplexer that makes it possible to switch several port lines to the IN1 input of the
GPTA1 module. After reset, the nominal GPTA input IN1 (P2.9) is connected to IN1 of
GPTA.

Table 5-7 GPTA1 Input Line IN1 Connections

SCU_CON.GIN1S GPTA1 Input IN1 Connected to
00B P2.9 / IN1 (default after reset)
01B P5.0 / RXD0A
10B P6.8 / RXD0B
11B P6.10 / RXD1B

SCU_CON
GIN1S
GPTA0
2
IN1
P2.9 / IN1

P5.0 / RXD0A GPTA1

M
U IN1
P6.8 / RXD0B X

P6.10 / RXD1B LTCA2

IN1

MCA05622_mod

Figure 5-11 GPTA1 Input IN1 Control

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5.9 Pad Test Mode Control

The pad test mode control logic in the SCU can be used for in-system tests of board
connections for dedicated pins (pins without GPIO functionality). The pad test mode can
be enabled in the normal operating mode of the TC1796. A special enable procedure
(two-word write sequence) avoids unintentionally enabling the pad test mode.
The pad test mode control logic especially makes it possible to:
• Output a value (low- or high-level) to dedicated pins
• Read the logic level on dedicated pins
Figure 5-12 shows the pad test mode control logic for one pad/pin. Test data is read or
written via four pad test data registers. These registers with numbering index n (n = 0-3)
make it possible to access at maximum sixteen of the dedicated pins, independently
from each other.

SCU
Control
1
M
RDSSn PTMEN U
PTMLC 0
X
ENOUTn
0
M
U
X
FPI Bus

1
1
M
Read U
X
PTDATn 1 Bit in 0
Pad
Register
PTDATn Logic for Pad Driver
Regular
Write Operation
PTDATn of
I/O Pad
MCA05623

Figure 5-12 Pad Test Mode Control in the SCU

When the pad test mode is disabled (PTMEN = 0), the dedicated pads are in their normal
operating mode. The pad output drivers are controlled by the hardware part that
determines whether the dedicated pad/pin is used for input, output, or for I/O purposes.
When the pad test mode is enabled, PTMEM is set. A value written into register PTDATn
is always output at the corresponding pad as inverted state. This means when writing a
1 (0) to a bit of register PTDATn, a low (high) level will be available at the corresponding
dedicated pin. When reading register PTDATn, either the (non-inverted) logic level at the
dedicated pad (RDSSn = 0) or the value of the PTDATn register bit (RDSSn = 1) can be

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read back. The ENOUTn bits determine whether or not the logic level state as defined
by the bits in the SCU_PTDATn register is output to the pad/pin.

5.9.1 Pad Test Mode Enabling

To enable the pad test mode, the following two-word write sequence must be executed:
1. Writing SCU_PTCON with lock code PTMLC = 5AH
2. Writing SCU_PTCON with lock code PTMLC = A5H. After this write operation pad
test mode is enabled, as indicated by PTMEN = 1. Bits ENOUTn and RDSSn
determine the requested pad test mode configuration (enable, input selection).
When pad test mode is enabled, the test mode configuration (as defined through
ENOUTn and RDSSn) can be changed without leaving the pad test mode by writing
SCU_PTCON with new values for bits ENOUTn and RDSSn and PTMLC = A5H. In pad
test mode, any other write operation to SCU_PTCON with lock code PTMLC not equal
to A5H terminates the pad test mode.
After pad test mode has been enabled via the two-word write operation to SCU_PTCON,
it can be disabled again by any reset operation or a write operation to SCU_PTCON.

5.9.2 Pad Test Mode Registers

The pad test mode control logic contains five registers.

Table 5-8 Pad Test Mode Registers

Register Short Name Register Long Name Description
see
SCU_PTCON SCU Pad Test Control Register Page 5-52
SCU_PTDAT0 SCU Pad Test Data Register 0 Page 5-53
SCU_PTDAT1 SCU Pad Test Data Register 1 Page 5-54
SCU_PTDAT2 SCU Pad Test Data Register 2 Page 5-55
SCU_PTDAT3 SCU Pad Test Data Register 3 Page 5-56

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SCU_PTCON
SCU Pad Test Control Register (F00000B0H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTM
0 0 0 0
EN
rh r rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN EN EN EN
RD RD RD RD
OUT OUT OUT OUT PTMLC
SS3 SS2 SS1 SS0
3 2 1 0
rw rw rw rw rw rw rw rw w

Field Bits Type Description

PTMLC [7:0] w Pad Test Mode Lock Code
This bit field must be written with a special two-word
write sequence to enable the pad test mode.
PTMLC is always read as 00H.
ENOUTn n+8 rw Enable Data Output for Pad Test Data Register n
(n = 0-3) In pad test mode (PTMEN = 1), these bits determine
whether or not the logic level state as defined by the
bits in the SCU_PTDATn register is switched as
inverted state to the pad/pin.
0B Pad drivers of the pad test data register n
related pads are disabled.
1B Pad drivers of the pad test data register n
related pads are enabled and the bits in the pad
test data register n are output as inverted state
at the related pins.
RDSSn n + 12 rw Read Source Selection for Pad Test Data
(n = 0-3) Register n
In pad test mode (PTMEN = 1), these bits determine
the read source for the SCU_PTDATn register.
0B Logic levels of the pad test data register n
related pads/pins are read.
1B Pad test data register n bits are read.
0 16 rw Reserved
Read as 0 after reset; returns the value that is written.

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Field Bits Type Description

0 17, 18 rw Reserved
Read as 0; bits must be written with 0.
PTMEN 31 rh Pad Test Mode Enable Flag
0B Pad test mode disabled (default after reset)
1B Pad test mode enabled
0 [30:19] r Reserved
Read as 0; should be written with 0.

SCU_PTDAT0
SCU Pad Test Data Register 0 (F00000B4H) Reset Value: XXXX XXXXH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR RD
ADV RD BC3 BC2 BC1 BC0 A23 A22 A21 A20 A19 A18 A17 A16
W WR
rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh

Field Bits Type Description

An n rwh Pad Test Value for/of EBU Address Bus Line An
(n = 0-23)
BC0 24 rwh Pad Test Value for/of BC0
BC1 25 rwh Pad Test Value for/of BC1
BC2 26 rwh Pad Test Value for/of BC2
BC3 27 rwh Pad Test Value for/of BC3
RD 28 rwh Pad Test Value for/of RD
RDWR 29 rwh Pad Test Value for/of RD/WR
ADV 30 rwh Pad Test Value for/of ADV
MRW 31 rwh Pad Test Value for/of MR/W

Note: In pad test mode, the bits in SCU_PTDAT0 are output to the pad/pin in inverted
state: a 0 generates a high level and a 1 generates a low level at the pad/pin.

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SCU_PTDAT1
SCU Pad Test Data Register 1 (F00000B8H) Reset Value: XXXX XXXXH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS
WAI B HL HO HD TR BRK BRK
0 BAA COM CS3 CS2 CS1 CS0 NMI
T REQ DA LD RST CLK OUT IN
B
r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rh rwh rwh rwh rwh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh

Field Bits Type Description

TRn n rwh Pad Test Value for/of TRn
(n = 0-15)
BRKIN 16 rwh Pad Test Value for/of BRKIN
BRKOUT 17 rwh Pad Test Value for/of BRKOUT
TRCLK 18 rwh Pad Test Value for/of TRCLK
HDRST 19 rwh Pad Test Value for/of HDRST
NMI 20 rh Pad Test Value of NMI
HOLD 21 rwh Pad Test Value for/of HOLD
HLDA 22 rwh Pad Test Value for/of HLDA
BREQ 23 rwh Pad Test Value for/of BREQ
CS0 24 rwh Pad Test Value for/of CS0
CS1 25 rwh Pad Test Value for/of CS1
CS2 26 rwh Pad Test Value for/of CS2
CS3 27 rwh Pad Test Value for/of CS3
CSCOMB 28 rwh Pad Test Value for/of CSCOMB
WAIT 29 rwh Pad Test Value for/of WAIT
BAA 30 rwh Pad Test Value for/of BAA
0 31 r Reserved
Reading this bit always returns 0.

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Note: In pad test mode, the bits in SCU_PTDAT1 are output to the pad/pin in inverted
state: a 0 generates a high level and a 1 generates a low level at the pad/pin.

SCU_PTDAT2
SCU Pad Test Data Register 2 (F00000BCH) Reset Value: XXXX 0XXXH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLS SCL MR MT SLS SLS
0
I0 K0 ST0 SR0 O1 O0
rwh rwh rwh rwh rwh rwh rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TES BF BF
TST T BYP
0 TMO TMS TDO TDI TCK CLK CLK
RES RST ASS
DE O I
r rh rh rwh rwh rwh rwh rwh rwh rwh rwh

Field Bits Type Description

BYPASS 0 rwh Pad Test Value for/of BYPASS
BFCLKI 1 rwh Pad Test Value for/of BFCLKI
BFCLKO 2 rwh Pad Test Value for/of BFCLKO
TRST 3 rwh Pad Test Value for/of TRST
TCK 4 rwh Pad Test Value for/of TCK
TDI 5 rwh Pad Test Value for/of TDI
TDO 6 rwh Pad Test Value for/of TDO
TMS 7 rwh Pad Test Value for/of TMS
TESTMODE 8 rh Pad Test Value of TESTMODE
TSTRES 9 rh Pad Test Value of TSTRES
0 [15:10] r Reserved
Reading this bit always returns 0.
0 [25:16] rw Reserved
Read as 0 after reset; returns the value that is written.
SLSO0 26 rwh Pad Test Value for/of SLSO0
SLSO1 27 rwh Pad Test Value for/of SLSO1
MTSR0 28 rwh Pad Test Value for/of MTSR0
MRST0 29 rwh Pad Test Value for/of MRST0

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Field Bits Type Description

SCLK0 30 rwh Pad Test Value for/of SCLK0
SLSI0 31 rwh Pad Test Value for/of SLSI0

Note: In pad test mode, the bits in SCU_PTDAT2 are output to the pad/pin in inverted
state: a 0 generates a high level and a 1 generates a low level at the pad/pin.

SCU_PTDAT3
SCU Pad Test Data Register 3 (F00000C0H) Reset Value: XXXX XXXXH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh

Field Bits Type Description

Dn n rwh Pad Test Value for/of EBU Data Bus Line Dn
(n = 0-31)

Note: In pad test mode, the bits in SCU_PDAT3 are output to the pad/pin in inverted
state: a 0 generates a high level and a 1 generates a low level at the pad/pin.

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5.10 Emergency Stop Output Control for GPTA and MSC

The emergency stop feature of the TC1796 allows for a fast emergency reaction on an
external event for the GPTA and MSC modules without the intervention of software. In
an emergency case, the GPTA outputs of the TC1796 can be selectively put immediately
to a well-defined logic level. The two MSC modules, MSC0 and MSC1, are also able to
handle an emergency case by selectively putting bits of the next following serial
downstream frame(s) to a programmable logic value instead of an actual data value.
The emergency case is indicated to the TC1796 by an emergency input signal with
selectable polarity that has to be connected to input HWCFG1 (P10.1).
Figure 5-13 shows a diagram of the emergency stop input logic. This logic is controlled
by the SCU Emergency Stop Register SCU_EMSR.

System Control Unit GPIO Ports

with GPTA
Synchronous Control Functionality

POL ENON EMSFM MODE Port2

Reset Set
& Set
EMSF Port3

Port4
0
P10.1 /
0
HWCFG1 1
1
1
Port8
Asynchronous Control

Port9
EMGSTOP
Signal

MSC1 MSC0

MCA05624

Figure 5-13 Emergency Stop Input Control

The emergency stop control logic can basically operate in two modes:
• Synchronous mode (default after reset):
Emergency case is activated by hardware and released by software.
• Asynchronous mode:
Emergency case is activated and released by hardware.

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In synchronous mode (selected by MODE = 0), the HWCFG1 signal is sampled for a
inactive-to-active level transition, and an emergency stop flag EMSF is set if the
transition is detected. The setting of EMSF activates the EMGSTOP signal. An
emergency case can only be terminated by clearing EMSF via software. The
synchronous control logic is clocked by the system clock fSYS. This results in a small
delay between the HWCFG1 signal and EMGSTOP signal generation. If the system
clock is switched off (not applicable in TC1796), the synchronous mode control logic is
frozen and not able to react to transitions at input HWCFG1. In this case, the
asynchronous mode can be used to put GPTA outputs to dedicated logic levels.
In asynchronous mode (selected by MODE = 1), the occurrence of an active level at
input HWCFG1 immediately activates the EMGSTOP signal to the GPTA outputs and
the MSC modules even if the synchronous control part is inactive and not clocked by the
system clock fSYS. Of course, a valid-to-invalid transition of HWCFG1 (emergency case
is released) also immediately deactivates the EMGSTOP signal.
The POL bit determines the active level of the emergency stop input signal HWCFG1.
The MODE bit selects synchronous or asynchronous mode for emergency stop signal
generation. The EMSF flag can be enabled/disabled for setting (control bit ENON) and
it can be set or cleared by software, too (bit field EMSFM).

5.10.1 GPTA Output Emergency Control in the GPIO Ports

The selection of which port line of a GPIO port is affected by an active EMGSTOP signal
is done in the Emergency Stop Registers (Pn_ESR), which are located in the port logics.
Each of the GPIO lines that can be assigned as GPTA output has its own emergency
stop enable bit Pn_ESR.ENx. If the emergency stop signal EMGSTOP becomes active,
one of two states can be selected:
• Emergency stop function disabled (Pn_ESR.ENx = 0):
A GPTA output line remains connected to the GPTA module (alternate function).
• Emergency stop function enabled (Pn_ESR.ENx = 1):
A GPTA output line is disconnected immediately from the GPTA module (alternate
function) and connected to the corresponding bit of the Pn_OUT output register
Pn_OUT.Px.

5.10.2 MSC Emergency Control Selection

With an active emergency stop signal (EMGSTOP = 1), the two MSC modules are
selectively put bits of the next following serial downstream frame(s) to a programmable
logic value instead of an actual data value. In an emergency case, the bits in the
downstream shift registers SRL/SRH that are enabled for the emergency stop feature
(corresponding bits in the emergency stop register ESR set) are loaded with the
corresponding bit of the downstream data register DD instead with the bits from the
ALTINL/ALTINH data source. Therefore, it takes a calculable time until the transmitted
downstream frame with the emergency stop information reaches the receiver device.

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5.10.3 Emergency Stop Register

The Emergency Stop Register SCU_EMSR contains control and status bits/flags of the
emergency stop input logic.

SCU_EMSR
SCU Emergency Stop Register (F0000044H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EMS
0 EMSFM 0
F
r w r rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN MO
0 POL
ON DE
r rw rw rw

Field Bits Type Description

POL 0 rw Input Polarity
This bit determines the polarity of the emergency
input line HWCFG1.
0B HWCFG1 is high active.
1B HWCFG1 is low active.
MODE 1 rw Mode Selection
This bit determines the operating mode of the
EMGSTOP signal.
0B Synchronous mode selected; EMGSTOP is
derived from the state of flag EMSF.
1B Asynchronous mode selected; EMGSTOP is
directly derived from the state of the input signal
HWCFG1.
ENON 2 rw Enable ON
This bit enables the (hardware) setting of flag EMSF
by an inactive-to-active level transition of input signal
HWCFG1.
0B Setting of EMSF by hardware is disabled.
1B Setting of EMSF by hardware is enabled.

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Field Bits Type Description

EMSF 16 rh Emergency Stop Flag
This bit indicates if an emergency stop condition has
occurred.
0B An emergency stop has not occurred.
1B An emergency stop has occurred and signal
EMGSTOP becomes active (if MODE = 0).
EMSFM [25:24] w Emergency Stop Flag Modification
This bit field makes it possible to set or clear flag
EMSF by software. In case of a simultaneous
hardware and software modification request, the
hardware operation will be executed.
00B EMSF remains unchanged.
01B EMSF is set.
10B EMSF is cleared.
11B EMSF remains unchanged.
EMSFM is always read as 00B.
0 [15:3], r Reserved
[23:17], Read as 0; should be written with 0.
[31:26]

5.11 Analog Input 7 Testmode

When setting bit SCU_CON.AN7TM, the analog input AN7 is pulled low via a resistor of
max. 900 Ω. This feature makes it possible to check the correct operation of the ADC
during operation. The conversion result should be near the minimum (depending on the
source resistance of the connected sensor).

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5.12 SCU Registers and Address Map

This section refers to all registers which are located in the SCU address range. Some of
these registers are described in other chapters of this User’s Manual. The entries in
column entitled “Description see” of Table 5-9 point to the pages on which such registers
are described in detail.

Miscelleaneous Clock / PLL /Reset Identification Watchdog Timer

Registers Registers Registers Registers
SCU_CON OSC_CON SCU_ID WDT_CON0
SCU_STAT PLL_CLC MANID WDT_CON1
SCU_SCLIR SCU_SCLKFDR CHIPID WDT_SR
NMISR RST_SR RTID
External Trigger
SCU_PETCR RST_REQ Register
SCU_PETSR
EICR0
Pad Test Mode Power Management Port Control EICR1
Registers Register Registers EIFR
SCU_PTCON PMG_CSR SCU_TCCON FMR
SCU_PTDAT0 SCU_TCLR0 PDRR
SCU_PTDAT1 SCU_TCLR1 IGCR0
SCU_PTDAT2 SCU_EMSR IGCR1
SCU_PTDAT3 TGADC0
TGADC1
MCA05625_mod

Figure 5-14 SCU Registers

The complete and detailed address map of all SCU registers is described in Table 18-3
on Page 18-7 of the TC1796 User’s Manual System Units part (Volume 1).

Table 5-9 SCU Registers

Register Short Register Long Name Offset Description
Name Address see
SCU_ID SCU Module IDentification Register 08H Page 5-69
SCU_SCLKFDR SCU System Clock Fractional Divider 0CH Page 3-42
Register
RST_REQ Reset Request Register 10H Page 4-5
RST_SR Reset Status Register 14H Page 4-3

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Table 5-9 SCU Registers (cont’d)

Register Short Register Long Name Offset Description
Name Address see
OSC_CON Oscillator Control Register 18H Page 3-8
WDT_CON0 Watchdog Timer Control Register 0 20H Page 16-29
WDT_CON1 Watchdog Timer Control Register 1 24H Page 16-31
WDT_SR Watchdog Timer Status Register 28H Page 16-32
NMISR NMI Status Register 2CH Page 14-27
PMG_CSR Power Management Control and Status 34H Page 5-4
Register
SCU_SCLIR SCU Software Configuration Latched 38H Page 10-24
Inputs Register
PLL_CLC PLL Clock Control Register 40H Page 3-16
SCU_EMSR SCU Emergency Stop Register 44H Page 5-59
SCU_TCCON SCU Temperature Compensation Control 48H Page 5-44
Register
SCU_CON SCU Control Register 50H Page 5-64
SCU_STAT SCU Status Register 54H Page 5-67
SCU_TCLR0 SCU Temperature Compensation 0 Level 58H Page 5-46
Register
SCU_TCLR1 SCU Temperature Compensation 1 Level 5CH Page 5-47
Register
MANID Manufacturer Identification Register 70H Page 5-69
CHIPID Chip Identification Register 74H Page 5-70
RTID Redesign Tracing Identification Register 78H Page 5-71
EICR0 External Input Channel Register 0 80H Page 5-17
EICR1 External Input Channel Register 1 84H Page 5-20
EIFR External Input Flag Register 88H Page 5-23
FMR Flag Modification Register 8CH Page 5-24
PDRR Pattern Detection Result Register 90H Page 5-25
IGCR0 Interrupt Gating Register 0 94H Page 5-26
IGCR1 Interrupt Gating Register 1 98H Page 5-29
TGADC0 Trigger Gating ADC0 Register 9CH Page 5-32
TGADC1 Trigger Gating ADC1 Register A0H Page 5-32

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Table 5-9 SCU Registers (cont’d)

Register Short Register Long Name Offset Description
Name Address see
SCU_PTCON SCU Pad Test Control Register B0H Page 5-52
SCU_PTDAT0 SCU Pad Test Data Register 0 B4H Page 5-53
SCU_PTDAT1 SCU Pad Test Data Register 1 B8H Page 5-54
SCU_PTDAT2 SCU Pad Test Data Register 2 BCH Page 5-55
SCU_PTDAT3 SCU Pad Test Data Register 3 C0H Page 5-56
SCU_PETCR SCU Parity Error Trap Control Register D0H Page 5-39
SCU_PETSR SCU Parity Error Trap Status Register D4H Page 5-40

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5.13 Miscellaneous SCU Registers

This section includes descriptions of the following registers:
• SCU Control Register SCU_CON
• SCU Status Register SCU_STAT
• SCU Module Identification Register SCU_ID
• Manufacturer Identification Register MANID
• Chip Identification Register CHIPID
• Redesign Tracing Identification Register RTID

5.13.1 SCU Control Register

SCU_CON
SCU Control Register (F0000050H) Reset Value: FF00 0002H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSC
SLS
ONE ZERO GIN1S 0
PDR
PDR
rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPA LD DTS AN7 NMI EPU CS CS CS
0 0 FIEN
RAV EN ON TM EN D GEN OEN EEN
r rw rw rw r rw rws rw rw rw rw rw

Field Bits Type Description

FIEN 0 rw FPU Inexact Interrupt Enable
0B Inexact error condition (setting FX flag) after a
FPU calculation will not generate an interrupt.
1B Inexact error condition (setting FX flag) after a
FPU calculation will generate an interrupt.
CSEEN 1 rw CSEMU Enable
0B CSEMU will not activate CSCOMB
1B CSEMU will activate CSCOMB
(default after reset)
See also Figure 13-10 on Page 13-29.

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Field Bits Type Description

CSOEN 2 rw CSOVL Enable
0B CSOVL will not activate CSCOMB
(default after reset)
1B CSOVL will activate CSCOMB
See also Figure 13-10 on Page 13-29.
CSGEN 3 rw CSGLB Enable
0B CSGLB will not activate CSCOMB
(default after reset).
1B CSGLB will activate CSCOMB.
See also Figure 13-10 on Page 13-29.
EPUD 4 rw EBU Pull-up Disable
0B Pull-up resistors are enabled
(default after reset).
1B Pull-up resistors are disabled.
NMIEN 5 rws NMI Enable
0B NMI is disabled (default).
1B NMI is enabled.
This bit is cleared with any reset.
It can be only set by software and will remain in this
state until the next reset. Writing a zero to this bit has
no effect. The NMI is described in detail at
Section 14.10 on Page 14-25.
AN7TM 6 rw Analog Input 7 Test Mode
0B Pull down of analog input 7 is disabled (default
after reset).
1B Pull down of analog input 7 is enabled.
DTSON 9 rw Die Temperature Sensor On
0B Die temperature sensor is switched off.
1B Die temperature sensor is switched on.
LDEN 10 rw LVDS Driver Enable
0B The LVDS drivers are disabled and in power-
down mode.
1B The LVDS drivers are enabled.
See also Page 10-85.
RPARAV 11 rw Reset SRAM Parity Available Bit
0B No action
1B Clear bit SCU_STAT.PARAV
This bit is always read as 0.
See also “SRAM Parity Control” on Page 5-37.

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Field Bits Type Description

SLSPDR 16 rw SLSO0/SLSO1 Pad Driver Strength Selection
0B Strong driver, sharp edge selected.
1B Strong driver, soft edge selected.
See also Page 10-83.
SSC0PDR 17 rw SSC0 Pad Driver Strength Selection
0B Strong driver, sharp edge selected
1B Strong driver, soft edge selected
See also Page 10-83.
GIN1S [19:18] rw GPTA Input1 Source Select
00B IN1 of GPTA input array
01B RxD0A
10B RxD0B
11B RxD1B
Details of GIN1S control are described in
Section 5.8 on Page 5-49.
ZERO [23:20] rw Spare 0 Control Bits
This bit field contains bits that are reserved for future
SCU control tasks. Field ZERO is set to 00H after
reset. ZERO bits should be written with 00H. Reading
ZERO bits will return the value last written.
ONE [31:24] rw Spare 1 Control Bits
This bit field contains bits that are reserved for future
SCU control tasks. Field ONE is set to FFH after
reset. ONE bits should be written with FFH. Reading
ONE bits will return the value last written.
0 [8:7], r Reserved
[15:12] Read as 0; should be written with 0.

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5.13.2 SCU Status Register

The SCU Status Register SCU_STAT holds the status bits for the FPU interrupt (see
Section 5.4.1 on Page 5-35).
The Boot ROM code is always executed after every reset operation. Depending on the
program flow through the Boot ROM code and the Boot ROM exit path, several
resources of the TC1796 on-chip hardware have been used and are programmed. This
means that the state of on-chip hardware resources that have been used by the Boot
ROM code, may differ from the device reset state as described by the register reset
values. This section describes which initial state of the on-chip hardware resources is left
after a specific Boot ROM exit.

SCU_STAT
SCU Status Register (F0000054H) Reset Value: 0000 E000H1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
0 0 EEA 0 FII FVI FZI FUI FXI
AV
r rh r rh r rh rh rh rh rh
1) The initial value of SCU_STAT after Boot ROM exit is 0000 2000B.

Field Bits Type Description

FXI 0 rh FPU Inexact Result Indication Flag
Indicates the state of the FPU’s FX status flag
latched during the last FPU interrupt.
FUI 1 rh FPU Underflow Error Indication Flag
Indicates the state of the FPU’s FU status flag
latched during the last FPU interrupt.
FZI 2 rh FPU Divide by Zero Error Indication Flag
Indicates the state of the FPU’s FZ status flag
latched during the last FPU interrupt.
FVI 3 rh FPU Overflow Error Indication Flag
Indicates the state of the FPU’s FV status flag
latched during the last FPU interrupt.

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Field Bits Type Description

FII 4 rh FPU Invalid Operation Error Indication Flag
Indicates the state of the FPU’s FI status flag latched
during the last FPU interrupt.
EEA 8 rh Emulation Extension Available
Indicates if the emulation extension (= 1796ED) is
available or not (= production device)
0B EEC is not available.
1B EEC is available.
PARAV 13 rh Parity Available
0B SRAM parity logic is disabled.
1B SRAM parity logic is enabled.
This bit is set with any power-on reset. It can be
cleared by software by writing bit
SCU_CON.RPARAV. It cannot be set by software.
More details about PARAV are described below
Table 5-5 on Page 5-37.
0 [7:5], r Reserved
[12:9], Read as 0.
[31:14]

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5.13.3 Device Identification Registers

The SCU Module Identification Register ID contains read-only information about the
SCU module version.

SCU_ID
SCU Module Identification Register
(F0000008H) Reset Value: 002C C0XXH
31 16 15 8 7 0

MODNUM MODTYPE MODREV

r r r

Field Bits Type Description

MODREV [7:0] r Module Revision Number
MODREV defines the module revision number. The value
of a module revision starts with 01H (first revision).
MODTYPE [15:8] r Module Type
This bit field defines the module as a 32-bit module: C0H
MODNUM [31:16] r Module Number Value
This bit field defines the module identification number for
the SCU: 002CH

MANID
Manufacturer Identification Register
(F0000070H) Reset Value: 0000 1820H
31 16 15 5 4 0

0 MANUF DEPT

r r r

Field Bits Type Description

DEPT [4:0] r Department Identification Number
= 00H: indicates the Automotive & Industrial
microcontroller department within Infineon Technologies.

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Field Bits Type Description

MANUF [15:5] r Manufacturer Identification Number
This is a JEDEC normalized manufacturer code.
MANUF = C1H stands for Infineon Technologies.
0 [31:16] r Reserved
Read as 0.

CHIPID
Chip Identification Register
(F0000074H) Reset Value: 0000 8AXXH
31 16 15 8 7 0

0 CHID CHREV

r r r

Field Bits Type Description

CHREV [7:0] r Chip Revision Number
This bit field indicates the revision number of the TC1796
device (01H = first revision). CHREV can be used e.g. for
major step identification purposes. The value of this bit
field is defined in the TC1796 Data Sheet.
CHID [15:8] r Chip Identification Number
8AH = TC1796
0 [31:16] r Reserved
Read as 0.

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The Redesign Tracing Register RTID provides a means of signalling minor redesigns
that are not reflected in the CHIPID.CHREV bit field.

RTID
Redesign Tracing Identification Register
(F0000078H) Reset Value: 0000 XXXXH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r r r r r r r r r r r r r r r r

Field Bits Type Description

RTn n r Redesign Trace Bit n
(n = 0-15) 0B No change indicated
1B A change has been made (without changing
bit field CHIPID.CHREV).
RTn can be used, e.g., for minor redesign stepping
identification purposes.
0 [31:16] r Reserved
Read as 0.

Note: The RTID reset value for a major design step (without modifications) is 0000H.

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On-Chip System Buses and Bus Bridges

6 On-Chip System Buses and Bus Bridges

The TC1796 has four independent on-chip buses
• Program Local Memory Bus (PLMB)
• Data Local Memory Bus (DLMB)
• System Peripheral Bus (SPB)
• Remote Peripheral Bus (RPB)

Floating Point Unit

Program Memory FPU Data Memory
Interface Interface
TriCore
PMI DMI
CPU
48 KB SPRAM 56 KB LDRAM
16 KB ICACHE CPU Slave Interface 8 KB DPRAM
CPS

Remote Peripheral Bus

Program Local Data Local
Memory Bus Memory Bus
PBCU DBCU
PLMB DLMB

RPB
Program Memory Data Memory
Unit Unit
LMI

EBU PMU DMU

16 KB BROM Local Memory -to- 16 KB SBRAM

2 MB PFLASH FPI Bus Interface 64 KB SRAM
128 KB DFLASH
LFI-Bridge
Emulation Memory
Interface System
Peripheral Bus

To Emulation Memory SPB

(Emulation device only )
LDRAM = Local Data RAM EBU = External Bus Unit
DPRAM = Dual-Port RAM LMI = Local Memory Interface
SPRAM = Scratch-Pad RAM PBCU = Program Local Memory
ICACHE = Instruction Cache Bus Control Unit
SBRAM = Stand-by RAM DBCU = Data Local Memory
SRAM = Data RAM Bus Control Unit
PFLASH = Program Memory Flash
DFLASH = Data Memory Flash
BROM = Boot ROM & Test ROM
MCB05626_mod

Figure 6-1 Buses in TC1796 Processor Subsystem

The two LMBs (PLMB and DLMB) connect the TriCore CPU to its local resources for
instruction fetches and data accesses.

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The SPB is accessible by the CPU via the LFI Bridge.

The RPB connects the peripherals with high data rates (SSC, ADC, FADC) to the Dual-
port memory (DPRAM) in the DMI, relieving the SPB and the two LMBs from these data
transfers. The RPB is controlled by a bus switch which is located in the DMA controller.
The two LMBs (PLMB and DLMB) run at CPU clock speed fCPU, whereas SPB and RPB
run at system clock speed fSYS. Note that fSYS can be equal to fCPU or half the fCPU
frequency, but fSYS is limited to max. 75 MHz.

6.1 Program and Data Local Memory Buses

The PLMB and DLMB are identical LMBs especially designed for the 32-bit TriCore
system technology. Both buses operate in the same manner. The following terminology
is used for these buses:

Table 6-1 LMB Terms

Term Description
Agent An LMB agent is any master or slave device which is connected to
the LMB.
Master An LMB master device is an LMB agent which is able to initiate
transactions on the LMB. It is also able to react as a LMB slave.
Slave An LMB slave device is an LMB agent which is not able to initiate
transactions on the LMB. It is only able to handle operations that
are dedicated to it by a LMB master device.

6.1.1 Overview
The LMB is a synchronous and pipelined bus with variable block size transfer support.
The protocol supports 8-, 16-, 32-, and 64-bit single transactions and 2/4 wide 64-bit
block transfers.
The LMB has the following features:
• Optimized for high speed and high performance data transfers
• 32-bit address bus, 64-bit data bus
• Simple central arbitration per cycle
• Slave-controlled wait state insertion
• Address pipelining (max depth - 2)
• Support of atomic operations LDMST, ST.T and SWAP.W
• Block transfers with variable block length (two or four 64-bit data transactions)

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6.1.2 Transaction Types

6.1.2.1 Single Transfers

Single transfers are all transactions that are initiated by any instruction (code or data) of
the TriCore 1 CPU and that require a system resource which not part of the TriCore 1
PMI or DMI. The only exceptions are the following instructions:
• LDMST, ST.T and SWAP.W generate atomic transfers
• Cache miss instructions generate block transfers

6.1.2.2 Block Transfers

Block transfers are only issued in two ways:
1. By the PMI in case of a cache miss.
2. By the PCP if it uses a BCOPY instruction.
Block transfers work in the same way as single transfers, except that only one address
phase with two or four data phases is generated.

6.1.2.3 Atomic Transfers

Atomic transfers are initiated by instructions that require two single transfers (e.g. read-
modify-write instructions such as LDMST, ST.T and SWAP.W). During an atomic
transfer, any other LMB master is blocked for gaining bus ownership.

6.1.3 Address Alignment Rules

Depending on the data size, there are rules that determine the address alignment of an
LMB transfer.
1. Byte accesses must be always located on byte address boundaries.
2. Half-word accesses must be aligned to addresses with address line A0 = 0.
3. Word accesses must be aligned to addresses with address lines A[1:0] = 00B.
4. Double-word accesses must be aligned to addresses with address lines
A[2:0] = 000B.
5. Block transfers must be aligned identical as double-word addresses.

6.1.4 Reaction of a Busy Slave

If an LMB slave is busy at an incoming LMB transaction request, it can delay the
execution of the LMB transaction. The requesting LMB master releases the LMB for one
cycle after the LMB transaction request in order to allow the LMB slave to indicate if it is
ready to handle the requested LMB transaction.

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Note: For the LMB default master, the one cycle gap does not result in a performance
loss because it is granted the LMB in this cycle as default master if no other master
requests the LMB for some other reasons.

6.1.5 LMB Basic Operation

Figure 6-2 describes some basic bus operations of the LMB.

Bus Cycle 1 2 3 4 5

Request / Address Data

Transfer 1
Grant Cycle Cycle
Request / Address Data
Transfer 2
Grant Cycle Cycle
Transfer 3 Request /Grant Address Data
Cycle Cycle
MCA05628_mod

Figure 6-2 Basic LMB Transactions

Transfer 1 displays the three cycles of any LMBs transaction:
1. Request/Grant Cycle: The LMB master attempts to perform a read or write transfer
and requests for the LMB. If the LMB is available, it is granted in the same cycle by
the LMB bus controller.
2. Address Cycle: After the request/grant cycle, the master puts the address on the
LMB and all LMB slave devices check whether they are addressed for the following
data cycle.
3. Data Cycle: In the data cycle, either the LMB master puts write data on the LMB
which is read by the LMB slave (write cycle), or vice versa (read cycle).
Transfers 2 and 3 show the conflict when two masters try to use the LMB, and how the
conflict is resolved. In the example, the LMB master of transfer 2 has a higher priority
than the LMB master of transfer 3.
During a block transfer, the address cycle of a second transfer is extended until the data
cycles of the block transfer are finished. In the example shown in Figure 6-3, transfer 1
is a block transfer while transfer 2 is a single transfer.

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Bus Cycle 1 2 3 4 5 6 7

Request/ Address Data Data Data Data

Transfer 1
Grant Cycle Cycle Cycle Cycle Cycle
Request/ Data
Transfer 2 Address Cycle
Grant Cycle
MCA05629

Figure 6-3 LMB Block Transactions

6.2 Local Memory Bus Controller Units

Each of the two LMBs in the TC1796 have a LMB Bus Control Unit (LBCU), one for the
DLMB (DBCU) and one for the PLMB (PBCU). Where the description in this section
refers to LBCU, the related topic is also valid for DBCU and PBCU.

6.2.1 Basic Operation

The LBCU handles the cycle sequences of the transfers that have been requested by
the LMB master devices. The LBCU is also able to detect bus protocol violations and
addressing of un-implemented addresses. In case of a bus error, the LBCU captures all
relevant data such as bus address, bus data and bus status information in register where
the information can be analyzed by software.

6.2.2 LMB Bus Arbitration

All LMB master devices requesting the LMB will participate in an arbitration round.
Arbitration rounds are performed in each cycle that preceeds a possible address cycle.
Each LMB master device has a fixed priority as shown in Table 6-2.

Table 6-2 Priority of Master PLMB Agents

LMB Bus Priority LMB Bus Master
PLMB Low priority DMU
High priority PMI (Default Master)
DLMB Low priority LFI
High priority DMI (Default Master)

For all the masters requesting an LMB (PLMB or DLMB) during any one cycle, the
master that is granted the LMB is the one with the highest priority.

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6.2.2.1 LMB Bus Default Master

When no LMB master is requesting the LMB, it is granted to the LMB default master. This
means if the default master needs the LMB in the next cycle, it can enter the address
cycle without running through a request/grant cycle.

6.2.3 LMB Bus Error Handling

When an error occurs on LMB, the LMB bus control unit captures and stores data about
the erroneous condition and generates a service request if enabled to do so. The
conditions that force an error-capture event are:
• Un-implemented address: No LMB slave responds to an address target
• Error acknowledge: An LMB slave responds with an error to a transaction
When a transaction causes an error, the address and data phase signals of the
transaction causing the error are captured and stored in the following registers:
• The LMB Error Address Register (LEADDR) stores the LMB address that has been
captured during the last erroneous LMB transaction.
• The LMB Error Data Low/High Registers (LEDATL/LEDTAH) store the 64-bit LMB
data bus information that has been captured during the last erroneous LMB
transaction.
• The LMB Error Attribute Register (LEATT) stores status information about the bus
error event.
If more than one LMB transaction generates a bus error, only the first bus error is
captured. After a bus error has been captured, the capture mechanism must be released
again by software.
If a transaction from the PCP, the DMA or the Cerberus causes a bus error on the DLMB,
the originating masters are not informed about this bus error because they are not a
DLMB master agent. With each bus error-capture event, a service request is generated
and an interrupt can be generated if enabled and configured in the corresponding service
request register.

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6.2.4 DLMB and PLMB Bus Registers

This section describes the registers of the DBCU/PBCU modules. The complete and
detailed address maps of DBCU/PBCU are described in Table 18-38/Table 18-41 on
Page 18-122/Page 18-125 of this TC1796 System Units (Vol. 1 of 2) User’s Manual.

LMB Bus Register Overview

Module Identification General Registers Address/Data Interrupt Registers

Register Register

xBCU_ID xBCU_LEATT xBCU_LEADDR xBCU_SRC

xBCU_LEDATL
x = “D“ for DBCU
x = “P“ for PBCU xBCU_LEDATH
MCA05630_mod

Figure 6-4 DLMB/PLMB Bus Control Unit Registers

Table 6-3 Registers Address Space

Module Base Address End Address Note
DBCU F87F FA00H F87F FAFFH –
PBCU F87F FE00H F87F FEFFH –

Table 6-4 Registers Overview - LMB Bus Control Unit Registers

Register Register Long Name Offset Description
Short Name1) Address see
xBCU_ID xBCU Module Identification Register 08H Page 6-8
xBCU_LEATT xBCU LMB Error Attribute Register 20H Page 6-9
xBCU_LEADDR xBCU LMB Error Address Register 24H Page 6-12
xBCU_LEDATL xBCU LMB Error Data Low Register 28H Page 6-12
xBCU_LEDATH xBCU LMB Error Data High Register 2CH Page 6-13
xBCU_SRC xBCU Service Request Control Register FCH Page 6-13
1) Prefix x = “D” stands for “DBCU” and x = “P” for “PBCU”.

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DBCU_ID
DBCU Module Identification Register (08H) Reset Value: 000F C0XXH
PBCU_ID
PBCU Module Identification Register (08H) Reset Value: 000F C0XXH
31 16 15 8 7 0

MODNUM MODTYPE MODREV

r r r

Field Bits Type Description

MODREV [7:0] r Module Revision Number
MODREV defines the module revision number. The value
of a module revision starts with 01H (first revision).
MODTYPE [15:8] r Module Type
This bit field defines the module as a 32-bit module: C0H
MODNUM [31:16] r Module Number Value
This bit field defines the module identification number for
the DBCU/PBCU: 000FH

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DBCU_LEATT
DBCU LMB Error Attribute Register (20H) Reset Value: XXXX XXX0H
PBCU_LEATT
PBCU LMB Error Attribute Register (20H) Reset Value: XXXX XXX0H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OPC 0 TAG RD WR SVM 0 UIS ACK

rh r rh rh rh rh r rh rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LOC 0 FPITAG 0 LEC

rh r rh r rwh

Field Bits Type Description

LEC 0 rwh Lock Error Capture
This bit indicates and controls whether the error-
capture mechanism is unlocked or locked.
0B The error-capture mechanism is unlocked.
The next LMB bus error will be captured.
1B The error-capture mechanism is locked. The
registers LEADDR, LEDATL, LEDATH, and
bits [31:4] of LEATT contain valid data.
LEC is automatically set when an LMB bus error has
been captured. Any further LMB bus error is not
captured if LEC = 1. When writing a 1 to LEC, the
error-capture mechanism becomes unlocked and is
ready for the next LMB bus error-capture event.
FPITAG [7:4] rh FPI Bus Master TAG
This bit field indicates the FPI Bus master tag in case
of an LMB bus error.
Note that the FPI Bus master tag is only of interest if
the erroneous LMB transfer was initiated either by
the PCP, DMA, or by Cerberus.
LOC 15 rh LMB Bus Lock State
This bit indicates the bus lock state in case of an
LMB bus error.
0B LMB bus error occurred at an atomic transfer.
1B LMB bus error occurred at a single or block
transfer.

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Field Bits Type Description

ACK [18:16] rh LMB Bus Slave Response State
This bit indicates status information of the LMB slave
device in case of an LMB bus error.
000B Slave is in normal operation.
010B Slave is busy.
011B Slave has an error encountered.
other Reserved
UIS 19 rh Un-implemented Address
This bit indicates whether the LMB bus error
occurred by an un-implemented address.
0B LMB slave address is valid.
1B Invalid LMB slave address occurred.
SVM 21 rh LMB Bus Supervisor Mode
This bit indicates whether the LMB bus error
occurred in supervisor mode or in user mode.
0B Transfer was initiated in supervisor mode.
1B Transfer was initiated in user modes.
WR 22 rh LMB Bus Write Error Indication
This bit indicates whether the LMB bus error
occurred at a write cycle (see Table 6-5).
RD 23 rh LMB Bus Read Error Indication
This bit indicates whether the LMB bus error
occurred at a read cycle (see Table 6-5).
TAG [26:24] rh LMB Master TAG
This bit field indicates the LMB master device in case
of a LMB bus error.
DBCU_LEATT register (DLMB):
000B LFI
001B DMI
other Reserved
PBCU_LEATT register (PLMB):
000B LMI
001B PMI
other Reserved

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Field Bits Type Description

OPC [31:28] rh LMB Bus Error Transaction Type
This bit field indicates the type of transfer at which
the LMB bus error occurred.
0000B 8-bit data single transfer
0001B 16-bit data single transfer
0010B 32-bit data single transfer
0011B 64-bit data single transfer
1000B 2 × 64-bit data block transfer
1001B 4 × 64-bit data block transfer
other Reserved
0 [3:1], r Reserved
[14:8], Read as 0; should be written with 0.
20, 27

LEATT[31:4] contains valid read data only if its bit LEC bit is set.

Table 6-5 LMB Read/Write Error Indication

RD WR LMB Bus Cycle
0 0 LMB bus error occurred at the read cycle of an atomic transfer.
0 1 LMB bus error occurred at a read cycle of a single transfer.
1 0 LMB bus error occurred at a write cycle of a single transfer or at the
write cycle of an atomic transfer.
1 1 Does not occur

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DBCU_LEADDR
DBCU LMB Error Address Register (24H) Reset Value: XXXX XXXXH
PBCU_LEADDR
PBCU LMB Error Address Register (24H) Reset Value: XXXX XXXXH
31 0

LEADDR

rh

Field Bits Type Description

LEADDR [31:0] rh LMB Address
This bit field holds the LMB address that has been
captured at an LMB bus error.
LEADDR only contains valid read data when bit LEC
in the corresponding register LEATT is set.

DBCU_LEDATL
DBCU LMB Error Data Low Register (28H) Reset Value: XXXX XXXXH
PBCU_LEDATL
PLMB LMB Error Data Low Register (28H) Reset Value: XXXX XXXXH
31 0

LEDAT[31:0]

rh

Field Bits Type Description

LEDAT[31:0] [31:0] rh LMB Bus Address Bits [31:0]
This bit field holds the lower 32-bit part of the 64-bit
LMB data that has been captured at an LMB bus
error.
LEDAT[31:0] only contains valid read data when bit
LEC in the corresponding register LEATT is set.

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DBCU_LEDATH
DBCU LMB Error Data High Register (2CH) Reset Value: XXXX XXXXH
PBCU_LEDATH
PBCU LMB Error Data High Register (2CH) Reset Value: XXXX XXXXH
31 0

LEDAT[63:32]

rh

Field Bits Type Description

LEDAT[63:32] [31:0] rh LMB Bus Address Bits [31:0]
This bit field holds the upper 32-bit part of the 64-bit
LMB data that has been captured at an LMB bus
error.
LEDAT[63:32] only contains valid read data when bit
LEC in the corresponding register LEATT is set.

DBCU_SRC
DLMB Service Request Control Register(FCH) Reset Value: 0000 0000H
PBCU_SRC
PBCU Service Request Control Register(FCH) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET CLR
SRR SRE TOS 0 SRPN
R R
w w rh rw r r rw

Field Bits Type Description

SRPN [7:0] rw Service Request Priority Number
TOS [11:10] r Type-of-Service State
Always read as 00B. This means type-of-service is
associated with interrupt bus 0 (CPU interrupt
arbitration bus).

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Field Bits Type Description

SRE 12 rw Service Request Enable
SRR 13 rh Service Request Flag
CLRR 14 w Request Flag Clear Bit
SETR 15 w Request Flag Set Bit
0 [9:8], r Reserved
[31:16] Read as 0; should be written with 0.

Note: Further details on interrupt handling and processing are described in Chapter 14
of this TC1796 System Units (Vol. 1 of 2) User’s Manual.

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6.3 Local Memory to FPI Bus Interface (LFI Bridge)

6.3.1 Functional Overview

The LFI Bridge is a bi-directional bus bridge between the DLMB and the System
Peripheral FPI Bus (SPB). The bridge supports all transactions types of both the
LMB Bus and FPI Bus.
The bridge is not direction-transparent; this means that the master TAG of a bus master
is not forwarded to the other side of the bridge and is replaced instead by the master TAG
of the LFI Bridge itself.
In order to avoid deadlocks, priority is given to transactions initiated either by PCP, DMA,
or by Cerberus.
The bridge supports the pipelining of both connected buses. Therefore, no additional
delay is created except for bus protocol conversions.

Address Translation
Addresses of SPB transfers (initiated either by the PCP, DMA controller, or Cerberus)
via the LFI Bridge that address a DLMB or PLMB slave device are translated into a
DLMB address according Table 6-6.

Table 6-6 SPB to DLMB Address Translation

Transaction SPB Access Range Translated DLMB Address
Destination
SBRAM/SRAM E800 0000H - E800 FFFFH C000 0000H - C000 FFFFH
Reserved E801 0000H - E83F FFFFH C001 0000H - C03F FFFFH
DMI LDRAM and E840 0000H - E840 FFFFH D000 0000H - D000 FFFFH
DPRAM
Reserved E841 0000H - E84F FFFFH D0010000H - D00F FFFFH
PMI SPRAM E850 0000H - E850 BFFFH D400 0000H - D400 BFFFH
Reserved E850 C000H - E85F FFFFH D400 C000H - D40F FFFFH

Bus Errors at Writes via the LFI Bridge

When a write operation has been initiated and directed to the LFI Bridge by a SPB bus
master, the LFI Bridge handles the write transaction at the LMBs (DLMB and PLMB)
autonomously. If the write operation at the LMB results in a bus error, the BCU of the
corresponding LMB detects the bus error and generates a LMB bus error interrupt. There
is no bus error generated at the SPB side in this case because of the nature of a posted
write operation.

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The equivalent behavior occurs when an LMB master initiates a write to a SPB slave
device. In this case, SPB bus errors are detected by the SBCU but not at the LMB side.
Note that this behavior occurs only at write operations via the LFI Bridge. It also can be
triggered by an erroneous write cycle of a read-modify-write bus transaction.

6.3.2 LFI Register

This section describes the kernel register of the LFI Bridge.

LFI Register

Module Identification Control Registers

Register
LFI_ID LFI_CON
MCA05631_mod

Figure 6-5 LFI Register

The complete and detailed address map of LFI is described in Table 18-42 on
Page 18-126 of this TC1796 System Units (Vol. 1 of 2) User’s Manual.

Table 6-7 Registers Address Space - LFI Bridge

Module Base Address End Address Note
LFI F87F FF00H F87F FFFFH –

Table 6-8 Registers Overview - LFI Register

Register Register Long Name Offset Description
Short Name Address see
LFI_ID LFI Module Identification Register 08H Page 6-17
LFI_CON LFI Configuration Register 10H Page 6-17

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LFI_ID
LFI Module Identification Register (08H) Reset Value: 000C C0XXH
31 16 15 8 7 0

MODNUM MODTYPE MODREV

r r r

Field Bits Type Description

MODREV [7:0] r Module Revision Number
MODREV defines the module revision number. The value
of a module revision starts with 01H (first revision).
MODTYPE [15:8] r Module Type
This bit field defines the module as a 32-bit module: C0H
MODNUM [31:16] r Module Number Value
This bit field defines the module identification number for
the LFI: 000CH

LFI_CON
LFI Configuration Register (10H) Reset Value: 0000 0B02H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 FTAG 0 LTAG 0 1 0

r rh r rh r r rw

Field Bits Type Description

0 0 rw Reserved
Returns 0 if read; must be written with 0.
1 1 r Reserved
Returns 1 if read; should be written with 1.

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Field Bits Type Description

LTAG [6:4] rh LMB Bus (DLMB) Tag ID
In the TC1796, the bit field LTAG = 000B.
FTAG [11:8] rh FPI Bus (SPB) Tag ID
In the TC1796, the bit field FTAG = 1011B, which
reflects the tag number of the LFI Bridge on the SPB.
0 [3:2], 7, r Reserved
[31:12] Returns 0 if read.

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6.4 System and Remote Peripheral Bus

The TC1796 has two on-chip FPI buses:
• System Peripheral Bus (SPB)
– System bus for on-chip peripherals (except for SSCs and ADCs)
• Remote Peripheral Bus (RPB)
– Mainly dedicated to DMA transactions of SSCs and ADCs with DMI memories
This section gives an overview of the two on-chip FPI buses. It describes its bus control
units, the bus characteristics, bus arbitration, scheduling, prioritizing, error conditions,
and debugging support. Both FPI buses have the same FPI-Bus functionality. If required,
implementation-specific differences are described.

6.4.1 Overview
The FPI buses interconnect the on-chip peripheral units with the TC1796 processor
subsystem. Figure 6-6 gives an overview of the FPI Buses and the modules connected
to them.
The FPI Bus is designed to be quick to acquire by on-chip functional units, and quick to
transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast
FPI Bus acquisition, which is required for time-critical applications.
The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate
of up to 160 Mbyte/s can be achieved with the 32-bit data bus at 40 MHz bus clock.
Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to
its peak bandwidth.
Additional features of the FPI Bus include:
• Optimized for high speed and high performance
• Support of multiple bus masters
• 32-bit wide address and data buses
• 8-, 16-, and 32-bit data transfers
• 64-, 128-, and 256-bit block transfers
• Central simple per-cycle arbitration
• Slave-controlled wait state insertion
• Support of atomic operations LDMST, ST.T and SWAP.W
• Designed to minimize EMI and power consumption
The functional units of the TC1796 are connected to the FPI bus via FPI bus interfaces.
An FPI Bus interface act as bus agent, requesting bus transactions on behalf of their
functional unit, or responding to bus transaction requests.
There are two types of bus agents:
• FPI Bus master agents can initiate FPI Bus transactions and can also act as slaves.
• Slave agents can only react and respond to FPI Bus transaction requests in order to
read or write internal registers of slave modules as for example memories.

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When an FPI Bus master attempts to initiate a transfer on the FPI Bus, it first signals a
request for bus ownership to the bus control unit. When bus ownership is granted by the
bus control unit, an FPI Bus read or write transaction is initiated. The unit targeted by the
transaction becomes the FPI Bus slave, and responds with the requested action.
Some functional units operate only as slaves, while others can operate as either masters
or slaves. In the TC1796, DMI and PMI (via the LFI Bridge), PCP, DMA, and Cerberus
operate as FPI Bus masters. On-chip peripheral units are typically FPI Bus slaves.
Figure 6-6 shows the two FPI Buses and the interface types of the various modules.
FPI Bus arbitration is performed by the Bus Control Unit (BCU) of the FPI Bus. In case
of bus errors, the BCU generates an interrupt request to the CPU and provides
debugging information about the actual bus error to the CPU.
In the TC1796, device external memory/peripheral accesses are handled via the EBU as
part of the PMU. Therefore, the FPI Buses are not required for such type of device
external transactions.

Data Local
Memory Bus TriCore CPU DMI

LFI Bridge CPS DPRAM

Slave Slave
M/S
Slave

Slave

Slave
GPTA0 SBCU RBCU

Master/Slave
M/S
Slave

Slave

Slave

GPTA1 SCU FPI Bus Interface SSC0

Remote Peripheral Bus

Slave
Slave
FPI Bus Interface
Slave

Slave
M/S

LTCA2 OCDS SSC1

DMA Controller
Slave

Slave

Slave

CAN STM ADC0

Move Move
Engine Engine
0 1
Slave

Slave

Slave

MSC0 Ports ADC1

System Peripheral Bus

Slave

Slave
M/S

M/S

MSC1 Bus Switch FADC

Slave

M/S

ASC0 PCP2
Slave

ASC1 MEM
MLI0 MLI1
CHK

MCB05632_mod

Figure 6-6 TC1796 FPI Buses Block Diagram

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The Bus Switch in the DMA controller operates as a bus bridge between the SPB and
RPB.

6.4.2 Bus Transaction Types

This section describes the SPB transaction types.

Single Transfers
Single transfers are byte, half-word, and word transactions that target any slave
connected either to SPB or RPB. Note that the LFI Bridge operates as an SPB master.

Block Transfers
Block transfers operate in principle in the same way as single transfers do, but one
address phase is followed by multiple data phases. Block transfers can be composed of
2 word, 4 word, or 8 word transfers.
Note: In general, block transfers (2 word, 4 word, or 8 word) cannot be executed in the
TC1796 with peripheral units that operate as FPI Bus slaves during an FPI Bus
transaction.
Block transfers are initiated by the following CPU instructions: LD.D, LD.DA, MOV.D,
ST.D and ST.DA. The BCOPY instruction of the PCP also initiates a block transfer
transaction on the FPI Bus.

Atomic Transfers
Atomic transfers are generated by LDMST, ST.T and SWAP.W instructions that require
two single transfers. The read and write transfer of an atomic transfer are always locked
and cannot be interrupted by another bus masters. Atomic transfers are also referenced
as read-modify-write transfers.
Note: See also Table 6-12 for available FPI Bus transfer types.

6.4.3 Reaction of a Busy Slave

If an FPI Bus slave is busy at an incoming FPI Bus transaction request, it can delay the
execution of the FPI Bus transaction. The requesting FPI Bus master releases the
FPI Bus for one cycle after the FPI Bus transaction request, in order to allow the FPI
slave to indicate if it is ready to handle the requested FPI Bus transaction. This sequence
is repeated as long as the slave indicates that it is busy.
Note: For the FPI Bus default master, the one cycle gap does not result in a performance
loss because it is granted the FPI Bus in this cycle as default master if no other
master requests the FPI Bus for some other reasons.

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6.4.4 Address Alignment Rules

FPI Bus address generation is compliant with the following rules:
• Half-word transactions must have a half-word aligned address (A0 = 0). Half-word
accesses on byte lanes 1 and 2 addresses are illegal.
• Word transactions must always have word-aligned addresses (A[1:0] = 00B).
• Block transactions must always have block-type aligned addresses.

6.4.5 FPI Bus Basic Operations

This section describes some basic transactions on the FPI Bus.
The example in Figure 6-7 shows the three cycles of an FPI Bus operation:
1. Request/Grant Cycle: The FPI Bus master attempts to perform a read or write
transfer and requests for the FPI Bus. If the FPI Bus is available, it is granted in the
same cycle by the FPI Bus controller.
2. Address Cycle: After the request/grant cycle, the master puts the address on the
FPI Bus, and all FPI Bus slave devices check whether they are addressed for the
following data cycle.
3. Data Cycle: In the data cycle, either the master puts write data on the FPI Bus which
is read by the FPI Bus slave (write cycle) or vice versa (read cycle).
Transfers 2 and 3 show the conflict when two masters try to use the FPI Bus and how
the conflict is solved. In the example, the FPI Bus master of transfer 2 has a higher
priority than the FPI Bus master of transfer 3.

Bus Cycle 1 2 3 4 5

Request / Address Data

Transfer 1
Grant Cycle Cycle
Request / Address Data
Transfer 2
Grant Cycle Cycle
Address Data
Transfer 3 Request /Grant
Cycle Cycle
MCA05634_mod

Figure 6-7 Basic FPI Bus Transactions

At a block transfer, the address cycle of a second transfer is extended until the data
cycles of the block transfer are finished. In the example of Figure 6-8, transfer 1 is a
block transfer, while transfer 2 is a single transfer.

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Bus Cycle 1 2 3 4 5 6 7

Request/ Address Data Data Data Data

Transfer 1
Grant Cycle Cycle Cycle Cycle Cycle
Request/ Data
Transfer 2 Address Cycle
Grant Cycle
MCA05635

Figure 6-8 FPI Bus Block Transactions

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6.5 FPI Bus Control Units (SBCU and RBCU)

The TC1796 incorporates two BCUs: one for the SPB, called SBCU, and the other for
the RPB, called RBCU. The register name module prefix “x” of xBCU refers to the SBCU
with x = S and to the RBCU with x = R.

6.5.1 FPI Bus Arbitration

The arbitration unit of the BCU determines whether it is necessary to arbitrate for
FPI Bus ownership, and, if so, which available bus requestor gets the FPI Bus for the
next data transfer. During arbitration, the bus is granted to the requesting agent with the
highest priority. If no request is pending, the bus is granted to a default master. If no bus
master takes the bus, the BCU itself will drive the FPI Bus to prevent it from floating
electrically.

6.5.1.1 Arbitration on the System Peripheral Bus

The TC1796 SPB has five bus agents that can become a SPB bus master. Each agent
is supplied a arbitration priority as shown in Table 6-9. DMA controller and OCDS agents
can be assigned to low or high priorities by software.

Table 6-9 Priority of TC1796 SPB Bus Agents

Priority Agent Comment
highest Any bus requestor meeting the starvation Highest priority, used only for
protection criteria is assigned this priority starvation protection
On-Chip Debug System (Cerberus), Priority selection by software
high priority
Peripheral Control Processor Default master 0
DMA Controller, high priority channels Priority selection by software
LFI Bridge Default master 1
DMA Controller, low priority channels Priority selection by software
lowest On-Chip Debug System (Cerberus), Priority selection by Software
low priority

If there is no request from a SPB bus master, the SPB is granted to a default master
(PCP or LFI Bridge) which has been at last the default master.

6.5.1.2 Arbitration on the Remote Peripheral Bus

The TC1796 RPB has only one bus master agent, the DMA Controller. Therefore, the
RPB does not need the RBCU to arbitrate the bus, and the DMA controller is always its
default master.

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6.5.1.3 Starvation Prevention

Starvation prevention is a feature that is especially important for the SPB. Because the
priority assignment of the SPB agents is fixed, it is possible that a lower-priority bus
requestor may never be granted the bus if a higher-priority bus requestor continuously
asks for, and receives, bus ownership. To protect against bus starvation of lower-priority
masters, an optional feature of the TC1796 will detect such cases and momentarily raise
the priority of the lower-priority requestor to the highest priority (above all other priorities),
thereby guaranteeing it access.
Starvation protection employs a counter that is incremented each time an arbitration is
performed in the BCU. When this counter reaches a user-programmable threshold
value, for each active bus request a request flag is stored in the BCU. This flag is cleared
automatically when a master is granted the bus.
When the counter reaches the threshold value, it is automatically reset to zero and starts
counting up again. When the next period is finished, an active request of a master from
which the request flag was set, a starvation event happened. This master will now be set
to the highest priority and will be granted service. If there are several masters to which
this starvation condition applies, they are served in the order of their hard-wired priority
ranking.
Starvation protection can be enabled and disabled through bit SBCU_CON.SPE. The
sample period of the counter is programmed through bit field SBCU_CON.SPC. SPC
should be set to a value at least greater than or equal to the number of masters. Its reset
value is 40H.
Note: The RPB also provides the SPE starvation protection enable bit and the SPC
starvation protection counter bit field. Because of the RPB single master agent
configuration, RBCU_CON.SPE can be always disabled.

6.5.2 FPI Bus Error Handling

When an error occurs on a FPI Bus, its BCU captures and stores data about the
erroneous condition and generates a service request if enabled to do so. The error
conditions that force an error-capture are:
• Error acknowledge: An FPI Bus slave responds with an error to a transaction.
• Un-implemented address: No FPI Bus slave responds to a transaction request.
• Time-out: A slave does not respond to a transaction request within a certain time
window. The number of bus clock cycles that can elapse until a bus time-out is
generated is defined by bit field xBCU_CON.TOUT.
When a transaction causes an error, the address and data phase signals of the
transaction causing the error are captured and stored in registers.
• The Error Address Capture Register (xBCU_EADD) stores the 32-bit FPI Bus
address that has been captured during the erroneous FPI Bus transaction.

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• The Error Data Capture Registers (xBCU_EDAT) stores the 32-bit FPI Bus data bus
information that has been captured during the erroneous FPI Bus transaction.
• The Error Control Capture Register (xBCU_ECON) stores status information of the
bus error event.
If more than one FPI Bus transaction generates a bus error, only the first bus error is
captured. After a bus error has been captured, the capture mechanism must be released
again by software.
If a write transaction from TriCore causes an error on the SPB, the originating master is
not informed about this error as it is not an SPB master agent. With each bus error-
capture event, a service request is generated, and an interrupt can be generated if
enabled and configured in the corresponding service request register.

Interpreting the BCU Control Register Error Information

Although the address and data values captured in registers xBCU_EADD and
xBCU_EDAT, respectively, are self-explanatory, the captured FPI Bus control
information needs some more explanation.
Register xBCU_ECON captures the state of the read (RDN), write (WRN), Supervisor
Mode (SVM), acknowledge (ACK), ready (RDY), abort (ABT), time-out (TOUT), bus
master identification lines (TAG) and transaction operation code (OPC) lines of the
FPI Bus.
The SVM signal is set to 1 for an access in Supervisor Mode and set to 0 for an access
in User Mode.The time-out signal indicates if there was no response on the bus to an
access, and the programmed time (via xBCU_TOUT) has elapsed. TOUT is set to 1 in
this case. An acknowledge code has to be driven by the selected slave during each data
cycle of an access. These codes are listed in Table 6-10.

Table 6-10 FPI Bus Acknowledge Codes

Code (ACK) Description
00B NSC: No Special Condition.
01B SPT: Split Transaction (not used in the TC1796).
10B RTY: Retry. Slave can currently not respond to the access. Master
needs to repeat the access later.
11B ERR: Bus Error, last data cycle is aborted.

Each master on the FPI Bus is assigned a 4-bit identification number, the master TAG
number (see Table 6-11). This makes it possible to distinguish which master has
performed the current transaction.

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Table 6-11 FPI Bus Master TAG Assignments

TAG-Number FPI Bus Description
1001B SPB Peripheral Control Processor (PCP2)
1010B DMA Controller
1011B LFI Bridge
1100B OCDS (Cerberus)
1111B RPB DMA Controller
Others – Reserved

Transactions on the FPI Bus are classified via a 4-bit operation code (see Table 6-12).
Note that split transactions (OPC = 1000B to 1110B) are not used in the TC1796.

Table 6-12 FPI Bus Operation Codes (OPC)

OPC Description
0000B Single Byte Transfer (8-bit)
0001B Single Half-Word Transfer (16-bit)
0010B Single Word Transfer (32-bit)
0100B 2-Word Block Transfer
0101B 4-Word Block Transfer
0110B 8-Word Block Transfer
1111 No operation
0011B, 0111B, 1000B - 1110B Reserved

6.5.3 Clock Management

The BCU can be configured so that it shuts down automatically when not needed by
disabling its internal clock. When it is needed again, for instance when a bus request
signal is received from a master, the BCU will enable its clock and perform the
arbitration. If no further bus activity is required after the transfer has completed, the BCU
will automatically shut off its clock and return to idle mode.
Automatic power management is controlled through the xBCU_CON.PSE bit. When
cleared to 0, power management is disabled, and the BCU clock is always active. This
might be required, for instance, to debug both the active and idle FPI Bus states of an
application via an external emulator or other debugging hardware.

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6.5.4 BCU Debug Support

For debugging purposes, the BCU has the capability for breakpoint generation support.
This OCDS debug capability is controlled by the Cerberus module and must be enabled
by it (indicated by bit xBCU_DBCNTL.EO).
When BCU debug support has been enabled (EO = 1), any breakpoint request
generated by the BCU to the Cerberus disarms the BCU breakpoint logic for further
breakpoint requests. In order to rearm the BCU breakpoint logic again for the next
breakpoint request generation, bit xBCU_DBCNTL.RA must be set. The status of the
BCU breakpoint logic (armed or disarmed) is indicated by bit xBCU_DBCNTL.OA.
There are three types of trigger events:
• Address triggers
• Signal triggers
• Grant triggers

6.5.4.1 Address Triggers

The address debug trigger event conditions are defined by the contents of the
xBCU_DBADR1, xBCU_DBADR2, and xBCU_DBCNTL registers. A wide range of
possibilities arise for the creation of debug trigger events based on addresses. The
following debug trigger events can be selected:
• Match on one signal address
• Match on one of two signal addresses
• Match on one address area
• Mismatch on one address area
Each pair of DBADRx registers and DBCNTL.ONAx bits determine one possible debug
trigger event. The combination of these two possible debug trigger events defined by
DBCNTL.CONCOM1 determine the address debug trigger event condition.

xBCU_DBADR1 xBCU_DBADR2 xBCU_DBCNTL

x = “S“ for SBCU
ADR1 ADR2 ONA2 ONA1
x = “R“ for RBCU
2 2
Control
Compare Logic 1
(equal, Address 1
greater equal) Trigger
FPI Bus
Address Control
Compare Logic 2
(equal, less equal) Address 2
Trigger
MCA05636

Figure 6-9 Address Trigger Generation

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6.5.4.2 Signal Status Triggers

The signal status debug trigger event conditions are defined by the contents of the
xBCU_DBBOS and xBCU_DBCNTL registers. Depending on the selected configuration
a wide range of possibilities arise for the creation of a debug trigger event based on
FPI Bus status signals. Possible combinations are:
• Match on a single signal status
• Match on a multiple signal status
With the multiple signal match conditions, all single signal match conditions are
combined with a logical AND to the signal status debug trigger event signal. The
selection whether or not a single match condition is selected can be enabled/disabled
selectively for each condition via the xBCU_DBCNTL.ONBOSx bits.

xBCU_DBBOS xBCU_DBCNTL
ON ON ON ON x = “S“ for SBCU
RD WR SVM OPC x = “R“ for RBCU
BOS3 BOS2 BOS1 BOS0
4
=
1
RD ≥1
0 0
FPI Bus Signals

=
1
WR
0 0 Signal
=
Status
1 Trigger
SVM
0 0

Equal 1
4 Compare
OPC
0 0

MCA05637

Figure 6-10 Signal Status Trigger Generation

6.5.4.3 Grant Triggers

The signal status debug trigger event conditions are defined via the registers
xBCU_DBGRNT and xBCU_DBCNTL. Depending on the configuration of these
registers, any combination of FPI Bus master trigger events can be configured. Only the
enabled masters in the xBCU_DBGRNT register are of interest for the grant debug
trigger event condition. The grant debug trigger event condition can be enabled/disabled
via bit xBCU_DBCNTL.ONG (see Figure 6-11).

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SBCU_DBGRNT SBCU_DBCNTL
DMA DMA
CBL LFI PCP CBH ONG
L H

Cerberus is granted as
& ≥1
bus master, low priority
&
DMA is granted as bus
master, low priority
&
LFI Bridge is granted as
& Grant
bus master
Trigger
&
DMA is granted as bus
master, high priority
&
PCP is granted as bus
master
&
Cerberus is granted as
bus master, high priority
MCA05638

Figure 6-11 Grant Trigger Generation

6.5.4.4 Combination of Triggers

The combination of the four debug trigger signals to the single BCU breakpoint trigger
event is defined via the bits CONCOM[2:0] of register xBCU_DBCNTL (see
Figure 6-12). The two address trigger signals are combined to one address trigger that
is further combined with signal status and grant trigger signals. A logical AND or OR
combination can be selected for the BCU breakpoint trigger generation.

xBCU_DBCNTL
x = “S“ for SBCU
CONCOM2 CONCOM1 CONCOM0 x = “R“ for RBCU

Address 1 Trigger Address

AND/OR Trigger
Selection
Address 2 Trigger AND/OR
Selection
Signal Status Trigger BCU
AND/OR
Breakpoint
Selection
Grant Trigger Trigger

MCA05639_mod

Figure 6-12 BCU Breakpoint Trigger Combination Logic

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6.5.4.5 BCU Breakpoint Generation Examples

This section gives three examples of how BCU debug trigger events are programmed.

OCDS Debug Example 1

• Task: Generation of a BCU debug trigger event on any SPB write access to address
00002004H or 000020A0H by SPB masters PCP or LFI Bridge.
For this task, the following programming settings for the BCU breakpoint logic must be
executed:
1. Writing SBCU_DBADR1 = 0000 2004H
2. Writing SBCU_DBADR2 = 0000 20A0H
3. Writing SBCU_DBCNTL = C1115010H:
ONBOS[3:0] = 1100B means that no signal status trigger is generated (disabled) for
a read signal match AND write signal match condition according to the settings of bits
RD and WR in register SBCU_DBBOS. Debug trigger event generation for
supervisor mode signal match and opcode signal match condition is disabled.
ONA2 = 01B means that the equal match condition for debug address 2 register is
selected.
ONA1 = 01B means that the equal match condition for debug address 1 register is
selected.
ONG = 1 means that the grant debug trigger is enabled.
CONCOM[2:0] = 101B means that the address trigger is created by address trigger 1
OR address trigger 2 (CONCOM1 = 0), and that the grant trigger is ANDed with the
address trigger (CONCOM0 = 1), and that the signal status trigger is ANDed with the
address trigger (CONCOM2 = 1).
RA = 1 means that the BCU breakpoint logic is rearmed.

4. Writing SBCU_DBGRNT = FFFFFFD7H means that the grant trigger for the SPB
masters PCP and LFI Bridge is enabled.
5. Writing SBCU_DBBOS = 00001000H means that the signal status trigger is
generated on a write transfer and not on a read transfer.

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OCDS Debug Example 2

• Task: generation of a BCU debug trigger event on any half-word access in user mode
to address area 01FFFFFFH to 02FFFFFFH by any master.
For this task, the following programming settings for the BCU breakpoint logic must be
executed:
1. Writing SBCU_DBADR1 = 01FFFFFFH
2. Writing SBCU_DBADR2 = 02FFFFFFH
3. Writing SBCU_DBCNTL = 32206010H:
ONBOS[3:0] = 0011B means that the signal status trigger is disabled for a read or for
write signal status match but enabled for supervisor mode match AND opcode match
conditions according to the settings of bit SVM and bit field OPC in register
SBCU_DBBOS.
ONA2 = 10B means that the address 2 trigger is generated if the FPI Bus address is
greater or equal to SBCU_DBADR2.
ONA1 = 10B means that the address 1 trigger is generated if the FPI Bus address is
greater or equal to SBCU_DBADR1.
ONG = 0 means that the grant debug trigger is disabled.
CONCOM[2:0] = 110B means that the address trigger is created by address trigger 1
AND address trigger 2 (CONCOM1 = 1), and that the grant trigger is OR-ed with the
address trigger (CONCOM0 = 0), and that the signal status trigger is ANDed with the
address trigger (CONCOM2 = 1).
RA = 1 means that the BCU breakpoint logic is rearmed.
4. Writing SBCU_DBGRNT = FFFFFFFFH:
means that no grant trigger for SPB masters is selected (“don’t care” because also
disabled by ONG = 0).
5. Writing SBCU_DBBOS = 00000001H:
means that the signal status trigger is generated for read (RD = 0) and write (WR = 0)
half-word transfers (OPC = 0001B) in user mode (SVM = 0).

OCDS Debug Example 3

• Task: Generation of a BCU debug trigger event on any access into address area
01FFFFFFH to FFFFFFFFH by the PCP.
For this task the following programming settings for the BCU breakpoint logic must be
executed:
1. Writing SBCU_DBADR1 = 01FFFFFFH
2. Writing SBCU_DBADR2 = don’t care
3. Writing SBCU_DBCNTL = 00215010H:
ONBOS[3:0] = 0000B means that a signal status trigger is generated for all FPI Bus
opcodes not equal to a “no operation” opcode.
ONA2 = 00B means that no address 2 trigger is generated.
ONA1 = 10B means that the address 1 trigger is generated if the FPI Bus address is

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greater or equal to SBCU_DBADR1.

ONG = 1 means that the grant debug trigger is enabled.
CONCOM[2:0] = 101B means that the address trigger is created by address trigger 1
OR address trigger 2 (CONCOM1 = 0), and that the grant trigger is ANDed with the
address trigger (CONCOM0 = 1), and that the signal status trigger is ANDed with the
address trigger (CONCOM2 = 1).
RA = 1 means that the BCU breakpoint logic is rearmed.
4. Writing SBCU_DBGRNT = FFFFFFF7H:
means that the grant trigger for the SPB bus master PCP is enabled.
5. Writing SBCU_DBBOS is “don’t care”. No signal trigger for SVM, WR, or RD is
generated.

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6.5.5 SBCU and RBCU Registers

The registers shown in Figure 6-13 are available for the SBCU.

SBCU Registers Overview

Control Register Address/Data Debug Registers Interrupt Registers

Register

xBCU_CON xBCU_ECON xBCU_DBCNTL xBCU_SRC

xBCU_EADD xBCU_DBGRNT
Module Identification xBCU_EDAT xBCU_DBADR1
Register
xBCU_DBADR2
xBCU_ID xBCU_DBBOS
x = “S“ for SBCU
x = “R“ for RBCU xBCU_DBGNTT
xBCU_DBADRT
xBCU_DBBOST MCA05640_mod

Figure 6-13 SBCU Registers

The complete and detailed address maps of SBCU/RBCU are described in
Table 18-4/Table 18-26 on Page 18-11/Page 18-79 of this TC1796 System Units (Vol.
1 of 2) User’s Manual.

Table 6-13 Registers Address Space

Module Base Address End Address Note
SBCU F000 0100H F000 01FFH –
RBCU F010 0000H F010 00FFH –

Table 6-14 Registers Overview - SBCU Registers

Register Register Long Name Offset Description
Short Name1) Address see
xBCU_ID xBCU Module Identification Register 08H Page 6-36
xBCU_CON xBCU Control Register 10H Page 6-37
xBCU_ECON xBCU Error Control Capture Register 20H Page 6-39
xBCU_EADD xBCU Error Address Capture Register 24H Page 6-41
xBCU_EDAT xBCU Error Data Capture Register 28H Page 6-41
xBCU_DBCNTL xBCU Debug Control Register 30H Page 6-42

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Table 6-14 Registers Overview - SBCU Registers (cont’d)

Register Register Long Name Offset Description
Short Name1) Address see
SBCU_DBGRNT SBCU Debug Grant Mask Register 0034H Page 6-45
RBCU_DBGRNT RBCU Debug Grant Mask Register Page 6-47
xBCU_DBADR1 xBCU Debug Address 1 Register 0038H Page 6-48
xBCU_DBADR2 xBCU Debug Address 2 Register 003CH Page 6-48
xBCU_DBBOS xBCU Debug Bus Operation Signals 0040H Page 6-49
Register
SBCU_DBGNTT SBCU Debug Trapped Master Register 0044H Page 6-51
RBCU_DBGNTT RBCU Debug Trapped Master Register Page 6-53
xBCU_DBADRT xBCU Debug Trapped Address Register 0048H Page 6-54
xBCU_DBBOST xBCU Debug Trapped Bus Operation 004CH Page 6-55
Signals Register
xBCU_SRC xBCU Service Request Control Register 00FCH Page 6-58
1) Prefix x = “S” stands for “SBCU” and x = “R” for “RBCU”.

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6.5.5.1 BCU Control Registers

The xBCU Module Identification Register ID contains read-only information about the
xBCU module version.

SBCU_ID
SBCU Module Identification Register (08H) Reset Value: 0000 6AXXH
RBCU_ID
RBCU Module Identification Register (08H) Reset Value: 0000 6AXXH
31 16 15 8 7 0

0 MODNUM MODREV

r r r

Field Bits Type Description

MODREV [7:0] r Module Revision Number
MODREV defines the module revision number. The value
of a module revision starts with 01H (first revision).
MODNUM [15:8] r Module Number Value
This bit field defines the module identification number for
the xBCU: 6AH
0 [31:16] r Reserved
Read as 0.

The BCU Control Registers for SPB and RPB control the overall operation of the SBCU
and PBCU, including setting the starvation sample period, the bus time-out period,
enabling starvation-protection mode, and error handling.

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SBCU_CON
SBCU Control Register (10H) Reset Value: 4009 FFFFH
RBCU_CON
RBCU Control Register (10H) Reset Value: 4009 FFFFH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPC 0 SPE PSE 0 DBG

rw r rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TOUT

rw

Field Bits Type Description

TOUT [15:0] rw BCU Bus Time-Out Value
The bit field determines the number of System
Peripheral Bus time-out cycles. Default after reset is
FFFFH (= 65536 bus cycles).1)
DBG 16 rw BCU Debug Trace Enable
0B BCU debug trace disabled
1B BCU debug trace enabled (default after reset)
PSE 18 rw BCU Power Saving (Automatic Clock Control)
Enable
0B BCU power saving disabled (default after reset)
1B BCU power saving enabled
SPE 19 rw BCU Starvation Protection Enable
0B BCU starvation protection disabled
1B BCU starvation protection enabled (default
after reset)
SPC [31:24] rw Starvation Period Control
Determines the sample period for the starvation
counter. Must be larger than the number of masters.
The reset value is 40H.
0 17 rw Reserved
Read as 0 after reset; should be written with 0.

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Field Bits Type Description

0 [23:20] r Reserved
Read as 0; should be written with 0.
1) When an access occurs from an SPB bus master to the RPB while the RPB is busy, the SPB bus master has
to wait until the RPB is granted. Therefore, the SBCU time-out value must be larger than the RBCU time-out
value: SBCU_CON.TOUTmin = RBCU_CON.TOUT + 28.

6.5.5.2 BCU Error Registers

The capture of bus error conditions is enabled by setting BCU_CON.DBG to 1. In case
of a bus error, information about the condition will then be stored in the BCU error
capture registers. The BCU error capture registers for SPB and RPB can then be
examined by software to determine the cause of the FPI Bus error.
If enabled and a FPI Bus error occurs, the ECON registers holds the captured FPI Bus
control information and an error count of the number of bus errors. The EADD registers
store the captured FPI Bus address. The EDAT registers store the captured FPI Bus
data.
If the capture of FPI Bus error conditions is disabled (BCU_CON.DBG = 0), the BCU
error capture registers remain untouched.

Note: The BCU error capture registers store only the parameters of the first error. In case
of multiple bus errors, an error counter BCU_ECON.ERRCNT shows the number
of bus errors since the first error occurred. A hardware reset clears this bit field to
zero, but the counter can be set to any value through software. This counter is
prevented from overflowing, so a value of 216 - 1 indicates that at least this many
errors have occurred, but there may have been more. After BCU_ECON has been
read, the BCU_ECON, BCU_EADD and BCU_EDAT registers are re-enabled to
trace FPI Bus error conditions.

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SBCU_ECON
SBCU Error Control Capture Register (20H) Reset Value: 0000 0000H
RBCU_ECON
RBCU Error Control Capture Register (20H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
T
OPC TAG RDN WRN SVM ACK ABT RDY
OUT
rwh rwh rwh rwh rwh rwh rwh rwh rwh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ERRCNT

rwh

Field Bits Type Description

ERRCNT [15:0] rwh FPI Bus Error Counter
ERRCNT is incremented on every occurrence of an
FPI Bus error. ERRCNT is reset to 0000H after the
ECON register is read.1)
TOUT 16 rwh State of FPI Bus Time-Out Signal
This bit indicates the state of the time-out signal at an
FBI Bus error.
0B No time-out occurred.
1B Time-out has occurred.
RDY 17 rwh State of FPI Bus Ready Signal
This bit indicates the state of the ready signal at an
FBI Bus error.
0B Wait state(s) have been inserted. Ready signal
was active.
1B Ready signal was inactive.
ABT 18 rwh State of FPI Bus Abort Signal
This bit indicates the state of the abort signal at an
FBI Bus error.
0B Master has aborted an FPI Bus transfer. Abort
signal was active.
1B Abort signal was inactive.

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Field Bits Type Description

ACK [20:19] rwh State of FPI Bus Acknowledge Signals
This bit field indicates the acknowledge code that has
been output by the selected slave at an FPI Bus
error. Coding see Table 6-10.
SVM 21 rwh State of FPI Bus Supervisor Mode Signal
This bit indicates whether the FPI Bus error occurred
in supervisor mode or in user mode.
0B Transfer was initiated in supervisor mode.
1B Transfer was initiated in user modes.
WRN 22 rwh State of FPI Bus Write Signal
This bit indicates whether the FPI Bus error occurred
at a write cycle (see Table 6-15).
RDN 23 rwh State of FPI Bus Read Signal
This bit indicates whether the FPI Bus error occurred
at a read cycle (see Table 6-15).
TAG [27:24] rwh FPI Bus Master Tag Number Signals
This bit field indicates the FPI Bus master TAG
number (definitions see Table 6-11).
OPC [31:28] rwh FPI Bus Operation Code Signals
The FPI Bus operation codes are defined in
Table 6-12.
1) For the SBCU_ECON.ERRCNT bit field, the following additional sentence must be added: in the TC1796,
aborted accesses to a 0 wait state SPB slave may also increment ERRCNT when the slave generates an error
acknowledge.

Table 6-15 FPI Bus Read/Write Error Indication

RD WR FPI Bus Cycle
0 0 FPI Bus error occurred at the read transfer of a read-modify-write
transfer.
0 1 FPI Bus error occurred at a read cycle of a single transfer.
1 0 FPI Bus error occurred at a write cycle of a single transfer or at the
write cycle of a read-modify-write transfer.
1 1 Does not occur

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SBCU_EADD
SBCU Error Address Capture Register (24H) Reset Value: 0000 0000H
RBCU_EADD
RBCU Error Address Capture Register (24H) Reset Value: 0000 0000H
31 0

FPIADR

rwh

Field Bits Type Description

FPIADR [31:0] rwh Captured FPI Bus Address
This bit field holds the 32-bit FPI Bus address that has
been captured at an FPI Bus error. Note that if multiple
bus errors occurred, only the address of the first bus
error is captured.

SBCU_EDAT
SBCU Error Data Capture Register (28H) Reset Value: 0000 0000H
RBCU_EDAT
RBCU Error Data Capture Register (28H) Reset Value: 0000 0000H
31 0

FPIDAT

rwh

Field Bits Type Description

FPIDAT [31:0] rwh Captured FPI Bus Address
This bit field holds the 32-bit FPI Bus data that has
been captured at an FPI Bus error. Note that if multiple
bus errors occurred, only the data of the first bus error
is captured.

User’s Manual 6-41 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

6.5.5.3 OCDS Registers

SBCU_DBCNTL
SBCU Debug Control Register (30H) Reset Value: 0000 7003H
RBCU_DBCNTL
RBCU Debug Control Register (30H) Reset Value: 0000 7003H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON ON ON ON
BOS BOS BOS BOS 0 ONA2 0 ONA1 0 ONG
3 2 1 0
rw rw rw rw r rw r rw r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CON CON CON
0 COM COM COM 0 RA 0 OA EO
2 1 0
r rw rw rw r w r r r

Field Bits Type Description

EO 0 r Status of BCU Debug Support Enable
This bit is controlled by the Cerberus and enables the
BCU debug support.
0B BCU debug support is disabled.
1B BCU debug support is enabled.
(default after reset)
OA 1 r Status of BCU Breakpoint Logic
0B The BCU breakpoint logic is disarmed. Any
further breakpoint activation is discarded.
1B The BCU breakpoint logic is armed.
The OA bit is set by writing a 1 to bit RA. When OA is
set, registers xBCU_DBGNTT, xBCU_DBADRT, and
xBCU_DBBOST are reset.
RA 4 w Rearm BCU Breakpoint Logic
Writing a 1 to this bit rearms BCU breakpoint logic and
sets bit OA = 1. RA is always reads as 0.

User’s Manual 6-42 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

Field Bits Type Description

CONCOM0 12 rw Grant and Address Trigger Relation
0B Grant trigger condition and the address trigger
condition are combined with a logical OR for
further control.
1B The grant trigger condition and the address
trigger condition are combined with a logical
AND for further control (see Figure 6-12).
CONCOM1 13 rw Address 1 and Address 2 Trigger Relation
0B Address 1 trigger condition and address 2
trigger condition are combined with a logical
OR for further control.
1B Address 1 trigger condition and address 2
trigger condition are combined with a logical
AND for further control (see Figure 6-12).
CONCOM2 14 rw Address and Signal Trigger Relation
0B Address trigger condition and signal trigger
condition are combined with a logical OR for
further control.
1B Address trigger condition and the signal trigger
condition are combined with a logical AND for
further control (see Figure 6-12).
ONG 16 rw Grant Trigger Enable
0B No grant debug event trigger is generated.
1B The grant debug event trigger is enabled and
generated according the settings of register
DBGRNT (see Figure 6-11).
ONA1 [21:20] rw Address 1 Trigger Control
00B No address 1 trigger is generated.
01B An address 1 trigger event is generated if the
FPI Bus address is equal to DBADR1.
10B An address 1 trigger event is generated if
FPI Bus address is greater or equal to
DBADR1.
11B same as 00B.
See also Figure 6-9.

User’s Manual 6-43 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

Field Bits Type Description

ONA2 [25:24] rw Address 2 Trigger Control
00B No address 2 trigger is generated.
01B An address 2 trigger event is generated if the
FPI Bus address is equal to DBADR2.
10B An address 2 trigger event is generated if
FPI Bus address is greater or equal to
DBADR2.
11B same as 00B.
See also Figure 6-9.
ONBOS0 28 rw Opcode Signal Status Trigger Condition
0B A signal status trigger is generated for all
FPI Bus opcodes except a “no operation”
opcode.
1B A signal status trigger is generated if the
FPI Bus opcode matches the opcode as
defined in DBBOS.OPC (see Figure 6-10).
ONBOS1 29 rw Supervisor Mode Signal Trigger Condition
0B The signal status trigger generation for the
FPI Bus supervisor mode signal is disabled.
1B A signal status trigger is generated if the
FPI Bus supervisor mode signal state is equal
to the value of DBBOS.SVM (see Figure 6-10).
ONBOS2 30 rw Write Signal Trigger Condition
0B The signal status trigger generation for the
FPI Bus write signal is disabled.
1B A signal status trigger is generated if the
FPI Bus write signal state is equal to the value
of DBBOS.WR (see Figure 6-10).
ONBOS3 31 rw Read Signal Trigger Condition
0B The signal status trigger generation for the
FPI Bus read signal is disabled.
1B A signal status trigger is generated if the
FPI Bus read signal state is equal to the value
of DBBOS.RD (see Figure 6-10).

User’s Manual 6-44 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

Field Bits Type Description

0 [3:2], r Reserved
[11:5], Read as 0; should be written with 0.
15,
[19:17],
[23:22],
[27:26]

SBCU_DBGRNT
SBCU Debug Grant Mask Register (34H) Reset Value: 0000 FFFFH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA DMA
1 CBL LFI PCP 1 CBH
L H
rw rw rw rw rw rw rw rw

Field Bits Type Description

CBH 0 rw Cerberus Grant Trigger Enable, High Priority
0B FPI Bus transactions on SPB with high-priority
Cerberus as bus master are enabled for grant
trigger event generation.
1B FPI Bus transactions on SPB with high-priority
Cerberus as bus master are disabled for grant
trigger event generation.
1 [2:1], rw Reserved
[15:8] Read as 1 after reset; reading these bits will return the
value last written.
PCP 3 rw PCP Grant Trigger Enable
0B FPI Bus transactions on SPB with PCP as bus
master are enabled for grant trigger event
generation.
1B FPI Bus transactions on SPB with PCP as bus
master are disabled for grant trigger event
generation.

User’s Manual 6-45 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

Field Bits Type Description

DMAH 4 rw DMA Grant Trigger Enable, High Priority
0B FPI Bus transactions on SPB with low-priority
DMA channels as bus master are enabled for
grant trigger event generation.
1B FPI Bus transactions on SPB with low-priority
DMA channels as bus master are disabled for
grant trigger event generation.
LFI 5 rw LFI Bridge Grant Trigger Enable
0B FPI Bus transactions on SPB with LFI Bridge as
bus master are enabled for grant trigger event
generation.
1B FPI Bus transactions on SPB with LFI Bridge as
bus master are disabled for grant trigger event
generation.
DMAL 6 rw DMA Grant Trigger Enable, Low Priority
0B FPI Bus transactions on SPB with high-priority
DMA channels as bus master are enabled for
grant trigger event generation.
1B FPI Bus transactions on SPB with high-priority
DMA channels as bus master are disabled for
grant trigger event generation.
CBL 7 rw Cerberus Grant Trigger Enable, Low Priority
0B FPI Bus transactions on SPB with low-priority
Cerberus as bus master are enabled for grant
trigger event generation.
1B FPI Bus transactions on SPB with low-priority
Cerberus as bus master are disabled for grant
trigger event generation.
0 [31:16] r Reserved
Read as 0; should be written with 0.

User’s Manual 6-46 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

RBCU_DBGRNT
RBCU Debug Grant Mask Register (34H) Reset Value: 0000 FFFFH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA DMA
1 1 1
L H
rw rw rw rw rw

Field Bits Type Description

1 [3:0], rw Reserved
5, Read as 1 after reset; reading these bits will return the
[15:7] value last written.
DMAH 4 rw DMA Grant Trigger Enable, High Priority
0B FPI Bus transactions on RPB with low-priority
DMA channels as bus master are enabled for
grant trigger event generation.
1B FPI Bus transactions on RPB with low-priority
DMA channels as bus master are disabled for
grant trigger event generation.
DMAL 6 rw DMA Grant Trigger Enable, Low Priority
0B FPI Bus transactions on RPB with high-priority
DMA channels as bus master are enabled for
grant trigger event generation.
1B FPI Bus transactions on RPB with high-priority
DMA channels as bus master are disabled for
grant trigger event generation.
0 [31:16] r Reserved
Read as 0; should be written with 0.

User’s Manual 6-47 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

SBCU_DBADR1
SBCU Debug Address 1 Register (38H) Reset Value: 0000 0000H
RBCU_DBADR1
RBCU Debug Address 1 Register (38H) Reset Value: 0000 0000H
31 0

ADR1

rw

Field Bits Type Description

ADR1 [31:0] rw Debug Trigger Address 1
This register contains the address for the address 1
trigger event generation.

SBCU_DBADR2
SBCU Debug Address 2 Register (3CH) Reset Value: 0000 0000H
RBCU_DBADR2
RBCU Debug Address 2 Register (3CH) Reset Value: 0000 0000H
31 0

ADR2

rw

Field Bits Type Description

ADR2 [31:0] rw Debug Trigger Address 2
This register contains the address for the address 2
trigger event generation.

User’s Manual 6-48 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

SBCU_DBBOS
SBCU Debug Bus Operation Signals Register
(40H) Reset Value: 0000 0000H
RBCU_DBBOS
RBCU Debug Bus Operation Signals Register
(40H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 RD 0 WR 0 SVM OPC

r rw r rw r rw rw

Field Bits Type Description

OPC [3:0] rw Opcode for Signal Status Debug Trigger
This bit field determines the type (opcode) of a
FPI Bus transaction for which a signal status debug
trigger event is generated (if enabled by
DBCNTL.ONBOS0 = 1).
0000B Trigger on single byte transfer selected
0001B Trigger on single half-word transfer
selected
0010B Trigger on single word transfer selected
0100B Trigger on 2-word block transfer selected
0101B Trigger on 4-word block transfer selected
0110B Trigger on 8-word block transfer selected
1111B Trigger on no operation selected
others Reserved
SVM 4 rw SVM Signal for Status Debug Trigger
This bit determines the mode of a FPI Bus
transaction for which a signal status debug trigger
event is generated (if enabled by
DBCNTL.ONBOS1 = 1).
0B Trigger on user mode selected
1B Trigger on supervisor mode selected

User’s Manual 6-49 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

Field Bits Type Description

WR 8 rw Write Signal for Status Debug Trigger
This bit determines the state of the WR signal of an
FPI Bus transaction for which a signal status debug
trigger event is generated (if enabled by
DBCNTL.ONBOS2 = 1).
0B Trigger on a single write transfer or write cycle
of an atomic transfer selected
1B No operation or read transaction selected
RD 12 rw Write Signal for Status Debug Trigger
This bit determines the state of the RD signal of an
FPI Bus transaction for which a signal status debug
trigger event is generated (if enabled by
DBCNTL.ONBOS3 = 1).
0B Trigger on a single read transfer or read cycle
of an atomic transfer selected
1B No operation or write transfer selected
0 [7:5], r Reserved
[11:9], Read as 0; should be written with 0.
[31:13]

User’s Manual 6-50 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

SBCU_DBGNTT
SBCU Debug Trapped Master Register
(44H) Reset Value: FFFF FFFFH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH
NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR
17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA DMA
1 CBL LFI PCP 1 CBH
L H
r rh rh rh rh rh r rh

Field Bits Type Description

CBH 0 rh High-Priority Cerberus FPI Bus Master Status
This bit indicates whether the high-priority Cerberus
was SPB bus master when the break trigger event
occurred.
0B The high-priority Cerberus was not a SPB bus
master.
1B The high-priority Cerberus was SPB bus
master.
PCP 3 rh PCP FPI Bus Master Status
This bit indicates whether the PCP was SPB bus
master when the break trigger event occurred.
0B The PCP was not a SPB bus master.
1B The PCP was SPB bus master at the break
trigger event.
DMAH 4 rh High-Priority DMA FPI Bus Master Status
This bit indicates whether the high-priority DMA
channels were SPB bus master when the break
trigger event occurred.
0B The high-priority DMA channels were not an
SPB bus master.
1B The high-priority DMA channels were SPB bus
master. Bits CHNRxy determine the DMA
channel number.

User’s Manual 6-51 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

Field Bits Type Description

LFI 5 rh LFI Bridge FPI Bus Master Status
This bit indicates whether the LFI Bridge was SPB
bus master when the break trigger event occurred.
0B The LFI Bridge was not a SPB bus master.
1B The LFI Bridge was SPB bus master.
DMAL 6 rh Low-Priority DMA FPI Bus Master Status
This bit indicates whether the low priority DMA
channels were SPB bus master when the break
trigger event occurred.
0B The low priority DMA channels were not a SPB
bus master.
1B The low priority DMA channels were SPB bus
master. Bits CHNRxy determine the DMA
channel number.
CBL 7 rh Low-Priority Cerberus FPI Bus Master Status
This bit indicates whether the low-priority Cerberus
was SPB bus master when the break trigger event
occurred.
0B The low-priority Cerberus was not a SPB bus
master.
1B The low-priority Cerberus was SPB bus master.
CHNR0y 16 + y rh DMA Channel Number Status
(y = 0-7) These bits indicate which DMA channel with number
0y was active when a DMA break trigger event
occurred.
0B DMA channel 0y was not active at a DMA break
trigger event.
1B DMA channel 0y was active at a DMA break
trigger event.
CHNR1y 24+ y rh DMA Channel Number Status
(y = 0-7) These bits indicate which DMA channel with number
1y was active when a DMA break trigger event
occurred.
0B DMA channel 1y was not active at a DMA break
trigger event.
1B DMA channel 1y was active at a DMA break
trigger event.
1 [2:1], r Reserved
[15:8] Read as 1.

User’s Manual 6-52 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

RBCU_DBGNTT
RBCU Debug Trapped Master Register
(44H) Reset Value: FFFF FFFFH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH
NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR
17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA DMA
1 1 1
L H
r rh r rh r

Field Bits Type Description

1 [3:0], rw Reserved
5, Read as 1.
[15:7]
DMAH 2 rh High-Priority DMA FPI Bus Master Status
This bit indicates whether the high-priority DMA
channels were RPB bus master when the break
trigger event occurred.
0B The high-priority DMA channels were not a
RPB bus master.
1B The high-priority DMA channels were RPB bus
master. Bits CHNRxy determine the DMA
channel number.
DMAL 4 rh Low-Priority DMA FPI Bus Master Status
This bit indicates whether the low priority DMA
channels were RPB bus master when the break
trigger event occurred.
0B The low priority DMA channels were not a RPB
bus master.
1B The low priority DMA channels were RPB bus
master. Bits CHNRxy determine the DMA
channel number.

User’s Manual 6-53 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

Field Bits Type Description

CHNR0y 16 + y rh DMA Channel Number Status
(y = 0-7) These bits indicate which DMA channel with number
1y was active when a DMA break trigger event
occurred at the RPB.
0B DMA channel 1y was not active at a DMA break
trigger event at the RPB.
1B DMA channel 1y was active at a DMA break
trigger event at the RPB.
CHNR1y 24 + y rh DMA Channel Number Status
(y = 0-7) These bits indicate which DMA channel with number
1y was active when a DMA break trigger event
occurred at the RPB.
0B DMA channel 1y was not active at a DMA break
trigger event at the RPB.
1B DMA channel 1y was active at a DMA break
trigger event at the RPB.

SBCU_DBADRT
SBCU Debug Trapped Address Register
(48H) Reset Value: 0000 0000H
RBCU_DBADRT
RBCU Debug Trapped Address Register
(48H) Reset Value: 0000 0000H
31 0

FPIADR

Field Bits Type Description

FPIADR [31:0] r FPI Bus Address Status
This register contains the FPI Bus address that was
captured when the OCDS break trigger event
occurred.

User’s Manual 6-54 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

SBCU_DBBOST
SBCU Debug Trapped Bus Operation Signals Register
(4CH) Reset Value: 0000 3180H
RBCU_DBBOST
RBCU Debug Trapped Bus Operation Signals Register
(4CH) Reset Value: 0000 3180H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPI
0
TAG
r rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPI FPI
FPI FPI FPI FPI FPI FPI FPI FPI
0 T ABO
RD OPS RST WR RDY ACK SVM OPC
OUT RT
r rh rh rh rh rh rh rh rh rh rh

Field Bits Type Description

FPIOPC [3:0] rh FPI Bus Opcode Status
This bit field indicates the type (opcode) of the
FPI Bus transaction captured from the FPI Bus signal
lines when the BCU break trigger event occurred.
0000B Single byte transfer
0001B Single half-word transfer
0010B Single word transfer
0100B 2-word block transfer
0101B 4-word block transfer
0110B 8-word block transfer
1111B No operation
others Reserved
FPISVM 4 rh FPI Bus Supervisor Mode Status
This bit indicates the state of the supervisor mode
signal captured from the FPI Bus signal lines when
the BCU break trigger event occurred.
0B User mode
1B Supervisor mode

User’s Manual 6-55 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

Field Bits Type Description

FPIACK [6:5] rh FPI Bus Acknowledge Status
This bit field indicates the acknowledge signal status
captured from the FPI Bus signal lines when the BCU
break trigger event occurred.
00B No special case
01B Error
10B Reserved
11B Retry, slave did not respond
FPIRDY 7 rh FPI Bus Ready Status
This bit indicates the ready signal status captured
from the FPI Bus signal lines when the BCU break
trigger event occurred.
0B Last cycle of transfer
1B Not last cycle of transfer
FPIWR 8 rh FPI Bus Write Indication Status
This bit indicates the write signal status captured from
the FPI Bus signal lines when the BCU break trigger
event occurred.
0B Single write transfer or write cycle of an atomic
transfer
1B No operation or read transfer
FPIRST [10:9] rh FPI Bus Reset Status
This bit field indicates the reset signal status captured
from the FPI Bus signal lines when the BCU break
trigger event occurred.
00B Reset of all FPI Bus components
11B No reset
others Reserved
FPIOPS 11 rh FPI Bus OCDS Suspend Status
This bit indicates the OCDS suspend signal status
captured from the FPI Bus signal lines when the BCU
break trigger event occurred.
0B No OCDS suspend request is pending
1B An OCDS suspend request is pending

User’s Manual 6-56 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

Field Bits Type Description

FPIRD 12 rh FPI Bus Read Indication Status
This bit indicates the read signal status captured from
the FPI Bus signal lines when the BCU break trigger
event occurred.
0B Single read transfer or read cycle of an atomic
transfer
1B No operation or write transfer
FPIABORT 13 rh FPI Bus Abort Status
This bit indicates the abort signal status captured
from the FPI Bus signal lines when the BCU break
trigger event occurred.
0B A transfer that had already started was aborted
1B Normal operation
FPITOUT 14 rh FPI Bus Time-out Status
This bit indicates the time-out signal status captured
from the FPI Bus signal lines when the BCU break
trigger event occurred.
0B Normal operation
1B A time-out event was generated
FPITAG [19:16] rh FPI Bus Master TAG Status
This bit indicates the master TAG captured from the
FPI Bus signal lines when the BCU break trigger
event occurred. The master TAG identifies the master
of the transfer which generated BCU break trigger
event.
0000B Cerberus Interface (high-priority)
0001B Peripheral Control Processor (PCP)
0010B DMA Controller (high-priority channels)
0011B LFI Bridge
0100B DMA Controller (low-priority channels)
0101B Cerberus Interface (low-priority)
others Reserved
0 15, rh Reserved
[31:20] Read as 0; should be written with 0.

User’s Manual 6-57 V2.0, 2007-07

Buses, V2.0
 TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges

6.5.5.4 BCU Service Request Control Register

In case of a bus error, the BCU generates an interrupt request to the selected service
provider (usually the CPU). This interrupt request is controlled through a standard
service request control register.

SBCU_SRC
SBCU Service Request Control Register
(FCH) Reset Value: 0000 0000H
RBCU_SRC
RBCU Service Request Control Register
(FCH) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET CLR
SRR SRE TOS 0 SRPN
R R
w w rh rw r r rw

Field Bits Type Description

SRPN [7:0] rw Service Request Priority Number
TOS [11:10] r Type of Service Control
The SBCU/RBCU can only be serviced by the CPU.
SRE 12 rw Service Request Enable
SRR 13 rh Service Request Flag
CLRR 14 w Request Clear Bit
SETR 15 w Request Set Bit
0 [9:8], r Reserved
[31:16] Read as 0; should be written with 0.

Note: Further details on interrupt handling and processing are described in Chapter 14
of this TC1796 System Units (Vol. 1 of 2) User’s Manual.

User’s Manual 6-58 V2.0, 2007-07

Buses, V2.0
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System Units (Vol. 1 of 2)
Program Memory Unit

7 Program Memory Unit

The Program Memory Unit (PMU) shown in Figure 7-1 contains the following functional
units:
• 2 Mbyte of Program Flash Memory (PFLASH)
• 128 Kbyte of Data Flash Memory (DFLASH)
• 16 Kbyte of Boot ROM (BROM)
– 8 Kbyte Boot Code ROM
– 8 Kbyte Factory Test ROM
• Program Local Memory Bus Interface
• Emulation Memory Interface

To/From Program
Local Memory Bus
64

PLMB Interface
Slave

64

Emulation Flash Interface Module ROM Control

Memory
Interface 128 KB 16 KB BROM
DFLASH (8 KB for Boot
8 KB for Test)
2 MB
Program PFLASH
Memory Unit
(PMU)
64

To Emulation Memory EBU = External Bus Unit

(TC1796ED only) PLMB = Program Local Memory Bus
DFLASH = Data Flash Memory
PFLASH = Program Flash Memory
BROM = Boot ROM
MCB05641

Figure 7-1 PMU Block Diagram

7.1 Boot ROM

The functionality of the 16 Kbyte Boot ROM (BROM) is described in Chapter 4 (Reset
and Boot Operation) at Page 4-16.

User’s Manual 7-1 V2.0, 2007-07

PMU, V2.0
 TC1796
System Units (Vol. 1 of 2)
Program Memory Unit

7.2 Program & Data Flash Memory

The embedded Flash module of TC1796 incorporates a 2 Mbyte Flash memory for
program code or constant data (called PFLASH or program Flash) and a 128 Kbyte
Flash memory used for data storage (called DFLASH or data Flash).
Both, PFLASH and DFLASH, provide error correction of single-bit errors within a 64-bit
read double-word, resulting in a very low failure rate. The programming quantity is one
page, including 256 byte for the PFLASH and 128 byte for the DFLASH.
The PFLASH is implemented as one Flash bank. The DFLASH is built up by two Flash
banks. This bank configuration allows combinations of concurrent Flash operations:
• Reading code or data from PFLASH while one bank of the DFLASH is busy with a
program or erase operation.
• Reading data from one bank of the DFLASH while the other bank of the DFLASH is
busy with a program or erase operation.
• Programming one bank of the DFLASH while the other bank of the DFLASH is busy
with an erase operation and simultaneously reading from PFLASH.
Note: It is not possible to read data from DFLASH while the PFLASH is busy with a
program or erase operation.
The embedded Flash module is divided into the following two sub-modules:
• The Flash Interface and Control Module (FIM)
– Controls the execution of Flash commands (Flash command state machine FCS)
– Handles error correction and ECC generation
– Provides a PLMB bus interface to the PMI for instruction accesses and to the DMI
module (via the LMI-Bridge) for data accesses.
• The Flash Array Module (FAM)
– One PFLASH bank of 2 Mbyte
– Two PFLASH banks of 64 Kbyte each
– Control logic that includes assembly buffers and voltage generators, for example
The FIM and FAM are main parts of the Program Memory Unit (PMU). An overview of
the PMU integration into the system architecture is shown in the TC1796 block and bus
system diagrams (see Page 1-9 and Page 6-1). A basic diagram of the Flash modules
is shown in Figure 7-2.

User’s Manual 7-2 V2.0, 2007-07

PMU, V2.0
 TC1796
System Units (Vol. 1 of 2)
Program Memory Unit

Flash Command
State Machine 2 Mbyte
Flash Interface (PLMB)

(FCS) Program Flash

(PFLASH)
Flash
64 Control
Logic
Data Bank 0
Error 128 Kbyte
Correction Data Flash
(ECC) (DFLASH) Bank 1

Flash Interface & Flash Array Module

Control Module (FIM) (FAM)

MCB05642

Figure 7-2 Basic Diagram of Flash Module

All Flash operations are initiated by transferring command sequences to the Flash that
are based on the JEDEC standard. The command sequences to the Flash are high-level
commands such as “Erase Sector”. State transitions during execution of the commands,
such as termination of command execution or errors, are indicated by status flags and
maskable interrupts. Command sequences are normally written to the PMU by the CPU
but can also be issued by the PCP or the DMA controller.

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7.2.1 Program Flash Overview

The PFLASH memory has a capacity of 2 Mbyte. The internal structure of the PFLASH
is based on a sector architecture. For flexible erase, programming, and protection
capability, the 2 Mbyte are divided into 13 sectors of eight 16 Kbyte sectors (combined
into two 64 Kbyte physical sectors), one 128 Kbyte sector, one 256 Kbyte sector, and
three 512 Kbyte sectors. PFLASH sectors are numbered as PSx with x = 0 to 12.

PFLASH
256 byte Page PP8191
…. Sector PS12 512 Kbyte
256 byte Page PP6144

Sector PS11 512 Kbyte

Sector PS10 512 Kbyte

2 Mbyte
PFLASH Bank
Sector PS9 256 Kbyte

Sector PS8 128 Kbyte

Sector PS7 16 Kbyte
Sector PS6 Physical Sector 1
16 Kbyte
PPS1
Sector PS5 16 Kbyte 64 Kbyte
Sector PS4 16 Kbyte
Sector PS3 16 Kbyte
256 byte Page PP63 Sector PS2 16 Kbyte Physical Sector 0
PPS0
…. Sector PS1 16 Kbyte 64 Kbyte
256 byte Page PP0 Sector PS0 16 Kbyte
MCA05643

Figure 7-3 PFLASH Structure

The PFLASH operates in paging mode which makes it possible to load 64 words
(= 256 byte) into a page assembly buffer with fast CPU accesses before this buffer is
programmed into the Flash memory with one Write Page command. Thus, the
programming width is always 256 byte. Programming of single words, bytes, or bits is
not supported. The 256-byte wide PFLASH pages are numbered with PPy with y = 0 to
8191.
Only one complete sector can be erased. Program and erase operations are initiated
and supervised by the Flash Command State Machine (FCS), but its execution is further
controlled by control logic in the Flash Array Module (FAM).

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The PFLASH array delivers 256-bit wide read data with one read access. In the TC1796,
these 256 bits are transferred to the CPU and PMI via the 64-bit wide Program Local
Memory Bus (PLMB) using single-cycle burst transfers with four 64-bit transfers. During
such a burst transfer, the next sequential 256-bit read data is prefetched from the
PFLASH. Therefore, except a delay of the first initial read data access, sequential burst
transfers are provided, supporting the highest possible instruction throughput from
PFLASH to the CPU with execution of two 32-bit instructions in one cycle. Also non-
cached instruction accesses are burst accesses with up to four double-word transfers.
Each PFLASH sector can be separately locked against erasing and reprogramming.
Write operations to a locked and protected sector are only possible only if the sector is
temporarily unlocked using a dedicated password check sequence. Additionally, also an
OTP (One Time Programmable) function can be selected for each sector. An OTP sector
is locked forever, and erasing and reprogramming is no longer possible.

Features of Program Flash

• 2 Mbyte on-chip program Flash memory
• Usable for instruction code execution or constant data storage
• 256-byte wide program interface
– 256 bytes are programmed into PFLASH page in one step/command
• 256-bit read interface
– Transfer from PFLASH to CPU/PMI by four 64-bit single-cycle burst transfers
• Dynamic correction of single-bit errors during read access
• Detection of double bit errors
• Fixed sector architecture
– Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte, and three 512 Kbyte sectors
– Each sector separately erasable
– Each sector separately write-protectable
• Configurable read protection for complete PFLASH with sophisticated read access
supervision, combined with write protection for complete PFLASH (protection against
“Trojan horse” software)
• Configurable write protection for each sector
– Each sector separately write-protectable
– With capability to be re-programmed
– With capability to be locked forever (OTP)
• Password mechanism for temporarily disable write or read protection
• On-chip programming voltage generation
• PFLASH is delivered in erased state (read all zeros)
• JEDEC standard based command sequences for PFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
• Margin check for detection of problematic PFLASH bits

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Table 7-1 defines the sectors with their sector numbers, sector sizes, and address
ranges. The PFLASH contains thirteen sectors PS[12:0] with different sizes. Two
64 Kbyte physical sectors PPS[1:0] are defined for the PFLASH.

Table 7-1 PFLASH Bank, Sector and Page Definitions

Numbering Size Cached Non-Cached
Address Range Address Range
PFLASH Bank
PB 2 Mbyte 8000 0000H - 801F FFFFH A000 0000H - A01F FFFFH
PFLASH Sectors
PS0 PPS01) 16 Kbyte 8000 0000H - 8000 3FFFH A000 0000H - A000 3FFFH
PS1 PPS02) 8000 4000H - 8000 7FFFH A000 4000H - A000 7FFFH
PS2 16 Kbyte 8000 8000H - 8000 BFFFH A000 8000H - A000 BFFFH
PS3 16 Kbyte 8000 C000H - 8000 FFFFH A000 C000H - A000 FFFFH
PS4 PPS1 16 Kbyte 8001 0000H - 8001 3FFFH A001 0000H - A001 3FFFH
PS5 16 Kbyte 8001 4000H - 8001 7FFFH A001 4000H - A001 7FFFH
PS6 16 Kbyte 8001 8000H - 8001 BFFFH A001 8000H - A001 BFFFH
PS7 16 Kbyte 8001 C000H - 8001 FFFFH A001 C000H - A001 FFFFH
PS8 128 Kbyte 8002 0000H - 8003 FFFFH A002 0000H - A003 FFFFH
PS9 256 Kbyte 8004 0000H - 8007 FFFFH A004 0000H - A007 FFFFH
PS10 512 Kbyte 8008 0000H - 800F FFFFH A008 0000H - A00F FFFFH
PS11 512 Kbyte 8010 0000H - 8017 FFFFH A010 0000H - A017 FFFFH
PS12 512 Kbyte 8018 0000H - 801F FFFFH A018 0000H - A01F FFFFH
PFLASH Pages
PP0 256 byte 8000 0000H - 8000 00FFH A000 0000H - A000 00FFH
PPn3) 256 byte (8000 0000H + OFF) - (A000 0000H + OFF) -
(8000 0000H + OFF + FFH) (A000 0000H + OFF + FFH)
(with OFF = n × 100H) (with OFF = n × 100H)
PP8191 256 byte 801F FF00H - 801F FFFFH A01F FF00H - A01F FFFFH
1) PPSx (x = 0, 1) is a physical PFLASH sector.
2) PPSx (x = 0, 1) is a physical PFLASH sector.
3) n = 0-8191

Note: The sectors PS[7:0] are also called “logical sectors”. These logical sectors have a
reduced endurance (50) compared to the physical sectors (1000). In order to

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increase the endurance of a logical sector, its corresponding physical sector can
be erased and reprogrammed after every 50 erase/program cycles of the logical
sector.

7.2.2 Data Flash Overview

The on-chip DFLASH has a capacity of 128 Kbyte, organized in two independent
banks/sectors of 64 Kbyte each, DB0/DS0 and DB1/DS1. The structure with two
independent Flash banks makes it possible executing read accesses to one bank while
erasing or programming the other array bank. Erase and programming operations can
also be performed simultaneously in the two DFLASH banks, whereby an erase
operation of one DFLASH bank is suspended by a programming operation of the other
DFLASH bank, and automatically resumed afterwards. Each DFLASH bank can be
erased only completely.

DFLASH

Page 1023 128 byte

Page 1022 128 byte
. .
. . 64 Kbyte
. . DFLASH Bank 1 (DB1)
. . DFLASH Sector 1 (DS1)
Page 513 128 byte
Page 512 128 byte

Page 511 128 byte

Page 510 128 byte
. .
. . 64 Kbyte
. . DFLASH Bank 0 (DB0)
. . DFLASH Sector 0 (DS0)
Page 1 128 byte
Page 0 128 byte
MCA05644

Figure 7-4 DFLASH Structure

For programming of the DFLASH, the data for one page (32 words = 128 bytes) must be
loaded into an assembly buffer using fast CPU accesses before this assembly buffer is
programmed into one page of the data Flash with one programming command operation.
Thus, the programming width of the DFLASH is always 128 bytes. Programming of
single words, bytes, or bits is not supported. The DFLASH uses the same JEDEC-
standard based command sequences as the program Flash does.

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Features of Data Flash

• 128 Kbyte on-chip data Flash memory, organized in two 64 Kbyte banks
• Usable for data storage with EEPROM functionality
• 128 byte program interface
– 128 bytes are programmed into one DFLASH page by one step/command
• 64-bit read interface (no burst transfers)
• Dynamic correction of single-bit errors during read access
• Detection of double bit errors
• Fixed sector architecture
– Two 64 Kbyte banks/sectors
– Each sector separately erasable
• Configurable read protection (combined with write protection) for complete DFLASH
together with PFLASH read protection
• Password mechanism to temporarily disable write and read protection
• Erasing/programming of one bank possible while reading data from the other bank
• Programming of one bank possible while erasing the other bank
• On-chip generation of programming voltage
• DFLASH is delivered in erased state (read all zeros)
• JEDEC-standard based command sequences for DFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
• Margin check for detection of problematic DFLASH bits
The DFLASH contains two 64 Kbyte sectors, DS0 and DS1, which are identical with
banks DB0 and DB1. DFLASH pages are always 128-byte wide.

Table 7-2 DFLASH Bank and Page Definitions

Numbering Size Cached Non-Cached
Address Range Address Range
DFLASH Sectors (and Banks)
DS0 (= DB0) 64 Kbyte 8FE0 0000H - 8FE0 FFFFH AFE0 0000H - AFE0 FFFFH
DS1 (= DB1) 64 Kbyte 8FE1 0000H - 8FE1 FFFFH AFE1 0000H - AFE1 FFFFH
DFLASH Pages
DS0 DP0 128 byte 8FE0 0000H - 8FE0 007FH AFE0 0000H - AFE0 007FH
DPn1) 128 byte (8FE0 0000H + OFF) - (AFE0 0000H + OFF) -
(8FE0 0000H + OFF + 7FH) (AFE0 0000H + OFF + 7FH)
(with OFF = n × 80H) (with OFF = n × 80H)
DP511 128 byte 8FE0 FF80H - 8FE0 FFFFH AFE0 FF80H - AFE0 FFFFH

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Table 7-2 DFLASH Bank and Page Definitions (cont’d)

Numbering Size Cached Non-Cached
Address Range Address Range
DS1 DP512 128 byte 8FE1 0000H - 8FE1 007FH AFE1 0000H - AFE1 007FH
DPn1) 128 byte 8FE1 0000H + OFF - AFE1 0000H + OFF -
8FE1 0000H + OFF + 7FH AFE1 0000H + OFF + 7FH
(with OFF = n × 80H) (with OFF = n × 80H)
DP1023 128 byte 8FE1 FF80H - 8FE1 FFFFH AFE1 FF80H - AFE1 FFFFH
1) n = 0-1023

7.2.3 User Configuration Blocks Overview

The contents of the three User Configuration Blocks (UCBm, m = 0-2) determine user-
specific Flash configuration and protection functions such as keywords and sector-
specific lock bits for the PFLASH. Each 1 Kbyte configuration block contains four UCB
pages.
The UCBs are implemented as a Flash memory. The addressing of the UCBs overlays
the cached addresses of the first 3 Kbyte of the PFLASH. The UCBs are not readable by
the user. A user program can indirectly modify the contents of one UCB page only by two
commands, the Write User Configuration Page and the Erase User Configuration Block
command.

256 byte UCB Page UCP11

256 byte UCB Page UCP10 User Config.
Block UCB2
256 byte UCB Page UCP9 (1 Kbyte)
256 byte UCB Page UCP8
256 byte UCB Page UCP7
256 byte UCB Page UCP6 User Config.
Block UCB1
256 byte UCB Page UCP5 (1 Kbyte)
256 byte UCB Page UCP4
256 byte UCB Page UCP3
256 byte UCB Page UCP2 User Config.
Block UCB0
256 byte UCB Page UCP1 (1 Kbyte)
256 byte UCB Page UCP0
MCA05645

Figure 7-5 UCB Flash Structure

More details on UCBs are described on Page 7-27.

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Table 7-3 User Configuration Block Definitions

Numbering Size Address Range
UCB0 UCP0 256 byte A000 0000H - A000 00FFH
UCP1 256 byte A000 0100H - A000 01FFH
UCP2 256 byte A000 0200H - A000 02FFH
UCP3 256 byte A000 0300H - A000 03FFH
UCB1 UCP4 256 byte A000 0400H - A000 04FFH
UCP5 256 byte A000 0500H - A000 05FFH
UCP6 256 byte A000 0600H - A000 06FFH
UCP7 256 byte A000 0700H - A000 07FFH
UCB2 UCP8 256 byte A000 0800H - A000 08FFH
UCP9 256 byte A000 0900H - A000 09FFH
UCP10 256 byte A000 0A00H - A000 0AFFH
UCP11 256 byte A000 0B00H - A000 0BFFH

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7.2.4 Basic Flash Operating Modes

The basic operating modes are Flash-bank specific. Generally, there are two basic
operating modes of the Flash banks:
• Read Mode (optionally with Page Mode activated)
• Command Mode
Since the TC1796 Flash array has three autonomous Flash banks, one PFLASH bank
and two DFLASH banks, parallel write command execution (programming one bank
while erasing the other bank) is supported for the two DFLASH banks, but not for the
PFLASH bank and one DFLASH bank.
Flash register accesses are independent of the operating modes and allowed in any
state. After any reset operation, the Flash banks are in Read Mode.
The following sections describe the operating modes specifically for the PFLASH. If
there is any difference for the DFLASH, additional hints are given.

7.2.4.1 Read Mode

A Flash bank enters or remains in the standard operating mode, the Read Mode
• After a Reset-to-Read command, if no programming or erase operation is active
• After any completed Erase command
• After a completed Write Page (programming) command
• After every other completed command execution
• During ramp-up time after the deactivation of any reset
• After incorrect address/data values or wrong command sequence
• After incorrect requests (password failure) to program or erase a locked sector
• After an incorrect write access to a read-protected Flash memory
In Read Mode, command sequences are allowed. The Read Mode remains active until
the last cycle of a command sequence is executed. In case of a write or erase command,
Read Mode is terminated at the end of the command sequence.
If Page Mode is active in Read Mode, the page assembly buffer can be loaded (written)
with data for the next write page (program) command while Flash read operations occur
in parallel. As a special case, it is even allowed to place instructions in the PFLASH, used
to load the page assembly buffer or to write command sequences to the DFLASH.
Read accesses from a Flash array are always 64-bit aligned. During these 64-bit wide
read accesses from the Flash array, automatic error detection and - if a single-bit error
is detected - an error correction can be executed. Bit errors are reported by separate
single-bit error flags and double-bit error flags that are located in the FLASH_FSR
register. Setting of single-bit or/and double-bit error flags can generate a Flash interrupt
if enabled (see Page 7-37). In case of a double-bit error, the CPU is interrupted by a bus
error trap per default which further results in an interrupt from the PLMB Bus Control Unit
PBCU.

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For verify operations, the standard read can be combined with a margin check to find
problematic bits (a 0 is read instead of a programmed 1) in advance. The change of
margins is controlled via the margin registers (see Page 7-35).

7.2.4.2 Command Mode

Every write operation to the Flash memory space is interpreted as a command cycle,
belonging to a command sequence. A command sequence is composed of one to at
maximum six command cycles (write operations) with well defined address and data
values. After the last command cycle of a correct command sequence, the Command
Mode is entered. The Command Mode remains active during the whole command
execution. The state of a command execution is indicated by several status flags in the
FSR status register.
Some command sequences that do not affect the Flash banks, e.g. the Enter Page Mode
command or the Clear Status command, are immediately executed and finished after the
last command cycle of the command. For such type of command sequences, the
Command Mode is terminated immediately after its execution. After all other command
sequences which activate a Flash bank operation such as erasing or programming, the
Command Mode and the related status flags remain active until the command is really
finished.
Note that all write operations to the Flash memory space are handled by the FCS.
Writing incorrect addresses or data values within a command sequence, or writing them
in an wrong sequence, generates a sequence error (FSR.SQER is set) and terminates
Command Mode.
If one DFLASH bank is busy with erasing, a programming command sequence for the
other DFLASH bank is accepted immediately and the execution of the erase operation
is interrupted until the programming operation is terminated (automatic suspend/resume
operation).
When accessing a busy PFLASH or DFLASH bank by a data read operation (e.g. by a
CPU read in a user program), the read operation is blocked (halted) until the related
Flash bank is no more busy. Therefore, it is recommended to access a PFLASH or
DFLASH bank by data read operations only when they are no longer busy (check the
corresponding busy flags first).
The cycle definitions of command sequences are based on the JEDEC standard. The
different write cycles of command sequences are not only used for operation definitions
such as a sector-erase command, but also as fail-safe and unlock cycles in order to
protect the Flash against inadvertent changes.
Note: The write cycles to the Flash belonging to a command sequence are/may be
buffered in the DMI in store/write buffers. To maintain data coherency (defined
sequence of command cycles is mandatory) and to guarantee immediate transfer
of the command sequence to the PMU, all write cycles to the Flash must access

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the Flash in its non-cached address space. Additionally, it is recommended to

include a dummy read cycle to a PMU register after the last write cycle of a
command sequence.
Note: User code (command sequences) that programs or erase Program Flash should
not be executed from internal program flash, but from other internal or external
memory (e.g. from SPRAM).

7.2.4.3 Page Mode

With the Enter Page Mode command, Page Mode is entered for one of the three Flash
banks and status flag FSR.PFPAGE (for PFLASH) or FSR.DFPAGE (for DFLASH) is
set. In Page Mode, the assembly buffer is ready to be filled with data in preparation for
a subsequent PFLASH or DFLASH programming operation. The width of the page
assembly buffer is 128-byte for DFLASH and 256-byte for PFLASH. Page Mode can be
entered only if the related Flash bank is not busy (if it does not execute program or erase
operations).

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7.2.5 Command Sequence Definitions

Flash commands are executed by writing specific data to dedicated addresses in a well
defined command specific sequence. The data to be transmitted within a command
sequence must be transmitted right-aligned on data bus lines D[7:0] as byte (exception:
32-bit data, 64-bit data, 32-bit password). Data lines D[31:8] are ignored in a command
sequence (indicated in the “Data” columns of the command tables by a “X”). Addresses
in a command sequence always refer to the non-cached address ranges. The available
command sequences are shown in Figure 7-4.

Table 7-4 Flash Command Overview

Command Description Details see
Reset-to-Read Resetting Flash State Machine to Page 7-15
Read Mode
Enter Page Mode Initiate Page Mode Page 7-15
Load Page Buffer Loading page assembly buffer with Page 7-16
32-bit or 64-bit data
Write Page Programming a Flash page with Page 7-18
assembly buffer content
Write User Configuration Page Programming a user configuration Page 7-19
page with assembly buffer content
Erase Sector Erasing a PFLASH or DFLASH Page 7-20
sector
Erase User Configuration Block Erasing a UCB Page 7-22
Disable Write Protection1) Temporarily unlocking write Page 7-23
protection
Disable Read Protection Temporarily unlocking read Page 7-24
protection
Resume Protection Resumption of disabled read or write Page 7-24
protection
Clear Status Resetting status register flags Page 7-25
1) This command is not available for the DFLASH.

Note: During a programming or erasing operation, a minimum CPU clock (fCPU)

frequency of 1 MHz must be provided.

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7.2.5.1 Reset-to-Read Command

With the one-cycle Reset-to-Read command, the internal command state machine is
reset to its initial state. This command can be issued at any time during a command
sequence.

Table 7-5 Reset-to-Read Command

Cycle No. Address Data
Cycle 1 A000 5554H XXXX XXF0H

A running programming or erase operation of a Flash bank is not affected by a Reset-to-

Read command and will be continued and finished. All error flags in the Flash Status
Register FSR are cleared, and an active Page Mode is aborted. The busy state of the
Flash bank (write operation or voltage ramp-up) is not aborted and the busy flags in the
FSR are not affected. A Reset-to-Read command during a command sequence does
not generate a sequence error (FSR.SQER is not set).

7.2.5.2 Enter Page Mode Command

The Page Mode is entered for a Flash bank with the one-cycle Enter Page Mode
command, indicating that the page assembly buffer is ready to be filled with data for the
related Flash bank in preparation for a subsequent Flash programming operation. The
Page Mode can only be assigned to one of the PFLASH/DFLASH banks by executing
the address/data information shown in Table 7-6. The width of the page assembly buffer
is 128-byte for DFLASH and 256-byte for PFLASH. Further, the Page Mode can only be
entered if the related Flash bank is not busy (if it does not execute program or erase
operations). However, an erase or program operation can be active in another Flash
bank than the one that is in Page Mode.

Table 7-6 Enter Page Mode Command

Cycle No. PFLASH DFLASH
Address Data Bank Address Data
Cycle 1 A000 5554H XXXX XX50H DB0 AFE0 5554H XXXX XX5DH
DB1 AFE1 5554H XXXX XX5DH

When Page Mode is entered, the pointer to the page assembly buffer is set to its first
word location. Its base address has to point to the addressed Flash bank.
An active Page Mode is indicated when bit FSR.PFPAGE (for PFLASH) or
FSR.DFPAGE (for DFLASH) is set.
The Page Mode and the Read Mode are allowed in parallel at the same time and in the
same Flash memory bank. A new Enter Page Mode command during Page Mode aborts

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the actual Page Mode, indicated by sequence error flag FSR.SQER set, and restarts a
new page operation. The selected assembly register remains unchanged (not cleared)
with a new Enter Page Mode command.

7.2.5.3 Load Page Buffer Command

There are basically two types of Load Page Buffer command:
• Load Page Buffer command with 32-bit data (two-cycle command)
• Load Page Buffer command with 64-bit data (one-cycle command)

Table 7-7 Load Page Buffer Command

Cycle No. PFLASH DFLASH
Address Data Bank Address Data
32-Bit Load Page Buffer Command
Cycle 1 A000 55F0H 32-bit data DB0 AFE0 55F0H 32-bit data
DB1 AFE1 55F0H
Cycle 2 A000 55F4H 32-bit data DB0 AFE0 55F0H 32-bit data
DB1 AFE1 55F4H
64-Bit Load Page Buffer Command
Cycle 1 A000 55F0H 64-bit data DB0 AFE0 55F0H 64-bit data
DB1 AFE1 55F0H

The Load Page Buffer command loads 32-bit words or 64-bit double-words into the
assembly buffer, starting from the lowest to the highest assembly buffer entry. Only one
type of the Load Page Buffer commands (either with 32-bit or 64-bit data width) is
allowed during one assembly buffer loading sequence. Mixing 64-bit and 32-bit write
data width within one assembly buffer filling sequence is not allowed.
The data width for the assembly buffer filling sequence is selected by using instruction(s)
with the corresponding data format. A single Load Page Buffer command consists of a
store instruction to a specific address. In case of 64-bit data width, the same address
A000 55F0H always has to be used. In case of 32-bit data width, alternating addresses
A000 55F0H and A000 55F4H must be used.
For loading of the 256-byte wide assembly buffer for PFLASH programming, thirty-two
Load Page commands with 64-bit data or sixty-four Load Page Buffer commands with
32-bit data must be issued. For loading of the 128-byte wide assembly buffer for
DFLASH programming, sixteen Load Page commands with 64-bit data or thirty-two Load
Page Buffer commands with 32-bit data must be issued.
The following example shows a Load Page Buffer command sequence for the DFLASH
bank 0 assembly buffer (128 bytes) with 32-bit data width:

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1. Write AFE0 55F0H = word 0 (assembly buffer byte 3-0)

2. Write AFE0 55F4H = word 1 (assembly buffer byte 7-4)
3. Write AFE0 55F0H = word 2 (assembly buffer byte 11-8)
4. Write AFE0 55F4H = word 3 (assembly buffer byte 15-12)
…
1. Write AFE0 55F0H = word 30 (assembly buffer byte 123-120)
2. Write AFE0 55F4H = word 31 (assembly buffer byte 127-124)
Sequence errors (bit FSR.SQER set) are generated by a Load Page Buffer command in
the following cases:
• A mix of 64-bit and 32-bit write data width within one assembly buffer filling sequence
has been detected.
• An assembly buffer overrun condition is detected. The write data causing the overrun
is lost.

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7.2.5.4 Write Page Command

With the four-cycle Write Page command, the complete contents of the assembly buffer
(256 bytes for PFLASH, 128 bytes for DFLASH) are transferred (programmed) into one
page of PFLASH or DFLASH. The write address of cycle 4 is the page start address of
the page to be programmed with the assembly buffer content. Parameter “n” is the page
number PPn for PFLASH or DPn for DFLASH (see also Table 7-1 and Table 7-2).

Table 7-8 Write Page Command

Cycle No. PFLASH DFLASH
Address Data Bank Address Data
Cycle 1 A000 5554H XXXX XXAAH DB0 AFE0 5554H XXXX XXAAH
DB1 AFE1 5554H
Cycle 2 A000 AAA8H XXXX XX55H DB0 AFE0 AAA8H XXXX XX55H
DB1 AFE1 AAA8H
Cycle 3 A000 5554H XXXX XXA0H DB0 AFE0 5554H XXXX XXA0H
DB1 AFE1 5554H
Cycle 4 A000 0000H + XXXX XXAAH DB0 AFE0 0000H + XXXX XXAAH
n × 100H n × 80H
DB1 AFE1 0000H +
n × 80H

Address bits [31:16] used in the command cycles of the Write Page command must be
the same as those used by the previous Enter Page Mode command. Otherwise, a
command sequence error is generated (bit FSR.SQER set) and the execution of the
command is aborted.
The Write Page command programs a specific Flash page with the complete content of
the assembly buffer. It also programs invalid data of assembler buffer locations that have
not been loaded by previous Load Page Buffer commands.
With the last cycle of the Write Page command, Page Mode is terminated and the
following status flags are updated:
• FSR.PFPAGE or FSR.DFPAGE is cleared, indicating that the related Flash is no
more in Page Mode.
• FSR.PROG is set, indicating that a programming operation is running.
• Either FSR.PBUSY or FSR.D0BUSY or FSR.D1BUSY is set, indicating that the
programming operation is running in PFLASH or in DFLASH bank 0 or in DFLASH
bank 1.

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The page programming algorithm includes a programming quality check that identifies
and reprograms weak bits of a Flash page. If the reprogramming of weak bits is
unsuccessful, the verify error flag FSR.VER is set.
If read protection is activated or if write protection is enabled for the sector that contains
the page to be programmed, Page Mode is terminated, programming operation is not
started, and the protection error flag FSR.PROER is set. Write protection must be
disabled previously to a programming operation for a write-protected sector by issuing a
Disable Read Protection or/and Disable Write Protection command.

7.2.5.5 Write User Configuration Page Command

The four-cycle Write User Configuration Page command is used to transfer (program)
the contents of the 256 byte assembly buffer into one page of a user configuration block.
The Write User Configuration Page command sequence is identical with the Write Page
command except cycle 3. Cycle 3 transmits different data than the Write Page command
does. The address transmitted in cycle 4 of the Write User Configuration Page command
is the start address of the corresponding User Configuration Page UCP[11:0] (see
Table 7-3).

Table 7-9 Write User Configuration Page Command

Cycle No. Address Data
Cycle 1 A000 5554H XXXX XXAAH
Cycle 2 A000 AAA8H XXXX XX55H
Cycle 3 A000 5554H XXXX XXC0H
Cycle 4 Start address of UCP to be XXXX XXAAH
programmed
(A000 0X00H with X = 0H-BH)

Only if protection is not installed (e.g. for the very first installation of protection),
read/write protection need not be disabled. After writing the correct protection
confirmation code in the respective user configuration page, the protection is installed
and becomes active after the next reset.
If a user configuration page needs to be reprogrammed (not possible for pages within
UCB2) and protection is installed (FSR.PROIN = 1), the protection must be temporarily
disabled, and afterwards the UCB must be erased by the Erase User Configuration Block
command. When no protection is installed (FSR.PROIN = 0), the user configuration
page can be programmed without any restriction.
If a Write User Configuration Page command is issued and the start address of the UCP
(cycle 4) belongs to a UCB that is read- or write-protected, the protection error flag
FSR.PROER is set and programming operation is not started.

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7.2.5.6 Erase Sector Command

The six-cycle Erase Sector command is used to erase a sector in PFLASH or DFLASH.
In PFLASH, either one of the 13 sectors PSx (x = 0-12) or one of the 2 physical sectors
PPS0 or PPS1 that each include four sectors can be erased. In DFLASH, one of its two
banks DB0 or DB1 (identical with sectors DS0 and DS1) can be erased.
The write address transmitted in the last cycle of the Erase Sector command is the sector
start address of the sector PSx that should be erased.

Table 7-10 Erase Sector Command

Cycle PFLASH DFLASH
No. Sec- Address Data Bank Address Data
tor
Cycle 1 PSx1) A000 5554H XXXX XXAAH DB0 AFE0 5554H XXXX XXAAH
PPS0 DB1 AFE1 5554H
PPS1 –
Cycle 2 PSx1) A000 AAA8H XXXX XX55H DB0 AFE0 AAA8H XXXX XX55H
PPS0 DB1 AFE1 AAA8H
PPS1 –
Cycle 3 PSx1) A000 5554H XXXX XX80H DB0 AFE0 5554H XXXX XX80H
PPS0 DB1 AFE1 5554H
PPS1 –
Cycle 4 PSx1) A000 5554H XXXX XXAAH DB0 AFE0 5554H XXXX XXAAH
PPS0 DB1 AFE1 5554H
PPS1 –
Cycle 5 PSx1) A000 AAA8H XXXX XX55H DB0 AFE0 AAA8H XXXX XX55H
PPS0 DB1 AFE1 AAA8H
PPS1 –
1)
Cycle 6 PSx A0XX XXXXH2) XXXX XX30H DB0 AFE0 0000H XXXX XX40H
PPS0 A000 0000H XXXX XX40H DB1 AFE1 0000H
PPS1 A001 0000H –
1) “x” is the number of the PFLASH sector PSx that is defined in Table 7-1 (x = 0-12).
2) This is the complete 32-bit non-cached start address of the PFLASH sector PSx (x = 0-12) to be erased.

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With the last cycle of the Erase Sector command, Command Mode is entered and the
following status flags are updated:
• FSR.ERASE is set, indicating that a erase operation is running.
• Either FSR.PBUSY or FSR.D0BUSY or FSR.D1BUSY is set, indicating that an erase
operation is running in PFLASH or in DFLASH bank 0 or in DFLASH bank 1.
The start of sector erase operation is delayed if the Erase Sector command was issued
to one DFLASH bank while the other DFLASH bank is busy with a program operation.
Read accesses to a DFLASH bank that is currently not erased or programmed are
possible while the other DFLASH bank is erased or programmed. A read access to a
busy (erasing or programming) Flash bank is allowed but delayed until the
corresponding Flash bank is no longer busy. Note that in this case the read path (PLMB)
is completely locked. Therefore, reading from a Flash bank in erase or program state
should be avoided by first polling the busy flags in the FSR register.
If the Erase Sector operation is used to erase a physical sector of the program Flash
(PPS0 or PPS1), this operation is executed only if none of the four sectors within the
related physical sector is write-protected, and if no read protection is installed, or if Flash
protection is disabled.
If read protection and/or write protection for the sector to be erased is enabled, or if one
or more of the sectors within the physical sector to be erased is OTP-protected, the
protection error flag FSR.PROER is set, Command Mode is not entered, and the erase
operation is not started.

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7.2.5.7 Erase User Configuration Block Command

This six-cycle Erase User Configuration Block command is used to erase a UCB.
The Erase User Configuration Block command sequence is identical with the Erase
Sector command sequence except cycle 6. Cycle 6 of the Erase User Configuration
Block command provides the base address of the UCB to be erased.

Table 7-11 Erase User Configuration Block Command

Cycle No. Address Data
Cycle 1 A000 5554H XXXX XXAAH
Cycle 2 A000 AAA8H XXXX XX55H
Cycle 3 A000 5554H XXXX XX80H
Cycle 4 A000 5554H XXXX XXAAH
Cycle 5 A000 AAA8H XXXX XX55H
Cycle 6 UCB0 A000 0000H XXXX XXC0H
UCB1 A000 0400H
UCB2 A000 0800H

With the last cycle of the Erase User Configuration command, Command Mode is
entered and the following status flags are updated:
• FSR.ERASE is set, indicating that a erase operation is running.
• FSR.PBUSY is set, indicating that the erase operation is running in the UCB.
This command can only be executed after read protection and/or sector write protection
has been disabled. If protection is not disabled when the Erase User Configuration Block
command is received, the protection error flag FSR.PROER is set, the Command Mode
is not entered, and the erase operation is not started.
After a Erase User Configuration Block command, a new protection configuration
(including keywords and protection confirmation code) can be written to the pages of the
user configuration block. But note that the user configuration blocks UCB0 and UCB1
can only be modified up to 4 times during the lifetime of a TC1796 device. UCB2 can be
programmed only once.
Note: UCB2 is OneTime-Programmable (OTP). If sector write protection is installed and
confirmed in UCB2, this block can never be erased again. UCB2 can only be
erased before the confirmation of OTP write protection.

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7.2.5.8 Disable Write Protection Command

The six-cycle Disable Write Protection command temporarily disables the write
protection of all protected PFLASH sectors as defined for user 0 (indicated in register
PROCON0) or user 1 (indicated in register PROCON1).
The Disable Write Protection command is not accepted for UCB2 because UCB2 is a
OTP write-protected UCB.

Table 7-12 Disable Write Protection Command

Cycle No. Address Data
Cycle 1 A000 5554H XXXX XXAAH
Cycle 2 A000 AAA8H XXXX XX55H
Cycle 3 A000 553CH XXXX XX00H (user 0, UCB0) or
XXXX XX01H (user 1, UCB1)
Cycle 4 A000 AAA8H First 32-bit password
Cycle 5 A000 AAA8H Second 32-bit password
Cycle 6 A000 5558H XXXX XX05H

The Disable Write Protection command is a protected command sequence, meaning

that two passwords (data in cycle 4 and 5) must be issued within the command. The first
and second 32-bit passwords are internally compared with the first and second 32-bit
keyword as defined in the related UCB0 or UCB1 (see Table 7-16). If one or both
passwords are not identical to their related keywords, the sectors remain protected and
the protection error flag FSR.PROER is set. In this case, a new Disable Write Protection
command is only accepted after the next reset operation.
After the correct execution of the Disable Write Protection command, all protected
sectors as defined for UCB0 or UCB1 are unlocked (if no read protection is additionally
installed and active) and flag FSR.WPRODIS0 or FSR.WPRODIS1 is set. Erase and
write operations to temporarily unlocked sectors are now possible, until
• A Resume Protection command is executed, or
• The next reset operation (hardware or software reset) is executed.

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7.2.5.9 Disable Read Protection Command

The six-cycle Disable Read Protection command temporarily disables an installed Flash
read protection.

Table 7-13 Disable Read Protection Command

Cycle No. Address Data
Cycle 1 A000 5554H XXXX XXAAH
Cycle 2 A000 AAA8H XXXX XX55H
Cycle 3 A000 553CH XXXX XX00H
Cycle 4 A000 AAA8H First 32-bit password
Cycle 5 A000 AAA8H Second 32-bit password
Cycle 6 A000 5558H XXXX XX08H

The Disable Read Protection command is a protected command sequence, meaning

that two passwords (data in cycle 4 and 5) must be issued within the command. The first
and second 32-bit passwords are internally compared to the first and second 32-bit
keyword as defined in the related user configuration block UCB0 (see Table 7-16).
If one or both passwords are not identical to their related keywords, the sectors remain
protected and the protection error flag FSR.PROER is set. In this case, a new Disable
Read Protection command is only accepted after the next reset operation.
After the correct execution of this command, the PFLASH and both DFLASH banks are
temporarily unlocked and flag FSR.RPRODIS is set. Read, erase, and write operations
to all unlocked (not separately write-protected) sectors are now possible, until
• A Resume Protection command is executed, or
• The next reset operation (hardware or software reset) is executed.

7.2.5.10 Resume Protection Command

With the one-cycle Resume Protection Command, a temporarily unlocked write
protection and/or read protection is terminated and the protection state is resumed. This
command resumes both kinds of temporarily disabled protection, write and read
protection.

Table 7-14 Resume Protection Command

Cycle No. Address Data
Cycle 1 A000 5554H XXXX XX5EH

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7.2.5.11 Clear Status Command

The one-cycle Clear Status command clears/resets the following flags of the Flash
status register FSR:
• Error flags:
PFOPER, DFOPER, SQER, PROER, PFSBER, DFSBER, PFDBER, and DFDBER
• Status flags:
PROG, ERASE
The one-cycle Clear Status command is accepted only in Read Mode. Otherwise a
command sequence error occurs (FSR.SQER is set). Read Mode is entered if Flash is
not busy and after every error detection and indication change in FSR.

Table 7-15 Clear Status Command

Cycle No. Address Data
Cycle 1 A000 5554H XXXX XXF5H

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7.2.6 Data Flash and EEPROM Emulation

The 128 Kbyte Data Flash is able to support an emulation of an EEPROM. This
EEPROM emulation is fully based on a software administration by a user program. The
only hardware feature that supports EEPROM emulation is the ability to program a page
in one DFLASH bank while the other DFLASH bank is erased, and to read data from one
bank while the other bank is busy with programming or erasing operation.
The main difference between a Flash memory and an EEPROM is its endurance. For
EEPROMs, the endurance is typically 120.000 write/erase cycles. The typical endurance
of a Flash memory is in the range of 1.000 to 10.000 write/erase cycles. The following
example discusses the basic principles of the EEPROM emulation as supported in the
TC1796.
Example: 16 Kbyte EEPROM emulation, using the complete 128 Kbyte DFLASH
The DFLASH is logically divided into eight 16 Kbyte regions that operate as a circular
buffer memory. Each of these regions has 128 pages, the smallest DFLASH entity that
can be programmed by one programming/write command. At a time, one of the eight
16 Kbyte regions is always regarded as active EEPROM region. The other regions are
within a loop in which all regions within one DFLASH bank can be erased together and
programmed (page-wise) consecutively in a fixed order.
The active EEPROM region is held as a mirror memory in an on-chip RAM area. After a
reset operation, the active EEPROM region is copied into the RAM and the related
16 Kbyte region may be marked (e.g. with all-one programming of a page) to be invalid.
Now the next consecutive 16 Kbyte region within the DFLASH circular buffer becomes
the active EEPROM region.
After the copy event, the user program is able to read/write data from/to the mirrored
RAM area very fast. The user program also has the task of tracking the changes in the
RAM and to decide when and which part of the mirrored EEPROM region must be written
back (programmed) to the actual active (and erased) EEPROM region of the DFLASH.
This decision can be, for example, an upcoming system switch-off event for which the
EEPROM data must be saved.
As a result of the continuously changing assignment of the active EEPROM region in a
circular buffer, the DFLASH memory cells of one EEPROM region can be
erased/programmed 8-times as often as one physical 16 Kbyte region, resulting in an
8-fold endurance for one EEPROM region. Additionally, a reduced retention is assumed
for EEPROM data. Thus, for the above described example with 16 Kbyte regions and
with a retention of 5 years, the endurance for an emulated EEPROM region is increased
to 120.000 write/erase cycles. As a result, the endurance of an emulated EEPROM
region can be increased by raising the software overhead and DFLASH memory area.
For marking of invalid word-lines (two consecutive pages) it is allowed to over-program
with all-one data. This is the only kind of twofold programming of a page which is allowed
and can only be performed in DFLASH.

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7.2.7 Read and Write Protection

In the TC1796, three different types of protection are possible:
• Read protection for PFLASH and DFLASH
(always implies also a global write protection for PFLASH and DFLASH)
• Sector write protection for PFLASH
• Sector OTP write protection for PFLASH
In general, three protection configurations, assigned to so-called “users”, are defined in
UCBs.
• User 0 = User Configuration Block 0:
This is the master user. It is able to install read protection for the whole PFLASH and
DFLASH. It can also install sector write protection for the PFLASH sectors. User 0
controls its protection configuration and its keywords via UCB0.
• User 1 = User Configuration Block 1:
User 1 is able to install sector write protection for the PFLASH sectors with lower
priority than user 0. User 1 controls its protection configuration and its keywords via
UCB1.
• User 2 = User Configuration Block 2:
User 2 is able to install sector OTP write protection for the PFLASH sectors. OTP
write-protected sectors are locked for ever, and are never re-programmable.
If read or write protection is installed and activated once, changing the read/write
protection configuration parameters in the UCBs is password-protected and can only be
executed if the passwords are known.
Note: If any PFLASH sector is locked for ever (OTP installed), PFLASH and DFLASH
related testing investigations for Failure Analysis Requests (FARs) are no more
possible.

7.2.7.1 User Configuration Block Definitions

The three 1 Kbyte user configuration blocks UCBx (x = 0-2) contain four 256 byte pages
each. The contents of the three user configuration blocks determine the read, write, and
OTP protection configuration as assigned for user 0, user 1, and user 2.
The UCBs are Flash memory locations that can be programmed page-wise with the
Write User Configuration Page command, and erased block-wise by the Erase User
Configuration Block command. User configuration blocks UCB0 and UCB1 can be
programmed/erased during TC1796 device life-time only up to 4 times. UCB2 can be
programmed only once.
Table 7-16 defines the contents of the three UCBs.

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Table 7-16 Layout of User Configuration Blocks

UCB Page Address Byte(s) Content
UCB0 UCP0 A000 0000H [1:0] Protection configuration bits (content as
defined for PROCON0)
A000 0008H [9:8] Copy of bytes [1:0]
A000 0010H [19:16] First 32-bit keyword of user 0
A000 0014H [23:20] Second 32-bit keyword of user 0
A000 0018H [27:24] Copy of first 32-bit keyword of user 0
A000 001CH [31:28] Copy of second 32-bit keyword of user 0
– others Must be programmed to 00H
UCP1 – all This page is reserved for future
purposes; must be programmed to 00H
UCP2 A000 0200H [3:0] 32-bit confirmation code: 8AFE15C3H
A000 0208H [11:8] Copy of 32-bit confirmation code
– others Must be programmed to 00H
UCP3 – all This page is reserved for future
purposes; must be programmed to 00H
UCB1 UCP4 A000 0400H [1:0] Protection configuration bits (content as
defined for PROCON1)
A000 0408H [9:8] Copy of bytes [1:0]
A000 0410H [19:16] First 32-bit keyword of user 1
A000 0414H [23:20] Second 32-bit keyword of user 1
A000 0418H [27:24] Copy of first 32-bit keyword of user 1
A000 041CH [31:28] Copy of second 32-bit keyword of user 1
– others Must be programmed to 00H
UCP5 – all This page is reserved for future
purposes; must be programmed to 00H
UCP6 A000 0600H [3:0] 32-bit confirmation code: 8AFE15C3H
A000 0608H [11:8] Copy of 32-bit confirmation code
– others Must be programmed to 00H
UCP7 – all This page is reserved for future
purposes; must be programmed to 00H

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Table 7-16 Layout of User Configuration Blocks (cont’d)

UCB Page Address Byte(s) Content
UCB2 UCP8 A000 0800H [1:0] Protection configuration bits (content as
defined for PROCON2)
A000 0808H [9:8] Copy of bytes [1:0]
– others Must be programmed to 00H
UCP9 – all This page is reserved for future
purposes; must be programmed to 00H
UCP10 A000 0600H [3:0] 32-bit confirmation code: 8AFE15C3H
A000 0608H [11:8] Copy of 32-bit confirmation code
– others Must be programmed to 00H
UCP11 – all This page is reserved for future
purposes; must be programmed to 00H

The protection configuration bits that are located in the first two bytes of the UCBs
determine the requested protection configuration as it is defined for bits [15:0] of the
Flash Protection Configuration registers PROCON0, PROCON1, and PROCON2. When
a read/write protection has been installed for an user configuration block, the content of
its first two bytes is copied into the corresponding Flash Protection Configuration
register.

UCB Configuration, Confirmation and Activation

In order to set up a UCB correctly, several steps must be done to avoid incorrect and
inoperable UCB contents and, as a result, unrepairable read/write protection.
There are three main tasks to execute for UCB setup:
1. Configuration of a UCB
This step includes the programming of the first page of a UCB by executing a User
Configuration Page command. This first page determines the protection type and the
two 32-bit keywords. Unused bytes in the first page of the UCB must be programmed
with 00H.
2. Confirmation of the Keywords
The 32-bit confirmation code word, which is located in the third page of a UCB,
should be programmed only after a check of the correct programming of the two
32-bit keywords. Reason: wrong keywords in a UCB can never be retrieved (because
UCBs are not readable), and a confirmed read or write protection cannot be disabled
and changed anymore when the password check (see Page 7-33) always fails.
The check for correct keywords in a UCB requires to execute a reset operation (e.g.
software reset) after the configuration has been setup as described under point 1.
After the reset, the protection is not fully activated because the confirmation code in

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the UCB is still not valid but it is already configured. After issuing a Disable Read
Protection or Disable Write Protection command (depending on the configured
protection type) with the expected passwords, the status flag FSR.PROER indicates,
whether password checking was ok or not.
If PROER = 0 after the Disable Read Protection or Disable Write Protection
command, the password check was ok, meaning that the keywords in the UCB are
identical with the passwords that have been transmitted with the command. Now the
32-bit confirmation code word must be still programmed into the third page of the
UCB by the Write User Configuration Page command. Unused bytes of the third page
of the UCB should be programmed with 00H. After that operation, the selected
protection is defined to be “installed”.
If PROER = 1 after the Disable Read Protection or Disable Write Protection
command, the password check was negative. In this case (and if the correct
passwords are not known), the related UCB has to be erased again and the UCB
setup must be repeated as described under point 1.
3. Activation of an Installed Protection
When a read or write protection has been installed, it can only be activated by
executing any reset operation. After this reset operation, an installed protection
becomes “active”.

7.2.7.2 Write and OTP Protection for PFLASH

Write protection is a feature that must be installed by the user of the TC1796 device. In
the delivery state of the TC1796, no write protection is installed meaning that the UCBs
are in erased state. If sector write protection is active for a PFLASH sector, erasing and
programming of this sector is only possible if the corresponding UCB keywords are
known.
OTP write protection can be installed and enabled for a PFLASH sector only once after
the TC1796 delivery state. Write protection configuration for a PFLASH sector can be
modified by erasing and re-programming of the related UCB.
The sector write protection configuration must be initially programmed into one of the
three UCBs by using the Write User Configuration Page command. With this command,
the user determines the PFLASH sector(s) to be write-protected and two 32-bit keywords
which are required to temporarily disable an already installed write protection
configuration or to temporarily disable an active sector write protection. Erasing and
reprogramming of UCB0 or UCB1 can be performed up to 4 times during TC1796 device
lifetime.
As described above on Page 7-29, sector write protection remains active as long as no
Disable Write Protection command is issued. Within this command sequence, the user
has to identify itself by its passwords and its user level (UL, see command sequence
definition). After the Disable Write Protection command, sector write protection is
temporarily disabled for all sectors that belong to the user. Thereby, disabling of write

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protection is hierarchically controlled. This means, if user 0 (assigned to UCB0) disables

write protection for his sector(s), also write protection for user 1 (assigned to UCB1) is
disabled but not vice versa (user 1 can only disable his own protected sectors).
Note: Sector specific write protection may be combined with read protection. In this
case, after execution of the Disable Sector Write Protection command the
protected sectors are only unlocked if read protection is also disabled.
Resumption of the temporarily disabled write protection (and read protection) is done by
sending the Resume Protection command or by executing a reset operation. For UCB2,
disabling write protection and thus re-programming is not possible.
The configuration of an installed write protection is indicated by:
• Three status flags FSR.WPROINx (x = 0-2) that indicate whether sector write
protection is installed for UCBx or not
• Status flag FSR.PROIN = 1; this bit is set coincidently with FSR.WPROINx
• Status flags SnL (n = 0-12) in the three Protection Configuration registers PROCONx
(x = 0-2) that indicate which Flash sectors are write-protected by UCBx
• The state of a write protection (enabled or temporarily disabled) is indicated by bits
FSR.WPRODIS0 (for UCB0) and FSR.WPRODIS1 (for UCB1).
After the execution of an Erase User Configuration Block command, which requires the
preceding disabling of an active write protection by the Disable Write Protection
command, all keywords and all protection parameters in the UCB are erased. Thus, the
UCB is totally unprotected until it becomes re-programmed. The only exception is UCB2,
which can never be erased after installation of OTP write protection.
If global write protection is additionally installed (implicitly with an installed read
protection), a Disable Read Protection command must be issued before the write
protection configuration parameters in UCB0 can be modified by user 0.
Note: All PFLASH sectors can be write-protected or OTP-protected, separately for all
three users. DFLASH sectors cannot be separately write-protected (only generally
via Read Protection).

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7.2.7.3 Read Protection for PFLASH and DFLASH

When read protection is active, read accesses from PFLASH and DFLASH memory
locations are generally disabled, if code execution is not started from internal Flash after
reset. Additionally, a global write protection is always active for a read-protected
PFLASH and DFLASH. This feature supports a protection against trojan horse
programs. Note that read protection cannot be activated separately for PFLASH and
DFLASH.
Read protection is installed only via UCB0. At programming of UCB0, the highest bit of
its second byte (corresponds to bit PROCON0.RPRO, see Page 7-59) must be set.
After the configuration and confirmation of UCB0 (see Page 7-29), read protection is
installed but still not active. After the following reset operation, the installed read
protection becomes really active. It remains active as long as no Disable Read
Protection command is issued. This command is password-protected and the user must
provide the two passwords for temporarily disabling the read protection. This mechanism
assures, that an installed read protection configuration can only be changed (e.g.
disabled) by an user which has knowledge about the two keywords that have been
initially programmed into the UCB. After the Disable Read Protection command, the read
protection configuration as defined in UCB0 can be changed (after erasing UCB0), if not
coincidently sector write protection is installed by the user 0 (in this case, also sector
write protection must be disabled). A temporarily disabled read protection can be re-
enabled by sending the Resume Protection command, or by executing a reset operation.
Read protection can be combined with sector specific write protection. In this case, after
execution of the Disable Read Protection command, only those sectors are unlocked for
write accesses, which are not separately write-protected.
The status of a correctly installed read protection is indicated by:
• Status flag FSR.RPROIN = 1; this bit becomes updated after a reset operation (when
the Boot ROM code has been left) and when read protection has been configured.
• Status flag PROCON0.RPRO = 1; indicates an installed (and confirmed) read
protection as programmed in the protection configuration bits of UCB0.
• Read protection active flag FCON.RPA; indicates the state of an installed read
protection (active or temporarily disabled).
There are also two Flash access disable bits in register FCON, DCF (= Disable Code
Fetch) and DDF (= Disable Data Fetch), which control the Flash access during an active
read protection. During execution of the Boot ROM program (see Page 4-18) with read
protection, the following three locations for program code execution can be selected:
• Case 1: code execution from internal PFLASH
• Case 2: code execution from internal program memory after execution of a bootstrap
loader
• Case 3: code execution from external program memory via EBU

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With a reset operation, the FCON register bits DCF and DDF are set. When starting code
execution from internal PFLASH, these flags become cleared by the Boot ROM program
before Boot ROM exit. This means that code execution from PFLASH and data read
accesses from PFLASH or DFLASH is generally allowed. The program code, which
executes the data read accesses from Flash, can be located in any program memory.
When starting from internal or external program RAM (case 2 and 3), flags DCF and DDF
remain set at Boot ROM exit. This means, that code execution from PFLASH and data
read access from PFLASH or DFLASH is disabled. In this case, code or data accesses
from PFLASH or DFLASH are only possible while read protection is temporarily disabled
by the password protected Disable Read Protection command (FCON.RPA is cleared).
In this disable state, it is also possible to clear the DCF/DDF flags of register FCON.
Flash data accesses from dedicated bus masters others than the CPU/DMI can be
disabled separately with FCON register bits DDFDBG, DDFDMA, and DDFPCP of
register FCON. When such a bit is set, the corresponding bus master (Debug system,
DMA controller, or PCP) is not allowed to access PFLASH or DFLASH memory. When
these bits are set once, they can only be cleared again when read protection is not
selected at all (inactive), or temporarily disabled.
Note: The debug interface is disabled after Boot ROM exit with read protection.

7.2.7.4 Password Check Control

The Disable Write Protection command and the Disable Read Protection command
provide a protected command sequence, meaning that two 32-bit passwords must be
issued within the command. Both commands are executed only if the two passwords are
identical with the two keywords that are stored in the corresponding user configuration
block. If one or both passwords are not identical to their related keywords, the protected
sectors remain in the locked state (read- and/or write-protected) and the protection error
flag FSR.PROER is set. In this case, a new Disable Write Protection command or a
Disable Read Protection command is only accepted after the next TC1796 reset
operation.
Note that the Disable Write Protection command can be applied for user 0 (UCB0) or
user 1 (UCB1). The Disable Read Protection command can be applied only for user 0
(UCB0).

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7.2.8 Error Correction and Margin Control

7.2.8.1 Dynamic Error Correction

Error detection and correction are controlled in the Flash module by using a SECDED
algorithm. This algorithm calculates an 8-bit error correction code (ECC) for every 64-bit
data portion in PFLASH and DFLASH. This 8-bit ECC is generated during write
operations to the assembly buffer and programmed into the Flash array together with the
assembly buffer data during the execution of the Write Page command. With every 64-bit
read access from PFLASH and DFLASH, the associated 8-bit ECC is fetched and
checked whether it is correct or not.
The ECC is defined such that an 8-bit ECC of 00H is generated for 64-bit data portions
with all bits set at 0. Therefore, after an erase operation all Flash locations including the
ECCs are at logical 0, meaning that the Flash is erased with correct ECC information.
On the other hand, an ECC of FFH is generated when all bits of a 64-bit data portion are
programmed with a 1.
In general, the TC1796 Flash module supports the following error detection and
correction functionality for PFLASH and DFLASH read accesses:
• Single-bit error detection within 64-bit read data with on-the-fly correction
– Status flag indication for PFLASH (FSR.PFSBER) and DFLASH (FSR.DFSBER)
single-bit errors
– Optional single-bit error Flash interrupt generation for PFLASH and DFLASH
• Double-bit error detection (no correction)
– Status flag indication for PFLASH (FSR.PFDBER) and DFLASH (FSR.DFDBER)
double-bit errors
– Optional double-bit error Flash interrupt generation for PFLASH and DFLASH
– In double-bit error case, the CPU/PCP can be interrupted by a PLMB bus error
which further results in an interrupt from the PLMB bus control unit PBCU.
This PLMB bus error interrupt can be disabled e.g. for margin check purposes.
A single-bit or a double-bit error may also be caused by a disturbed ECC with correct
64-bit data, or by a wrong selection of internal Flash access time with wait states.
Note: After the detection of a single-bit error it is generally recommended to execute a
margin check procedure (described in the next section) and, as a result of this
check, to erase the violated sector and reprogram it completely new (to avoid
double-bit errors).

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7.2.8.2 Margin Check Control

The margin control feature of the TC1796 Flash module makes it possible to change the
sensing levels of the sense amplifiers of the Flash array bit lines for read operations. With
this feature, problematic Flash array bits can be found in advance, before they convert
to stable erratic bits. Margin control is supported separately for PFLASH and DFLASH.
Two Margin Control Registers, MARP for PFLASH and MARD for DFLASH, are provided
to adapt the margin levels. Two margin levels, standard or high margin level, are
selectable for 0 or 1 level detection. Standard margin levels are selected as default after
reset.
Since problematic Flash array bits always change their value from a valid 1 to an invalid
0 level, these bits can be identified and corrected in advance by executing the following
steps:
1. Checking the high-level margin by setting bit field MARGIN1 in the MARP or MARD
register to 01B (high margin selected) and MARGIN0 to 00B (standard margin
selected).
2. Reading related Flash memory locations while observing the single-bit and double-
bit Flash interrupts; if an error occurs, executing an erase and reprogramming of the
corresponding sector.
A zero check (analogous procedure as shown in steps 1 and 2 for programmed cells) is
normally not necessary, because the energetically stabilized state of Flash cells is close
to the zero-state.
Only one high margin level (high or standard level, either for PFLASH or DFLASH) is
allowed at a time. During erase or programming operations only the standard margin
selections are allowed.
Attention: To increase the security and to inhibit unintended write accesses to the
MARP register, the standard “ENDINIT” protection feature (including
watchdog password access control) should be used for write accesses
to the MARP register (for PFLASH). Using this mechanism, it is
possible to change the read margins of the PFLASH only before End-
of-initialization or after ENDINIT with valid password access to register
WDT_CON0. The MARD register for Data Flash is not especially
protected.
Note: After changing a margin level in the MARP or MARD registers, a wait time of 10 µs
must elapse before Flash read operations with the modified margin can be
executed.

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7.2.9 Flash Interrupt Generation and Control

One interrupt request can be issued by the Flash module. The related interrupt control
register is located in the DMA controller.
The Flash interrupt can be issued when any of the following events occur:
• End-of-busy: programming or erase operation of Flash bank finished
• Command sequence error
• Protection error
• Single-bit error in PFLASH
• Single-bit error in DFLASH
• Double-bit error in PFLASH
• Double-bit error in DFLASH
The source of the Flash interrupt is indicated in the Flash Status Register FSR by the
corresponding busy and error flags. Every interrupt source is disabled after reset, and
can be enabled individually via dedicated enable bits in the Flash Configuration Register
FCON.
The end-of-busy interrupt becomes active whenever a programming or erasing
operation is finished. At this event, one of the three FSR busy flags PBUSY, D0BUSY,
or D1BUSY is cleared from 1 to 0. End-of-busy interrupts are enabled by setting the
FCON.EOBM bit.
The error flags in the Flash Status Register are controlled independently of the interrupt
configuration as defined in the FCON register. Thus, they may be polled without interrupt
support. When set, an error flag has to be cleared by the user with the Clear Status
command. All error flags are also cleared with any reset.
Errors, which are caused by a reset during program or erase operation, are not indicate,
but its detection is supported via the PROG and ERASE flags in the Flash Status
Register FSR. These two flags are cleared only with a power-on reset. Therefore, it is
possible to detect an aborted Flash operation, if after every terminated Flash operation
these flags are immediately cleared by the user with the Clear Status command, and if
these flags are checked with every user-boot after reset (all except power-on reset).

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FSR FCON
End-of-Busy
PBUSY Conditions EOBM

FSR
Edge
D0BUSY
Detection
FSR
D1BUSY FSR FCON
SQER PROER SQERM PROERM

Set Set
Command Sequence
Error
Protection
Error ≥1

FSR FCON
DFSBER PFSBER DFSBERM PFSBERM

Set Set
DFLASH Single Bit FLASH
Error Interrupt
PFLASH Single Bit
Error

FSR FCON
DFDBER PFDBER DFDBERM PFDBERM

Set Set
DFLASH Double Bit
Error
PFLASH Double Bit
Error
MCA05646

Figure 7-6 Flash Service Request Control

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7.2.10 Flash Power Supply, Power Saving and Reset

This section describes some power supply, power saving mode, and reset related issues
of the Flash modules.

7.2.10.1 Power Supply

The TC1796 Flash module has a separate 3.3 V power supply line VDDFL3. It is used to
generate on-chip regulated voltages for the program and erase operations, as well as for
read operations.
If a power-fail occurs during a Flash erase or programming operation, a proper control
of the PORST input is required to avoid a possibly destructive operation (see Data Sheet
for details of power-fail control).

7.2.10.2 Sleep Mode

The TC1796 Flash module provides a sleep mode which makes it possible to reduce the
power consumption of the Flash module. Flash sleep mode is only entered if the Flash
module is in idle state with all pending or active operations processed and terminated.
Only in this case, the Flash module executes a ramp-down into Flash sleep mode. In
Flash sleep mode, all sense amplifiers are switched off, the internal voltages are ramped
down, and the Flash array oscillator is switched off. Next, status flag FSR.SLM is set
indicating an active Flash sleep mode.
Flash sleep mode can be initiated by software (separately from the other modules in the
TC1796) by setting bit FCON.SLEEP.
Flash sleep mode can also be initiated by hardware when the sleep mode is initiated by
the power management system of the TC1796 (see Section 5.1 on Page 5-2). A
TC1796 device sleep mode request affects the Flash module only if the external sleep
request disable bit FSR.ESLDIS is not set.
Wake-up from Flash sleep mode is initiated by clearing bit FCON.SLEEP or when the
device sleep mode signal from the power management system is released. In both
cases, the wake-up from sleep mode is controlled in the Flash module by starting the
Flash array oscillator again, ramping-up the internal voltages, and returning to read
mode. When again in read mode, also status flag FSR.SLM becomes cleared.
During ramp-down, active sleep mode, and wake-up from Flash sleep mode to active
mode, the Flash reports to be busy also by setting the bits FSR.PBUSY, FSR.D0BUSY,
and FSR.D1BUSY.

7.2.10.3 Shut-Down Mode

The Flash module can also be put into a shut-down mode in which it is switched off
completely and cannot be used at all. This shut-down mode is not available for a user

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program but controlled by the Boot ROM startup procedure that is executed after each
reset operation.

7.2.10.4 Reset Control

The Flash module uses
• The system reset, which is represented by the fast LMB reset; this reset includes all
reset sources (power-on, hardware, software and watchdog reset), and
• The power-on reset.
The Flash will be automatically reset to Read Mode within 900 µsec (including Flash
ramp-up) after every reset represented by the system reset. When that happens, any
erase or programming operation that is running is aborted, and the Flash might have
erroneous data in the location being operated on (thus, the aborted operation must be
repeated). Such an aborted state can be detected by careful handling of the PROG and
ERASE flags in FSR.
Note: The startup time after reset until the first user instruction includes the Flash ramp-
up and the Boot ROM startup, and depends on the reset type (cold or warm) and
on the clock frequency (PLL free-running or application frequency). But for all
cases and fCPU > 12 MHz, it is < 1.5 msec.

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7.2.11 Flash Registers

FLASH Register Overview

Identification Status/ Control Margin Control Protection Configuration

Register s Register Registers Registers

FLASH_ID FLASH_FSR FLASH_MARP FLASH_PROCON0

FLASH_FCON FLASH_MARD FLASH_PROCON1
PMU_ID DMA_SYSSRC1 FLASH_PROCON2
MCA05647_mod

Figure 7-7 Flash Registers

The complete and detailed address map of the FLASH registers is described in
Table 18-36 on Page 18-117 of the TC1796 User’s Manual System Units part
(Volume 1).

Table 7-17 Registers Address Space -Flash Registers

Module Base Address End Address Note
FLASH F800 1000H F800 23FFH –
PMU F800 0500H F800 05FFH –

Table 7-18 Registers Overview - Flash Registers

Register Short Register Long Name Offset Description
Name1) Address see
FLASH_ID Flash Module Identification Register 1008H Page 7-41
FLASH_FSR Flash Status Register 1010H Page 7-43
FLASH_FCON Flash Configuration Register 1014H Page 7-53
FLASH_MARP Flash Margin Control Register PFLASH 1018H Page 7-51
FLASH_MARD Flash Margin Control Register DFLASH 101CH Page 7-52
FLASH_PROCON0 Flash Protection Config. Reg. User 0 1020H Page 7-59
FLASH_PROCON1 Flash Protection Config. Reg. User 1 1024H Page 7-60
FLASH_PROCON2 Flash Protection Config. Reg. User 2 1028H Page 7-61
2)
DMA_SYSSRC1 DMA System Interrupt Service Request Page 12-108
Control Register 1

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1) The Flash register short names are also referenced in other parts of this chapter without the module prefix
name “FLASH_”.
2) This register is located in the address range for the DMA controller.

7.2.11.1 Flash and PMU Module Identification Registers

The Flash Module Identification Register ID contains read-only information about the
Flash module version.

FLASH_ID
FLASH Module Identification Register(1008H) Reset Value: 0031 C0XXH
31 16 15 8 7 0

MODNUM MODTYPE MODREV

r r r

Field Bits Type Description

MODREV [7:0] r Module Revision Number
MODREV defines the module revision number. The value
of a module revision starts with 01H (first revision).
MODTYPE [15:8] r Module Type
This bit field defines the module as a 32-bit module: C0H
MODNUM [31:16] r Module Number Value
This bit field defines the module identification number for
the FLASH: 0031H

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The PMU Module Identification Register ID contains read-only information about the
PMU module version.

PMU_ID
PMU Module Identification Register
(08H) Reset Value: 002E C0XXH
31 16 15 8 7 0

MODNUM MODTYPE MODREV

r r r

Field Bits Type Description

MODREV [7:0] r Module Revision Number
MODREV defines the module revision number. The value
of a module revision starts with 01H (first revision).
MODTYPE [15:8] r Module Type
This bit field defines the module as a 32-bit module: C0H
MODNUM [31:16] r Module Number Value
This bit field defines the module identification number for
the PMU: 002EH

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7.2.11.2 Flash Status Register

The read-only Flash Status Register indicates the overall status of the Flash module. It
includes busy, program, erase, error, protection, and sleep mode flags.

FLASH_FSR
Flash Status Register (1010H) Reset Value: 0XXX X0X0H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W W W W R R
PRO
VER 0 SLM 0 PRO PRO 0 PRO PRO PRO 0 PRO PRO 0
IN
DIS1 DIS0 IN2 IN1 IN0 DIS IN
rh r rh r rh rh r rh rh rh r rh rh r rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DF PF DF PF DF PF DF PF D1 D0 FA P
PRO SQ ERA PR
DB DB SB SB OP OP PA PA BU BU BU BU
ER ER SE OG
ER ER ER ER ER ER GE GE SY SY SY SY
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh

Field Bits Type Description

PBUSY 0 rh PFLASH Busy
This flag indicates the busy state of the PFLASH
during program or erase operations. It also indicates
when the PFLASH is not in Read Mode, e.g. in ramp-
up state. PBUSY is cleared by any reset operation.
0B PFLASH is ready and in Read Mode.
(default after reset)
1B PFLASH is busy (program, erase, ramp-up, or
in sleep mode) and it is not in Read Mode.
FABUSY 1 rh Flash Array Busy
This status flag is a flag for test purposes that should
not be used by software drivers. It indicates whether
any of the Flash arrays is in busy state. FABUSY is
cleared by any reset operation.
0B Flash array banks are not busy and are in Read
Mode (default after reset).
1B At least one of the Flash array banks or the
whole array is busy (program, erase, ramp-up
or sleep mode). Flash read accesses are not
possible.

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Field Bits Type Description

D0BUSY 2 rh DFLASH Bank 0 Busy
This flag indicates the busy state of DFLASH bank 0
during program or erase operations. It also indicates
when the DFLASH bank 0 is not in Read Mode, e.g.
in ramp-up state. D0BUSY is cleared by any reset
operation.
0B DFLASH bank 0 is ready and in Read Mode.
(default after reset)
1B DFLASH bank 0 is busy (program, erase,
ramp-up or sleep mode) and it is not in Read
Mode.
D1BUSY 3 rh DFLASH Bank 1 Busy
This flag indicates the busy state of DFLASH bank 1
during program or erase operations. It also indicates
when the DFLASH bank 1 is not in Read Mode, e.g.
in ramp-up state. D0BUSY is cleared by any reset
operation.
0B DFLASH bank 1 is ready and in Read Mode.
(default after reset)
1B DFLASH bank 1 is busy (program, erase,
ramp-up or sleep mode) and it is not in Read
Mode.
PROG 4 rh Programming State
This flag indicates whether PFLASH or DFLASH is
currently programmed or have been programmed.
PROG is set with the last cycle of a write page
command. After a programming operation, this bit
remains set. PROG is cleared by a Clear Status
command or by a power-on reset.
0B There is no programming operation running,
requested or finished.
1B A programming operation (write page) is
running, requested or finished.

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Field Bits Type Description

ERASE 5 rh Erase State
This flag indicates whether PFLASH or DFLASH is
currently erased or have been erased. ERASE is set
with the last cycle of an erase command sequence.
After an erase operation this bit remains set. ERASE
is cleared by a Clear Status command or by a power-
on reset.
0B There is no erase operation running,
requested, or finished.
1B An erase operation is running, requested, or
finished.
PFPAGE 6 rh PFLASH in Page Mode
This flag indicates whether the PFLASH is in Page
Mode or not. It is set with the enter Page Mode
command and cleared by a Write Page command, or
by a Reset-to-Read command, or by any reset
operation.
0B PFLASH is not in Page Mode.
(default after reset)
1B PFLASH is in Page Mode. The page assembly
buffer of the PFLASH is ready to be filled.
DFPAGE 7 rh DFLASH in Page Mode
This flag indicates whether the DFLASH is in Page
Mode or not. It is set with the enter Page Mode
command and cleared by a write Page Mode
command, or by a Reset-to-Read command, or by
any reset operation.
0B DFLASH is not in Page Mode.
(default after reset)
1B DFLASH is in Page Mode. The page assembly
buffer of the DFLASH is ready to be filled.
PFOPER 8 rh PFLASH Operation Error
This flag indicates a flash array error during PFLASH
operation. PFOPER is cleared by a reset operation,
by a Reset-to-Read command, or by a Clear Status
command.
0B PFLASH operation is finished or currently
running without error.
1B PFLASH operation is aborted caused by a
PFLASH array failure.

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Field Bits Type Description

DFOPER 9 rh DFLASH Operation Error
This flag indicates a flash array error during DFLASH
operation. DFOPER is cleared by a reset operation,
by a Reset-to-Read command, or by a Clear Status
command.
0B DFLASH operation is finished or currently
running without error.
1B DFLASH operation is aborted caused by a
DFLASH array failure.
SQER 10 rh Command Sequence Error
This flag indicates a command sequence error.
SQER is cleared by a Reset-to-Read command, or by
a Clear Status command, or by any reset operation.
SQER is not set when a command sequence is
aborted by a Reset-to-Read command.
0B No command sequence error has occurred.
(default after reset)
1B An invalid command sequence has been
detected (command is not executed).
PROER 11 rh Protection Error
This flag indicates a protection error. Such an error is
a command that is not allowed, for example an erase
sector or write page command addressing a locked
sector. It also indicates when wrong passwords are
used in disable read or disable write protection
commands. PROER is cleared by a Reset-to-Read
command, or by a Clear Status command, or by any
reset operation.
0B No protection error has occurred.
(default after reset)
1B A protection error has occurred.
PFSBER 12 rh PFLASH Single-Bit Error and Correction
This flag indicates the occurrence of a single-bit error
in the PFLASH that has been corrected. PFSBER is
cleared by a Reset-to-Read command, or by a Clear
Status command, or by any reset operation.
0B No error has been detected.
(default after reset)
1B A single-bit error in PFLASH has been detected
and corrected.

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Field Bits Type Description

DFSBER 13 rh DFLASH Single-Bit Error and Correction
This flag indicates the occurrence of a single-bit error
in the DFLASH that has been corrected. DFSBER is
cleared by a Reset-to-Read command, or by a Clear
Status command, or by any reset operation.
0B No error has been detected.
(default after reset)
1B A single-bit error in DFLASH has been detected
and corrected.
PFDBER 14 rh PFLASH Double-Bit Error
This flag indicates the occurrence of a double-bit
error in the PFLASH. PFDBER is cleared by a Reset-
to-Read command, or by a Clear Status command, or
by any reset operation.
0B No error has been detected.
(default after reset)
1B A double-bit error in PFLASH has been
detected.
DFDBER 15 rh DFLASH Double-Bit Error
This flag indicates the occurrence of a double-bit
error in the DFLASH. DFDBER is cleared by a Reset-
to-Read command, or by a Clear Status command, or
by any reset operation.
0B No error has been detected.
(default after reset)
1B A double-bit error in DFLASH has been
detected.
PROIN 16 rh Protection Installed
This flag indicates whether read or/and write
protection is correctly installed. This bit is updated
only if a modified protection installation is detected at
a reset operation.
0B No protection is installed.
1B A read or/and write protection is correctly
installed.

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Field Bits Type Description

RPROIN 18 rh Read Protection Installed
This flag indicates whether read protection is
correctly installed. This bit is updated only if a
modified read protection installation is detected at a
reset operation.
0B No read protection installed.
1B Read protection is correctly installed.
RPRODIS 19 rh Read Protection Disable State
This flag indicates whether read protection is
temporarily disabled. RPRODIS is cleared by any
reset operation and by the Resume Protection
command.
0B The read protection is installed and enabled, or
it is not installed (default after reset).
1B The read and global write protection is
temporarily disabled. External Flash read as
well as programming or erase on not separately
write-protected sectors is possible.
WPROIN0 21 rh UCB0 Write Protection Installed
This flag indicates whether sector write protection in
UCB0 is correctly installed and confirmed. This bit is
updated only if a modified UCB0 protection
installation is detected at a reset operation.
0B No write protection installed in UCB0.
1B Sector write protection is correctly installed in
UCB0.
WPROIN1 22 rh UCB1 Write Protection Installed
This flag indicates whether sector write protection in
UCB1 is correctly installed and confirmed. This bit is
updated only if a modified UCB1 protection
installation is detected at a reset operation.
0B No write protection installed in UCB1.
1B Sector write protection is correctly installed in
UCB1.

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Field Bits Type Description

WPROIN2 23 rh UCB2 Write Protection (OTP) Installed
This flag indicates whether sector write protection
(OTP) in user configuration block UCB2 is correctly
installed and confirmed.
0B No OTP write protection installed in UCB2.
1B Sector write protection correctly installed in
UCB2. The protection is permanently locked.
WPRODIS0 25 rh UCB0 Write Protection Disabled
This flag indicates whether PFLASH sectors that are
write-protected by user configuration block UCB0 are
temporarily unlocked. WPRODIS0 is cleared by any
reset operation and by the Resume Protection
command.
0B All write-protected sectors of UCB0 are locked
or write protection is not installed in UCB0.
1B All write-protected sectors of UCB0 and UCB1
are temporarily unlocked. The programming or
erasing of UCB0 is possible if no read
protection is installed.
Hierarchical protection levels: Unlock state of user-
level zero also includes sectors, that are protected by
user 1.
WPRODIS1 26 rh UCB1 Write Protection Disabled
This flag indicates whether PFLASH sectors that are
write-protected by UCB1 are temporarily unlocked.
WPRODIS1 is cleared by any reset operation and by
the Resume Protection command.
0B All write-protected sectors of UCB1 are locked
or write protection is not installed in UCB1.
1B All write-protected sectors of UCB1 are
temporarily unlocked if not globally (read
protection) or concurrently (write protection)
locked by UCB0/UCB2. The programming or
erasing of UCB1 is possible.
SLM 28 rh Flash Sleep Mode
This flag indicates whether the Flash module is in
sleep mode. SLM is cleared by any reset operation or
when Flash sleep mode is left.
0B Flash is not in sleep mode (default after reset).
1B Flash is in sleep mode.

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Program Memory Unit

Field Bits Type Description

VER 31 rh Verify Error
This flag indicates whether a Flash page has been
correctly programmed. VER is cleared by any reset
operation and by the Clear Status command.
0B A Flash page is correctly programmed. All
programmed 1 bits have a full quality.
1B A Flash page programming verify error has
been detected. A correction of weak bits by the
programming algorithm was unsuccessful
during the last programming operation.
Note: There is no interrupt generated when VER is
set.
0 17, 20, r Reserved
24, 27, Read as 0.
[30:29]

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System Units (Vol. 1 of 2)
Program Memory Unit

7.2.11.3 Margin Control Registers

The Margin Control Registers for Program Flash (MARP) and for Data Flash (MARD) are
defined as follows:

FLASH_MARP
Flash Margin Control Register PFLASH
(1018H) Reset Value: 0000 8000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR
MARGIN MARGIN
AP 0
1 0
DIS
rw r rw rw

Field Bits Type Description

MARGIN0 [1:0] rw PFLASH Margin Selection for Low Level
00B Standard margin selected
01B High margin for 0 (low) level selected
10B Reserved
11B Reserved
MARGIN1 [3:2] rw PFLASH Margin Selection for High Level
00B Standard margin selected
01B High margin for 1 (high) level selected
10B Reserved
11B Reserved
TRAPDIS 15 rw PFLASH Double-Bit Error LMB Bus Error Disable
0B If a double-bit error occurs in PFLASH, a bus
error at PLMB or DLMB is generated.
1B If a double-bit error occurs in PFLASH, no LMB
bus error is generated.
After Boot ROM exit, double-bit error traps are enabled
(TRAPDIS = 0).
0 [14:4], r Reserved
[31:16] Read as 0; should be written with 0.

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Program Memory Unit

FLASH_MARD
Flash Margin Control Register DFLASH
(101CH) Reset Value: 0000 8000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR
BNK MARGIN MARGIN
AP 0
SEL 1 0
DIS
rw r rw rw rw

Field Bits Type Description

MARGIN0 [1:0] rw DFLASH Margin Selection for Low Level
00B Standard margin selected
01B High margin for 0 (low) level selected
10B Reserved
11B Reserved
MARGIN1 [3:2] rw DFLASH Margin Selection for High Level
00B Standard margin selected
01B High margin for 1 (high) level selected
10B Reserved
11B Reserved
BNKSEL 4 rw DFLASH Bank Selection
0B DFLASH bank 0 selected for margin control
1B DFLASH bank 1 selected for margin control
TRAPDIS 15 rw DFLASH Double-Bit Error DLMB Bus Error Disable
0B If a double-bit error occurs in DFLASH, a DLMB
bus error is generated.
1B If a double-bit error occurs in DFLASH, no
DLMB bus error is generated.
After Boot ROM exit, double-bit error traps are enabled
(TRAPDIS = 0).
0 [14:5], r Reserved
[31:16] Read as 0; should be written with 0.

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 TC1796
System Units (Vol. 1 of 2)
Program Memory Unit

7.2.11.4 Flash Configuration Register

The Flash Configuration Register FCON controls general Flash configuration functions:
• Number of internal wait states for Flash accesses (without or with word-line hit)
• Indication of installed and active read protection
• Instruction and data access control for read protection
• Interrupt enable/mask bits
• Power reduction and shut-down control
FCON is an Endinit-protected register. The reset value of register FCON as indicated
below shows the value after ramp-up and after execution of the startup procedure out of
Boot ROM.

FLASH_FCON
Flash Configuration Register (1014H) Reset Value: 000X 0636H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DF PF DF PF
EOB PRO SQ DDF DDF DDF
DB DB SB SB 0 DDF DCF RPA
M ERM ERM PCP DMA DBG
ERM ERM ERM ERM
rw rw rw rw rw rw rw r rw rw rw rwh rwh rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WS WS
SL ESL WS WS WS
0 EC 0 EC
EEP DIS DFLASH WLHIT PFLASH
DF PF
rw rw r rw rw r rw rw rw

Field Bits Type Description

1)
WSPFLASH [2:0] rw Wait States for PFLASH Read Access
This bit field determines the number of internal wait
states that are used for an initial PFLASH read
access.
000B 1 clock cycle wait state selected
001B 1 clock cycle wait state selected
010B 2 clock cycles wait state selected
011B 3 clock cycles wait state selected
100B 4 clock cycles wait state selected
101B 5 clock cycles wait state selected
110B 6 clock cycles wait state selected
(default after reset)
111B 7 clock cycles wait state selected

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System Units (Vol. 1 of 2)
Program Memory Unit

Field Bits Type Description

WSECPF1) 3 rw Wait State for PFLASH Error Correction
This bit determines whether an additional wait state is
inserted for error correction during read accesses to
PFLASH.
0B No additional wait state inserted.
1B One additional wait state inserted for PFLASH
error correction.
If enabled, this wait state is only used for the first
transfer of a burst transfer.
WSWLHIT1) [6:4] rw Wait States for PFLASH Read Access with
Wordline Hit
This bit field determines the number of internal wait
states that are used for an initial read access to the
same word-line (512 byte) of the PFLASH memory as
the last PFLASH access.
000B Reserved
001B Flash read hit access in one clock cycle
010B Hit access in 2 clock cycles
011B Hit access in 3 clock cycles
(default after reset)
100B Hit access in 4 clock cycles
101B Flash access in 5 clock cycles
110B Flash access in 6 clock cycles (default after
Boot ROM exit; see Table 4-4 on Page 4-19)
111B Reserved
WSDFLASH1) [10:8] rw Wait States for DFLASH Read Access
This bit field determines the number of internal wait
states that are used for a DFLASH read access.
000B 1 clock cycle wait state selected
001B 1 clock cycle wait state selected
010B 2 clock cycles wait state selected
011B 3 clock cycles wait state selected
100B 4 clock cycles wait state selected
101B 5 clock cycles wait state selected
110B 6 clock cycles wait state selected
(default after reset)
111B 7 clock cycles wait state selected

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System Units (Vol. 1 of 2)
Program Memory Unit

Field Bits Type Description

WSECDF1) 11 rw Wait State for DFLASH Error Correction
This bit determines whether an additional wait state is
inserted for error correction during read accesses to
DFLASH.
0B No additional wait state inserted.
1B One additional wait state inserted for DFLASH
error correction.
ESLDIS 14 rw External Sleep Request Disable
0B External sleep mode request also requests the
Flash sleep mode.
1B External sleep mode request does not request
the Flash sleep mode.
The external sleep mode is controlled and requested
by the Power Management System of the SCU.
SLEEP 15 rw Flash Sleep Mode Control
This bit controls the Flash sleep mode of the Flash
module.
0B Normal Flash mode or wake-up mode is active.
1B Flash sleep mode is selected.
Flash sleep mode is left (wake-up from sleep) by
clearing the SLEEP bit.
RPA 16 rh Read Protection Activated
This flag indicates the status of the read protection.
0B The read protection is inactive or temporarily
disabled. Bits DCF and DDF can be cleared or
set by software. DCF and DDF are not
evaluated.
1B The read protection is active. Bits DCF and
DDF are evaluated and cannot be cleared by
software.

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 TC1796
System Units (Vol. 1 of 2)
Program Memory Unit

Field Bits Type Description

DCF 17 rwh Disable Code Fetch from Flash Memory
This bit enables/disables the code fetches from the
internal PFLASH memory when read protection is
active. Once set, this bit can only be cleared when
read protection is inactive (RPA = 0).
DCF is automatically set after a reset operation. It is
cleared by hardware in case of internal program start
out of the PFLASH.
0B Code fetches from PFLASH are allowed.
1B Code fetches from PFLASH are not allowed.
DCF is not evaluated when read protection is inactive
(RPA = 0).
DDF 18 rwh Disable Data Fetch from Flash Memory
This bit enables/disables the data read access from
the PFLASH and DFLASH memory when read
protection is active. Once set, this bit can only be
cleared when read protection is inactive (RPA = 0).
DDF is automatically set after a reset operation. It is
cleared by hardware in case of internal program start
out of the PFLASH.
0B Data read access to PFLASH and DFLASH is
allowed.
1B Data read access to PFLASH and DFLASH is
not allowed.
DDF is not evaluated when read protection is inactive
(RPA = 0).
DDFDBG 19 rw Disable Data Fetch from Debug System
This bit enables/disables PFLASH and DFLASH data
read accesses that are initiated by the on-chip debug
system (Cerberus). Once set, this bit can only be
cleared when RPA = 0.
0B Data read accesses from PFLASH/DFLASH
initiated by the debug system are enabled.
1B Data read accesses from PFLASH/DFLASH
initiated by the debug system are disabled.

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System Units (Vol. 1 of 2)
Program Memory Unit

Field Bits Type Description

DDFDMA 20 rw Disable Data Fetch from DMA Controller
This bit enables/disables PFLASH and DFLASH data
read accesses that are initiated by the DMA
controller. Once set, this bit can only be cleared when
RPA = 0.
0B Data read accesses from PFLASH/DFLASH
initiated by the DMA controller are enabled.
1B Data read accesses from PFLASH/DFLASH
initiated by the DMA controller are disabled.
DDFPCP 21 rw Disable Data Fetch from PCP
This bit enables/disables PFLASH and DFLASH data
read accesses that are initiated by the PCP. Once
set, this bit can only be cleared when RPA = 0.
0B Data read accesses from PFLASH/DFLASH
initiated by the PCP are enabled.
1B Data read accesses from PFLASH/DFLASH
initiated by the PCP are disabled.
SQERM 25 rw Command Sequence Error Interrupt Mask
This bit disables/enables the command sequence
error interrupt.
0B Command sequence error interrupt is disabled.
1B Command sequence error interrupt is enabled.
PROERM 26 rw Protection Error Interrupt Mask
This bit disables/enables the protection error
interrupt.
0B Protection error interrupt is disabled.
1B Protection error interrupt is enabled.
PFSBERM 27 rw PFLASH Single-Bit Error Interrupt Mask
This bit disables/enables the PFLASH single-bit error
interrupt.
0B PFLASH single-bit error interrupt is disabled.
1B PFLASH single-bit error interrupt is enabled.
DFSBERM 28 rw DFLASH Single-Bit Error Interrupt Mask
This bit disables/enables the DFLASH single-bit error
interrupt.
0B DFLASH single-bit error interrupt is disabled.
1B DFLASH single-bit error interrupt is enabled.

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 TC1796
System Units (Vol. 1 of 2)
Program Memory Unit

Field Bits Type Description

PFDBERM 29 rw PFLASH Double-Bit Error Interrupt Mask
This bit disables/enables the PFLASH double-bit
error interrupt.
0B PFLASH double-bit error interrupt is disabled.
1B PFLASH double-bit error interrupt is enabled.
DFDBERM 30 rw DFLASH Double-Bit Error Interrupt Mask
This bit disables/enables the DFLASH double-bit
error interrupt.
0B DFLASH single-bit error interrupt is disabled.
1B DFLASH single-bit error interrupt is enabled.
EOBM 31 rw End-of-Busy Interrupt Mask
This bit enables the end-of-busy interrupt.
0B End-of-busy interrupt is disabled.
1B End-of-busy interrupt is enabled.
0 7, r Reserved
[13:12], Read as 0; should be written with 0.
[24:22]
1) These bits and bit fields can be changed at any time, also with code fetched from Program Flash. A modified
wait state parameter will be taken into account with the next corresponding access.

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 TC1796
System Units (Vol. 1 of 2)
Program Memory Unit

7.2.11.5 Protection Configuration Registers

The configuration of read/write protection and OTP functionality is indicated by three
Protection Configuration Registers:
• FLASH_PROCON0 indicates the read/write protection configuration for user 0
(UCB0)
• FLASH_PROCON1 indicates the write protection configuration for user 1 (UCB1)
• FLASH_PROCON2 indicates the OTP write protection for user 2 (UCB2)

FLASH_PROCON0
Flash Protection Configuration Register User 0
(1020H) Reset Value: 0000 XXXXH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 S12L S11L S10L S9L S8L S7L S6L S5L S4L S3L S2L S1L S0L
PRO
rh r rh rh rh rh rh rh rh rh rh rh rh rh rh

Field Bits Type Description

SnL n rh Sector Locked for Write Protection by User 0
(n = 0-12) These bits indicate whether PFLASH sector PSn is
write-protected by user 0 or not.
0B No write protection is installed for PFLASH
sector PSn.
1B Write protection is installed for PFLASH sector
PSn.
RPRO 15 rh Read Protection Configuration
This bit indicates whether read protection is installed
for user 0.
0B No read protection installed
1B Read protection and global write protection is
installed
0 [14:13], r Reserved
[31:16] Read as 0.

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Program Memory Unit

FLASH_PROCON1
Flash Protection Configuration Register User 1
(1024H) Reset Value: 0000 XXXXH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 S12L S11L S10L S9L S8L S7L S6L S5L S4L S3L S2L S1L S0L

r rh rh rh rh rh rh rh rh rh rh rh rh rh

Field Bits Type Description

SnL n rh Sector Locked for Write Protection by User 1
(n = 0-12) These bits indicate whether sector n is write-
protected by user 1 or not.
0B No write protection installed for sector n.
1B Write protection installed for sector n.
0 [31:13] r Reserved
Read as 0.

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Program Memory Unit

FLASH_PROCON2
Flash Protection Configuration Register User 2
(1028H) Reset Value: 0000 XXXXH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 S12L S11L S10L S9L S8L S7L S6L S5L S4L S3L S2L S1L S0L

r rh rh rh rh rh rh rh rh rh rh rh rh rh

Field Bits Type Description

SnL n rh Sector with OTP Protection (User 2)
(n = 0-12) These bits indicate whether OTP protection is
installed and locked for sector n.
0B No OTP protection installed for sector n.
1B OTP protection installed for sector n.
Reprogramming of this sector is no longer
possible.
0 [31:13] r Reserved
Read as 0.

7.3 Emulation Interface

The emulation memory interface shown in Figure 7-1 is always disabled in the TC1796
device. This interface is a 64-bit wide memory interface that controls an emulation
memory in the TC1796 emulation device, called TC1796ED. Segment 8 and 10 reserves
512 Kbyte for the emulation memory interface.
In the TC1796, a CPU read access from the emulation memory region causes a DSE
trap, a PLMB and a DLMB bus error. If the emulation memory region read access is
initiated by a SPB master (e.g. PCP or DMA), additionally a SPB error is generated.
Write accesses to the emulation memory region by any master causes a PLMB bus
error.

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Data Memory Unit

8 Data Memory Unit

The Data Memory Unit (DMU) shown in Figure 8-1 contains a total of 80 Kbyte of fast
static RAM memory:
• 64 Kbyte SRAM memory that can be used as
– Normal data storage
– Overlay memory
– Data Flash mirror memory
• 16 Kbyte of standby memory (SBRAM)
• SRAM and SBRAM are parity protected
• With overlay address generation and control logic, that makes it possible to redirect
data accesses to the PMU-based memories into the DMU or emulation memory.

To/From Data To SCU

Local Memory Bus (DMU Memory Parity Error)

64

DLMB Interface
Slave Master
Parity
DMU Control/Check
64

Overlay Address
Generation &
Control
SRAM VDDRAM
PLMB (LMI) Interface

64 KB
Slave

To
Program 64
DMU
Local
Control
Master

Memory 64
Bus
SBRAM VDDSBRAM
16 KB
VDD

SRAM = Data Memory

DFSRAM = Data Flash shadow RAM
OVRAM = RAM with overlay capability
SBRAM = Stand-by RAM
MCB05648

Figure 8-1 Block Diagram of the Data Memory Unit (DMU)

Note: DMU memories cannot be accessed by the PCP using burst transfers (BCOPY
instruction).

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Data Memory Unit

8.1 DLMB/PLMB Interfaces

The DLMB interface is used for execution of data read write operations to/from the DMU
memories and registers.
The PLMB interface is used when data accesses from internal or external code memory
are redirected to data read accesses from the SRAM memory (data access overlay
capability for calibration purposes).

8.2 SBRAM
The 16 Kbyte SBRAM provides stand-by functionality. It is connected to a separate
power supply pin VDDSBRAM. This power supply pin provides the power for normal
operation of SBRAM, and during power-off state of the TC1796. If VDDSBRAM does not
drop below a specified voltage level in power-down mode (specified in Data Sheet), the
SBRAM will remain its memory content. The switch between regular supply voltage and
power-down mode supply voltage must be done externally.
In order to maintain the memory contents when switching into power-down mode and
coming back from power-down mode, the SBRAM must be locked. This SBRAM lock
mechanism is controlled by the Stand-by SRAM Control Register SBRCTR. When
writing a dedicated pattern into bit fields STBULK and STBSLK, the SBRAM will be
locked. A status flag STBLOCK indicates whether the SBRAM is locked or not. To unlock
the SBRAM, register SBRCTR must be written by three consecutive write operations (for
a detailed description see Page 8-12.
).
If an access to the SBRAM is performed while the SBRAM is locked, an error
acknowledge will be issued as response to the access.

8.3 SRAM
64 Kbyte of fast SRAM are available in the DMU. Besides being used for normal data
storage, this memory can be used to shadow the active portions of the Data Flash and
as overlay RAM for calibration/instrumentation support.
The SRAM can operate as fast mirror memory during Data Flash EEPROM emulation.
In this application, a copy of the active DFLASH region (typically 16 Kbyte) is stored in
the SRAM memory and can be accessed (read/written) very fast. More details about
Data Flash EEPROM emulation are described on Page 7-26.
The SRAM also provides an overlay functionality. During calibration operations, SRAM
memory can be the target of redirected data accesses from internal or external code
memories. The redirection process is described in the following section.

User’s Manual 8-2 V2.0, 2007-07

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System Units (Vol. 1 of 2)
Data Memory Unit

8.4 Parity Protection for DMU Memories

In the TC1796, the SBRAM and SRAM memory blocks of the DMU are equipped with a
parity error detection logic that makes it possible to detect parity errors. In case of a parity
error a NMI is generated.
Note that before using parity protection for SBRAM and SRAM the first time after a
power-on reset operation (before setting the corresponding parity error enable bits), the
corresponding memories must be completely initialized by a user program that writes
every memory location of it once.
More details about the parity control for on-chip memories are described in Section 5.5
on Page 5-37.

8.5 Data Access Overlay Functionality

The DMU overlay functionality provides the capability to redirect data read accesses
from internal or external code memory to data accesses from the DMU SRAM. This
functionality makes it possible, for example, to modify program parameters (which are
typically stored in the code memory) during run time of a program. Instruction fetches are
not affected by the PMU data read access redirection capability. Note that read and write
data accesses from/to code memory are redirected.
The basic overlay scheme is shown in Figure 8-2.

User’s Manual 8-3 V2.0, 2007-07

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 TC1796
System Units (Vol. 1 of 2)
Data Memory Unit

Internal or External
Code Memory DMU Memory

Block Size
(OMASKx)
Overlay
Memory Block x Base Address
(RABRx)
Overlay Target
Target Code Memory
Address
(OTARx)

Redirect

Code Data Data

Fetch Read/ Write Read/ Write
(unaffected) MCA05649

Figure 8-2 Redirection of Data Read Accesses from Code Memory to Internal
Data Memory
In the TC1796, the complete 64 Kbyte SRAM of the DMU can be used as overlay
memory. Sixteen overlay memory blocks within the SRAM with programmable base
address and block sizes are supported, and can be individually enabled for overlay
functionality. The block size of each overlay memory block can be in the range of 2 bytes
up to 512 bytes.
Attention: In the TC1796ED emulation device, it is possible in addition to redirect
code memory data accesses to the emulation memory of the
TC1796ED.

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System Units (Vol. 1 of 2)
Data Memory Unit

There are four overlay RAM control registers (DMU_IOCRn, n = 0-3) assigned to control
the internal overlay functionality. Each register specifies the start address of an
overlayed 2 Kbyte block within the lower 128 Mbytes of segment 10 and 11. This start
address can be placed on any 2 Kbyte boundary within the external code memory, using
bit field OVPTR.
The principal operation of the address translation process is shown in Figure 8-3.

Target Address
4 Bits 28 Bits

Seg Offset

OMASKx
0000 11111 …..111111111 0000 0

Programmable
no match match
Compare

OTARx
TBASE 0

RABRx
OBASE 0

16 Bits (64 KB SRAM)

Redirected Address
C000H OBASE

16 Bits (fix value)

Overlay Memory Block x
Destination Address Base Address Bits
Overlay Memory Block x
Offset Address Bits
MCA05650

Figure 8-3 Address Translation Process

In each enabled overlay block control logic, three registers hold the information to control
the overlay functionality:
• The overlay target address in the Overlay Target Address Register OTARx, which
determines the base address of the code memory data block x to be redirected
• The base address of the overlay memory block in the DMU SRAM in the Redirected
Address Base Register RABRx
• A mask in the Overlay Mask Register OMASKx, defining the size of the block, the
address bits to check for an address match, and which bits are used from the target
address and which from the redirected address base

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Data Memory Unit

The size of the overlay memory blocks can be 2n times the minimal block size (2 byte or
1 Kbyte). The start address of the block can be a integer multiple of the programmed
block size (natural page boundary).
If the overlay block is enabled and the segment address is 8H or AH, the segment offset
of the target address is compared with the target block address of the overlay target
address. This bit-wise comparison is qualified by the content of the mask, ignoring the
address bits that form the offset into the overlayed block.
If there is no match, the original target address is taken to perform the access.
If there is a match:
• The most significant part of the segment offset, that addresses memory sizes beyond
the maximum overlay memory size (64 Kbyte for DMU, 1024 Kbyte for TC1796ED
emulation memory), is set to predefined values according to the address map (fixed
bits in registers RABRx).
• The part of the target block address, that corresponds to the overlay block base
address and is masked, is replaced by the respective overlay block base address bits
(bits OBASE in RABRx, where the corresponding mask bits OMASK in registers
OMASKx are set to “1”).
• The address is completed by the original offset into the block; the number of bits used
are determined by the bits set to “0” in the mask OMASK.

Minimum Block Sizes for DLMB Transactions

The overlay functionality provides the possibility to redirect data accesses with block
sizes of 2 bytes or higher. The redirection is done by a modification of the target address
as shown in Figure 8-3. If the data size of a DLMB transaction in TC1796 is greater than
the selected overlay memory block size, the following behavior will be observed:
• If the address of the DLMB transaction matches the overlay target address, the
complete transaction is redirected, and the complete data (exceeding the block size)
is taken from the overlay memory.
• If the address of the DLMB transaction does not match the overlay target address,
the transaction is not redirected even if the overlay block resides within the
transaction data block.
Therefore, it is recommended not to use DLMB transactions which have a greater data
size as the programmed minimum overlay memory block size (OMASK bit field in
Register OMASKx). This recommendation can, for example, be guaranteed by using a
minimum overlay memory block size of 8 byte.

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Data Memory Unit

8.5.1 Internal Overlay

For internal overlay, the size of the blocks can be 2n, with n = 1 to 9 (2 to 512 byte). Thus
the maximum memory size needed for overlay memory (if all blocks are used with
maximum size) is 8 Kbyte. Only the 64 Kbyte DMU SRAM (not the Stand-by SBSRAM)
can be used as internal overlay memory.
During address translation, the segment number is set to CH.

8.5.2 Emulation Memory Overlay

For Emulation Memory Overlay (only available in the emulation device TC1796ED), the
size of the blocks can be 2n × 1 Kbyte, with n = 1 to 5 (2 Kbyte to 32 Kbyte). Thus, the
maximum memory size needed for overlay memory (if all blocks are used with maximum
size) is 512 Kbyte.

8.5.3 Switching between Internal and Emulation Memory Overlay

When switching a region between internal and external overlay, it has to be ensured that
the respective OVEN bit is cleared, all region parameters are set properly, and then the
region is enabled again. Other wise, unintended access re-directions may occur.

8.5.4 Region Priority

If concurrent matches in more than one region occur, the region with the lowest order
number will win and perform the address translation.

8.5.5 Access Performance

Write Accesses
Write accesses are performed with zero wait states.
If no overlay is enabled, the accesses to the DMU memories take one cycle (1 wait
state). If a pipelined read follows immediately a write, the read will be delayed by an
additional wait state.
If an overlay is enabled, the access to the DMU overlay memory block may be prolonged
by one cycle.
The access to the Emulation Memory will not be more than 10 cycles. Details can be
found in TC1796ED specific documents.

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8.6 Program Local Memory Bus Interface (LMI)

The PLMB (LMI) interface is a unidirectional interface, allowing the DMI/DMU to do data
reads and writes into the PLMB-based modules such as e.g. Flash or EBU space.
Accepted DLMB-to-PLMB bus write transactions are never error acknowledged by the
LMI.
The data phase of a PLMB read transaction will be extended until the data is available.
The LMI will reject any legal transaction that it cannot handle at that particular time (e.g.
when the LMI is busy and a second LMI- related transaction request is requested). Other
DMU memory accesses can be performed in parallel.
LMI transactions may receive error acknowledgments to any transaction. In every case
the LMI responds to error acknowledgments by halting the ongoing transaction that
received the error acknowledge, and dropping this transaction from the LMI PLMB bus
master transaction queue. The PLMB bus is released completely (including LOCK) for a
single cycle before further transactions are processed.

8.6.1 Data Read Buffer

The LMI contains a data read buffer which makes it possible to cache one line of
16 bytes (= 128 bits) of data read from specific memory areas on PMU side.

Read Transactions
When the first read access to cachable memory areas is done, the LMI initiates a 2-beat
burst access on PLMB, requesting 128 bit of data. The start address for the burst is
generated by setting the last 4 bits of the address to 0.
Cachable memory regions for data accesses are:
Segment 8: 8000 0000H - 8FFF FFFFH
In all other memory regions mapped via the LMI, normal non-burst accesses of the
requested data size are initiated and the read data are not stored in the read buffer. The
read data cache buffer content remains unmodified.
For subsequent accesses into cachable memory regions, it is checked, whether the data
is completely contained in the buffer:
• If this is true, the data is extracted out of the buffer without initiating an access to the
PLMB.
• If the data is not contained in the buffer, a new 2-beat burst access is performed to
the PLMB as previously described, and the read data is stored in the buffer.
The requested data can only be extracted after all 128 bits have been read; thus a
cached access will take 1 cycle longer than non-cached access. As the cachable
memory regions are also visible in non-cachable areas (see address map), the user can
map the data dependent on his application to optimize between additional latency and

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subsequent fast accesses for data with high locality, and un-cached faster accesses for
data with low locality.

Write Transactions
When a write transaction hits into the read buffer, the buffer content is invalidated. This
feature also can be used to flush the buffer contents.

Read-Modify-Write Transactions
Read-modify-write transaction always will be forwarded to the PLMB. They will not effect
the buffer content at all (no caching, no invalidation). This implies that read-modify-write
operations should be done to non-cached areas only.

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8.7 DMU Registers

Figure 8-4 shows all registers associated with the DMU.

DMU Registers Overview

General/Control Overlay Registers

Register
ID RABRx
SBRCTR OTARx
x = 0-15 OMASKx
MCA05651_mod

Figure 8-4 DMU Overlay Control Registers

The complete and detailed address map of the PMU module with its registers is shown
in Table 18-37 on Page 18-118 of this TC1796 System Units (Vol. 1 of 2) User’s Manual.

Table 8-1 Registers Address Space - DMU Registers

Module Base Address End Address Note
DMU F801 0100H F801 01FFH –

Table 8-2 Registers Overview PMU Overlay Control Registers

Register1) Register Long Name Offset Description
Short Name Address see
ID Module Identification Register 0008H Page 8-11
RABRx Redirected Address Base Register x 0020H + Page 8-13
(x = 0-15) x × CH
OTARx Overlay Target Address Register x 0020H + Page 8-15
(x = 0-15) x × CH + 4
OMASKx Overlay Mask Register x 0020H + Page 8-16
(x = 0-15) x × CH + 8
SBRCTR Stand-by SRAM Control Register 00E0H Page 8-12
1) The PMU register short names are extended and referenced in the other parts of the TC1796 User’s Manual
with the module name prefix “PMU_”.

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The Module Identification Register ID contains read-only information about the DMU
module version.

ID
Module Identification Register (08H) Reset Value: 002D C0XXH
31 16 15 8 7 0

MODNUM MODTYPE MODREV

r r r

Field Bits Type Description

MODREV [7:0] r Module Revision Number
MODREV defines the module revision number. The value
of a module revision starts with 01H (first revision).
MODTYPE [15:8] r Module Type
This bit field defines the module as a 32-bit module: C0H
MODNUM [31:16] r Module Number Value
This bit field defines the module identification number for
the DMU: 002DH

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The Stand-by SRAM Control Register SBRCTR controls the locking and unlocking of the
DMU stand-by memory (SBRAM).

SBRCTR
Stand-by SRAM Control Register (E0H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STB
0 STBSLK STBULK LOC
K
r w w rh

Field Bits Type Description

STBLOCK 0 rh Stand-by Lock Flag
Shows the current lock state of the SBRAM.
0B SBRAM is locked
1B SBRAM is unlocked
STBULK [3:1] w Unlock Stand-by Lock Flag
In order to unlock the SBRAM, three consecutive write
cycles must be written into STBULK with the following
pattern:
1. Write STBULK = 001B
2. Write STBULK = 011B
3. Write STBULK = 111B
During the three consecutive write operations, STBSLK
must be written with 0000B. If any bit of STBSLK is set
when writing a non-zero pattern to STBULK, this is
treated as invalid pattern and the SBRAM will not be
unlocked. Reading STBULK always return 000B.
STBSLK [7:4] w Set Stand-by Lock Flag
In order to lock the SBRAM, the value 1001B must be
written into STBSLK. At the same time, the value 000B
must be written into STBULK. If any bit of STBULK is
set when writing 1001B to STBSLK, this is treated as
invalid pattern and the SBRAM will not be locked.
Reading STBSLK always returns 0000B.

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Field Bits Type Description

0 [31:8] r Reserved
Read as 0; should be written with 0.

For each of the 16 overlay sections (indicated by index x), three registers control the
overlay operation:
• The Redirected Address Base Register RABRx, which holds the base address of the
overlay memory block in the overlay memory, and some control bits
• The Overlay Target Address Register OTARx, which holds the base address of the
memory block being overlayed
• The Overlay Mask Register OMASKx, which determines which bits are part of the
offset address and which bits are part of the base address

RABRx (x = 0-15)
Redirected Address Base Register x
(20H+x*CH) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OV IEMS
RC1 RC0 0
EN = 0
rw r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OBASE 0

rw r

Field Bits Type Description

OBASE [15:1] rw Overlay Base Address
This bit field holds the base address of the overlay
memory block in the overlay memory.
The largest block base address that is allowed, is
(OBASEmax - block size1))
RC0 28, r Reserved Control Bits
RC1 29 These bits are reserved for future control expansions.
Read returns 0. Bits should be written with 0.

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Field Bits Type Description

IEMS = 0 30 r Internal/Emulation Memory Select
This bit indicates the location of the overlay memory. In
the TC1796, this bit is always read as 0, indicating that
the DMU SRAM is used as overlay memory.
0B DMU SRAM is selected as overlay memory;
Block sizes are 2n bytes, n = 1-9;
Segment address bits [31:28] are set to 1100B.
Note: In an TC1796ED emulation device, this bit can
be written, too. When set, an emulation memory
is selected as overlay memory (not applicable in
the TC1796).
OVEN 31 rw Overlay Enabled
This bit controls whether or not the overlay function of
overlay block x is enabled.
0B Overlay function of block x is disabled.
1B Overlay function of block x is enabled.
0 0, r Reserved
[27:16] Read as 0; should be written with 0.
1) The block size is determined by the mask register OMASK.

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OTARx (x = 0-15)
Overlay Target Address Register x
(20H+x*CH+4H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TSEG TBASE

rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TBASE 0

rw r

Field Bits Type Description

TBASE [27:1] rw Target Base
Holds the base address of the overlay memory block in
the target memory. If IEMS is set, bits [9:1] will be
forced to 0 and cannot be modified.
TSEG [31:28] rw Target Segment (reserved)
This bit field is reserved for future use, to select a
segment. In TC1796 implementation, any access to
segments 8H, or AH will be checked for a valid base
address; return 0 if read; should be written with 0.
0 0 r Reserved
Read as 0; should be written with 0.

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The Overlay Mask Register x determines the size of the overlay memory block x. It also
determines which address bits will participate in the address compare for a block base
address and which bits are used from the original target address and which bits are taken
from RABRx.OBASE.

OMASKx (x = 0-15)
Overlay Mask Register x (20H+x*CH+8H) Reset Value: 0FFF FE00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0 1

r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 OMASK 0

r rw r

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Field Bits Type Description

OMASK [8:1] rw Overlay Address Mask
This bit field determines two parameters:
• Block size of the overlay memory block x
• Address bits taken for address generation
The mask bits determine which address bits are taken
to check if a target address is overlayed, and
determines which address bits are taken from the
original target address as offset, and which are taken
from RABRx.OBASE. Thus the mask also determines
the block size of the overlay block.
0B Corresponding address bits are not used in the
address comparison
Corresponding final address bits are derived
from the original address
Block size is 2n bytes, n = number of trailing
zeros in the register
1B Corresponding address bits are used in the
address comparison
Corresponding final address bits are derived
from RABR_OBASE
Block size is 2n bytes, n = number of trailing
zeros in the register
All OMASK bits located right of the most significant
mask bit which is set to zero, are treated as zeros as
well, independent from their actual value. They will be
read back as 0.
Selected overlay memory block size:
00000000B 512 bytes
10000000B 256 bytes
11000000B 128 bytes
11100000B 64 bytes
11110000B 32 bytes
11111000B 16 bytes
11111100B 8 bytes
11111110B 4 bytes
11111111B 2 bytes

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Field Bits Type Description

0 0, r Fixed Values
[31:28] Corresponding address bits are not used in the address
comparison. Corresponding final address bits are taken
from the original address.
1 [27:9] r Fixed Values
Corresponding address bits are participating in the
address comparison. Corresponding final address bits
are taken from RABR.

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9 Memory Maps
This chapter gives an overview of the TC1796 memory map, and describes the address
locations and access possibilities for the units, memories, and reserved areas as “seen”
from the three different on-chip buses’ points of view.
The TC1796 has the following memories:
• Data Memory Unit (DMU) with
– 64 Kbyte of Data Memory (SRAM)
– 16 Kbyte of Stand-by Data Memory (SBRAM)
• Program Memory Unit (PMU) with
– 2 Mbyte of Program Flash Memory (PFLASH)
– 128 Kbyte of Data Flash Memory (DFLASH)
– 8 Kbyte of Boot ROM (BROM)
– 8 Kbyte of Test ROM (TROM)
• Program Memory Interface (PMI)
– 48 Kbyte of Scratch-Pad RAM (SPRAM)
– 16 Kbyte of Instruction Cache (ICACHE)
• Data Memory Interface (DMI)
– 56 Kbyte of Local Data RAM (LDRAM)
– 8 Kbyte of Dual-Port RAM (DPRAM)
• PCP memory
– 32 Kbyte of PCP Code Memory (CMEM)
– 16 Kbyte of PCP Data Memory (PRAM)
Furthermore, the TC1796 has four on-chip buses:
• System Peripheral Bus (SPB)
• Remote Peripheral Bus (RPB)
• Program Local Memory Bus (PLMB)
• Data Local Memory Bus (DLMB)

9.1 How to Read the Address Maps

The bus-specific address maps describe how the different bus master devices react on
accesses to on-chip memories and modules, and which address ranges are valid or
invalid for the corresponding buses.
The FPI Bus address map shows the system addresses from the point of view of the
SPB and RPB master agents. SPB master agents are PCP2, OCDS, and DMA (BI0).
The RPB is a single master bus with DMA (BI1) as the only master agent. Note that SPB
and RPB are combined in the single FPI Bus address map for simplification.
The PLMB address map shows the system addresses from the point of view of the PLMB
master (PMI).

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The DLMB address map shows the system addresses from the point of view of the
DLMB master (DMI).
Table 9-1 defines the acronyms and other terms that are used in the address maps
(Table 9-2 to Table 9-5).

Table 9-1 Definition of Acronyms and Terms

Term Description
...BE Means “Bus error” generation
...BET Means “Bus error & trap” generation
RPBBE A bus access is terminated with a bus error on the RPB.
RPBBET A bus access is terminated with a bus error on the RPB and a DSE
trap (read access) or DAE trap (write access).
SPBBE A bus access is terminated with a bus error on the SPB.
SPBBET A bus access is terminated with a bus error on the SPB and a DSE
trap (read access) or DAE trap (write access).
PLMBBE A bus access is terminated with a bus error on the PLMB.
PLMBBET A bus access is terminated with a bus error on the PLMB and a
DSE trap (read access) or DAE trap (write access).
DLMBBE A bus access is terminated with a bus error on the DLMB.
DLMBBET A bus access is terminated with a bus error on the DLMB and a
DSE trap (read access) or DAE trap (write access).
EBUBET If the requested address is configured by the EBU registers and
exist externally, the access is executed. In case of an address
error, a DLMBBET or PLMBBET is generated for a read access.
A PLMBBE is generated for a write access.
EBU access If the requested address is configured by the EBU registers, the
access is executed. In case of an un-configured address, an
“ignore” is applicable for a write access.
For read access, a SPBBE, DLMBBE, and PLMBBE are
generated for PCP2, DMA, and OCDS.
DLMBBE and PLMBBE are generated for DMI.
PLMBBE is generated for PMI.
access A bus access is allowed and is executed.
ignore A bus access is ignored and is not executed. No bus error is
generated.
trap A DSE trap (read access) or DAE trap (write access) is generated.

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Table 9-1 Definition of Acronyms and Terms (cont’d)

Term Description
32 Only 32-bit word bus accesses are permitted to that
register/address range.
nE A bus access generates no bus error, although the bus access
points to an undefined address or address range. This is valid e.g.
for CPU accesses (MTCR/MFCR) to undefined addresses in the
CSFR range.

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9.2 Contents of the Segments

This section summarizes the contents of the segments.

Segments 0-7
These segments are reserved segments in the TC1796.

Segment 8
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment allows
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM) and the
external EBU space.
From the CPU point of view (PMI and DMI), this memory segment allows cached
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM) and the
external EBU space.

Segment 9
This memory segment is reserved in the TC1796.

Segment 10
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment allows
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM) and the
external EBU space.
From the CPU point of view (PMI and DMI), this memory segment allows non-cached
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM) and the
external EBU space.

Segment 11
This memory segment is reserved in the TC1796 (comparable to segment 9).

Segment 12
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment is
reserved in the TC1796.
From the PLMB point of view (PMI), this memory segment is reserved in the TC1796.
From the DLMB point of view (DMI), this memory segment allows cached accesses to
all DMU memories (SRAM and SBRAM).

Segment 13
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment allows
accesses to the external peripheral and emulator space.

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From the PLMB point of view (PMI), this memory segment allows non-cached accesses
to the external peripheral and emulator space, the PMI scratch-pad RAM and read
access to the boot ROM and test ROM (BROM and TROM).
From the DLMB point of view (DMI), this memory segment allows non-cached accesses
to the external peripheral and emulator space and to the DMI memories (LDRAM and
DPRAM).

Segment 14
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment allows
accesses to the external peripheral space, the PMU data memory (SRAM), the DMI
memories (LDRAM and DPRAM), and the PMI scratch-pad memory (SPRAM).
From the CPU point of view (PMI and DMI), this memory segment allows non-cached
accesses to the external peripheral space.

Segment 15
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment allows
accesses to all SFRs and CSFRs, the PCP memories, and the MLI transfer windows.
From the CPU point of view (PMI and DMI), this memory segment allows accesses to all
SFRs and CSFRs, the PCP memories, and the MLI transfer windows.

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9.3 Address Map of the FPI Bus System

9.3.1 Segments 0 to 14
Table 9-2 shows the address map of segments 0 to 14 as it is seen from the SPB and
RPB bus masters PCP, DMA, and OCDS.

Table 9-2 SPB/RPB Address Map of Segment 0 to 14

Seg- Address Size Description Access Type
ment Range Read Write
0-7 0000 0000H - 8 byte Reserved (virtual address MPN trap MPN trap
0000 0007H space)
0000 0008H - 8 × 256 SPBBE SPBBE
7FFF FFFFH Mbyte
8 8000 0000H - 2 Mbyte Program Flash (PFLASH) access access1)
801F FFFFH
8020 0000H - 6 Mbyte Reserved PLMBBE & PLMBBE
807F FFFFH DLMBBE &
SPBBE
8080 0000H - 246 External EBU space EBU EBU
8FDF FFFFH Mbyte access access
8FE0 0000H - 128 Data Flash (DFLASH) access access1)
8FE1 FFFFH Kbyte
8FE2 0000H - 896 Reserved PLMBBE & PLMBBE
8FEF FFFFH Kbyte DLMBBE &
8FF0 0000H - 512 Reserved for TC1796 SPBBE
8FF7 FFFFH Kbyte emulation device memory
8FF8 0000H - 496 Reserved
8FFF BFFFH Kbyte
8FFF C000H - 8 Kbyte Boot ROM (BROM) access
8FFF DFFFH
8FFF E000H - 8 Kbyte Test ROM (TROM)
8FFF FFFFH
9 9000 0000H - 256 Reserved SPBBE SPBBE
9FFF FFFFH Mbyte

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Table 9-2 SPB/RPB Address Map of Segment 0 to 14 (cont’d)

Seg- Address Size Description Access Type
ment Range Read Write
10 A000 0000H - 2 Mbyte Program Flash (PFLASH) access access1)
A01F FFFFH
A020 0000H - 6 Mbyte Reserved PLMBBE & PLMBBE
A07F FFFFH DLMBBE &
SPBBE
A080 0000H - 246 External EBU space EBU EBU
AFDF FFFFH Mbyte access access
AFE0 0000H - 128 Data Flash (DFLASH) access access1)
AFE1 FFFFH Kbyte
AFE2 0000H - 896 Reserved PLMBBE & PLMBBE
AFEF FFFFH Kbyte DLMBBE &
AFF0 0000H - 512 Reserved for TC1796 SPBBE
AFF7 FFFFH Kbyte emulation device memory
AFF8 0000H - 496 Reserved
AFFF BFFFH Kbyte
AFFF C000H - 8 Kbyte Boot ROM (BROM) access
AFFF DFFFH
AFFF E000H - 8 Kbyte Test ROM (TROM)
AFFF FFFFH
11 B000 0000H - 256 Reserved SPBBE SPBBE
BFFF FFFFH Mbyte
12 C000 0000H - 64 Kbyte DMU data memory SPBBE SPBBE
C000 FFFFH (SRAM)
C001 0000H - 3.92 Reserved SPBBE SPBBE
C03F BFFFH Mbyte
C03F C000H - 16 Kbyte DMU stand-by data SPBBE SPBBE
C03F FFFFH memory (SBRAM)
C040 0000H - 251 Reserved
CFFF FFFFH Mbyte

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Table 9-2 SPB/RPB Address Map of Segment 0 to 14 (cont’d)

Seg- Address Size Description Access Type
ment Range Read Write
13 D000 0000H - 56 Kbyte DMI Local Data RAM SPBBE SPBBE
D000 DFFFH (LDRAM)
D000 E000H - 8 Kbyte DMI Dual-Port RAM
D000 FFFFH (DPRAM)
D001 0000H - ≈ 64 Reserved
D3FF FFFFH Mbyte
D400 0000H - 48 Kbyte PMI Scratch-Pad RAM
D400 BFFFH (SPRAM)
D400 C000H - ≈ 64 Reserved
D7FF FFFFH Mbyte
D800 0000H - 96 Mbyte External Peripheral Space compare compare
DDFF FFFFH
DE00 0000H - 16 Mbyte External Emulator Space
DEFF FFFFH
DF00 0000H - ≈ 16 Reserved SPBBE SPBBE
DFFF BFFFH Mbyte
DFFF C000H - 8 Kbyte Boot ROM (BROM)
DFFF DFFFH
DFFF E000H - 8 Kbyte Test ROM (TROM)
DFFF FFFFH

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Table 9-2 SPB/RPB Address Map of Segment 0 to 14 (cont’d)

Seg- Address Size Description Access Type
ment Range Read Write
14 E000 0000H - 128 External Peripheral Space EBU EBU
E7FF FFFFH Mbyte access access
E800 0000H - 64 Kbyte PMU data memory access access
E800 FFFFH (SRAM))
E801 0000H - 3.92 Reserved DLMBBE & DLMBBE
E83F FFFFH Mbyte SPBBE
E840 0000H - 56 Kbyte DMI Local Data RAM access access
E840 DFFFH (LDRAM)
E840 E000H - 8 Kbyte DMI Dual-Port RAM
E840 FFFFH (DPRAM)
E841 0000H - ≈ 1 Mbyte Reserved DLMBBE & DLMBBE
E84F FFFFH SPBBE
E850 0000H - 48 Kbyte PMI Scratch-Pad SRAM access access
E850 BFFFH (SPRAM)
E850 C000H - ≈ 3 Mbyte Reserved DLMBBE & PLMBBE
E87F FFFFH SPBBE
E880 C000H - ≈ 120 Reserved SPBBE PLMBBE
EFFF FFFFH Mbyte
15 F000 0000H - 256 see Table 9-3
FFFF FFFFH Mbyte
1) Only applicable when writing Flash command sequences.

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9.3.2 Segment 15
Table 9-3 shows the address map of segment 15 as seen from the SPB and RPB bus
masters PCP, DMA, and OCDS. Please note that access in Table 9-3 means only that
an access to an address within the defined address range is not automatically incorrect
or ignored. If an access is really addressing a correct address, it can be found in the
detailed tables in Chapter 18.

Table 9-3 SPB/RPB Address Map of Segment 15

Unit Unit Unit Access Type
Read Write
System Control Unit (SCU) and F000 0000H - 256 byte access access
Watchdog Timer (WDT) F000 00FFH
System Peripheral Bus Control Unit F000 0100H - 256 byte access access
(SBCU) F000 01FFH
System Timer (STM) F000 0200H - 256 byte access access
F000 02FFH
Reserved F000 0300H - – SPBBE SPBBE
F000 03FFH
On-Chip Debug Support (Cerberus) F000 0400H - 256 byte access access
F000 04FFH
Reserved F000 0500H - – SPBBE SPBBE
F000 07FFH
MicroSecond Bus Controller 0 F000 0800H - 256 byte access access
(MSC0) F000 08FFH
MicroSecond Bus Controller 1 F000 0900H - 256 byte access access
(MSC1) F000 09FFH
Async./Sync. Serial Interface 0 F000 0A00H - 256 byte access access
(ASC0) F000 0AFFH
Async./Sync. Serial Interface 1 F000 0B00H - 256 byte access access
(ASC1) F000 0BFFH
Port 0 F000 0C00H - 256 byte access access
F000 0CFFH
Port 1 F000 0D00H - 256 byte access access
F000 0DFFH
Port 2 F000 0E00H - 256 byte access access
F000 0EFFH

User’s Manual 9-10 V2.0, 2007-07

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Table 9-3 SPB/RPB Address Map of Segment 15 (cont’d)

Unit Unit Unit Access Type
Read Write
Port 3 F000 0F00H - 256 byte access access
F000 0FFFH
Port 4 F000 1000H - 256 byte access access
F000 10FFH
Port 5 F000 1100H - 256 byte access access
F000 11FFH
Port 6 F000 1200H - 256 byte access access
F000 12FFH
Port 7 F000 1300H - 256 byte access access
F000 13FFH
Port 8 F000 1400H - 256 byte access access
F000 14FFH
Port 9 F000 1500H - 256 byte access access
F000 15FFH
Port 10 F000 1600H - 256 byte access access
F000 16FFH
Reserved F000 1700H - – SPBBE SPBBE
F000 17FFH
General Purpose Timer Array 0 F000 1800H - 8 × 256 access access
(GPTA0) F000 1FFFH byte
General Purpose Timer Array 1 F000 2000H - 8 × 256 access access
(GPTA1) F000 27FFH byte
Local Timer Cell Array 2 (LTCA2) F000 2800H - 8 × 256 access access
F000 2FFFH byte
Reserved F000 3000H - – SPBBE SPBBE
F000 3BFFH
Direct Memory Access Controller F000 3C00H - 3 × 256 access access
(DMA) F000 3EFFH byte
Reserved F000 3F00H - – SPBBE SPBBE
F000 3FFFH
MultiCAN Controller (CAN) F000 4000H - 8 Kbyte access access
F000 5FFFH

User’s Manual 9-11 V2.0, 2007-07

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Table 9-3 SPB/RPB Address Map of Segment 15 (cont’d)

Unit Unit Unit Access Type
Read Write
Reserved F000 6000H - – SPBBE SPBBE
F003 FFFFH
PCP Reserved F004 0000H - – SPBBE SPBBE
F004 3EFFH
PCP Registers F004 3F00H - 256 byte access access
F004 3FFFH
Reserved F004 4000H - – SPBBE SPBBE
F004 FFFFH
PCP Data Memory (PRAM) F005 0000H - 16 nE, 32 nE, 32
F005 3FFFH Kbyte
Reserved F005 4000H - – SPBBE SPBBE
F005 FFFFH
PCP Code Memory F006 0000H - 32 nE, 32 nE, 32
(CMEM) F006 7FFFH Kbyte
Reserved F006 8000H - – SPBBE SPBBE
F007 FFFFH
Reserved F008 0000H - – SPBBE SPBBE
F00F FFFFH
Remote Peripheral Bus Control Unit F010 0000H - 256 byte access access
(RBCU) F010 00FFH
Synchronous Serial Interface 0 F010 0100H - 256 byte access access
(SSC0) F010 01FFH
Synchronous Serial Interface 1 F010 0200H - 256 byte access access
(SSC1) F010 02FFH
Fast Analog-to-Digital Converter F010 0300H - 256 byte access access
(FADC) F010 03FFH
Analog-to-Digital Converter 0 F010 0400H - 2 × 256 access access
(ADC0) F010 05FFH byte
Analog-to-Digital Converter 1 F010 0600H - 2 × 256 access access
(ADC1) F010 07FFH byte
Reserved F010 0800H - – RPBBE & RPBBE
F010 9FFFH SPBBE1)

User’s Manual 9-12 V2.0, 2007-07

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Table 9-3 SPB/RPB Address Map of Segment 15 (cont’d)

Unit Unit Unit Access Type
Read Write
Dual-Port RAM F010 A000H - 8 Kbyte access access
F010 BFFFH
Micro Link Interface 0 (MLI0) F010 C000H - 256 byte access access
F010 C0FFH
Micro Link Interface 1 (MLI1) F010 C100H - 256 byte access access
F010 C1FFH
Memory Checker (MCHK) F010 C200H - 256 byte access access
F010 C2FFH
Reserved F010 C300H - – SPBBE SPBBE
F01D FFFFH
MLI0 Small Transfer Windows F01E 0000H - 4×8 access access
F01E 7FFFH Kbyte
MLI1 Small Transfer Windows F01E 8000H - 4×8 access access
F01E FFFFH Kbyte
Reserved F01F 0000H - – SPBBE SPBBE
F01F FFFFH
MLI0 Large Transfer Windows F020 0000H - 4 × 64 access access
F023FFFFH Kbyte
MLI1 Large Transfer Windows F024 0000H - 4 × 64 access access
F027 FFFFH Kbyte
Reserved F028 0000H - – SPBBE SPBBE
F7E0 FEFFH
CPU CPU Slave Interface F7E0 FF00H - 256 byte access access
Registers (CPS) F7E0 FFFFH
CPU Core SFRs & GPRs F7E1 0000H - 64 access access
F7E1 FFFFH Kbyte
Reserved F7E2 0000H - – SPBBE SPBBE
F7FF FFFFH
External Bus Interface Unit (EBU) F800 0000H - 4 × 256 access access
F800 03FFH byte
Reserved F800 0400H - – PLMBBE & PLMBBE
F800 04FFH DLMBBE &
SPBBE

User’s Manual 9-13 V2.0, 2007-07

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Table 9-3 SPB/RPB Address Map of Segment 15 (cont’d)

Unit Unit Unit Access Type
Read Write
Program Memory Unit (PMU) F800 0500H - 256 byte access access
F800 05FFH
Reserved F800 0600H - – PLMBBE & PLMBBE
F800 0FFFH DLMBBE &
SPBBE
Flash Register F800 1000H - 5 Kbyte access access
F800 23FFH
Reserved F800 2400H - – DLMBBE & DLMBBE
F801 00FFH SPBBE
Data Memory Unit (DMU) F801 0100H - 256 byte access access
F801 01FFH
Reserved F801 0200H - – DLMBBE & DLMBBE
F87F F9FFH SPBBE
Data Local Memory Bus Control F87F FA00H - 256 byte access access
Unit (DBCU) F87F FAFFH
Reserved F87F FB00H - – DLMBBE & DLMBBE
F87F FBFFH SPBBE
CPU DMI Registers F87F FC00H - 256 byte access access
F87F FCFFH
PMI Registers F87F FD00H - 256 byte access access
F87F FDFFH
Program Local Memory Bus Control F87F FE00H - 256 byte access access
Unit (PBCU) F87F FEFFH
LFI Bridge F87F FF00H - 256 byte access access
F87F FFFFH
Reserved F880 0000H - – DLMBBE & DLMBBE
FFFF FFFFH SPBBE
1) The SPBBE is not generated for accesses from the DMA.

User’s Manual 9-14 V2.0, 2007-07

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9.4 Address Map of the Program Local Memory Bus (PLMB)

Table 9-4 shows the address map as seen from the PLMB bus masters (PMI and DMU).

Table 9-4 PLMB Address Map

Seg- Address Size Description Action
ment Range Read Write
1)
0-7 0000 0000H - 8 byte Reserved (virtual address MPN trap MPN trap
0000 0007H space)
0000 0008H - 8 × 256 PLMBBET PLMBBET
7FFF FFFFH Mbyte
81) 8000 0000H - 2 Mbyte Program Flash (PFLASH) access access2)
801F FFFFH
8020 0000H - 6 Mbyte Reserved PLMBBET PLMBBET
807F FFFFH
8080 0000H - 246 External EBU Space EBU EBU
8FDF FFFFH Mbyte access access
8FE0 0000H - 128 Data Flash (DFLASH) PLMBBET access2)
8FE1 FFFFH Kbyte
8FE2 0000H - 896 Reserved PLMBBET PLMBBET
8FEF FFFFH Kbyte
8FF0 0000H - 512 Reserved for TC1796
8FF7 FFFFH Kbyte emulation device memory
8FF8 0000H - 496 Reserved
8FFF BFFFH Kbyte
8FFF C000H - 8 Kbyte Boot ROM (BROM) access
8FFF DFFFH
8FFF E000H - 8 Kbyte Test ROM (TROM)
8FFF FFFFH
91) 9000 0000H - 256 Reserved PLMBBET PLMBBET
9FFF FFFFH Mbyte

User’s Manual 9-15 V2.0, 2007-07

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Table 9-4 PLMB Address Map (cont’d)

Seg- Address Size Description Action
ment Range Read Write
3)
10 A000 0000H - 2 Mbyte Program Flash (PFLASH) access access2)
A01F FFFFH
A020 0000H -