UNIT-3

PHYSICAL DESIGN
INTRODUCTION:

The transformation of a circuit description into a geometric description, is known as a layout.

A layout consists of a set of planar geometric shapes in several layers.
The process of converting the specifications of an electrical circuit into a layout is called the
Physical design. Due to the large number of components and the fine details required by the
fabrication process, the physical design is not practically possible without the help of
computers. As a result, almost all phases of physical design extensively use computer-aided
design (CAD) tools and many phases are either partially or fully automated. This automation
of the physical design process has increased the level of integration, reduced the turnaround
time, and enhanced chip performance.
There are various CAD tools available in market and each of them have their own strengths
and weaknesses. The Electronic Design Automation (EDA) companies like Cadence,
Synopsys, Magma, and Mentor Graphics provide these CAD tools. VLSI physical design
automation is mainly deals with the study of algorithms related to the physical design process.
The objective is to study optimal arrangements of devices on a plane (or in a three-dimensional
space) and various interconnection schemes between these devices to obtain the desired
functionality. Because space on a wafer is very expensive, algorithms must use the space very
efficiently to decrease the costs and improve the yield. In addition, the arrangement of devices
(placement) plays a key role in determining the performance of a chip. Algorithms for physical
design must also ensure that all the rules required by the fabrication are followed and that the
layout is within the tolerance limits of the fabrication process. Finally, algorithms must be
efficient and should be able to handle very large designs. Efficient algorithms not only lead to
fast turnaround time, but also permit designers to iteratively improve the layouts.

VLSI DESIGN CYCLE:

The design process of producing a packaged VLSI chip physically follows various steps which
is popularly known as VLSI design cycle. This design cycle is normally represented by a flow
chart shown below. The various steps involved in the design cycle are elaborated below.
(i). System specification: The specifications of the system to be designed are exactly specified
in this step. It considers performance, functionality, and the physical dimensions of the design.
The choice of fabrication technology and design techniques are also considered. The end results
are specifications for the size, speed, power, and functionality of the VLSI system to be
designed.
(ii) Functional design: In this step, behavioural aspects of the system are considered. The
outcome is usually a timing diagram or other relationships between sub-units. This information
is used to improve the overall design process and to reduce the complexity of the subsequent
phases.
(iii). Logic design: In this step, the functional design is converted into a logical design, using
the Boolean expressions. These expressions are minimized to achieve the smallest logic design.
which conforms to the functional design. This logic design of the system is simulated and
tested to verify its correctness.
(iv).Circuit design: This step involves conversion of Boolean expressions into a circuit
representation by taking into consideration the speed and power requirements of the original
design. The electrical behaviour of the various components are also considered in this phase.
The circuit design is usually expressed in a detailed circuit diagram.
(v).Physical design: In this step, the circuit representation of each component is converted into
a geometric representation. This representation is a set of geometric patterns which perform
the intended logic function of the corresponding component. Connections between different
components are also expressed as geometric patterns. (This geometric representation of a
circuit is called a layout). The exact details of the layout also depend on design rules, which
are guidelines based on the limitations of the fabrication process and the electrical properties
of the fabrication materials. Physical design is a very complex process, therefore, it is usually
broken down into various sub-steps in order to handle the complexity of the problem.

In integrated circuit design, physical design is a step in the standard design cycle which follows
after the circuit design. At this step, circuit representations of the components (devices and
interconnects) of the design are converted into geometric representations of shapes which,
when manufactured in the corresponding layers of materials, will ensure the required
functioning of the components. This geometric representation is called integrated circuit
layout. This step is usually split into several sub-steps, which include both design and
verification and validation of the layout.
Modern day Integrated Circuit (IC) design is split up into Front-end design using HDLs,
Verification, and Back-end Design or Physical Design. The next step after Physical Design is
the Manufacturing process or Fabrication Process that is done in the Wafer Fabrication
Houses. Fab-houses fabricate designs onto silicon dies which are then packaged into ICs.
Each of the phases mentioned above has Design Flows associated with them. These Design
Flows lay down the process and guide-lines/framework for that phase. Physical Design flow
uses the technology libraries that are pro-vided by the fabrication houses. These technology
files provide information regarding the type of Silicon wafer used, the standard-cells used, the
layout rules (like DRC in VLSI), etc.

Physical design steps within the IC design flow

Typically, the IC physical design is categorised into Full custom & Semi-Custom Design.

Full-Custom: Designer has full flexibility on the lay-out design, no predefined cells are
used.
Semi-Custom: Pre-designed library cells (prefer-ably tested with DFM) are used, designer
has flexi-bility in placement of the cells & routing.[3]
One can refer ASIC for Full Custom design and FPGA for Semi-Custom design flows. The
reason being that one has the flexibility to design/modify design blocks from Vendor provided
libraries in ASIC. This flexibility is missing for Semi-Custom flows like FPGA (e.g. Altera).

2 ASIC Physical Design Flow

A typical ASIC back-end flow

The main steps in the ASIC physical design flow are:

Design Netlist (after synthesis) Floorplanning

Partitioning Placement

Clock-tree Synthesis (CTS) Routing

Physical Verification

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A more detailed Physical Design Flow is shown below. Here you can see the exact steps and
the tools used in each step outlined.
4.2 Partitioning

feature size. Standard sizes, in the order of miniaturiza-tion, are 2μm, 1μm , 0.5μm , 0.35μm,
0.25μm, 180nm, 130nm, 90nm, 65nm, 45nm, 28nm, 22nm, 18nm, 14nm, etc. They may be also
classified according to major man-ufacturing approaches: n-Well process, twin-well pro-cess,
SOI process, etc.

3 Design Netlist

Physical design is based on a netlist which is the end result of the Synthesis process. Synthesis
converts the RTL design usually coded in VHDL or Verilog HDL to gate-level descriptions
which the next set of tools can read/understand. This netlist contains information on the cells
used, their interconnections, area used, and other details. Typical synthesis tools are:

Cadence RTL Compiler/Build Gates/Physically Knowledgeable Synthesis (PKS)

Synopsys Design Compiler

During the synthesis process, constraints are applied to ensure that the design meets the
required functionality and speed (specifications). Only after the netlist is veri-fied for
functionality and timing it is sent for the physical design flow.
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to be closer together. This leads to shorter interconnect distances, less routing resources to be
used, faster end-to-end signal paths, and even faster and more consistent place and route times.
Done correctly, there are no neg-atives to floorplanning.
As a general rule, data-path sections benefit most from floorplanning, and random logic, state
machines, and other non-structured logic can safely be left to the placer section of the place
and route software.
Data paths are typically the areas of your design where multiple bits are processed in parallel
with each bit being modified the same way with maybe some influence from adjacent bits.
Example structures that make up data paths are Adders, Subtractors, Counters, Registers, and
Muxes.

4.2 Partitioning

Partitioning is a process of dividing the chip into small blocks. This is done mainly to separate
different func-tional blocks and also to make placement and routing eas-ier. Partitioning can
be done in the RTL design phase when the design engineer partitions the entire design into sub-
blocks and then proceeds to design each module. These modules are linked together in the main
module called the TOP LEVEL module. This kind of partition-ing is commonly referred to as
Logical Partitioning.

4 Physical Design Steps

4.1 Floorplanning

The first step in the physical design flow is Floorplanning. Floorplanning is the process of
identifying structures that should be placed close together, and allocating space for them in
such a manner as to meet the sometimes conflict-ing goals of available space (cost of the chip),
required performance, and the desire to have everything close to everything else.
Based on the area of the design and the hierarchy, a suit-able floorplan is decided upon.
Floorplanning takes into account the macros used in the design, memory, other IP cores and
their placement needs, the routing possibilities and also the area of the entire design.
Floorplanning also decides the IO structure, aspect ratio of the design. A bad floorplan will
lead to waste-age of die area and rout-ing congestion.
In many design methodologies, Area and Speed are con-sidered to be things that should be
traded off against each other. The reason this is so is probably because there are limited routing
resources, and the more routing re-sources that are used, the slower the design will operate.
Optimizing for minimum area allows the design to use fewer resources, but also allows the
sections of the design
4.3 Placement

Before the start of placement optimization all Wire Load Models (WLM) are removed.
Placement uses RC values from Virtual Route (VR) to calculate timing. VR is the shortest
Manhattan distance between two pins. VR RCs are more accurate than WLM RCs.
Placement is performed in four optimization phases:

1. Pre-placement optimization

2. In placement optimization

3. Post Placement Optimization (PPO) before clock tree synthesis (CTS)

4. PPO after CTS.

Pre-placement Optimization optimizes the netlist before placement, HFNs are collapsed.
It can also downsize the cells.
In-placement optimization re-optimizes the logic based on VR. This can perform cell
sizing, cell mov-ing, cell bypassing, net splitting, gate duplication, buffer insertion, area
recovery. Optimization per-forms iteration of setup fixing, incremental timing and
congestion driven placement.
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 Post placement optimization before CTS performs netlist optimization with ideal clocks.
It can fix setup, hold, max trans/cap violations. It can do placement optimization based on
global routing. It re does HFN synthesis.
Post placement optimization after CTS optimizes timing with propagated clock. It tries to
preserve clock skew.

4.4 Clock tree synthesis

Ideal clock before CTS

The goal of clock tree synthesis (CTS) is to minimize skew and insertion delay. Clock is not
propagated before CTS as shown in the picture. After CTS hold slack should improve. Clock
tree begins at .sdc defined clock source and ends at stop pins of flop. There are two types of
stop pins known as ignore pins and sync pins. ‘Don’t touch’ circuits and pins in front end (logic
synthesis) are treated as ‘ignore’ circuits or pins at back end (physical synthesis). ‘Ignore’ pins
are ignored for timing analysis. If clock is divided then separate skew analysis is necessary.

Global skew achieves zero skew between two syn-chronous pins without considering logic
relation-ship.
Local skew achieves zero skew between two syn-chronous pins while considering logic
relationship.
If clock is skewed intentionally to improve setup slack then it is known as useful skew.

Rigidity is the term coined in Astro to indicate the re-laxation of constraints. Higher the rigidity
tighter is the constraints.
In clock tree optimization (CTO) clock can be shielded so that noise is not coupled to other
signals. But shield-ing increases area by 12 to 15%. Since the clock signal is global in nature
the same metal layer used for power routing is used for clock also. CTO is achieved by buffer
Clock After CTS

sizing, gate sizing, buffer relocation, level adjustment and HFN synthesis. We try to improve
setup slack in pre-placement, in placement and post placement optimiza-tion before CTS stages
while neglecting hold slack. In post placement optimization after CTS hold slack is im-proved.
As a result of CTS lot of buffers are added. Gen-erally for 100k gates around 650 buffers are
added.

4.5 Routing

There are two types of routing in the physical design pro-cess, global routing and detailed
routing. Global routing allocates routing resources that are used for connections.

4.6 Physical Verification

Physical verification checks the correctness of the gener-ated layout design. This includes
verifying that the layout

Complies with all technology requirements – Design Rule Checking (DRC)

Is consistent with the original netlist – Layout vs. Schematic (LVS)
Has no antenna effects – Antenna Rule Checking
This also includes density verification at the full chip level...Cleaning density is a very
critical step in the lower technology nodes
Complies with all electrical requirements – Electri-cal Rule Checking (ERC).[5]