LD49300

3 A very low-dropout voltage regulator

Datasheet - production data

Applications
• Graphics processors
• PC add-in cards
• Microprocessor core voltage supply
PPAK • Low voltage digital ICs
• High efficiency linear power supplies
• SMPS post regulators
Features
Description
• Input voltage range:
– VI = 1.4 V to 5.5 V The LD49300 is a high-bandwidth, low-dropout,
3.0 A voltage regulator, ideal for powering core
– VBIAS = 3 V to 6 V
voltages of low power microprocessors. The
• Stable with ceramic capacitors LD49300 implements a dual supply configuration,
• ±1.5% initial tolerance which guarantees a very low output impedance
and a fast transient response. The LD49300
• Maximum dropout voltage (VI - VO) 400 mV
requires a bias input supply and a main input
over the operating temperature range
supply, allowing ultra-low input voltages on the
• Adjustable output voltage starting from 0.8 V main supply rail. The input supply operates from
• Very fast transient response (up to 10 MHz 1.4 V to 5.5 V and bias supply requires between 3
bandwidth) V and 6 V to work properly. The LD49300 offers
fixed output voltages from 0.8 V to 1.8 V and
• Excellent line and load regulation
adjustable output voltages from 0.8 V. The
specifications
LD49300 requires a minimum output capacitance
• Logic-controlled shutdown option for stability, and works optimally with small
• Thermal shutdown and current limit protection ceramic capacitors.
• Junction temperature range: - 25 °C to 125 °C
Table 1. Device summary
Order codes Package Packaging

LD49300PT08R (1) PPAK (tape and reel) 2500 pieces per reel
LD49300PT10R PPAK (tape and reel) 2500 pieces per reel
LD49300PT12R PPAK (tape and reel) 2500 pieces per reel
1. Adjustable version.

May 2014 DocID12861 Rev 4 1/23

This is information on a product in full production. www.st.com
Contents LD49300

Contents

1 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Alternative application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1 Input supply voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.2 Bias supply voltage (VBIAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.3 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.4 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.5 Minimum load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.6 Power sequencing recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.7 Power dissipation/heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.8 PPAK package heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.9 Adjustable regulator design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.10 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/23 DocID12861 Rev 4

LD49300 Typical application circuits

1 Typical application circuits

Figure 1. Adjustable version

Figure 2. Fixed version with enable

DocID12861 Rev 4 3/23

23
Alternative application circuits LD49300

2 Alternative application circuits

Figure 3. Single supply voltage solution

Figure 4. LD49300 and DC-DC pre-regulator to reduce power dissipation

4/23 DocID12861 Rev 4

LD49300 Pin configuration

3 Pin configuration

Figure 5. Pin connection (top view)

Table 2. Pin description

Pin Symbol Note

EN Enable (input): logic high = enable, logic low = shutdown

1
ADJ Adjustable regulator feedback input connected to resistor voltage divider
2 VIN Input voltage regulator
3 GND Ground (tab is connected to ground)
4 VOUT Regulator output
5 VBIAS Input bias voltage powers the circuitry on the regulator except the output power device

DocID12861 Rev 4 5/23

23
Diagram LD49300

4 Diagram

Figure 6. Block diagram

6/23 DocID12861 Rev 4

LD49300 Maximum ratings

5 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VIN Supply voltage -0.3 to 7 V

-0.3 to VIN + 0.3
VOUT Output voltage V
-0.3 to VBIAS + 0.3
VBIAS Bias supply voltage -0.3 to 7 V
VEN Enable input voltage -0.3 to 7 V
PD Power dissipation Internally limited
TSTG Storage temperature range -50 to 150 °C

Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
All values are referred to ground.

Table 4. Operating ratings

Symbol Parameter Value Unit

VIN Supply voltage 1.4 to 5.5 V

VOUT Output voltage 0.8 to 4.5 V
VBIAS Bias supply voltage 3 to 6 V
VEN Enable input voltage 0 to VBIAS V
TJ Junction temperature range - 25 to 125 °C

DocID12861 Rev 4 7/23

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Electrical characteristics LD49300

6 Electrical characteristics

TJ = - 25 °C to 125 °C; VBIAS = VO + 2.1 V(1); VI = VO + 1 V; VEN = VBIAS(2); IO = 10 mA;

CI = 1 µF; CO = 10 µF; CBIAS = 1 µF; unless otherwise specified. Typical values are referred
to TJ = 25 °C.

Table 5. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

TJ = 25 °C, fixed voltage option -1.5 1.5

VO Output voltage accuracy %
TJ = -25 °C to 125 °C -3 3
VLINE Line regulation VI = VO + 1 V to 5.5 V -0.1 0.1 %/V
VLOAD Load regulation IL = 0 mA to 3 A, VBIAS ≥ 3 V 1 %
IL = 1.5 A 200
VDROP Dropout voltage (VI - VO) mV
IL = 3 A 400
VDROP Dropout voltage (VBIAS- VO) IL = 3 A(1) 1.5 2.1 V
IL = 0 mA 4 6
IGND Ground pin current mA
IL = 3 A 4 6
IGND_SHD Ground pin current in shutdown VEN ≤ 0.4 V(2) 5 µA
IL = 0 mA 3 5
IVBIAS Current through VBIAS mA
IL = 3 A 3 5
IL Current limit VO = 0 V 4.5 A

Enable input(2)

Enable input threshold (fixed Regulator enable 1.4

VEN V
voltage only) Regulator shutdown 0.4
IEN Enable pin input current 0.1 1 µA

Reference

TJ = 25 °C 0.788 0.8 0.812

VREF Reference voltage V
TJ = -25 °C to 125 °C 0.776 0.8 0.824
VI = 2.5 V ± 0.5 V, VO = 1 V
SVR Supply voltage rejection 68 dB
F = 120 Hz, VBIAS = 3.3 V
1. For VO ≤ 1 V, VBIAS dropout specification is not applied due to 3 V minimum VBIAS input.
2. Fixed output voltage version only.

8/23 DocID12861 Rev 4

LD49300 Typical characteristics

7 Typical characteristics

Figure 7. Reference voltage vs. temperature Figure 8. Output voltage vs. temperature

Figure 9. Load regulation vs. temperature Figure 10. Line regulation vs. temperature
-0"%


Figure 11. Output voltage vs. input voltage Figure 12. Dropout voltage (VIN-VOUT) vs.
temperature (IOUT = 1.5 A)
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7(03(5$785(

DocID12861 Rev 4 9/23

23
Typical characteristics LD49300

Figure 13. Dropout voltage (VIN-VOUT) vs. Figure 14. VBIAS pin current vs. temperature
temperature (IOUT = 3 A)
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Figure 15. Noise vs. frequency Figure 16. Quiescent current vs. temperature

Figure 17. Supply voltage rejection vs. output Figure 18. Stable region vs. COUT and high ESR
current

10/23 DocID12861 Rev 4

LD49300 Typical characteristics

Figure 19. Stable region vs. COUT and low ESR Figure 20. VBIAS and VIN start-up transient
response (VIN and VBIAS startup at the same
time)

VIN=V BIAS=VEN=3.1V, VOUT=1V, COUT=1µF

Figure 21. VIN start-up transient response Figure 22. VIN start-up transient response
(VBIAS startup before than VIN) Trise = 300 μs (VBIAS startup before than VIN) Trise = 30 μs

VIN=2.5V, VBIAS=VEN=3.1V, VOUT=1V, COUT=1µF VIN=2.5V, VBIAS=VEN=3.1V, VOUT=1V, COUT=1µF

DocID12861 Rev 4 11/23

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Typical characteristics LD49300

Figure 23. VIN start-up transient response Figure 24. Load transient response
(VBIAS startup before than VIN and VEN = VIN)

VIN=VEN=2.5V, VBIAS=3.1V, VOUT=1V, COUT=1µF VIN=2.5V, VBIAS=5V, VOUT=1.8V, IOUT=10mA to 3A,

COUT = 10 µF

12/23 DocID12861 Rev 4

LD49300 Application hints

8 Application hints

The LD49300 is a low-dropout linear regulator, designed for high-current applications

requiring a fast transient response. The LD49150 has separate input and bias voltage ports,
in order to reduce dropout voltage. Thanks to the LD49300, a minimum quantity of external
components is required.

8.1 Input supply voltage (VIN)

VIN provides the LD49300 with power input current. The minimum input voltage can be as
low as 1.4 V, allowing conversion from very low voltage supplies to achieve low output
voltage levels and low power dissipation.

8.2 Bias supply voltage (VBIAS)

The LD49300 control circuitry is supplied by VBIAS pin, which requires a very low bias
current (3 mA typ.) even at the maximum output current level (3 A). A bypass capacitor on
VBIAS pin improves the LD49300 performance during line and load transient. The small
ceramic capacitor from VBIAS to ground reduces high frequency noise that could be injected
into the control circuitry. In typical applications, one ceramic chip capacitor of 1 µF may be
used. VBIAS input voltage has to be 2.1 V above the output voltage, with a minimum VBIAS
input voltage of 3 V.

8.3 External capacitors

To assure regulator stability, input and output capacitors are required as shown in the typical
application circuit.

8.4 Output capacitor

The LD49300 requires a minimum output capacitance to maintain stability. At least 1 µF
ceramic chip capacitor is required. However, specific capacitor selection assures the
transient response. 1 µF ceramic chip capacitor satisfies most applications but 10 µF
capacitor guarantees a better transient performance. In applications where VIN level is close
to the maximum operating voltage (VIN > 4 V), a 10 µF minimum output capacitor avoids the
overvoltage stress on the input/output power pins during short-circuit conditions due to
parasitic inductive effect. The output capacitor has to be as closer as possible to the
LD49300 output pin. ESR output capacitor (equivalent series resistance) has to be within
the stable region as shown in Section 7: Typical characteristics. Both ceramic and tantalum
capacitors are suitable.

8.5 Minimum load current

The LD49300 does not require a minimum load to maintain the output voltage regulation.

DocID12861 Rev 4 13/23

23
Application hints LD49300

8.6 Power sequencing recommendations

To assure the correct biasing and settling of the regulator internal circuitry during the start-
up phase, as well as to avoid overvoltage spikes on the output, the correct power
sequencing has to be provided.
As general rule, VIN and VEN signal timings should be chosen properly, so that they are
applied to the device after VBIAS voltage has already been settled on its minimum operative
value (see Section 8.2: Bias supply voltage (VBIAS)). This can be achieved, for instance, by
avoiding too slow VBIAS rising edges (Tr > 10 ms).
Provided that the above condition is satisfied, when fast VIN transient input (Tr < 100 µs) is
present, a smooth startup, with limited overvoltage on the output, can be achieved
simultaneously by VIN and VBIAS voltage (refer to Figure 20, Figure 21 and Figure 22).
In the fixed voltage version, overvoltage spikes can be reduced during very fast startup (Tr
<< 100 µs) by pulling VEN pin up to VIN voltage (see Figure 23).

8.7 Power dissipation/heatsinking

In relation to the maximum power dissipation and maximum ambient temperature of the
application, a heatsink may be required. Junction temperature has to be within the specified
range under operating conditions. The total power dissipation of the device is given by:

Equation 1
PD = VIN x IIN + VBIAS x IBIAS - VOUT x IOUT
where:
• VIN = input supply voltage
• VBIAS = bias supply voltage
• VOUT = output voltage
• IOUT = load current
The required θSAthermal resistance for the heatsink is given by the following formula:

Equation 2
θSA = (TJ - TA/PD) - (θJC + θCS)
TRmax, the maximum allowed temperature rise depends on TAmax, the maximum ambient
temperature of the application, and TJmax, the maximum allowable junction temperature:

Equation 3
TRmax = TJmax - TAmax
The maximum allowable value for junction-to-ambient thermal resistance, θJA, can be
calculated as follows:

Equation 4
θJAmax = TRmax / PD
For PPAK package only.

14/23 DocID12861 Rev 4

LD49300 Application hints

The thermal resistance depends on the amount of copper area or heatsink, and on the air
flow. If θJA maximum allowable value is ≥ 100 °C/W for PPAK package, no heatsink is
needed since the package can dissipate enough heat to satisfy these requirements. If the
value for allowable θJA falls below these limits, a heatsink is required as described below.

8.8 PPAK package heatsinking

PPAK package uses the copper plane on the PCB as a heatsink. The tab of this package is
soldered to the copper plane for heatsinking. The PCB ground plane can be used as a
heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a dual-layer PCB,
it can be the unbroken GND area on the bottom layer thermally connected to the tab
through-via holes.
Figure 25 shows θJA curve for PPAK package for different copper area sizes, using a typical
PCB: thickness 1/16 G10 FR4.

Figure 25. θJA vs. copper area for PPAK package

8.9 Adjustable regulator design

The LD49300 adjustable version allows the output voltage to be fixed anywhere between
0.8 V and 4.5 V using two resistors as shown in the typical application circuit. For example,
to fix R1 resistor value between VOUT and ADJ pin, the resistor value between ADJ and
GND (R2) is calculated as follows:

Equation 5
R2 = R1 [0.8 / (VOUT - 0.8)]
where VOUT is the desired output voltage.
R1 values should be lower than 10 kΩ to obtain a better load transient performance. Higher
values up to 100 kΩ are suitable.

DocID12861 Rev 4 15/23

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Application hints LD49300

8.10 Enable
The LD49300 fixed output voltage version features an active high enable input (EN) that
allows the on-off control of the regulator. EN input threshold is guaranteed between 0.4 V
and 1.4 V. The regulator is in shutdown mode when VEN < 0.4 V and it is in operating mode
(VOUT activated) when VEN > 1.4 V. If it is not in use, EN pin has to be tied directly to VIN to
keep the regulator continuously activated. EN pin has not to be left with high impedance.

16/23 DocID12861 Rev 4

LD49300 Package mechanical data

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

DocID12861 Rev 4 17/23

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Package mechanical data LD49300

Figure 26. PPAK drawing

0078180_F

18/23 DocID12861 Rev 4

LD49300 Package mechanical data

Table 6. PPAK mechanical data

mm
Dim.
Min. Typ. Max.

A 2.2 2.4
A1 0.9 1.1
A2 0.03 0.23
B 0.4 0.6
B2 5.2 5.4
C 0.45 0.6
C2 0.48 0.6
D 6 6.2
D1 5.1
E 6.4 6.6
E1 4.7
e 1.27
G 4.9 5.25
G1 2.38 2.7
H 9.35 10.1
L2 0.8 1
L4 0.6 1
L5 1
L6 2.8
R 0.20
V2 0° 8°

DocID12861 Rev 4 19/23

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Packaging mechanical data LD49300

10 Packaging mechanical data

Figure 27. PPAK tape

10 pitches cumulative
tolerance on tape +/- 0.2 mm

Top cover P0 D P2
T tape
E

F
K0 W
B1 B0

For machine ref. only A0 P1 D1

including draft and
radii concentric around B0
User direction of feed

Bending radius
User direction of feed

AM08852v1

20/23 DocID12861 Rev 4

LD49300 Packaging mechanical data

Figure 28. PPAK reel

T
REEL DIMENSIONS

40mm min.

Access hole

At slot location

A N

Full radius Tape slot G measured at hub

in core for
tape start 25 mm min.
width

AM08851v2

Table 7. PPAK tape and reel mechanical data

Tape Reel

mm mm
Dim. Dim.
Min. Max. Min. Max.

A0 6.8 7 A 330
B0 10.4 10.6 B 1.5
B1 12.1 C 12.8 13.2
D 1.5 1.6 D 20.2
D1 1.5 G 16.4 18.4
E 1.65 1.85 N 50
F 7.4 7.6 T 22.4
K0 2.55 2.75
P0 3.9 4.1 Base qty. 2500
P1 7.9 8.1 Bulk qty. 2500
P2 1.9 2.1
R 40
T 0.25 0.35
W 15.7 16.3

DocID12861 Rev 4 21/23

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Revision history LD49300

11 Revision history

Table 8. Document revision history

Date Revision Changes

20-Nov-2006 1 Initial release.

01-Dec-2006 2 Add note in cover page.
29-Jun-2010 3 Modified Section 8.6: Power sequencing recommendations on page 14.
Changed the part numbers LD49300xx08, LD49300xx10 and LD49300xx12 to
LD49300.
Changed the title.
26-May-2014 4 Updated the description in cover page and Section 9: Package mechanical
data.
Added Section 10: Packaging mechanical data.
Minor text changes.

22/23 DocID12861 Rev 4

LD49300

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