Fdq7238S: Dual Notebook Power Supply N Channel Powertrench in So-14 Package
Fdq7238S: Dual Notebook Power Supply N Channel Powertrench in So-14 Package
September 2003
FDQ7238S
Dual Notebook Power Supply N-Channel PowerTrench in SO-14 Package
General Description Features
The FDQ7238S is designed to replace two single SO-8
• Q2: 14 A, 30V. RDS(on) = 9.5 mΩ @ VGS = 10V
MOSFETs in DC to DC power supplies. The high-side
switch (Q1) is designed with specific emphasis on RDS(on) = 10.5 mΩ @ VGS = 4.5V
reducing switching losses while the low-side switch
(Q2) is optimized to reduce conduction losses using
Fairchild’s SyncFET TM technology. • Q1: 11 A, 30V. RDS(on) = 14.5 mΩ @ VGS = 10V
S2
S2
S2
G2
SO-14 G1
pin 1 Vin
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a & 1b) 52 68 °C/W
(Note 1c & 1d) 94 118
On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 1 mA Q2 1 1.4 3 V
VDS = VGS, ID = 250 µA Q1 1 1.4 3
∆VGS(th) Gate Threshold Voltage ID = 10 mA, Referenced to 25°C Q2 −3 mV/°C
∆TJ Temperature Coefficient ID = 250 µA, Referenced to 25°C Q1 −5
RDS(on) Static Drain-Source VGS = 10 V, ID = 14 A Q2 7 9.5 mΩ
On-Resistance VGS = 4.5 V, ID = 13 A 8 10.5
VGS = 10 V, ID = 14A, TJ = 125°C 11 16
VGS = 10 V, ID = 11 A Q1 11 14.5
VGS = 4.5 V, ID = 10 A 12 16
VGS = 10 V, ID = 11, TJ = 125°C 16 23
ID(on) On–State Drain Current VGS = 10 V, VDS = 5 V Q2 50 A
VGS = 10 V, VDS = 5 V Q1 50
gFS Forward Transconductance VDS = 10 V, ID = 14 A Q2 67 S
VDS = 10 V, ID = 11 A Q1 48
Dynamic Characteristics
Ciss Input Capacitance VDS = 15 V, VGS = 0 V, Q2 2872 pF
f = 1.0 MHz Q1 1906
Coss Output Capacitance Q2 522 pF
Q1 311
Crss Reverse Transfer Capacitance Q2 186 pF
Q1 134
RG Gate Resistance VGS = 15 mVf = 1.0 MHz Q2 1.5 Ω
Q1 0.8
Switching Characteristics (Note 2)
td(on) Turn-On Delay Time VDD = 15 V, ID = 1 A, Q2 14 25 nS
VGS = 10V, RGEN = 6 Ω Q1 11 20
tr Turn-On Rise Time Q2 13 23 nS
Q1 13 23
td(off) Turn-Off Delay Time Q2 51 82 nS
Q1 28 45
tf Turn-Off Fall Time Q2 18 32 nS
Q1 15 27
Qg Total Gate Charge Q2 Q2 48 67 nC
VDS = 15 V, ID = 14A, VGS = 10 V Q1 33 46
Qgs Gate-Source Charge Q2 6 nC
Q1 Q1 4
Qgd Gate-Drain Charge VDS = 15 V, ID = 11A,VGS = 10 V Q2 8 nC
Q1 4
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user’s board design.
60 2.2
VGS = 10V 3.0V
DRAIN-SOURCE ON-RESISTANCE
3.5V 2
50
6.0V 4.5V VGS = 2.5V
ID, DRAIN CURRENT (A)
RDS(ON), NORMALIZED
1.8
40 2.5V
1.6
30
3.0V
1.4
3.5V
20
1.2 4.5V
6.0V
10 1 10V
0 0.8
0 0.5 1 1.5 2 0 10 20 30 40 50 60
ID, DRAIN CURRENT (A)
VDS, DRAIN-SOURCE VOLTAGE (V)
1.8 0.024
ID = 14A ID = 7A
DRAIN-SOURCE ON-RESISTANCE
0.02
RDS(ON), NORMALIZED
1.4 0.018
0.016
1.2
0.014
TA = 125oC
1 0.012
0.01
0.8
0.008
TA = 25oC
0.6 0.006
-50 -25 0 25 50 75 100 125 150 2 4 6 8 10
o
TJ, JUNCTION TEMPERATURE ( C) VGS, GATE TO SOURCE VOLTAGE (V)
70 100
VDS = 5V TA = -55oC 25oC
60
VGS = 0V
IS, REVERSE DRAIN CURRENT (A)
125oC 10
ID, DRAIN CURRENT (A)
50
TA = 125oC
40 1
30 25oC
0.1
20
-55oC
10 0.01
0
1 1.5 2 2.5 3 3.5 0.001
VGS, GATE TO SOURCE VOLTAGE (V) 0 0.2 0.4 0.6 0.8
VSD, BODY DIODE FORWARD VOLTAGE (V)
10 4000
f = 1MHz
ID = 14A VDS = 10V
VGS, GATE-SOURCE VOLTAGE (V)
CISS VGS = 0 V
15V
8 3200
CAPACITANCE (pF)
20V
6 2400
4 1600
COSS
2 800
CRSS
0 0
0 10 20 30 40 50 0 5 10 15 20 25 30
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
100 50
100us
P(pk), PEAK TRANSIENT POWER (W) SINGLE PULSE
1ms RθJA = 94°C/W
RDS(ON) LIMIT 40 TA = 25°C
10ms
ID, DRAIN CURRENT (A)
10
100ms
1s
10s 30
1 DC
20
VGS = 10V
0.1 SINGLE PULSE
10
RθJA = 94oC/W
TA = 25oC
0.01 0
0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000
VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
1
r(t), NORMALIZED EFFECTIVE TRANSIENT
D = 0.5
RθJA(t) = r(t) * RθJA
0.2
RθJA = 94 °C/W
THERMAL RESISTANCE
0.1 0.1
0.05
P(pk
0.02
t1
0.01
0.01 t2
TJ - TA = P * RθJA(t)
SINGLE PULSE Duty Cycle, D = t1 / t2
0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
0.01
o
TA = 100 C
CURRENT : 0.8A/div
0.001
o
TA = 25 C
0.0001
0.00001
0 5 10 15 20 25 30
VDS, REVERSE VOLTAGE (V)
TIME : 12.5nS/div
60 2.4
VGS = 10V 3.5V 3.0V
DRAIN-SOURCE ON-RESISTANCE
2.2
50 VGS = 2.5V
6.0V
ID, DRAIN CURRENT (A)
RDS(ON), NORMALIZED
4.5V
40
1.8
30 1.6
3.0V
2.5.V
1.4
20 3.5V
1.2 4.5V
6.0V
10 10V
1
0 0.8
0 0.5 1 1.5 2 2.5 3 0 10 20 30 40 50 60
1.8 0.036
ID = 11A ID = 5.5A
DRAIN-SOURCE ON-RESISTANCE
0.028
1.4
0.024
1.2 TA = 125oC
0.02
1
0.016
0.8
0.012
TA = 25oC
0.6
0.008
-50 -25 0 25 50 75 100 125 150
2 4 6 8 10
o
TJ, JUNCTION TEMPERATURE ( C) VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance Variation with Figure 18. On-Resistance Variation with
Temperature. Gate-to-Source Voltage.
60 100
VDS = 5V VGS = 0V
TA = -55oC 25oC
IS, REVERSE DRAIN CURRENT (A)
50 10
ID, DRAIN CURRENT (A)
125oC TA = 125oC
40 1
25oC
30 0.1
-55oC
0.01
20
0.001
10
0.0001
0
0 0.2 0.4 0.6 0.8 1 1.2
1 1.5 2 2.5 3 3.5
VSD, BODY DIODE FORWARD VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 19. Transfer Characteristics. Figure 20. Body Diode Forward Voltage Variation
with Source Current and Temperature.
10 2400
f = 1MHz
ID = 11A VDS = 10V VGS = 0 V
VGS, GATE-SOURCE VOLTAGE (V)
15V CISS
2000
8
20V
CAPACITANCE (pF)
1600
6
1200
4
800
COSS
2
400
CRSS
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
100 50
10 10ms
100ms
1s 30
10s
1 DC
20
VGS = 10V
0.1 SINGLE PULSE
RθJA = 118oC/W 10
TA = 25oC
0.01 0
0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000
VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)
Figure 23. Maximum Safe Operating Area. Figure 24. Single Pulse Maximum
Power Dissipation.
1
r(t), NORMALIZED EFFECTIVE TRANSIENT
D = 0.5
R θJA(t) = r(t) * R θJA
0.2
THERMAL RESISTANCE
0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. I5
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