| = a = }ad is : HAND WRITTEN NOTES m F |} gh a tLECTRONICS & COMMUNICATION = ENGINEERINI a: a, a > =) SUBIECT:- Za 2:DIGITAL ELECTRONICS 2 |) ‘| jetoate CT ICICLE __ Boolean Algebra :- | © when no. of variable are less y (2.3) a Ft -is_prejfered when __ output a no. of voriobeS are 2.3.4.5 (upto 5 variable) G) output is O.10F, a. “3 | Tabvlation method. = This used— when no. of variables are _ mare | Boolean Algebra + 2 A or, A‘ c. im ==! — = sae a — - AA = A i Ad = A 2 Av. z WOR aco a] OR +- oro = 0 AtrA = A on =r At! qo) = Ato fol Sm Ait Ae - Abt AB A (86) at) =k claccmate. : ace TT)“ABr ASce AGG , find the min. no. of _NAND @ate_ option. ~a) O ®t ©) 2 => a3. sore Agr AGC + ABC G (aus) = AB +r AB (Crd) = AB AS Cc =) | | = Atér@ J ae No NAND gate: required - a Advantage of Mioimization :- 3 No. of logic gate + = Speed T | Power dissipation _v [> compleaity of Girovit tess_ = fan in ¥ (no. of input Vv) > copt e Haaent Smtty = wm | AB + ase + AGED sor--| asec ae (1+ 60) asc + AS (ta =1) i a(6+ec) C: +86 = 8+e) A(6+e) AG +AE @rB) (AO) AAT AC TAB +r BC> = A+ AC CtB) + BC = AUrerc) + BC - A +8 i JTanspos|tion Theorem vact [_]— |G Gs Sane | (AP B46) (At B+C) CArB1E) take A+B =x (Care) CA4 B40) Cer) (+c) (At B40) ' *x (At Grc) (Ata (Ar B +c) A+ 8(6+C) = A+ 66 +6Cc = A+ BC re) | (At B) CATB) (A+B) CAB) “soll (AtB) CA4B) (At BytAt @) a = (At BB)eCA+reB } : AMA) = i ° ke a t ar AG s ArAAre) = 1(ArB) = AB. [ar ec = (rere | Distribution theorem. @| Ar AS gor:| @+A) (A+B) 5 : = atB) = Ate Sol ae AGr AB + AG A (818) + AS = A+AE > A+A ATED = A+B any classmatefh | AB+ AB + AG : os BC Ata) +. AB = 6+ae (6a) (B48) 2 aT A+B Ans. CY @ AGG + ABC + ABC Sol-| ABe + ABC + ABC 4ABC (zr aAta= a) l= AG(c+e) + ATA)BC - = AB+t Bc = B(AtC) ®» AB+ AC +.6C-—— redundant term. Sol} AB + Ac+ Bc (ATA) AB +A; + BCA + ABC AB (146) + ACCI+B) = AB+AT s In this cose 6C is Known os redurdonl term se notused or _not_compulsory term, > AB + AC + Bc = AB+ AC » called _consensus_theorem or _redundanc: y theoem - es 3 Shortcut method :— @) Three variable - : eo variable comes twice. © One voriable is complemented. (4)| AB+ BG + AC Ac 7 The term which is complemented fs token. =(A+ 8) (Ate) 5 + (8tc) 1S redundant .term +8) G0) (40) v (8tc) : oD AG +66 In this case atl the variable are complemented only one are uncomplemented.__ then. 3 = AB+AG 5 (+ the term whiots is uncomplemerted is_taken) Boolean Algebra +— Minimization —_. minimal cononicat minimal Te conoaicat Complement Expression | Truth table Venn diagram Switching circuit ‘Staternent-‘Minimizahon 2 xy + X¥wWz A= XY and ms i = A+AB = (tA) (AB) ~ Ate Xyr We tet f(Age) = A+t8 then the value _ of ¢.U4 (r7. y) 52) is xy +2 ©) Kr+P2 xy+2 @ x 4 CH, yf, ZI] Sy issay eed ¥ 22] ey 477 +2 x¥+Z Ars. int Kee = Ka ant Then the vawe cof =* * @ xX ®) 1 z= xy is @o | “ @ xSOP (Sum of Pradvot Form) Asc + Aec + ABC TS minterm In SoP form, .each product term is -known_as Impticant , Sop Farm is used when %/P of togical_eapression 1 A and 0—>A) tor + “ABC — abcd Minter _or is f. (means Ex 5s > -9 = 1001 For the given truth table minimize SOP expression A 8 O oO ' o 1 AB AB sop form only 1 taken. a6 + Ag B (A+A) 8 "y con written as :- = = m,2) 7 (4,8) = Simplified the eapression_f0" ¥(A,8) - =m(%2,3) mo WO logical € sSrcttle in sop form :- AB + AB + AB @ (Ara) + AB B+rAR (Sra) (6+8) ats A+me is a. = minimal form) aes “each term must_have_ all “variable. 6 @ 7 az8c A(ee8)icee) + BC CAA) 4ABr AG) (CtE) + ABC + AGC ABC + AGG + ABC +AGG + AB =—ABC + ABG + ABC + ABS + ABC ie. Sterms. Bc + ABC(Product of Sum) + (At B4C) (Aner) (A184) maa_term Si 107 9 > wor table minimize at i) a given th troth Oe 1 OF ff we take only that valve at which O/p is 0’ Y= (Are) (At 8) = B+ AA 28 Y can be uritlen in Pos form as, YCA8) = 8 and for sop Y (8) = TM (13) = =m (0,2) ae Le =mlo,2) = TMC3)° = (0,154.7) Tf F (4.8.6) = & combinabon then mar. term There are 3 variable then are, 2.3,5,6. —$———— = m (% be4I) Tom (2.3.96) : F(A,BC) =" variable. _manimum m_possile minterms or “Tata no of minor ym terms are ave 27s | ie. (A.80) Tata) nov of_™mIn_o - fo n=2. (A,8) totat 16 logo expression ie. r man_ terms are Pee J Ag AB ae AB At8 _o0 AB +tAR ai8 Ag AB+ AG Are Ate Note] with variable maaimum possible logical expression | are = 2 eq. for n=2 _ logical expression = x 6 ea Zara wase for _n=3 total no. of logical eapression. 4 For m=4 what is the logical eapression = z 16Dual Form F is a) tive logic sive logic» — » +live logic means figher fugher gi: stein “eqres ponds to togie 1 ov __ Higher “value of voltage (OY) form logic 1. then +ive logic ECL * togic'O" + — TV logic 1 > —0 ay v =ogv 4s larger vale than -l7v then it is +ive logic. —ive logic AND sive logic A 0 ° 1 I A \ ° Bs a pie mre a O50: fo For -ive logic or gate , convert ! ta 0 and Oto tL. we can say that +ive logic AND gate. is equal to -ive logic oR gate and ~ive logic AND. gate is eat to +ive toqic OR gateto convert +i Sive logic oe Sek — + no keep variable as itis Find Oval. Apc + ABc + ABC Dual -— (A+ B1E) (A718 +0 (At@rc) if. we find again dvat then, ABS + ABC + ABC resviting same _eapression . For_any lagical expression , it two times dwat is used Self Oval AB+ 8c +AC Dual *— = (zB) (8+) (AtC) = GA (A409 = BA+ BC+ AC + AC a = ABr BC+AC (again same _eapression) In some of the logicat expression not all its dwal qives the same expression. - lacsmate _ PAGE=| In self Dual espression , if one time doat is used _resut in same eapression. 1 saci — n variable —>~ Self Dual = pera are n_vayiables then total no. of self dual eapr- amt 3 ae diss Then -% doal eapression. A—> sett dual —~A ] Total Self dwal eapresion A>A J ore 2. i 1 UW fer—n-a— = 4. Then _4 dwal expression t Raa ee AA ee dp For n-3 = a = 16 Then 16 dval expression. as A, A» B, 8,6, 65 ABSBORCA , ABIBCICA, €) | Complement *— if Y = a@c+ ABC + ABC complement iS, a S (+646) (AvG+6) (A+8+6) : ; ae= Ques | sop eapression for 34) for Pas form. Shaded __ region. As Ee AB+ AB +AG A(616) + AG A+A8 — = — (+A) (448) AtB (2.5) —» (in 0s form )form for shaded portion aac “ABC+-ABcr Acc + ABC + ABC + ABC — eatraxidad . = BG(ATA) + AB(E+C) + ACLBtG) = ABrBCt GA= Inplace of bulb if there is yesistor then answer remains the same but some drop. Truth table :- War rs In ploce of switch if there is a transistor. Ane Vee. @ For A=t. transistor - becomes shgt circuit - For two switch A and @ =A- (tC): 5 = (AB+ AC) 6 ABD + ACD.forthe follow! B and_c_ are twe A and ¢_ are false A ,Band-c are twe A,B and c are fals€ ten minimize the Ve forY yeh ( take min term = sop form) Bc + AG + ABC + ABE ec(i+A) + AC(it B) Bcr AG T f %p Y2o , then tone maa term (Pos form). + A logic ckt hove 3 input _A.6.¢ and op is F =4. when majority 70 of Ips are logic £- > minimizing eapression F (@ _Imolement _to7ié_ cht 8 c o < I 1 q = Retir Abe. Ab oe Nee Aec+ Asc + ABct AGC + ABE +4 ABC Bc(ATA) + Ack Bte). + AB (E+) Ags BC1CA- if asseateLOGIG GATES Basic gate “3 4 TuANDey a uewersnt gate NOR a 5 5xOR ] ~ Arithmetic _ckt Saal comporator , parity generator / checker , (Binary to qray , Gray to_Binams) eode Se x a? - Circuit shown in the fig are Buffer Astable MY Bistable MV “square wave.gengator. Yy_there is no feedback then it % butter. In Gviter if we apply oO then get 0 E » 1 i » noup 00 S/R. Bujfer_means whatever ‘the Wr ie the UP. [> But there is a feedbock and ihe oP is sinble if we give | os ve ,O/p is also 1 and if gives 0 then O/P iss o ber two stable stale. © 3 Hene it is @ Bistable molti vibrator. classmateee sy ext shown _'S Ac Q”p & rot stable sometime _1_and. sometime © ied _astable mmultivibrator itis also call Fotol time period (7) = 6 Tra — Ha no. of inverters in feedback. Ina ckt Stam in fi}. the proroption delay of each NOT e & worse ten frequancg of generator square _wove ©poe a oD The ckt show? in the fiq the propoyation delasy 0) each Not gate fg 2nsec. Then time pariod of generated— equove wove is, @) lens ©) Mn pet 212” 16ns | astable Multi vibrator, . square _ fs 2Ntpg 2 2x3x2nsec = wave .qenevator. nSec- AND GATE i= => Ye Blow Y any of the csp 1S tow ie logic 0".= Thus YP remains in “Q’ due to control yp disable. AND gate, =a “isnot -in-working state. © __s spirsl_{ Disable) ———— > ano gote is in workieg state o/p_ is ohanging in Enabled state In _ Trt logic family ty any Typ 1S open and float hen it will act as “1°. Th ecl logic family, floating input iil! ait as logic © 1 ‘= Question occurs mostly from ect and TTL. in Exam. Unused I/p’s i= A A= In moltipin (t/P) AN gate unused typ can be connected to logic 1 ar“ pull oul”. connected to __ logicaa ley Y=As (only for TTL) ——_4+7 if if is Tri_togie_family : “ten unused */p canbe cr? or fisted. (unconnected) _~ of Unneecessary 1/p attached to 6 , fan in will ef es. Best way to connecting unused pin U/p)_in connecting to _lagic" 4”. ‘= ___ Because be down. r AND gate is Y= AB =p == when any of the Typ 1s High tp oR gate then “OP” ig High. >| oR gae follows bath commutative _and_ Associative low. © a mmotative law - A+B = BtA A= ATS a= #ssociative law AtB+c = (AtB)+C = A+(6+C) 3 OP is changing a WP jis changing or _we 54 the gate is enabled. (osects]3 9p. 16 fined oF not changed it (g Said to be disoble a a3 aie Unused _I/p‘s :— : SAA + —In_oR~gate , usused t/p is connected 6 logic ‘o?- “purl down.” “ Lz Connect to one of the used 1/p fit is Ect then unused 7p canbe open or floated . In OR gate, Best woy of connecting the unused te is a 40 connect to logic ‘O°. A a B Se In the cKt shown infg. in TTL, for_the given 1/p_ OP is AND, OR .INVERTER OKE au p's are float then@)_ 0 Bw)! fc) AB (>) AB T{ all yp are jloating in EGt_then itis ‘0’ and Op ¥ = AB Ans.NAND GATE :— (@ubbied OR) me © disabe ( notdhonging tp Sze) NAND gate folly commutotive lao burner Jollow associative [tia only two qote not follow ossciahve law te universal | Gate INANBL “or eNORs ‘Gates unused 1/p “in NAND gate can 6e connect similar to unused Y/p in AND gate NOR GATE : (Bubbied AND) OR gate followed by NOT qale1 = drsable- and disable __ both are some as OR gote law and not follow associ= =| enabdl =| Nor gate follow commutative ate law. Geen Ate =) StA. eo meee ATE Cc Pern | unvsed tip in NOR G@te con be connectect similar to oR gate. memset TT ee | EXOR.o. XOR = Exclusive OR gate- =| oR gate is also called as inclusive OR gate = = no 8 a => when] a=6 , %p is low 16 ion i > phen AFB, FP is High ie. logic '!. PACE )O— Bojjer 4.+ inverter It is also catled controlled inverter. Note + A@A 20 A® A=) AGO Ag! Tt A@8=C then G) ASC = B o Bec % ABBAC Since, A@A “= Then we say. A® AOA =A odd no.of same Typ gives same O/p A® A®@A@A- O |and even no same @l/p gives 8zé and so on - -- Jas op. Hn is odd > if 9 is even B®@8e@8e----n = B, 0 Foblem:- The ckt shown in fig. contoins cascading of 20 EX0R gate. HX the Wp then Ye is. a = @) 0 S : SH) x 1 : @k ; gqip of even €xor gate have same OP.Exor gate follow both commutative and associative law. Exok gate is fellow available with two ips only. Truth table :— A B c Y (4@6 @c) ° oo ° Se: ° 1 1 So IO. 1 ’ ° 1 1 ° a mee 1 : 1 ON cael o ae ad (ee ° —_ 4 1 1 1 The Wp of ExOR gale is 1. when no. A ts at the -Ije is odd no. ees e logical expression =~ 2 ¥ = AG cl Ape we Abo Age = oot + O19 + 100, + (11 —> add no. of It’s. Y = BmCuz,4.7) =] The weauced form of this eapression.'s, AS Ee@c clncorate race(_[ 1]= whenever the wey same Pp 1S _HIGh- SOP expression = AB + AB POS expression - (Ar8) (A+) i ExoR:- AB +AB aS ExnoR: AB+AB (AtB) (A+ B)< : (4+B)CAtB) | ra + when A=B then O/p 1S High - therefore _coincedence logic ckt and also called as equivalent detector when A¥B The %p 1s law. Enatle and Disable =~AOAQDAOA= ft and so on: = a, if D- even 8 yf N= oda { =xoR and ExNoR is not always complement , it is comple- ment only when the no. of /p is even. and if vp is odd then GBOR and EXNOR are same. te Ap Be. Sho Bos > me. and, ASBBecmp = AV BOGOD = complement Find espression Of Ao BOG. Aoeo c : = (AB+AB) OC : — (AB+AB)G + (6+AB)C = (AB -AB)C + (AB+t ABC (Aer Aas = CAO6) = A@G. = AB+AB (Ae+AB)G + (AB +A8) C Bee +ABC + ABc + ABC = AS BEC.for GOR > o/p is 1 When odd ro. of Ss at sip In this _case., Y= A@BO@C = A@BOC Ans, EXOR and ExNOR are -never always complemented > Lt is complement only when even variable occurs. . ‘even no. ot 1S detector when no. of 5/P'S are Dexnor gate is even EXNOR gate is odd no.a VS detector when no. ot T/p's avA(ée6) +B ~ AZAG = (arr Tare) = _ATB_ AMS.Dd 1 gate _reqsived (AAs - B- Aa) (a:AB + 6:48) _ (A(AtB) + 6 (ATE)) AB + 6A = A@B pene? | irantesp. To implement—X¥ logic gate 2 NOT AND OR EXOR EXNOR | Zz. The min ‘no. of two. Typ NAND gate required... Probler:-_To implement _*¥ +W2, Sol Tetal no. of NAND qate ZeQrt The min no. of 2 input NAND gate requie’ xz ‘and 3 cancelled a we are Same gra is_ 3 Now the total no. of NAND ® gate = g+ Bubbled oR (= NANO) Av ees > 3NAND gate required -ext COLO ate ime ment sop form, only NAND gate alone. Jo implement pos form, only sNok gate alone. | it @tBHCtD), then min no. o| Gate. &) ' we 1 ' Twoleve) NOR-NOR. - Twolevel OR- AND = —Digital_circurts: combination ckt Sequential cKt ot Op is only depend esent T/p. > Present vey ear a Previous °/p No feedback = feedback. No” memory: 3 Memory. 2g. Hdl} Adder (HA) { Fa ——MDx DEMUx 3 €q> FlipFlop (FF) Register Counter.“COMBINATIBNAL_CIRCUT, ow (EEE) Procedure to Design = _ | ©) Tdentity vp _and_ YP. } t ConStrect__twth table a & Write logical expres rah EEL Ea a E “Minimize logical expression _ if possible es Implement loge circuits. _ SUM a 3 ' ° 1 o ' 1 ° Sscil | lS “No. 0} NoR gate ! s 24+3 35 W Tih table = An 8 Diff Barrows tio _logical_expression :~ pigerence = | AB + AB BARRO = AB ay Implement 3- A Difference 8ee! iogioa expression 10 AUB) = mn = roof NOR gate =©| FUU_ ADDER +— -— SS — mate aoe = = FULL ADDER Get Gas} “Fe CARRY. [er Tuth table = Z 4 A eC suM caRRY | o oo oO oO = SoerO me 1 Con 10 ia ° 10 0 1 imone 1 ° 1ot o 1 (Guiecne leno ! peste 1 1 _ |b tegical eapression 4% SUM = AGC s+ Ac HAGE ABC = AO SOC a = Em (2,4, CARRY = ABC t+ ABC + ABC + ABC = AB+BC+AC athe truth toble Cf carry shows the mazority oj Vs function. ue = 2m (35,67) = : ted Sed > SUM = 2ted E gi 2 Aesec ted C ie 3 In full adder each logic gate have pro jan delay of ta to provid sum or carry _ ofp, it requires = 2tpa ap{aed + © EERE __ —w ee Important ques: @ logizal expression for SUM = gb No. of HA and og gote = QHA, 1-OR @ Mir. no-cf NAND aed eee ee 9 wm Ns. of MUX. = ow Ka. of DEGODER = ¢ 1, x8) Decoder and _2-0k gate A® B@C CARRY = ABtBC+ACw Implementation of Full adder using NOR Gote = since A® Bec = A@BOC. NAND is replaced by NOR. The the ckt is Same only iad —_— [ c+(Aee) = ©:(A0B) + G-(AGB)= (ara) (c+ ABB) a SAG» ARGEE ARGH Eee ASE ae = AC + ABt BG+AB = c (AB) + ABPARALLEL ADDER =~ There are three type of adder 1. Serio) oder (we vorite with sequentiol okt) Poralle! addler. wok. ahead carry adden Gy) [> In serial adder only one Full adder LFA) is used _to of bits = Tt fs stowest adder. foroliel_ adder + “FA FAFA HA TIVO Gy AY Yor 4 bit adder (yor maa i SFA and 1 HA required Tes vs + orb FA 1S required (ome fraile) adder is used to add grove of bits Te add two N bit no. it requires Wt) Full adder and Half adder. oF, N Full adder or | (ans) Hol} adder and W-1) oR gotes requiredParallel adder (sats called Ripple carry . oddev. Propogation debby from vp array tO %e__array . Hence Rf also Krown as Ripple camry _ adder. —) < ‘S& In _paraile) adder each —FA will provide ~2-toqic_gate delay In 7 bit_parallel adder _ provide total delay of - = 20ta | LOOK AHEAD CARRY CIRCUIT :— b Disadventage ef parallel! adder (Ss carry propogation delay present AS no.of-bit increases- speed cf operation _ reduced - jo amd tS took chaak carry adler ts used. ee = : : = oP sum: (52) carry Conn Fe_= Propogation Se Generation term is Ac @ Br Gi = AO Bi = Accor SX =R @ Cina- =- AC + GE For tour (4) bit look ahead carry adder +— Lie. Az ®2 Ac Ao : 62 & & Bo Ten & = Ao @: Bo es a eB G&- Ar@ Gs Preeee As O Ee 2)© OCs look ahead carry generator “eapre: Cr= %CotGo Cr = FG a Gy = A(R CotGe) +G, = APoCoe Plo Gy — Gy = AC: +Gy = A PiPoCo + P2PiGot AG Gi C. = C3 tGs = PsPrPiP, Cot PaPsRGo+t Pa%eGit M3Grt Gy Sam ss 1424544 = (re) _ 4a35_ z Tota) no. of ANO Gate inside 2 no. of ANO Gate = nine no. of OR Gate 3| Toto! propogation delay _= 3| Tis is faster than _ parallel adder.SUB TRACTOR ¢ Dif]-(A-B-<) BARROW. ° oO [ =" sane eee estah otf — = (12,4.7)- ae o. BARROW AGc + AGG + AGC + ABC = Bc + A (6618) Fay VS add Asc two more .— A®6lE +c) +(At a) ect eRUe78) Ab ACHE zm una) ww Implementation = ~ A eeBarrow eapressian :— AGco * Age + ABCE Aac Ae(c+e) + C(AG+ AG) AG + c (AOB) AB +c( 8) = BARROW AB Full Subtractor usill be implemented with 2-H4S ard + OR Gate | Important “aves = no. of NAND goie ro. of NOR gate logcal expression for Oitieence = AOS@C logical_eapression for Sarrouw no ioe MuA i no. of Decoder :- 1 (3x8) Decoder and 20R gote AB+ACt BC oF, AB+ CCACB)COMPARATOR ihe a alldK- MAP t- is used when 0,1, and OY iS _qyophicol it In K-MAP K- map. Ie_is code representotion representation X {dant core) fs used > Groy Code _vepresentation i 3 ge ESS a 10 OL => each successve term LsB is bit “wo variable * M changed © only one| tn sor form 4 atl are ALL are don't care means ~ 4 variable 3 means. %p is nt care See TS Oe a \€o0 ° | “| FCA. B.i=. eet = f(AB.O HBO) a ai we toke @c then itis tedundont term and it must be removed : ose (1Ge 2 AG + 6c +AGC =m (0.1, 5.6-7) HABBO) = at ac Gc _ec_ af “ie oj oy - I a qiace) = AB+Get AB aa 2 = AG 2AB+Ac K-mos provide minimize ezpression bot not neccesarly unique. ic 20 sal* also - Sn 0.42, 5.2) + 2d (3/6)Care steal tea ae y 6B + AB m (0, 16,7) ec ats ae ig “Ty me =) ele G+ ae | $(AGcD) = =m(0,1, 4,5, 89,13, 715) = MO, 2,8,10,1G) + = ACS, 1S) pace [|FA, 8) = WH (0,3) + TAQ) S (4,8) = AeB = AB @: | 44.6.9 = 1™(4,14,3,5,7) =i orc 6te BE Bsc Sel- = a of [eimai ae ona ey 4AEBO = c+ (A+B) = < (A718)s20 function are ~same +f the positon of 13 are O's are same in K-mdp._and_if_the "S place o are placed -and 3 at o's place 15 are placed then the function is compleme +o each other. = 3. Problem — 26 - poqe -13 RS(tes methocl for voi ahe_expression yo" _ Toth table ) . 4 MPA RO ACN ABC B(A + AC) @(A7¢)fe) Sse} 13 11 is combinational circuits : 1p ,9ne at the te 1s tronsters 3 Depending on cartip! or select | to the 9% tine 5 It is select T/p Many to one ckt OF, then also _callel_as pata selector, Of. _ universal logic cut or , parauel | serial 3 cKt contrat yp) ame <—— to = oy Y ‘i =a Ty , i ¥ Ceymnbad of 07)eo Teuth ie tagica! enpression Y= SI, +S, ge Imptementahon :— = Wr Jn MUX , generally AND gate followed by OR gote. 6:1 MUK 2— Ze faa te easel SiSatas SiSo TsImplementation Implement no. of 2:1 MUXBm Bemewqeee SssS— art FEB + SIME SA =| Teerefore for 27x tr MUX x nived ee aext MUXMux as uPiversal +—hr Pa % | apf dn Spex (2:1) required for ExOR gate Exngk 8 de 7 y - ag + AS 8 a * : —= BS geur (231) required tor exndR gote. required ogni “MUX -= bee. 6 = a = Any HO variable function ‘s implemented” With 4 +1 EXNOR MOXx.yp AGC € ABE 7 ne oe ABC =e Tere) © ac (648) = AG + ACT aos — 1 Ts uxt = q ° fers * GS i d = reese = = =aeaee Ce a ee Bee Rec + AB +ABE a Ac Fst . ica) expression = Tm tementation of given 109} SwinieeseSp 1-4t1Mun ond t- nor aote : repuired. Implement logical expression _ $0AG,.0) = (ly 2/3, 5.627) PE AB as select line w AC wy BC Ww Ww XL @ @ =i 53 tit mux required ae ke To i,Any two variable jenchion _implemerl > using one il a es gome of three variable implement Slane uxi Mux and ane NoT AU Two W,. aa fe All Three’ = one Sxi MUX @nd one NOT —- one Sxit MUX y= ait Three : Some four. AU Three are teut implement All Four are implernented a: first = TM(O1, 47) comert it into minterm expression f= ereHazard pun ceor eis CcooIEy jopaation delay of the loyic eke See change at the Cp. case It: tos in TH there is propagaton delay of ro delay in ano gate= as dynamic Te Essential 3 occur in iio 2 occurs’ in Asynche eee in __ Sequential kt “Js accor in combina!’ 4 in aambinatonat ies = chreuit 2 Awd by adding occur ®- twolevel satic + Tasso “eveid stotic and _oynomis nom: Hazard d redundant terms Hazard :- a i- Tiese__Haords _tbt_ feels essential _can nat beY : a t ZA Becondar tena rat ace 4 - ¥ Semi random Serial access memor vite, > Read onty Al disk 9 magnetic tape Randor) access |) Random. 5 co ___|a Magnetic bubb Vottaile +) Non volataile = DvD ) Temporary ) Permanent A data (choiqed_ coup BI9S/ System program device) — : Fernt te —» DRO > Discric ive read _ onky out. RAM (Random access memory) = 4 Each rmemory tbcation if m bits are stored then capacity Cee vas ae with obit address po. of memory feation | static _ Stored LikeMemories a Row a Semi randon> E Serial access ss aot memor} 3 Reodonty All disk mognetic tape [5 Rantomaaess 3 CD 3 Mag netic _bubb IS Voltaile 3 Non volataile 2 Ovd *_—s| » Ferrite core fs Temporary [a Permanent HD 5 ep. = data (charged couple G10S/ System progrom | device) Ferrite core —> DRO — Discrictive read only out. RAM (Random acess memory) — _ Each memary beation if m bits ave stored then memory capacity @°x_m) With n-bit address - man. no. of merrory tomtron requir is Se __uSx 8 memory. 2x 20g See ‘2- address line 6 — data lines. ~ static Stored Sike FrDEMUK (DEMULTIPLEXER) Siege We and Many ofp. DeMux is combinational —eKt wwbich have one T/p _and_may o/e olepa on Select Iyp., ve is transfered to any _ of the ofp. Also known as 1 to many ckt % dato distritutor. Yo vi wth table :- Ss oO 3 hit BO VtG DEMUE 2 4Jmplementahon of Myber eder DEMUx From tower order: X4 DEMUX TRE pemox <—iL~ 1x2 DEMLY a= 7zel pemva, === AB ersox Tx2Sé DEMDX «EKG BEMOX a 1G C= Xu DEMOX zy y wx6L DENUX <4 > ( X#4QD EM OX fet See,a combinational ckt Which have many —t/p and rm« TA ig used 0 convert binary data to other code (biraky to €9. Binary to “ootak (3%8) _ re @cp to Decimal (4x10) 5 CD I Binary to Hesadecimal fl BoD seven_seqment =4_2 tof decoder fs — minimum possible decoder. 2x4 Decoder +— Ye iz | A Sse) 2 ned Decoder Ya a es = : ee aa ; = 2 sae Truth table — EAB | pfs iar ied ie 2 Oo xx oO o Oo Z 1 00 OG lon som) tor 6 SOS 190 Oe ie @ 0 0. oO = logical Expresmion -- youn A % AGE Ya ABE Ys = ABE Decoder and DEmux 2ENCODER * Eneader is the combinahionat eKt which have many many op is used to convert other code to Ginory octal to Binary Decirmp) to eco Hexadecimal to Binary Octal to Binary Enooder + OGTAL to Binary Tn normal encoder one of the Yp Bine 8 high and Binary available at the o/p In priority encoder no. of I/p iS Righ. Only _highe: no corresponding Binary is available at the op Truth toble fetta oO ° {7p and vvespor priorityee eres. Ta + Is =} Ty+Ist te th = pecoder contains AND Gate- pemox contains AND @ate 2 oR a@ote [5 ENCODER contoinsFLIp- FLOP. aan coe == = Tis _basic memory element. Soa a &D It can store? bits = L E FF have two ofp which have complemented to each « her It have two stable state hence itis known as @istable multi vibrator. a CONT INT 7— NAND. 0. SK latch NOR FE cKts FF Truth table EG characteristic table FF Characterishic equation | Excitation toble conversion from one to another simple CKt ‘ latch gate. the problem is, it hove only one nor gate insteed of A _using Not Iyp__then nor gate we use NAND or FF is not only used for storing bit but it abo vse dor freqiengy divider .=i.[s eR Q ° ° Invailid . (& ° 1 1 ui 1 o oO { ~ Revious state (no change) | o/p remains some i In SR latch ‘tf both gates are enabled ofp vermains same previous state and _bothare disable then invailid state _ SR latch using NOR gate *: @AND enable ist disable iso and, intOR- E= 0 | R i Ds then we cho seth Soe @_position “a z Aa | ¥ Previous State. oo}. ° ot lo 1 =e 10 [oO invalid (€-@-0) 7 =| SK latch 1s used 10 eliminate switch bouncing. =| Bomcing means vibmtion of switches when ON or OFFPrevious state. (An) } An, og! ___—>. Reset [2 ee ape 1 invoilidh | =< R&R _|2 Toth table is some as for NAND gale SR FF. eace[ TT J= Since S=t, R=! the de is iavailid becavse S-R=1 Ot | satisfy the above canditian - Excitation table :— a Disadvantage of SR FF is invailid. state Present when Sat andees. =| % avéid this JK FF is used-TK Flip Flop ¢— =k FF using ZK FF using nog gatelogical Expression :- rminimizahan — Exitation table .— Qn Gnas 3K 4f is Roce @rrourd Condition whioh Is 2 dptlop.D-Flip Flop += esi raisloe | Cok a 7K Twth table :— —ELK Qn+1 Be oO * an i of Characteristic table :— BD Gn Gon =? ano oO a 1 ° ' 3 Therefore it also calied transparent (ate ° i 7 i ee Excitation table :- Qn | © ° ° ' o T ’ [o} 7Excitahon = table -- Bn Gon “f=> AN tables-are inside J FF therelore it ‘s also : SK “FE universal dlip Jlap. FF = Flip Flop — one bit storing element Ga eiseas > Se 2. Set Resct Qn = JA, 4+KGn 2 3% = name of person who give the IC Ane = 5 = Qn = 2 Toqgle mode of JK = Ha :: a pecs al} All 7 diagram is fm Toggle modeost In tevel__ trigger ckt , Op may changes _ many time in single_ clock In edge trigger ,O/p may change anly ones __in single pbise. Jit = oiferentl 3 SSE vtf tpw = lansec thre = 1nse Then.- << lonsec—> ctock:- |? Ofe = a Then, To remove vace arround canclition s— [hpi eet tetne | tpdctoc, << teaex | In Jk FF. RAG occurswhen J=K=L. then 7 and teagt is “Bore than that of trdciocn. and therefore the Oe is changes several time in gingle atock pulse. [condition to remove ace arround _candlition :— WO __tedctoch << tare w Use of Masterslave_jflipflop- Ww To increase the propagation delay of _ ae hie dlop-Master Slave Rip Ropt __Since the yp of Stove _ never __Masterstave the Since Ve of stave ts ataays (1.0) or (0,1) E a Simee race arround condition gecurs only when the J/p is Gn. Deaas |= in MS FF, Op 1S change only when slave opis chang hy |= In™SFF . Master is tevel tmggered and edge ig clave [ is edge triggered _Conversion of one {f 10 Otber FF %- Frocector a > => Requived FF characleristic ) Available FF eacitation x ) write the logicat empressian for 7 and k:— : oNae on : ‘Dilan K =6TKFF 10 SREP: implementation :~ed a a a ata i] ig . R Ss jon == a Ro srt Linplementaty w)| sk FF to D FRG” 4 3 ©Se Tas Implementation :—T FFto SR FF c- RQ, Qnn T oO Ogre a s \RA ° - ‘86 Rana =a “halts ° ie ma|Ee Setup time + The min. time-reyived to Keep Jip at-propér level bojore atty apply f clock Note’ - Any ff ee Oata first th Hold time :- tee We apply Chk The min. time ‘vewired to 4eep tp is Same tevel after opplying lock .GISTER : 4 aa 7 er aie used to store group. of bis. eR) are cascaded in register =| Register are Jour tyre (Depepding on VP aba oP) 3- @- SISO (Serial_in_serial_ovt). ww 31P0 “| @ PISO = wy PIPO (most imp). al Depending an application thé _register_are two type: Ww Shift_ register a Storage register a | SISO (Serial in Serial ovt) :— tort me Benne, pa, o. a iA 4) al 4 al Cota 434, GQ, Av CLK. 10 1.01 ao Q o oO 7 SS o 2 SS cee 3 (Osa a n 2 _For_serial in register__the repires n_clook pulse | 3 In siso_reqister to store nbit data id require 1 clock j pulse - j 3 6180 register used to provide _n clock pulse delay to Tip dota. CN chsseute race 1 1) bit dota storageDATE |> Toprovide noit data serially out it requires (N-1) « pulse or . Sct a Of) aaa @)|_ SIPo (Serial in parallel out) :- eux 3 In siP0 register to provide nbit data serially in it requires clock pulse and provide parallel oe _it requires O chk pulse required 3 It is used to seria} to porallel converter 2 4 stPo is used 1% comert Temporal code to Spacial code 3 Blow to fat converter serial — x “Parallel = Spacial code é a] The ckt shown in the fig. if 4 Ort SIPO register Which in initially toaded with 1010 It stare three chk pulses applied then the. data if the system is. mi ay ote [ao 1 @ ttlot aT om vir aoe[arta loaded roip iy otk pulse applied continuously “after haw may che pulse again the data become _2080. Qe ef Srariable x-or is 1 if no. of US. is od. F a ajter 7-clock -| a} -| of of 9} -| ~| =] O19 control)=0 = Parallel! In @ntrol]-1 = Seriat_aut in PISO register- provide parailel in it requive Vclock euse ard to | provide o' serial owt (1) e100 Se et el ee tt tet te eet eT_PIPO beste a oe Sars > Piso is also used to convert Spaciol code to \temporiok code ) iS used as storage register. Parallel in it requires 1 olock pulse jor parallel out it requires 0 clock pulse = Important -— SISO S1PO PISO PIPO 1) a Seach Ghift loft register operation provide by 2 plied by 2" multiplicatiar Ty. “Th shift left operation peformed then data is muti Each shi{t right. aperation perjormed them data is divide oy 2 divided by 2”: ga If 1 shitt right operation performed al dota is 7—4 St) = with nt COUNTER Si- aE ted > Ganters are. basically used to caunt no of Glock pul “applied. it. can also be _for “prequency_ __divider, __ time measure >ment, it frequency — Sp Seen eR Rage neaniienorts Ee puise saith es 2s. 1 eat NAA 168 pysewilth = Total wrth = _.Also_ used for _wmavefarm __ generator. . maa. possible stage in the counter [we ms = 7,N __N= no. of stage n> no. of FF. — ‘ pq en clock pulse applied counters of two type: |e Asynchronous w Synchronous - Asynchronous Synchronous Different FF are applied |). All FF are applied same with different clock clack , : It © Stower 2 it is faster Fiaed count sequece 3. Any count sequence ig possi te. ve or down. Decoding errs “will 4 No decoding error. will present Present Ripple counter 5. Ring counter_|=> No. of stage use in counter mean = let Madm and mopn are cascaded modwlug of counter ie. if Mop 5 counter s ataqa Nap n counter n stoge C3) decaqde counter i& applied with frequency of toms then jp frequency ts foot = then (F fe witl act an Mao mn counter { et fer ee content ;~ Basic * Ripple _cavoter Non binary ripple counter Ring counter Johnson counter Synchronous series carry Synchronaus* parallel carry _ Synchraenavs counter design Gre Analysts _ Ripple counter = 2 3 2 2 Ttis a Asynchroaovs _ counter. Different FF used different _clook pulse. Toggle mode. 5 Only one FF &_oppli with eaternal ot. and ather {t's are ctk is froma fo pean tt ofp. (whether a @ @)_ The FF applied with |_entemat Clk will acts. as se SB3 bit_ripple counter 2— (up counter) x xt 40 topple for every © An change _ “An change fr when a, Geer 10 = Truth table :— | =| = D Belo 9} of ojo 7 ° ° 1 1 oO ie Me eT Pt) tl)3 In "bit ripple counter _propogation delay 0f each -4{ tray. then time perfod of -CLK is, Ca) =ive edge trigger > @ as clock up counter eve, > @ a8 clock up counter ~ive» » 77 @ as clook down counter => a as lox dlown eaunter +e ” ” 3-Bit Ripple counter (Down counter) <= _|= The ckt shown. 1” iq Go toggles “for every clock pulse - > @, toggles when Qs changes from 0 to 4. 34. toggles when 4. changes fromm _@ to 4. Twth table — clock g 1 me — &. 32 Ts is called ripple counter. because iS the ap of previous rr out pot ripple then called apple counter. the Qe is (000) and clock is applied then 1 _ 000 aun unwanted dr or decading error error. | _ als called frangent state “Decoding errars a1 transient state counter _dwe to propogation delay. avoid decoding error strobe signal strobie. 2 Er ke strobe signal is zerd for Oto and after thot i is one for neat clock. - then atl the Yp is zero dor the transient time -therefore due to strobe signal we can remove decoding error. [Fene = Mt + Ts | ae Te TP Pere Pt Pte tt PP = In vipple eounter with nf. man. possible state is 2”. a tepiency after n SF inthe Ripple counter ig Tn. (ie. for SFF Op is Tie)| S:#:5.% 0,7 ave Synchronous Ip. : ip lear “use to rest our #{.. or counter D use to set our Fe or counter, Ripple counter :—_ |" BD counter :— (Cecaxde counter) = 4 ftip top used. —| Oko} 9] 9] 0) 9/9) ° q\-|(| we uses erty as ond ay we _| clear ckt ; Sate -on a8 - a ! a 15 AU GoD counter is Deasede counter but reverse _ is rot te. eco counter ts Asymmetric gip_time Diagram . o/e frequency of 860 counter is t/q - low for 8 clock and high for 2 clock Yn Ax duty cycle is 20% In Asynchronous counter follow steps '~ 4. Trigger sive =Wwe clock =es counter ve Dowin . Freset_/clear = coo Presed vit Decoding tagic (Terminating logic) -connected to firsh ff 7p Erplanation:— = only One FF Op 1S high and remaining “a 3 In 4 bit ring counter 4 states _are there. (ie. For nF there is 7 States) Truth table :- Cue oO 1 2 3 @ s -==7 Sh’ synchronous unter the +ive edge o —ive edge, the o/p remains same Gi) Time Diagram :— . fit Bt hee a ss & - Las) a Mase shift ora generated waveform is 360/, |e = Appiodtion : [5 vseal in _Stepper_motor contro! = Advariage of Ring counter is leceriey is simple. +o decode no logic gate are required . t 3 _tast o/p can not be connected in the 37p of self stat ring counter F(») Johnson Counter t- [> Symmetns, Op wavetarn. cap) 2. 8-stages are there jor 4 bit counter Phase shift = 360 - 90 |5 Tt ts qust We SISO register vil Truth Table Ont oo [4 Totat no. of used stote . = 8 3 Total no. of unosed state - 2 8- atg- 8 Stote—o 5 Also_catled Twisted “ebunter , Mobies counter OF, creeping counter Or. Walking eounter or, switch tail counter -Tn Johnson counter to decode ‘each state one two Zep. AND / NOR gate used [ Disadvantage : lock out may occur (when counter enter into onuses state)carry pare [ BERET counter ALe _ series carry —up_counter ery clock pulse A, toggles Q, toggles when and block is applied . @o-! and clock applied a\o ~|o| 9] ~} - > To provide down counter ved 4G o/p to povide ‘nent stageALAND. (124) 2 Faster than series carry counter Disadvantage iS increased T/p pin’ of AND Gate \ > tere + tranee | Tox parallek earry counter. for faster logicont COISOICEED |_4pchronous Series carr _Expianattion :- _|2__ekt shown is — Synchronous series “carry fue: Ss Go _toqgtes dor every clock pulse _ Ao = 1 and Clock is applied. 5 Q@= Go-!' and clock applied ~ will toggles when @1=4,>@5 =) And lock [app 3 This ckt_ may be down counter when _@ is connectet 1 ea 3 we] 0) W] a) | > =|} =| 9] |] -|o}—|0]/-|°}-]°e}-|o GO} o}- -|-}a| 9] -|~= Faster than Series carry counter 4 Disacantage —is_increased We Fem > tree + trams = Syre —— 3 Ripple counter < Synchronous seria carry < Synchronow faratek carry counter for faster lore .uO | |) SLA Soha pce atresia ea = ie G2y Sequence O->3— 1 Identity no. of FF and Wp and %p. Constuct state table: logical enpression for WP_ Minimize Empleo mine chive [i> Stte table: | fesent state| Nextstate @ Go Qi4Qoe oo ’ 0 i ' t oO we logical eapresslon ;— D, = @@+@.@o =. & (GoGo) = Qigo + Q@ = A © Fr | | WW Imple menigtion -Content - = 2 Various ne. system | Arithmetic operation F = 2s. Number system and codes \- Tt zl T Weighted __Vawerghted, > Positional weighted 2 No weighted €g Binary , cotal €8. qroy code , Excess -3ax Decimal , Headeciral Boo code y > Anumber system with base or radia’ r cantains different digit_and they are trom (O— Fr eg Gor), t= Base or radian. Gase Different Digit- or --- 7 Oo, ---9 0, --- FAB ams 5 A.60.D.EF a 052.3.5-53t| Conversion (various number system) t= 4] Decimal to others % convert decimal na. Part _mouttiply convert : “(@s eS) = —— Giro01- 101) Gonvert (25-625) — (—)s. ayes 0-625x8 es wa z = Ans:- (31:5), |= When we go from higher to lower base | 6425416 gomert (254)ig — Hypare | CARS iain) Convert (@ru), — tu } ss er Others 40 Decimal : Ou kas A), __digit_with pasitional weighted then adh then, (=)io = Xik T+ ar ekg |5 7 convert any other base ¥ Fo dechral multiply each | convert (10101 -11), y ao 2 7 o i =a UA2"+ OXZ + 1X2" 4+ QR I‘'t! 2° 4 KD 4 1x2 = Wr r ies yy pais ee +P (Br FENve _coment (67-4)8= Cra s16' + 1x8° 44ax8! LOAT enka 320+ 56+, Ss s = SS eh elen convert (ST 4)ieQ = Cio ‘SKlext gh A Ges 87+0-25 = 87-25 Jig tS i convert (GAD), = C Nie DKIG 4 Et IO KG + 13 Z56 Kil + 1GO4F?3 2816 4160413 = (Q2989)y_ classmate ieee Ch each no. is represent by its gonvert (87-4S)g = Ca (amin. 100101), ginary to octal — convert (10110. 11), (e109 110 - 110), = @6-6), Hezatecirmal to Binary APA Binary to _Hexacecimal=— 3] Gach digit %s represent by 4 bit binary, (259A)4 = (—)2 (90100101 1001 1010) ,muitiptication ssh a J OM OE @l Molt ply = TOV aad &) teu ; 1010 wt ret 6 = oo0O— -| toio TAY temoraahiCt ral ay wae oe, re List __» 4 = 109, Fs Sw — |r Oo te fig ao z a (8)| Cctal. Addition ._ SUbhraction = Z O10= 0 741 =(8)= sls Oul=ar 2 eart =o) ae BPs Be Bay (47 = 10 aah 72 = 00 Sumof 2 octak no! a 243 wb s6e7 + 2l2 See 4SS 1032 Subhack ‘= aie HAS Sé Gy tore z =z — ——— re olscmmate. male eeComplements :— Oe complement 7 a Ls ¥%s complement (7 %5~) Binary => 1S Coit ae ork tent Soars nets: Decimal => 9's | Heaa, esi Ls 10's 16's es complement :— [3 Sobtroct from man. no. to the gnen m0 eg comp. of ( 1010) 2 ties TOTO, o1o1 To determine (¥-1)’s Ompliment subtract given ie) here: 1S complement of lool is, a Thani = =TOTToT @-| determine 71'S complemen? of octal no. sé7y Soll See —s6 7% 21703 c x 5 - = @:| Determine 935 compliment aj Decimal 2679 _ Sal Bde: = R26 79 WIA eS @:| Det. F’s comp. of} Hexa. 2689 FrFFE OS mor. no. possible In the given base. (mar: no. @=>}oar P'S complement iiss Fite Yo determine 1's complement first wmte Gay's complement then add tat tse Cat right most) Det. —2°s complement. of 10100. Fae) G0 Ans. Determine 2's _camplement of fO110 «ty 18 complement = 91001.00 7 C190 FOr Ans Ostermine 8°S complement of - octal 2670. F.comp - ner “ i v RE Fo Sior +1 190 Sif 10°s Complement of Decimal S690. g's = 9999 E = = Sto ae ze a Ane. Tefermine 1675 pamplemad oF _ Hera decimal 5989. ea er Fe =~ 52% 89 i ALB are | aeGobES 3— 8cb code + Binary coded—decimal weighted code. 4 bit Gode. 8421 code. Each decimal digit with represented with & bib” Oecimat Bco Excess -3 code 2900 Oo1t 0001 Oro3o 0010 OTot oolt orlo 0100 Omer oro; 1000 aito Too? ro aa TOTS 1000 TO 1 100T T1090 19] |S] | a) +) &} 9} ~/0 lo1o to He 11d vay = =f During Arithemetc operation if ‘nvalid- cp presen? the add 110 to get cOrvect result- invailid @CD code or don‘tcure- A combinational ckr iS applied with, “«oit 86D cade which Ss represenied ap O32, 0.0,, We is ¥., ¥-! a EE then __T/e eco is divisible oy 3. then logical expmssi & ¥ is. t c aOg D) + DdD,Bg +d, 5, OF Os0ud, DB, + O.Dg + DiD2Dg t B0,d, __ | Y= _ Osdud,5, 2 |For write eco code each digit (decimal) is wilte sepera wm 6CD es (S34). = (o101 oor 2100 aon 2.| Excess -3 code :— _ 3 | Excess-3ande = 8CD +3 Fi - =| _Unweignted code a 3} &bit code ie a Decimal Excess -3- code, ‘ o oot; ———_ ; : 1 2100 7 2 — ow — > 3 o1l10 — a : =rao a} | ffeteztensnt t ion eel 7 Talo @ = tort 5 anil) >| It i self complement code. 3| Only unweighted code which ‘s_selt complement is: Excesg 3-cade- | 4| The code which addition 4 9 Is self Complement code. i -es- BURL Ts 7 s 3321. Sal See . = eats ; Es Bae’torite 2421 weighled code - Decima) 242) et BOOS O001 LEOLISON TY je v4 o100 a0 6; I e100 etd) TTTO Pobmalcie Ginary to rosy code .— @) Binary to Groy =- Unweighted code - | Successive no. is differ by Alisa called unit distance ‘Also cyclic code, Reflective code. and Minimum error code. OES __ 63 82 6, Be Gs Gi GiGo_3Y| Oata Representation :— Data (cantwrite) presentahon ive _no- are fepresented in simiby represent —ive 70 in sign magnitude. zi sign bit ohange . In_''s complement represent write positive mm. and‘ then 1¢s ip 2s complement first write tive no. and complement for tort == (lot)| To find 5-4 Sw (4) olor 1100 iS | In 25 bit. at} Page - @), loan —_ ‘foot —> —oret) - Ittoot —» — (o0018 Binary “0000 ooo ©o0to OOolt 0100 otoar Oto Orit 1000 oot 1016 torr 11006 110)2tit °- range of _ Signed mag » S ' complement 2‘s complemen! :— _ nbit => —(@.) 2 + (a Stl, using 2 complement. _ ao1rol Es e100 Wo o\ wt x =a overflow may occur when same (two sign no. are added in signed representation] for__4 bit we can only reptesent. —(Q7) to +(o74,) (a5 +7) let__x andy are sign bit of two no. and = is resviton—E sign m0. then _conditon yor overflow is . F can BeDATE tet Cin = - Cout = carry into 8B carry from MeeDesign a synchronowy counter using OFF for the 02245236 —= 4 +730 = sice_1,6 is.unusedd used lock out condition ie, j—=o cur 60 Wb Toth_ ‘table i ae a Qa, @ | Ae, 00.0 oO Speier 1 900° ooo 000 3 To avid lock out change unused states stotes in state toble JO or, 34. Ho iio vifo oiftot wa oe Jovertapeing 2 4boit > 4 state requires 53 Design compiler . 3 less no. of state. ___© faratle) (O) _dval slope integrating type. lw Digital to Analog converter (DAG) z= “) Resowtion / step size, _ @ Analog Yp vottage a eaves Ss ) 7. Resobtion __@)_Error_ Accuracy a] Resolution/Step size > = Lt_change in aralaq voltage corresponding 0 rement_iq the Ijp ae ———— —— Resaluhion _ he ara Where Vy = reference voltage corresponding to logic 4 n no. of bits Aralog_/p vottags +— Vanolog’= __ Resolution % Pecimal equivalent of binary dai In a 4bit DAC reference voltage sv. if binary daly lca: is applied then analog voltage 3. Resalution - Ye ¥y, aa zs, a2 Ves = | Full sagle Ves—= Beate enor acceptable in Abdec’ser OAc's x 340 ¥ssxutton or step size SE | Characte ics Of AD&G’s :— Resavtion = 27-4 josere. Negnge= Uinaa -Venin so] (6+ 1-76) dB 6nd6Fesotution of R-2R Lodder typa AG's E ‘Resalution Resolution - 10:24 a oi 10 tsB = lomv 2 2 erroy = colibavate at 25° ic. error at 25% iszero wit ASC 3 Sim = _ elena ae enw 25°¢ R00". _je Digital to “Analog | Civeud Digital _to_Analog “cicvits — more current leBS_corrent BR WO Ise Tat kTe = Fs Re resistance = (2%2t) -MsB_ resistance. = _In_ weighted resists vAC the accuracy ts less Ave to use of diferent resistance. evercome this we use R-aR ladder use= eB aR __tadder_ et Normar ladder Inver tect toddler | x Non inverting x Inverting. _ 36it R-2R ladder :- ea = Adjecent to 2k slsB. -= Or Bye am (decimat equivalent = ebicaatbnany cela ies ~ 622746, a + Gy 2 _ Wt > Nooo NO oe ea tee zn tse CRs . Resaluhon x OCecimol +« gain. i -2R Inve rth 3 Git R ladder ( werting)Since A anda’ woth are Ground then (logicak er _virtval ground and ground) the switch ts at same potentrot then charging ond discharging of switth eroblon removed in previous cKt-fomine Tg eeoeree = [ets + 4b, re bo (_ = aibiy aa2 5 | in counter type ADC a compar used _'/ 37p stege to compare — 1/p endian age with reference vo! rovided by Dac feedback . A counter is used to count 0.of olock pvises a when Onalog wltage (Va) IS greater thah pac vali then -9p is 3. then counter count and if -analo yottage (Va) is tess than reference voltage (DAC voltage) then gp is 0 and counter _ stops _counti ani give the comparative dagital Man no. of clock pulses required or’ N bit conversion ts a Maa. conversion time = (2°41) Tex. Conversion time depends on 4/p_aralog voltage | Aso coiled fam, pe ABCFaratte) comparator type arr sister _vequired & 2 prionty encoder -allec|__ Flash aoc (fastest ana) |For nit pa __ comparator veqptired . t parole? comparator :— Chak L Ictock required - No clock pulsé is tequired. Therefore itis fastest. Abc among alt. Man no. of Glock pulse required for © bit conversion is which is Inside PIPO.Range of anol a Sy —. Noe ae RS SYve Vas 2¥eJg Sec- Start ef conversion Eoc - End of conversion . Ring counter is used to set the base Gontrol_ckt is used to reset (Vac Vy) in SAR Tpe aoc , ri counter will present | +o successively set the base. | Sontal cKt is used to reset Previously got bit whe Na £¥r. Zn_8AR Type Avec , ” clock pulse required for nbit conversion. __ no i iil ili ii iii i i i i a ui i i i i i ilDATE SAR is. mostly used in Orgital cK ith micropro. zi ssor, a a F == ae Da slope is alwoys greater than vq slope eee =e Be a T See J Teme a sige R= KF NTow In Qual slope -a aunter is usec to count dlock pulse convevion started intra Wy @uniter is. reset to zero and switch s is canneded to \y (analog voltage) ah inteqrater is integrating analog voltage _Yp of _ integrade will becom —ive voltage due to this comparator Yp i 4. and counter continues esl clock _ pulses, after 2” otk pbises again counter valve became zen. at this tme A control ck? —onect _suiitch ¢ te —Ne, During” Ve _integrabon upto T2 time %p OF integrator is —ive, _dueto thio counter in_amtbin clock pulses. at time Ta ofp of integrator cawme +i and comparator yp become 0when counter stops: _ VaTi VrCa-T) Mas Tay = Ve CN Tee) Va +2 Va 2 3-This is the most acwrote mec among ery 3 AL ripple and noise is seperated or _compresseo\ by capacitor. (therefore this have more accuracy due to integrator). -mar- 70.0 clockpulse = 2ad2™ Ee 2 ‘Flash - 4 Dual type = g™t face po AA Be Ve = Ave B: =F COfod OR Gate) use __ transistor -NAND Gate :- a > jaa 7% S os i 5] NOR Gate 5 P Me - Ss aate ai = c 3 Fe as oolt Et a 4 - 3 A — ee i to fo ———— ek [eer ESO 3 | when logic gate opis 4 Ch. OFF) it ellact a» current source. 3 | when logic qate opis 0 (TON) it will act as current sink. =a 3 [In coteif and saturation region transistor will act as switch . : Ef de Je Region } RB R86 cutofy R8 FB Reverse active ee Fe RB ActNe SRUPATOS, clessuete ss ae mee [11]| Granctevistios of logis family = Peqsgation delay = Uy) = ed_ in nsec. of — Cpe. — tw trot teat tein OFF ON on OFE 2 _Popogation delay is always measured from 507. \alve o the diag. [5 In Tr, ON to OFF time is more compare to OFF “st on time dve to saturation or storatge time Rower_ dissipation :— — = fewer dissipation by each logic gate. SEE a 2 iiaW}_ Fon out of logic gate that can be given by man. fanoub . Noise Margin — Itis the man. nose voltage that can be ackled tothe logic family which will not affect the %p. — =p O-—> Noe: | Bie:| overat (NMn, NMe) min, Tt (Register Transistor logic) familys A _ =e = > === = : | Gaon ie au == 3 Basic gate -Nor gate g-oited = ‘Sons ig = = FOM = sooPd 3 NM = O2V 3 Fant = 3 > wired AND used Disadvantage :—- 3. lower speed of operation 2. (009 Noise margin 2. towest fan out -oare [J [i OCTt_COvect tainted Tanatalen LgieYE RTL logic family i} vp resistonce removed then resular is Bere Saas : tog 2 4Onsec aera lig? ss _| Disadvantage =] aes Current Hogging : : at ee OFF OFF 1 OFF Ono ar TON OFF, o You OFF oF = iene Begging et a sj In ven logic . Y t. switch different. characten'shcs are use the. Tr having lower Veesar then first om and it willna allow cther Tr to on. this phenomenon is 4nown as cure Hoggin: Inteqrated Injection logic Cxr*L) ?— Its injecting the urrent into Gase_ Ke wher | Was Ao] —_—= ¥ When Ais high the current Hows through the base of Tr ! _ te. Tr. most be oON- Tu covers jess space — ie Tt hove high density. Ir iS qqyuivatent to _NoT date. classmate| current Hogging. 1 3 Tree is no problem ot FON = O-1fP7-=O-7PIS Best FOM amang all _ logic family. = “ons. Fon ott = 8 Ssh at? {aa usr. - .G-99 ae used ist — 100-100 in “this eS vist - — >1000. | In Ti logic, due to integration cf PNP and NPN +r, it Occupies tess area hence density are mare in TEL bogic It is mostly vseA in MSI ond USI logic family . Also called MTL (Merged logic family) _dve to inteqration of; Transistov-DTL (dade Transistor logic) family AND date followed by Nor gate. New ROK resister used only for -digcharging the unclion capacite -ce. The capacitance which. is discharge. is Transition cap. Cec. The lat is called gasvé orc qate. In this any one of the i/p_ is Tp are low: , Da @ng OF Dg Will become forward bias Band 02 “will become “reverse wias due to t TT tsorr and %p is 4 eg when all the wp's are high then. Daand 0g became reverse bias. ond Rand Pr will became forward bras and t tg on ~aMd Op is tow. = low. or G20 the where as The basic gate 's WAND gate sons. Bmw ao fdiss = FOM = 240 PF NM = a7sv Fanott = 3 TE provides wired ANo operahon. _yNec To increase far aol _we intraduce Ww in place of Diode. SKA resistor used to lower the Ty current. classmate called STANDARD woaitttTreshold logic Diode is Used inplace of D2 2 Zener = NM= 4- SV (Highest noise margin) 3 Since in DTL atl diode and ‘Transistor 1s —ive A temp coafficient ( 9X = e-25~v ec. 2v gons SS mw x 5000 PS. 4950 PI 8 NAND gate gate = maygin = 4N-SYV.Transistor 109 je) family 2 Trt C Tras Multiemitter transistor. Iqhe oxt Shown in fig. is standarct TTL logic family “eadically, have three stage: FE ® Mothomitter s/p stage wb Phase __ splitter . Ww “Totem pole oo active Pullup use Tr active pullup. o/p stage - of Tr Te (Te) conneck ta Vee. + Operation low- than ES tow. oF alt ups are qurchon is FB. (de= FB). and catlector tose ( Je= St is R6 | ig in active mode. due to this Th T and 3 are, OFF ( in wtoft...region) where as Ty in_‘s SAT op os 4 all the We's are high then Je (ee Junct”) io RB, and Je (68 Junct”) 6S Fe. (the of _overation fs Reverse active. vcs (LT) = Any one of 3/P ‘Hence When Cham mode dassate i 3DATE T ard 13 are in saturation anol cutoff Hence Op Is zero. Os) — Typ vottage at whiok Ty. takes logic 3. lower power: dissipation _ 2. Higher speed of _aperotian s Higher fan out ig wot ane in wed logis o—— 3) To provide- wired - AND. logic. open collector amnfig is used .*so | 130 A vesiator usecdl collector 19 O/P slatge b vednce ripple or noise qaneralion, 4 in po high frequency ‘of operation , In TTL if any yp is open it behaves a% logic | Clamping diodes ‘are connected in /p stage ‘olor davir } high frequency of operation > riaging, to_ grote bar C” Clamping DB. removes _ ringing Ff high Jrequency aperatior There are __alifferent_ type of TTL’ - @) standard TIL @&) Migh speek ©) low power _(9) Soho tt hy TersoOUUSe ma 2 Ty standard are Logic family it Resistor valve reduce then tar reduces and Known as high speed logic family. ~ tol = 6NSec. Zeid Saipaleniecreckeaent Co low spescl pdier tm -- In TT then. power known as logic family” if Resistor volwe increased) dissipation \ -reoluced and: resuttant is low power logic family. Sabottky diode :~ [ T{ svhottky diode is used blo collector and Bose region then it will Storage time ard satoration delay. remove the fomily ““nown as Schottky diode TL.ECL (Emitter coupled logic family) : Itis never qo in saturation region. S “ork only in cutof{ and Active region. ip z Jt _'s tastest logic family dve to work in 3 Active anc cwtott region. (Bemuse it is nom saturated) t 2-170 : 15% __tr= nsec fanout = 25 It__basically comtanw% contains two stage. UW) __OifferentioL ame" We stage- @- cc or Emitter follower /p Sloge - Ove to use Of O.A. complementy Yp are available in Ect logic fomily (NOR /oR) gate. Ove to use of cc Stage in the ofp fanout is high Negative spikes donot Offect the tronsistory due to ~ie power supply . ECL uses ~ive power supply. ue fo. this any spikes or _negativa witage not offect operation ted = Ins = fais = SS™w fom = SSPT Fanoot = 25 Mo= o3v senate: ox COOLED Se 1égic 1—mode—orty SSE vottagre Supply fe eQonve a| Ect provide. wired _ AND: logic 4 Sal Bp © G@FS)+ (c+d) z - a = Tt any 3/p is open then itis logia O°.ty channel logic logic. P-channel _ : logic 0" - logic Lo = Since FET 1s voltage variable vesistor hence {nMOS cirevit in place sf reg! vesistor we use MOSFET NMos Not Gote + - |GMOS NOT Gate Vino Yoo 2 | fewer issipahon +— @ stoic Po = = t During logic 0 OF logic P- orDATE _GMOS —_NAND Gates Bit T% Ts Ty O ON ON OVE OFF hd ‘ | Slols# _Highimpedence ° o 1 ae _-Symbol_of Transmission qate = _ Total no. of transistor So 2t2t 6 cmgs _monoslable multh vibrator +— a