How does a buck converter manage the voltage conversion process during its switching cycle, as explained through the inductor’s role?

A buck converter manages the voltage conversion process through its switching cycle primarily by regulating the inductor current and voltage. During the on-state, when the main switch is closed, the inductor is connected to the input voltage, storing energy as its current increases linearly with a slope proportional to (Vi - Vo)/L. When the switch opens, the stored energy is released through the diode to the output, causing the inductor current to decrease with a slope of -Vo/L. This two-phase process ensures that the average output voltage is a portion of the input voltage, allowing step-down conversion efficiently with the current flowing steadily through the load .

Discuss the impact of collector current variations on BJT saturation and the implications for base drive in a dynamic load environment.

Collector current variations significantly affect BJT saturation levels, impacting the required base drive. When the collector current decreases, for a given base drive, the transistor could be overdriven into saturation, leading to higher stored base charges and thus slower switching times and greater on-state losses. Conversely, increasing collector current can drive the transistor out of saturation into the active region, possibly affecting performance due to insufficient drive. In dynamic load environments, this requires adaptive base drive schemes where the base current is proportionate to the collector current to maintain optimal operation without over or under-saturating the transistor .

How does the Baker’s clamp technique improve the switching speed of a BJT during its operation?

The Baker’s clamp technique improves the switching speed of a BJT by preventing the transistor from fully saturating, thereby reducing the stored base charge. It clamps the collector–emitter voltage to the Vbe(sat) value using diodes, which means Vce is never below about 0.7 V, thus keeping the transistor at the edge of saturation. By avoiding full saturation, the turn-off time is significantly reduced because the base charge that needs to be removed is much smaller, thereby accelerating the switching speed .

What is the purpose of using an inductor in BJT drive circuit-3, and how does it improve the turn-off time of the power transistor Qp?

The purpose of using an inductor in BJT drive circuit-3 is to improve the turn-off time of the power transistor Qp. The inductor stores energy when Q1 is conducting, and during turn-off, it acts as a generator supplying reverse base current for a fast turn-off of Qp. This process limits the current in the inductor to ib through the resistance R2, and when Q1 is cut off, the stored energy ensures a swift transition by preventing a sudden change in current. This reverse base current expedites the switching off of Qp by quickly removing the base charge, enhancing performance .

Why is it necessary to equate the rate of change of state variables to zero in circuit averaging methods for steady-state solutions?

Equating the rate of change of state variables to zero in circuit averaging methods is necessary for determining the steady-state solutions because it simplifies the dynamic components to static equivalents. This condition models the averaged effect over a complete switching cycle, ensuring that the derived equations reflect a balanced state where the accumulated changes in energy from inputs (i.e., sources) and outputs (i.e., loads) are zero. It is crucial for designing systems like switched-mode power converters to ensure consistency and stability in their operation over time, preventing transients or fluctuations that could disrupt performance .

Describe the impact of using a capacitor input filter in single-phase rectifier circuits on output voltage ripple and power factor.

Using a capacitor input filter in single-phase rectifier circuits significantly reduces the output voltage ripple by storing charge during the peak voltage periods and discharging during the troughs, smoothing out the rectified waveform. However, this improvement in ripple reduction comes at the cost of a poor power factor, as the capacitor draws peak currents from the supply predominantly during the peak parts of the input waveform, thus distorting the input current waveform. The ripple reduction is beneficial for downstream components, but the reduced power factor implies higher apparent power demand from the source, leading to decreased system efficiency .

In the context of power electronics, how does an anti-saturation circuit like the Baker’s clamp ensure faster transistor switching?

An anti-saturation circuit like the Baker’s clamp ensures faster transistor switching by preventing full saturation, which otherwise increases switching times due to excessive stored charge. The circuit clamps the collector-to-emitter voltage to a level just above Vbe(sat), reducing the base storage time by ensuring the transistor operates just on the edge of saturation, thus minimizing the charges that need to be removed during turn-off. This facilitates a quicker transition to the off state by lowering both the energy and time required to extract the stored charge, leading to improved turn-off speed and reduced switching losses .

What are the design considerations for the inductor in an LC-rectifier filter to minimize output ripple?

The design considerations for the inductor in an LC-rectifier filter to minimize output ripple include selecting an inductance value that is high enough to maintain continuous current under varying load conditions. The inductor must be adequate to prevent the core from saturating, thus it should handle the peak currents without maximum inductance causing excessive voltage drop that affects line regulation. It should also provide low parasitic resistance to minimize losses. The quality of the inductor core material is significant as it affects losses and efficiency, with the aim to achieve low ripple content while maintaining stable and efficient operation across the desired load range .

Explain how the bond graph method enhances the accuracy of modeling multi-domain physical systems compared to traditional transfer function methods.

The bond graph method enhances the accuracy of modeling multi-domain physical systems by inherently accounting for the loading effects up to the first stage and handling multiple energy domains in a unified framework. Unlike traditional transfer function methods, which assume infinite input impedance and zero output impedance, the bond graph approach allows for variable interactions within and across domains, providing a more accurate representation of real-world systems. It explicitly models the energy exchanges in systems, representing both effort and flow variables, which offers a more holistic picture of system dynamics and behavior, aiding in more precise control and analysis .

What role does a bleeder resistor play in LC filter circuits, and how does it enhance circuit performance?

A bleeder resistor in LC filter circuits serves to discharge the capacitor slowly when the load is disconnected, ensuring safety and preventing any hold of charge that could present hazards. Additionally, it stabilizes the performance by continuously providing a path for the inevitable leakage current, thereby maintaining a low voltage ripple across the capacitor. This helps in enhancing circuit reliability and minimizing voltage spikes, ultimately achieving a more consistent and efficient output under different load conditions .

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Chapter 07.

indd 421 3/13/2009 7:08:49 PM

Chapter 07.indd 421 3/13/2009 7:08:49 PM
Power Electronics
Essentials and Applications
Power Electronics
Essentials and Applications

L. Umanand
Centre for Electronic Design & Technology
Indian Institute of Science
Bangalore 560 012
Power Electronics
Essentials and Applications
Copyright © 2009 by Wiley India Pvt. Ltd., 4435-36/7, Ansari Road, Daryaganj, New Delhi-110002.

All rights reserved. No part of this book may be reproduced, stored in a retrieval system, or transmitted in any
form or by any means, electronic, mechanical, photocopying, recording or scanning without the written
permission of the publisher.

Limits of Liability: While the publisher and the author have used their best efforts in preparing this book, Wiley
and the author make no representation or warranties with respect to the accuracy or completeness of the
contents of this book, and specifically disclaim any implied warranties of merchantability or fitness for any
particular purpose. There are no warranties which extend beyond the descriptions contained in this paragraph.
No warranty may be created or extended by sales representatives or written sales materials. The accuracy and
completeness of the information provided herein and the opinions stated herein are not guaranteed or warranted
to produce any particular results, and the advice and strategies contained herein may not be suitable for every
individual. Neither Wiley India nor the author shall be liable for any loss of profit or any other commercial
damages, including but not limited to special, incidental, consequential, or other damages.

Disclaimer: The contents of this book have been checked for accuracy. Since deviations cannot be precluded
entirely, Wiley or its author cannot guarantee full agreement. As the book is intended for educational purpose,
Wiley or its author shall not be responsible for any errors, omissions or damages arising out of the use of the
information contained in the book. This publication is designed to provide accurate and authoritative
information with regard to the subject matter covered. It is sold on the understanding that the Publisher is not
engaged in rendering professional services.

Trademarks: All brand names and product names used in this book are trademarks, registered trademarks, or
trade names of their respective holders. Wiley is not associated with any product or vendor mentioned in this
book.

Other Wiley Editorial Offices:

John Wiley & Sons, Inc. 111 River Street, Hoboken, NJ 07030, USA
Wiley-VCH Verlag GmbH, Pappellaee 3, D-69469 Weinheim, Germany
John Wiley & Sons Australia Ltd, 42 McDougall Street, Milton, Queensland 4064, Australia
John Wiley & Sons (Asia) Pte Ltd, 2 Clementi Loop #02-01, Jin Xing Distripark, Singapore 129809
John Wiley & Sons Canada Ltd, 22 Worcester Road, Etobicoke, Ontario, Canada, M9W 1L1

First Edition: 2009

ISBN: 978-81-265-1945-3
ISBN: 978-81-265-8016-3 (ebk)
www.wileyindia.com

Printed at:
Foreword

T he book that you have in your hands is the outcome of years of patient but enthusiastic learning and
exploration of the field of power electronics by its author. You may feel a bit apprehensive in coming to
terms with more than eight hundred pages on this topic; however, a closer look at the table of contents will
reveal the comprehensive coverage of the subject, explored from many angles and with various tools. This
book, indeed, reflects well the professional trajectory of its author. Having known Dr L. Umanand from his
student days and later as a colleague at the Centre for Electronics Design and Technology, I had the pleasure
to interact with him during his entire professional career and share his passion for power electronics. I can
clearly recognize in this book that same passion that he progressively developed for various aspects of the
subject.
He has taken up the challenge to present here a comprehensive synthesis of the field with the required
theoretical approach, combined with the pragmatism that comes from experience accumulated through
years of direct involvement in design, development and testing of the power electronics systems. This,
together with the originality of certain topics like Bond graphs, Design of Magnetism or Design for
Reliability, will surely make this book stand out.
The book reflects equally well the deep interest the author has taken in the last few years of the “teaching/
learning” process. The learning objectives of each chapter are clearly stated and the material is illustrated
with numerous examples. The reader is also challenged throughout the book with numerous questions,
problems, laboratory assignments, that, if carried out sincerely, should ensure proper anchoring of the newly
acquired knowledge.
In spite of the limitations of any written material, I wish that through this book Dr Umanand will be
able to inspire you in sharing his passion and enthusiasm for the subject as he does so well with his students,
even if you miss the immediate proximity of his broad smile and great sense of humor.

Andre Pittet
Chief Project Advisor
CEDT, Indian Institute of Science
Bangalore

PE_Preface.indd v 3/24/2009 7:20:16 PM

PE_Preface.indd vi 3/24/2009 7:20:16 PM
Preface

T he subject of power electronics has been treated in numerous literatures with various viewpoints and
styles. At the outset, it may appear as though one more book is being introduced into the market,
which may at most be a marginal update on the existing literature with the same topics that are addressed in
other books. Likewise, I would like to reiterate that the topics and concepts covered in this book are not new
as one would expect, considering the field of power electronics is rather mature. Notwithstanding the
maturity of the field, I must add that the topics in this book are neither old wine in new bottle nor a
marginal update. Power electronics that initially started its career in processing power revolved primarily
around devices like the vacuum tubes, mercury arc rectifiers and, later on, the thyristors. Power electronics
has come a long way since then. Technology has improved by leaps and bounds making the power devices
more closely to an ideal switch, and the control of the switches are performed in the discrete domain with
complex control structures. Thus, power electronics now spans a very wide knowledge base such as power
devices, drives, circuit topologies, magnetics, system modeling, control configurations, digital processing,
thermal and reliability aspects. If all these aspects are to be treated in a single book, then the topics will, in
general, have a superficial bearing. If the topics are to be treated in depth, then it becomes difficult to
accommodate all these topics into a single book. Here in lies the challenge and hence this book.
All the topics discussed in this book have been handed down from my teachers and teachers before them
by way of exhortation; and to them, I offer my sincere salutations. In the run up to this book, I must say
that I have been indeed very lucky to have been tutored by some of the best minds in the field. Every topic
has a flavor of the teaching styles of my mentors. From the confluence of the teaching styles of my teachers,
I hope that a style will emerge that I may call my own. If the topics are well treated and addressed, then the
credit, I must say, should go to my mentors; and if there are mistakes which I presume there will be some, I
am solely responsible and will make efforts to correct them in future editions.
The book has been broadly divided into two types of topics: (a) circuit-oriented aspects and (b) system-
oriented aspects. The first seven chapters deal with circuit-oriented aspects of power electronic systems, and
Chapters 8–15 deal with system-oriented aspects like controls and reliability. Chapter 1 discusses the power
semiconductor switches which are the main building blocks of the power electronic systems. The treatment
of the semiconductor switches addresses static characteristics, dynamic characteristics, losses and modeling
issues. Chapter 2 discusses the drive circuit requirements of BJTs and MOSFETs. Typical drive circuits and
their designs are dealt in this chapter. This chapter also introduces the concepts of the series and shunt snubber
circuits for power semiconductor devices that behave as power switches.
Chapters 3–6 deal with the power electronic circuit applications. Chapter 3 is on the topic of AC–DC
converters or rectifiers. This chapter discusses single- and three-phase rectification topologies along with a
detailed discussion on the popular rectifier–capacitor filter circuit addressing its design aspects. The
rectifier–LC filter circuit is also discussed. This is followed by a discussion on controlled rectification. Chapter 4
does not fall into the switched-mode category. This chapter addresses the linear regulators wherein the
power semiconductor devices are operated in the linear region. Apart from design, the analysis of the linear
regulators by progressively including non-idealities is dealt with in a systematic manner.

PE_Preface.indd vii 3/24/2009 7:20:16 PM

Preface viii

Chapter 5 discusses the DC–DC converter application. The primary non-isolated topologies of the
DC–DC converters are discussed, followed by isolated converters and other special converters. The discus-
sions in this chapter are based on the steady-state analysis that primarily addresses the component design
issues. Chapter 6 handles the DC–AC converters or inverters. The various generic topologies are explained
followed by a detailed Fourier series analysis of pulse-width modulation strategies for both single- and three-
phase inverters. Chapter 7 is a generic topic on magnetic devices that is needed for all applications in AC–DC,
DC–DC, DC–AC conversions and isolated drive circuits. This chapter discusses the general principles of
magnetism applied to design of inductors, potential transformers and current transformers.
Chapters 8–15 discuss system-oriented aspects of power electronics. Chapter 8 discusses the different
modeling methods and their applications to power electronic circuits and systems in order to obtain a
dynamic model. Special emphasis is placed on the circuit averaging method, bond graph method and the
space vector methods, including detailed discussions with application examples. Chapter 9 is not strictly
related to power electronics, but the topics discussed here are essential for designing controllers. It is a cock-
tail of many topics such as z-transform basics, digital filters, sampling, analog-to-digital conversion methods
and performance specification issues.
Chapter 10 develops a formal and systematic approach towards design of controllers for the power elec-
tronic systems, wherein the dynamic models are obtained from the concepts of Chapter 8. Both the classical
methods of controller design and the state space methods of controller and estimator design are addressed
with more emphasis on digital controller and estimator design. Chapter 11 is the extension of the state space
controller and estimator design with focus on optimality and robustness issues.
Chapter 12 discusses an important implementation aspect which is discrete computation methods. As
most of the control implementations of the power electronic systems are in the digital domain, a detailed
discussion on the numeric formats and practical arithmetic algorithms are addressed. This chapter also dis-
cusses the implementation of important components like the PI controller and pulse-width modulators
within a digital processor. Chapter 13 discusses yet another important and practical aspect of power elec-
tronic system which is the thermal aspect. This discusses the heat transfer mechanisms for conducting the
heat away from the junction of the power semiconductor devices to the ambient. The selection of heat sinks
for the power electronic applications is addressed in this chapter.
Chapters 14 and 15 are devoted to reliability aspects. Chapter 14 discusses in detail the concepts of
modeling systems from the reliability point of view. Chapter 15 presents the methods for predicting the reli-
ability of a system. A formal and systematic method to predict the reliability of circuits by part stress co-variate
approach is presented by integrating the functional and life aspects of the circuit specifications at the design
stage itself. A MATLAB based toolbox called reliability for electronic circuits (REC) is included in the
accompanying CD. This toolbox is developed based on the concepts presented in Chapter 15.
As is evident from the topics and the chapters, the vast area of power electronics cannot be handled in a
single semester course of the engineering curriculum. In order to handle the topics for semester duration,
the chapters may be re-organized in the following manner that is only suggestive and also not exhaustive.
• Parts of Chapters 1, 3, 4 and 7 are a possible combination for a course on linear power supplies.
• Parts of Chapters 1–3, 5 and 7 are a possible combination for a course on switched-mode DC–DC
power supplies.
• Chapters 5 and 7 can be suitable for a course on DC–DC converters.
• Parts of Chapters 1–3, 6 and 7 are a possible combination for a course on inverters.
• Chapters 6 and 7 can be suitable for a course on inverters along with pulse-width modulation
strategies.

PE_Preface.indd viii 3/24/2009 7:20:16 PM

Preface ix

• Chapters 5, 8–10 can be useful for an advanced-level course on dynamics of DC–DC converters.
• Chapters 8–11 by themselves can be suitable for an advanced-level course on control of power elec-
tronic systems.
• Chapters 5, 7, 12 and 13 can be a possible combination for a course on implementation aspects of
DC–DC converters.
• Chapters 6, 7, 12 and 13 can be a possible combination for a course on implementation aspects of
inverters.
• Chapters 14 and 15 by themselves can be useful for a course on reliability of power electronic systems.
• Parts of Chapters 5, 7, 13–15 can be suitable for a course on reliability design for DC–DC converters.
• Parts of Chapters 6, 7, 13–15 can be suitable for a course on reliability design for inverters.
I must acknowledge that though it appears that I am the sole author of this book, the material in the book
has evolved over many years with constant interaction with my teachers, colleagues and students who have
directly and indirectly contributed to the knowledge base of the book; my sincere salutations to all of them.
For the past year and a half, I have not given suﬃcient time to my family and the matters of the home
due to the long and late hours spent in writing this book. My wife and son have been very patient and sup-
portive in this aspect, awaiting the time for the completion of the book. I sincerely acknowledge my gratitude
for their continuous support.

L. Umanand

PE_Preface.indd ix 3/24/2009 7:20:16 PM

PE_Preface.indd x 3/24/2009 7:20:16 PM
Contents

Foreword v
Preface vii

1 Power Semiconductor Switches 1

1.1 Ideal Switch 2
1.2 Diodes 2
Static Characteristics 6
Dynamic Characteristics 7
Diode Classiﬁcations 8
Diode Parameters 8
1.3 Surge Current 9
1.4 Thermal Viewpoint 9
Diode Model 10
1.5 Bipolar Power Transistors 11
Static Characteristics 13
Dynamic Characteristics 14
Calculation of Power Dissipation in a Transistor 17
1.6 Safe Operating Area (SOAR) 19
1.7 Paralleling of Transistors 20
1.8 Darlington Connection 21
1.9 Power MOSFETs 22
Static Characteristics 25
Dynamic Characteristics 25
Paralleling of MOSFETS 29
Handling Precautions for MOSFET 29
Remarks on BJT and MOSFET 29
Power Dissipated in a Power MOSFET 30
Model for Power MOSFET 30
1.10 Insulated Gate Bipolar Transistor (IGBT) 30
Static Characteristics 34
Dynamic Characteristics 35
Remarks on IGBT 37
1.11 Thyristor Family 37
Silicon-Controlled Rectiﬁer (SCR) 38
DIACs and TRIACs 42
Gate Turn-OFF Thyristor (GTO) 44
MOS-Controlled Thyristor (MCT) 46
Concluding Remarks 46
Laboratory Exercises 47
Fill in the Blanks 51

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xii Contents

Descriptive Questions 52
Problems 53
Answers 53

2 Drive Circuits 55
2.1 Transistor Drive Circuits 55
Turn-ON Behavior 56
Turn-OFF Behavior 56
Characteristics and Classiﬁcation of the Drive Circuits 58
BJT Drive Circuit-1 59
BJT Drive Circuit-2 59
BJT Drive Circuit-3 60
BJT Drive Circuit-4 61
BJT Drive Circuit-5 61
BJT Drive Circuit-6 62
BJT Drive Circuit-7 64
BJT Drive Circuit-8 65
BJT Drive Circuit-9 65
BJT Drive Circuit-10 66
BJT Drive Circuit-11 67
BJT Drive Circuit-12 67
BJT Drive Circuit-13 69
2.2 MOSFET Drive Circuits 70
MOSFET Drive Circuit-1 71
MOSFET Drive Circuit-2 72
MOSFET Drive Circuit-3 73
MOSFET Drive Circuit-4 73
MOSFET Drive Circuit-5 74
MOSFET Drive Circuit-6 75
MOSFET Drive Circuit-7 75
MOSFET Drive Circuit-8 76
MOSFET Drive Circuit-9 77
MOSFET Drive Circuit-10 78
MOSFET Drive Circuit-11 79
2.3 Snubber Circuits 80
Turn-OFF Snubber or Shunt Snubber 80
Turn-ON Snubber or Series Snubber 83
Concluding Remarks 85
Laboratory Exercises 86
Fill in the Blanks 91
Descriptive Questions 92
Problems 93
Answers 94

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Contents xiii

3 Rectifiers 95
3.1 Uncontrolled Rectifiers 96
3.2 Rectifier Circuits 96
Single-Phase Circuits 96
Three-Phase Circuits 103
3.3 Capacitor Input Filter 109
Design of Capacitor Input Filter Rectifier 110
Turn-ON Currents and Surge Limiting 117
3.4 Power Factor 121
3.5 Rectifier–LC Filter 124
Output Ripple 127
Turn-ON Current 128
Design Summary 128
3.6 Controlled Rectifiers 128
Single-Phase Power Circuits 129
Three-Phase-Controlled Rectifier Circuits 134
Concluding Remarks 142
Laboratory Exercises 142
Fill in the Blanks 145
Descriptive Questions 146
Problems 147
Answers 148

4 DC–DC Linear Regulators 149

4.1 Generic Linear Regulator 149
Operating Principle 150
4.2 Linear Regulator Topologies 151
Shunt Regulator 151
Modified Shunt Regulator 154
Series Regulator 154
Negative Voltage Regulator 156
IC Linear Regulators 158
Practical Tips 160
Four-Wire Connection 162
Protection 163
Current Regulation 165
4.3 Parameters of the Linear Regulator 166
4.4 Analysis of a Series Regulator 166
First-Level Modeling 166
Effect of Current through Rb 170
Effect of Current through R1 171
Regulator Parameters 172
Range of Load Resistance RL 173

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xiv Contents

Second-Level Modeling 174

Inﬂuence of Temperature 179
4.5 Analysis of a Current Regulator 180
Line Regulation 182
Range of RL 182
Second-Level Modeling 183
Concluding Remarks 184
Laboratory Exercises 184
Fill in the Blanks 188
Descriptive Questions 188
Problems 189
Answers 192

5 DC–DC Switched-Mode Converters 193

5.1 Single Pole Double Throw Switch 193
5.2 The Chopper 194
5.3 DC Steady-State Principles 200
5.4 The Three Basic Converters 201
Step-Down or Buck Converter 201
Step-Up or Boost Converter 206
Step-Up/Down or Buck–Boost Converter 213
5.5 Selection of Power Switches 219
Device Selection 219
Electrical Stress Rating 221
Thermal Stress Rating 221
5.6 Continuous and Discontinuous Conduction Modes 221
5.7 Isolated Converters 225
Forward Converter 226
Semiconductor Switches 228
Waveforms 229
Governing Equations 230
Forward Converter with Demagnetizing Winding 233
Dual Switch Forward Converter 236
Push–Pull Converter 238
Half-Bridge Converter 243
Full-Bridge Converter 248
Flyback Converter 253
5.8 Practical Issues 258
5.9 Other Topologies 258
Cuk Converter 259
High-Boost Converter 263
Soft Switching in Converters 265
Concluding Remarks 275
Laboratory Exercises 276
Fill in the Blanks 281

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Contents xv

Descriptive Questions 283

Problems 286
Answers 288

6 DC–AC Switched-Mode Converters 289

6.1 Inverter Topologies 290
Single-Phase Topologies 290
Three-Phase Topologies 296
6.2 Self-Driven Inverters 297
Saturable-Core Inverter 298
Saturable Base Drive Inverter 302
6.3 Driven Inverter 304
Push–Pull Configuration 304
Half-Bridge Configuration 306
Full-Bridge Configuration 308
6.4 Quasi-Square Wave Inverter 309
6.5 Three-Phase Inverter Topologies 312
Six-Step Inverter 314
Current-Controlled Inverter 315
6.6 Pulse-Width Modulation 318
Quasi-Square Modulation 321
End Pulse Modulation 324
Center Pulse Modulation 327
Sinusoidal Pulse-Width Modulation 329
PWM through Phase Modulation 337
Space-Vector Modulation 339
6.7 Pulse–Width Modulation with Harmonic Elimination 350
Harmonic Elimination with Multiple Notches 351
Determination of Notch Angles 352
Staircase PWM 355
Summary of Staircase PWM Design 357
Concluding Remarks 358
Laboratory Exercises 359
Fill in the Blanks 363
Descriptive Questions 365
Problems 367
Answers 368

7 Design of Magnetics 369

7.1 Magnetic Concepts 369
Dissipative Component 371
Flux and Flux Density 372
Volt-Second Balance 374

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xvi Contents

7.2 Inductor 375

Inductor Value 375
Energy Storage 375
Area Product 377
Window Area 378
Cross-Section Area 378
Design of Inductors 379
Multiple-Winding Inductors 382
7.3 Potential Transformer 383
Operating Principle 384
Turns Ratio 385
Leakage Flux Linkage 386
Equivalent Circuit 388
Area Product 391
Transformer Design 394
7.4 Current Transformer 398
Design of Current Transformers 401
7.5 General Notes on Magnetics 403
Window Utilization Factor 403
Core Shapes 404
Polarity and Dot Convention 406
Magnetic Losses 407
Skin Eﬀect 412
Proximity Eﬀect 413
Concluding Remarks 415
Laboratory Exercises 416
Fill in the Blanks 418
Descriptive Questions 419
Problems 420
Answers 421

8 Modeling of Systems 423

8.1 Input–Output Relations 425
8.2 Diﬀerential Equations and Linearization 426
8.3 State Space Representation 428
8.4 Transfer Function Representation 431
Modeling an Armature-Controlled DC Motor 434
Poles and Zeros 436
8.5 Block Diagrams 436
Mason’s Rule 440
8.6 Lagrange Method 442
8.7 Circuit Averaging 447
8.8 Bond Graphs 453
Standard Elements 454
One-Ports 454

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Contents xvii

Two-Ports 455
Multi-Ports (Junctions) 457
Rules for the Selection of Causality 457
Steps in Obtaining the System Model 457
Bond Graph Construction 458
Causality Assignment 462
State Equation Extraction 463
Modeling Switched Power Systems 467
8.9 Space-Vector Modeling 473
Space Vectors 475
Representation of Space Vectors in Orthogonal Co-ordinates 476
Space-Vector Transformations 476
Modeling of Induction Motor 479
State Space Representation of the d–q Model of the Induction Motor 483
Concluding Remarks 491
Tutorial Exercises 492
Fill in the Blanks 494
Descriptive Questions 496
Problems 497
Answers 498

9 Control System Essentials 499

9.1 Representation of System in Digital Domain 501
9.2 The z-Transform 502
Physical Significance of z–1 506
9.3 Digital Filter 508
Few Common Digital Filters 512
9.4 Mapping between s-Plane and z-Plane 515
s = 0 + j0 → z = 1 515
s = 0 + jπ/ T → z = –1 516
s = 0 − jπ/ T → z = –1 516
s = –σ + j0 → z = Real Axis between 0 and 1 517
s = σ + j0 → z = Real Axis between 1 and Infinity 517
9.5 Effect of Sampling 518
9.6 Continuous to Discrete Domain Conversion 521
Pole–Zero Map 522
Numerical Integration Methods 523
Hold Equivalence 530
Discretizing the State Equation 533
9.7 Control System Basics 535
Performance Specifications 535
Stability 535
Steady-State Accuracy 536
Speed of Response 538
Measures for Performance Parameters 538

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xviii Contents

9.8 Control Principles 540

9.9 State Space Method 542
Concluding Remarks 543
Tutorial Exercises 544
Fill in the Blanks 545
Descriptive Questions 546
Problems 547
Answers 548

10 Digital Controller Design 549

10.1 Controller Design Techniques 550
10.2 Bode Diagram Method 551
Bode Diagrams 552
Controller Design with Bode Diagram 556
10.3 PID Controller 562
PID Controller Design 567
Integrator Windup in PID Controller 568
Practical PID Controllers 570
10.4 Root Locus Method 573
Root Locus Plot 574
Controller Design 575
10.5 State Space Method 582
Controllability 582
Observability 583
10.6 Full-State Feedback 584
Regulator 585
Tracker 585
10.7 Regulator Design by Pole Placement 587
10.8 Estimator Design 591
Estimator Error Dynamics 592
Separation Principle 593
Current Estimator 594
Reduced Order Estimator 596
10.9 Tracker: Controller Design 599
10.10 Controlling Voltage 600
Operation 605
10.11 Controlling Current 607
Current-Controlled Converter 607
Unity Power Factor Converter 610
Front-End Converter 613
10.12 Control of Induction Motor 619
Scalar Control 619
Vector Control 622
10.13 Output Feedback 631

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Contents xix

10.14 Induction Motor Control with Output Feedback 633

Plant Dynamics 636
Anti-Alias Filter Dynamics and Augmentation 636
Controller Dynamics and Augmentation 638
Concluding Remarks 641
Tutorial Exercises 642
Fill in the Blanks 643
Descriptive Questions 644
Problems 646
Answers 647

11 Optimal and Robust Controller Design 649

11.1 Least Squares Principle 650
11.2 Quadratic Forms 651
11.3 Minimum Energy Principle 653
11.4 Least Squares Solution 655
11.5 Weighted Least Squares 658
11.6 Recursive Least Squares 659
LMS Algorithm 660
Kalman Filter 664
11.7 Optimal Control: Linear Quadratic 668
Linear Quadratic Regulator 670
Linear Quadratic Gaussian 672
Linear Quadratic Tracker: Output Feedback 672
11.8 Induction Motor Example 674
11.9 Robust Controller Design 679
Frequency Domain Performance Speciﬁcations 681
Modeling Uncertainties 681
Controller Design Steps 682
Speed Controller Synthesis 685
Concluding Remarks 688
Tutorial Exercises 688
Fill in the Blanks 691
Descriptive Questions 692
Problems 693
Answers 694

12 Discrete Computation Essentials 695

12.1 Numeric Formats 695
Fixed-Point Numeric Format 696
Floating-Point Numeric Format 699
General Notes on Number System 702

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xx Contents

12.2 Tracking the Base Point in the Fixed-Point System 703

Addition of Numbers 703
Subtraction of Numbers 703
Multiplication of Numbers 703
12.3 Normalization and Scaling 704
Multiplication Algorithm 707
12.4 Arithmetic Algorithms 709
Reciprocal 709
Square Root 711
Reciprocal of Square Root 713
Hypotenuse 713
Polynomial 714
Sine and Cosine 714
Exponential 715
Logarithm 716
Implementation Examples 717
PI Controller 717
Sine and Cosine 719
Pulse-Width Modulation (PWM) 720
Space Vector PWM 724
Over-Modulation 727
Concluding Remarks 729
Tutorial Exercises 730
Fill in the Blanks 732
Descriptive Questions 732
Problems 733
Answers 734

13 Thermal Aspects 735

13.1 Modeling Heat Transfer 736
13.2 Heat Transfer by Conduction 738
13.3 Heat Transfer by Convection 742
Determination of Nusselt Number 743
Free Convection 744
Forced Convection 747
13.4 Heat Transfer by Radiation 753
Reﬂectance, Absorptance and Transmittance 755
13.5 Heat Transfer by Mass Transport 756
13.6 General Notes on Heat Transfer 758
Mixed Heat Transfer Mechanisms 758
Thermal Resistance of Varying Cross-Sections 759
Mounting of Power Devices on Heat Sink 760
Transient Model for Heat Transfer 761
Best Method of Heat Transfer 762

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Contents xxi

Concluding Remarks 763

Tutorial Exercises 763
Fill in the Blanks 765
Descriptive Questions 766
Problems 767
Answers 768

14 Reliability Modeling 769

14.1 Reliability Concepts 771
Failure Rate 771
Failure-Time Probability Density Function 773
Mean Time Between Failure (MTBF), Mean Time to Failure (MTTF) 776
14.2 Modeling for Reliability 777
Series System 777
Parallel System 778
Mesh System 786
14.3 Redundant Systems 788
Full-On Redundancy: Multiple-Survivor Sub-System 789
Switching in Redundant Systems 791
Mean Time to Failure 795
Standby Redundancy 797
Standby Redundancy with Imperfect Switching 799
14.4 Redundant Systems with Non-Identical Components 799
14.5 Design for Reliability 804
14.6 Reliability Apportioning/Allocation 813
Method 1: Equal Apportionment Technique 814
Method 2: AGREE Apportionment Technique 814
Method 3: ARINC Apportionment Technique 815
14.7 Inter-Connection and Wiring 816
14.8 General Notes on Designing for Reliability 822
Connectors 822
14.9 Part Derating 828
Concluding Remarks 828
Tutorial Exercises 829
Fill in the Blanks 830
Descriptive Questions 831
Problems 832
Answers 833

15 Reliability Prediction 835

15.1 Similar Equipment Technique 836
15.2 Similar Complexity Technique 836
15.3 Prediction by Function Technique 836

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xxii Contents

15.4 Parts Count Technique 837

Part Count with Non-Series Model 839
15.5 Part Stress Technique 839
15.6 Environments 842
15.7 Reliability Prediction Process 842
15.8 Component Naming Convention 843
15.9 Component Object Notation 844
15.10 Example Reliability Prediction Process 849
Steps to Design a Circuit 849
15.11 Physics of Failure (PoF) 852
Concluding Remarks 854
Tutorial Exercises 854
Fill in the Blanks 855
Descriptive Questions 855
Problems 856
Answers 857

Appendix I 859
Appendix II 861
Appendix III 863
Appendix IV 865
Appendix V 866
Appendix VI 867

Bibliography 909
Index 911

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Power Semiconductor Switches

Learning Objectives
CHAPTER

1
After reading this chapter, you will be able to:
understand the requirements of an ideal switch and the characteristics of important
power semiconductor switches.
estimate the conduction and switching power losses in various power semiconductor
switches.
model and simulate the power semiconductor switches.

P ower electronic applications deal with the flow of power. However, majority of the applications in power
electronics are based on switching the power flow in order to improve efficiency. As a consequence, one
has to use power semiconductor devices that act as power switches. This chapter discusses various power
semiconductor devices with an emphasis on using them as power electronic switches. There are many semi-
conductor devices that can be used as power switches. Few of the common power semiconductor switches are
diodes, bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistor (MOSFETs),
insulated gate bipolar transistors (IGBTs), thyristors, gate turn-OFF thyristors (GTOs) and metal oxide
semiconductor controlled thyristor switches (MCT). Power MOSFETs and IGBTs have a large role to play
in modern power control equipments and hence their study is emphasized.
The power semiconductor switches may be studied from various viewpoints:
1. physics viewpoint;
2. circuit viewpoint;
3. protection viewpoint;
4. drive viewpoint;
5. modeling viewpoint;
6. packaging viewpoint.
The physics viewpoint explains the operation and the functional features of the device. The circuit view-
point deals with the static and dynamic characteristics. For reliable operation of the power switches, one
must ensure that the electrical and thermal stresses within the device are well below the stated ratings of
the device. These switches handle large currents and dissipate a considerable amount of heat; consequently,
the thermal aspects need detailed attention to ensure that the switch operates within the permissible junc-
tion temperatures. The protection viewpoint focuses on the electrical and thermal stresses within the

Chapter 01.indd 1 3/12/2009 3:47:46 PM

2 Power Electronics

device. In this respect, the safe operating limits for the operation of the power semiconductor device are
addressed. The drive viewpoint emphasizes and clariﬁes the switching behavior of the power devices that
enables one to synthesize reliable and meaningful drive circuits. The packaging viewpoint focuses on the
device mounting strategies, removal of heat through heat sinks, forced cooling devices and connection
issues.
Modeling switches for purposes of simulation are also important aspects that need to be addressed. The
mathematical representation of the switches will aid in simulating the power topologies so that the circuit
behavior and the waveforms at various parts in the circuit may be determined before the actual hardware
implementation. In fact, it is essential to complement the hardware bread-boarding sessions with electronic
bread-boarding sessions not only to enhance the understanding of the circuit and its operation, but also to
reduce the design cycle time.

1.1 Ideal Switch

T his chapter focuses on semiconductor devices that are operated in such a manner that they behave as
switches. These semiconductor switches are supposed to emulate the operation of an ideal single pole
single throw (SPST) switch. However, it will become clear from the discussions in the sections to follow that
none of the semiconductor switches have all the characteristics of an ideal SPST switch. Before discussing
the features of the semiconductor switches, it is necessary to have a reference list of features that an ideal
SPST switch has in order to aid in a better understanding of the practical semiconductor switch. An ideal
SPST switch will have the following features:
1. ON resistance = 0 (or zero forward voltage drop).
2. OFF resistance = infinity (or zero reverse current).
3. When ON-conducts infinite current in both the forward and reverse directions.
4. When OFF-withstands infinite forward and reverse voltages.
5. It can switch instantaneously from OFF to ON and from ON- to OFF-states.
6. Power dissipated in the switch is zero, that is, both the conduction and the switch transition losses
are zero.
7. ON-to-OFF and OFF-to-ON transitions of the switch are fully controllable.
8. It requires no power to drive or control the switch.
While none of the power semiconductor switches have these ideal characteristics, efforts are continuously
made to improve the performances of the semiconductor switches such that they may tend towards ideal
behavior. There are many different types of power semiconductor devices available commercially. However,
in this chapter, only a few popular generic power semiconductor switch types will be discussed. The discus-
sion will initially try to provide some basic insights into the physics of operation of the semiconductor
junction taking diode as an example. Subsequently the circuit viewpoint is discussed for the diode as well
as few other device types like BJTs, MOSFETs, IGBTs and thyristors to aid in the selection of the devices as
power switches for power electronic applications.

1.2 Diodes

D iodes are devices that have two terminals, namely, (a) anode and (b) cathode. When the anode is more
positive than the cathode, the diode is said to be forward-biased and allows a ﬂow of current from the
anode to the cathode. The forward-biased state of the diode is called the ON-state or the conducting state

Chapter 01.indd 2 3/12/2009 3:47:47 PM

Power Semiconductor Switches 3

of the diode. On the other hand, when the cathode is more positive than the anode, the diode is said to be
reverse-biased and does not permit any flow of current. The reverse-biased state of the diode is called
the OFF-state or the blocking state of the diode. The switching action of the diode is solely dependent on
the anode-to-cathode potential and this is determined by the external circuit. As there is no control on the
switching state, a diode is termed as an uncontrolled switch.
In a metal (e.g. copper), the valence electrons are completely free and roam from atom to atom. In a
semiconductor (e.g. silicon), a covalent bond is imposed between the valence electrons of adjacent atoms.
As a result the motion of valence electrons is coordinated with the motion of valence electrons of an
adjacent atom. Thus, in a pure semiconductor there are very few free electrons. Evidently, the conduction
property of a metal and a semiconductor is very different. If a fraction of a volt is applied across a semi-
conductor, a small amount of current will flow whereas if applied across a metal, a large current will result.
The conductivity of pure semiconductors can be changed by adding impurities. This process of adding
impurities into a pure semiconductor is called doping. By adding some impurities in a pure semiconductor,
its conductivity can be increased and electron (or hole) flow can be easily controlled, for example, pure
silicon plus a pentavalent impurity (e.g. arsenic) increases the mobile free electron charges and is called
n-material, whereas pure silicon plus a trivalent impurity (e.g. boron) increases the mobile hole charges and
is called as p-material.
A p–n junction diode can be formed by growing a single crystal of semiconductor material and doping
with the above impurities in a controlled manner. Figure 1.1 shows a schematic diagram of a p–n junction.
The p-side has a high density of holes (i.e. electron vacancies) and the n-side has a high density of electrons.
These electrons will diffuse from the n- to the p-side and the holes will diffuse from the p- to the n-side. This
will create a space charge layer on either side of the junction called the depletion region wherein the holes
and the electrons combine to form immobile charges as shown in Figure 1.1. This gives rise to an electric
field and a potential barrier. The electric field creates a drift current that acts in such a way as to oppose the
diffusion current. Equilibrium is reached when the diffusion and the drift currents balance each other.
The depletion region at the junction has only immobile charges. The value of the potential barrier in
volts depends on the charge carriers and is governed by the Boltzmann’s relation given in Eq. (1.1). The

p n
Mobile hole Mobile electron

− +
− − − − + + + +
Immobile
− − − − + + + + charge

fo
Depletion region

Figure 1.1 Schematic diagram of p–n junction.

Chapter 01.indd 3 3/12/2009 3:47:47 PM

4 Power Electronics

p n

fο
pp
No. of charge
pn
carriers
0 x

Figure 1.2 Charge carrier levels in the p- and n-regions in the absence of external bias.

charge carrier levels at equilibrium for the p-region and the n-region in the absence of any external bias
voltage are depicted in Figure 1.2. The number of holes in the p-region is denoted by pp and the number of
holes in the n-region is denoted by pn:
−φo /( KT /q ) −φo /V T
pn = pp × e = pp e (1.1)
where VT = KT/q and K is the Boltzmann constant in Joules per degree Kelvin; T is the junction tempera-
ture in degree Kelvin; q is the electron charge in coulomb; pn is the number of holes in the n materials; pp is
the number of holes in the p material; fo denotes the barrier potential.
Note that Eq. (1.1) is an exponential relationship. VT is of the order of few tenths of volt. With this basic
relationship one can try to understand the operation of a p–n junction that is the building block of almost
all semiconductor devices.
On applying a forward bias (positive to p and negative to the n) to the p–n junction as indicated in
Figure 1.3(a), the barrier potential across the p–n junction reduces from the equilibrium value of fo to
(fo − f) and the resulting equilibrium hole density in the n-material is changed, which is given by
Boltzmann law as
−(φ0 −φ )/( KT/q ) φ /VT
pn* = pp × e = pn e (1.2)
Equation (1.2) is a fundamental relationship in junction theory. This shows that a small forward bias
increases the minority carrier (holes) concentration in the n-region exponentially. These excess holes come
from the p-side and are in turn replenished from the external source. As the holes cross over from the
p-region to the n-region, swift recombination results. The charge density decreases with distance, x from the
junction as depicted in Figure 1.3(a). For every electron in the n-material that combines with a hole, there
is another electron entering the n-region from the negative side of the external voltage source. It is important
to understand that this change of charge density with distance in the semiconductor involves a transport of
charge and thereby constitutes a current flow. It takes place predominantly by diffusion.
The hole-current through diffusion is proportional to dpn*/dx. Similarly diffusion current due to the
electron density difference also exists. The diffusion current in the p–n junction is given as
I = I o (e qV /KT − 1) (1.3)
where I is the diode current; Io the saturation current; q the electronic charge in coulombs; K the Boltzmann’s
constant; T the junction temperature in degree Kelvin.

Chapter 01.indd 4 3/12/2009 3:47:48 PM

Power Semiconductor Switches 5

p n

fο −f

No. of charge pp
carriers
pn

0 x

(a)

p n

fο +f
pp

No. of charge pn
carriers

0 x

(b)

Figure 1.3 Charge densities near a biased p–n junction.

In the conventional conductor, the current and the voltage are related by the well-known Ohm’s law.
However, it is evident from the expression given in Eq. 1.3, that in the case of a p–n junction, the current is
exponentially related to the voltage as a consequence of the Boltzmann relation. On applying a reverse bias
(positive to n and negative to p) to the p–n junction as indicated in Figure 1.3(b), the barrier potential across
the p–n junction increases to (fo + f) and the resulting equilibrium hole density in the n-material is given
by the Boltzmann law as
−(φo + φ )/( KT /q ) −φ /V T
pn′ = pp e = pn e (1.4)

Chapter 01.indd 5 3/12/2009 3:47:48 PM

6 Power Electronics

Under reverse-biased condition, p n′ is less than the equilibrium density of holes in the n-region. This
implies that the holes diﬀuse from the n-region into p-region. Thus, an extremely small current called the
reverse saturation current results and is denoted as I0. A very large negative voltage disrupts all covalent
bonds and results in a large current. Now it behaves like a metallic conductor and the diode is said to have
attained reverse breakdown.

Static Characteristics
The symbol of a diode is shown in Figure 1.4(a). Lead A that is connected to the p-region of the p–n junc-
tion is called the anode and lead K that is connected to the n-region of the p–n junction is called the
cathode. The v–i characteristics of an ideal diode are depicted in Figure 1.4(b). From Figure 1.4(b), it can
be observed that the voltage across the diode when forward-biased is zero. In forward-biased condition it
allows ﬂow of currents from the anode to the cathode. When the diode is reverse-biased, then the diode
blocks any ﬂow of current. However, the diode can withstand the applied reverse voltage as shown in
Figure 1.4(b).

i
A K v

(a) (b)

i i

1/rd

v Vd v

Figure 1.4 (a) Symbol of diode; (b) ideal v–i characteristics; (c) actual characteristic;
(d) piece-wise linear characteristic.

Chapter 01.indd 6 3/12/2009 3:47:48 PM

Power Semiconductor Switches 7

The practical v–i characteristic of the diode is shown in Figure 1.4(c). It shows that during the forward-
bias condition, the diode has a ﬁnite resistance called the forward dynamic resistance (rd). For quick
engineering calculations, it is normal to simplify the characteristics by the piece-wise linear characteristic,
as shown in Figure 1.4(d).

Dynamic Characteristics
Turn-OFF of Diode
A forward-biased diode has a charge distribution as shown in Figure 1.3. If a reverse bias is now applied to
the diode, the charges will have to re-distribute from pn* to pn′. This takes a certain amount of time. The
waveform for the current and voltage are shown in Figure 1.5. The test circuit used to obtain the dynamic
characteristics is as shown in Figure 1.5(a).
The excess charge stored in the diﬀusion region has to be removed before the junction can be reverse-
biased. As long as there are excess charge carriers in the diﬀusion region (also called the space-charge
region), the junction will be in forward-biased state. The diode voltage will not change from its ON-state
value except for the small decrease due to Ohmic drop caused by the reverse current. After the current goes
negative and the excess charges are removed at time t2, the junction becomes reverse-biased and quickly
acquires the applied negative voltage value. At time t2, the junction charge distribution would have reached
the equilibrium charge distribution of a non-biased junction like that shown in Figure 1.2. From t2 to t3

V1
i
R

−VR

(a)

i i
V1/R V1/R
di/dt
trr
trr

0 t3 t 0 t1 t3 t
di /dt
−VR /R Qrr −VR /R Qrr
Irr Irr
t1 t2 t2
VF − Irr rd VF − Irr rd
VF VF

0 0

−VR −VR
(b) (c)

Figure 1.5 Diode turn-OFF: (a) Test circuit for turn-OFF; (b) idealized dynamic characteristic
during turn-OFF; (c) practical dynamic characteristic during turn-OFF.

Chapter 01.indd 7 3/12/2009 3:47:48 PM

8 Power Electronics

the charge distribution tends towards that of the reverse-biased junction like that shown in Figure 1.3(b).
The diode now starts to withstand the applied reverse voltage and the diode current falls quickly to zero.
In the case of a practical diode, owing to parasitic inductance, the current in the diode does not immedi-
ately reverse like that of the ideal recovery shown in Figure 1.5(b). It reduces at a certain rate decided by
the lead inductance as indicated in Figure 1.5(c). The time interval trr is called the reverse recovery time
and is an important parameter in switching applications. The interval between t1 and t2 is sometimes called
the storage time.

Turn-ON of Diode
If the diode is under reverse bias and it has to be forward-biased, it requires certain time, known as turn-
ON time or forward recovery time before all carriers in the whole junction can contribute to the current
ﬂow. Here, the charges will have to re-distribute from pn′ to p*.
n In the case of turn-OFF, the charges have
to be removed or re-combined whereas in the case of turn-ON the junction has to acquire charges. This
is generally a faster process than removal of the charges. Therefore, turn-ON times will be much faster
than turn-OFF times. In practical situations, it turns out that forward recovery time does not constitute
a serious problem.

Diode Classifications
The diodes are generally classiﬁed based on the turn-OFF times. The reverse recovery time (trr) is a measure
of the speed at which the diode can switch (turn-OFF) and therefore gives an indication on the external
switching frequencies that may be used. Based on this, the diodes are classiﬁed as follows:

1. Rectiﬁer diodes (trr in microsecond range).

2. Fast recovery diodes (trr in 200–500 ns).
3. Ultra fast recovery diodes (trr ∼ 30–200 ns).
4. Schottky diode (metal semiconductor junction –trr < 30 ns).

In high-frequency switching circuits, fast recovery diodes (types 2–4) should be used depending on the
frequency range of interest and voltage rating. Type 1 is used for low-frequency applications like mains
rectification, as in front-end rectifier for the capacitor input filter.

Diode Parameters
There are various parameters in the datasheet of a diode that need to be understood before selecting a diode
for a particular type of application. These parameters must be calculated a priori before selecting a diode for
the speciﬁc application. The important parameters in the datasheet of a diode are

1. Average current, I Fav

2. Root mean square (RMS) current, I Frms
3. Peak current, I F
4. Surge current, I FSM
5. Breakdown or reverse voltage, V RRM
6. Forward drop, V F
7. Dynamic resistance, rd
8. Reverse recovery time, trr
9. I 2t rating

Chapter 01.indd 8 3/12/2009 3:47:49 PM

Power Semiconductor Switches 9

For sinusoidal currents, IFav , IFrms and IF are related and the relationships are well known. It is not so when
current in the circuit is non-sinusoidal. In such cases, depending on the current and voltage waveforms of
the diodes for the speciﬁc circuitry, the corresponding average, rms and peak values must be calculated from
the fundamentals.
In high-power circuits, it is important to make sure that the chosen diode ratings are higher than the
respective values of currents that will ﬂow in the circuit to ensure that the diode can reliably operate. In
detailed datasheets, some of the parameters may be given in the form of nomo-graphs. One may choose the
diode based on the parameter nomo-graphs also.

1.3 Surge Current

T he rectifier has the ability to sustain overload currents for a brief period of time without damaging the
device. Two parameters are specified in datasheets: IFSM and I 2t rating. IFSM is the maximum peak half-
cycle non-repetitive current rating. In applications that use the capacitor input rectifier filter, the problem of
surge current is severe. When the capacitor is fully discharged, the surge current will be enormous at the
time when the rectifier filter is switched ON and the input voltage waveform is at its peak. This problem is
most severe in the case of line-operated switched-mode power supplies when the input or the mains voltage
is at its worst case maximum value of around 270 V rms. If the expected surge current is higher than what
the device can sustain, one has to limit the current using some limiting device such as a series resistor. The
amp-squared second (I 2t) rating is normally associated with protective fuse co-ordination and the rating is
usually given for 10 ms. For proper functioning, the fuse I 2t rating has to be less than the diode I 2t rating.

1.4 Thermal Viewpoint

A n ideal diode does not have any power dissipation. However, a practical diode will have a power loss.
It is essential to quantify the amount of power loss in the diodes so that one can select a suitable heat
sink in addition to budget the power loss in the circuit so that the efficiency can be estimated. There are
different components of power loss in a diode, viz. (a) the ON-state loss (Pon); (b) the OFF-state loss (Poff)
and (c) the switching loss (Pswitching). The total power dissipation (Pd) is given as
Pd = Pon + Poff + Pswitching (1.5)
Pon is the average power loss when the diode is in the ON-state. One can use the piece-wise linear model [see
Figure 1.4(d)] to estimate the power loss. The power loss is estimated as follows:
T
1
T ∫0
Pon = v × i × dt (1.6)

From the piece-wise linear model of the diode depicted in Figure 1.4(d), it can be observed that
v = Vd + (i × rd ) (1.7)
where Vd is the cut-in voltage or the knee voltage of the diode as shown in Figure 1.4(d). From Eqs. (1.6)
and (1.7), the ON-state power loss in the diode is given as
Pon = (Vd × I Fav ) + ( I Frms
2
× rd ) (1.8)
The knowledge of the average and rms values of the current in the circuit can be used to evaluate
the ON-state conduction losses. OFF-state losses are due to the ﬂow of the reverse saturation current

Chapter 01.indd 9 3/12/2009 3:47:49 PM

10 Power Electronics

in the reverse-biased p–n junction. The reverse saturation current is negligibly small and therefore the i2R
loss due to it is generally not significant. The reverse recovery losses are negligible at low frequencies (e.g., at
50 Hz operation). However, at higher switching frequencies the reverse recovery losses are significant and
affect the efficiency of the circuit considerably. In Figure 1.5(c), the shaded area represents the reverse recovery
charge Q rr. The loss during the reverse recovery is given as follows:
Pswitching = Eswitching × fs (1.9)
where Eswitching is the energy spent during the reverse recovery process and fs is the switching frequency.
⎛1 ⎞
Pswitching = ⎜ Q rrVR ⎟ × f s (1.10)
⎝2 ⎠
Q rr can be obtained from the datasheets and can be used to evaluate Pswitching. If the shaded portion of
Figure 1.5(c) is approximated as a triangle, then Q rr can be estimated from the reverse current during
turn-OFF Irr as
1
Q rr = t rr I rr (1.11)
2
Substituting Eq. (1.11) in Eq. (1.10), the switching loss can also be expressed as
1
Pswitching =I V t f (1.12)
4 rr R rr s
Irr, VR and fs are circuit parameters which are known for the specific circuit. trr is obtained from the datasheet
for the diode used. It is important to note that the switching losses are a function of the switching frequency.
The junction temperature of the device should not exceed a certain limit (150°C as specified in the data-
sheet). The heat generated in the junction should be removed in such a manner that at thermal equilibrium
the junction temperature is well below the rated junction temperature. This is made possible by mounting
the device on a heat sink. The thermal issues and the selection of heat sink for a specific calculated device
power dissipation are discussed in Chapter 13.

Diode Model
A true model of a diode should take care of the steady-state and transient behaviors. One of the commonly
used models for simulation is shown in Figure 1.6. Referring to Figure 1.6, id–Vd variables are characterized
by an exponential relationship in accordance with Eq. (1.3). Rs is the Ohmic resistance of bulk material plus

A + − K
Rs Vd

Figure 1.6 Diode model.

Chapter 01.indd 10 3/12/2009 3:47:49 PM

Power Semiconductor Switches 11

the contact resistance. It is ideally zero; however, in practice it has a ﬁnite but small value. When a diode is
abruptly switched from the forward to the reverse bias, the excess mobile charge has to be removed. This can
be modeled as a diﬀusion capacitance CD. For a transition from reverse to forward bias, the mobile charge
must build up. This is characterized by a transition capacitance CT . It should be noted that both CD and CT
are capacitances whose values are not constant but dependent on the charge in it. Circuit simulator pro-
grams also use a similar model.

1.5 Bipolar Power Transistors

T he bipolar transistor (bipolar junction transistor, BJT) is a three-terminal device. It has an emitter lead
E, a collector lead C and a base lead B. The flow of current from the collector to the emitter is con-
trolled by the current through the base. This base current is a fraction of the current through the collector.
Therefore the BJT is called a current-controlled device. In the ON-state, the BJT can allow the flow of
current in only one direction (from collector to emitter for NPN transistors; from emitter to collector for
PNP transistors). Further, they can support only unidirectional voltages during the OFF-state.
BJT is a dual junction device with two possible configurations, namely, NPN or PNP. Figure 1.7(a)
shows a schematic of the vertical cross-sectional structure of the NPN transistor. Figure 1.7(b) shows the
circuit symbol of an NPN transistor. Referring to Figure 1.7(a), the transistor consists of a highly doped
n-type emitter. The base region is a p-type doped semiconductor. The bottom layer is the n-type collector.
The doping of the n-type collector is light towards the collector–base junction and higher towards the
collector terminal. Generally, the collector is the largest region. Larger the collector region, greater is the
amount of voltage that the transistor can withstand during the OFF-state. The arrow in the NPN transistor
symbol points out of the emitter. In the case of the PNP transistor, the arrow in the emitter would point
inwards as depicted in Figure 1.7(c). In general, the arrow would indicate the conventional direction of the
current flow in the device. In the discussions to follow, NPN transistors only will be considered as the
concepts of the NPN transistors can be extended to the PNP transistors without loss of generality.
Figure 1.8 depicts the basic operation of an NPN transistor. The base–emitter junction is forward-biased
by connecting an external voltage VE as shown. Electrons are injected from the emitter into the base. They

B E B

N
P
E
N
C
B B

C E C
(a) (b) (c)

Figure 1.7 NPN transistor: (a) Structure; (b) symbol (c) Symbol of PNP transistor.

Chapter 01.indd 11 3/12/2009 3:47:49 PM

12 Power Electronics

E−B depletion layer C−B depletion layer

IE IC
N P N
E C

− −

B
IB

VE VC

Figure 1.8 Operation of NPN transistor.

appear at the emitter–base junction. Diffusion takes place in a manner similar to that of the p–n junction
diode. However, the base is made intentionally small to prevent re-combination of electrons with holes in
the p-region. This results in a very small IB. As a result, the vast majority of electrons injected across the
emitter–base junction move on to the base–collector junction and further into the n-material of the collector.
Once the injected electrons appear in this region, the effect of VC accelerates them towards collector, through
the load resistor, through VC and then back to VE, thus completing the circuit.
The ratio of the collector current to the emitter current is called the “alpha parameter” of the transistor,
that is, IC/IE = a. This parameter varies between 0.9 and 0.98 depending on the base width. If the base were
wide, then all electrons that have crossed the emitter–base junction will re-combine with holes in the base
and there will be lesser or no electrons reaching the collector. In this case the emitter–base junction and
collector–base junction will act as though they were diodes connected back-to-back. There is no transistor
action taking place in such a case. From the discussion above, it should be noted that the transistor is not
simply a back-to-back connection of two diodes.
The transistor connected as shown in Figure 1.8 is called the normal mode of operation and a is referred
to as aF or aN. One can also have an inverted mode of connection wherein the collector acts as the emitter
and vice versa. The a under this configuration is denoted as aR or aI. One can write the equivalent circuit
model of the NPN transistor as shown in Figure 1.9. It is called the Ebers–Moll model. The equations for
IE and IC for the normal and inverted mode of operations can be written as
VC V T
I C = α F I F − I CO (e − 1) (1.15)

I E = α R I R − I EO (e
VE VT
− 1) (1.16)

Referring to the equivalent circuit model of the NPN transistor depicted in Figure 1.9,
VE V T VC VT
I F = I EO (e − 1); I R = I CO (e − 1); I C + I E + I B = 0
Here IEO is the emitter–base junction saturation current when collector–base junction is zero-biased (Vc = 0);
ICO is the collector–base junction saturation current when emitter–base junction is zero-biased (VE = 0).

Chapter 01.indd 12 3/12/2009 3:47:49 PM

Power Semiconductor Switches 13

aRIR aFIF

IE IC

E C
IB

IF IR
B

Figure 1.9 Equivalent circuit of an NPN transistor.

Including the bulk resistance and capacitance (similar to the diode case) results in the model shown in
Figure 1.10. CDE and CTE are the emitter–base junction diffusion and transition capacitances, respectively.
Similarly, CDC and CTC are the collector–base junction diffusion and transition capacitances, respectively.
Circuit simulation programs use a further refined version of the model called as the Gummel–Poon model.

Static Characteristics
BJT is a current-controlled device. Its output characteristics, that is, ic versus Vce is dependent on the base
current ib. Thus,
ic = f (Vce , ib ) (1.17)
where Vce is the collector-to-emitter voltage; ib is the base current and ic is the collector current.
Ideally ic = aie = bib and should be independent of Vce. However, due to “Early eﬀect” (base width
changes as Vce changes) the parameter b changes with Vce. Therefore, the iC versus Vce characteristics change
with diﬀerent values of the base current as depicted in Figure 1.11.

aRIR aFIF

IE IC

E RE RC C

IF IR

C TE C TC

B′

CDE CDC
RB

Figure 1.10 Equivalent circuit of a transistor with bulk resistance and capacitance.

Chapter 01.indd 13 3/12/2009 3:47:50 PM

14 Power Electronics

Saturation (ON)
region ib
Vcc /RL
Vcc

C
B

Load
line OFF region

0 Vcc Vce

Figure 1.11 Output characteristics of a transistor.

At very low Vce values, the transistor is said to be in the ON-state. This region is called the saturation
region. In this region, the collector current is independent of the base current and depends on the value of
Vce and load resistor RL. A transistor parameter of interest is the ratio of the collector current to the base
current, denoted by b or hFE. The parameter hFE is a useful number essential for design and is supplied by
the manufacturers. Knowledge of iC and hFE gives the base current that will be needed to saturate the transis-
tor or maintain the transistor in the ON-state.
At very low collector-current values, the transistor is said to be in the OFF-region as depicted in
Figure 1.11. Here the transistor is capable of supporting the applied external voltage. The other region of
the output characteristics that is not shaded is called the active region wherein the transistor behaves as a
dynamic resistor. For a transistor to be operated as a switch, it is primarily switched between the satura-
tion region or the ON-region and the OFF-region of the characteristics. However, during the transition
from the saturation region to the OFF-region and back, the operating point may transit through the
active region resulting in a loss called the switching loss.

Dynamic Characteristics
This sub-section describes the switching processes within a transistor under various base drive conditions.
For a transistor that is in the ON-state, the following three charges may be said to exist.

1. A charge Q b located in the base area.

2. A charge Q ce located in the collector region underneath the emitter.
3. A charge Q cb located in the collector region underneath the base contact.

Chapter 01.indd 14 3/12/2009 3:47:50 PM

Power Semiconductor Switches 15

Q Q

Qcb
Qce

Qce
Qb
Qb

Vce Ic

Figure 1.12 Charge dependency on Vce and Ic.

However, there are no charges present in a transistor that is in the OFF-state. Figure 1.12 illustrates the
dependency of these charges with respect to the collector–emitter voltage and the collector current.
Referring to Figure 1.12, it may be observed that the charge Q b is independent of the collector–emitter
voltage drop. However, Q b increases linearly as collector current increases. The charge Q ce also increases
linearly with the collector current but decreases linearly with increases in collector–emitter drop. To achieve
lower collector–emitter drop, Q ce must increase. The charge Q cb that is located in the collector underneath
the base contact has a signiﬁcant eﬀect on the collector–emitter voltage as depicted in Figure 1.12. The
charge Q cb increases rapidly as Vce drop decreases and the transistor goes towards saturation.

Turn-OFF of Transistor
During turn-OFF, the charges in the transistor must be removed. For a transistor that is in the ON-state, the
charges Q b, Q ce and Q cb are as depicted in Figure 1.13(a). A collector current will flow only when there is a
base charge Q b. The charge Q ce will be located in the collector region underneath the emitter. This results in
a low Ohmic collector consequently making the collector–emitter voltage low. An increase in the charge,
Q ce results in a decrease in Vce. The charge Q cb will be located in the collector region underneath the base
contact. When the base–collector region becomes forward-biased, Q ce rapidly increases and Vce decreases.
The process of turn-OFF of the transistor is illustrated in Figure 1.13. Referring to Figure 1.13(a), when
the base voltage is made zero or negative, a negative base current flows as the collector potential is much
greater than the base potential. This removes the charge Q cb. Then the charge Q c will be removed, starting
from the area underneath the edges of the emitter as shown in Figure 1.13(b). Q b also will now start to
decrease.
As Q b starts to decrease, the collector current will gradually be forced towards the center as shown in
Figure 1.13(c). As long as Q b is sufficiently high, the collector circuit will force the collector current to
flow. However, Vce will increase now as the current density becomes higher. With the emitter current
reducing, the negative base-current flows through the base resistance underneath the emitter (Rb – base-
spreading resistance). The charges Q ce and Q b now become increasingly located beneath the center of the
emitter and thus have to be extracted through an increasing resistance. Consequently, the base–emitter
terminal voltage becomes more negative. Subsequently, the emitter current is concentrated in the middle
of the emitter. This marks the end of a period called the storage period wherein most of the stored charges
in the base are removed. The storage period is denoted as storage time ts and is in general given in the tran-
sistor datasheet.

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16 Power Electronics

B E B B E B

n n
p p
Qb Qb

Qcb Qce Qce

n n

C C
(a) (b)

B E B B E B

n n
p p
Rb Qb Rb

n n
Qr

C C
(c) (d)

Figure 1.13 Turn-OFF of the transistor.

Fall time tf begins as soon as Q b is so low that the emitter injection of electrons starts to reduce. The
emitter current decreases with a speed depending on the rate of decrease in Q b. Ie = 0 when Q b = 0. A
trapped rest charge Q r in the collector must still be removed by way of a collector–base current which
appears as a tail current in the turn-OFF waveforms. This rest charge is indicated in Figure 1.13(d).

Turn-ON of Transistor
A transistor that is in the OFF-state has no charges within it. To obtain a low ON-state voltage, a base
current is applied such that the collector charge Q ce is built up, which will accordingly reduce the col-
lector resistance and therefore the collector–emitter voltage (see Figure 1.12). To quickly build up the
collector charge, the base-current waveform should have a peak at the beginning.
The dynamic characteristics of the transistor are shown in Figure 1.14. Referring to Figure 1.14(a),
during the fall time tf , the voltage across the collector–emitter [shown shaded in Figure 1.14(a)] is decided
by the external circuit. If the load is resistive, then the voltage will rise linearly as the collector current falls
linearly. If the load were an inductive one, then the voltage during the tf period would be governed by
LdiL/dt, where L is the inductance of the load and iL is current through the load inductance.
Referring to Figure 1.14(b), during the rise time tr , the current during this time [shown shaded in Figure
1.14(b)] is decided by the external circuit. If the load is resistive, then the current during this time will rise
linearly. If the load across the collector–emitter of the transistor is capacitive, the current during the period
tr is governed by CdVce/dt, where C is the capacitance across the collector–emitter.

Chapter 01.indd 16 3/12/2009 3:47:51 PM

Power Semiconductor Switches 17

Vce OFF Turn-ON ON Turn-OFF OFF

Determined by
external circuit
(a)

Vce(sat)
0 t
ic

(b)
Determined by
external circuit
Tail current due
to Qr

0 t

(c)

0 t

tr ts
tf

Figure 1.14 Switching characteristics of a transistor: (a) Collector–emitter voltage waveform;

(b) collector current; (c) base current.

Calculation of Power Dissipation in a Transistor

The different components of power loss in a transistor are: (a) the ON-state loss (Pon); (b) the OFF-state loss
(Poff) and (c) the switching loss (Pswitching ). The total power dissipation (Pd) is given by
Pd = Pon + Poff + Pswitching (1.18)
Pon is the average power loss when the transistor is in the ON-state. The power loss is estimated as follows:

Chapter 01.indd 17 3/12/2009 3:47:51 PM

18 Power Electronics

T
1
T ∫0
Pon = v × i × dt (1.19)

where v is the voltage across the collector–emitter of the transistor and i is the collector current through the
transistor. During the ON-state, the voltage across the transistor, v = Vce(sat). Therefore Eq. (1.19) becomes
T
1
T ∫0
Pon = V ce(sat) ×
i × dt = Vce(sat) I cavg (1.20)

For applications wherein the collector current is a pulsed current with a ﬂat top Ic during the ON-state, the
ON-state loss is given by
Pon = Vce(sat) × Ic × D (1.21)
where D is the duty cycle given by the ratio of the ON-time to the total switching period.
Like in the case of the diodes, the OFF-state losses are generally negligible. In the case of the switching losses,
Pswitching depends on the nature of the load as is evident from the dynamic characteristics shown in Figure 1.14.
A representative example case is discussed wherein the load is resistive. For resistive loads, assuming a linear rise
and fall of voltages and currents, the switching losses can be calculated as discussed in the following sub-sections.

Switching Loss from OFF-State to ON-State

Referring to Figure 1.14, when the base drive signal is initiated, there is a time duration (td) called the delay
time during which time the voltage and the current waveforms do not change much as the charges Q b, Q ce
and Q cb are being set up. This is followed by the time duration tr. During the time tr, the voltage across the
device falls from Vcc to Vce(sat). Without much error, this fall may be assumed to be linear for a resistive load.
The collector–emitter voltage during the rise time tr is
⎛ t⎞
v ce = Vcc ⎜ 1 − ⎟ (1.22)
⎝ t r⎠
The collector current for a resistive load will linearly rise from zero to Ic. This is given as
⎛t⎞
ic = I c ⋅ ⎜ ⎟ (1.23)
⎝ tr ⎠
The power dissipation during the OFF-state to ON-state transition is given by
t
r
⎛ t⎞ ⎛t⎞ V It f
POFF-ON = ∫ Vcc ⎜1 − ⎟ I c ⎜ ⎟ dt = cc c r s (1.24)
0
⎝ t r ⎠ ⎝ t r ⎠ 6
where fs is the switching frequency.

Switching Loss from ON-State to OFF-State

Referring to Figure 1.14, when the base drive signal is stopped, there is a time duration ts called the storage
time during which the voltage and the current waveforms do not change much as the charges Q b, Q ce and
Q cb are being removed. This is followed by the time duration t f . During the time t f , the current through the
device falls from Ic to zero. Without much error, this fall may be assumed to be linear for a resistive load. The
collector current during the fall time tf is given as
⎛ t⎞
ic = I c ⎜ 1 − ⎟ (1.25)
⎝ tf ⎠

Chapter 01.indd 18 3/12/2009 3:47:51 PM

Power Semiconductor Switches 19

The collector–emitter voltage for a resistive load will linearly rise from Vce(sat) to Vcc. This is given as
⎛t⎞
v ce = Vcc ⎜ ⎟ (1.26)
⎝ tf ⎠
The power dissipation during the ON-state to OFF-state transition is given by
t
f
⎛ t ⎞ ⎛t ⎞ Vcc I c t f f s
PON-OFF = ∫ I c ⎜1 − ⎟⎠ Vcc ⎜⎝ t ⎟⎠ dt = (1.27)
0
⎝ tf f 6
where fs is the switching frequency. The total switching loss is given as
Pswitching = POFF-ON + PON-OFF (1.28)
Substituting Eqs. (1.24) and (1.27) in Eq. (1.28), one obtains
Vcc I c f s (t r + t f )
Pswitching = (1.29)
6
It should be observed that the switching losses are proportional to the frequency of switching. The load is generally
never resistive. If the load is inductive, the voltage across the transistor during turn-OFF is determined by Ldic/dt,
where L is the external load inductance. If the load is capacitive, the current through the transistor during turn-
ON is determined by CdVce/dt, where C is the load capacitance as seen at the collector. The switching losses must
be estimated for non-resistive loads also in a manner similar to that discussed for the resistive load. The total power
dissipated is the sum of the ON-state loss and the switching loss. The power dissipated as above must be trans-
ported away from the junction such that the junction temperature remains at a safe value in equilibrium condi-
tions. A proper heat sink has to be selected. The thermal calculations are discussed in Chapter 13.

1.6 Safe Operating Area (SOAR)

T he maximum electric field across the collector–emitter of the transistor must remain below a critical value
at all instants for proper functioning of the transistor. The electric field across the transistor is dependent
on the collector-current density and the applied collector–emitter voltage. The electric field increases with
increasing collector voltage. It also increases with increasing collector-current density. If the collector voltage is
lowered then a higher collector-current density is permitted and vice versa. During switching transitions, there
are some destructive combinations of the collector-current density and the collector voltage that are likely to
occur. The SOARs give information about a given device on the current and voltage handling capabilities.
The collector-current density is dependent on the collector current and the amount of current crowding
in the regions of the collector. The amount of current crowding is different for turn-ON (positive base voltage)
and turn-OFF (negative base voltage) conditions. Therefore, the allowed combinations of the collector cur-
rent and collector voltage will differ for turn-ON transition and turn-OFF transition. This information is
available in the forward safe operating area (FSOAR) and the reverse safe operating area (RSOAR). A transis-
tor in the ON-state or the OFF-state has the operating point along the Y-axis or the X-axis when either Vce or
ic is zero. However, during switching transitions, both Vce and ic are non-zero and finite. This means that the
operating point will be in the region of the I-quadrant of the Vce–ic characteristic. In selecting a transistor, the
one which operates within both the FSOAR and the RSOAR, for the specific circuit, should be chosen.
With positive voltage applied to the base, the shape of a typical SOAR characteristic is as shown in Figure
1.15(a). The solid line shows the SOAR for DC operation and the dashed lines shows the SOAR for pulsed
operation. Operation outside the safe operating area is not allowed. For pulsed operation, the FSOAR increases

Chapter 01.indd 19 3/12/2009 3:47:51 PM

20 Power Electronics

ic ic

ICM Pdmax ICM

Secondary
breakdown

0 Vceo Vce 0 Vceo Vcesm Vce

(a) (b)

Figure 1.15 Safe operating area (SOAR): (a) Forward SOAR (FSOAR); (b) reverse SOAR (RSOAR).

and for very small duty cycles, the FSOAR becomes square. The SOAR is designed to indicate the current, power
dissipation, voltage and second breakdown limits of the transistor as depicted in Figure 1.15(a). The power dissi-
pation limit is the hyperbolic portion of the limit curve that is given by the maximum possible dissipation allowed
for the device. The second breakdown limit is the straight sloped line connecting the power dissipation limit and
the voltage limit lines. The second breakdown is generally triggered by combinations of high collector-voltage and
high collector-current density. With a positive voltage applied to the base, the region of highest current density is
at the edge of the emitter which conducts a substantial proportion of the collector current. During sudden change
of currents (especially during switching), a thermal gradient gets generated across the cross-section of the collec-
tor–emitter current flow. This thermal gradient will result in the non-uniform spreading of the current in the
device. This uneven spreading produces localized hot spots and it can in turn reduce the local resistance, further
increasing the non-uniformity. This will result in hot spots in the device that will finally destroy the device.
During turn-ON of the transistor, the high resistance of the collector region is reduced by the introduc-
tion of holes from the base and electrons from the emitter. This process is known as conductivity modulation.
However, during turn-OFF of the transistor, these extra holes and electrons constitute a stored charge that
must be removed from the collector before the voltage across the depletion region can develop. To turn OFF
the transistor, a negative voltage is applied to the base and reverse base-current flows. During turn-OFF, it is
essential that the device stays within its reverse safe operating area (RSOAR) that is shown in Figure 1.15(b).

1.7 Paralleling of Transistors

I n high-power switching applications, transistors can be paralleled to share the load current. The transistor
has a negative temperature co-eﬃcient of resistance. As a result, one has to ensure that the current sharing
between various parallel transistors is uniform, such that no transistor is over burdened and goes into a
thermal runaway. It is very common to add an emitter resistance as shown in Figure 1.16 to equalize the
currents. The emitter resistors give a negative feedback in the base–emitter circuit. If Ic increases then Vbe
will decrease, which would result in a decrease of Ib. This consequently will counteract the increase of Ic. The
emitter resistor values are governed by the following equations:

Chapter 01.indd 20 3/12/2009 3:47:51 PM

Power Semiconductor Switches 21

Ic1 Ic2

+ + +
Vbe1 − Vbe2 −

Vbe
R1 R2

Figure 1.16 Paralleling of transistors.

Vbe = Vbe1 + RI c1 = Vbe2 + RI c2 (1.30)

where R1 = R2 = R. From Eq. (1.30), one obtains
ΔVbe = Vbe1 − Vbe2 = R ΔI c (1.31)
Limit DVbe to around 0.2 V. Let DIc (diﬀerence in collector currents between the two transistors) of about
0.5 A be tolerated. This means R = 0.2/0.5 = 0.4 Ω. It should be noted that R dissipates power. Higher
R means more dissipation and higher Vbe (and Vcc) requirements. Paralleling transistors simplify heat trans-
fer problem by spreading the heat produced in a group of transistors over a large surface area heat sink.

1.8 Darlington Connection

H igh-power, high-voltage transistors generally have a low hFE (b ). The hFE of saturated high-voltage
transistors can be as low as 2. This means a very high base drive current is required. Therefore, the base
drive circuit is no longer a simple low-power circuit. To circumvent this problem, Darlington connection as
shown in Figure 1.17 can be used. In this case, the Ib requirement can be cut down to Ic/(hFE*hFE). It should

Q1
Ib
Q2

Figure 1.17 Darlington connections of transistors.

Chapter 01.indd 21 3/12/2009 3:47:52 PM

22 Power Electronics

be noted that Vce(sat) of the Darlington device is higher (∼1 V to 1.2 V) as opposed to 0.4–0.6 V Vce(sat) of a
single transistor. This implies that the power dissipation is higher in Q2 for a given load.

1.9 Power MOSFETs

T he metal oxide semiconductor field effect transistor (MOSFET) is a three-terminal device. It has a
source lead S (analogous to the emitter of the transistor), a drain lead D (analogous to the collector of
the transistor) and a gate lead G (analogous to the base of the transistor). The flow of current from the drain
to the source is controlled by the voltage applied between the gate–source terminals. Thus the MOSFET is
a voltage-controlled device. In the ON-state, the MOSFET can allow current in only one direction (from
drain to source for n-channel MOSFETs and from source to drain for p-channel MOSFETs). In the OFF-
state, they can support only unidirectional voltages in a manner similar to the BJT.
A structural schematic of an n-channel power MOSFET is shown in Figure 1.18(a). It consists of three
layers, viz., (a) an n-type semiconductor that is connected to the drain D; (b) an n-type semiconductor that
is connected to the source S and (c) in between the drain and the source is a p-type semiconductor that is on
the substrate. Generally the substrate is connected to the source within the MOSFET. The gate is connected
to a metallic conductor. This is insulated from the bulk of the MOSFET by an insulator that is generally an
oxide of some metal such as silicon dioxide. The symbol for the n-channel MOSFET is shown in Figure
1.18(b) and the symbol for the p-channel MOSFET is shown in Figure 1.18(c). Note that for the n-channel
MOSFET, the arrow mark shown in the symbol points inwards towards the gate and in the case of a p-chan-
nel MOSFET, the arrow mark points outwards, that is, away from the gate.
When a positive voltage is applied at the gate as shown in Figure 1.19, an electric field will be generated
across the insulating oxide layer. This brings about a polarization of charges within the oxide layer. Conse-
quently, these charges attract electrons from the p-material thereby creating an induced n-channel that

D
D

G
Polysilicon n
metal
S

Substrate (b)
p
G

n S
G

Insulating layer of
metal oxide S D
(e.g. silicon dioxide)

(a) (c)

Figure 1.18 (a) Structural schematic of an n-channel MOSFET; (b) symbol of an

n-channel MOSFET; (c) symbol of a p-channel MOSFET.

Chapter 01.indd 22 3/12/2009 3:47:52 PM

Power Semiconductor Switches 23

+ −
+ −
+ − p
+ −
G + −
+ −
n

Vgs

Figure 1.19 Operation of the MOSFET.

bridges the n-type drain and source regions of the MOSFET. If a positive drain voltage is now applied
between D and S terminals, the n-channel bridge provides a conducting path between the two n-regions.
This conducting path that bridges the two n-type semiconductors in the MOSFET is called the inversion
layer. As the voltage Vgs is increased, the width of the inversion layer increases. The MOSFET is said to have
reached full enhancement when the inversion layer width is maximum.
It can be noted that there is a parasitic NPN BJT between the drain and source contacts with p substrate
serving as the base of the parasitic BJT. To minimize the possibility that this transistor is ever turned ON,
the p-type substrate is shorted to the source region as indicated in Figure 1.18. As a result of this short, a
parasitic diode called the body diode exists between the drain and source of the MOSFET. This integral
body diode can be used in many circuit conﬁgurations to advantage, thereby avoiding the use of an external
diode that is required in such topologies.
Figure 1.18(a) gives the structural schematic of the MOSFET from a functional viewpoint. However, a typi-
cal cross-section of the practical MOSFET is as shown in Figure 1.20. The MOSFET has associated capacitances
with respect to its terminals. This parasitic capacitance model of the MOSFET is shown in Figure 1.21. One should
be aware that while manufacturing the MOSFET, a reverse diode from source to drain (i.e., anode at source and
cathode at drain) gets inherently built by shorting the substrate and the source. This internal diode or the body
diode is advantageous as it can be used for freewheeling purposes in inverters that are driving inductance loads.
Referring to Figure 1.20, the capacitance between the drain and the source Cds varies in accordance with
the width of the depletion layer that in turn depends on the voltage being supported by the device. The gate
source capacitance consists of three components Cgsn, Cgsp and Cgsm (the metal to gate lead capacitance that
is not indicated in Figure 1.20). Of these capacitances, Cgsp depends on the width of the inversion layer that
in turn depends on the applied gate–source voltage. Of particular interest is the feedback capacitance Cgd.
This capacitance plays a dominant role during switching. This is also the most voltage dependent. Cgd is
essentially two capacitors in series such that
1 1 1
= + (1.32)
C gd C gdox C gdbulk

Chapter 01.indd 23 3/12/2009 3:47:53 PM

24 Power Electronics

Cgsn Cgsp Cgdox

S S

n n

p p

Cds Cgdbulk n

Figure 1.20 Structure of the MOSFET.

Cgd

G
Cds

Cgs

S
Figure 1.21 Parasitic capacitance model of the MOSFET.

Chapter 01.indd 24 3/12/2009 3:47:53 PM

Power Semiconductor Switches 25

All the capacitances vary according to the thickness of the depletion region. Figure 1.21 depicts the capaci-
tance model of the MOSFET. Most MOSFET datasheets do not refer to these capacitances. However, they
provide information on the input capacitance Ciss, the output capacitance Coss and the feedback capacitance
Crss. The datasheet capacitances relate to the parasitic capacitances shown in Figure 1.21 as follows:
Ciss: Parallel combination of Cgs and Cgd
Coss: Parallel combination of Cds and Cgd
Crss: Equivalent to Cgd

Static Characteristics
The magnitude of the gate–source voltage Vgs essentially determines the drain current. Figure 1.22(a) shows
the drain current id versus gate–source voltage Vgs characteristics. It can be observed from Figure 1.22(a) that
there is a threshold voltage VgsT below which the device is OFF. This VgsT is of the order of 3–4 V in most
power MOSFETs. Figure 1.22(b) shows the drain current id versus drain–source voltage Vds. In the active
region, the drain current is independent of the drain–source voltage and depends only on Vgs. This relation
is approximately given by
id ∝ (Vgs − VgsT )2 (1.33)
The MOSFET is said to be in the Ohmic region if Vds is less than (Vgs – VgsT). The boundary between the
Ohmic and active region is depicted in Figure 1.22(b). The Ohmic region corresponds to the saturation
region of BJT output characteristics. The MOSFET in the ON-state will operate in the Ohmic region. The
drain to source resistance of the MOSFET in the Ohmic region is denoted by RDS(ON) and is an important
selection parameter for the device.
In order to reduce the power dissipation in the ON-state, the device should have a low RDS(ON). A Vgs
of ∼10 V will take the MOSFET to the ON-state. However, in practical circuits, a Vgs of 15 V is applied in
order to take the MOSFET to full enhancement such that the RDS(ON) is low. The maximum Vgs that can be
applied is limited to +20 V, as only this much Vgs can be supported by the thin oxide layer.

Dynamic Characteristics
Power MOSFETs are intrinsically faster than BJTs as they have no excess minority carriers that must
be moved into or out of the device during turn-ON and turn-OFF conditions. The only charges that must be

Vgs − VgsT

id id Vgs
Ohmic
region

Active
region

VgsT Vgs Vds

(a) (b)

Figure 1.22 Static characteristics of MOSFET.

Chapter 01.indd 25 3/12/2009 3:47:53 PM

26 Power Electronics

Gate
drive (a)
signal

Vgs

VgsT
(b)

t0 t1 t2 t3 t4 t5 t6 t7 t8
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

(c)

Vds

(d)

Figure 1.23 Switching characteristic of MOSFET.

moved in or out are those on the stray parasitic capacitances due to oxide and depletion layers. The parasitic
capacitances have been shown in Figure 1.21. The dynamic or the switching characteristics of the MOSFET
are shown in Figure 1.23. The switching characteristic of the MOSFET is divided into various intervals.
These intervals are explained based on the capacitance model of the MOSFET shown in Figure 1.21. For
the purpose of the discussion regarding the switching behavior of the MOSFET, the current fed to the gate
can be assumed to be a constant ﬂowing into the gate terminal during the turn-ON period, that is, t0–t4.
During the period t4–t5 when the MOSFET is ON, the gate current is negligible. During the period t5–t8,
when the MOSFET is turning OFF, the gate current is again assumed as constant but ﬂowing out of the
gate terminal. The equivalent circuit of the MOSFET during the turn-ON process at the various intervals is
depicted in Figure 1.24. Referring to Figures 1.23 and 1.24, the switching action of the MOSFET is dis-
cussed referring to the various time intervals.

Chapter 01.indd 26 3/12/2009 3:47:54 PM

Power Semiconductor Switches 27

Vdd Vdd

Load Load

igd

D D

ig Cgd ig Cgd

G G
id = f(Vgs)
igs
Cgs Cgs

gnd S gnd S

(a) (b)

Vdd Vdd

Load Load

D D
− −
Cgd Cgd
ig + ig +

G G
RDS(ON)
+ +
Cgs Cgs
− −

gnd S gnd S

Figure 1.24 Equivalent circuits during turning ON of a MOSFET: (a) During interval t0 – t1;
(b) during interval t1 – t2; (c) during interval t2 – t3; (d) during interval t3 – t4.

During Interval t0–t1

At t0, let there be an initial charge of Q 0 at the gate to source capacitance. An amount of charge (Q1 – Q 0) is
required to charge the gate to the threshold voltage VgsT . The gate current ﬂows through Cgs and Cgd as shown
in Figure 1.24(a).
At turn-ON, Cgs is charged by a current
dVgs
igs = C gs
dt

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28 Power Electronics

and Cgd is charged by a current

dVgd dVds
igd = C gd ≈ −C gd .
dt dt
During Interval t1–t2
An amount of charge (Q2 – Q1) is required such that the full drain current id ﬂows. The equivalent circuit is
as shown in Figure 1.24(b).

During Interval t2–t3

The equivalent circuit is as shown in Figure 1.24(c). During this interval, almost the entire gate current
ﬂows through the capacitance Cgd. As a consequence, the charge on Cgs is almost constant. This leads to an
almost ﬂat Vgs waveform during this interval as indicated in Figure 1.23(b). The drain-to-source voltage
waveform starts falling as the MOSFET moves further into the Ohmic region. The rate at which Vds falls as
Cgd gets charged is
dVds dVgd ig
=− = (1.34)
dt dt C gd

During Interval t3–t4

Once the drain–source voltage has dropped to its ON-state value of idRDS(ON), Cgs gets charged such that the
MOSFET is driven to full enhancement. An amount of charge (Q4 – Q3) is required for the MOSFET to be
taken to full enhancement. The equivalent circuit is as shown in Figure 1.24(d).

During Interval t4–t5

During this interval, the MOSFET is fully ON and no charge is required to maintain it in its ON-state.
Thus the gate current is zero during the time when the MOSFET is fully ON.

During Interval t5–t6

At instant t5, the gate signal to the MOSFET is made zero. Now the MOSFET begins the turn-OFF pro-
cess. The charge (Q6–Q5) is the excess gate charge from Cgs that is required to be removed to bring the
MOSFET out of full enhancement.

During Interval t6–t7

(Q7–Q6) amount of charge has to be discharged to bring the MOSFET out of the Ohmic region to the
OFF-state. The drain–source voltage Vds increases during this time as indicated in Figure 1.23. The feedback
capacitance Cgd is discharged during this period. The rate at which the voltage across the feedback capaci-
tance Cgd, reduces will be same as the rate at which the drain–source voltage rises.

During Interval t7–t8

(Q8–Q7) is the charge required to be discharged from Cgs to fully turn-OFF the MOSFET as indicated in
Figure 1.23. One should note that the gate drive source should be able to sink during the discharge dura-
tion. The interval t1–t2 where the drain current rises up to its full value corresponds to the rise time tr and
the interval t7–t8 where the drain current falls from its full value to zero corresponds to the fall time tf . [A
typical MOSFET has the following speciﬁcations: for example, for BVZ 45 B, 500 V, 10 A MOSFET has
Cgs ∼ 4000 pF; Cgd ∼ 100 pF; Cds ∼ 300 pF; tr ∼ 100 ns; tf ∼ 120 ns.]

Chapter 01.indd 28 3/12/2009 3:47:54 PM

Power Semiconductor Switches 29

D D

Rg1 Rg2
G
G
S
S

Figure 1.25 Paralleling of MOSFETs.

Paralleling of MOSFETS
The Ohmic region resistance RDS(ON) is due to majority carriers. It has a positive temperature coefficient.
This is advantageous when paralleling the devices. Current sharing resistors in series with the source are
normally not required (as in the case of BJTs). Incidentally it can be noted that due to positive temperature
coefficient of RDS(ON), the second breakdown will not take place in MOSFETS. In case there is a non-uni-
form distribution of the drain current, as the current increases in any section, the RDS(ON) will increase for
that particular local section and as a consequence the current will reduce in that section and spread from the
hot spot region to other areas.
If MOSFETS have to be connected in parallel, the schematic shown in Figure 1.25 is generally used.
The drains and sources can be connected in parallel directly. While this can take care of the static condition,
it is necessary to put small gate resistances of 10–100 Ω to damp high frequency oscillations that might
result between gate leads and the parasitic device capacitances.
One should note that for a given rated current, the voltage drop will be much higher for a high-voltage
MOSFET (RDS(ON) ∼1 to 2 Ω) than for a low-voltage device (RDS ∼ 0.1 Ω). This is due to the fact that the
bulk n-region, that is, the drain region has to be larger in order to be capable of withstanding the electric
field due to the higher applied voltage.

Handling Precautions for MOSFET

The gate–source oxide layer is very thin. Therefore, when touched with our body (that can have a minimum
of 1–2 μC charge) the ﬁelds created can be extremely high so as to breakdown the oxide layer.

Remarks on BJT and MOSFET

1. BJTs have lower conduction losses in ON-state but higher switching losses whereas power MOSFETs
have higher conduction losses and lower switching losses. Thus at higher frequencies, power MOSFETS
are the obvious choice.
2. BJTs are current-controlled devices whereas MOSFETs are voltage-controlled devices.
3. It is easier to parallel power MOSFETs when compared to BJTs.
4. BJTs suﬀer from secondary breakdown, but the power MOSFETs do not suﬀer from secondary
breakdown.

Chapter 01.indd 29 3/12/2009 3:47:54 PM

30 Power Electronics

EXAMPLE 1.1 Consider a MOSFET with a Cgs = 4000 pf. From the basic charge–potential
relationship,
Q = CV
The voltage across the gate–source capacitance that would get developed for a charge
of 1 μC is
Q 1 × 10−6
Vgs = = = 250 V
C gs 4 × 10−9

The maximum gate–source voltage that is allowable is only 20 V. Therefore, just

touching a MOSFET may damage it permanently and hence the MOSFETs must
be always carried in a conducting pad, so that the charge leaks if it tries to build up.
While not in use, it is recommended to short the gate and source of the MOSFET
with a conducting jumper or wire so that the gate–source voltage does not build
due to spurious electrostatic ﬁelds. In order to limit the Vgs to 20 V, it is always a
good practice to clamp the voltage across the gate-source terminals of a MOSFET
by connecting a 15 V Zener diode close to gate and source leads.

Power Dissipated in a Power MOSFET

The ON-state loss for the MOSFET is given by

PON = I drms
2
RDS( ON) (1.35)

RDS(ON) has a temperature coefficient of approximately 0.6% per oC and should be considered to cal-
culate RDS(ON) (and PON) as the device temperature rises. In a manner similar to the discussion with
regard to the BJT, the switching loss for resistive loads, assuming linear rise and decay of Vds and id ,
is given as
1
Pswitching = Vds I d (t r + t f ) f s (1.36)
6

Model for Power MOSFET

There are diﬀerent levels of MOSFET models that have been used depending on the application. For
integrated circuit fabrication using simulation, more complex models are necessary. Figure 1.26 shows a
simple model that can be used for macro circuit simulation. In Figure 1.26, the capacitance subscript
“gs” means gate to source, “gd” means gate to drain, “gb” means gate to bulk and “sb” means substrate
to bulk.

1.10 Insulated Gate Bipolar Transistor (IGBT)

T he IGBT is a combination of the advantageous features of MOSFET (like high drive input imped-
ance, voltage control, fast switching) and BJTs (like low ON-state losses and high OFF-state voltage
capability). The IGBT is also a three-terminal device. It has an emitter lead E (analogous to the emitter of

Chapter 01.indd 30 3/12/2009 3:47:55 PM

Power Semiconductor Switches 31

D
Cgb

RD
Cgd

Substrate
RDS Id
G Rgs Rss

Cgs Csb
RS

Figure 1.26 Simulation model of a MOSFET.

the BJT), a collector lead C (analogous to the collector of the BJT) and a gate lead G (analogous to the gate
of the MOSFET). The ﬂow of current from the collector to the emitter is controlled by the voltage applied
between the gate–emitter terminals. Therefore, like the MOSFET, the IGBT is also a voltage-controlled
device. In the ON-state, the IGBT can allow current in only one direction (from collector to the emitter
for n-channel IGBTs and from emitter to the collector for p-channel IGBTs). Further, they can support
bipolar voltages during the OFF-state.
A structural schematic of an n-channel IGBT is depicted in Figure 1.27(a). It consists of four layers: a
p-type semiconductor that is connected to the collector C, an n-type semiconductor that is connected to the
emitter E and in between is a p–n semiconductor junction. The gate is connected to a metallic conductor.
This is insulated from the bulk of the IGBT by an insulator that is generally an oxide of metal, like, silicon
dioxide. The symbol for the n-channel IGBT is shown in Figure 1.27(b) and that for a p-channel IGBT is
shown in Figure 1.27(c).
When a positive voltage is applied at the gate as indicated in Figure 1.28, an electric ﬁeld will be directed
through the insulating oxide layer. This brings about polarization of charges within the oxide layer. As a
consequence, electrons from the p-material get attracted towards the insulating oxide layer thereby creating
an induced n-channel that bridges the two n-type sections of the IGBT. The induced n-channel along with
the two n-sections forms an equivalent n-type semiconductor. The p-type semiconductor connected to the
collector C along with the equivalent n-type semiconductor forms an equivalent p–n junction and behaves
like a diode. Because of the formation of the equivalent p–n junction, the IGBT is capable of withstanding
reverse voltages also during the OFF-state.
From the structural schematic of the IGBT, it is evident that an IGBT can be viewed equivalently as a
MOSFET with a diode connected to its drain as indicated in Figure 1.29. Alternatively, it can also be
viewed as a MOSFET and a PNP transistor as shown in Figure 1.30.
The detailed structure of the IGBT is shown in Figure 1.31. One should note that the IGBT has a para-
sitic thyristor between its collector and emitter as indicated in Figures 1.31 and 1.32. This parasitic thyristor
should not latch. If it latches then the IGBT will loose the gate control. Therefore, when the IGBT is

Chapter 01.indd 31 3/12/2009 3:47:55 PM

32 Power Electronics

C C

p
G

Polysilicon E
metal n
(b)

p E
G

n
G

Insulating layer of
metal oxide
(e.g., silicon dioxide) E C
(a) (c)

Figure 1.27 (a) Structural schematic of an n-channel IGBT; (b) symbol of an n-channel IGBT;
(c) symbol of a p-channel IGBT.

+ −
+ −
+ − p
+ −
G + −
+ −
n
Vge

Figure 1.28 Operation of the IGBT.

Chapter 01.indd 32 3/12/2009 3:47:55 PM

Power Semiconductor Switches 33

p
G

n G

Figure 1.29 Equivalent circuit of IGBT: Diode and MOSFET.

C
C
p

n n

p p
G

n
G
E

Figure 1.30 Equivalent circuit of IGBT: Transistor and MOSFET.

manufactured, Rs as indicated in Figure 1.32 is made very low so that the drop across it is less than cut-in
voltage of the base–emitter of the NPN transistor in the parasitic thyristor. This way the NPN transistor is
always oﬀ, thereby avoiding the latching problem. One should be aware that while manufacturing the
IGBT, a reverse diode from emitter to collector (i.e., anode at emitter and cathode at the collector) is built
separately as it is not inherent like in the case of the MOSFETs. This internal diode or the body diode
is required for freewheeling purposes in topologies that are driving inductance loads.

Chapter 01.indd 33 3/12/2009 3:47:55 PM

34 Power Electronics

E E

n n

p p

n n

Figure 1.31 Structure of an IGBT.

Parasitic
thyristor

G Rs

Figure 1.32 Equivalent circuit of the IGBT showing the parasitic thyristor.

Static Characteristics
The ic–Vce characteristics of an n-channel IGBT are shown in Figure 1.33 and the ic–Vge characteristics are
shown in Figure 1.34. From Figure 1.33 it is observed that the IGBT can support both forward and reverse
voltages during the OFF-state. From Figure 1.34, it is seen that if Vge is less than the threshold voltage, the
IGBT is in the OFF-state.

Chapter 01.indd 34 3/12/2009 3:47:56 PM

Power Semiconductor Switches 35

ic
Active region
Vge

Vce
Reverse characteristics Forward characteristics

Figure 1.33 Static ic–Vce characteristic of an IGBT.

VgeT Vge
(Threshold voltage)

Figure 1.34 Static ic–Vge characteristic of an IGBT.

In comparison, for a given ic, the Vce(sat) of the IGBT is less than the Vds of a comparable MOSFET
when ON but greater than Vce(sat) of a comparable BJT.

Dynamic Characteristics
The dynamic behavior of an IGBT is similar to that of a MOSFET when viewed from the gate side and is
similar to that of a BJT when viewed from the collector side. However, the maximum switching frequency
is limited as compared to that of a MOSFET.
The switching times of the IGBT are related to the gate–emitter voltage and collector-current wave-
forms. Figure 1.35 shows the typical switching waveforms. The switching times of an IGBT are mainly
determined by its internal capacitances and parasitic inductances together with the internal resistance

Chapter 01.indd 35 3/12/2009 3:47:56 PM

36 Power Electronics

Vge

90%

(a)

10%
t
Vce

(b)

t
ic

90%

(c)

10%
t

td(on) td(off) tf
tr

ton toff

Figure 1.35 Dynamic switching characteristics of an IGBT.

of the gate-side voltage source. In order to charge and discharge the capacitances rapidly and to reduce the
transients caused by the gate circuit inductance, a low internal impedance of the gate-side voltage source is
desirable. It shortens the switching times and reduces the switching losses. On the other hand, a very fast
turn-ON causes a high peak reverse recovery current through the body diode that appears as an additional
peak collector current. During very fast turn-OFF, a high transient voltage is caused by the parasitic collec-
tor–emitter inductance as shown in Figure 1.35(b).
It is very important to keep the parasitic inductance in the gate circuit at a minimum by using very short
leads. This inductance might otherwise generate parasitic oscillations in conjunction with the IGBT
capacitances. The maximum rated gate–emitter voltage as speciﬁed in the datasheets in most cases is ±20 V.
It is recommended to connect a 15 V Zener diode between the gate and the emitter as a protective clamper.

Turn-ON
During turn-ON, the IGBT behavior is more like that of a MOSFET. The collector–emitter voltage, the
collector-current and the gate–emitter voltage waveforms are similar to the turn-ON waveforms of the

Chapter 01.indd 36 3/12/2009 3:47:57 PM

Power Semiconductor Switches 37

MOSFET. When the gate–emitter voltage reaches the threshold value of VgeT , the collector-current starts to
rise. The time interval between the instant when Vge reaches 10% of its final value and the instant when ic
reaches 10% of its final value is called the turn-ON delay time td(on). The subsequent time interval up to the
instant when the collector current reaches 90% of its final value is called the rise time tr. During this period
of time, most of the turn-ON power dissipation takes place. The sum of the turn-ON delay time td(on) and
the rise time tr is called the turn-ON time ton. At the end of ton, the collector–emitter voltage Vce often has
not yet fallen to its final value of Vce(sat). This has to be considered when calculating the turn-ON dissipation.
The collector-current peak shown in Figure 1.35 indicates the peak reverse recovery current of the body diode
or the freewheeling diode. This peak current has to be taken into account in any turn-ON power dissipation
calculations as well.

Turn-OFF
During turn-OFF, the IGBT behaves more like a BJT. To turn the IGBT OFF, the voltage in the gate con-
trol circuit is switched to zero. Referring to Figure 1.35, there is first a turn-OFF delay time td(off ) that is the
interval between the instant when the gate–emitter voltage has fallen to 90% of its initial value and the
instant when the collector current has fallen to 90% of its initial value. The subsequent period of time up to
the instant when the collector current has fallen to 10% of its initial value is called the fall time tf . The sum
of td(off) and tf is called the turn-OFF time toff .

Tail Current
The tail current and tail time are properties that are speciﬁc to the IGBT. However, they also depend on the
operating conditions. The tail current is higher for lower saturation voltage Vce(sat). The trade-oﬀ for the favor-
able reduction of the conducting state power loss is an increase in the tail current. Since at pulse frequencies
of 10–20 kHz the switching losses are more prevalent, most IGBTs are designed for a low tail current at the
expense of the saturation voltage which would be a little higher than the minimum possible value.

Remarks on IGBT
1. The power loss calculations for the IGBT are similar to the loss calculations indicated for BJTs and
MOSFETs.
2. The gate drive power is low such as in the case of MOSFETs.
3. IGBT has considerably greater overload capability as compared to a MOSFET. For a MOSFET, the
peak overload is about 5–6 times the continuous drain current whereas for the IGBT, the peak overload
is about 20 times the continuous collector current. An IGBT is capable of taking a short-circuit current
(across a 600 V bus) for a period of 10 μs.
4. Over voltage robustness is less than that of MOSFETs.
5. IGBTs are more like the BJTs during turn-OFF and like the MOSFETs during turn-ON.
6. Unlike the BJT, where the collector current is limited by the current gain, that is (hFE(sat)ib), the IGBTs
do not have such limitations. The collector current is limited only by the external source.

1.11 Thyristor Family

T he term thyristor is a generic name for a semiconductor switch having four or more layers and is in
essence a p–n-p–n structure. Thyristors form a large family of semiconductor switches. If an Ohmic
connection is made to the ﬁrst p-region and the last n-region and no other connection is made to any other
intermediate region, then the device is a diode thyristor. If an additional Ohmic connection is made to the

Chapter 01.indd 37 3/12/2009 3:47:57 PM

38 Power Electronics

intermediate n-region or the intermediate p-region, the device is called a triode thyristor. If an Ohmic con-
nection is made to both intermediate regions, then the device is a tetrode thyristor. All such devices have a
forward characteristic of the form shown in Figure 1.36.
There are three categories of thyristor reverse characteristic: blocking (as in normal diodes like in sym-
metric SCRs), conducting (large reverse current at low reverse voltages like in asymmetric SCRs and GTOs)
and approximate mirror image of the forward characteristic (bi-directional thyristors like in DIACs and
TRIACs). The simplest thyristor structure and the most common is the reverse blocking triode thyristor
usually referred to as the silicon-controlled rectiﬁer (SCR). The more complex thyristor structure is the
bi-directional triode thyristor or TRIAC. In this section, the various devices in the thyristor family will be
brieﬂy reviewed.

Silicon–Controlled Rectifier (SCR)

SCR is a three-terminal device with an anode terminal A, a cathode terminal K and a control or gate termi-
nal G. Structurally it is similar to a BJT with an extra p-layer at the anode. The structure of the SCR is
depicted in Figure 1.37(a) and the circuit symbol is shown in Figure 1.37(b).

ig = 0

VBR
VBF V
AK

Figure 1.36 Forward characteristics of the thyristor family.

K G K

n n

A
n

p
G

A K
(a) (b)

Figure 1.37 (a) Structure of an SCR; (b) symbol of an SCR.

Chapter 01.indd 38 3/12/2009 3:47:57 PM

Power Semiconductor Switches 39

Static Characteristics
Application of a negative voltage to the anode–cathode of an SCR will reverse bias the SCR. In this condition,
the junctions J1 and J3 are reverse-biased and J2 is forward-biased. The device is said to be in the OFF-state and
blocks the reverse voltage. On the other hand, applying a positive voltage to the anode–cathode, as shown in
Figure 1.38, with the gate open, will forward bias the SCR. With the anode–cathode voltage positive, it can be
observed that junctions J1 and J3 are forward-biased and J2 is reverse-biased. The SCR is still in the OFF-state
and blocks the applied forward voltage. This is a property unique to the thyristor family. If forward-bias voltage
is further increased, the junction J2 will breakdown and the device turns ON behaving in a manner similar to
a diode. The static characteristic is shown in Figure 1.39. Figure 1.39(a) shows the static characteristics when
the gate current is zero. The voltage at which the junction J2 breaks down and the SCR conducts is called the
forward breakover voltage VBF . If the gate of the SCR is connected to a voltage source and a gate current is
allowed to ﬂow, then the breakover voltage reduces as indicated in Figure 1.39(b).
The SCR action is best understood by modeling it as two BJTs connected as shown in Figure 1.40. With
the gate open or shorted to the cathode, the device is OFF and no current ﬂows from anode to cathode,
except for a very low leakage current. If an external positive current pulse is applied to the gate, it becomes
the base current of the NPN transistor Q2. Consequently, the collector current of Q2 supplies the base cur-
rent to the PNP transistor Q1. The collector current of Q1 then further increases the base current of Q2 and
so on. This iterative action maintains the device in the conducting state even if the gate signal is now
removed. The device continues to conduct till the anode voltage is less positive than the cathode voltage.
Figure 1.39(b) shows the static characteristics with gate current as a parameter. It should be noted that once
the device is ON, the gate looses complete control of the device and the device cannot be turned OFF
through the gate. The SCR can be switched OFF only if the anode current is brought below a threshold
called the holding current value for that SCR.

Dynamic Characteristics
di/dt Effect On supplying the gate trigger to a forward-biased SCR, the SCR will turn ON. The anode
current starts to rise after a small delay. The rate of change of the anode current will depend on the nature of

J1
n VAK
J2
G
p
J3

Figure 1.38 Biasing the SCR.

Chapter 01.indd 39 3/12/2009 3:47:57 PM

40 Power Electronics

ig = 0

VBR
VBF VAK

(a)

VBR
VBF VAK

(b)

Figure 1.39 V–I characteristic of an SCR (a) with gate open; (b) with gate current applied.

A
p
Q1

n
p

p
G G

Q2
n

(a) (b)

Figure 1.40 Two transistor equivalent circuit of an SCR.

Chapter 01.indd 40 3/12/2009 3:47:58 PM

Power Semiconductor Switches 41

the load. Initially the ON-state current is concentrated in a small area around the gate region. If the rate of
rise of this ON-state current is high, then the area around the gate region will become overheated that may
permanently damage the device. Therefore, it should be ensured that the external circuit di/dt encountered
by the SCR should be less than the rated di/dt of the device.
Turn-OFF Characteristics The turn-OFF characteristic waveforms of the anode current and the anode–
cathode voltage are similar to that of the diode with the added restriction that all junctions including the
gate junction should fully recover before the SCR gets into a forward-blocking state. The turn-OFF charac-
teristics are depicted in Figure 1.41.
A high rate of rise of the applied forward voltage across the anode and cathode (dv/dt) can trigger the
SCR. To keep the SCR turned OFF, the re-application of the OFF-state forward voltage must be delayed to
avoid re-triggering due to high dv/dt. The circuit commutated recovery time tq is measured from the zero
crossover of the current as shown in Figure 1.41. It should be noted that tq is an important parameter. SCRs
are often classiﬁed as line-commutated or converter grade if tq > 50 μs and as inverter grade if tq < 20 μs. For
the line commutated converter, tq is less important since the half-period is 10 ms. But for inverter circuits
switching at higher frequencies, inverter grade SCRs with appropriately lower tq will have to be used.
dv/dt Effect Figure 1.41 shows a possible problem with large rate of forward voltage, dv/dt. If dv/dt is
large, the SCR may self-trigger even in the absence of gate current. This is due to the fact that there exists
a leakage current through the reverse-biased junction. This leakage current ﬂows through the capacitance
of junction J2 and is given by i = c dv/dt. This leakage current is dependent on dv/dt. If this leakage current

trr

VAK

dVF /dt Forward

blocking

Figure 1.41 Anode current and anode–cathode voltage during turn-OFF.

Chapter 01.indd 41 3/12/2009 3:47:58 PM

42 Power Electronics

is larger than the latching current of the device, then the device will self-trigger and go into conduction
even in the absence of the gate current. Therefore a high dv/dt has the possibility of undesirable latch up
of the device. Practical SCRs have dv/dt limits of about 200–500 V/μs. In circuits wherein the dv/dt
exceeds the rated dv/dt limits of the device, additional circuits called snubber circuits will have to be used
to lower the dv/dt.

Other Parameters
The various current ratings like ITav , ITrms , ITsurge are similar to those discussed for the diode. The ratings are
a bit complicated compared to a diode. The value given in the datasheet for the mean ON-state current ITav
is valid for a certain waveform and case temperature. ITrms signifies the heating effect due to i2R dissipation
and is limited due to the thermal stress on the device. ITSM is the maximum permissible peak current of half
sine wave with a duration of 10 ms at a specified temperature.
Power dissipated in a thyristor is calculated in the same way as that of the diode. Gate-current losses add
to the power losses in the case of thyristors as compared with the diode losses. Power loss calculation depends
on the type of waveform too. Thyristors are very rugged devices as they can carry considerable overload cur-
rents without exceeding the junction temperature.

Circuit Model
There are many circuit models of SCRs available in the literature and circuit simulator libraries like SPICE.
One such simple model is given here. It can be constructed using the two-transistor analog of an SCR as
shown in Figure 1.42. Diode DFOR is added to model the forward breakdown. A resistance is added across
the base–emitter of Q2 to provide a discharge path for the stored charges in Q2. The various parameters for
the PNP and NPN transistors are included in the model to give a satisfactory simulation performance.

DIACs and TRIACs

DIAC is a two-terminal device without any gate. It is a bi-directional switch. The breakdown voltage is gener-
ally kept low (∼30 V) because it is generally used as a threshold device in many applications. Figure 1.43(a)
shows the DIAC characteristics and Figure 1.43(b) depicts its symbol.

DFOR

125 Ω Q2

Figure 1.42 Circuit model of an SCR.

Chapter 01.indd 42 3/12/2009 3:47:58 PM

Power Semiconductor Switches 43

MT2

VAK

MT1

(a) (b)

Figure 1.43 DIAC: (a) v–i characteristic; (b) symbol.

ig
MT2

VAK
G MT1
(b)

(a)

Figure 1.44 TRIAC: (a) v–i characteristic; (b) symbol.

TRIAC is also a bi-directional thyristor switch but it has a gate terminal that is used for controlling the
turn-ON of the TRIAC. It is mainly used for AC control applications. As the switch is bi-directional, its
terminals are called main terminal 1 and 2 (MT1 and MT2), instead of anode and cathode. Figure 1.44(a)
shows the characteristics of the TRIAC and Figure 1.44(b) depicts its symbol. A simple TRIAC control
circuit is shown in Figure 1.45. This circuit uses a DIAC as a threshold device for triggering the TRIAC at a
particular source phase angle.
There are different ways in which the gate can be fired. The most common is with reference to MT1. The
polarity of voltage across MT2 and MT1 decides the direction of current flow, and gate pulse is always positive
irrespective of direction of current flow. TRIACs are generally used for 50 Hz applications. With inductive
load, the TRIAC will be subjected to large dv/dt and therefore protective snubber circuits must be used.

Chapter 01.indd 43 3/12/2009 3:47:58 PM

44 Power Electronics

Load

MT2
DIAC
TRIAC
MT1
230 V AC
MT2 G MT1

Figure 1.45 TRIAC control circuit using DIAC.

Gate Turn-OFF Thyristor (GTO)

It can be recalled that an SCR cannot be turned OFF by gate control. It needs an extra turn-OFF/commutation
circuit. GTO has been devised to provide turn-OFF through the gate terminal. The GTO is a four-layer
device that can be turned ON with a positive gate current pulse and turned OFF with a negative gate current
pulse. Figure 1.46(a) shows some of the commonly used GTO symbols.
The physical structure of a GTO is shown in Figure 1.46(b). Referring to figure, it may be observed that
the gate and cathode are interspersed. Such a sectionalized geometry helps in having better gate control.
The anode layer has n- and p-regions interspersed as shown in Figure 1.46(b). This gives a structure termed
as the “anode short” structure that is found to improve the turn-OFF time.
GTO action can also be described by the two-transistor model as discussed for the case of an SCR. By
suitably controlling the doping profiles of the n- and p-regions, the a and b of the transistors, it is possible
to achieve gate turn-OFF with a negative gate current. Removal of excess charge is an important part of
the turn-OFF process. The negative gate current and the anode current during the turn-OFF process are
depicted in Figure 1.47.
The SCR and GTO differences are highlighted below:
1. GTO has higher ON-state drop as compared to the SCR. The GTO has an ON-state drop of about
3–4 V whereas the SCR has an ON-state drop of around 1.5–2 V.
2. The latching and holding currents are high for a GTO. As an example, a typical 110 A SCR has IH of
150 mA and IL of 300 mA, whereas even a low current GTO, a typical 18 A GTO has IH = 600 mA and
IL = 900 mA. For 30 A GTO, they are more than 1 A. Therefore the triggering pulse must be long
enough or continuous for the GTO unlike the case of the SCR.
3. The reverse-blocking capability of a GTO is very low (∼20 V) and hence cannot be used in rectifier
applications.
4. When the device is to be turned OFF, the turn-OFF amplification factor (anode current with respect to
the turn-OFF gate current) can be anywhere between 1 and 5 and the turn-OFF time between 1 and
several milliseconds. There is a maximum current rating beyond which gate cannot turn OFF the GTO.
This is called repetitive controllable ON-state current (or extinguishable current).
5. GTO has a large dv/dt capability (1000 V/μs) compared to a SCR (200–500 V/μs).
6. GTOs can be used up to 1–4 kHz of switching frequency range.

Chapter 01.indd 44 3/12/2009 3:47:59 PM

Power Semiconductor Switches 45

A A A

G G G
K K K

(a)

K K K
G G

n+ n+ n+
J3

p
J2
n−
J1
p n+ p n+

(b)

Figure 1.46 (a) Symbols of GTO; (b) structure of a GTO.

0
t

0
t
ts tf

Figure 1.47 Turn-OFF characteristics of a GTO.

Chapter 01.indd 45 3/12/2009 3:47:59 PM

46 Power Electronics

A
A

ON
(n-channel)
OFF
(p-channel)
G
G

K
K

(a) (b)

Figure 1.48 MCT configurations.

MOS-Controlled Thyristor (MCT)

MCT is an interesting device wherein both the turn-ON and turn-OFF can be controlled. However, com-
mercially it is not as popular as the MOSFETs and the IGBTs. Figure 1.48 shows some possible MCT
functional conﬁgurations. Figure 1.48(a) shows an MCT where turn-ON is done in the usual way but turn-OFF
is done using a MOSFET. Figure 1.49(b) shows another conﬁguration wherein an n-channel MOSFET is
used for turning ON the MCT and a p-channel MOSFET is used for turning OFF the MCT. The major
features of an MCT are:
1. It has low conduction voltage drop: 1/3 to 1/2 of a comparable IGBT.
2. It combines high-speed, low-power gate turn-ON–turn-OFF advantages.
3. It has high dv/dt and di/dt capabilities.

| CONCLUDING REMARKS
This chapter discussed few important viewpoints of There are many semiconductor devices avail-
the semiconductor devices giving a ﬂavor for the able commercially that have been fabricated with
operation of the various devices as a power switch. newer and improved technologies. However, this
It should, however, be observed that no single switch chapter discusses only a few generic types, high-
meets all the features of an ideal switch as described lighting the important issues that need to be stud-
in Section 1.1. One should be aware of the non- ied and understood when encountered with a new
idealities of each type of the power switch so that device. With special regard to the semiconductor
the power electronic circuits can be modeled with devices being used as power switches in power elec-
greater closeness to the physical system. tronic circuits, one should study with emphasis on

Chapter 01.indd 46 3/12/2009 3:47:59 PM

Power Semiconductor Switches 47

three aspects in general, viz. (a) static characteristics device. The next section provides some laboratory
that give insight on the steady-state operating exercises that should be implemented both on a sim-
points, (b) dynamic characteristics that give the ulation platform like spice and by hardware bread-
behavior of the switch during turn-ON and turn- boarding to appreciate the functional features of a
OFF and (c) power loss within the device due to particular power semiconductor switch. The labora-
conduction and switching. tory exercises are focused on popular devices like
The theoretical insights should be cemented diodes, BJTs, MOSFETs and IGBTs. However, the
with the experience that can be gained from practi- exercises can be extended for any other power semi-
cal work to strengthen the understanding of the conductor switch too.

| LABORATORY EXERCISES
1. Consider the diode test circuit shown in (b) Find out the forward dynamic resistance of
Figure 1.49 where Vi is a voltage source and D the diode from the i–v characteristic.
is a diode. The diode D is appropriately (c) Use a square waveform input voltage source
chosen such that the current and voltages are and observe the current through the diode
within ratings. and the voltage across it during turn-ON
and turn-OFF.
Mode of implementation: The above circuit
(d) Compute the experimental switching loss
can be studied by
and compare with the theoretical estimate.
a. Simulation in Spice
(e) Compute the experimental conduction loss
b. Hardware breadboarding
and compare with the theoretical estimate.
Tasks for study: (f ) Repeat steps (a)–(c) for different loads by
(a) Use a variable DC voltage source. Measure varying RL.
the current through and the voltage across (g) Repeat steps (a)–(c) for different source fre-
the diode for different input DC voltage quencies. What is the effect on the diode
values. Reverse the polarity of the input power loss?
voltage source and measure the current (h) Measure the trr of the diode from the cur-
through and the voltage across the diode rent waveform through the diode. What is
for different input voltage values. Tabulate the effect of the load on trr?
the diode current and voltage values and (i) Measure the reverse recovery charge Q rr
plot the i–v characteristics of the diode. from the experimental results.
(j) Use a sinusoidal waveform input voltage
D source and observe the current through
and the voltage across it during voltage
id transition from positive to negative.
Vd Compute the power loss in the device
Vi RL and compare the loss with that obtained
when using a square waveform input source.
2. Consider the two BJT test circuits shown in the
Figure 1.50 where Vb is the base drive pulse
Figure 1.49 Diode test circuit. source. Vb should be chosen such that it is capable

Chapter 01.indd 47 3/12/2009 3:48:00 PM

48 Power Electronics

of both sourcing and sinking current. Vc is the a and b parameters. Plot the Ic–Vce charac-
collector DC supply voltage. Rc is the collector teristics for different base current values.
load and Rb is the base drive resistor. The BJT is (b) Set Vb to be a pulse source of frequency 20
chosen with appropriate rating to handle the kHz. Measure the collector current and
collector current and the maximum Vce as the collector–emitter voltage waveforms
decided by Rc and Vc, respectively. The circuit and observe the turn-OFF and turn-ON
of Figure 1.50(a) consists of a resistive collector portions.
load and that of Figure 1.50(b) consists of an (c) Compute the experimental switching loss
R–L load. The diode D is connected as shown and compare with the theoretical estimate.
to provide a freewheeling path for the inductor (d) Compute the experimental conduction
current when the BJT Q is turned OFF. loss and compare with the theoretical
estimate.
Mode of implementation: The above circuit (e) Repeat steps (b)–(d) for different loads by
can be studied by varying RL.
a. Simulation in Spice (f ) Repeat steps (b)–(d) for different base pulse
b. Hardware breadboarding frequencies. What is the effect on the BJT
power loss?
Tasks for study: (g) What is the effect of Rb on the turn-ON
(a) Set Vb to be a DC source. Measure the and turn-OFF times? Why?
collector current and the collector–emitter (h) Perform the steps (b)–(g) for the inductive
voltage across transistor for different load test circuit of Figure 1.50(b).
values of Rb. Tabulate the BJT collector
current, base current, emitter current and 3. Consider the two MOSFET test circuits shown
collector–emitter voltage values. Find the in Figure 1.51 where Vg is the gate drive pulse

Vc L

D
Rc Rc

ic
Rb ib Rb ib
Q Vce Q Vce

Vb Vb

(a) (b)

Figure 1.50 BJT test circuit.

Chapter 01.indd 48 3/12/2009 3:48:00 PM

Power Semiconductor Switches 49

source. Vg should be chosen such that it is Id–Vds characteristics for different gate
capable of both sourcing and sinking current. voltage values.
Vd is the drain DC supply voltage. Rd is the (b) Set Vg to be a pulse source of frequency 20
drain load and Rg is the gate drive resistor. kHz. Measure the drain current and the
The MOSFET is chosen with appropriate drain–source voltage waveforms and
rating to handle the drain current and the observe the turn-OFF and turn-ON
maximum Vds as decided by Rd and Vd, respec- portions.
tively. The circuit of Figure 1.51(a) consists of (c) Compute the experimental switching
a resistive drain load and that of Figure 1.51(b) loss and compare with the theoretical
consists of an R–L load. The diode D is con- estimate.
nected as shown to provide a freewheeling path (d) Compute the experimental conduction
for the inductor current when the MOSFET is loss and compare with the theoretical
turned OFF. estimate.
(e) Repeat steps (b)–(d) for different loads by
Mode of implementation: The above circuit
varying RL.
can be studied by
(f ) Repeat steps (b)–(d) for different gate pulse
a. Simulation in Spice
frequencies. What is the effect on the
b. Hardware breadboarding
MOSFET power loss?
Tasks for study: (g) What is the effect of Vg on the turn-ON
(a) Set Vg to be a DC source. Measure the and turn-OFF times?
drain current and the drain–source voltage (h) What is the effect of Rg on the turn-ON
across the MOSFET for different values of and turn-OFF times?
Vg. Tabulate the MOSFET drain current, (i) Measure the gate current and explain its
and drain–source voltage values. Plot the pulse shape.

Vd
Vd
L

Rd D
Rd
id
Rg ig Rg ig
Vds Vds

Vg Vg

(a) (b)

Figure 1.51 MOSFET test circuit.

Chapter 01.indd 49 3/12/2009 3:48:00 PM

50 Power Electronics

(j) Perform the steps (b)–(g) for the inductive Tasks for study:
load test circuit of Figure 1.51(b). (a) Set Vg to be a DC source. Measure the col-
(k) Compare the switching speed and power lector current and the collector–emitter volt-
loss of MOSFET with comparable BJT. age across transistor for different values of
Vg. Tabulate the IGBT collector current and
4. Consider the two IGBT test circuits shown in
collector–emitter voltage values. Plot the Ic–
Figure 1.52 where Vg is the gate drive pulse
Vce characteristics for different gate voltage
source. Vg should be chosen such that it is
values.
capable of both sourcing and sinking current.
(b) Set Vg to be a pulse source of frequency 20
Vc is the collector DC supply voltage. Rc is the
kHz. Measure the collector current and
collector load and Rg is the gate drive resistor.
the collector–emitter voltage waveforms
The IGBT is chosen with appropriate rating to
and observe the turn-OFF and turn-ON
handle the collector current and the maximum
portions.
Vce as decided by Rc and Vc, respectively. The
(c) Compute the experimental switching
circuit of Figure 1.52(a) consists of a resistive
loss and compare with the theoretical
collector load and that of Figure 1.52(b) con-
estimate.
sists of an R–L load. The diode D is connected
(d) Compute the experimental conduction loss
as shown to provide a freewheeling path for the
and compare with the theoretical estimate.
inductor current when the IGBT is turned
(e) Repeat steps (b)–(d) for different loads by
OFF.
varying RL.
Mode of implementation: The above circuit (f ) Repeat steps (b)–(d) for different gate pulse
can be studied by frequencies.
a. Simulation in Spice (g) Perform the steps (b)–(f ) for the inductive
b. Hardware breadboarding load test circuit of Figure 1.52(b).

Vc L

D
Rc Rc

ic
Rg ig Rg ig
Q Vce Q Vce

Vg Vg

(a) (b)

Figure 1.52 IGBT test circuit.

Chapter 01.indd 50 3/12/2009 3:48:00 PM

Power Semiconductor Switches 51

| FILL IN THE BLANKS

1. Diodes are devices that have two terminals: 18. The safe operating areas give information about
________ and ________. the capability of a device to handle the speci-
fied ________.
2. When the anode is more positive than the
________, the diode is said to be forward-biased. 19. MOSFET is a ________.
3. When the ________ is more positive than the 20. The Ohmic region resistance RDS(ON) is due to
________, the diode is said to be reverse-biased. ________.
4. During turn-OFF of the diode, the ________ 21. RDS(ON) has a ________ temperature coefficient.
stored in the diffusion region has to be ________
before the junction can be reverse-biased. 22. Compared to MOSFETs, BJTs have ________
conduction losses but ________ switching-losses.
5. As long as there are excess charge carriers in the dif-
fusion region, the junction will be in ________. 23. BJTs are ________-controlled devices whereas
MOSFETs are voltage-controlled devices.
6. The bipolar transistor is a ________ device.
24. IGBT is a ________.
7. BJT is a ________ device.
25. IGBT can support ________ voltages during
8. BJT is a ________ device. the OFF-state.
9. Based on the doping type, there are two types 26. In comparison, for a given ic, the Vce(sat) of the
of BJT: ________ and ________. IGBT is ________ than the Vds of a compara-
10. Larger the collector region, ________ is the ble MOSFET when ON but ________ than
amount of voltage that the transistor can with- Vce(sat) of a comparable BJT.
stand during the OFF-state. 27. IGBT has ________ overload capability as
11. The ratio of the collector current to the emitter compared to a MOSFET.
current is called the ________ of the transistor. 28. IGBT has ________ overvoltage robustness than
12. The alpha parameter varies between ________ MOSFETs.
and ________.
29. IGBTs are more like the ________ during
13. Using the Eber-Molls model, the collector cur- turn-OFF and like the ________ during
rent is given as ________. turn-ON.
14. Using the Eber-Molls model, the emitter cur- 30. Thyristors is a generic name for a semiconduc-
rent is given as ________. tor switch having ________ layers.
15. The ratio of the collector current to the base 31. Application of a ________ voltage to the
current is given by ________. anode–cathode of an SCR will reverse-bias the
SCR.
16. The electric field across the transistor is depen-
dent on the ________ and the ________. 32. DIAC and TRIAC are ________ switches.
17. The electric field increases with ________ and 33. In a GTO, the turn-OFF is ________ whereas
with ________. in an SCR, the turn-OFF is ________.

Chapter 01.indd 51 3/12/2009 3:48:01 PM

52 Power Electronics

34. GTO has ________ ON-state drop as compared 36. The reverse-blocking capability of a GTO is
to the SCR. very low and hence cannot be used in _______
applications.
35. The latching and holding currents are _______
for a GTO as compared to the SCR.

| DESCRIPTIVE QUESTIONS
1. What are the characteristic features of an ideal 14. What is second breakdown?
switch?
15. How are transistors connected in parallel?
2. What is a controlled switch? Discuss.
3. What is an uncontrolled switch? 16. How does the current gain, or the beta parame-
ter, increase with the Darlington conﬁguration?
4. What is the depletion region?
17. What are the semiconductor layers in a
5. “The value of the potential barrier in volts depends MOSFET structure?
on the charge carriers and is governed by the
Boltzmann’s relation.” Discuss. 18. What is the inversion layer? How is it formed?

6. With respect to the diode’s V–I static charac- 19. Discuss the MOSFET structure and the vari-
teristics, explain the difference among the ous associated capacitances?
ideal, piece-wise linear and the actual V–I 20. How are the MOSFET capacitances Ciss, Coss
characteristics. and Crss related to the parasitic capacitances
Cgs, Cgd and Cds?
7. Discuss the turn-OFF process in the diode.
21. What is gate threshold voltage?
8. What is meant by reverse recovery time for a
diode? 22. What is Ohmic region of the MOSFET static
characteristics?
9. What is the ON-state loss in a diode?
23. Explain the MOSFET turn-OFF and turn-ON
10. What is the switching loss in a diode? processes?
11. Describe the switching process within a 24. How is the positive temperature coefficient
transistor. advantageous for paralleling of MOSFETs?
12. Derive relationship for the power dissipation 25. Discuss the functional structure of the IGBT.
within the transistor between the applied
26. Explain the turn-ON and turn-OFF of IGBT
collector–emitter voltage, the collector-
with waveforms.
current and the switching frequency of the
transistor for (a) resistive load in the collec- 27. What is tail current in IGBT?
tor, (b) resistive–inductive load in the col-
28. What are holding and latching currents in SCR?
lector and c) resistive–capacitive load across
the collector–emitter of the transistor. 29. What is forward breakover voltage in SCR?
13. Discuss forward and reverse safe operating 30. Discuss the effect of di/dt and dv/dt on the
areas. SCR switch.

Chapter 01.indd 52 3/12/2009 3:48:01 PM

Power Semiconductor Switches 53

| PROBLEMS
1. Find the ratio of the diffusion current to the satu- Icm = 15 A, Vcesat = 0.3 V, hFEmin = 100, td = 1 μs,
ration current for a p–n junction at 75oC having ts = 2 μs, tr = 1.5 μs, tf = 1.5 μs. Calculate the
a forward potential of 0.6 V applied across it. power loss in the BJT.
2. A diode and a 10 Ω resistor are connected in 7. For Problem 6 above, plot the device power
series to a square wave voltage source of 50 V dissipation as the switching frequency varies
peak. Find the conduction loss for the diode if from 1 kHz to 100 kHz.
the forward dynamic resistance is (a) 0.1 Ω and 8. Two BJTs are connected in parallel to share the
(b) 0.2 Ω at the operating point. (Assume the load current. In order to ensure sharing, two
forward barrier potential to be 0.7 V.) equal-valued resistors with value R are con-
3. A diode and a 10 Ω resistor are connected in nected in the emitter leads of the BJTs. For a
series to a pulse voltage source of 50 V peak. If mismatch in the base–emitter voltage of 0.2 V
the forward dynamic resistance is 0.1 Ω at the between the two BJTs, a mismatch in the col-
operating point, then find the conduction loss of lector currents of the two BJTs should be less
the diode when (a) pulse frequency is 20 kHz than 1 A. Calculate the value of the resistors
and pulse width 40 μs, (b) pulse frequency is 20 that needs to be connected in the emitter
kHz and pulse width is 10 μs, (c) pulse frequency leads.
is 10 kHz and pulse width is 80 μs and (d) pulse 9. A MOSFET is operated such that the operating
frequency is 10 kHz and pulse width is 20 μs. point is in the active region. The MOSFET has
4. A diode and a 10 Ω resistor are connected in a gate–source threshold voltage value of 2.5 V.
series to a square wave voltage source of 50 V A gate–source voltage of 5 V is applied to the
peak. The reverse recovery time for the diode is gate–source terminals of the MOSFET which
given to be 200 ns. Find the switching loss of results in the flow of drain current. On increas-
the diode when (a) input frequency is 100 kHz ing the gate–source voltage to 7.5 V, what is the
and (b) input frequency is 50 kHz. factor by which the drain current increases?
10. A MOSFET is driving a 10 A resistive load
5. For Problem 4 above, estimate the reverse
from a 100 V DC supply. The base drive
recovery charge.
signal is switching at frequency of 100 kHz
6. A BJT is driving a 10 A resistive load from a and duty cycle of 0.6. The MOSFET has the
100 V DC supply. The base drive signal is following datasheet specifications: RDS(ON) =
switching at frequency of 50 kHz and duty 0.1 Ω, tr = 100 ns, tf = 150 ns. Calculate the
cycle of 0.75. The BJT has the following data- conduction and switching power losses in the
sheet specifications: Vbesat = 0.7 V, Vceo = 30 V, MOSFET.

| ANSWERS
Fill in the Blanks
1. anode and cathode 3. cathode; anode 5. forward-biased state
2. cathode 4. excess charge; removed 6. three-terminal

Chapter 01.indd 53 3/12/2009 3:48:01 PM

54 Power Electronics

7. current-controlled 17. increasing collector voltage; 26. less; greater

8. dual junction increasing collector-current 27. greater
9. NPN transistor and PNP density 28. less
transistor 18. current and voltage 29. BJTs; MOSFETs
10. greater 19. voltage-controlled device 30. four or more
11. alpha parameter 20. majority carriers 31. negative
12. 0.9 and 0.98 21. positive 32. bi-directional
13. I c = αF I F − I co (eVC /VT − 1) 22. lower 33. controlled; uncontrolled
14. I e = α R I R − I eo (eVe /VT − 1) 23. current 34. higher
15. b or hFE 24. voltage-controlled device 35. higher
16. collector-current density; 25. bipolar 36. rectiﬁer
applied collector-emitter
voltage

Chapter 01.indd 54 3/12/2009 3:48:01 PM

Drive Circuits

Learning Objectives
CHAPTER

2
After reading this chapter, you will be able to:
design the base drive circuits for BJTs.
design the gate drive circuits for MOSFETs and IGBTs.
learn the principles of snubber circuits for power switches.

A lmost all power applications are increasingly moving away from linear and dissipative mode of opera-
tion and towards switched-mode operation to achieve improved efficiency. The power devices now are
being used primarily as switches. To achieve proper and efficient operation of the power equipments, the
power devices should be driven in an appropriate manner that makes them behave as switches.
In Chapter 1, the operation, characteristics and models of the various power switches are discussed. Of
the power switches discussed, the bipolar junction transistors (BJTs), the metal oxide semiconductor field
effect transistors (MOSFETs) and the insulated gate bipolar transistors (IGBTs) can be switched ON and
OFF by means of a control signal. This feature of controllability has made the them increasingly popular
in power electronics systems like the DC–DC converters, AC-to-DC rectifiers with power factor ( pf )
correction, DC-to-AC inverters, DC and AC motor drives, etc. The insights gained in the previous chapter
will be used here to design the drive circuits for the controlled switches. The discussion in this chapter will
focus mainly on drive circuits for fully controlled power switches. Two of the generic power switch
drive circuits discussed in this chapter are BJTs and MOSFETs. However it should be noted that the drive
circuits for MOSFETs are directly applicable for IGBTs too. These controlled power switches account for
80–90% of the power electronic applications. In most applications MOSFETs and IGBTs are the more
popular and preferred high-power switches. Their gate drives are in general composed of stages of
BJT-based switches.

2.1 Transistor Drive Circuits

F igure 2.1 shows the typical collector–emitter voltage and collector-current waveforms for a switching
power transistor. The turn-ON and turn-OFF intervals are indicated in Figure 2.1. The switching behavior
of the transistor during these two intervals and the dependency of the turn-ON and turn-OFF behavior on
the transistor base drive are discussed in the following sections.

Chapter 02.indd 55 3/12/2009 4:02:22 PM

56 Power Electronics

Vce

Turn-ON Turn-OFF
interval interval

Figure 2.1 Typical collector-current and collector–emitter voltage waveforms of a transistor.

Turn-ON Behavior
The portion of the waveform corresponding to the turn-ON of the transistor (shown in Figure 2.1) is shown
in Figure 2.2 with an expanded timescale for various base-current waveshapes. A typical set of voltage and
current waveforms at the collector and base of a transistor during the turn-ON interval is depicted in
Figure 2.2(a). One should observe that during transistor turn-ON, a large collector-current spike, as indicated
in Figure 2.2(a), is generated. Such waveforms are found in a power-converter circuit wherein a capacitance
(parasitic or otherwise) is discharged at transistor turn-ON.
Figure 2.2(b) shows the turn-ON situation for a base-current waveshape that has a faster rate of rise. It
can be noted that here the peak and the average values of the turn-ON dissipation are smaller than that
shown in Figure 2.2(a). Figure 2.2(c) shows the effect on the transistor turn-ON for a very fast rising
base-current pulse which initially overshoots the final (steady-ON) value. The turn-ON dissipation is much
lower and narrower than the cases indicated in Figures 2.2(a) and 2.2(b). From Figure 2.2, it is evident that
for the power transistor, the turn-ON conditions are most favorable when the driving base-current pulse has
a fast leading edge and overshoots the final value or steady-ON value of the base current.

Turn-OFF Behavior
The portion of the waveform corresponding to the turn-OFF of the transistor (Figure 2.1) is shown in
Figure 2.3 with an expanded timescale. For the transistor to turn-OFF faster, it is essential that a negative
base-current drive be provided as indicated in Figure 2.3. The turn-OFF dissipation pulse is dependent on
both the transistor turn-OFF time and the collector-current waveshape during turn-OFF. One should note
that the major portion of the turn-OFF dissipation is during the fall time tf and the dissipation during the
storage time ts is negligible.

Chapter 02.indd 56 3/12/2009 4:02:23 PM

Drive Circuits 57

Vce Vce ic Vce

ic ic

ib ib ib

0
ic × Vce
ic × Vce ic × Vce

0
Turn-ON Turn-ON Turn-ON
interval interval interval

(a) (b) (c)

Figure 2.2 Expanded turn-ON interval to show the effect of base current
on the switching characteristics.

0 Vce

0
ib

ic × Vce

ts tf
Turn-OFF interval

Figure 2.3 Expanded turn-OFF interval.

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58 Power Electronics

Characteristics and Classification of the Drive Circuits

Figure 2.4 shows the base drive requirement for a power transistor switch. During the turn-ON period, the
base current should be fast rising and must overshoot the ﬁnal or steady-ON value. The maximum value of
the base current during turn-ON is denoted by ib +. During the turn-OFF period, a negative base current
(with a maximum value of ib –) should be provided to quickly remove the stored charges in the transistor as
explained in Chapter 1. During the steady-ON period, the base-current value is decided by the expected
collector current and the minimum b (hFE(sat) or hFE(min)) of the transistor. The steady-ON state base current
is denoted by ibon. During the steady-OFF period, the base-current value should be zero. Thus, a transistor
drive circuit should be designed such that the base-current waveshape (as shown in Figure 2.4) is realized.
A rule of thumb that has been found successful in most practical circuits is to take ibon = 2 × ic/hFE(sat); ib + =
1.5(i bon) and ib – = 2(ibon).
A good BJT base drive circuit must be able to:
1. supply adequate positive base current during turn-ON, that is ib +;
2. supply adequate base current to maintain the transistor in the steady-ON state, that is ibon;
3. supply negative base current for proper turn-OFF of the transistor, that is, ib –.
Moreover, depending on the nature of the application, the drive circuit should:
1. provide isolation between the control signals used for the base drive and the power signals that are being
controlled;
2. include protection against high dv/dt or surge voltage and overcurrents.
Thus, a base drive circuit can be classiﬁed as
1. drive circuit without isolation;
2. drive circuit with transformer isolation;
3. drive circuits with opto-isolation;

ib+
ib

ibon

ib−

Steady-ON
period
td + tr ts + tf

Turn-ON Turn-OFF
interval interval

Figure 2.4 Base drive requirement.

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Drive Circuits 59

4. drive circuits without negative voltage source;

5. drive circuits with negative voltage source;
6. drive circuits with various combinations of the above.
Few BJT drive circuits examples are discussed in the following sub-sections.

BJT Drive Circuit-1

This base drive circuit is shown in Figure 2.5. This is the simplest of all the base drive circuits. In fact, it is
the basic building block of many other complex base drive circuits. For low-power and low-frequency
applications, this base drive circuit is well suited. This circuit does not provide the starting surge base
current ib + during the turn-ON time. The resistor R2 provides the discharge path for removing the
base charges in the transistor Q. As a rule of thumb, it is found that ibon = 2(ic/hFE(sat)) and iR2 = ibon gives
satisfactory performance. Thus
Vbe(sat) Vbe(sat) hFE(sat)
R2 = = (2.1)
iR2 2ic

Vb − Vbe(sat) (Vb − Vbe(sat) )hFE(sat)

R1 = = (2.2)
2ibon 4ic

BJT Drive Circuit-2

This drive circuit is shown in Figure 2.6. Here, Q p is the power transistor to be controlled. Q 1 and Q 2 are
auxilliary low-power transistors. This circuit is useful when the sourcing capability of Vb is low. The two
transistor stages, Q 2 and Q 1, provide the necessary current gain to suitably drive Q p. One can notice from
Figure 2.6 that the drives for the intermediate transistors Q 1 and Q 2 are based on the basic BJT drive
circuit-1.
When Vb is positive, Q 2 turns ON. As a consequence, collector-to-emitter voltage of Q 2 is almost zero.
As R4 is now connected to a ground at one end, the emitter–base junction of the PNP transistor Q 1 is
forward-biased and therefore Q 1 turns ON. This pumps the necessary base drive current through the resistor
R1 for Q p to turn-ON. When Vb is zero, then Q 2 is OFF and the base of Q 1 is high, thus making Q 1 OFF.
This will cut oﬀ the base drive for Q p and thus switch-OFF Q p.

Vb R1 ib
Q

Figure 2.5 BJT drive circuit-1.

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60 Power Electronics

Vcc

R4
R1 ic

Vb R5 Qp
Q2

R2
R6

Figure 2.6 BJT drive circuit-2.

BJT Drive Circuit-3

The base drive circuit shown in Figure 2.7 is similar to the BJT drive circuit-2 that is shown in Figure 2.6. Here,
the turn-OFF time of the power transistor Q p is improved by using an inductor L as depicted in Figure 2.7.
When the transistor Q 1 is conducting, a current is ﬂowing through L and some energy gets stored in the
inductor. The current in the inductor is limited to ib – by the resistance R2. When Q 1 is cut oﬀ, the inductor
will not allow sudden change in its current, and therefore the voltage polarity across the inductor will

Vcc

R3
ic
Q1 R1
Qp
R4
R2

R5
Vb
Q2
L
R6

Figure 2.7 BJT drive circuit-3.

Chapter 02.indd 60 3/12/2009 4:02:23 PM

Drive Circuits 61

reverse. This makes the inductor to act as a generator which will now supply the reverse base current ib – for
fast turn-OFF of Q p. The value of L in μH is calculated using the following relationship:
( R1 + R2 ) ⋅ ib − − Vbe(sat)
L= (2.3)
dib / dt
where dib/dt is taken as a value between 0.15ic A/μs for high-voltage transistors (>700 V) to 0.5ic A/μs for
low-voltage transistors (<200 V).

BJT Drive Circuit-4

This base drive circuit is shown in Figure 2.8. This drive circuit is similar to the base drive circuit of
Figure 2.6. But in this case, the resistor R 2 is connected to a negative supply to improve the turn-OFF speed
of the power transistor Q p. The operation is exactly similar to that of the base drive circuit-2, but here during
the turn-OFF of Q p, a negative base current ib – is provided by the negative source through the resistance R 2.
The resistance R2 is decided by
Vbe(sat) + Vcc (Vbe(sat) + Vcc ) ⋅ hFE(sat)
R2 = = (2.4)
ib − 4ic
where ib – is chosen as 2 times ibon.

BJT Drive Circuit-5

This base drive circuit is shown in Figure 2.9. This drive circuit provides a fast turn-ON and turn-OFF of
Q p. This is because the circuit provides a surge base current ib + during turn-ON of Q p and also a negative
base current ib – during turn-OFF of Q p.
When Vb is zero, the PNP transistor Q 3 is ON. This makes the base node of Q 1 and Q 2 positive. This will
forward bias the base–emitter of Q 1 and reverse bias the emitter–base of Q 2. Thus, Q 1 is turned ON and Q 2

Vcc

R4
ic
R1

Vb R5
Q2 Qp

R6 R2

−Vcc

Figure 2.8 BJT drive circuit-4.

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62 Power Electronics

Vce

Q3
R2 C ic
Q1
R5
Qp
Vb R1
Q2

Figure 2.9 BJT drive circuit-5.

is turned OFF. When Q 1 is turned ON, a surge current ib + is delivered to the base of Q p through the R2–C
branch. This base surge current will induce fast turn-ON of Q p. During the time when the power transistor
Q p is fully ON, the capacitor would have charged to Vcc. When Vb is made positive, Q 3 is turned OFF and
this makes the base node of Q 1 and Q 2 zero. The emitter of Q 2 is positive because of the voltage of Vcc on C.
Thus, the emitter–base node of Q 2 is forward-biased and will turn ON Q 2. If emitter–base of Q 2 is forward-
biased, the base–emitter of Q 1 will be reverse-biased automatically. Thus, Q 1 will be turned OFF. The
capacitor C, which was charged to Vcc, will discharge through Q 2 providing the reverse base current ib –,
thus enabling fast turn-OFF of Q p.
The turn-ON base current surge ib + will ﬂow through R2–C branch. The steady-ON base current ibon of
the transistor Q p will ﬂow through R1. Thus,
Vcc − Vce(sat)(Q1) − Vbe(sat)(Qp)
R1 = (2.5)
ibon

where ibon = 2(ic/hFE(sat)); R2 is chosen as 1/5 times R1.

Now
τ ≈ R2C (2.6)
Set t equal to the turn-OFF time of Q p, that is toﬀ = ts + tf . Then,
t off
C= (2.7)
R2

BJT Drive Circuit-6

This base drive circuit is shown in Figure 2.10. This drive circuit is similar in operation to the drive circuit-5
shown in Figure 2.9. Here the R2–C branch is removed and the negative base current during turn-OFF of
Q p is provided by the negative supply as shown in Figure 2.10. In this base drive circuit, there is no turn-ON
base surge current ib +. However, the negative base current for fast turn-OFF is given by (Vcc + Vbe(sat))/R1.

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Drive Circuits 63

Vcc

Q3
ic
Q1
R4

Vb Qp
R1
Q2

−Vcc

Figure 2.10 BJT drive circuit-6.

One may recall that if a large base drive is injected, then the base charges are more and as a consequence the
turn-OFF time will be longer. If, however, the transistor is allowed to be just hovering at saturation, then the
stored base charge is small and the turn-OFF times will be very fast. But this will lead to higher ON-state Vce
of the transistor which in turn leads to larger ON-state losses. Therefore, if faster switching of the transistor is
required, the transistor should be biased such that it is just out of saturation. This is done by the use of an anti-
saturation circuit or the Baker’s clamp as shown in Figure 2.11. Referring to Figure 2.11, it is evident that
Vce = VD2 + Vbe(sat) − VD1 (2.8)
If the Baker’s clamp was not used, then on providing a base overdrive, the collector–emitter voltage will reduce
(to about 0.1–0.3 V). But by using the Baker’s clamp, when the collector–emitter voltage reduces, diode D1 con-
ducts and clamps the collector–emitter voltage to approximately Vbe(sat) value (assuming approximate cancella-
tion of drops due to D1 and D2). This means that Vce is never lower than about 0.7 V and thus the transistor Q p
is always at the edge of saturation. Therefore, the charges in the transistor will be reduced, thereby improving the
turn-OFF times. One should note that the diode D3 is used to provide a path for the reverse base current. This
anti-saturation circuit, that is, the Baker’s clamp can be used in any of the base drive circuits discussed.

D1 ic

D2
Qp

Figure 2.11 Anti-saturation circuit or Baker’s clamp.

Chapter 02.indd 63 3/12/2009 4:02:24 PM

64 Power Electronics

BJT Drive Circuit-7

This base drive circuit is shown in Figure 2.12. The base drives discussed until now are for a particular value
of collector currents. If the collector current (i.e., load) decreases, the transistor will be overdriven into
saturation for the same base drive. On the other hand, if the collector current increases, the transistor will
come out of saturation and operate in the active region. In applications where the load current can vary
within a wide range, the above problem can be overcome if the base current also varies in proportion to the
collector current. This concept is called the proportional-base drive. The base drive circuit indicated in
Figure 2.12 is a proportional-base drive circuit.
A current transformer (CT) is placed in the collector as shown in Figure 2.12. A short-duration positive
pulse (which is generally obtained by passing the base drive pulse through an R–C differentiator network) is
applied to the base of Q p. The energy in the base drive pulse is just sufficient to turn-ON the transistor Q p.
As a result, the collector current increases. Owing to transformer action, the collector current gets reflected
into the secondary of the CT and a current in2 will flow through the base of Q p. This increased drive will
further turn ON Q p which will, in turn, increase ic. In this manner, the transistor will go into saturation by
re-generative action. The turns ratio for the CT is chosen in the following manner:

ib 1 i n
= = n2 = 1 (2.9)
ic hFE(min) ic n2

One can note from Eq. (2.9) that the base current to the transistor Q p varies in proportion to the load
current, that is, the collector current. Therefore, the turn-ON and turn-OFF speeds will be fast at all loads.
To turn OFF the transistor, a negative pulse is applied as shown in Figure 2.12. This will bring the transistor
out of saturation and will cause the collector current to decrease. This will lead to re-generative turn-OFF of
the transistor. The transistor Q 1 is provided to demagnetize the core of the CT. During the time when Q p is
OFF, Q 1 is turned ON. This causes a current to ﬂow through the winding n3 in a direction which will re-set
the core of the CT. The design of the CT is discussed in Chapter 7.

Vcc
R1

n3
Q1 n1
n2
ic

Vb
Qp

Figure 2.12 BJT drive circuit-7.

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Drive Circuits 65

BJT Drive Circuit-8

Until now, all the base drive circuits considered had no isolation between the base or control portion of the
circuitry and the load or the power portion of the circuitry. However, in many situations isolation between
the high-power side and the low-power base side of the circuit is essential. In such cases, the base drive
circuits will have to be designed taking isolation into account. Generally, isolation can be provided either by
using opto-couplers or by using transformers. The base drive circuit shown in Figure 2.13 is one such
isolated drive circuit which uses an opto-coupler to provide the isolation between the base side and the
high-power collector side circuits.
One can note that the base drive circuit portion in Figure 2.13 after the opto-isolation is exactly similar
to the base drive circuit-5 shown in Figure 2.9. Therefore, the turn-ON and turn-OFF operations of the
power transistor Q p are similar. A positive base drive pulse Vb causes a current to flow through the photodiode
of the opto-coupler. This causes the transistor Q 4 of the opto-coupler to turn ON. As a consequence, Q 3 is
OFF and Q 1 is ON as discussed for the base drive circuit-5 of Figure 2.9. Likewise, when Vb is zero, no current
flows through the photodiode and Q 4 is OFF. This causes Q 3 to turn ON. As a consequence, the power
transistor Q p turns OFF with reverse base current flowing through Q 2. One should note that the choice of
the opto-coupler depends on the current transfer ratio of the opto-coupler, the propagation delay for turn-
ON and turn-OFF and the breakdown voltage between the opto-coupler diode and transistor terminals.

BJT Drive Circuit-9

This is a transformer-isolated base drive circuit and is shown in Figure 2.14. When a positive voltage Vb is
applied to Q 1, the transistor Q 1 will turn ON and the full voltage of Vcc is applied across the primary of the
transformer. The transformer is a pulse transformer designed for the specific frequency and it passes the
primary pulse to the secondary which turns ON Q p. When the transistor Q 1 is turned OFF, the current in
the primary will be suddenly cut off and will give rise to a large voltage (of Ldi/dt) across the primary. This
will also appear across Q 1 (by Kirchhoff’s voltage law) and will damage the transistor. Therefore, to prevent
the abrupt cut off of the primary current when Q 1 turns OFF, a freewheeling path through Df and R3 is
provided. (The design of the transformer is discussed in Chapter 7.)
The ratio of the time for which the power transistor Q p is ON to the switching time period is called the
duty cycle or the duty ratio, D. The base drive circuits 1–8 discussed until now can be used for duty cycle range

Vcc

R4
R7
ic
R8 Q1 R2 C
Vb R5
Q3
Qp
R1
R6
Q4 Q2

Figure 2.13 BJT drive circuit-8.

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66 Power Electronics

Vcc ic
D1
Qp
R1
Df
R2
R3

Vb R4
Q1

Figure 2.14 BJT drive circuit-9.

from 0 to 1. But in this case, the duty cycle is limited because the transistor has to be OFF for the period of time
when the core is being re-set by freewheeling action. If the value of R3 is large, then the core re-setting is faster
and therefore the range of duty cycle is larger as Q p needs to be compulsorily OFF only for a smaller time. How-
ever, in such a case, as the drop across R3 is higher, the Vceo rating of Q 1 is higher which is evident from
Vceo(Q1) > Vcc + I mag R3 + VDf (2.10)
where Imag is the magnetizing current in the primary at the instant when Q 1 is being turned OFF. Therefore,
to have a reasonable Vceo rating for Q 1, the value of R3 cannot be chosen too large. In practice, the duty ratio
is limited to less than 0.5 (50%).

BJT Drive Circuit-10

This base drive circuit is shown in Figure 2.15. This is exactly similar to the base drive circuit of Figure 2.14.
The only diﬀerence lies in the freewheeling circuitry. In Figure 2.14, the freewheeling path contained

Vcc
ic
D1
n2
Qp
R1
n1 n3 R2

Vb R3
Df
Q1

Figure 2.15 BJT drive circuit-10.

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Drive Circuits 67

Vcc R2 C ic
D1 D2
Qp
R1
Df
Q1

R4 R3

Vb R5
Q2

Figure 2.16 BJT drive circuit-11.

a resistor R3 which leads to dissipation. In Figure 2.15, the dissipation is avoided during freewheeling. When
Q 1 turns OFF, the dot poles of the transformer become negative with respect to the other pole. This causes
Df to be forward baised. Df conducts and freewheels the magnetic energy stored in the core. This causes the
required core re-setting which prevents core saturation. As winding n2 is used for demagnetizing the core,
this winding is also called the demagnetizing winding. In practice, to achieve a very tight coupling (i.e., low
leakage) between n1 and n2, these two windings are wound biﬁlar. Therefore, the turns ratio n1:n2::1:1 is
maintained. As a consequence, a time equal to the ON time of Q 1 is required for the core to re-set. Therefore,
the duty cycle in this case cannot exceed 0.5 (or 50%).

BJT Drive Circuit-11

This is a transformer-isolated base drive circuit as shown in Figure 2.16. This circuit is similar to the transformer-
isolated base drive circuits of Figures 2.14 and 2.15. But here, the turn-OFF time of Q p is improved by using
an active turn-OFF circuit with the help of a PNP transistor Q 1.
When Vb is positive, the transformer secondary is positive at the dot pole. This will forward bias the
diodes D1 and D2. The drop across D2 will ensure that the emitter–base junction of Q 1 is reverse-biased. Thus,
Q 1 is in the turned-OFF condition. The R2–C will provide a low-impedance path during pulse transitions
which will provide the needed surge base current for fast turn-ON, that is ib +. When Q p is to be turned OFF,
Vb is made zero. Then, D1 will be reverse-biased and the base of Q 1 is pulled low. Owing to the presence of
the capacitor C, the emitter of Q 1 will now be positive which ensures that the emitter–base junction of Q 1 is
forward-biased. This causes Q 1 to turn ON, thereby providing the necessary reverse base current for fast
turn-OFF of Q p. One should note that here also the duty cycle is limited to 0.5.

BJT Drive Circuit-12

This base drive circuit is shown in Figure 2.17. This is an isolated proportional-base drive circuit. As discussed
in the case of the non-isolated proportional-base drive circuit of Figure 2.12, there is a CT (nc – nb windings)
which provides the necessary base current to maintain the power transistor Q p in the ON-state. A ﬂyback
tranformer with air gap (np – nb windings) is used to supply the required turn-ON and turn-OFF pulses to
start the turn-ON and turn-OFF re-generative processes, respectively, for Q p.

Chapter 02.indd 67 3/12/2009 4:02:25 PM

68 Power Electronics

Vcc

ic
R1

C
np nb

Vb R2
Q1

Figure 2.17 BJT drive circuit-12.

The operation of the base drive circuit of Figure 2.17 is similar to the non-isolated proportional-base drive
circuit. Consider the situation where Q p is in the ON condition. During this time, Q 1 is OFF. The capacitor
C charges to Vcc through R1 with a time constant of R1C. Now, when Q 1 is turned ON, the secondary voltage
will be the same as the base–emitter voltage of Q p which is around 0.7 V because as yet Q p is not turned OFF
due to the presence of stored charges in it. Therefore, the primary of the transformer will experience a virtual
short circuit. A large current will be discharged from C. This will be reﬂected at the secondary as a large
negative base current which will quickly and re-generatively turn OFF Q p.
During the time when Q p is OFF and Q 1 is ON, the primary current will rise and saturate the core. The
resistance R1 will limit the current through Q 1. The dot poles of the transformer are positive and therefore
Q p is maintained in the OFF-state. Now, if Q 1 is turned OFF, the voltage polarities across the windings
reverse due to inductance action and the stored energy in the core (air gap) will freewheel through the base
of Q p. This will provide the turn-ON energy to start the re-generative process for turn-ON of Q p.
The choice of nc:nb will depend on the hFE(min) of the power transistor Q p. Thus

nb ic
= = hFE(min) (2.11)
nc ib
The choice of np:nb will depend on the base–emitter breakdown voltage of Q p. This is because, when Q p is
OFF, the secondary voltage should not exceed the base–emitter breakdown voltage BVebo of Q p. Thus,

np Vcc
= (2.12)
nb BVebo

Chapter 02.indd 68 3/12/2009 4:02:25 PM

Drive Circuits 69

When Q 1 is ON, the current through the primary increases till it saturates the core. This saturation current
ipon, which is limited by R1, should provide the necessary turn-ON base drive current ib + for Q p. Thus,

⎛n ⎞
ipon = ib+ ⎜ b ⎟ (2.13)
⎝ np ⎠

Vcc
R1 = (2.14)
ipon

When Q 1 is turned ON in order to turn OFF Q p, the primary current ipoﬀ , consists mainly of the reﬂected
collector current of Q p and the reverse base drive current ib – of Q p. Thus,

⎛n ⎞ ⎛n ⎞
ipoff = ic ⎜ c ⎟ + ib − ⎜ b ⎟ (2.15)
⎝ np ⎠ ⎝ np ⎠

This current of ipoﬀ has to be supplied by the capacitor when Q 1 is turned ON. Thus, the capacitor should
have energy of at least
1
E c = CVcc2 = Vcc ⋅ ipoff ⋅ t off (2.16)
2

where toﬀ is the turn-OFF time of Q p which is equal to (ts + tf ) of Q p. From Eq. (2.16), the value of
capacitor C is given by

2 ⋅ ipoff ⋅ t off
C= (2.17)
Vcc

One should note that when Q p is ON, the capacitor should charge to Vcc during this time. The charging
time constant is R1C. The capacitor will charge fully to Vcc in 5 R1C. This means that Q p should be on for at
least 5 R1C. Therefore, there is a minimum duty cycle limitation in this circuit. Thus, the duty cycle ranges
from 5R1C/Ts to almost 1, where Ts is the switching period.

BJT Drive Circuit-13

This drive circuit is shown in Figure 2.18. This is almost identical to that shown in Figure 2.17. The only dif-
ference is that the charging time constant of C is made faster here by using a transistor Q 2. It can be shown
that the capacitor charging time constant is given by

R1C
τ= (2.18)
hFE(Q2)

It is evident from Eq. (2.18) that the charging time constant is signiﬁcantly reduced if Q 2 is a high hFE
transistor. The hFE of Q 2 is generally chosen such that t is half of the turn-ON time of Q p that is (tr + td).
With this circuit, the duty cycle range is increased from almost 0 to almost 1.

Chapter 02.indd 69 3/12/2009 4:02:25 PM

70 Power Electronics

Vcc

R1 ic

Q2
Qp

D np nb
C

Vb R2
Q1

Figure 2.18 BJT drive circuit-13.

2.2 MOSFET Drive Circuits

T he MOSFETs are voltage-controlled devices. As a consequence, the gate currents are not dependent on
the drain currents. The gate power required to maintain the MOSFETs in the ON condition is negligible.
This section discusses primarily the MOSFET drive circuits; however, as discussed in Chapter 1, the gate
portion of the IGBTs being functionally similar to the MOSFETs, these drive circuits that will be discussed
can also be applied for driving IGBTs.
Figure 2.19 shows the gate drive requirements for a MOSFET. It can be observed from the gate drive
requirements that the gate current required to maintain the MOSFET in the steady-ON condition is zero.
Therefore, the gate power required to maintain the MOSFET in the steady-ON condition is low. The gate
circuit energy is used only to turn-ON and turn-OFF the MOSFET. During turn-ON, a peak current of ig +
is applied which is used to turn-ON the MOSFET. During turn-OFF, a negative peak current of ig– is
provided for fast turn-OFF of the MOSFET.
During the turn-ON period (ton), it can be assumed that an equivalent constant current of igon is being
applied to the gate of the MOSFET. One can approximate the turn-ON surge current to be a right-angled
triangle with the peak of ig +. Thus
ig+
igon = (2.19)
2
The turn-ON and turn-OFF operation of the MOSFET is as explained in Chapter 1. To turn-ON a
MOSFET, a speciﬁc amount of gate charge Q G has to be supplied to the gate of the MOSFET. This amount
of Q G for a speciﬁc MOSFET is given in the manufacturers’ datasheets. Thus

Chapter 02.indd 70 3/12/2009 4:02:25 PM

Drive Circuits 71

ig+
ig

igon

ig−

Steady-ON
period
ton toff

Turn-ON Turn-OFF
interval interval

Figure 2.19 Gate drive requirement for MOSFETs.

Q G = igon t on (2.20)
It is evident from Eq. (2.20) that if one requires to turn-ON the MOSFET faster (i.e., smaller ton), the igon
required should be more. If the MOSFET can be switched slower, then a smaller igon would suﬃce. Consider
a MOSFET where 250 nC of charge is required to turn-ON the MOSFET. For a speciﬁc application, if it
is required that the MOSFET should be turned-ON in 1 μs, then the igon required would be 250 mA and ig +
required would be 500 mA. If on the other hand, the required turn-ON time is 2 μs, then igon required
would be 125 mA and ig + required would be 250 mA.
To allow a turn-ON gate drive surge current of ig +, only a limiting resistor R1 can be connected in series
with the gate of the MOSFET such that
Vcc
R1 = (2.21)
ig+
where Vcc is the gate drive supply voltage.
MOSFETs generally require a gate voltage of 15 V. Therefore, Vcc = 15 V in most cases. Various
MOSFET gate drive circuits will be now discussed in the following sections.

MOSFET Drive Circuit-1

The MOSFET drive circuit shown in Figure 2.20 is the simplest MOSFET drive circuit. The resistor R1
is used for limiting the turn-ON surge current and it is chosen based on Eq. (2.21). If the source Vg does
not have current-sinking capability, a resistor R2 is connected as shown and is used to provide a discharge
path for the input capacitance during turn-OFF of the MOSFET. R2 is usually chosen 10 times the value
of R1.
If the gate drive source Vg is capable of sinking current, then R2 need not be used. In such a case, as the
output resistance of the source Vg is low, the input capacitance will charge and discharge through R1.

Chapter 02.indd 71 3/12/2009 4:02:26 PM

72 Power Electronics

Q
Vg R1

Figure 2.20 MOSFET drive circuit-1.

MOSFET Drive Circuit-2

MOSFETs can be driven directly from a complementary metal oxide semiconductor (CMOS) logic integrated
circuit (IC) as shown in Figure 2.21. For faster switching, igon should be increased. This is achieved by parallel-
ing buffers as indicated in Figure 2.21. Either the CMOS hex inverting buffer IC or non-inverting hex buffer
IC can be used to drive the MOSFETs. The input gate pulse signal source, Vg should have a polarity that
should be appropriate with respect to the type of buffer chosen, whether inverting or non-inverting. It should
be noted that here also as in all the MOSFET gate drive circuits that are discussed, the series resistor R1, which
is used to limit the turn-ON gate surge current, is selected based on Eq. (2.21).

Q
Vg R1

Figure 2.21 MOSFET drive circuit-2.

Chapter 02.indd 72 3/12/2009 4:02:26 PM

Drive Circuits 73

Vcc

id
Q3
Q1
Qp
R4 R1

Vg
Q2

Figure 2.22 MOSFET drive circuit-3.

MOSFET Drive Circuit-3

The MOSFET drive can be made faster by using transistors to increase the turn-ON gate drive current, igon.
The MOSFET drive circuit shown in Figure 2.22 is similar in topology and operation to the BJT drive circuit
shown in Figure 2.10. The only diﬀerence is that the negative power supply is not used here. In Figure 2.10,
the negative power supply was used to provide the forward bias for Q 2 while turning OFF Q p. Here, the
input capacitance of the MOSFET provides the necessary forward bias to turn ON the PNP transistor Q 2
when Q 1 is turned OFF in order to switch-OFF the MOSFET Q p. This would imply that a negative power
supply is not needed.
However, if a lower voltage negative power supply Vss (~–5V) is used wherein the emitter of Q 2 is con-
nected to the negative pole of the Vss, then Q 2 would be ON even when the gate–source MOSFET capacitor
is fully discharged. This would ensure that the gate–source is connected by R1 which is almost like a short as R1
is a small resistance value. This would also ensure greater reliability in the sense that no spurious dv/dt on the
high-power drain side circuit will charge up the gate–source capacitance through the drain–gate capacitance
due to the fact that the gate is connected to source through R1 and Q 2.

MOSFET Drive Circuit-4

Some circuits demand that the gate and source terminals of MOSFETs are ﬂoating with respect to those of
other MOSFETs in the circuit. This is typical of bridge topologies wherein the top MOSFET and the bottom
MOSFET need diﬀerent drive grounds. Isolated drive to these MOSFETs can be provided either by using
opto-isolators or by using pulse transformers. Figure 2.23 shows a gate drive circuit using an opto-isolator.
This circuit is similar in topology and operation to the BJT opto-isolated circuit shown in Figure 2.13. One
should note that for all opto-isolated drive circuits whether BJT or MOSFET drive circuits, the secondary-side
circuitry (transistor side) should have a local power supply which is isolated from the primary-side circuitry
(diode side).
When Vg is positive, the diode in the primary side of the opto-isolator emits photons. These photons
impinge on the base region of the transistor in the secondary side. This causes photogeneration of carriers

Chapter 02.indd 73 3/12/2009 4:02:26 PM

74 Power Electronics

Vcc

R4
R7 ic

Vg R8 R5 Q1 Qp
Q3 R1

R6
Q4 Q2

Figure 2.23 MOSFET drive circuit-4.

suﬃcient to satisfy the base requirement for turn-ON of Q 4. When Q 4 turns ON, Q 3 is turned OFF. This
causes Q 1 to turn ON which supplies the required gate current to the MOSFET through R1 and turns ON
the MOSFET Q p.

MOSFET Drive Circuit-5

The gate drive circuit shown in Figure 2.24 is another opto-isolated circuit. Here, the complementary pair
Q 1 and Q 2 shown in Figure 2.23 is replaced by CMOS buﬀer ICs either inverting or non-inverting type as
required by the polarity of Vg.

Vcc

R2 Qp
R5
R1
Vg R6 R3
Q1

R4
Q2

Figure 2.24 MOSFET drive circuit-5.

Chapter 02.indd 74 3/12/2009 4:02:26 PM

Drive Circuits 75

Vcc = 15 V

Vdclink = 300 V
D
R4 id
C
R2
Q1 Qp1
R1

R3
Q2

Vg R5
Q3 gnda

R6 Qp2

gndb

Figure 2.25 MOSFET drive circuit-6.

MOSFET Drive Circuit-6

In most inverter and converter applications, the power converter is generally a half-bridge or a full-bridge conﬁg-
uration. The top MOSFET and the bottom MOSFET are switched at mutual exclusive time intervals to prevent
shorting the DC link or bus. In either case, the gate drive for the high-side MOSFET is generally isolated from
the low-side MOSFET by the use of opto-isolators or pulse transformers. Figure 2.25 gives a circuit wherein the
high-side and the low-side MOSFETs can be driven without the use of opto- or transformer isolation.
When Vg is zero, both Q 3 and Q 1 are OFF. Therefore, the MOSFET Q p1 is also in the OFF-state. But
during this period, the bottom MOSFET Q p2 is ON. The capacitor C will get charged to Vcc through the
diode D and the bottom ON MOSFET Q p2. When Q p2 is turned OFF and Vg is positive, Q 3 is ON, which
in turn switches Q 1 ON. The capacitor C now discharges through Q 1 into the input capacitance of the
MOSFET Q p1 thereby turning ON Q p1. When Vg is made zero again, Q 1 is turned OFF and Q 2 is turned
ON. The input capacitor of the MOSFET discharges through R1 and Q 2, thereby turning Q p1 OFF.
As the capacitor C needs to charge to Vcc during the time when Q p2 is ON, there is a minimum ON-time
limitation on Q p2. It should also be noted that when Q p1 is ON and Q p2 is OFF, the Q p1 drive capacitor’s nega-
tive pole which is connected to the source of Q p1 is at the DC-link voltage. At this time the diode D will have a
reverse voltage of (Vcc – VC – Vdclink ) and therefore should be rated to withstand the full DC-link voltage.

MOSFET Drive Circuit-7

A transformer-isolated gate drive circuit is shown in Figure 2.26. One can note that this gate drive circuit is
exactly similar both in topology and operation to the BJT transformer-isolated base drive circuit shown in
Figure 2.14. The operation of the pulse transformer and the freewheeling circuit is similar to that discussed
for the transformer-isolated BJT base drive circuit. Here again, one can use a demagnetizing winding to perform
non-dissipative freewheeling as indicated in Figure 2.15 for the BJT base drive.

Chapter 02.indd 75 3/12/2009 4:02:26 PM

76 Power Electronics

Vcc Qp
D1

Df R1

R2
R3

Vg R4
Q1

Figure 2.26 MOSFET drive circuit-7.

Qp
D1 D2 R1
Vcc

R3 Q1
R4

Vg R5
Q2

Figure 2.27 MOSFET drive circuit-8.

For the MOSFET gate drive circuits discussed till now, the upper limit on the duty cycle is 1 (i.e., 100%).
But in the case of this drive circuit, the upper limit on the duty cycle is 0.5, that is, 50% only.

MOSFET Drive Circuit-8

Another transformer-isolated gate drive circuit is shown in Figure 2.27. Here, the turn-OFF is due to active
pull down by the PNP transistor Q 1. This will, therefore, provide a faster turn-OFF of the MOSFET than

Chapter 02.indd 76 3/12/2009 4:02:27 PM

Drive Circuits 77

that provided by the gate drive circuit shown in Figure 2.26. When Vg is positive, Q 2 is turned ON. This
causes the dot poles of the pulse transformer to be positive with respect to the other poles. D1 and D2 will be
forward-biased and charge the input capacitor of the MOSFET and turn-ON Q p. During this time, as D2
is ON, the emitter–base junction of Q 1 is reverse-biased and therefore Q 1 is OFF. When Vg is made zero, Q 2
turns OFF. This causes the dot poles of the pulse transformer to become negative with respect to the other
poles. This will reverse bias D1 and D2, thereby switching OFF these diodes. As a consequence, the base of
Q 1 is pulled low through R3. The charge on the input capacitance of the MOSFET will make the emitter of
Q 1 positive with respect to the base and will therefore forward bias the emitter–base junction of Q 1 and turn
it ON. The input capacitance will then discharge through Q 1, thereby turning Q p OFF. One should note
that here also the upper limit for the duty cycle is 0.5, that is, 50%.

MOSFET Drive Circuit-9

To obtain the full duty cycle range of 0 to 1 using transformer isolation, one can use the transformer-
isolated gate drive circuit shown in Figure 2.28. Here, two pulse transformers are used and they are

Vcc Qp
D1 R1

Df
R2
R3
T1

R6
Q1

HF Carrier
osci.
Vcc
Carrier D2 R4
Vg gating
circuit
Df1

R5
T2

R8
Q2

Figure 2.28 MOSFET drive circuit-9.

Chapter 02.indd 77 3/12/2009 4:02:27 PM

78 Power Electronics

switched with 180° phase diﬀerence. The secondaries of the transformers are diode ORed to obtain the
desired gate pulse.
The gate drive pulse Vg is gated with a high-frequency carrier as indicated in Figure 2.28. Two switching
patterns are generated to switch the two pulse transformers. One signal is obtained by directly gating the
gate drive pulse Vg with the high-frequency carrier. The other signal is obtained by gating the gate drive
pulse Vg with the inverted high-frequency carrier. These two signals are used to switch the two pulse trans-
formers whose secondaries are diode ORed. In this manner, whatever be the duty cycle of the gate drive
waveform Vg, the transformers are always switching at 50% duty cycle thereby avoiding transformer core
saturation. In this manner, the duty cycle range of the MOSFET can be extended to 100%. One should
note that, in this case, the series resistor for the MOSFET is now connected in series with each transformer
before the ORing node. This is used to avoid any large circulating currents that may occur during turn-OFF
of one pulse transformer and turn-ON of the other pulse transformer.

MOSFET Drive Circuit-10

A relatively simple transformer-isolated gate drive circuit with large duty cycle range capability (of 0 to
almost 100%) is shown in Figure 2.29. Here, when Q 2 is switched ON, the dot poles are positive with
respect to the other poles. This will charge the input capacitance of Q p through the body diode of the
MOSFET Q 1. When Q 2 is switched OFF, the dot poles become negative with respect to the other poles
and will switch ON Q 1. The input capacitance of the MOSFET Q p will discharge through Q 1 and thereby
turn-OFF Q p.
One should note that as MOSFETs do not need any gate current to maintain it in the ON-state, the
pulse transformer should be designed to transfer energy just suﬃcient to turn-ON Q p when Q p is required
to be turned ON and energy just suﬃcient to turn-ON Q 1 when Q p is required to be turned OFF. As a
consequence, the pulse transformer size will be small. The resistor R2 is used to limit the primary current of
the transformer when the transformer goes into saturation. However, one should note that in this circuit,

Vcc
id

Qp
R2 Q1

Vg R3
Q2

Figure 2.29 MOSFET drive circuit-10.

Chapter 02.indd 78 3/12/2009 4:02:27 PM

Drive Circuits 79

when Q p is OFF, the gate of Q p is ﬂoating. This will leave the MOSFET open to Miller turn-ON. Any large
dv/dt spikes on the drain side can easily charge up the gate–source capacitance through the drain–gate
capacitance and turn-ON Q p at an undesirable time.

MOSFET Drive Circuit-11

This gate drive circuit, which is shown in Figure 2.30, provides inherent protection against overcurrents
through the drain of the MOSFET. The protection circuit discussed here can be used with any of the gate
drive circuits discussed till now. Here, a transistor Q 2 is used as a series-pass element which is normally ON.
When Q 2 is ON, the gate drive circuit will operate in the normal manner. If a large drain current ﬂows
through the MOSFET when it is ON, then the series-pass transistor Q 2 is immediately cut oﬀ, thereby turning
OFF the MOSFET.
When Q p is ON, the voltage across it is the ON-state drop which is idRDS(ON). When the drain current
increases beyond a certain limit, the ON-state voltage will increase such that the “+” input of the comparator
A1 will be greater than the “−” input of the comparator. This will cause the output of A1 to go high. This will
enable the AND gate G3 which will switch-OFF the PNP series-pass transistor Q 2 (output of G2 is high at
this time). The threshold limit for the ON-state voltage can be set by adjusting the reference voltage to
the “−” input pin of the comparator. During the turn-ON process, when Q p is to be turned ON, the voltage
across Q p will be high. This will cause the comparator output to be high which will, in turn, cause Q 2 to
be OFF. Therefore, any gate drive pulse will not be passed on to the gate of Q p to turn it ON. To circumvent
this starting problem, a small delay of 1–5 μs is provided at turn-ON during which time the gate G3 is forcibly

Vcc

G2 +
G1
R6 A1
D2
−
C G3

R4
R3
id
Vref Qp
Vg Q2
D1

Q1
R2

Figure 2.30 MOSFET drive circuit-11.

Chapter 02.indd 79 3/12/2009 4:02:27 PM

80 Power Electronics

disabled by the delay circuit of G1 and G2 such that Q 2 is ON till the MOSFET Q p turns ON. After the
initial period of 1–5 μs, G2 will go high and enable G3. But now A1 output will be low as Q p is now fully
ON. A1 will now go high only when overcurrents occur which turns OFF Q 2. This in turn will turn OFF
Q p. The gates G1, G2 and G3 should be Schmitt gates in order to avoid meta-stability problems.

2.3 Snubber Circuits

I n most power semiconductor devices, there is a danger of exceeding the voltage and the current ratings of
the devices during the turn-OFF and turn-ON instants, respectively. As was discussed earlier in Chapter 1,
when the BJT is being turned OFF, the voltage across the device Vce is determined by the external cir-
cuitry. If there is an inductive load in the collector or if there is significant amount of lead inductance associ-
ated with the collector or emitter leads, then when the BJT is being turned OFF, the current through the
device will fall rapidly to zero in a time corresponding to the fall time of the device. As a consequence,
a large voltage spike due to Ldi/dt will occur across the device and cause the Vce of the BJT to have a large spike
during the fall time. This may damage the device. Therefore, it becomes essential to limit the voltage spike across
the device during turn-OFF such that the voltage is within the Vceo rating of the device. Similar argument
applies to MOSFET and IGBT switches too. In general, during turn-OFF, the power switch should be
protected against overvoltage stress. The turn-OFF voltage stresses are reduced by using circuits called the
turn-OFF snubber circuits.
On the other hand, during turn-ON of the device, due to the presence of any capacitive load or parasitic
capacitance across the switch, there will be a huge surge current through the device which could damage
the device. Therefore, it is essential to limit the current spike through the device during turn-ON such that the
device current is within the peak rating of the device. The turn-ON current stresses are reduced by using
circuits called the turn-ON snubber circuits.
The snubber circuits, in general, modify the device switching characteristics and in doing so, reduce the
device transient stress. In fact, the transient voltage and current stress during turn-OFF and turn-ON,
respectively, are transferred to the snubber circuits. The snubber circuit action involves temporary energy
storage in either an inductor or a capacitor. In re-setting these passive components, it is usual to dissipate the
stored energy in a resistor as heat. As a consequence, the circuits with snubbers will be less efficient. At high
frequencies, these losses may become a limiting factor because of the difficulties associated with equipment
cooling. Instead of dissipating the snubber energy stored in the inductance and capacitance, alternately one
may recover the energy either back into the supply or into the load. There are both passive and active circuits,
available in the literature, which perform this energy recovery from the snubber. However, here the basic
concepts of the snubber action will be illustrated with the generic turn-OFF and turn-ON dissipative snubber
circuits. The discussion of the snubber circuits which will follow can be equally applied to BJTs, MOSFETs
and IGBTs.

Turn-OFF Snubber or Shunt Snubber

Consider a power semiconductor switch Q which could be a BJT or a MOSFET or an IGBT as shown in
Figure 2.31(a). Let the load be an inductive load. When the device Q is turned OFF, the load current iL will
fall to zero in a period of time corresponding to the fall time tf . This will cause the voltage across the transis-
tor Vce to shoot up to a large value due to the Ldi/dt phenomenon where L could be the lead inductances
associated with the collector and emitter leads. Therefore, it is required to limit the voltage across the collector–
emitter of the transistor and it should be made to rise gradually during the period tf as indicated in
Figure 2.31(c). To slow down the change in the voltage across the device, one can connect a capacitor C

Chapter 02.indd 80 3/12/2009 4:02:27 PM

Drive Circuits 81

iL iL
iL D ic

icap icap
Q
ic Vce Vcc
C Q ic R C

(a) (b) (c)

Figure 2.31 Turn-OFF or shunt snubber.

across the device as indicated in Figure 2.31(a). As the capacitor C is connected in shunt with the device,
this type of snubber is also called the shunt snubber.
Without loss of generality, one can assume that the load current is falling linearly as shown in Figure 2.31(c)
during the fall time and the collector–emitter voltage across the device is rising linearly as shown in
Figure 2.31(c) during the fall time when the shunt snubber is used. Referring to Figure 2.31(a),
iL = ic + icap (2.22)
where ic is the current through the device and icap is the current through the capacitor. During the fall time
period of tf , the current ic through the device is given by
⎛ t⎞
ic = iL ⎜ 1 − ⎟ (2.23)
⎝ tf ⎠
From Eqs. (2.22) and (2.23), the current through the capacitance is given by
⎛ t⎞ ⎛t⎞
icap = iL − iL ⎜ 1 − ⎟ = iL ⎜ ⎟ (2.24)
⎝ tf ⎠ ⎝ tf ⎠
The voltage vce across the device is the same as the voltage across the capacitor C. Therefore,
1
v ce =i dt (2.25)
C cap
Use Eq. (2.24) in Eq. (2.25) and integrate within the fall time period. Then, apply the boundary condition
that at the end of the fall time period, the voltage across the device or the capacitor should be Vcc, that is, the
supply voltage. The capacitor value C is then given by
iLt f
C= (2.26)
2Vcc
One should note that though the circuit in Figure 2.31(a) will solve the problem of voltage spike during
turn-OFF process of the device, it will create a serious problem during the turn-ON of the device Q. When
the device Q is turned ON again, the capacitor will discharge through Q and will result in a large current

Chapter 02.indd 81 3/12/2009 4:02:27 PM

82 Power Electronics

spike through the device which can damage the device. Therefore, to limit current through the device,
a resistor R is introduced in series with C. The resistor R should provide the function of current limiting only
during turn-ON of the device. However, during turn-OFF of the device, R is not needed. Therefore, to
reduce the dissipation in R during turn-OFF, a diode is placed across R as shown in Figure 2.31(b) so that R
comes into eﬀect only during turn-ON when C discharges through R and the device.

Selection of R
When Q is turned ON, it should carry the following currents: The capacitive current discharge from C
which is equal to Vcc/R and the load current iL. Therefore,

Vcc
+ iL < I cm (2.27)
R
where Icm is the maximum collector-current rating of the transistor.
Re-arranging the inequality in Eq. (2.27), the following inequality is obtained:

Vcc
R> (2.28)
I cm − iL

It is also important to ensure that the capacitor discharges fully before the next charging when the transistor
turns OFF. Therefore, there is a minimum duration of time during which time the transistor should remain
ON so that the capacitor can fully discharge. The discharge time constant of the capacitor is RC. In ﬁve
times this time constant, the capacitor will be almost fully discharged. Therefore

Ton-min > 5RC (2.29)

where Ton-min is the minimum time for which the device Q should remain in the ON-state.
Re-arranging inequality (2.29), the following inequality is obtained:

Ton-min
R< (2.30)
5C
From inequalities in Eqs. (2.28) and (2.30), the range for choice of R is given by

Vcc T
< R < on-min (2.31)
I cm − iL 5C

One should note that when C is being charged, an energy of CVcc2 /2 is dissipated in R and when C is being
discharged, an energy of another CVcc2 /2 is dissipated in R. Therefore, in all, an energy of CVcc2 is dissipated
in R. As the function of R is to limit the current through the device Q during turn-ON only it is bypassed
using a diode D as shown in Figure 2.31(b). In this case, power is dissipated in R only during capacitor
discharge time. The power dissipated in R is now given by

1
PR = CVcc2 f s (2.32)
2
where fs is the switching frequency of the device Q.

Chapter 02.indd 82 3/12/2009 4:02:28 PM

Drive Circuits 83

Vcc

Vce Vcc
D
VL
L
R

ic iL

Q Vce

(a) (b)

Figure 2.32 Turn-ON or series snubber.

Turn-ON Snubber or Series Snubber

The turn-ON snubber is the dual of the turn-OFF snubber. Consider a power semiconductor switch Q
which could be a BJT or a MOSFET or an IGBT as shown in Figure 2.32(a). Let the load be a capacitive
load. When the device Q is turned ON, the voltage across the device (Vce) will fall to zero in a period of time
corresponding to the rise time tr. This will cause the current through the transistor ic to shoot up to a large
value due to the C(dVcc/dt) phenomenon (capacitive discharge) where C could be the load capacitance or
any parasitic capacitance between the collector and emitter leads. Therefore, it is required to limit the current
through the transistor and it should be made to rise gradually during the period tr as indicated in Figure 2.32(b).
To slow down the change in the current through the device, one can connect an inductor L in series with the
device as indicated in Figure 2.32(a). As the inductor L is connected in series with the device, this type of
snubber is also called the series snubber. This snubber is an exact dual of the shunt snubber. Referring to
Figure 2.32(a), diode D and resistor R provide the freewheeling path for the inductance when the transistor
Q is turned OFF, so that voltage spike during turn-OFF process is limited.
Without loss of generality, one can assume that the voltage across the collector–emitter of the device
Q is falling linearly as shown in Figure 2.32(b) during the rise time and the current through the device is
rising linearly as shown in Figure 2.32(b) during the rise time when the series snubber circuit is used. Referring
to Figure 2.32(a),
Vcc = Vce + VL (2.33)

where Vce is the voltage across the device and VL is the voltage across the inductor. During the rise time
period of tr , the voltage Vce across the device is given by

⎛ t⎞
Vce = Vcc ⎜ 1 − ⎟ (2.34)
⎝ tr ⎠

Chapter 02.indd 83 3/12/2009 4:02:28 PM

84 Power Electronics

From Eqs. (2.33) and (2.34), the voltage across the inductor is given by

⎛t⎞
VL = Vcc ⎜ ⎟ (2.35)
⎝ tr ⎠
The current ic through the device is the same as the current through the inductor L. Therefore
1
ic = iL = V dt (2.36)
L L
Use Eq. (2.35) in Eq. (2.36) and integrate within the rise time period. Then apply the boundary condition
that at the end of the rise time period, the current through the device, that is the current through the inductor,
should be iL (the load current value). The inductor value L is then given by
Vcc t r
L= (2.37)
2iL

Selection of R
When Q is turned OFF, it should withstand the following components of the voltage:
1. The voltage across the freewheeling components, that is D and R. This is equal to iLR + VD, where VD
is the diode forward drop.
2. The supply voltage Vcc.
Thus the following inequality should be satisfied for the device voltage rating.
Vcc + iL R + VD < Vceo (2.38)
where Vceo is the maximum collector–emitter voltage rating of the transistor.
Re-arranging inequality (2.38), the following inequality is obtained:
Vceo − Vcc − VD
R< (2.39)
iL
It is also important to ensure that the magnetic energy in the inductor L discharges fully before the next
charging when the transistor turns ON. Therefore, there is a minimum duration of time during which time
the transistor should remain OFF so that the inductor energy can fully discharge. The discharge time constant
of the inductor is L/R. In five times this time constant, the inductor will be almost fully discharged.
Therefore,
L
Toff-min > 5 (2.40)
R
where Toff-min is the minimum time for which the device Q should remain in the OFF-state.
Re-arranging inequality (2.40), the following inequality is obtained:

5L
R> (2.41)
Toff-min
From inequalities in Eqs. (2.39) and (2.41), the range for choice of R is given by

5L V − Vcc − VD
< R < ceo (2.42)
Toff-min iL

Chapter 02.indd 84 3/12/2009 4:02:28 PM

Drive Circuits 85

The power dissipated in R is given by

1 2
PR = Li f (2.43)
2 L s
where fs is the switching frequency of the device Q.

| CONCLUDING REMARKS
In this chapter we have discussed the requirements just by handling. They must be place on anti-static
for driving the BJTs and the MOSFETs giving a pads with the gate and source/collector shorted. In
flavor for the various types of drive circuits. It addition, a protective 15 V Zener diode is connected
should, however, be noted that by no means is the between gate and source/emitter to provide a measure
list of discussed drive circuits exhaustive. There are of clamping if the static induced voltage exceeds 15 V.
many ICs and hybrid circuits available commercially However, once the MOSFETs and IGBTs are mounted
that implement the drives circuits of all the switches onto the printed wiring boards or connected to the
of either half-bridge or full-bridge or three-phase drive circuits, they are usually very robust.
full-bridge as a single device. These integrated devices The key to reliable power switch performance
in addition provide features like overcurrent protec- is to ensure that the locus of the operating point is
tion and thermal protection. If a fault occurs, a fault always within the forward and reverse safe operat-
output is provided that can be used as an interrupt ing areas (SOARs). Any transition of the operating
signal to disable the drive pulses to the bridge circuit point locus across the boundary of the SOAR will
used in a converter or inverter application. Whether cause overstressing of the semiconductor bulk and
one uses a discrete drive circuit or an integrated the junctions. This will cause fast aging of the
drive circuit device for a specific application depends device leading to deterioration and premature fail-
on the cost, size, isolation feature, protection features ure. Most failures of the power switches are due to
and interface compatibility to microcontrollers or non-restriction of the operating point locus within
DSPs. However it should be borne in mind that the the SOAR during switching transitions. If such a
reliability and the performance of the power switch situation is even suspected, then appropriate snub-
is very much dependent on the drive circuit. It is not ber circuits must be incorporated to reduce the
without reason that the phrase “a power electronic device stresses even though it may be at the expense
product is as good as the drive circuit ” is central to the of efficiency.
performance of power electronic systems. Practice and practical are the essence of a good
BJTs are generally more robust during handling engineer. One must strive to both simulate and
whereas care must be taken in handling MOSFETs breadboard the BJT and MOSFET drive circuits
and IGBTs. The MOSFETs and IGBTs are voltage- discussed in this chapter and more by referring to
controlled devices. Their turn-ON depends on the literature. The next section provides few exercises
gate charge that is provided. The body of a person that can be simulated in spice and also implemented
contains sufficient static charge to charge up the gate by hardware breadboarding. The insights gained in
capacitance to a few hundred volts whereas the gate– obtaining experimental clarifications will be helpful
source or gate–emitter can handle only around 20 V. while designing DC–DC converters and DC–AC
Therefore, in many cases, the devices will get damaged inverters.

Chapter 02.indd 85 3/12/2009 4:02:28 PM

86 Power Electronics

| LABORATORY EXERCISES
1. Consider the BJT drive test circuit shown in (c) From the tabulated values of ib, ic and Vce,
Figure 2.33. It consists of the test transistor Q p compute the product ic × Vce the instanta-
that is to be studied. Q p is used to switch a resis- neous power loss in the device. Plot ib, ic,
tive load Rc that draws power from a 15 V DC Vce and ic × Vce versus time.
supply. The base drive circuit comprises comple- (d) What is the effect of R1 on the above
mentary transistors Q 1 (NPN) and Q 2 (PNP) waveforms?
transistors that are connected as shown. Q 1 col- (e) At what value of ic and ib does Vce attain
lector is connected to Vcc positive pole and Q 2 saturation value of around 0.3 V?
collector is connected to Vee negative pole as (f ) At what value of ic and ib does Vce attain a
shown. The base pulse signal source Vb is used to value around 0.7 V which is just at the
provide the base drive pulse signal to switch the boundary of saturation?
power transistor Q p at a specific frequency. (g) Set R1 to an appropriate value. Set Vee = 5 V.
Mode of implementation: The above circuit Measure and tabulate ic, ib and Vce of Q p
can be studied by for various values of Vcc.
a. Simulation in Spice (h) From the tabulated values of ib, ic and Vce,
b. Hardware breadboarding compute the product ic × Vce the instanta-
neous power loss in the device. Plot ib, ic,
Tasks for study: Vce and ic × Vce versus time.
(a) Rig up the circuit/netlist as given in (i) What is the effect of Vcc on the above
Figure 2.33. waveforms?
(b) Set Vcc = 10 V, Vee = 5 V. Measure and ( j) Set R1 to an appropriate value. Set Vcc = 10 V.
tabulate ic, ib and Vce of Q p for various Measure and tabulate ic, ib and Vce of Q p
values of R1. for various values of Vee.

15 V

RC
Vcc
0−10 V ic
Q1
R3 ib
QP Vce
Vb R1
Q2
Vee
0−5 V 0−5 V
R2

Figure 2.33 BJT drive test circuit.

Chapter 02.indd 86 3/12/2009 4:02:28 PM

Drive Circuits 87

(k) From the tabulated values of ib, ic and Vce, (c) From the tabulated values of ib, ic and Vce,
compute the product ic × Vce the instanta- compute the product ic × Vce the instanta-
neous power loss in the device. Plot i b, ic, neous power loss in the device. Plot i b, ic,
Vce and ic × Vce versus time. Vce and ic × Vce versus time.
(l) What is the effect of Vee on the above (d) What is the effect of R2 on the above wave-
waveforms? forms?
2. Consider the BJT drive test circuit shown in (e) Set Vcc = 10 V. Set R1 to provide steady-
Figure 2.34. It is the same as the test circuit of ON base-current value appropriate for the
Figure 2.33 but for the inclusion of the speed collector current. Set R2 to provide the i b+.
up circuit. Measure and tabulate ic, ib and Vce of Q p
for various values of Vee.
Mode of implementation: The above circuit (f ) From the tabulated values of ib, ic and Vce,
can be studied by compute the product ic × Vce the instanta-
a. Simulation in Spice neous power loss in the device. Plot i b, ic,
b. Hardware breadboarding Vce and ic × Vce versus time.
Tasks for study: (g) What are the values of ib+ and ib – at which
turn-ON and turn-OFF is best and switching
(a) Rig up the circuit/netlist as given in power dissipation is least?
Figure 2.34. (h) On incorporating another BJT in
(b) Set Vcc = 10 V, Vee = 5 V. Set R1 to provide Darlington configuration with the output
steady-ON base-current value appropriate for power BJT Q p as shown in Figure 2.35,
the collector current. Measure and tabulate ic, what is the effect on the base drive
ib and Vce of Q p for various values of R2. requirements?
Ensure in all cases that R2 is less than R1/5.

15 V

RC
Vcc
0−10 V R2 C ic
Q1
R3 ib
QP Vce
Vb R1
Q2
Vee
0−5 V 0−5 V
R2

Figure 2.34 BJT drive test circuit.

Chapter 02.indd 87 3/12/2009 4:02:28 PM

88 Power Electronics

15 V Mode of implementation: The above circuit

can be studied by
Rc a. Simulation in Spice
b. Hardware breadboarding
ic
Tasks for study:
ib
QP1 (a) Rig up the circuit/netlist as given in
QP Vce Figure 2.36.
RP1
(b) Set Vcc = 15 V, Vee = 5 V. Measure and
tabulate id, ig and Vds of Q p for various
RP2 values of R1.
(c) What is the effect of R1 on the turn-ON
Figure 2.35 Darlington configuration of the and turn-OFF times? From the tabulated
output power transistor. (All other values of id, ig and Vds estimate the gate
portions of the drive are the same charge required to turn-ON the MOSFET
as in Figure 2.34.) to full enhancement.
3. Consider the MOSFET drive test circuit shown (d) Set R1 to an appropriate value. Set Vcc = 15 V.
in Figure 2.36. It consists of the test MOSFET Measure and tabulate id, ig and Vds of Q p
Q p that is to be studied. Q p is used to switch a for various values of Vee.
resistive load Rc that draws power from a 15 V (e) What is the effect of Vee on the above
DC supply. The gate drive circuit comprises waveforms?
complementary transistors Q 1 (NPN) and Q 2 4. Consider the MOSFET shunt snubber test cir-
(PNP) transistors that are connected as shown. cuit shown in Figure 2.37. It consists of the test
Q 1 collector is connected to Vcc positive pole and MOSFET Qp that is used to switch a resistive load
Q 2 collector is connected to Vee negative pole as Rd that draws power from a DC supply, Vdd. The
shown. The gate pulse signal source Vg is used to inductance L1 indicates the track inductance of
provide the gate drive pulse signal to switch the the inductive effects in the load. The shunt snub-
power MOSFET Q p at a specific frequency. ber circuit comprising R, C and D is connected

15 V

Vcc id
0−15 V
Q1
R3 QP Vds
ig

Vg R1
Q2
Vee
0−5 V 0−5 V
R2

Figure 2.36 MOSFET drive test circuit.

Chapter 02.indd 88 3/12/2009 4:02:29 PM

Drive Circuits 89

Vdd

Vcc(15 V) L1
R

MOSFET QP
Vg drive
circuit R1 D
C

Figure 2.37 MOSFET shunt snubber test circuit.

as shown. The gate pulse signal Vg is used to pro- (b) Set Vdd = 100 V, Rd = 20 Ω. Measure and
vide the gate pulse signal to switch the power tabulate id and Vds of Q p for various values
MOSFET Q p at a specific frequency. The pulse of C.
signal from Vg is passed through an appropriate (c) What is the effect of C on the Vds waveform?
MOSFET drive circuit to provide the necessary (d) What is the effect of R on the turn-ON
gate charge to switch the MOSFET Q p. drain current of the MOSFET?
(e) Measure the rms current through R and
Mode of implementation: The above circuit compute the power dissipation in R with
can be studied by and without D.
a. Simulation in Spice (f ) How does the modified shunt snubber cir-
b. Hardware breadboarding cuit as shown in Figure 2.38 operate? What
Tasks for study: is the effect on the id and Vds waveforms?
What is the role of RC time constant on
(a) Rig up the circuit/netlist as given in the Vds waveform? What should be the
Figure 2.37. value of R and C for a given load?

Vdd

L1
Vcc(15 V)

D
MOSFET QP
C R
Vg drive
circuit R1

Figure 2.38 Modified shunt snubber circuit.

Chapter 02.indd 89 3/12/2009 4:02:29 PM

90 Power Electronics

5. Consider the MOSFET series snubber test cir- passed through an appropriate MOSFET drive
cuit shown in Figure 2.39. It consists of the test circuit to provide the necessary gate charge to
MOSFET Q p that is used to switch a capaci- switch the MOSFET Q p.
tive load. The series snubber circuit comprising
Mode of implementation: The above circuit
R, L and D is connected as shown. The gate
can be studied by
pulse signal Vg is used to provide the gate pulse
signal to switch the power MOSFET Q p at a a. Simulation in Spice
speciﬁc frequency. The pulse signal from Vg is b. Hardware breadboarding

Vdd

D
L
R
Vcc(15 V)

MOSFET QP
Vg drive
circuit R1

Figure 2.39 MOSFET series snubber test circuit.

Vdd

L
R C
Vcc (15 V)

MOSFET QP

Vg drive
circuit R1

Figure 2.40 Modified series snubber circuit.

Chapter 02.indd 90 3/12/2009 4:02:29 PM

Drive Circuits 91

Tasks for study: (e) Measure the rms current through R and
compute the power dissipation in R.
(a) Rig up the circuit/netlist as given in Figure
2.39. (f ) How does the modified series snubber
circuit as shown in Figure 2.40 operate?
(b) Set Vdd = 15 V. Measure and tabulate id
What is the effect on the id waveform and
and Vds of Q p for various values of L.
Vds waveform? What is the role of RC time
(c) What is the effect of L on the id waveform? constant on the id and Vds waveforms?
What should be the value of R and C for a
(d) What is the effect of R on the turn-OFF
given load?
drain–source voltage of the MOSFET?

| FILL IN THE BLANKS

1. BJT is a device. 11. If the collector current , then the
transistor will come out of saturation and oper-
2. In BJT switching, the base currents are
ate in the active region.
on the collector currents.
12. In applications where the load current can vary
3. During the turn-ON period, the base current
in a wide range, the base current should vary
must be than the ﬁnal or steady-ON
to the collector current. Such a base
value.
drive circuit is called .
4. During the turn-OFF period, a base
13. Isolation between the higher power collector
current should be provided to quickly remove
side and the lower power base side of the power
the stored charges in the transistor.
transistor is provided either by using
5. For the BJT drive circuit-1, R2 is used to pro- or by using .
vide the path for removing the
14. In the case of opto-coupler isolation, the duty
charges during turn-OFF.
cycle can be varied from 0 to 1, but
6. In BJT drive circuit-2, the two transistor stages, power supplies for the diode side and transistor
Q 2 and Q 1, provide the gain to suit- side of the opto-coupler are required.
ably drive Q p.
15. In the case of transformer isolation, the duty
7. In BJT drive circuit-3, the turn-OFF time of cycle can be varied only from .
the power transistor is improved by using an
16. MOSFET is a .
.
17. In MOSFET switching, the gate currents are
8. During turn-OFF, the negative base current for
on the drain currents.
fast turn-OFF in BJT drive circuit-6 is given
by . 18. The gate current is during the steady-
ON period when the MOSFET is ON.
9. If the transistor is operated to be just out of
, then the stored base charge is small 19. Compared to the BJT, the MOSFET drive
and the turn-OFF times will be very fast. circuit power requirement is .
10. If the collector current , then the 20. The beneﬁts of the dual transformer ORed
transistor will be overdriven into saturation for circuit as given in MOSFET drive circuit-9 are
the same base drive. , and .

Chapter 02.indd 91 3/12/2009 4:02:29 PM

92 Power Electronics

21. In MOSFET drive circuit-10, when the output 23. limits the voltage across the device
power MOSFET is OFF, the gate is during turn-OFF process.
and open to due to large dv/dt spikes
24. Turn-OFF snubber is also called .
on the drain side.
25. If there is a capacitive load or parasitic capaci-
22. If there is an inductive load in the collector or
tance across the device, then a large
if there is significant amount of lead inductance
flows through the device at turn-ON.
associated with the collector or emitter leads,
then when the BJT is being turned OFF, the 26. Turn-ON snubber circuit limits the
current through the device will fall rapidly to the device during turn-ON process.
zero in a time corresponding to the fall time of
27. Turn-ON snubber is also called .
the device leading to large stress
on the device. 28. The circuits with snubbers will be
efficient.

| DESCRIPTIVE QUESTIONS
1. Discuss the effect of the base drive waveshape on 12. Explain the operation of the opto-coupler-based
the turn-ON and turn-OFF speeds of the device. BJT drive circuit-8.
2. Discuss the effect of the base drive waveshape 13. Explain the operation of the transformer-based
on the switching power dissipation. BJT drive circuit-9.
3. What are the requirements of a good base drive? 14. Explain the operation of the BJT drive circuit-12.
Illustrate with the base-current waveform.
15. What is the difference between BJT drive
4. Explain the operation of the BJT base drive circuit-12 and BJT drive circuit-13?
circuit-1.
16. Explain the operation of MOSFET drive
5. Explain the operation of the BJT base drive circuit-1. What is the function of resistor R2?
circuit-2. Under what constraints should R2 be used?
6. How does the operation of BJT drive circuit-3 17. In MOSFET drive circuit-2, why are the buffers
differ from that of BJT drive circuit-4? connected in parallel?
7. In BJT drive circuit-5, the R2-C is the speed up 18. Explain the operation of MOSFET drive
circuit that ensures fast turn-ON. Explain? circuit-3.
8. Explain the difference between the BJT drive 19. Explain the difference between the opto-
circuit-5 and BJT drive circuit-6. isolated BJT drive circuit-8 and MOSFET
drive circuit-4.
9. What is Baker’s clamp? Where and why is it
used? 20. “The MOSFET drive circuit-6 is used to drive
the top MOSFET of bridge arms.” Explain its
10. Explain the operation of a non-isolated
operation.
proportional-base drive circuit.
21. How can the duty cycle range be improved
11. What is the function of D1 in the proportional-
with transformer isolation between the collec-
base drive circuit as given in BJT drive circuit-7?
tor side and the base drive side?

Chapter 02.indd 92 3/12/2009 4:02:29 PM

Drive Circuits 93

22. In the MOSFET drive circuit-9, what is the func- 24. The protection circuit discussed in MOSFET
tion of the secondary-side resistors R1 and R4? drive circuit-11 needs to be disabled at turn-ON.
Why?
23. Explain the operation of MOSFET drive
circuit-10.

| PROBLEMS
1. A BJT has to switch a load of 1 A. The base turn-ON is 2 A, then calculate the turn-ON
drive power is derived from 5 V voltage source. time.
Calculate the values of resistors R1 and R2 for
8. For Problem 7 above, what is the peak current
the BJT having saturation hFE as 100.
requirement for a turn-ON time of 1 μs? Calcu-
2. A BJT has to switch a load of 10 A that is late the gate resistance that needs to be connected
connected to a 400 V DC link/bus. The BJT in series.
drive circuit-3 is used to drive the power tran-
9. What should be the voltage and current rating
sistor. The power transistor has a saturation
of Q 2 in MOSFET drive circuit-3?
hFE of 80. The base drive is powered from a 10
V DC source. Calculate the values of R1, R2 10. A bridge arm is used as part of a converter. The
and L. DC-link voltage is 400 V. The gate power
supply is derived from a 15 V power supply.
3. A load of 10 A is to be switched by a BJT. The
The MOSFET drive circuit-6 is employed to
BJT base drive circuit is powered from 10 V DC
drive the top MOSFET of the bridge arm. The
source. The BJT selected for the application has
bridge MOSFETs are switching a drain cur-
the following specifications: hFE(sat) = 100,
rent of 10 A. The RDS(ON) of the bridge MOS-
tr = 2 μs and tf = 2 μs. If the BJT drive circuit-5
FETs is 0.1 Ω. When the top MOSFET is
is used in the application, then calculate the
ON, what is the reverse voltage across the
values of R1, R2 and C.
diode D?
4. In BJT drive circuit-10, consider the time
11. In the protection circuit of MOSFET drive
period when the transistor Q 1 is ON. What is
circuit-11, a drain current of 20 A flows
the voltage across the freewheeling diode Df
through the power MOSFET that has a RDS(ON)
during this time period?
of 0.1 Ω. What is the voltage at the “+” terminal
5. In the BJT drive circuit-11, the PNP transistor of ampliﬁer A1?
Q 1 is used to ensure fast turn-OFF of the power
12. A MOSFET is switching a 20 A inductive load
transistor. What should be the Vce and the col-
from a 100 V DC source. The fall time of the
lector-current rating of the transistor Q 1?
device is 0.5 μs. Calculate the shunt snubber
6. For a varying load current that has a maximum capacitance value.
value of 10 A, design a proportional-base drive
13. For Problem 12, the peak current rating of the
circuit as discussed in BJT drive circuit-13.
MOSFET is speciﬁed as 30 A. The converter,
7. A particular MOSFET requires 400 nC to take where the MOSFET is used, operates at a
it to full enhancement. The MOSFET is driven switching frequency of 20 kHz. The range of
from a 15 V source. If the peak gate current during duty cycle is from 0.2 to 0.7. What is the value

Chapter 02.indd 93 3/12/2009 4:02:30 PM

94 Power Electronics

of the shunt snubber resistor? What is the power time of the device is 2 μs. Calculate the series
dissipation in the shunt snubber resistor? snubber inductance value. The voltage rating
of the device is speciﬁed as 150 V. The con-
14. For Problem 13, what is the snubber diode
verter where the IGBT is used operates at a
current and peak inverse voltage rating?
switching frequency of 20 kHz. The range of
15. An IGBT is switching a capacitive load. The duty cycle is from 0.2 to 0.7. What is the
load current is 20 A drawn from a 100 V DC value of the series snubber resistor? What is
source. To protect against the turn-ON cur- the power dissipation in the shunt snubber
rent surges, a series snubber is used. The rise resistor?

| ANSWERS
Fill in the Blanks
1. current-controlled 12. in proportion; proportional- isolated power supplies on
2. dependent base drive circuit the secondary side
3. higher 13. opto-couplers; transformers 21. ﬂoating; turn-ON
4. negative 14. isolated 22. voltage
5. discharge; stored base 15. 0 to 0.5 23. Turn-OFF snubber circuit
6. current 16. voltage-controlled device 24. shunt snubber
7. inductor 17. not dependent 25. current surge
8. (Vcc + Vbesat)/R1 18. zero 26. current through
9. saturation 19. lesser 27. series snubber
10. decreases 20. isolation; full range of duty 28. less
11. increases cycle; no requirement for

Chapter 02.indd 94 3/12/2009 4:02:30 PM

Rectifiers

Learning Objectives
CHAPTER

3
After reading this chapter, you will be able to:
understand the operation of rectifiers and the effect of the various loads on rectifier
functioning.
draw current and voltage waveforms at various points in the circuit.
understand and design capacitor-filter rectifier circuits.
understand the operation of controlled rectification.

T his chapter deals primarily with converting the AC voltage that is available from the mains to the DC
voltage which is required for most electronic products. The AC voltage is first converted to a pulsating
DC voltage by using diodes or thyristor. This pulsating DC is then filtered to provide smooth DC voltage.
The rectifiers may be broadly classified as
1. uncontrolled rectifiers;
2. controlled rectifiers.
The uncontrolled rectifiers use diode as the semiconductor power switch. As the turn-ON and turn-OFF of the
diode is uncontrolled (discussed in Chapter 1), such rectifier topologies using diodes as the power switch are called
uncontrolled rectifier. On the other hand, if any of the controllable power semiconductor switches like the bipolar
junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar
transistors (IGBTs) and thyristors are used, then such rectifiers are called controlled rectifiers.
The uncontrolled rectifiers are discussed first in this chapter. The various single- and three-phase rectifier
configurations are discussed. This is followed by a discussion on the popular capacitor input filter rectifier
wherein the operation and design of capacitor input filters are dealt. The inrush current at rectifier startup is
also addressed by including some methods to solve this problem. The discussion on the capacitor input filter
is followed by the inductance input filter or the LC-filter rectifier. The output ripple content of the LC filter
is analyzed. The effect of LC filter on the currents in the rectifier is also discussed.
After discussing uncontrolled rectifiers, the controlled rectifiers are addressed. The phase-controlled
converters, viz., single-phase half-wave controlled converters, single-phase full-wave converters, three-phase
half-wave controlled converters, three-phase full-wave half-controlled converters and three-phase full-wave
full-controlled converters are considered. The firing sequences and the corresponding waveforms at the rectifier
outputs are also discussed.

Chapter 03.indd 95 3/12/2009 3:49:15 PM

96 Power Electronics

3.1 Uncontrolled Rectifiers

E lectrical power generation and distribution is usually accomplished in the form of AC currents and
voltages. However, many types of electronic and electrical equipments operate from DC sources. The
AC voltage must therefore be rectified and filtered to provide a DC output voltage at a specified current or
power level. Depending on the load power requirements, the AC input may be obtained from
1. single-phase supply for low-to-medium power requirements;
2. three-phase supply for medium-to-high power requirements.
A transformer may be used in between the AC input supply and the rectifier input to provide
1. voltage scaling;
2. isolate the input from the rectifier output.
In such cases, the transformer should be capable of handling the entire load power and should be designed
for the mains frequency. This would increase the cost, size and weight of the rectifier. Frequently, the
input voltage is directly rectified by using a transformer and the filtered rectifier output is then switched
at a high frequency across a load or transformer supplying the load. A typical example of the latter case is
switching power supplies and step-up frequency converters. In either case, the magnetics operate at a
higher frequency for size, weight and cost reduction. These are classified as DC–DC converters that are
discussed in Chapter 5.
In high-power systems, regulation is frequently accomplished by controlling the phase or conduction
time of the AC wave by thyristors (silicon-controlled rectifiers; SCRs). In low-power systems, such as
AC–DC power supplies, regulation is usually achieved by either a transistor post regulator like in linear
regulator or by pulse-width modulation for switched-mode regulation.

3.2 Rectifier Circuits

T he uncontrolled rectifier circuits consist primarily of diode semiconductor switches. The diodes are
connected in various topological configurations. The source for the rectifier circuits is considered to be
a sinusoidal voltage source such as the mains/grid that is the most common source in many applications.
Based on the type of the input source for the rectifiers, they are broadly classified as
1. single-phase rectifier circuits;
2. three-phase rectifier circuits.
As the names imply, the single-phase rectifier circuit topologies are designed for applications wherein the
input source is the single-phase grid and likewise, the three-phase rectifier circuit topologies are designed for
applications with three-phase grid as the input source.

Single-Phase Circuits
In this category of rectifier topologies, there are three basic rectifier configurations that are popular:
1. half-wave rectifier;
2. full-wave center-tapped rectifier;
3. full-wave bridge rectifier.
These three basic configurations will now be discussed.

Chapter 03.indd 96 3/12/2009 3:49:16 PM

Rectifiers 97

Half-Wave Rectifier
The single-phase half-wave rectifier circuits for various load conditions are shown in Figure 3.1. The recti-
fier topology of Figure 3.1(a) is applicable for resistive and/or capacitive loads. On the other hand, the
rectifier topology of Figure 3.1(b) is applicable for inductive and/or resistive–inductive loads. The diode D2
across the load is needed for providing a path for the trapped kinetic energy in the inductor to discharge
when the diode D1 is reverse-biased. As the diode D2 provides a path for the inductor current to freewheel
through it when D1 is OFF, D2 is called the freewheeling diode. The mains/grid voltage Vin is applied at the
primary of the transformer. The voltage at the secondary of the transformer is nVin. The choice of the turns
ratio n depends on the load voltage requirements.
Whenever the dot poles of the transformer are positive, diode D1 will conduct and the load voltage VL
will follow the secondary voltage Vs. During this time the diode D2 in the case of circuit of Figure 3.1(b)
will be reverse-biased and therefore OFF. When Vs goes negative with respect to the dot pole, D1 will be
reverse-biased and will switch OFF. If the load is inductive, then the inductive current will freewheel
through diode D2.
Figure 3.2 shows the voltage and current waveforms for a resistive load. In this case the diode D2 is not
operative. Referring to the waveforms shown in Figure 3.2, the load voltage is a pulsating half-sinusoid as
indicated. It is given by
nVm
VLav = (3.1)
π
where VLav is the average voltage across the load resistor RL; Vm is the peak voltage of the input sine wave; n
is the transformer turns ratio.

D1 IL
1:n

Load
Vin Vs VL (R or RC)

(a)

D1
1:n IL

Load
Vin Vs D2 VL (L or RL)

(b)

Figure 3.1 Half-wave rectifier configuration: (a) For resistive–capacitive

loads; (b) for resistive–inductive loads.

Chapter 03.indd 97 3/12/2009 3:49:16 PM

98 Power Electronics

Vin

0 t

nVm

VL
VLav

0 t
Im /n
IL
ILav

0 t

Figure 3.2 Half-wave rectifier: Waveforms for resistive load.

The average load current is given as

nVm
I Lav = (3.2)
π RL
where ILav is the average load current and the remaining symbols have their usual meaning. The power
delivered to the load is given as

1
T /2
⎛ nVm sin ω t ⎞
Po =
T ∫ (nVm sin ω t ) ⎜⎝ RL ⎟ dt
⎠
0

n 2Vm 2 ⎛ nVm ⎞ ⎛ nVm ⎞ (3.3)

= =⎜ ⎟⎜ ⎟
4 RL ⎝ 2 ⎠ ⎝ 2 RL ⎠
= VLrms I Lrms

where VLrms is the root mean square (rms) voltage across the load resistor and ILrms is the rms current ﬂowing
through the load resistor.
The current through the secondary of the transformer is also same as that of the load and hence the rms
secondary current is given as
I srms = I Lrms (3.4)

The primary or line side rms current is given as

I prms = nI srms (3.5)

Chapter 03.indd 98 3/12/2009 3:49:16 PM

Rectifiers 99

It can be seen from the waveforms of Figure 3.2 that the maximum peak inverse voltage (PIV) that Dl
should withstand when OFF is Vm. Likewise in the case of inductive loads, D2 is operative. When D2 is
OFF, D1 is ON. The maximum PIV that D2 should withstand when OFF is also Vm.
The output voltage is only a half sine wave. Some form of output ﬁltering is essential to obtain a low
ripple output voltage. This topology can also be used for direct line rectiﬁcation by removing the costly
transformer. However, the half-wave circuit is usually limited to low-power, poor output ripple applications.
This topology is used to obtain the DC bus voltage for inputs of linear regulators in power supplies.

Full-Wave Center-Tapped Rectifier

The full-wave center-tapped rectifier circuit is shown in Figure 3.3. Here the use of a transformer is manda-
tory. The turns ratio n is defined as the ratio of the number of windings in the secondary between the dot pole
and the center-tap to the number of windings in the primary. Referring to Figure 3.3, diode D1 will conduct
when the dot poles of the transformer are positive and VL will follow the positive half of Vs. When the dot
poles are negative, diode D2 will conduct resulting in a full wave rectified waveform at the output. Here, the
peak-reverse voltage for the diodes is twice Vs, thus demanding a higher reverse voltage rating for a given VL
requirement.
In the case of the center-tapped rectifier circuit, there is no need for a separate freewheeling diode. This
is due to the fact that one of either D1 or D2 is always ON. The voltage and current waveforms are shown in
Figure 3.4.
Referring to the waveforms shown in Figure 3.4, the load voltage is a pulsating full sinusoid as indicated.
It is given by
2nVm
VLav = (3.6)
π
where VLav is the average voltage across the load resistor RL; Vm is the peak voltage of the input sine wave;
n is the transformer turns ratio. The average load current is given as
2nVm
I Lav = (3.7)
π RL
where ILav is the average load current.

D1
1:n IL

Vs = nVin VL Load

Vin

Figure 3.3 Full-wave center-tapped rectifier.

Chapter 03.indd 99 3/12/2009 3:49:17 PM

100 Power Electronics

Vin

0 t

nVm
VLav
VL

0 t
Im/n ILav
IL

0 t
Im/n

ID1

0 t
Im/n
ID2

0 t
Im
Iin

0 t

Figure 3.4 Center-tapped full-wave rectifier: Waveforms for resistive load.

The power delivered to the load is given as

T /2
⎛ nVm sin ω t ⎞
∫ (nVm sin ω t ) ⎜⎝
2
Po = ⎟ dt
T 0
RL ⎠
(3.8)
n Vm 2 ⎛ nVm ⎞ ⎛ nVm ⎞
2
= =⎜ ⎟⎜ ⎟ = VLrms I Lrms
2 RL ⎝ 2 ⎠ ⎜⎝ 2 RL ⎟⎠
where VLrms is the rms voltage across the load resistor and ILrms is the rms current ﬂowing through the load
resistor.

Chapter 03.indd 100 3/12/2009 3:49:17 PM

Rectifiers 101

The current through the secondary of the transformer is a half-wave rectified waveform. The portion of
the transformer secondary winding above the center-tap carries current only when D1 is ON as indicated in
ID1 waveform of Figure 3.4. On the other hand, the portion of the secondary winding below the center-tap
carries current only when D2 is ON as indicated in ID2 waveform of Figure 3.4. Thus the secondary winding
currents are half-wave rectified waveforms. The rms value of the secondary winding current is given as
nVm I Lrms
I srms = = (3.9)
2 RL 2
The primary or line side current is however a full sine waveshape as this is the algebraic sum of the reflected
secondary winding currents. This is indicated in the Iin waveform of Figure 3.4. The rms primary or line side
current is given as
I prms = nI Lrms (3.10)
Unlike the half-wave rectifier topology, the output voltage here is a full-wave rectified waveform. This means
that the output filter requirement is less stringent as compared to the half-wave rectifier output.

Full-Wave Bridge Rectifier

The full-wave bridge rectifier circuit is shown in Figure 3.5. This is one of the most popular rectifier configu-
rations used in many practical circuits. Here four diodes are used as indicated. When the dot poles of the
transformer are positive, then D1 and D4 will conduct. When the dot poles are negative, then D3 and D2 will
conduct thus resulting in a full-wave rectified voltage waveform at the output. It should be noted that the
full-wave bridge topology can also be used for direct line rectification wherein one can avoid using the input
transformer.
The bridge circuit is normally used for medium-to-high-voltage output applications. Here, the peak-
reverse voltage for all the diodes is Vs itself, thus requiring diode with PIV ratings that are half that
required for the center-tapped configuration for a given output voltage requirement. However, it should
be noted that two diodes at any given instant will conduct and are in series. Hence there will be two diode
drops in the bridge rectifier topology as compared to the half-wave or full-wave center-tapped rectifier
topologies.

D1 D3

1:n

VL Load
Vin Vs = nVin (R, L, C)

D2 D4

Figure 3.5 Full-wave bridge rectifier.

Chapter 03.indd 101 3/12/2009 3:49:17 PM

102 Power Electronics

In the case of the bridge rectiﬁer circuit also, there is no need for a separate freewheeling diode. This is
due to the fact that diode pair D1, D2 and diode pair D3, D4 act as freewheeling paths for any inductive load.
The voltage and current waveforms are shown in Figure 3.6.
Referring to the waveforms shown in Figure 3.6, the load voltage is a pulsating full sinusoid as indicated.
2nVm
VLav = (3.11)
π
where VLav is the average voltage across the load resistor RL; Vm is the peak voltage of the input sine wave;
n is the transformer turns ratio.

Vin

0 t

nVm VLav
VL

0 t
Im/n ILav
IL

0 t
Im/n

ID1, ID4

0 t
Im/n
ID2, ID3

t
Im
Iin

0 t

Figure 3.6 Bridge full-wave rectifier: Waveforms for resistive load.

Chapter 03.indd 102 3/12/2009 3:49:18 PM

Rectifiers 103

The average load current is given as

2nVm
I Lav = (3.12)
π RL
where ILav is the average load current. The power delivered to the load is given as

2
T /2
⎛ nVm sin ω t ⎞
Po =
T ∫ (nVm sin ω t ) ⎜⎝ RL ⎟ dt
⎠
0

n Vm 2 ⎛ nVm ⎞ ⎛ nVm ⎞
2 (3.13)
= =⎜ ⎟⎜ ⎟ = VLrms I Lrms
2 RL ⎝ 2 ⎠ ⎜⎝ 2 RL ⎟⎠

where VLrms is the rms voltage across the load resistor and ILrms is the rms current ﬂowing through the load
resistor.
The current through the secondary of the transformer is a full-wave rectiﬁed waveform. The rms value of
the secondary winding current is given as
I srms = I Lrms (3.14)

The primary or line side current is a full sine waveshape that is the reﬂected secondary winding current. This
is indicated in the Iin waveform of Figure 3.6. The rms primary or line side current is given as
I prms = nI Lrms (3.15)

The currents through the diodes are half-wave rectified waveforms as indicated in Figure 3.6. As in the
case of the center-tapped full-wave rectifier topology, the output voltage here is a full-wave rectified wave-
form. This means that the output filter requirement is less stringent as compared to the half-wave rectifier
output.

Three-Phase Circuits
Three-phase power is used in medium-to-high-power applications and may be applied to an off-line rectifier,
say to produce a nominal 560 V DC bus from a 400 V AC line, or to a transformer whose secondary or
secondaries are rectified in various manners. The advantages of using three-phase power as compared to
single-phase power are: (a) higher output voltages, (b) lower output ripple, (c) higher input power factor and
(d) reduced harmonic distortion of the input current.
Figures 3.7 and 3.8 show the Y–Y and Δ–Y half-wave rectifier circuit configurations. The RYB
secondary-side line-to-line voltages, the load voltage and the load currents for a resistive load are shown
in Figure 3.9. It can be observed that the load voltage ripple is considerably reduced as compared to that
of the single-phase rectifier configurations. Referring to Figure 3.9, it can be observed that the load voltage
ripple swing is from the peak voltage nVm to nVmcos(60°), that is, nVm/2. Referring to Figure 3.9 and
considering the voltage reference axis to be at the peak of the sinusoid, the load voltage contribution
from each phase is
π /3
1
2π ∫ nVm cos θ dθ (3.16)
− π /3

where n is the secondary to primary line-to-line turns ratio.

Chapter 03.indd 103 3/12/2009 3:49:18 PM

104 Power Electronics

VL Load
Y
D2

B
D3

Figure 3.7 Three-phase half-wave rectifier, Y–Y.

VL Load
D2

B
D3

Figure 3.8 Three-phase half-wave rectifier, Δ–Y.

Each of the three phases contribute to the total load average voltage equally in a period and hence the
average load voltage is given as
π /3
3 3nVm π /3 3 3nVm
VLav =
2π ∫ nVm cos θ dθ =
2π
sin θ − π /3 =
2π
(3.17)
− π /3

The average load current for a resistive load RL is given as

VLav 3 3nVm
I Lav = = (3.18)
RL 2π RL

Chapter 03.indd 104 3/12/2009 3:49:18 PM

Rectifiers 105

R Y B
nVm
VS

0 t

60˚
nVm/RL

0 t
nVm/RL
ID1

0 t

Figure 3.9 Load voltage and current waveforms for half-wave rectifier
configurations of Figures 3.7 and 3.8.

The rms value of the load voltage is given as

π /3
1
VLrms =
2π ∫ (nVm cos θ )2 dθ × 3
− π /3

3n 2Vm 2 ⎛ π /3 ⎞
π /3 π /3
3n 2Vm 2 sin 2θ
=
2π ∫ cos 2 θ dθ =
4π ⎜⎝
⎜ θ − π /3 +
2
⎟
⎟
− π /3 − π /3 ⎠

⎛ 1 3 3⎞ n 2Vm 2 ⎛ 3 3 ⎞
= n 2Vm 2 ⎜ + ⎟ = ⎜1+ ⎟
⎝ 2 8π ⎠ 2 ⎝ 4π ⎠

nVm 3 3
VLrms = 1+ (3.19)
2 4π

Similarly, the rms value of the load current for a resistive load is given as

nVm 3 3
I Lrms = 1+ (3.20)
RL 2 4π

Chapter 03.indd 105 3/12/2009 3:49:19 PM

106 Power Electronics

The power delivered to the load is given as

⎡ 1 π /3 ⎛ nV cos θ ⎞ ⎤
Po = ⎢ ∫
⎢⎣ 2π −π /3
(nVm cos θ ) ⋅ ⎜⎜ m ⎟⎟ dθ ⎥ × 3
⎝ RL ⎠ ⎥⎦
π /3 π /3
3n 2Vm2 3n 2Vm2
=
2π RL ∫ cos 2 θ ⋅ dθ =
4π RL ∫ (1 + cos 2θ ) ⋅ dθ
−π /3 −π /3

3n 2Vm2 ⎛ π /3 sin 2θ ⎞
π /3
= ⎜θ + ⎟
4π RL ⎜ −π /3 2 ⎟
⎝ −π /3 ⎠

3n 2Vm2 ⎛ 2π 3⎞
= ⎜ + ⎟
4π RL ⎜⎝ 3 2 ⎟⎠

n 2Vm2 ⎛ 1 3 3 ⎞
Po = ⎜ + ⎟ (3.21)
RL ⎝ 2 8π ⎠
Referring to Eqs. (3.19) and (3.20), one can observe that the output power Po is
Po = VLrms I Lrms (3.22)
Diodes D1, D2 and D3 carry current for only a third portion of each period. The current in diode D1 is
shown in Figure 3.9. The average and the rms values of the diode currents are given as

3nVm
I Dav = (3.23)
2π RL

nVm 1 3
I Drms = + (3.24)
RL 2 3 4π

The secondary windings of the transformer carry the same currents as that flowing through the diodes.
Therefore the secondary winding average and rms currents are the same as that of the diodes. The primary
winding currents are turns ratio (n) times the secondary currents. In the case of star-connected primary, the
winding and line currents are same. In case the primary windings are delta-connected, the line currents are
3 times the winding currents.
Figure 3.10 shows a full-wave rectification with a three-phase bridge diode rectifier connected to the
secondary as indicated in Figure 3.10. It can be observed that the availability of the neutral point is not
essential for rectification in this topology. However, if the neutral point is available then a positive output at
the positive output rail with respect to the neutral and a negative output at the negative output rail with
respect to the neutral can be obtained in this configuration.
Figure 3.10 shows the D–Y full-wave bridge rectifier circuit configurations. The RYB secondary-side
line-to-line voltages, the load voltage and the load currents for a resistive load are shown in Figure 3.11.
Here the full-bridge topology performs a full-wave rectification. For example, when the secondary-side
R phase is positive, diode D1 conducts and when the R phase goes negative, diode D4 conducts. In a similar

Chapter 03.indd 106 3/12/2009 3:49:19 PM

Rectifiers 107

R
D1 D2 D3

Load
Y

D4 D5 D6

Figure 3.10 Three-phase full-wave bridge rectifier, Y–Y.

R Y B
Vsec

nVm

0
t

nVm/RL
iL

30°

0
t

nVm/RL
iD1

0
t

Figure 3.11 Load voltage and current waveforms for bridge rectifier
configurations of Figure 3.10.

Chapter 03.indd 107 3/12/2009 3:49:19 PM

108 Power Electronics

manner the diode pairs (D2, D5) and (D3, D6) bridge arms also operate. It can be noted that the load voltage
ripple is further improved as compared to the three-phase half-wave rectiﬁer circuit. Referring to Figure 3.11,
it can be observed that the load voltage ripple swing is from the peak voltage nVm to nVmcos(30°), that is,
3nVm / 2. There are six ripples in one period. This means that each phase contributes two of the six ripples.
Referring to Figure 3.11 and considering the voltage reference axis to be at the peak of the sinusoid, the load
voltage contribution from each phase is equal to
π /6
1
2
2π ∫ nVm cos θ dθ (3.25)
− π /6

where n is the secondary to primary line-to-line turns ratio.

Each of the three phases contribute to the total load average voltage equally in a period and hence the
average load voltage is given as
π /6
3 3nVm π /6 3nVm
VLav = 2
2π ∫ nVm cos θ dθ =
π
sin θ − π /6 =
π
(3.26)
− π /6

The average load current for a resistive load RL is given as

VLav 3nVm
I Lav = = (3.27)
RL π RL
The rms value of the load voltage is given as

π /6
1
2π −π∫/6
VLrms = (nVm cos θ )2 dθ × 6

3n 2Vm 2 ⎛ π /6 sin 2θ ⎞
π /6 π /6
3n 2Vm 2
⎜θ ⎟
=
2π ∫ cos 2 θdθ =
2π ⎜ −π /6
+
2 ⎟
−π /6 ⎝ −π /6 ⎠

⎛1 3 3⎞ n 2Vm 2 ⎛ 3 3 ⎞
= n 2Vm 2 ⎜ + ⎟= ⎜1 + ⎟
⎜ 2 4π ⎟ 2 ⎜⎝ 2π ⎟⎠
⎝ ⎠

nVm 3 3
VLrms = 1+ (3.28)
2 2π
Similarly, the rms value of the load current for a resistive load is given as

nVm 3 3
I Lrms = 1+ (3.29)
RL 2 2π
The power delivered to the load is given as

⎡ 1 π /6 ⎛ nV cos θ ⎞ ⎤
Po = ⎢ ∫
⎢⎣ 2π −π /6
(nVm cos θ ) ⋅ ⎜ m
⎝ RL
⎟ dθ ⎥ × 6
⎠ ⎥⎦

Chapter 03.indd 108 3/12/2009 3:49:19 PM

Rectifiers 109

π /6
3n 2Vm2
=
π RL ∫ cos 2 θ ⋅ dθ
−π /6
2 2 π /6
3n Vm
=
2π RL ∫ (1 + cos 2θ ) ⋅ dθ
−π /6
π /6
3n 2Vm2 ⎛ π /6 sin 2θ ⎞
= ⎜θ + ⎟⎟
2π RL ⎜⎝ −π /6 2 −π /6 ⎠

3n 2Vm2 ⎛ π 3⎞
= ⎜ + ⎟
2π RL ⎝ 3 2 ⎠

n 2Vm2 ⎛ 1 3 3 ⎞
Po = ⎜ + ⎟ (3.30)
RL ⎝ 2 4π ⎠

Referring to Eqs. (3.28) and (3.29), one can observe that the output power Po is
Po = VLrms I Lrms (3.31)
Referring to Figure 3.11, it can be seen from the representative D1 current waveshape that each diode carries
the load current during two ripples in a period or carry an equivalent of one of the six load current ripples
in half a period. The D1 diode current is shown in Figure 3.11. The average and the rms values of the diode
currents are given as
π /6
1 nVm π /66 nV
I Dav =
π RL ∫ nVm cos θ dθ =
π RL
sin θ − π /6 = m
π RL
(3.32)
− π /6

nVm 1 3
I Drms = + (3.33)
RL 2 3 2π

3.3 Capacitor Input Filter

T he capacitor input filter is an inexpensive and one of the most popular filters that is used for almost all
applications and loads that require a DC bus. Capacitor input filters are the most volumetrically effi-
cient means of filtering rectified sine waves and storing energy. The schematic of the capacitor input filter is
shown in Figure 3.12. The capacitor charges up to the peak value of the input voltage and tries to maintain
this value as the full-wave rectified input drops to zero. The capacitor will discharge through the load until
the input full-wave rectified voltage again increases to a value greater than the capacitor voltage. At this
point, the diode rectifier will again recharge the capacitor.
The ripple voltage across the filter capacitor is a function of the filter capacitance value, the input fre-
quency and the load current. Considerable importance is given to calculations of ripple amplitude because
this parameter influences other design parameters for downstream power conversion devices. In the case of
linear power supplies, the minimum capacitor voltage at low line (i.e., minimum input voltage) must be
equal to the output voltage plus the minimum voltage which the pass regulator can tolerate while maintain-
ing a regulated output. At high line, the voltage across the pass regulator increases and the regulator must
dissipate substantial power.

Chapter 03.indd 109 3/12/2009 3:49:20 PM

110 Power Electronics

1φ
or C RL Vo
3φ

AC
input
Rectifier

Figure 3.12 Capacitor input filter.

In switch-mode power supplies, higher ripple voltage may be tolerated since the pulse-width modulator
will correct for the DC bus ripple variations without an increase in power dissipation. The ﬁlter capacitance
may be chosen (for a desired output ripple) or the output ripple may be decided (for a desired capacitance).
In many cases, the power supply can operate with a 25% peak-to-peak ripple voltage across the input ﬁlter
capacitor and a line variation of ±15%.

Design of Capacitor Input Filter Rectifier

Figure 3.13 shows a single-phase full-wave bridge rectifier with capacitor input filter. This is the most
common type of AC-to-DC converter used in most applications. The design of the circuit of Figure 3.13 is
now discussed in detail.
The input filter capacitor C determines the peak-to-peak ripple voltage component DVr. At low-line
voltage, DVr determines the minimum input voltage Vm-min which is an important design consideration and
defines the transformer turns ratio required to achieve the specified output voltage at maximum load condi-
tions or maximum duty cycle of any downstream-controlled converter or inverter.
If the input filter capacitor is too small, the resulting large ripple voltage will require the post regulator
to have a large line-regulation requirement. This would result in poor transformer utilization and higher
ratings for the post regulator power devices. If the input filter capacitor is larger than necessary, it will not
only cost more but the recharging capacitive current pulses drawn from the line will also be narrower and

id i

D1 D3 ic io

Vmsin wt RL Vo

D2 D4

Figure 3.13 Single-phase rectifier–capacitor input filter.

Chapter 03.indd 110 3/12/2009 3:49:20 PM

Rectifiers 111

larger in amplitude. This adversely affects the line power factor and also increases the conducted electromag-
netic interference (EMI). The higher rms input line current causes increased losses in the line, diodes and
filter capacitor, thus decreasing the efficiency and reliability. Therefore a reasonable rule of thumb is to com-
promise on a ripple voltage of about 15–30% of the minimum peak line voltage resulting in acceptable
capacitor size, weight and cost. It is expected that the downstream converter or inverter will take care of the
ripple and line regulation.
Figure 3.14 shows the voltage and current waveforms for the rectifier-filter circuit of Figure 3.13. The
capacitor charges only during the period corresponding to the angle δ shown in Figure 3.13. During the
remaining period the capacitor is discharging to the load. The current waveforms are approximated to
pulsed waveforms as shown in Figure 3.13 without loss of generality from the point of view of design of
diodes and capacitor as the current rating obtained for the components would be a conservative value.
During the positive cycle the diode pair (D1, D4) conducts and during the negative cycle the pair (D3, D2)
conducts. The capacitor gets fully charged after four to five cycles. Referring to Figure 3.14, it can be

V1
Vo
V2 ΔVr

0
wt
a p−a
i
Im

0
wt
id

0
wt

Figure 3.14 Waveforms of voltage and currents for C-filter rectifier as shown in Figure 3.13.

Chapter 03.indd 111 3/12/2009 3:49:20 PM

112 Power Electronics

observed that diodes D1 and D4 will get forward-biased when the input voltage increases more than V2.
Similarly, diodes D3 and D2 get forward-biased when the input voltage goes below V2 in the negative half-
cycle. Only when the rectifier diodes are forward-biased will there be a current flow to charge the capacitor C.
The charging up of the capacitor is reflected as an increase in voltage across the capacitor as indicated in the
waveform shown in Figure 3.14. Once the capacitor charges to V1, the input voltage begins to fall wherein
the rectifier diodes will become reverse-biased. Now the capacitor discharges into the load with average load
current Io and as a consequence the output voltage Vo will decrease as shown. This process repeats cycle by
cycle resulting in the output voltage to have a ripple of DVr. Observe from Figure 3.14 that the capacitor
charging current flows only during period α as indicated.

Rectifier Component Selection

In order to select the components of the rectiﬁer, the following parameters must be speciﬁed a priori.
1. Output voltage, Vo.
2. Output ripple, DVr.
3. Maximum load power, Po.
4. Nominal input rms voltage, Vin,rms ± % tolerance.
5. Input voltage variation tolerance, %tol.
6. Frequency of input, fs.
At steady state, the energy gained by the capacitor is equal to the energy lost to the load. In a half-period, the
capacitor energy that is given to the load εo is
1
εo = C (V12 − V2 2 ) (3.34)
2
The output load energy in a half-period of T/2 when the capacitor discharges is given as
⎛π −α ⎞ T
εo = Po ⎜ ⎟ (3.35)
⎝ π ⎠ 2
From Eqs. (3.34) and (3.35), the output capacitor value is given as
π −α 2 Po
C= (3.36)
π (V1 − V2 2 ) f r
2

where fr is the frequency of the rectified waveform and is equal to 2/T. Equation (3.36) is the capacitor selec-
tion equation. With reference to this equation, the following comments are important. If fs is the source or
line frequency, then
1. for single-phase half-wave rectifiers, fr = fs = 50 Hz;
2. for single-phase full-wave rectifiers, fr = 2fs = 100 Hz;
3. for three-phase full-wave rectifiers, fr = 6fs = 300 Hz.
The output power Po is a design specification that is determined from the load requirements. V1 is the peak
value of the input voltage. It should correspond to the minimum peak value the input voltage can reach.
This is because the capacitor should be selected such that it is capable of providing the specified output
energy even under low input voltage situations. Thus,
V1 = Vm − min (3.37)

Chapter 03.indd 112 3/12/2009 3:49:21 PM

Rectifiers 113

where
⎛ %tol ⎞
Vm − min = 2Vin-rms ⎜ 1 −
⎝ 100 ⎟⎠
V2 is given as
V2 = V1 − ΔVr (3.38)
where DVr is the peak-to-peak ripple voltage and is usually specified at 15–30% of the minimum input
voltage.
In Figure 3.14, the currents through the diodes and the capacitors are shown approximated as pulse cur-
rents of peak amplitude Im and conducting for a period corresponding to the angle α. As the pulse approxi-
mation of the current waveshapes totally enclose the actual current waveshapes any component selection
(diode and capacitor) made based on the pulse current waveshapes will definitely work for the actual wave-
shapes also. It should be noted that approximations based on such engineering judgment will be encoun-
tered frequently in circuit design. Such approximations will enable one to obtain close form solutions to
many design parameters without compromising on the component ratings.
The peak, average and the rms currents that flow through the diodes and the rms current through the
capacitor are required to the calculated so that properly rated diodes and output capacitor can be selected.
Referring to Figure 3.14, it can be observed that
V2 = V1cos α
and therefore
V
α = cos −1 2 (3.39)
V1
Let Io be the average value of the load current, then
P
Io = o (3.40)
Vo-avg
where Vo,avg = Vo-avg = (V1 + V2 ) / 2.
Referring to Figure 3.14, the current i flows through the capacitor and also through the load. As the
capacitor current has zero average value under steady state, the load current Io is the average value of the
current i. Therefore,
⎛α⎞
Io = Im ⎜ ⎟ (3.41)
⎝π⎠
Substitution of Eq. (3.40) into Eq. (3.41) and re-arranging gives
2π Po
Im = (3.42)
α (V1 + V2 )

Diode Selection
1. The diode peak current rating should be greater than the value calculated by Eq. (3.42).
2. The rms value of current through diodes is given by I d,rms = I m α / 2π .
3. The average value of current through diodes, Id,avg = Ima /2p.
4. The PIV rating for the diodes should be greater than the maximum peak value that the input voltage
will reach. This is given as

Chapter 03.indd 113 3/12/2009 3:49:21 PM

114 Power Electronics

⎛ %tol ⎞
PIV > V1− max = 2Vin-rms ⎜ 1 +
⎝ 100 ⎟⎠
5. The average and the rms currents through the diodes are needed to estimate the power dissipated in the
diodes. This will reﬂect in the selection of heat sinks for the diodes.

Capacitor Selection
1. The capacitor value selected should be greater than that calculated by Eq. (3.36). As the capacitor
charges up only in one direction, the voltage across the capacitor is unidirectional. Therefore an electro-
lytic capacitor should be selected.
2. The rms value of current through capacitor is

α ⎛ π −α ⎞
I Crms = ( I m − I o )2 + I o2 ⎜ (3.43)
π ⎝ π ⎟⎠
Equation (3.43) is obtained by referring to Figure 3.14. It can be observed that (Im – Io) current flows
through the capacitor during a out of p periods and Io value of current flows through the capacitor
during the remaining p − a out of p periods. Squaring the currents and integrating between the angle
limits mentioned above and taking the mean over p gives ICrms. The rms value of the capacitor current
is used to select the equivalent series resistance (ESR) rating for the capacitor.
3. The voltage rating of the capacitor should be greater than V1-max.
Remarks on the rectifier–capacitor input filter design:
1. The specifications for the design of the rectifier–capacitor input filter circuit consists of input voltage
minimum (Vm-min) and maximum (Vm-max) limits, desired output voltage peak-to-peak ripple (DVr),
output power (Po) and the input frequency (fs ).
2. The capacitor value is evaluated according to Eq. (3.36). It is essential to take care that the capacitor
value is evaluated for the minimum input voltage value.
3. The capacitor is an electrolytic capacitor as the voltage it supports is unidirectional. The voltage rating
of the capacitor selected should be greater than Vm-max. Either an aluminum electrolytic or a tantalum
capacitor is normally chosen.
4. The rms current rating required for the capacitor is calculated using Eq. (3.43). From the manufacturers’
datasheets, a capacitor having an rms current rating that is 1.5 to 2 times that calculated is
selected.
5. The average, peak and rms current rating of the rectifier diodes are calculated using Eqs. (3.40)–(3.42).
From the manufacturers’ datasheets, a diode having current ratings that are 1.5 to 2 times the values
calculated is selected.
6. The PIV seen by the rectifier diodes is Vm-max. Therefore, diodes having PIV ratings that are greater than
the value of Vm-max should be selected.
One should note that the design of rectifier-filter circuit with three-phase inputs is similar to that outlined
above. In the case of three-phase inputs, the rectifier is a three-phase full-wave bridge rectifier as shown in
Figure 3.15. The output Vo charges to the peak value of the line-to-line voltage. If Vm is the peak value of the
line-to-neutral voltage, then Vo will charge up to 3Vm . The capacitor design equation is same as Eq. (3.36)
except that fr is now six times fs. Thus, it is evident that for a given output power and peak-to-peak ripple,
the size of the capacitor is smaller with three-phase input source than that for a single-phase input source.

Chapter 03.indd 114 3/12/2009 3:49:21 PM

Rectifiers 115

3f R
line-to-
Y C R Vo
line
voltages B

Figure 3.15 Three-phase capacitor-filter rectifier circuit.

Many products are made for the global markets. The two most common types of mains input that the
AC–DC converter may be used with are 115 V and 230 V line inputs. A circuit diagram of a universal or
dual input range rectifier filter is shown in Figure 3.16. The charges on the capacitors C1 and C2 are balanced
by equalizing resistors connected across each capacitor. For 230 V line operation, the switch S is set at
position “b”. The input rectifiers are now configured as a normal full-wave bridge circuit. For 115 V line
operation, the switch S is set at position “a”. The input rectifier is now configured as a voltage doubler such
that Vo will have the same value as though operating from a 230 V line. While it is technically possible to
operate the input section as a bridge at both 230 V and 115 V, the post regulator, which in most cases is a
switching regulator, will have to be designed to operate over a much larger input voltage swing which would
significantly increase the cost. Therefore, by adopting the above strategy as indicated in Figure 3.16, the post
regulator needs to be designed only for 230 V line input.

io
C1

b
Vm sinwt C RL Vo
a S

Figure 3.16 Dual input range rectifier filter.

Chapter 03.indd 115 3/12/2009 3:49:21 PM

116 Power Electronics

Hold Time
Let Vh be the minimum voltage required by the load/post regulator to function. This implies that for Vo
greater than Vh, the load/post regulator will function as per specification. However, when Vo becomes less
than Vh, the load will not get the required minimum voltage and therefore will not become operational.
When the input power goes OFF, the time taken by the rectifier output voltage to come down to Vh from
the moment the input power went OFF is called the hold time (th). The concept of hold time can be visual-
ized from Figure 3.17.
If the rectifier output is powering up a digital controller board or any intelligent microcontroller or
microprocessor or digital signal processor board, during the hold time the digital controller will perform safe
shut down operations. Therefore, sometimes the output capacitor needs to be calculated based on the mini-
mum hold time requirement of the load. The worst case hold time occurs when the input mains voltage is
at a minimum, that is, Vm-min and the power goes OFF when the output capacitor voltage is at V2 value.
During the hold time, the output capacitor must supply a maximum amount of energy given by
ε h = Pot h (3.44)
1
ε h = C (Vm- min 2 − Vh2 ) (3.45)
2
where
⎛ %tol ⎞
Vm- min = 2 ⋅Vin-rms ⎜ 1 −
⎝ 100 ⎟⎠
and Vh is specified as per load requirements. From Eqs. (3.44) and (3.45) the capacitor value for a specified
hold time is given as
2 Pot h
C= (3.46)
Vm-min − Vh2
2

The greater of the two values, as calculated from Eqs. (3.36) and (3.46), should be used for selection of the
capacitor value such that both the ripple and hold time requirements are met.

Power
OFF

Figure 3.17 Illustration of hold time.

Chapter 03.indd 116 3/12/2009 3:49:22 PM

Rectifiers 117

Turn-ON Currents and Surge Limiting

In a capacitor input filter, the current flow is quite narrow and sharp (as indicated in Figure 3.14). If the AC
power is turned ON at or just before the peak of the input voltage waveform, the peak current is limited
only by line resistance (Rline), ESR of the capacitor(RESR ), rectifier diode dynamic resistance and the input
line and/or the leakage reactance of the transformer if present (XL).
If an input side transformer is used, then the total equivalent resistance of the transformer looking into
the secondary is
⎛N2⎞
Rsec + ( Rline + Rpri ) ⎜ s2 ⎟
⎜⎝ N p ⎟⎠

where Rsec and Rpri are the winding resistances of the secondary and primary windings of the transformer,
respectively; Rline is the line or conductor track resistance of the primary side; Ns and Np are the secondary
and the primary number of turns, respectively. The total series resistance Rs is given as

N s2
Rs = Rsec + ( Rline + Rpri ) + 2rd + RESR (3.47)
N p2
where rd is the dynamic resistance of the diodes. During the capacitor charge duration, two of the four
diodes of the full-bridge will conduct. Therefore, two diode dynamic resistances are included in series.
The total series inductance Ls is given as
⎛N2⎞
Ls = Lline ⎜ s2 ⎟ + Lleakage (3.48)
⎜⎝ N p ⎟⎠

Lline is the conductor inductance on the primary or the line side and Lleakage is the equivalent transformer
leakage inductance as seen from the secondary. It should be noted that if the transformer is not present then
Rsec and Rpri values will be zero and Ns/Np ratio will be unity in Eqs. (3.47) and (3.48). The rectifier–capacitor
circuit along with the series impedance is shown in Figure 3.18.
The total source inductance Ls is a function of the inductance in the input line and the leakage reactance
of the transformer referred to the secondary. Figure 3.18 shows an off-the-line bridge rectifier with the AC
voltage applied when its voltage value corresponds to the maximum. The dynamic equation during the time
the capacitor is charging is given as

di 1
dt C ∫
Vac = Rsi + Ls + idt (3.49)

From the above equation it may be observed that the startup current i drawn from the source is dependent
on the instantaneous amplitude of the input source at startup, the equivalent series circuit resistance Rs, the
equivalent series circuit inductance Ls and the output capacitor C. At startup as the capacitor voltage is not
yet built up, the current is primarily dependent on the component values of Rs and Ls. In off-the-line bridge
rectifier circuits wherein there is no input transformer, the startup current surges could be very high in low
Ls circuits. Especially for high-power circuits, the line inductance is very small due to the use of wide con-
ductors. In such cases, the startup surge current will depend primarily on only Rs. This could be detrimental
to the components of the rectifier–capacitor circuit. However, in many cases, the inductance of an EMI
filter at the input provides sufficient surge protection for the off-the-line rectifier circuit. The startup peak

Chapter 03.indd 117 3/12/2009 3:49:22 PM

118 Power Electronics

i
Ls io
Rs

Vm sinwt C RL Vo

(a)

0 t
i First
cycle
inrush

(b)

Figure 3.18 (a) Rectifier filter with source inductance and resistance; (b) inrush current
in the first cycle.

current may be reduced by a factor of 10 if the power supply is turned ON at the zero crossing of the input
wave, as compared to turning ON the power supply at the peak of the input wave.
The substantial startup current surge may be more economical to limit than choosing higher current
diodes. Figure 3.19 shows few methods of limiting the startup surge current. In the step-start circuit shown
in Figure 3.19(a), Rs is in series with R1 through which current ﬂows when the input switch is closed,
thereby limiting the inrush current. The energizing time of contactor, K1, is typically from one-to-three
cycles of the input frequency which allows the ﬁlter capacitor to become charged, after which R1 is shorted
by K1 contacts to eliminate power dissipation and voltage drop due to inclusion of R1.

Chapter 03.indd 118 3/12/2009 3:49:22 PM

Rectifiers 119

A negative temperature co-eﬃcient power thermistor, as shown in Figure 3.19(b), can also be used to
limit the inrush currents. At turn-ON, the “several ohms” resistance in TH1 limits the inrush current which,
in turn, dissipates power in the thermistor. This power dissipation raises the temperature of the device and the
resistance drops to a low value for normal operation. However, the thermal time constant of the thermistor
must be considered. If a power supply has been operating at near no load for some time, the resistance of TH1
will be higher than at full load. When full load is applied, the voltage drop across TH1 will cause the output
to drop substantially or in the case of a regulated supply, the output may go out of regulation. If the power
supply is operating at full load where TH1 is very low in resistance and a short power interruption occurs
(long enough for the input ﬁlter capacitor to discharge), then a high inrush current will occur when the mains
voltage returns. This is because the thermistor resistance has not yet recovered to its high cold state value.
R1

C RL Vo
k1

(a)

TH1

C RL Vo

(b)

Soft start
circuit C RL Vo

(c)

Figure 3.19 Surge current-limiting circuits.

Chapter 03.indd 119 3/12/2009 3:49:23 PM

120 Power Electronics

D1 D3
C RL
Vo

D5
Vm sinwt
D6
R1
Q1

D2 D4
R2 C1

(d)

Figure 3.19 Continued.

The circuit shown in Figure 3.19(c) utilizes a TRIAC Q1. The soft-start control circuit is phase con-
trolled at turn-ON to limit inrush current. Initially, the conduction period of each half-cycle is very short,
but then increases with time until full conduction is reached. Three precautions should be observed with
this circuit. First, the conduction period should increase linearly every cycle at turn-ON to prevent a DC
component to be applied to the transformer primary if a transformer is used. In such cases, it may be better
to locate the TRIAC on the secondary side. Second, the control circuit should have mains-interruption sens-
ing, with a time constant sufficient to permit soft-start operation when the mains again returns; otherwise,
a high inrush current will occur. Third, the control circuit should provide continuous turn-ON signal to Q1
during desired full conduction. Otherwise, Q1 will turn-OFF when the input current, which is discontinu-
ous, goes to zero.
An input rectifier and capacitor filter is shown in Figure 3.19(d) with an N-channel power MOSFET
inserted in the DC return line. Diodes D1–D4 rectify the input to charge C and supply power to RL when
Q1 is ON. The MOSFET has two main advantages over a bipolar transistor. First, the high input impedance
of the gate allows high-resistance values for the biasing resistor, thus minimizing power dissipation. Second,
the MOSFET is immune to forward-biased secondary breakdown, although the safe operating area (SOA)
must still be observed. At turn-ON, C1 charges exponentially through R1 to a final steady-state value deter-
mined by R2/(R1 + R2). C1 charges to a few volts before the gate threshold voltage is reached, at which time
Q1 begins to conduct in the active region and act like a resistor. C reaches full charge in a few cycles, deter-
mined by the time constant of R1R2C1/(R1 + R2). The addition of diodes D5 and D6 serves to decouple C1
from C during operation and allows C1 to discharge through R2 when input power is removed. If D5 and D6
were omitted and R1 were connected to C, the voltage across C (as C discharges) would maintain a charge
on C1 even though input power is momentarily removed. Thus, when input power is again applied, the
charge on C1 could be sufficient to bias Q1 into full conduction. Complete discharge of C1 during power
interruptions could be achieved by paralleling C1 with a PNP transistor such that the base is biased by a
voltage divider from D5, D6 to DC return. With the power ON, the transistor would be reverse-biased but
with power OFF, the transistor would conduct to rapidly discharge C1. Inserting a small resistor between the
source terminal of Q1 and the negative terminal of C1 can act as a current limiter. As source current increases,
Vgs decreases thus increasing Vds thereby limiting the inrush current.

Chapter 03.indd 120 3/12/2009 3:49:23 PM

Rectifiers 121

3.4 Power Factor

P ower factor ( pf ) gives the quality measure of a circuit. If the pf is unity, the input power drawn from the
source will be the load power and the power that gets dissipated in the various components. However, if
the pf is low, the input source should be rated for a much higher power than the required load power. This
would imply higher line losses resulting in lower efficiencies. Referring to Figure 3.14, the input voltage
waveform is sinusoidal, but the current is not. It should be noted that the average current required by the
load is Io but the peak current demand from the source is Im which is much higher than Io. This implies a
low pf for the rectifier–capacitor circuit. Further, as the line current flows only for a period corresponding to
a, there is a voltage drop in the line impedance only during this period. This leads to distortion in the input
applied voltage. For such cases, what is the pf ? And how is it computed and measured?
Consider a voltage source of an arbitrary waveshape that is periodic with period T. It is connected to a
pure resistive load R as shown in Figure 3.20. The current waveshape will exactly resemble the voltage wave-
shape. The entire power drawn from the source is given to the load R. This means that no power is used for
kinetic storage (in inductor) or potential storage (in capacitor) or returned back to the input. The power that
is given to load R is called the active power and the power that is either stored or returned back to the input
is called the reactive power. In the case of the circuit as described above the reactive power is zero. The power
that is given to the resistive load, Pres, is given by
T
1
T ∫0
Pres = v × i × dt (3.50)

where v and i are the instantaneous values of the current and voltage across the load resistor R.
If the input source is a voltage source, the reference waveshape for the source currents is that correspond-
ing to the voltage source, and if the input source is a current source, the reference waveshape for the source
voltage is that corresponding to the current source. For now, consider that the input source is a voltage
source and its waveshape is deﬁned. Let this voltage source of deﬁned waveshape be connected to an arbi-
trary load. The power delivered from the source is given as
T
1
T ∫0 i L
Pload = v × i × dt (3.51)

where vi is the instantaneous value of input source voltage that is across the arbitrary load; iL is the instanta-
neous value of the current flowing through the source for the specified arbitrary load.
Measure or estimate the peak current Im that flows from the source for the specified load. Replace the
load with a resistive load Rref that has a value which results in the same peak current through the source and
load. For a resistive load, the peak current occurs at the peak of the input voltage waveshape, Vm. This would

V R

Figure 3.20 A voltage source connected to a resistive load.

Chapter 03.indd 121 3/12/2009 3:49:24 PM

122 Power Electronics

be the reference load for the input voltage source for a specified peak current Im. Thus the value of the refer-
ence load resistor R that should be selected for Im is
Vm
Rref = (3.52)
Im
where Vm is the peak of the input source voltage; Im is the measured or estimated peak current flowing
through the source for the specified arbitrary load.
The power that is delivered from the input source with the reference resistive load as determined above
is given as
T
1
T ∫0 i R
Pref = v × i × dt (3.53)

where Pref is the reference power delivered from the input source with the reference load; vi is the instanta-
neous value of input source voltage that is across the arbitrary load; iR is the instantaneous value of the cur-
rent ﬂowing through the source for the reference resistive load.
The pf is deﬁned as the ratio of the power delivered to the arbitrary load to the reference power delivered
to the reference resistive load wherein the same input peak current is maintained. Thus pf is given by
T T
1
T ∫0 i L ∫ vi × iL × dt
v × i × dt
Pload
pf = = T
= T0 (3.54)
Pref 1
T ∫0 i R ∫ vi × iR × dt
v × i × dt
0

The pf gives a measure of the departure of the arbitrary load from the resistive load. If pf is unity, the arbi-
trary load is equivalent to the resistive load. If pf is less than unity, it implies that there are either kinetic or
potential energy storage components in the arbitrary load.

EXAMPLE 3.1 RLC Load

Consider a series RLC load connected to a sinusoidal voltage source as shown in
Figure 3.21.

i R L

V C

Figure 3.21 Series RLC load.

Chapter 03.indd 122 3/12/2009 3:49:24 PM

Rectifiers 123

The current waveform leads or lags the voltage waveform by an angle q. One
can apply Eq. (3.54) to obtain the pf for this RLC load supplied from a sinusoidal
voltage source. Here
v i = Vm sin(ω t )
iL = I m sin(ω t − θ )
where
⎛ ωL⎞ ⎛ 1 ⎞
θ = tan −1 ⎜ ⎟ − tan −1 ⎜
⎝ R ⎠ ⎝ ωCR ⎟⎠
The reference load resistor Rref is given by
Vm
Rref =
Im
The pf for the series RLC load can be estimated using Eq. (3.54). This is given by
T T

∫ Vm sin(ωt )I m sin(ωt − θ )dt Vm I m ∫ sin(ωt )sin(ωt − θ )dt

pf = T 0 = 0
T
= cos(θ )
∫ Vm sin(ωt )Vm sin(ωt ) / Rref ]dt Vm I m ∫ sin(ωt )sin(ωt )dt
0 0

EXAMPLE 3.2 Rectiﬁer–Capacitor Filter Load

Consider the rectifier–capacitor filter load that is supplied by the sinusoidal voltage
source. Here
v i = Vm sin(ω t )
iL is the discontinuous waveform i as shown in Figure 3.14. This current flows every
half-cycle for a period corresponding to a. The peak value Im of this current wave-
form can be measured using an oscilloscope.
From the estimate of the peak current that flows through the input source, the
reference load resistor Rref is given by
V
Rref = m
Im
and then
iR = I m sin(ω t )
From Eq. (3.54), the pf for the rectifier–capacitor filter load can be obtained as follows:
T
1
T ∫0 m
V sin(ω t )idt
Po + Ploss 2( Po + Ploss ) (3.55)
pf = T
= =
1 Vm I m / 2 Vm I m
T ∫0 m
V sin(ω t )I m sin(ω t )dt

Chapter 03.indd 123 3/12/2009 3:49:24 PM

124 Power Electronics

where Ploss is the consolidated losses of the diodes, ESR of capacitor and the transformer
losses if transformer is present. In higher power circuits where the losses are negligible
compared to the output power, the pf for the rectiﬁer–capacitor ﬁlter circuit reduces to
2 Po
pf = (3.56)
Vm I m
The value of Im has to be measured. However, one can obtain an approximate esti-
mate of the pf by using the relationship for Im given by Eq. (3.42) in Eq. (3.56):
α (V1 + V2 )
pf =
πV m
where
⎛V ⎞
α = cos −1 ⎜ 2 ⎟
⎝ V1 ⎠

Observe from the above representation that as the output ripple decreases, the time duration for which the
diodes conduct, a, will reduce. This implies that for the same output power, the current peak Im will be
larger, resulting in lower pf. The pf can be improved by
1. introducing an inductor in series;
2. increasing the diode conduction angle, by-means of controlled switching of power switches. This is
called the unity pf converter.
The former method will be discussed in the next section. However, the latter method will be discussed in
Chapter 10 after discussion of the control principles.

3.5 Rectifier–LC Filter

T he rectifier–LC filter consists of an inductor that is placed between the rectifier and the capacitor filter.
Since current cannot change instantaneously in the inductor, inrush currents at turn-ON are reduced.
Further, as the inductor has a smoothening effect on the current, the output voltage ripple is reduced as com-
pared to the rectifier–capacitor filter. Most importantly, introduction of the inductor widens the conduction
angle of the diodes, thereby improving the pf significantly. Alternately one may argue that the capacitor is a
potential energy storage element and the inductor being a kinetic energy storage element offsets the effect of
the capacitor such that the input source sees an impedance that is closer to the resistive load.
However, the major drawback is the inductor itself. The inductor will have to be designed for the supply
frequency of 50 Hz. This will make the size and cost of the inductor prohibitively large. This significant
drawback has prevented this topology from becoming popular in commercial equipments.
A single-phase full-wave rectifier with LC filter is shown in Figure 3.22(a). During the peak portions of the
voltage waveform, energy is stored in the inductor and during the valley portion of the voltage waveform, it is
transferred to the capacitor and load. The waveforms for the rectifier–LC filter are shown in Figure 3.22(b).
Referring to Figure 3.22(b), the rectified waveform contains an average voltage component and an AC
component. As the rectified waveform has even wave symmetry, it can be deduced that the AC component
contains only even harmonics. The Fourier series of the rectified waveform is given as
2Vm ⎛ 2 2 2 ⎞
Vrect =
π ⎜⎝ 1 − 3 cos 2ω t − 15 cos 4ω t − 35 cos 6ω t − …⎟⎠ (3.57)

Chapter 03.indd 124 3/12/2009 3:49:24 PM

Rectifiers 125

L i

Vm sinwt
Vo = Vdc

(a)

V
Vm V0

2Vm/π

0
(b)

V0
Vm

2Vm /π

0 Idc-min i0
(c)

Figure 3.22 (a) Rectifier–LC filter circuit; (b) voltage waveform; (c) output voltage versus load.

where Vm is the peak value of the rectiﬁed sinusoidal voltage; w = 2pf is the fundamental radian frequency
and f is the line frequency.
The rectiﬁed waveform Fourier component representation given in Eq. (3.57) can be re-written as
Vrect = VDC-part + V AC-part (3.58)

Chapter 03.indd 125 3/12/2009 3:49:25 PM

126 Power Electronics

where
2Vm
VDC-part = (3.59)
π

2Vm ⎡ ∞ ⎛ −2 ⎞ ⎤
V AC-part = ⎢ ∑ ⎜ 2 ⎟ cos nω t ⎥ (3.60)
π ⎢⎣ n = 2 ⎝ n − 1⎠ ⎥⎦

where n is the even harmonic number.

The LC-filter circuit is an averaging circuit or a low-pass circuit. It will remove the AC components and
pass only the DC part. Therefore, the output voltage Vo primarily contains only the average or DC part of
the rectified waveform.
2Vm
VDC = VDC-part = (3.61)
π
The AC part of the rectified waveform gets attenuated due to the capacitive reactance. Thus the AC part of
the rectifier waveform that appears at the output is given as
⎛ X C RL ⎞
Vripple = V AC-part ⎜ ⎟ (3.62)
⎝ X L + X C RL ⎠
Thus
Vo = VDC + Vripple

For a good LC-filter circuit, XC << RL and XC << XL. Therefore, the output ripple voltage given in Eq. (3.62)
can be approximated as
⎛X ⎞
Vripple = V AC-part ⎜ C ⎟ (3.63)
⎝ XL ⎠
The discussion above assumes that the current through the inductor is continuous. The desired output voltage
ripple is achievable only if the inductor current is continuous. As the load resistance RL increases, the DC or
the average part of the current through the inductor that flows through RL reduces. As RL is further increased
towards open circuit, the inductor current gradually reduces and becomes discontinuous. When this happens,
the output voltage will tend to rise toward the peak input voltage, Vm, as shown in Figure 3.22(c). Current
Idc-min is the load value at which the inductor current becomes discontinuous and each rectifier diode con-
ducts for less than 180o. The load Idc-min is the minimum load current for which the inductor is in continuous
conduction.
If the minimum load is specified, then the inductor value can be designed such that the inductor current
is continuous even at minimum load and the output voltage is as given by Eq. (3.61). The inductor has a
DC component and an AC component of current. For the current to be continuous, the DC component
2Vm / π RL-max must be equal to or greater than the AC component. As the capacitive reactance XC << XL,
the AC component of the inductor current that comprises predominantly of the second-harmonic compo-
nent is 4Vm / 3π X L . Thus
2Vm 4Vm
≥ (3.64)
π RL 3π X L

Chapter 03.indd 126 3/12/2009 3:49:25 PM

Rectifiers 127

where X L = 2ω L . From the above inequality, the following inductor value selection criterion is obtained.
RL-max
L≥ (3.65)
3ω
where RL-max corresponds to the load resistance value at minimum load. The input source considered for the
LC-filter circuit is a single-phase sinusoidal source. On rectification, the number of rectified pulses per
period is two. If a three-phase source is rectified then the number of rectified pulses per period is six. If such
a rectified output is fed to the LC filter, then the general equation for inductance value of polyphase rectifi-
ers can be obtained along similar lines as discussed and is given as
2 RL-max
L≥ (3.66)
p( p 2 − 1)ω
where p is the number of rectified pulses per fundamental line period.
From Eq. (3.63) it can be observed that a larger L will result in a smaller output voltage ripple. From
Eq. (3.66) it can be noted that when the load is light, RL is large and a large value of L is needed if the ripple
is not to be excessive. This means that the series inductance should have a large value at no load and may
be allowed to decrease as the load increases. Reactors can be designed wherein the inductance decreases as
the DC current through inductor increases by making use of the non-linear B–H magnetic characteristic of
the inductor core material. This can be a solution to the bulky and expensive constant inductance chokes
that need more iron to avoid saturation at larger currents.
Alternately, a bleeder resistor could be added across the output filter capacitor such that the minimum
load is guaranteed. In this case, the power dissipation and rating of the bleeder resistor and reduction in over-
all efficiency must be considered. The value of the bleeder resistor for a single-phase full-wave rectifier is
VDC
RB = (3.67)
I dc-min
Referring to Figure 3.22(c), the current Idc-min is the value of the load current at which the current in the
inductor becomes discontinuous or in other words the DC component of the inductor current is equal to
the peak of the AC component of the inductor current. At still lighter loads, the DC component becomes
lesser than the peak AC component and leads to discontinuous currents in the inductor. Therefore, by
introducing a bleeder resistor RB across the output capacitor C the rectifier filter will always see a minimum
load that is just enough to make the current in the inductor continuous. From Eq. (3.65) it can be argued
that the bleeder resistor that will provide the minimum load for continuous conduction of the inductor
current is
RB = 3ωL (3.68)
and for polyphase input sources, the general equation for the bleeder resistor is
p( p 2 − 1)ω L
RB = (3.69)
2
where p is the number of rectified pulses per fundamental line period.

Output Ripple
Equation (3.63) gives the amount of ripple voltage in the output. The inductor has a high reactance and
the capacitor has a low reactance at the harmonic frequencies and the following discussion considers only

Chapter 03.indd 127 3/12/2009 3:49:25 PM

128 Power Electronics

the predominant second-harmonic eﬀect, with negligible error in analysis. As the second harmonic is the
dominant eﬀect with respect to the ripple voltage, the ripple waveshape can be considered to be sinusoidal.
Referring to Eqs. (3.60) and (3.63), the rms value of the output ripple voltage is given as

4Vm X C Vm
Vripple-rms = = (3.70)
3 2π X L 3 2πω 2 LC
The preceding equation provides the LC product, but individual component values must still be determined.
For a speciﬁed value of the minimum load, the value of L can be calculated. From the LC product, the value
of C can then be estimated.

Turn-ON Current
An important consideration with inductor input filters is the frequently under-damped nature of the circuit
at turn-ON. This is especially true of soft-start switch-mode power supplies because the input filter capacitor
will charge to a voltage higher than the peak input voltage and the “downstream” switching transistors will
experience a higher-than-normal voltage when switching commences. This effect has to be taken into
account while designing post regulators.

Design Summary
In the design of the rectifier–LC filter circuit, the input voltage, the minimum load requirements and the
output rms ripple are specified. Based on these inputs:
1. The LC value is evaluated using Eq. (3.70).
2. The value of L for minimum load is calculated using Eq. (3.65).
3. The value of C is calculated from LC product and the value of L. Ensure that XC << XL at the second
harmonic.
4. The rectifier diodes should be rated to carry the inductor current. Considering the second harmonic as
the dominant effect, this is given as

2Vm 4Vm
Id = +
π RL-min 6πω L

5. The PIV ratings for the diodes should be greater than Vm.

3.6 Controlled Rectifiers

I n the previous sections, it is seen that the rectiﬁed DC output voltage is dependent on the amplitude of
the AC input voltage and the load. The output voltage is therefore unregulated. As the input voltage
varies, so does the output voltage. The output voltage increases as the load approaches an open circuit. This
section presents phase-control topologies that may be employed to provide a regulated output. Line and
load regulation are achieved by using thyristors family of power switches to control the conduction angle of
the sine wave input in response to some desired control. TRIACs are used to control AC load voltages, as in
light dimmer assemblies. For high-power AC loads, parallel back-to-back SCRs can be used. Power supplies
utilize rectiﬁers and TRIACs or SCRs as the control element to provide a desired DC output from single-
phase or three-phase inputs.

Chapter 03.indd 128 3/12/2009 3:49:25 PM

Rectifiers 129

Single-Phase Power Circuits

Few topologies of single-phase power circuits are shown in Figure 3.23. The full-wave center-tap with resistive
load is used primarily for low-voltage outputs, as there is only one forward SCR drop. The resistive load of
Figure 3.23(a) is replaced by an inductor ﬁlter in Figure 3.23(b). In this case, a freewheeling diode D is
inserted to provide a path for the inductor current when the SCRs turn OFF. The bridge circuits of Figures
3.23(c)–(f ) are used primarily for higher output voltage applications. Figures 3.23(a)–(d) have the advantage
of common cathodes that permit ﬁring pulse to be applied to both SCRs without need for isolation between
the two SCR gate drive circuits. They also permit simultaneous application of trigger pulses from a pulse
transformer with a single secondary if isolation is required. However, individual gate resistors to each SCR are
recommended. The anode terminal is normally the case of the SCR in stud-mounted devices. The circuit of
Figure 3.23(e) allows the SCRs to be mounted to a common heat sink without isolation, while the diodes
(cathode is normally the case of the device) are mounted to another heat sink without isolation. The two SCRs
are connected in series in Figure 3.23(f ), which has the advantage of eliminating the freewheeling diode since
this function is performed by the two bridge diodes in series. However, isolated trigger pulses to the SCRs
must be provided for the circuits in Figures 3.23(e) and (f ). In Figure 3.23(g), four SCRs are utilized. Here,
output polarity reversal is possible.

Resistive Load
Figure 3.24 shows the output voltage waveforms at various firing angles for resistive loads in single-phase
circuits given in Figure 3.23. Referring to Figure 3.24, the average value or the DC value of the rectified
waveform, triggered at firing angle a is given as

Vs = Vm sinwt RL Vdc

(a)

L
Vs = Vm sinwt C RL Vdc

(b)

Figure 3.23 Single-phase, phase-control circuits.

Chapter 03.indd 129 3/12/2009 3:49:26 PM

130 Power Electronics

1φ
AC Vdc RL
input

(c)

1φ
AC C RL Vdc
input

(d)

1φ
AC Vdc RL
input

(e)

Figure 3.23 Continued.

Chapter 03.indd 130 3/12/2009 3:49:26 PM

Rectifiers 131

1φ
AC Vdc C RL
input

(f)

1φ
AC Vdc C RL
input

(g)

1φ
AC
RL
input

(h)

Figure 3.23 Continued.

Chapter 03.indd 131 3/12/2009 3:49:26 PM

132 Power Electronics

π
1 V
VDC =
πα∫ Vm sin θ dθ = m (1 + cos α )
π
(3.71)

The outputs of circuits shown in Figures 3.23(a), (c), (e) have an average value as given in Eq. (3.71). The out-
puts of the rectifier for circuits in Figures 3.23(b), (d), (f ) also deliver an average value given above. Here the
outputs are filtered using an LC filter to remove the AC component in the rectified output. Circuits of
Figures 3.23(b), (d), (f ) have a freewheeling diode across the rectifier. Because of this, the rectifier output will
contain only positive portions, as the freewheeling diode will clamp the output to zero when it conducts.

Input
waveform

α = 0°

α
α = 60°

α = 90°

α = 120°

Figure 3.24 Voltage waveforms after rectification for various firing

angles for circuits given in Figures 3.23(a)–(f).

Chapter 03.indd 132 3/12/2009 3:49:27 PM

Rectifiers 133

Inductive Load
The circuit shown in Figure 3.23(g) has no freewheeling diode. Therefore, SCR commutation will take place
only when the inductor current goes below the holding current value. The waveforms for the phase-control
circuit of Figure 3.23(g) for various trigger angles are shown in Figure 3.25.
The output voltage with an inductive load is given as
π +α
1 2Vm
VDC =
π ∫ Vm sin θ dθ =
π
cos α (3.72)
α

Input
waveform

α = 0°

α
α = 60°

α = 90°

α = 180°

Figure 3.25 Voltage waveforms after rectification for various firing

angles for circuit given in Figure 3.23(g).

Chapter 03.indd 133 3/12/2009 3:49:27 PM

134 Power Electronics

Figure 3.23(h) provides a topology wherein two SCRs are connected back to back. This topology is a useful
circuit for voltage control of resistive loads like heating applications and light dimmer applications. In low-
power applications, the two SCRs may be replaced by a single TRIAC to control the voltage to the load as
in conventional light dimmers. For high-power applications including inductive loads, the parallel back-to-
back SCRs offer additional current capability and overcome the problem of low-commutating dv/dt rating
associated with TRIACs. If the resistive load is replaced by a transformer whose secondary voltage is rectified
and filtered, a phase-controlled power supply results and regulation is achieved by controlling the firing
angle via feedback circuitry from the DC output to the TRIAC or SCR gates.

Three-Phase-Controlled Rectifier Circuits

Various three-phase-controlled power circuits are shown in Figure 3.26. The half-wave circuits of Figures
3.26(a) and (b) are seldom used due to poor utilization of transformer VA ratings. The bridge circuits of
Figures 3.26(c)–(f ) are more common.

A
1

B Vdc RL
2

C
3
(a)

L
A
1

B C Vdc

C
3
(b)

Figure 3.26 Three-phase, phase-controlled circuits.

Chapter 03.indd 134 3/12/2009 3:49:27 PM

Rectifiers 135

1 3 5

3φ
AC RL Vdc

2 4 6

(c)

1 3 5

3φ Vdc
C RL
AC

2 4 6

(d)

1 3 5

3φ RL Vdc
AC

2 4 6

(e)

Figure 3.26 Continued.

Chapter 03.indd 135 3/12/2009 3:49:28 PM

136 Power Electronics

1 3 5

3φ C RL Vdc
AC

2 4 6

(f)

Figure 3.26 Continued.

Half-Wave Control
The half-wave circuits of Figures 3.26(a) and (b) give output voltage waveforms as shown in Figure 3.27. Referring
to Figure 3.27, the average or the DC component of the half-wave control circuit output voltage is given as
π
1 3V
VDC = 3 ∫
2π (π /6 )+α
Vm sin θ dθ = m cos(α + 30o )
2π (3.73)

AN BN CN AN BN CN

α = 0°

α AN BN CN AN BN CN

α = 30°

Figure 3.27 Voltage waveforms after half-control rectification for various firing
angles for circuits given in Figure 3.26(a) and (b).

Chapter 03.indd 136 3/12/2009 3:49:28 PM

Rectifiers 137

AN BN CN AN BN CN
α

α = 60°

AN BN CN AN BN CN
α

α = 90°

Figure 3.27 Continued.

Reference
waveform

VAN

0
30° α

SCR 1 120°

SCR 2 120°

SCR 3 120°

Figure 3.28 Sequence of SCR firing.

Chapter 03.indd 137 3/12/2009 3:49:28 PM

138 Power Electronics

where Vm is the line-to-neutral peak voltage. The sequence of SCR ﬁring for the circuits of Figures 3.26(a) and (b)
is shown in Figure 3.28.

Full-Wave, Half-Control
The circuits in Figures 3.26(c) and (d) are full-wave bridges with half-control (only three SCRs are required)
and are suitable for resistive load where no regeneration is needed. The SCR cathodes are common which
allows a single non-isolated firing stage for triggering the SCRs. However, the output ripple frequency is
reduced from six times the lines frequency to three times the line frequency at delays angles a > 0 (refer Figure
3.29). The rectifier output voltage waveforms for full-wave half-control circuits are shown in Figure 3.29 for
various firing angles a. The average value of the output voltage for the full-wave half-control circuit is given as
3Vm
VDC = (1 + cos α ) (3.74)
2π

α
AB AC BC BA CA CB AB AC BC BA CA

α = 30°

α
AB AC BC BA CA CB AB AC BC BA CA

α = 60°

Figure 3.29 Voltage waveforms after rectification for full-wave half-control for various firing
angles of circuits given in Figures 3.26(c) and (d).

Chapter 03.indd 138 3/12/2009 3:49:29 PM

Rectifiers 139

α
AB AC BC BA CA CB AB AC BC BA CA

α = 90°

Figure 3.29 Continued.

Reference
waveform

VAB

0
60° α

SCR 1 120°

SCR 3 120°

SCR 5 120°

Figure 3.30 Firing sequence for the SCRs.

where Vm is the line-to-line peak voltage. The ﬁring sequence for the SCRs is as shown in Figure 3.30. The
diodes D2, D4 and D6 will conduct depending on the most negative line (A or B or C line) at any given
instant of time.

Full-Wave, Full-Control
Full-wave bridges with full control (six SCRs) are shown in Figures 3.26(e) and (f ). The ﬁring sequence is
more complicated than that of half-control topologies since the SCRs require two gate signals each cycle.

Chapter 03.indd 139 3/12/2009 3:49:29 PM

140 Power Electronics

The rectiﬁer output voltage waveforms for various ﬁring angles, a, are shown in Figure 3.31. The average
value of the output voltage for the full-wave full-control resistive load is given as

3Vm
VDC = cos α (3.75)
π

where Vm is the line-to-line peak voltage.

The ﬁring sequence for the full-wave, full-control circuits of Figures 3.26(e) and (f ) is given in Figure
3.32.

Overlap and Overlap Angle

In the discussions till now, instantaneous commutations among SCRs were assumed. However, in practice
this will not be the case. In series with each SCR there will be an inductance. This inductance exists because

α
AB AC BC BA CA CB AB AC BC BA CA

α = 30°

α
AB AC BC BA CA CB AB AC BC BA CA

α = 60°

Figure 3.31 Voltage waveforms after rectification for full-wave full-control for
various firing angles of circuits given in Figures 3.26(e) and (f).

Chapter 03.indd 140 3/12/2009 3:49:29 PM

Rectifiers 141

α
AB AC BC BA CA CB AB AC BC BA CA

α = 90°

Figure 3.31 Continued.

Reference
waveform

VAB

0
60° α

SCR 1 120°

SCR 3 120°

120°
SCR 5

120°
SCR 2

120° 120°
SCR 4

60° 120°
SCR 6

Figure 3.32 Firing sequence for the full-wave, full-control circuits of Figures 3.26(e) and (f).

Chapter 03.indd 141 3/12/2009 3:49:30 PM

142 Power Electronics

of source, line, load, etc. Owing to the presence of this series inductance, during commutation, the SCR
that is turning OFF will turn-OFF only after the current through its inductance reduces below the holding
current value. The current in the SCR that is turning ON will rise slowly depending on the value of the
inductance. During a small interval of the time both the commutating SCRs will be ON. This is called con-
duction overlap. The period in angle for which the conduction overlap occurs is called the overlap angle.
During overlap the output voltage reduces by the inductance voltage drop equal to L(di/dt) and this increases
with load current. It should be borne in mind that the presence of these series parasitic inductances that
cause the conduction overlap will result in loss of output regulation.

| CONCLUDING REMARKS
The rectifiers and especially the capacitor-filter rectifi- (EMI) issues. Therefore due to regulations, more
ers are rather ubiquitious as far as power electronic sys- and more power electronic systems are incorporat-
tems are concerned. Most power electronic systems ing unity pf correction circuits into the frontend
draw the power from the AC grid. They are first con- AC–DC rectifier circuits. The more popular fron-
verted to DC by the rectification mechanisms discussed tend boost converter for pf correction and the fron-
in this chapter to form the DC bus or the DC link for tend converters for inverter applications are
the system. In this respect, the AC–DC rectifiers play a discussed in Chapter 10.
pivotal role in most power electronic applications. Apart from the above problems, the issue of the
Though the capacitor-filter rectifier is volumet- turn-ON surge currents that is prevalent in capaci-
rically the most efficient and also least expensive, it tor-filter rectifier circuits is a serious drawback. Extra
suffers from low pf issues. This implies that the grid circuits have to be used to circumvent the problem
power from which the power is drawn has to be of startup surge currents. Notwithstanding the
rated many more times than the actual active load drawbacks mentioned above, the capacitor-filter
power. This leads to significant line loss. Further as rectifier is still the most simple and popular AC–DC
the peak currents flow in a small duration near the rectifier circuit that is in use till date. The rectifier
voltage peaks, the line drops due to the current LC filter is not as popular due to the bulky and
flow distorts the voltage waveforms causing a flat- costly inductor. In higher power circuits, controlled
tening of the sinusoidal voltage waveshape near the rectification followed by capacitor-filter circuits are
peaks. This leads to higher total harmonic distor- used. Here the trigger angle or the firing angle gives
tion and conducted electromagnetic interference a measure of control on the startup surge currents.

| LABORATORY EXERCISES
1. Consider the capacitor-filter rectifier circuit as b. Simulation in SciLAB
shown in Figure 3.33. The input is a single-phase c. Hardware bread-boarding
source that is derived from a 230 V mains. The
Tasks for study:
input may be given from an autotransformer to
(a) Rig up the circuit as shown in Figure 3.33
obtain different input voltage amplitudes.
and plot Vi and i versus time.
Mode of implementation: The above circuit (b) Why is there ringing on the current wave-
can be studied by form?
a. Simulation in Spice (c) What is the series impedance of the circuit?

Chapter 03.indd 142 3/12/2009 3:49:30 PM

Rectifiers 143

c iR
+ i
1 3
ic
Vi ∼ a
+
Cf RL Vo
b
∼
4 2
−

Figure 3.33 Single-phase capacitor-filter rectifier circuit.

(d) Plot Vi and Vo versus time. What is the (j) Under what conditions do you get maxi-
ripple? How does ripple depend on load, mum peak current to flow through the
capacitor Cf and frequency of input wave- diodes?
form? (k) Measure the input voltage and current and
(e) Measure the current and voltage waveform estimate the power factor.
across the rectifier diode. (l) What is the effect of change in Cf value on
(f ) Estimate the average and rms currents the input current and power factor?
through the rectifier diode. Calculate the
2. Consider the three-phase capacitor-filter recti-
diode power dissipation.
fier circuit as shown in Figure 3.34. The input is
(g) What should be the peak current rating of
a three-phase source that is derived from a 400 V
the diode?
mains. The input may be given from a three-
(h) Change the initial charge voltage on the
phase autotransformer to obtain different input
capacitor Cf. What is the effect on the
voltage amplitudes. The circuit shown consists
input surge current?
of a basic single-phase full-bridge rectifier.
(i) Change the phase angle of the input Vi at
When switches “S1” are put in position 1, then
start up. Observe the effect on current i.
one more diode arm gets connected. This trans-
What happens and why?
forms the circuit into a three-phase full-bridge

0
i iR
S1 + ic +
1 C1
a 0
b c RL Vo
Va Vb Vc
S2 +
1 C2
0
S1 −
S1
1 0 1

Figure 3.34 Three-phase capacitor-filter rectifier circuit.

Chapter 03.indd 143 3/12/2009 3:49:30 PM

144 Power Electronics

rectifier circuit. Note that when “S1” are in (j) What is the effect of the S2 switch on the
position 0, Va and Vc are disconnected by S1 diode currents for a given load?
thereby applying only a single-phase voltage (k) What is the effect of unequal C1 and C2 on
across the b-c diode bridge. During single-phase the output voltage?
operation of the circuit, switch “S2” gives a (l) How is charge equalization done for C1
doubler effect. and C2? [Hint: Connect resistors across
each capacitor and observe.]
Mode of implementation: The above circuit
can be studied by 3. Consider the single-phase LC-filter rectifier
a. Simulation in Spice circuit as shown in Figure 3.35. The input is a
b. Simulation in SciLAB single-phase source that is derived from a 230 V
c. Hardware bread-boarding mains. The input may be given from an auto-
Tasks for study: transformer to obtain different input voltage
(a) Keep S1 in position 0 and S2 in position 0. amplitudes. Ls and Rs are the equivalent circuit
Observe Vbc, i, iR, iC and Vo. series inductance and resistance, respectively,
(b) Keep S1 in position 0 and S2 in position 1. that represent the non-idealities; Lf is the filter
Observe Vbc, i, iR, iC and Vo. What is the inductance of the LC filter.
effect of switch S2? What is its application? Mode of implementation: The above circuit
(c) Keep S1 in position 1 and S2 in position 0. can be studied by
Observe Va, Vb, Vc, i, iR, iC and Vo. a. Simulation in Spice
(d) What is the ripple frequency of the output b. Simulation in SciLAB
when S1 is in position 1 and in position 0? c. Hardware bread-boarding
(e) When S1 is in position 1, what is the worst
case ripple? Tasks for study:
(f ) What should be the peak current rating of (a) Rig up the circuit as shown above and plot
the diode? Vi and i versus time.
(g) Change the initial charge voltage on the (b) Plot the rectified Vi and Vo versus time.
capacitors. What is the effect on the turn- (c) Vary the load resistor RL and plot Vo versus
ON surge current? load Io.
(h) Observe the diode currents when S1 is in (d) What is the minimum load current for
position 1 and in position 0. which the inductor current is continuous?
(i) Estimate the average and rms currents of (e) Incorporate a bleeder resistor across the
the diode when S1 is in position 1 and in capacitor and plot the efficiency versus load
position 0. with and without the bleeder resistor.

LS RS Lf iR
+ iL
1 3 ic
Vi ∼ a +
Cf RL Vo
∼ b
4 2
−

Figure 3.35 Single-phase LC–rectifier circuit.

Chapter 03.indd 144 3/12/2009 3:49:31 PM

Rectifiers 145

(f ) What is the ripple? How does a ripple (i) What should be the peak current rating of
depend on load, inductor, capacitor and the diode?
frequency of input waveform? (j) Compare the turn-ON surge current with
(g) Measure the current and voltage waveforms the capacitor-filter rectifier for a given load.
across the rectifier diode. (k) Measure the input voltage and current and
(h) Estimate the average and rms currents estimate the power factor.
through the rectifier diode. Calculate the (l) What is the effect of change in Lf and Cf
diode power dissipation. value on the input current and power factor?

| FILL IN THE BLANKS

1. Single-phase rectifier circuit topologies are 11. In the case of the bridge rectifier circuit, there
designed for applications wherein the input is no need for a separate diode.
source is the .
12. The load ripple frequency for a half-wave recti-
2. Three-phase rectifier circuit topologies are fier system is the input source
designed for applications wherein the input frequency.
source is a .
13. The load ripple frequency for a full-wave recti-
3. For inductive loads, an additional diode called fier system is the input source
is needed to provide a path for the frequency.
inductor current when the rectifier diode is OFF.
14. In a three-phase half-wave rectifier circuit, the
4. Use of a is compulsory for the full- secondary windings of the transformer carry
wave center-tapped rectifier. the currents as that flowing through
5. The PIV for the diodes of a full-wave center- the diodes.
tapped rectifier is the PIV for the 15. The load ripple frequency for a three-phase
diodes of the half-wave or full-bridge rectifiers half-wave rectifier system is the
for a given load voltage requirement. input source frequency.
6. In a full-wave center-tapped rectifier, the cur- 16. The load ripple frequency for a three-phase
rent through the secondary of the transformer full-wave rectifier system is the input
is a wave rectified waveform. source frequency.
7. In a full-wave center-tapped rectifier, the current 17. Capacitor input filters are the most
through the rectifier diodes of the transformer is efficient means of filtering rectified sine waves
a wave rectified waveform. and storing energy.
8. In the full-wave bridge rectifier there will be 18. The output voltage ripple for a single-phase
diode drop in the bridge rectifier capacitor-filter rectifier is the input
topology as compared to the half-wave or full- frequency.
wave center-tapped rectifier topologies.
19. The output ripple frequency for three-phase
9. In a full-wave bridge rectifier with transformer, half-wave capacitor-filter rectifier is .
the current through the secondary of the trans-
former is a waveform. 20. The output ripple frequency for three-phase
full-wave capacitor-filter rectifier is .
10. In a full-wave bridge rectifier, the current
through the rectifier diodes is a wave 21. In a three-phase capacitor-filter rectifier circuit
rectified waveform. that is supplied from three-phase mains, the

Chapter 03.indd 145 3/12/2009 3:49:31 PM

146 Power Electronics

peak capacitor voltage is time the 29. In LC–rectifier filters, when the load is light, a
input mains phase voltage. value of L is needed if the ripple is
to be small.
22. The turn-ON surge current in the capacitor-
filter rectifier is limited by the line resistance, 30. Power supplies utilize TRIACs or SCRs as the
of the capacitor, rectifier diodes device to provide a desired dc output
and the input line and/or the leak- from single-phase or three-phase inputs.
age of the transformer if present. 31. In single-phase half-controlled SCR bridge
23. Low power factor implies line rectifier configurations, the rectifier output will
losses. contain only portions.

24. Unity power factor occurs when the load is 32. In single-phase full-controlled SCR bridge rec-
purely . tifier configuration, the SCR commutation will
take place only when the inductor current goes
25. In a capacitor-filter rectifier circuit, lower the below the value.
power factor, will be the
33. The reference waveform for sequencing the firing
current drawn from the input source.
of the SCRs for the three-phase half-wave half-
26. The rectifier–LC filter does not have the prob- controlled rectifier is the waveform.
lem of turn-ON due to the presence 34. The reference waveform for sequencing the
of the . firing of the SCRs for the three-phase full-
27. The major drawback of the LC-filter rectifier is wave half-controlled rectifier is the line-to-line
the that has to be designed for the waveform.
supply frequency. 35. Three-phase full-wave full-controlled rectifier
28. For a good LC-filter circuit, and consists of SCRs in bridge configu-
Xc << XL. ration.

| DESCRIPTIVE QUESTIONS
1. Where are rectifiers used? 7. Explain the operation of the three types of
single-phase rectifier circuits with illustrative
2. How are rectifiers classified?
waveforms.
3. What are the three basic rectifier configurations?
8. A delta-star transformer is used for a three-
4. For a half-wave rectifier, draw the load voltage phase full-wave rectifier system. In the
and current waveforms for an inductive load secondary of the three-phase transformer, if the
and derive the load power equation. neutral point is available, draw and explain the
schematic to generate positive and negative
5. For a full-wave center-tapped rectifier, draw
voltages with respect to the neutral point using
the load voltage and current waveforms for an
a single three-phase bridge-rectifier topology.
inductive load and derive the load power
equation. 9. Discuss the operation of the capacitor input
filter rectifier.
6. For a full-wave bridge rectifier, draw the load
voltage and current waveforms for an inductive 10. What are the factors that affect the output
load and derive the load power equation. ripple of the capacitor-filter rectifier?

Chapter 03.indd 146 3/12/2009 3:49:31 PM

Rectifiers 147

11. What is hold time? How does one design the 16. Discuss the design considerations for the
value of capacitor for a specified hold time? inductor of an LC–rectifier filter.
12. Discuss the turn-ON surge current problem in 17. Explain the terms minimum load current
capacitor-filter rectifier circuits. What are the and bleeder load resistance with respect to a
parameters affecting the amplitude of the turn- rectifier–LC filter.
ON surge current? How is this problem solved
18. What is the ripple content in the output volt-
in practice?
age of an LC–rectifier filter?
13. What are the methods for improving the power
19. Discuss the operation of half- and full-control
factor of AC–DC rectifiers?
of single-phase controlled rectifiers.
14. What are the benefits of the LC–rectifier filter?
20. Distinguish between half-wave half-control,
15. What are the disadvantages of the LC–rectifier full-wave half-control and full-wave full-con-
filter? trol in three-phase-controlled rectification.

| PROBLEMS
1. A half-wave rectifier is supplying 50 W to a secondary to primary phase winding turns ratio
resistive load by drawing power directly from a is 0.5. What are the average load voltage and
230 V rms mains grid. What are the average current? What are the rms load voltage and
load voltage and current? What are the rms current? What are the average and rms currents
load voltage and current? of the rectifier diodes?
2. A full-wave center-tapped rectifier is supplying 7. A 1000 W resistive load is supplied by a star–
50 W to a resistive load by drawing power from star transformer-isolated three-phase full-wave
a center-tapped transformer that is connected rectifier. The rectifier is drawing power directly
to the 230 V rms mains grid. The turns ratio of from the 400Vrms three-phase mains grid. The
the center-tapped transformer is unity. What secondary to primary phase winding turns ratio
are the average load voltage and current? What is 0.5. What are the average load voltage and
are the rms load voltage and current? current? What are the rms load voltage and
current? What are the average and rms currents
3. For Problem 2, calculate the rms value of the
of the rectifier diodes?
primary and secondary winding currents.
8. In a capacitor-filter rectifier that is supplied
4. A full-wave bridge rectifier is supplying 50 W
from 230 V, 50 Hz mains, a 100 μF output
to a resistive load by drawing power directly
capacitor discharges to 250 V every half-cycle.
from the 230 V rms mains grid. What are the
What is the energy given to the load by the
average load voltage and current? What are the
capacitor every input voltage cycle?
rms load voltage and current?
9. Calculate the capacitor value of a capacitor-
5. For Problem 4, calculate the rms value of the
filter rectifier that is supplied from 230 V, 50 Hz
primary and secondary winding currents.
mains wherein the peak-to-peak ripple is 50 V
6. A 1000 W resistive load is supplied by a star– and the load is 500 W.
star transformer-isolated three-phase half-wave
10. For Problem 9, calculate the load current and
rectifier. The rectifier is drawing power directly
the peak, rms and average values of the current
from the 400Vrms three-phase mains grid. The

Chapter 03.indd 147 3/12/2009 3:49:31 PM

148 Power Electronics

through the rectifier diodes. Calculate also the are triggered at firing angles of 45°, 90°, 120°
rms current through the capacitor. and 180°?
11. For Problem 9, estimate the power factor of the 17. A single-phase full-controlled SCR bridge
capacitor-filter rectifier circuit. rectifier is supplying an RL load from a single-
phase 230 V mains. What is the average value
12. For an LC–rectifier filter that is supplied from
of the load voltage if the SCRs are triggered at
the 230 V, 50 Hz mains, the load power is 500 W,
firing angles of 45°, 90°, 120° and 180°?
what is the output voltage if the current
through the inductor is continuous? 18. For a three-phase half-wave half-controlled recti-
fier which is supplying a load from a three-phase
13. For an LC–rectifier filter that is supplied from
400 V rms line-to-line mains grid, find the trigger
the 230 V, 50 Hz mains, if the maximum value
angle at which the average load voltage is 75V.
of the load resistance is 50 Ω, estimate the
minimum value of the filter inductor required. 19. For a three-phase full-wave half-controlled
rectifier which is supplying a load from a three-
14. For an LC–rectifier filter that is supplied from
phase 400 V rms line-to-line mains grid, find
the three-phase 400 V mains, if the maximum
the trigger angle at which the average load
value of the load resistance is 50 Ω, estimate the
voltage is 400 V.
minimum value of the filter inductor required.
20. For a three-phase full-wave full-controlled
15. For Problem 13, if the rms value of the output
rectifier which is supplying a load from a three-
ripple is not to exceed 50 V, calculate the
phase 400 V rms line-to-line mains grid, find
capacitor value of the LC filter.
the trigger angle at which the average load
16. A single-phase half-controlled SCR bridge voltage is 400 V.
rectifier is supplying a resistive load of 1000 W
from a single-phase 230 V mains. What is the
average value of the load voltage if the SCRs

| ANSWERS
Fill in the Blanks
1. single-phase grid 14. same 25. higher; peak
2. three-phase grid 15. thrice 26. surge currents; inductor
3. freewheeling diode 16. four times 27. inductor
4. transformer 17. volumetrically 28. Xc << RL
5. twice 18. twice 29. large
6. half 19. 150 Hz 30. control
7. half 20. 300 Hz 31. positive
8. two 21. 3 32. holding current
9. full 22. equivalent series resistance; 33. line-to-neutral A phase
10. half dynamic resistance; reactance 34. VAB
11. freewheeling 23. higher 35. six
12. same as 24. resistive
13. twice

Chapter 03.indd 148 3/12/2009 3:49:31 PM

DC–DC Linear Regulators

Learning Objectives
CHAPTER

4
After reading this chapter, you will be able to:
understand the operating principle of linear regulators.
design and apply the various types of linear regulators.
analyze and characterize the linear regulators.

T he DC−DC linear regulators convert the input DC voltage to an output DC voltage wherein the
output voltage is regulated for variations in input voltage, temperature and output load. The regulation
is achieved by operating the power semiconductor devices in the linear region rather than as switches. This,
of course, leads to large power dissipation in the power devices and consequent reduction in efficiency of the
regulator.
There are, in general, two component sets in the operation of the DC−DC linear regulators, namely, (a)
the voltage scaling circuit and (b) the output voltage regulation circuit. However, the operations of these two
component sets are interlinked and dependent on each other. Hence the designs of these two component
sets are not decoupled from each other.
The output DC voltage value is always lesser than the input unregulated DC voltage value, that is, the
scaling circuit will only attenuate the input voltage but will not amplify the input voltage. In other words, the
gain in the scaling circuit is less than unity. Even though the linear regulators have low efficiency, the quality
of the output voltage with respect to the variations in parameters like input voltage, temperature and load are
excellent and by far better than that offered by any switched-mode converter. The output voltage can be
designed to be almost ripple-free in the case of the linear regulators. The major disadvantage of the linear
regulators is in term of efficiency and as a consequence the very low resulting volumetric power density.

4.1 Generic Linear Regulator

T he schematic of a generic linear regulator is shown in Figure 4.1. It consists of two main resistive com-
ponents: (a) Rs, the series component that performs the function of dropping the voltage across itself to
obtain a specified scaling at the output; (b) Rsh, the shunt component that generally performs the function
of the regulation. Both Rs and Rsh are variable resistances.
Rs is an essential component is all linear regulators. However, Rsh may not be present in all linear regula-
tor topologies. If the output voltage regulation is performed by varying Rs, such regulators are classified as
series regulators and if it is performed by varying Rsh then such regulators are classified as shunt regulators.

Chapter 04.indd 149 3/12/2009 3:50:01 PM

150 Power Electronics

Iin
Rs Ish

Vi Rsh RL Vo

Linear regulator

Figure 4.1 Schematic of a generic linear regulator.

Operating Principle
The operation of the generic linear regulator depends on whether it is the series regulator type or the shunt
regulator type. In the series regulator, as the output voltage Vo increases, the series resistance Rs is increased.
The drop across Rs increases thereby bringing down the Vo. Likewise as Vo decreases, Rs is decreased. The drop
across Rs decreases and brings up Vo. In the shunt regulator, the shunt component is used for regulating Vo.
Referring to Figure 4.1, one can observe that
Vo Vo
I in = I sh + I o = + (4.1)
Rsh RL

Vo = Vi − I in Rs (4.2)

Let Pi be the power drawn from the input source. Using Eqs. (4.1) and (4.2), Pi is given as
Pi = Vi I in = (Vo + I in Rs )I in
= Vo I in + I in2 Rs
2
⎛ R + RL ⎞ 2 ⎛ Rsh + RL ⎞
= Vo I o ⎜⎜ sh ⎟⎟ + I o ⎜⎜ ⎟⎟ Rs (4.3)
⎝ Rsh ⎠ ⎝ Rsh ⎠
2
⎛ R ⎞ 2⎛ R ⎞
= Vo I o ⎜⎜ 1 + L ⎟⎟ + I o ⎜⎜ 1 + L ⎟⎟ Rs
⎝ Rsh ⎠ ⎝ Rsh ⎠

The output power (Po) delivered to the load is

Po = Vo I o (4.4)

The eﬃciency of the linear regulator is deﬁned as the ratio of the power delivered to the output load to the
power drawn from the input source. This is given as

Chapter 04.indd 150 3/12/2009 3:50:02 PM

DC–DC Linear Regulators 151

Po Vo I o
η= = (4.5)
Pi Vo I o [1 + ( RL / Rsh )] + I o2 [1 + ( RL / Rsh )]2 Rs

If Rsh is very high or tending to inﬁnity, then Iin = Io. From Eq. (4.5) it can be observed that
Vo
η=
Vi

4.2 Linear Regulator Topologies

Shunt Regulator
Figure 4.2 shows the circuit schematic of a Zener shunt regulator. The shunt component is a Zener diode
that is operated in the reverse breakdown region. The series component is a ﬁxed resistor Rs.

Ideal Zener
Figure 4.3 shows the static characteristic of the Zener diode. The Zener diode is the shunt element that is
connected across the load. According to the idealized static characteristic of the Zener diode as shown in
Figure 4.3(a), one can observe that the voltage across the Zener diode is a constant at Vz. Thus Vo is clamped
to Vz irrespective of the changes in the input voltage and the load. Thus Vo is regulated by virtue of the
Zener diode being operated in the breakdown region. Referring to Figure 4.2,

I in = I z + I o (4.6)

Vi − Vz
I in = (4.7)
Rs

Vo = V z (4.8)

From Eq. (4.8), it is seen that Vo is independent of the load Io and the input Vi. Thus the load voltage is reg-
ulated as Vz is constant. Under no-load condition, Io = 0 and the whole of Iin ﬂows into Iz. As the load
increases, a part of Iin commutates from the Zener to the load, that is, Iz decreases and Io increases. Likewise,
if Io decreases, Iz will increase to compensate for the decrease in Io, thus regulating the output. The Zener

Ii Io

Rs Iz

Vi Vz RL Vo

Figure 4.2 Zener shunt regulator.

Chapter 04.indd 151 3/12/2009 3:50:02 PM

152 Power Electronics

i i

Vz
Vz
0 u 0 u

1/rz Iz

(a) (b)

Figure 4.3 (a) Ideal static characteristic of the Zener diode;

(b) piece-wise linear static characteristic of the Zener diode.

current Iz is maximum under no-load condition when Io is zero. Under this condition, the input current Iin
ﬂows through the Zener. Thus,
Vi-max − Vz
I z-max = (4.9)
Rs

Iz-max is limited only by the power rating of the Zener diode. The other limiting condition is when the input
current completely ﬂows through the load under full-load condition. During this condition,

I o = I in and I z = 0 (4.10)

The Zener should be maintained in the breakdown region even under minimum input voltage condition.
Therefore, the maximum load current allowable is
Vi-min − Vz Vz
I in = I o-max = = (4.11)
Rs RL-min

Problem 4.1
Consider a shunt regulator circuit wherein the input voltage Vi varies between 9 and 13 V and the Zener diode
used is a 5 V, 400 mW device. What is the range of the load resistance?

Solution
The maximum possible Zener current is

Pz 400 mW
= = 80 mA
Vz 5V

Chapter 04.indd 152 3/12/2009 3:50:03 PM

DC–DC Linear Regulators 153

The operating input current should be less than 80 mA. Let 60 mA be the maximum Zener operating cur-
rent Iz-max. Then from Eq. (4.9),
V − Vz 13 − 5
Rs = i-max = ≈ 133 Ω
I z-max 60 mA
The power dissipated in the series resistor Rs is
(13 − 5)2
PRs = ≈ 0.48 W
133

From Eq. (4.11), the minimum value of the load resistance RL should be calculated such that even at the
lowest input voltage and load, the Zener is in reverse breakdown. Thus,
RsVz 133 × 5
RL-min = = ≈ 166 Ω
Vi-min − Vz 9−5

On the other hand, the maximum value of the load resistance can be inﬁnite, that is, open circuit when all
the input current ﬂows through the Zener diode. Thus the range of the load resistance is limited to
166 ≤ RL < ∞

Non-Ideal Zener
The Zener diode does not have ideal static characteristics as shown in Figure 4.3(a). The piece-wise linear
approximation of the actual static characteristic of the Zener diode shown in Figure 4.3(b) is much closer to
reality. The Zener has a non-zero operating resistance rz in the breakdown region as shown in Figure 4.3(b).
This ﬁrst-level non-ideality is introduced into the shunt regulator circuit as indicated in Figure 4.4.
Owing to the presence of rz, the output voltage is no longer identical to the Zener breakdown voltage Vz.
It is now given as
Vo = Vz + I z rz (4.12)
From Eq. (4.12) it is evident that the output voltage is dependent on Iz. However, Iz varies from almost zero
at full-load condition to full load current value during no-load operation. Therefore, the regulation of the
output with respect to variations in the load is poor due to the voltage drop across rz.

Iin Rs Iz Io

Vi rz RL Vo

Ro = rz //Rs

Figure 4.4 The Zener diode is replaced by first-level non-idealities.

Chapter 04.indd 153 3/12/2009 3:50:03 PM

154 Power Electronics

Io /b
Q
Rs
Iz
Vbe Io
Vi Vz
RL Vo

Figure 4.5 Modified shunt regulator.

Modified Shunt Regulator

The regulator shown in Figure 4.5 tries to reduce the eﬀect of the Zener diode non-ideality rz on the output
voltage regulation.
For the modiﬁed shunt regulator of Figure 4.5, the output voltage Vo is the Zener voltage Vz minus the
drop across the base−emitter junction of the transistor Q. Thus,
Vo = Vz − Vbe (4.13)

In this circuit, the maximum Zener current is limited to I o / β instead of Io for the circuit of the
Figure 4.4. As the Zener current variation is reduced by b, the drop across the Zener resistance rz is also very
much diminished. Thus, the output voltage including the Zener non-ideality is given as
Vo = Vz + I z rz − Vbe (4.14)

where maximum value of Iz is Io/b.

In this topology, even though the output voltage regulation with respect to variations in the load
is much better as compared to the circuit of Figure 4.4, the outp ut voltage is dependent on Vbe of the
transistor Q. The Vbe of the transistor varies with temperature at the rate of about −2 mV/°C rise in
temperature. However, if the Zener is chosen to have a positive temperature coeﬃcient then this would
compensate for the variations in Vbe due to temperature, thereby making the output voltage Vo independent
of temperature.

Series Regulator
The series regulator is a linear regulator wherein the series component is controlled. To control the series
component, a controllable resistor has to be used as the series-pass element. A transistor or bipolar junction
transistor (BJT) operating in the linear region can be used as a series-pass element whose base current can be
controlled to change the resistance presented to the input source. Figure 4.6(a) shows the basic schematic of
the series regulator with the series-pass component being a transistor Q.
Figure 4.6(b) shows the series regulator wherein the base drive for the series-pass transistor Q is being
controlled by the operational ampliﬁer (op-amp). The output voltage Vo is attenuated by two resistors R1
and R2 and fed to the “−” terminal of the op-amp. The “+” of the op-amp is fed from a Zener voltage refer-
ence. The output of the op-amp drives the base of the transistor Q. If the output voltage increases, the “−”
terminal of the op-amp will increase. As the “+” terminal is at a constant reference potential, the output of
the op-amp will decrease the drive to the base of the transistor Q. This will increase the resistance presented

Chapter 04.indd 154 3/12/2009 3:50:03 PM

DC–DC Linear Regulators 155

Vi RL Vo

(a)

Q
Rz R1
−
Vi RL Vo
+
R2
Vz

(b)

Io
Q1
Rb
R1
Rz

Vi Q2 RL Vo

R2
Vz

(c)

Figure 4.6 Series regulator: (a) Series regulator using transistor as the series pass; (b) the
series-pass transistor is controlled by an op-amp; (c) the series pass is controlled by
another transistor amplifier.

by Q to the input and thereby increase the drop across the collector to emitter of the transistor Q. As a con-
sequence, the output voltage will decrease and be brought back to the equilibrium state. All these events
occur simultaneously at an instant. Likewise if the output voltage were to decrease, the drive to Q will
increase thereby decreasing the drop across the collector−emitter of Q. This will tend to increase the output
voltage and bring it back to the equilibrium state.

Chapter 04.indd 155 3/12/2009 3:50:04 PM

156 Power Electronics

The circuit of Figure 4.6(c) is similar to that of Figure 4.6(b) except that the op-amp is replaced by a
transistor (BJT) ampliﬁer Q2 as shown. The Zener voltage reference is fed to the emitter terminal of Q2 and
the attenuated output voltage is fed to the base terminal of Q2. The transistor Q1 acts as the series-pass transis-
tor. The base of the transistor Q1 is at potential (Vo + Vbe1). Thus, the current through the bias resistor Rb is

Vi − Vo − Vbe1
I Rb = (4.15)
Rb
IRb can be considered as a current source that diverts the current between the base of Q1 and the collector of
Q2 depending on the output voltage.
If the output voltage decreases, then the base−emitter potential (Vbe2) of Q2 decreases. This will reduce
the collector-current flow of Q2. As a consequence, the portion of IRb that will be diverted to the base of Q1
will increase, resulting in reduced collector−emitter resistance of Q1. This will decrease the drop across the
collector−emitter of Q1 and will make the output voltage to increase and be brought back to the equilibrium
state. In a similar manner, the output voltage regulation will occur when the output voltage increases.
The resistances R1 and R2 are chosen based on the following governing equation:
⎛ R2 ⎞
Vo ⎜ ⎟ = Vz + Vbe2 (4.16)
⎝ R1 + R2 ⎠
Allow a current of about 1% of the full load current to flow through R1 and R2. This constraint and Eq. (4.16)
can be used to decide the values of R1 and R2. Rz is chosen such that the current flowing through the Zener
diode biases it in the breakdown region of the static characteristic curve. Rb is chosen based on Eq. (4.15) with
the nominal value of the input voltage Vi.

Negative Voltage Regulator

In the series regulator of Figure 4.6, the negative rail is used as the circuit ground. However, if one has to use
the positive rail as the circuit ground, then the schematic is modiﬁed as shown in Figure 4.7. The positive
output voltage series regulators have the series-pass component in the positive rail and the voltages are mea-
sured with reference to the negative rail as indicated in Figure 4.7(a). The NPN series-pass transistor Q is
replaced by an equivalent PNP series-pass transistor as shown in Figure 4.7(b). In this ﬁgure, the series-pass
element is included in the negative rail and the voltages are measured with respect to the positive rail.
Therefore the voltages are negative in the circuit of Figure 4.7(b).

Vi RL Vo
Vi RL Vo

(a) (b)

Figure 4.7 Series regulator with (a) negative rail as circuit ground; (b) positive rail as circuit ground.

Chapter 04.indd 156 3/12/2009 3:50:04 PM

DC–DC Linear Regulators 157

The negative regulator of Figure 4.7(b) is implemented in Figure 4.8(a). The schematic of the negative
output series regulator shown in Figure 4.8(a) is similar to the positive output regulator of Figure 4.6 except
that the transistors are replaced by PNP transistors to handle reverse current ﬂow direction. The Zener volt-
age reference is also reverse as indicated.

Q1 −
Rb
R1
Rz
−
Vi Q2 RL Vo
+ Io

− R2
Vz
+
+
(a)

Vi1
Common negative rail or
+Vo1 positive regulator

Common positive rail or

negative regulator
−Vo2

Vi2

(b)

Figure 4.8 (a) Series regulator with negative output voltage; (b) dual power supply linear regulator.

Chapter 04.indd 157 3/12/2009 3:50:04 PM

158 Power Electronics

The operation of the negative output voltage regulator of Figure 4.8(a) is also very similar to that of the
positive voltage regulator of Figure 4.6. Here too, the current through Rb can be assumed to be a current
source as the base of Q1 is at potential −Vo − Vbe1 and the other end of Rb is at −Vi potential. Thus,
Vo + Vbe1 − Vi
I Rb = (4.17)
Rb
If the output voltage becomes more negative, then the potential at the base of Q2 decreases as compared to
the emitter of Q2. This increases the drive for the PNP transistor and the contribution of collector current
of Q2 to IRc increases, thereby decreasing the contribution of the base current of Q1 to IRb. As this decreases
the base drive for Q1, the emitter−collector voltage drop of Q1 increases and brings Vo to the equilibrium
state. Similar regulation action occurs when Vo becomes less negative.
The positive rail regulators and the negative rail regulators can be used together to obtain both positive
and negative power supplies with a common ground. A typical dual supply linear regulator circuit is shown
in Figure 4.8(b).

IC Linear Regulators
The linear regulators are available commercially in the form of integrated circuits (IC). The IC regulators can
be classified into three major categories, namely,
1. fixed regulators;
2. variable regulators;
3. variable regulators with current boost.
The fixed regulator types are available as three-pin regulators. The more popular among them are the 78xx
and 79xx series. Here xx represents the output voltage of the regulator. For example, 7805 is a 5 V positive
voltage regulator, 7812 is a 12 V positive voltage regulator and so on. The 79xx series are negative voltage
regulators that are complementary to the 78xx series.
The variable regulators are also available as three-pin regulators with three pins, viz. input, output and
adjust. The “adjust” pin is used for varying and setting the output voltage of the regulator. The 317 regulator
is a popular variable voltage regulator. The 350 is also another three-pin adjustable regulator like the 317 but
with higher load current capability. The 337 is a negative voltage regulator that is complementary to the 317
positive voltage regulator.
There is a class of IC regulators that gives flexibility both in output voltage setting and also in the cur-
rent-carrying capability by giving facility to include an external boost transistor. The 723 is a very popular
linear regulator IC in this class.

Example: 317 IC Regulator

The schematic of the 317 IC linear regulator is shown in Figure 4.9. The characteristic feature of this regula-
tor is the voltage across the output pin (OUT) and the adjust pin (ADJ). The voltage between these two pins
is maintained at 1.25 V for this regulator. The output voltage Vo is decided by the ratio of R1 and R2.
Referring to Figure 4.9, the output voltage is given as

⎛ R ⎞
Vo = 1.25 ⎜ 1 + 2 ⎟ (4.18)
⎝ R1 ⎠

Chapter 04.indd 158 3/12/2009 3:50:05 PM

DC–DC Linear Regulators 159

Io
IN OUT
317

ADJ
R1

1.25 V
Vi RL Vo

Figure 4.9 Basic schematic of 317 IC linear regulator.

R1 is recommended by the manufacturer to be around 240 Ω. R2 can be calculated from the output voltage
requirement and Eq. (4.18). The maximum input voltage that can be applied is 40 V. The 317 IC regulator
needs a minimum diﬀerential voltage of 3 V between its input and output pins. Thus the maximum output
voltage can be 37 V. The 317 IC is rated to handle 1.5 A and the 350 IC is rated to handle 3 A. All other
aspects of 350 IC are similar to the 317 IC.
The circuit of Figure 4.9 is suﬃcient for the basic operation of the regulator. However there are a few
components that need to be included to improve the reliability of the circuit. The complete circuit sche-
matic of the 317 IC regulator circuit is shown in Figure 4.10.
The regulation of the 317 IC is best when the input and the output load are pure DC. However, there
will be ripples on the input side and the load may be switching loads like digital circuit loads. In such cases
there will be AC components present. The regulator performance deteriorates for the AC components.
Therefore, the AC components in the load side that are generated due to digital loads should not be passed

Io
IN OUT
317
ADJ
D1 R1

Vi C1 1.25 V
C3 RL
0.1 to 10 to
1 μF 20 μF
R2 C2
10 μF

Figure 4.10 317 IC linear regulator complete circuit schematic.

Chapter 04.indd 159 3/12/2009 3:50:05 PM

160 Power Electronics

through the regulator to the input side. Likewise the AC ripples present in the input side should not be
passed to the load side through the regulator. The AC components should be bypassed by using capacitors
that will provide low impedance paths for the AC components on either side. C1 and C3 are the input side
and the output side AC bypass capacitors, respectively. A capacitor C2 is connected between the ADJ pin of
the regulator and the circuit ground. This capacitor acts as a buffer to stabilize the fluctuations in the voltage
at the ADJ pin. This provides increased input ripple rejection. However, during turn OFF of the power
supply, the output capacitor C3 will discharge its charge to the load. The capacitor C2 will try to discharge
through the regulator. However, a large discharge current through the ADJ pin will damage the 317 IC. To
provide an alternate discharge path for the capacitor C2, diode D1 has been introduced. Capacitor C2 can
discharge through D1 into the output load. Diode D2 is a protection diode. During situations when the
input voltage suddenly becomes zero during power outage, the input output voltage differential across the
317 IC will become negative and will be equal to −Vo. This will damage the regulator IC. To prevent this,
D2 will ensure that the drop across the input and output of the regulator IC will be clamped to −0.7 V if
ever the output voltage increases beyond the input voltage thereby protecting the regulator IC.

Practical Tips
One of the main beneﬁts of the linear regulators is the high quality of performance. However, there are
integration issues that can have adverse eﬀects on the performance of the regulation. One such crucial issue
is the layout of the input side capacitor. The input side capacitor carries high peak currents as shown and
also discussed in the previous chapter. If the capacitor is laid out as shown in Figure 4.11(b), then the output
voltage is given as
Vo = Vreg + ic Rlead

Regulator

RL Vo

(a)

Regulator

a
Vreg RL Vo
Rlead

(b)

Figure 4.11 Loss of regulation due to incorrect layout of input capacitor

(a) correct; (b) incorrect.

Chapter 04.indd 160 3/12/2009 3:50:06 PM

DC–DC Linear Regulators 161

The term ic Rlead in the output voltage equation will cause de-regulation with load. Therefore care should be
taken to layout the input side capacitor such that it does not interfere with the regulation. The layout of
Figure 4.11(a) is correct and will not deteriorate the output regulation.
Another important layout issue that aﬀects the output regulation is shown in Figure 4.12 with respect to
the 317 IC regulators. In Figure 4.12(a), the lead resistance Rlead comes within the regulation loop of the IC
regulator and in Figure 4.12(b), the layout is such that the lead resistance through which the load current ﬂows
is out of the regulation loop of the IC regulator. For the layout of Figure 4.12(a), the output is given as
⎛ R ⎞ ⎛ R ⎞ ⎛ R ⎞
( )
Vo = 1.25 − I o Rlead ⎜ 1 + 2 ⎟ = 1.25 ⎜ 1 + 2 ⎟ − I o Rlead ⎜ 1 + 2 ⎟
⎝
(4.19)
R1⎠ ⎝ R1⎠ ⎝ R1 ⎠
For the layout of Figure 4.12(b), the output is given as
⎛ R ⎞
Vo = 1.25 ⎜ 1 + 2 ⎟ − I o Rlead (4.20)
⎝ R1 ⎠

From Eqs. (4.19) and (4.20) it is evident that in the case of layout of Figure 4.12(b), the term aﬀecting regu-
lation is only I o Rlead, whereas the term aﬀecting regulation in the case of layout of Figure 4.12(a) is

317
ADJ Rlead
R1
1.25 V

Vi RL Vo

(a)

317
ADJ Rlead
R1

Vi RL Vo

(b)

Figure 4.12 Effect of lead resistance in 317 IC or any variable IC regulator.

Chapter 04.indd 161 3/12/2009 3:50:06 PM

162 Power Electronics

I o Rlead [1 + ( R2 R1 )] which is higher than that for Figure 4.12(b). Therefore, the layout of Figure 4.12(b) is
the preferred layout.

Four-Wire Connection
Another important consideration in the linear regulators is the issue of high current loads. In the case of
high current loads, especially if they are located remotely, the lead resistance Rlead (Figure 4.13) will signifi-
cantly affect the output voltage regulation. Referring to the circuit schematic shown in 4.13, Vreg is the volt-
age that is regulated by the regulator. However, as the actual load is located remotely, the actual output
voltage is across the load resistor RL and is given as
Vo = Vreg − I o Rlead (4.21)
From Eq. (4.21), it is evident that the actual output voltage is different from the regulated voltage Vreg by a
load-dependent term I o Rlead . This will make the output voltage regulation for changes in the load poorer.
A solution for this is the four-wire connection as shown in Figure 4.14. The regulator provides four
output terminals 1−4 as indicated in Figure 4.14, viz., (a) positive rail or + power terminal; (b) positive

Rlead

−
Vi Vreg RL Vo
+

Vref

Figure 4.13 Effect of lead resistance in high current regulators.

1+ io
2 Rlead
100 Ω
S+

− Vreg RL Vo
Vi
+

Vref
3
100 Ω
S− Rlead

4−

Figure 4.14 Four-wire connection for high current linear regulators.

Chapter 04.indd 162 3/12/2009 3:50:06 PM

DC–DC Linear Regulators 163

of the output voltage sense or S+ terminal; (c) negative of the output voltage sense or S− terminal and
(d) negative rail or − power terminal.
The load current ﬂows through the positive rail terminal, through the load and ﬁnally returns through the
negative rail terminal. The actual output voltage Vo is sensed by the sensing leads that are connected to termi-
nals 2 and 3. The currents through the sensing leads are very small as compared to the load current Io. There-
fore, the sense terminals will essentially measure the actual remote output voltage Vo. In this way, even the
drops across the lead resistances in the positive rail and negative rail are included inside the regulation loop,
thereby regulating the actual output Vo. Sometimes terminals 1 and 2 and terminals 3 and 4 are connected
with resistances of about 100 Ω as shown in Figure 4.14. This will enable either two-wire connections or four-
wire connections to be used depending on the remoteness of the load, wiring layout and lead resistances.

Protection
Protection circuitry is an integral part of any system for improving the availability of the system. The linear
regulator should, in general, be protected against the following:
1. over current;
2. over voltage;
3. reverse voltages;
4. reverse voltage drops across the series component.
For the shunt linear regulators, the series component is a ﬁxed resistor. The power rating of the resistor is
normally chosen to be
(Vi- max − Vz )2
PRs =
Rs

However, if the output gets short circuited, then the entire output voltage will drop across the series resistor.
The dissipation will exceed the rated power dissipation and damage the series component. To take care of
this extreme situation, the series resistor Rs in the case of the shunt regulator should have a power rating of

Vi-2max
PRs =
Rs
For series regulators, Figure 4.15 shows a very simple and eﬀective current protection scheme. Two compo-
nents, transistor Q s and current resistor Rs are used for current protection. The current sense resistor is
chosen such that when the load current limit is reached, the voltage drop across it is 0.5 V. Any further
increase in the load current will increase the drop across Rs which in turn increases the base−emitter voltage
of Q s. This increased base−emitter voltage will make Q s to draw increased collector current. As the current
through Rb is a current source, the increase in the collector current drawn by Q s is at the expense of the base
current of Q1. Thus, as the drive to Q1 decreases, Q1 presents a higher resistance to the input source and the
drop across Q1 increases thereby decreasing the output voltage and load current. In this manner, the combi-
nation of Rs−Q s will provide over current limiting in linear series regulators.
The over voltage protection is mainly to ensure that the load is not damaged. The over voltage may occur
if the series pass of the linear regulator is shorted or due to an electrostatic coupling at the output. The over
voltage protection is implemented by means of the crow-bar protection circuit as shown in Figure 4.16.
Under normal operating conditions, (a) the thyristor, Th1, is OFF, (b) the Zener diode Dcb is reverse-biased
and in OFF region and (c) the potential of the thyristor gate is zero. If for some reason the output voltage
goes beyond a particular limit, the Zener diode Dcb breaks down and a potential of [(Vo − Vz-cb ) / ( R1b + R2b )]R2b

Chapter 04.indd 163 3/12/2009 3:50:07 PM

164 Power Electronics

Rs Io
Q1

Rb
R1
Q3
Rz

Vi RL Vo
Q2

Figure 4.15 Current protection.

Fuse
Q1

Dcb Rcb

Vi Dr Vo
R1b Th1

R2b

Figure 4.16 Voltage protections.

is applied at the gate of the thyristor Th1. The thyristor turns ON and connects a small value resistance Rcb
across the output Vo, eﬀectively shorting the output with Rcb. This will bring down the output voltage
within safe limits. The thyristor switches OFF only after its current is brought below the holding current
value. For crowbar protection, a fuse is included in series with the input source. When the output is short
circuited due to the action of the Th1, the current from the input source increases and blows the fuse. This
will bring the current in the thyristor below the holding current value and switches OFF the thyristor Th1.
Alternately, this is done by switching OFF the input source Vi by turning OFF a series switch that can be
included in series with the input source or the current protection scheme of Figure 4.15 can be used. If Th1
turns ON due to over voltage condition, the current through the sense resistor Rs of Figure 4.15 will increase
and clamp at 0.7 V. Transistor Q s will be in ON-state and divert all the current from IRb to its collector. This

Chapter 04.indd 164 3/12/2009 3:50:07 PM

DC–DC Linear Regulators 165

will cut-oﬀ Q1 which will bring down the thyristor current below the holding value and turn OFF the thy-
ristor. However, it should be noted that if the output over voltage has occurred due to Q1 collector−emitter
short, then the current limit circuit will not work. In such cases either the fuse in series with the input will
blow or the collector−emitter of Q1 that was shorted will open.
Diode Dr is connected as shown in the ﬁgure to prevent any negative voltage being applied to the load.
Similar reverse diode may be connected at the input side to prevent any accidental reverse voltage being
applied to the positive rail regulator, thereby preventing any damage to the linear regulator and the load.
Diode D1 is used to prevent any negative voltage drop occurring across the series-pass element. This can
happen when the input is turning OFF and the output capacitor is still holding charge. Under these condi-
tions, diode D1 will conduct and clamp the voltage across the series-pass element to −0.7 V.

Current Regulation
Till now, the linear regulators for output voltage regulation are discussed. However, similar principles can be
used for regulating the output current to obtain a current source. The main principle in a current regulator
is shown in Figure 4.17(a). Here the voltage across a resistor VR is held constant by means of a voltage regu-
lator that may be a shunt or a series regulator. This makes the current VR/R through that resistor constant
which is directed to the output as the load current.
Figure 4.17(b) shows the circuit implementation of the current regulator. A modiﬁed shunt regulator
with a PNP transistor is used in the circuit schematic of the current regulator. The voltage across the emitter
resistor Re is given as Vz − Vbe. The emitter current is therefore given as
Vz − Vbe
I Re = (4.22)
Re
From Eq. (4.22), it can be observed that Vz and Vbe are constants and hence the current through Re is a con-
stant. For a high b transistor, the current through the collector of the transistor Q is almost the same as IRe.
This current ﬂows through the connected load resistor RL as a constant current developing an output voltage
of
⎛ V − Vbe ⎞
Vo = I L RL = ⎜ z ⎟ RL (4.23)
⎝ Re ⎠

+
Re
Vz
−
Reg
VR / R Q
VR R Vi
IL
Vi IL
Rz

RL RL Vo

(a) (b)

Figure 4.17 (a) Current regulation principle; (b) current regulator circuit schematic.

Chapter 04.indd 165 3/12/2009 3:50:07 PM

166 Power Electronics

The maximum output voltage that can develop is given by

Vo-max = Vi-max − Vz + Vbe (4.24)

4.3 Parameters of the Linear Regulator

T he following four parameters of the linear regulator determine the quality of the regulator:

1. efficiency;
2. line regulation;
3. load regulation;
4. temperature regulation.
The first parameter is related to the power delivered to the output with respect to the power consumed from
the source. This primarily affects the volumetric power density of the linear regulator. The power dissipated
in the series-pass element determines the size of the heat sink that needs to be employed to ensure proper
heat flow to the ambient. The remaining three parameters provide quantitative measures for the perfor-
mance quality of the output voltage. This performance quality of the linear regulator is measured by regula-
tion of the output voltage for (a) variations in the line, (b) variations in load and (c) variations in temperature.
This is mathematically represented as
∂Vo ∂V ∂V
ΔVo = ΔVi + o ΔI o + o ΔT (4.25)
∂Vi ∂I o ∂T

where ∂Vo / ∂Vi is the line-regulation coefficient with Io and T constant; ∂Vo / ∂I o the load-regulation coef-
ficient with Vi and T constant; ∂Vo / ∂T the temperature-regulation coefficient with Vi and Io constant. For
any linear regulator selection, these four important parameters are essential and need to be quantified and
specified. The analysis of the regulators will also focus on these parameters.

4.4 Analysis of a Series Regulator

T ill now, the regulator circuits were discussed in an operational sense wherein one could design and
implement the regulator circuits. However, to obtain greater insight into the operation of the regulator
so that one may improve the circuits, a more systematic method of analysis has to be performed. In this sec-
tion, a systematic analysis will be performed on a series linear regulator circuit (shown in Figure 4.18). The
analysis will bring out the problems in this topology and will also suggest remedial measures that can be
taken to address the issues. Without loss of generality, a similar approach may be used to analyze other linear
regulator circuits.

First-Level Modeling
To analyze the regulator shown in Figure 4.18, the transistor and the Zener diode are replaced by the first-
level idealized model. The first-level model for the transistor and the Zener diode are shown in Figure 4.19.
For the NPN transistor shown in Figure 4.19(a), the first-level model is shown in Figure 4.19(b). The collec-
tor current is a dependent current source of value bib. The first-level model of a Zener diode is a DC source
of value Vz as shown in Figure 4.19(d).

Chapter 04.indd 166 3/12/2009 3:50:08 PM

DC–DC Linear Regulators 167

Io
Q1

Rb
R1
Rz

Vi RL Vo
Q2

R2
Vz

Figure 4.18 Linear series regulator.

ic ie
bib = ic
ie

ib ib

(a) (b)

Vz Vz

Figure 4.19 (a) NPN transistor; (b) NPN transistor first-level model;
(c) Zener diode; (d) first-level model of Zener diode.

Referring to Figure 4.18, both the transistors Q1 and Q2 are replaced by their first-level model. Similarly,
the Zener diode is also replaced by its first-level idealized model. The resulting equivalent circuit is shown in
Figure 4.20.
By applying Thevenin’s theorem to the base portion of the transistor Q2 of Figure 4.20, the modified
equivalent circuit representation of the series regulator is obtained as shown in Figure 4.21.
Referring to Figure 4.21, the base current of Q2 is given as

Vo [ R2 / ( R1 + R2 )] − Vz Vo ⎛ R + R2 ⎞
ib2 = = − Vz ⎜ 1 ⎟ (4.26)
R1 //R2 R1 ⎝ R1R2 ⎠

Chapter 04.indd 167 3/12/2009 3:50:08 PM

168 Power Electronics

b1ib1

Io
Rb ib1

irb
Rz R1

b2ib2
Vi RL Vo

ib2

Vz R2

Figure 4.20 Equivalent circuit of the series regulator using the first-level
models of the transistor and the Zener diode.

b1ib1

Rb ib1

irb

Rz
b2ib2
Vi RL Vo

R1//R2

ib2
R2
Vz Vo
R1 + R2

Figure 4.21 Equivalent circuit of the series regulator.

The current through Rb is given as

V i − Vo
irb =
Rb (4.27)

Chapter 04.indd 168 3/12/2009 3:50:08 PM

DC–DC Linear Regulators 169

ib1 = irb − β2ib2

Vi − Vo ⎧⎪ Vo ⎛ R + R2 ⎞ ⎫⎪
= − ⎨β2 − β2Vz ⎜ 1 ⎟⎬ (4.28)
Rb ⎪⎩ R1 ⎝ R1R2 ⎠ ⎭⎪

The regulating action of the series regulator is deﬁned by Eq. (4.26). If the output voltage Vo increases,
then ib2 increases. An increase in ib2 will cause a decrease in ib1 as seen from Eq. (4.28). This in turn will
reduce the base drive for Q1 which will present a higher resistance to the input source. As a consequence,
the collector−emitter of Q1 will drop more voltage and the output voltage will reduce and return back to
the equilibrium state. A similar regulating action occurs when the output voltage Vo decreases.
The output voltage is given as

Vo = (ib1 + β1ib1 )RL = (β1 + 1)ib1RL

⎡ V − Vo V ⎛ R + R2 ⎞ ⎤
= (β1 + 1)RL ⎢ i − β2 o + β2Vz ⎜ 1 ⎟⎥ (4.29)
⎢⎣ Rb R1 ⎝ R1R2 ⎠ ⎥⎦

The output relationship as given in Eq. (4.29) is re-arranged such that it is of the form
Vo = k1Vi + k2Vz (4.30)
where
( β1 + 1)RL / Rb
k1 =
[( β1 + 1)RL / Rb ] + [( β1 + 1)β2 ( RL / R1 )]+ 1

and
( β1 + 1)β2 RL [( R1 + R2 ) / R1R2 ]
k2 =
[( β1 + 1)RL / Rb ] + [( β1 + 1)β2 ( RL / R1 )] + 1

It should be noted that in the above derivation for Vo, the load current Io is taken as ( β1 + 1)ib1. However, Io
is actually ( β1 + 1)ib1 − iR1 where iR1 is the current through R1. Referring to Figure 4.20, this is given as
(Vo − Vz ) / R1 . As R1 is large, iR1 is neglected in the above ﬁrst-level derivation for Vo. However, in later dis-
cussions, the contribution of iR1 to the load current is also considered.
Referring to Eq. (4.30), there are a few conclusions that one can draw at this point of the analysis. If Vo
is to be independent of the input source Vi, then k1 should be zero and k2 should be a constant. The factor
k1 can be written as 1
k1 =
1 + β2 ( Rb / R1 ) + [ Rb / ( β1 + 1)RL ]

In this equation, only the term β2 ( Rb / R1 ) is greater than unity. If the transistor Q2 is chosen as a high gain
transistor, then b2 will be high. In fact, b2 will be much higher than the ratio of Rb/R1. As a consequence,
this term will be much greater than 1 and thus
k1 1 (4.31)
The factor k2 in Eq. (4.30) can be written as
β2 [( R1 + R2 ) / R1R2 ]
k2 =
(1 / Rb ) + β2 (1 / R1 ) + [1 / ( β1 + 1)RL ]

Chapter 04.indd 169 3/12/2009 3:50:09 PM

170 Power Electronics

Due to the b2 terms both in the numerator and the denominator, the value of k2 is signiﬁcant and
k2 k1 (4.32)
From the inequalities in Eqs. (4.31) and (4.32), one can say that the term k1Vi is negligibly small. Thus

Vo ≈ k2Vz
which is a regulated voltage.

Effect of Current through Rb

From Figure 4.21, it can be observed that the current through the base of the series-pass transistor Q1 is

ib1 = irb − β2ib2

where
Vo ⎛ R + R2 ⎞
ib2 = − Vz ⎜ 1 ⎟
R1 ⎝ R1R2 ⎠

If R1, R2, Vz and Vo are constants, then ib2 will be a constant. For a given temperature, b1 can also be consid-
ered to be a constant. Therefore, the term β2ib2 in the ib1 equation is a constant and does not contribute to
loss of regulation. The other term in the ib1 equation is the current through Rb. This is given as
V i − Vo
irb = (4.33)
Rb
In Eq. (4.33), one can observe that irb is a function of both Vi and Vo. If Vi varies, irb also varies and hence
ib1 varies which in turn causes Vo to vary as

Vo = ( β1 + 1)ib1RL (4.34)

Therefore from Eqs. (4.33) and (4.34) it is evident that the loss of output regulation is due to irb not being
a constant in the face of variations in Vi.
The solution to this is as follows: It is required that irb is constant and independent of variations in
the input source voltage Vi. If this is achieved then ib1 and hence Vo will become independent of variations in the
input source voltage Vi. One possible method to make irb independent of variations in Vi is to replace the resis-
tor Rb by a constant-current source as illustrated in Figure 4.17(b). The constant-current source circuit is inte-
grated into the series regulator circuit and the resulting modiﬁed circuit is depicted in Figure 4.22.
The operation of the constant-current source portion is as discussed in the section “Current Regulation”.
The current irb is now a constant that is independent of variations in the input voltage Vi. Now the output
voltage Vo is given as
Vo = (ib1 + β1ib1 )RL = ( β1 + 1)ib1RL
⎡ V ⎛ R + R2 ⎞ ⎤
= ( β1 + 1)RL ⎢irb − β2 o + β2Vz ⎜ 1 ⎟⎥ (4.35)
⎢⎣ R1 ⎝ R1R2 ⎠ ⎥⎦

From Eq. (4.35), it can be observed that as irb is a constant, Vo is essentially independent of Vi and depends
only on Vz.

Chapter 04.indd 170 3/12/2009 3:50:09 PM

DC–DC Linear Regulators 171

Constant-current source
Q1

Re
Vz1

R1
Q3
irb
Vi RL Vo
Rz1

Rz Q2

R2
Vz

Figure 4.22 Series regulator circuit: Rb is replaced by a constant-current source.

Effect of Current through R1

In the discussions till now, the output load current Io is considered to be ( β1 + 1)ib1 wherein the current
through R1 is neglected. If the current through R1 is also considered in the output voltage equation with
respect to the series regulator equivalent circuit of Figure 4.21, then Vo is given as

Vo = [(β1 + 1)ib1 − iR1 ]RL

⎡ ⎛ V − Vz ⎞ ⎤
( )
= ⎢ β1 + 1 ib1 − ⎜ o
⎝ R1 ⎠ ⎥⎦
⎟ ⎥ RL (4.36)
⎢⎣

Substituting for ib1 from Eq. (4.28) into Eq. (4.36), one obtains

⎡ V − Vo V ⎛ R + R2 ⎞ ⎤ ⎛ Vo − Vz ⎞
Vo = (β1 + 1)RL ⎢ i − β2 o + β2Vz ⎜ 1 ⎟⎥−⎜ ⎟ RL
⎢⎣ Rb R1 ⎝ R1R2 ⎠ ⎥⎦ ⎝ R1 ⎠

The above equation for Vo can be re-arranged in the following form:

Vo = k1Vi + k2Vz (4.37)

where
(β1 + 1)RL / Rb
k1 =
(β1 + 1)( RL / Rb ) + (β1 + 1)β 2 ( RL / R1 ) + ( RL / R1 ) + 1

and
(β1 + 1)β2 RL [( R1 + R2 ) / R1R2 ] + ( RL / R1 )
k2 =
(β1 + 1)( RL / Rb ) + (β1 + 1)β2 ( RL / R1 ) + ( RL / R1 ) + 1

Chapter 04.indd 171 3/12/2009 3:50:10 PM

172 Power Electronics

The load current Io is given as

Vo ⎡ V − Vo V ⎛ R + R2 ⎞ ⎤ ⎛ Vo − Vz ⎞
Io = = ( β1 + 1) ⎢ i − β2 o + β2Vz ⎜ 1 ⎟⎥−⎜ ⎟
RL ⎢⎣ Rb R1 ⎝ R1R2 ⎠ ⎥⎦ ⎝ R1 ⎠

which can be re-arranged as

(β1 + 1) ⎛ (β + 1) (β1 + 1)β2 1 ⎞ ⎡ ⎛ R + R2 ⎞ 1 ⎤
Io = Vi − ⎜ 1 + − ⎟ Vo + ⎢( β1 + 1)β2 ⎜ 1 ⎟ + ⎥V z (4.38)
Rb ⎝ Rb R1 R1 ⎠ ⎢⎣ ⎝ R1R2 ⎠ R1 ⎥⎦

Regulator Parameters
The regulation parameters, viz., line-regulation coefficient, load-regulation coefficient and temperature-
regulation coefficient can be estimated based on the equations for Vo and Io as given in Eqs. (4.37) and (4.38).

Line-Regulation Coefficient
The line-regulation coeﬃcient can be obtained from Eq. (4.37). It is the variation of the output voltage Vo
for variations of the input voltage Vi under the constraints of constant load and temperature. It is given as

∂Vo ( β1 + 1)RL / Rb
= (4.39)
∂Vi (β1 + 1)( RL / Rb ) + (β1 + 1)β2 ( RL / R1 ) + ( RL / R1 ) + 1

In the case of the modiﬁed series regulator circuit wherein the resistor Rb is replaced by a constant-current
source, irb is a constant. From Eq. (4.35), it can be observed that Vo is independent of Vi and therefore,

∂Vo
=0
∂Vi
Load-Regulation Coefficient
The load-regulation coeﬃcient is a measure of the change in the output voltage Vo for changes in the load Io
under the constraints of constant temperature and input voltage Vi. The load-regulation coeﬃcient can be
obtained from Eq. (4.38). Thus,
∂I o ⎛ β + 1 ( β1 + 1)β 2 1 ⎞
= − ⎜⎜ 1 + − ⎟⎟
∂Vo ⎝ Rb R1 R1 ⎠

The inverse of the above equation will give the load-regulation coeﬃcient. This is given as

∂Vo Rb R1
=− (4.40)
∂I o (β1 + 1)R1 + (β1 + 1)β 2 Rb − Rb

Here ∂Vo / ∂I o is a measure of the output resistance Ro of the regulator circuit. The negative sign in Eq. (4.40)
does not mean that Ro is negative, but it implies that the nature of the change in Vo with respective to changes
in Io is opposite in phase, that is, if Io increases by DIo, Vo decreases by DVo and this is equal to ΔI o Ro.
From Eq. (4.40), it can be observed that the denominator contains a term that is a product of the bs, that
is, the current gains of the transistors Q1 and Q2. This implies that Ro value is a very small value such that
Ro 1. If Q1 and Q2 are chosen such that their current gains are high, then Ro can be negligibly small.

Chapter 04.indd 172 3/12/2009 3:50:10 PM

DC–DC Linear Regulators 173

In the case of the modiﬁed series regulator circuit wherein Rb is replaced by a constant-current source
circuit, the load-regulation coeﬃcient is given as

∂Vo R1
=− (4.41)
∂I o ( β1 + 1)β2 − 1

Temperature Effects
In the ﬁrst-level modeling, as the transistors and the Zeners are considered as ideal. There is no contribution
from these elements to the output voltage variations due to temperature changes. However, there will be
changes in the output voltage for temperature changes due to variations in the value of the resistors with
temperature. The eﬀect of temperature variations on the output voltage is discussed later while considering
non-ideal transistors and Zeners in the second-level model.

Problem 4.2
Consider a linear series regulation with R1 = 3.6 kΩ, R2 = 2 kΩ, Rb = 3.6 kΩ, Rz = 20 kΩ, Vz = 6.55 V,
RL = 1 kΩ, Vi = 20 V to 30 V, Vi-nominal = 25 V, b1 = b2 = 100. Calculate the output voltage a load change of
0.1 A to 0.2 A.

Solution
Applying the values to the variables in Eq. (4.37), one obtains

Vo = 9.89 × 10−3Vi + 2.77Vz = 9.89 × 10−3Vi + 18.14

1. At Vi = 25 V, Vo = 18.39 V
2. At Vi = 20 V, Vo = 18.3378 V
3. At Vi = 30 V, Vo = 18.4367 V
For a change of 10 V in Vi, the change in output voltage is 0.0989 V.

∂Vo 3600 × 3600

Ro = =− = 0.3529 Ω
∂I o 101× 3600 + 101× 100 × 3600 − 36600

For a load change of 0.1 A to 0.2 A,

DVo = 0.3529 × 0.1 = 0.03529 V
which is about 0.2% of Vo.

Range of Load Resistance RL

Referring to the output voltage in Eq. (4.37), both k1 and k2 factors are functions of RL. Therefore the
output voltage Vo is not independent of RL. Dividing the numerator and denominators of k1 and k2 by RL,
a term 1/RL is present in the denominator of both k1 and k2. Referring to the denominators of k1 and k2 of
the output voltage Eq. (4.37), if

Chapter 04.indd 173 3/12/2009 3:50:10 PM

174 Power Electronics

⎧⎪ 1 1 1 ⎫⎪ 1
⎨( β1 + 1) + ( β1 + 1)β2 + ⎬
⎩⎪ Rb R1 R1⎪
⎭ RL

then the output voltage is not affected significantly by RL. As RL approaches infinity, that is, the series
regulator approaches open circuit condition, 1/RL anyway approaches zero and the above inequality
constraint is easily met thereby making Vo independent of RL. However, as RL decreases, that is, the
series regulator approaches the full-load or overload conditions, the dependency of Vo on RL is more
significant.
For Problem 4.2, wherein R 1 = 3.6 kΩ, R 2 = 2 kΩ, R b = 3.6 kΩ, R z = 20 kΩ, V z = 6.55 V,
RL = 1 kΩ, Vi = 20 V to 30 V, Vi-nominal = 25 V, b1 = b2 = 100, one can apply the inequality constraint
given above. Thus,

1 1 1
( β1 + 1) + ( β1 + 1)β2 + = 2.834
Rb R1 R1

1 1
= = 1 × 10−3
RL 1000

It can be observed that 1/RL is much less than 2.834 and hence the output voltage can be considered to
be reasonably independent of RL. However if RL approaches the short circuit condition, Vo will lose
regulation.

Second-Level Modeling
Till now the insights about the series regulator were obtained based on the idealized ﬁrst-level models for the
transistors and the Zener diode. However, there are many non-idealities in the semiconductor devices. If the
dominant non-idealities are included in the device models, then the insights obtained and the conclusions
about the circuit will be closer to reality. Figure 4.23 depicts the second-level models for the transistors and
the Zener diode. For the NPN transistor shown in Figure 4.23(a), the second-level equivalent circuit is
shown in Figure 4.23(b). The base-spreading resistance and the base-to-emitter junction potential are
included in the equivalent circuit. For the Zener diode of Figure 4.23(c), the second-level equivalent circuit
is shown in Figure 4.23(d). The Zener resistance, rz in the breakdown region is also included in the equiva-
lent circuit.
In the series regulator circuit of Figure 4.18, the second-level equivalent circuits are used to replace the
transistors and the Zener diode. The equivalent circuit of the series regulator with the second-level models
introduced is shown in Figure 4.24. Like in the case of the ﬁrst-level modeling, Thevenin’s theorem is
applied to the base circuit of transistor Q2. The reduced circuit after applying Thevenin’s theorem is shown
in Figure 4.25.
Referring to Figure 4.25, the base current of Q2 is given as

Vo [ R2 / ( R1 + R2 )] − Vbe2 − Vz − rz [(Vi − Vz ) / ( Rz + rz )]
ib2 = (4.42)
rb2 + R1 // R2 + ( β 2 + 1)rz

Chapter 04.indd 174 3/12/2009 3:50:10 PM

DC–DC Linear Regulators 175

bib

ic ie
Vbe
rb

ib ib

(a) (b)

rz
Vz
Vz

Figure 4.23 (a) NPN transistor; (b) NPN transistor second-level model;
(c) Zener diode; (d) second-level model of Zener diode.

Vbe1

Io
b1ib1 rb1
Rb
irb i b1
R1

Rz
b 2i b2

Vi RL Vo
r b2
Vbe2

R2
rz

Figure 4.24 Equivalent circuit of series regulator with second-level models.

The current through Rb is given as

Vi − (Vo + Vbe1 + ib1rb1 )
irb = (4.43)
Rb

ib1 = irb − β 2ib2 (4.44)

Chapter 04.indd 175 3/12/2009 3:50:10 PM

176 Power Electronics

Vbe1

Io
b1ib1 rb1
Rb
irb i b1

Rz
b 2i b2

Vi RL Vo
r b2 R1 //R2
Vbe2
Vo R2
(R1 + R2)
rz

Figure 4.25 Equivalent circuit of series regulator after circuit reduction.

The output voltage Vo is given as

Vo = (ib1 + β1ib1 )RL = ( β1 + 1)ib1RL (4.45)
The output relationship can be expressed in the form
Vo = k1Vi + k2Vz + k3Vbe1 + k4Vbe2 (4.46)
where
1 ⎧⎪ ⎛ RL ⎞ ( β1 + 1)β 2 RL [rz / ( Rz + rz )]Rb ⎫⎪
k1 = ⎨( β1 + 1) ⎜ ⎟+ ⎬
D ⎩⎪ ⎝ Rb + rb1 ⎠ [rb 2 + R1 // R2 + (β 2 + 1)rz }( Rb + rb1 ) ⎭⎪

1 ⎧ ( β1 + 1)β 2 RL [ Rz / ( Rz + rz )]Rb ⎫
k2 = ⎨ ⎬
D ⎩[rb 2 + R1 // R2 + ( β 2 + 1)rz ]( Rb + rb1 ) ⎭

1 ⎪⎧ ( β1 + 1)RL ⎫⎪
k3 = ⎨− ⎬
D ⎪⎩ Rb + rb1 ⎪⎭

1⎧ (β1 + 1)β 2 RL Rb ⎫
k4 = ⎨ ⎬
D ⎩[rb2 + R1 // R2 + (β 2 + 1)rz ]( Rb + rb1 ) ⎭

and
⎧ ( β + 1)RL ( β1 + 1)β 2 RL [ R2 / ( R1 + R2 )]Rb ⎫
D = ⎨1 + 1 + ⎬
⎩ Rb + rb1 [rb2 + R1 // R2 + ( β 2 + 1)rz ]( Rb + rb1 ) ⎭

Chapter 04.indd 176 3/12/2009 3:50:11 PM

DC–DC Linear Regulators 177

From Eq. (4.46), it is evident that Vo is dependent not only on Vi and Vz, but also on the base−emitter junc-
tion voltages of the transistors. It should be noted that when the non-idealities, that is, Vbe1, Vbe2, rz, rb1 and
rb2 are made equal to zero, the output voltage equation reverts back to the equation developed in the ﬁrst-
level model of the previous sub-section.

Influence of Vi on Output Voltage Regulation

From Figure 4.25, it can be observed that there are two parameters that are dependent on Vi and have a
strong influence on the output voltage. They are the following:
1. The current irb which is dependent on Vi, as can be seen from Eq. (4.43).
2. The current through Rz that biases the Zener diode is also dependent on Vi. This current flows through
rz which causes the drop across rz to change with Vi.
However, in the first-level model, rz is zero and, therefore, only irb variations contributed to the output volt-
age de-regulation.
The solution to this is as follows: The first dependency with respect to irb can be solved by using a con-
stant-current source circuit as discussed in the first-level model. This is shown in Figure (4.26). It should be
noted that even though irb is a constant and does not vary with variations in Vi, both the Zener voltage Vz1
and Vbe3 are temperature-dependent. Therefore irb has a dependency with respect to temperature variations.
However, the Zener can be selected to have a positive temperature coefficient and Q3 base−emitter junction
has negative temperature coefficient. If these two devices are appropriately chosen, the temperature depen-
dency of irb can be significantly reduced.
The second dependency is with respect to the current through rz. The current through the Zener break-
down resistance rz is due to contributions from

1. ( β2 + 1)ib2
Vi − Vz
2.
Rz + rz
The second contribution, wherein the current ﬂows from the input through Rz to bias the Zener diode, is
dependent on input voltage variations. To solve this dependency, the resistor Rz is re-located in such a
manner that the Zener bias current is drawn from the output side rather than the input side. As the output
is regulated, the Zener bias current becomes independent of the input voltage variations. Figure 4.26 illus-
trates the re-location of the Zener bias resistor Rz. After this relocation, the current through Rz is given as
(Vo − Vz ) / ( Rz + rz ) .

Effect of rz on Output Regulation

The current through rz has two components as discussed, viz., ( β2 + 1)ib2 and the bias current through Rz.
The variations in the drop across rz due to variations in Vi are solved by re-location of Rz. However, the
(β2 + 1)ib2 component of the current through rz also varies to de-regulate the output Vo. If this component
of current is made constant then the output voltage regulation action is lost. There are only two solutions,
viz., (a) make rz zero which is not practically possible or (b) do not allow the load-dependent component of
the current ( β2 + 1)ib2 to flow through rz. The latter solution is possible by use of a high impedance ampli-
fier like the op-amp. This solution is depicted in Figure 4.27. The op-amp has a very high input impedance
device. The current through the Zener diode is only the bias current component flowing through the resistor
Rz and no load-dependent component flows through it. Thus the reference is a constant and independent of
load variations.

Chapter 04.indd 177 3/12/2009 3:50:11 PM

178 Power Electronics

Q1
Re
Vz1
Rz R1

Vo RL Vo

Q2
Rz1

R2
Vz

Figure 4.26 Eliminating dependency on input voltage by using

constant-current source and relocating Rz.

Q1
Re Rz
Vz1 R1

−
Q3

Vi + RL Vo

Rz1 R2
Vz

Figure 4.27 Series regulator with op-amp.

There is another advantage in using an op-amp in the series regulator instead of the transistor Q2. In the
ﬁrst-level model, the range of RL depends on the inequality

⎧⎪ 1 1 1 ⎫⎪ 1
⎨( β1 + 1) + ( β1 + 1)β2 + ⎬
⎩⎪ Rb R1 R1⎪
⎭ RL

The gain of the op-amp is very high, of the order of 105 and greater. This makes β2 very large and the above
inequality is satisﬁed for even very low values of RL. As a consequence the output voltage regulation can be
achieved even at very high load, that is, very low RL. However, in this case the series pass should be rated for
high currents.

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DC–DC Linear Regulators 179

Influence of Temperature
There are four major parameters that are dependent on temperature. They are:
1. transistor current gains;
2. base−emitter junction potentials of transistors;
3. breakdown voltage of the Zener diode;
4. resistance variations.
From the output voltage in Eq. (4.46), it is evident that all these parameters will significantly affect the
output voltage regulation. The transistor current gain b increases with increase in temperature. One way to
minimize the effect of variations in b due to change in temperature is to make b as large as possible. The
large b will make the output Vo immune to changes in parameters. Another way is to use an op-amp as
shown in Figure 4.27. Due to its high gain, the dependency of Vo to changes in parameters due to tempe-
rature variations, is significantly reduced.
With regard to the base−emitter junction potential of transistors, the temperature coefficient is negative.
The Vbe of the transistor varies at the rate of −2.2 mV/°C rise in temperature. Zeners below 5.1 V generally
have negative temperature coefficient and Zeners above 5.1 V have positive temperature coefficients. Some
degree of temperature compensation can be achieved by choosing Zeners with positive temperature coeffi-
cient such that they negate the variations of Vbe with temperature changes.
Another solution to compensate for variations in Vbe is to use a diode D as shown in Figure 4.28(a). The
equivalent circuit for the base drive portion of Q2 by applying Thevenin’s theorem is shown in Figure 4.28(b).
The Thevenin voltage for the equivalent circuit of Figure 4.28(b) is given as

⎛ R2 ⎞ ⎛ R1 ⎞
Vth = Vo ⎜ ⎟ + VD ⎜ R + R ⎟
⎝ 1
R + R2⎠ ⎝ 1 2⎠

Q2 R1 //R2

rb2
Vbe2
R2
Vz Vth
Vz
D

(a) (b)

Figure 4.28 Using diode to compensate for temperature effects.

Chapter 04.indd 179 3/12/2009 3:50:12 PM

180 Power Electronics

Vo [ R2 / ( R1 + R2 )] + VD [ R1 / ( R1 + R2 )] − Vz − Vbe2
ib2 =
rb2 + R1 // R2

From the above equation for ib2, due to opposite signs for the diode voltage and the base–emitter voltage, a
certain degree of temperature compensation is achieved between the diode D and Vbe2 of the transistor Q2.
Alternately, yet another solution is to enclose Q1, Q2 and Vz in a constant temperature oven so that there
is no drift due to temperature. Though this solution is good for regulation performance, it is at the expense
of the eﬃciency of the series regulator. With regard to resistance variations with temperature, the only solu-
tion is to choose very tight tolerance resistors wherein the resistance value variations with temperature are
very small.

4.5 Analysis of a Current Regulator

T he modeling and analysis methodology followed in the previous section for the series regulator can be
applied for any other regulator too. In this section, the analysis is performed for a typical current regu-
lator. In the section “Current Regulation” the circuit and the operational principle of the current regulator
has been discussed. A current regulator based on PNP transistor is discussed. This current regulator is also
used in the series regulator to improve the output regulation performance as discussed in the previous sec-
tion. In this section, the analysis is performed on a current regulator with NPN transistor whose circuit
schematic is as shown in Figure 4.29.
The operation of this current regulator is exactly similar to that described in the section “Current
Regulation”. The voltage across Re is maintained constant and independent of the input voltage Vi. The
constant voltage across Re ensures a constant current through Re. This current flows as the output cur-
rent Io through RL. In a manner similar to that discussed for the series regulator, the first-level equivalent
circuit of the current regulator can be obtained by applying the first-level models for the transistor and
the Zener diode as illustrated in Figure 4.19. The first-level model for the current regulator is shown in
Figure 4.30.
From the model of Figure 4.30, the voltage across Re is Vz. The current through Re is given as

Vz
I Re = = ( β + 1)ib (4.47)
Re

Q Io
Re

Vi RL
Rz
Vz

Figure 4.29 Current regulator circuit.

Chapter 04.indd 180 3/12/2009 3:50:12 PM

DC–DC Linear Regulators 181

Re Io
bib
ib

Vi RL
Rz
VZ

Figure 4.30 Equivalent circuit of the current regulator with idealized models.

From Eq. (4.47), it is evident that a constant-current source is established as Vz is a constant. Referring
again to Figure 4.30, it can be observed that

Vo = I o RL (4.48)

V i − V z − Vo
iRz = (4.49)
Rz

Io
ib = (4.50)
β +1

iz = iRz − ib (4.51)
The output current Io is given as
Vz
Io = +i (4.52)
Re z
Substituting Eqs. (4.48)−(4.51) into Eq. (4.52), one obtains

(Vz / Re ) − [ I Re / ( β + 1)] + [(Vi − Vz ) / Rz ]

Io = (4.53)
1 / ( RL / Rz )
The output current Io can be re-arranged as
I o = k1Vi + k2Vz (4.54)
where
1 / Rz
k1 =
1 + ( RL / Rz )

(1 / Re ) − [1 / Re ( β + 1)] − (1 / Rz )
k2 =
1 + ( RL / Rz )

Chapter 04.indd 181 3/12/2009 3:50:13 PM

182 Power Electronics

It can be observed from the output current relationship of Eq. (4.54) that the output current Io is depen-
dent on Vi and the load resistance RL. It should be noted that Rz should be much larger in value than the
resistor Re to get eﬀective current regulation. This can be achieved by using higher current gain transistors
such that the base side currents become very small.

Line Regulation
The term line regulation for current regulators is associated with the variations of the output current Io for
variations in the input voltage Vi. The line-regulation coeﬃcient is expressed as

∂I o 1 / Rz 1
= = (4.55)
∂Vi 1 + ( RL / Rz ) RL + Rz

The variation of output current for variations in the input voltage can be signiﬁcantly reduced by increasing
the value of Rz. This implies that high b transistors should be selected such that the base side currents are
small, thereby allowing choice of higher values for Rz.

Range of RL
In the case of the current regulators, RL can easily extend up to short circuit at the lower end. However, at
the higher end, if RL is infinite, that is, open circuited, then no Io flows. Therefore there is an upper limit on
the value of the load resistor up to which the current regulation is effective. The load regulation is ensured as
long as the following inequality is satisfied.
Rz RL (4.56)

Problem 4.3
Consider a current regulator wherein Vi = 20 V to 30 V, Vi-nominal = 25 V, Vz = 5.1 V, Re = 10 Ω, RL = 10 Ω,
Rz = 3.6 kΩ and b = 100. How much should be the output voltage for regulation to be eﬀective?

Solution
From Eq. (4.54),
I o ≈ 0.5 A
The line-regulation coeﬃcient is given as

∂I o 1
= = 2.77 × 10−4
∂Vi RL + Rz

If RL increases to say 100 Ω, then Io cannot be maintained at 0.5 A. If Io were to be 0.5 A, then Vo = IoRL =
50 V. This is not possible as the maximum input voltage itself is 30 V. Therefore the output current will
invariably lose regulation. For regulation to be eﬀective, the output voltage should be less than the input
voltage.

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DC–DC Linear Regulators 183

Second-Level Modeling
The second-level models that include the dominant non-idealities of the semiconductor devices can be
introduced to obtain the second-level model of the current regulator circuit. The second-level models of the
transistor and the Zener diode are as discussed in the previous section and are illustrated in Figure 4.23.
Substituting these models in the current regulator circuit, the second-level model equivalent circuit is
obtained as shown in Figure 4.31.
Here the dominant transistor non-idealities like the base-spreading resistance and the base−emitter junc-
tion potential are introduced in the transistor model and the Zener breakdown resistance is introduced in
the Zener model.
Referring to the equivalent circuit of Figure 4.31, the current through Re is given as
Vz + iz rz − ibrb − Vbe
I Re = (4.57)
Re
The output current Io is given as
Vz + iz rz − ibrb − Vbe
I o = I Re + iz = + iz (4.58)
Re
From the output current given by Eq. (4.58), it can be noted that the term iz rz causes loss of regulation due
to the dependence of iz on Vi. The Zener current is given as

iz = iRz − ib

Here ib is constant for a constant Io. However, iRz depends on Vi and is given as

Vi − Vz − iz rz − Vo
iRz = (4.59)
Rz
If iRz is obtained from a constant-current source, then it becomes independent of Vi. This will make iz
independent of Vi which in turn will make the drop iz rz independent of Vi. As a consequence the output

ib Re Io
bib Vbe
rb

Vi RL
Rz iz rz
Vz

Figure 4.31 Equivalent circuit of the current regulator with dominant device non-idealities.

Chapter 04.indd 183 3/12/2009 3:50:13 PM

184 Power Electronics

Re Io

Vi RL

iRz
Vz

Figure 4.32 Current regulator circuit with Rz replaced by a constant-current source.

current Io becomes independent of Vi. The current regulator with the Rz replaced by a constant-current
source is shown in Figure 4.32.
The eﬀect of temperature on Vbe, Vz and b is similar to the discussion in the previous section on series
regulator. The solutions suggested are equally applicable here too.

| CONCLUDING REMARKS
The linear regulators are a class of DC−DC con- tion, the switched-mode converter topologies are
verters that are dissipative, have low efficiency, are the obvious choice.
bulky due to large heat sink requirements and also There are many commercial IC regulators that
have low power density. However, not withstand- incorporate all the features discussed in this chapter.
ing all the above disadvantages and more, when it Among the commercial IC regulators, the low drop-
comes down to the quality of the output voltage, out regulators are popular for applications demanding
there is no switched-mode converter topology that high performance and efficiency. The input−output
can even closely match the linear regulator differential voltage drop across the series-pass device is
performance. the cause for the loss of efficiency. The load current
Thus if an application demands high ripple rejec- multiplied by the input−output differential voltage
tion and low line-, load- and temperature-regulation drop across the series-pass device of the regulator is
coefficients, then linear regulator is way beyond any the dominant power dissipation of the regulator. In
other DC−DC converter and therefore must be the low dropout regulators this input−output differential
obvious choice. If compactness and high efficiency voltage is significantly lower around 0.5 V or 0.7 V.
are the governing constraints for a specific applica- As a consequence the efficiency is improved.

| LABORATORY EXERCISES
1. Consider the series regulator circuit shown in Mode of implementation: The above circuit
Figure 4.33. The input is a variable DC power can be studied by
supply that represents the unregulated DC a. Simulation in Spice
input voltage. b. Simulation in SciLAB
c. Hardware bread-boarding

Chapter 04.indd 184 3/12/2009 3:50:14 PM

DC–DC Linear Regulators 185

Q1
Rb
R1
Rz
Vi Q2 Vo RL

R2
Vz

Figure 4.33 Series regulator circuit.

Tasks for study: (i) Instead of connecting one end of Rb to the

(a) Rig up the series regulator circuit as shown input voltage, connect Rb to another fixed
in Figure 4.33 with appropriately selected voltage source. Vary the input voltage
components values. source keeping load fixed and tabulate Vi,
(b) Connect an appropriate load resistor across Vo and Io. From the tabulated results, esti-
the output terminals. mate the line-regulation coefficient. How
(c) Keeping the output load resistor fixed, vary does it compare with the line-regulation
the input voltage and tabulate Vi, Vo and Io. estimate of Step (e)?
(d) Keeping the input voltage at a fixed value, (j) Instead of connecting one end of Rz to the
vary the load resistor and tabulate Vo and Io. input voltage, connect Rz to the output.
Evaluate line and load regulation and
(e) From the tabulated results, estimate the
compare with those evaluated in Step (e).
line- and load-regulation coefficients.
(k) Incorporate a current protection circuit
(f ) From the tabulated results, evaluate the effi-
with the help of an additional NPN tran-
ciency of the linear regulator at various loads
sistor and a current sense resistor.
and input voltages. Plot the efficiency versus
(l) Replace Q2 with a Darlington BJT (like
input voltage using load as a parameter.
TIP122). Measure the effect on the range
(g) Vary R1/R2 ratio and observe the effect on of the load resistor.
the output voltage.
(h) Measure the voltage across Rb for different 2. Consider the three-pin IC regulator circuit
values of the input voltage. Plot the cur- shown in Figure 4.34. The input is a variable
rent through Rb versus Vi. DC power supply that represents the unregu-
lated DC input voltage.

78××
IN OUT
IC

Vi Vo RL

78×× 7805−5 Vreg

7815−15 Vreg

Figure 4.34 Three-pin 78xx series IC regulator.

Chapter 04.indd 185 3/12/2009 3:50:14 PM

186 Power Electronics

Mode of implementation: The above circuit (h) What is the minimum value of the input
can be studied by voltage for which the output is regulated?
a. Simulation in Spice
3. Consider the 723 IC regulator circuit shown
b. Hardware bread-boarding
in Figure 4.35. The input is a variable DC
Tasks for study: power supply (Vcc) that represents the unreg-
(a) Rig up the circuit as shown in Figure 4.34 ulated DC input voltage. Rsc is the current
using either 7805 or 7815 regulator IC. sense resistor that is used for over-current
(b) Study the data sheet and connect an protection.
appropriate load resistor across the output
Mode of implementation: The above circuit
terminals.
can be studied by
(c) Keeping the output load resistor fixed,
a. Simulation in Spice
vary the input voltage and tabulate Vi, Vo
b. Hardware bread-boarding
and Io.
(d) Keeping the input voltage at a fixed Tasks for study:
value, vary the load resistor and tabulate (a) Study the data sheet of 723 regulator IC.
Vo and Io. (b) Rig up the IC regulator circuit as shown in
(e) From the tabulated results, estimate the Figure 4.35.
line- and load-regulation coefficients. (c) Connect an appropriate load resistor across
(f ) From the tabulated results, evaluate the the output terminals (start with 1 kΩ).
efficiency of the linear regulator at various (d) Measure the voltage at pin “Vref ”. What is
loads and input voltages. Plot the effi- its value? Does it agree with the data sheet
ciency versus input voltage using load as a value?
parameter. (e) Keeping the output load resistor fixed,
(g) From the tabulated results plot the effi- vary the input voltage and tabulate Vi, Vo
ciency versus input−output differential and Io.
voltage.

Vcc(15 V)

Vcc Vc

4.7 kΩ Vref
Vo
NON
INV 723
4.7 kΩ R2 IC 1 Ω Rsc
INV
CL
COMP
12 kΩ
CS
GND RL

12 kΩ

Figure 4.35 Circuit schematic of 723 IC regulator.

Chapter 04.indd 186 3/12/2009 3:50:15 PM

DC–DC Linear Regulators 187

(f ) Keeping the input voltage at a fixed Mode of implementation: The above circuit
value, vary the load resistor and tabulate can be studied by
Vo and Io. a. Simulation in Spice
(g) From the tabulated results, estimate the b. Simulation in SciLAB
line- and load-regulation coefficients. c. Hardware bread-boarding
(h) From the tabulated results, evaluate the Tasks for study:
efficiency of the linear regulator at various (a) Rig up the current regulator circuit as
loads and input voltages. Plot the efficiency shown in Figure 4.36 with appropriately
versus input voltage using load as a param- selected components values.
eter. (b) Connect an appropriate load resistor across
(i) Vary R1/R2 ratio and observe the effect on the output terminals.
the output voltage. (c) Keeping the output load resistor fixed,
( j) Change the reference voltage applied to vary the input voltage and tabulate Vi, Vo
the “NON INV” pin of the IC. What hap- and Io.
pens to the output? (d) Keeping the input voltage at a fixed
(k) Rsc is the current sense resistor for current value, vary the load resistor and tabulate
protection. Decrease the load resistor value Vo and Io.
and monitor the voltage across the resistor (e) From the tabulated results, calculate the
Rsc. At what value of the load resistor does variation of the output current with respect
current limit come into operation? to the input voltage variation and load
( l) Increase the load current capability by con- variation.
necting an external BJT. Connect the base (f ) From the tabulated results, evaluate the
of the external BJT to “Vo” pin of the IC, efficiency of the linear regulator at various
the collector to “Vc” pin of the IC and the loads and input voltages. Plot the effi-
emitter to the junction of the “CL” pin and ciency versus input voltage using load as a
one terminal of Rsc. By how much is the parameter.
load current capability increased? (g) Change Re and observe the effect on the
4. Consider the current regulator circuit shown in output current.
Figure 4.36. The input is a variable DC power (h) Increase Ro from zero and observe the effect
supply that represents the unregulated DC on the output current. At what value of Ro
input voltage. does the output current lose regulation?

Vcc

Re
Vz

Io
Rz
Ro

Figure 4.36 Current regulator circuit.

Chapter 04.indd 187 3/12/2009 3:50:15 PM

188 Power Electronics

| FILL IN THE BLANKS

1. In linear regulators the power semiconductor 11. The no-load condition for the current regulator
devices are operated in the _______ region. is when the output resistor value is _______.
2. The output DC voltage value is always _______ 12. Efficiency primarily affects the volumetric
than the input unregulated DC voltage value. _______ of the linear regulator.
3. Even though the linear regulators have low 13. The power dissipated in the series-pass element
_______, the quality of the output voltage with determines the size of the _______ that needs
respect to the variations in _______, _______ to be employed.
and _______ are better than switched-mode
14. The first-level model for the transistor is a three-
regulator.
wire node with the collector current being a
4. In a simple shunt regulator, the shunt com- _______ current source of value _______.
ponent is a _______ that is operated in the
15. The first-level model of a Zener diode is a
_______ region.
_______ source of value _______.
5. In a shunt regulator, the output voltage is
16. For a series regulator, as the output resistor
regulated by virtue of the Zener diode being
value approaches infinity, the output voltage is
operated in the _______ region.
_______ of load.
6. The current absorbs the changes in the _______
17. For a series regulator, as the output resistor
and _______ currents.
value approaches zero, the output voltage
7. In a shunt regulator, under no-load condition, becomes more and more _______ on load.
the whole input current flows into the _______.
18. Th e second-level model for the transistor
8. A transistor or BJT operating in the linear includes the _______ and the base−emitter
region can be used as a _______ element in a _______.
series regulator.
19. The second-level model of a Zener diode
9. If the input voltage is a constant, then the current includes the _______.
through the bias resistor Rb of the series regulator
20. The load regulation of a current regulator is
can be considered as a _______ current.
ensured as long as _______.
10. Current regulators are built using _______
regulators.

| DESCRIPTIVE QUESTIONS
1. How are voltage scaling and regulation achieved 4. Explain the operation of a Zener-based shunt
in a linear regulator? regulator.
2. What is the eﬃciency of a generic linear regu- 5. Discuss the operation of the series regulator.
lator?
6. Discuss the eﬀect of input voltage variation on
3. What are the various linear regulator topologies? the output voltage.

Chapter 04.indd 188 3/12/2009 3:50:15 PM

DC–DC Linear Regulators 189

7. Draw a circuit schematic of a negative voltage 19. What is the effect of the current flowing through
regulator and explain its operation. the output sense resistors R1 and R2 on the
output voltage?
8. What are the categories of the IC linear regula-
tors? Give examples for each category. 20. What is the range of the load for a series linear
regulator?
9. What is four-wire connection in linear regula-
tors and why is it needed? 21. What is the effect of the output resistor RL on
the output voltage regulation?
10. Discuss the protection features needed to be
incorporated in the linear regulator circuits. 22. Discuss the constraints on the range of the
output resistor, RL.
11. Give a current protection circuit for a series linear
regulator. If the load over-current limit is to be 23. What are the second-level models for BJT and
set at 5 A, then choose the components of the Zener diode?
protection circuit.
24. Using the second-level model of the series regu-
12. Explain the operation of the crow-bar voltage lator, discuss the effect of Vi on the output
protection circuit. regulation.
13. What are the quantitative measures of a linear 25. Does the Zener breakdown resistance rz have an
regulator that determine its quality? effect on the output voltage regulation? Explain.
14. Define line-regulation, load-regulation and 26. What are the parameters of the series regula-
temperature-regulation coefficients for a linear tor that are affected by temperature? What is
regulator. the effect of temperature on output voltage
regulation?
15. In the analysis of linear regulators, what is first-
level modeling? 27. How does one compensate for the temperature
variation of the BJT’s base−emitter junction
16. What are the first-level models for BJT and Zener
potential?
diode?
28. How does one compensate for the Zener diode’s
17. In a series regulator, using the first-level model,
breakdown voltage variation with temperature?
what is the relation between output and the
base current of the series-pass transistor?
18. In a series regulator, how is the current through
the bias resistor Rb made independent of the
input voltage?

| PROBLEMS
1. A linear regulator is used to regulate an un- source? What is the eﬃciency of the linear
regulated DC source with nominal voltage regulator?
of 15 V. The shunt resistor value is 100 Ω and
the series resistor value is 250 Ω. A load resis- 2. For Problem 1, if there is no shunt resistor, then
tor of 1 kΩ is connected across the output. what is the output voltage? What is the input
What is the output voltage? What is the input power drawn from the unregulated input source?
power drawn from the unregulated input What is the eﬃciency of the linear regulator?

Chapter 04.indd 189 3/12/2009 3:50:15 PM

190 Power Electronics

3. Consider a Zener shunt regulator circuit wherein is the power rating of the series resistance used
the input voltage Vi varies between 10 V and in the regulator? What is the load resistor
20 V and the Zener diode used is a 5 V, 1 W range? If the Zener has a breakdown resis-
device. If the maximum allowable Zener current tance of 0.1 Ω, what is the output voltage
is 150 mA, then what is the value and power rat- variation?
ing of the series resistance used in the regulator?
7. For the current regulator circuit shown in
4. For Problem 3, what is the load resistor range? Figure 4.38, calculate the value of the load cur-
rent. What is the upper limit on the output
5. For the shunt regulator of Problem 3, if the
voltage?
Zener has a breakdown resistance of 0.1 Ω,
what is the output voltage variation? 8. For Problem 7, what is the range of the load
resistor?
6. Consider the shunt regulator circuit shown in
Figure 4.37. The Zener is a 1 W device with the 9. In a series regulator, the output voltage sens-
maximum allowable Zener current as 150 mA. ing resistors R1 and R2 are 5.6 kΩ each. The
The base−emitter voltage drop is 0.6 V. What output voltage is a regulated 15 V. The Zener

hFE = 100

Q
100 Ω
Io
10−20 V
5.1 V Vo
RL

Figure 4.37 Problem 6.

+
5Ω
5.6 V
− Q (b = 100)

12−18 V

Rz 1K
10 Ω Vo

Figure 4.38 Problem 7.

Chapter 04.indd 190 3/12/2009 3:50:15 PM

DC–DC Linear Regulators 191

diode value is 5.1 V. Using the fi rst-level 17. In a series regulator, the output voltage sensing
model, calculate the base current through the resistors R1 and R2 are 5.6 kΩ each. The output
transistor Q2. voltage is a regulated 15 V for a nominal input
voltage of 25 V. The Zener diode value is 5.1 V
10. The input voltage of a series regulator varies
and it is biased with a 20 kΩ resistor from the
between 20 V and 30 V. The output is a regu-
input. Using the second-level model, calculate
lated 15 V DC. If the bias resistor Rb has a
the base current through the transistor Q2.
value of 2 kΩ, then using the first-level model,
(Assume Vbe = 0.6, rb = 0.2 Ω for BJTs and rz =
estimate the nominal current through the bias
0.1 Ω for Zeners. The saturation current gains
resistor.
of Q1 and Q2 are 100.)
11. Consider a linear series regulator with R1 = 3.6 18. For Problem 17, the input voltage of a series
kΩ, R2 = 2.5 kΩ, Rb = 3.6 kΩ, Rz = 20 kΩ, regulator varies between 20 V and 30 V. The
Vz = 7 V, RL = 1 kΩ, Vi = 20 V to 30 V, output is a regulated 15 V DC. If the bias resis-
Vi-nominal = 25 V, b1 = b2 = 100. If the output tor Rb has a value of 2 kΩ, then using the
voltage is expressed as Vo = k1Vi + k2Vz , evalu- second-level model, estimate the nominal cur-
ate k1 and k2 using the first-level model. rent through the bias resistor for a load of 1 A.
12. In Problem 11, the current gain of Q1 is 19. Consider a linear series regulator with R1 =
increased to 1000. What is the effect on k1 and 3.6 kΩ, R2 = 2.5 kΩ, Rb = 3.6 kΩ, Rz = 20 kΩ,
k2? Explain the effect or lack of effect. Vz = 7 V, RL = 1 kΩ, Vi = 20 V to 30 V, Vi-nominal
13. In Problem 11, the current gain of Q2 is = 25 V, b1 = b2 = 100. If the output voltage is
increased to 1000. What is the effect on k1 and expressed as Vo = k1Vi + k2Vz + k3Vbe1 + k4Vbe2,
k2? Explain. evaluate k1, k2 k3 and k4 using the second-level
model. (Assume Vbe = 0.6, rb = 0.2 Ω for BJTs
14. Consider a linear series regulator with R1 = 3.6 and rz = 0.1 Ω for Zeners.)
kΩ, R2 = 2.5 kΩ, Rb = 3.6 kΩ, Rz = 20 kΩ,
Vz = 7 V, RL = 1 kΩ, Vi = 20 V to 30 V, 20. In Problem 19, the current gain of Q1 is
Vi-nominal = 25 V. Using the first-level model, increased to 1000. What is the effect on k1 and
find the line-regulation coefficient for (a) b1 = k2? Explain the effect or lack of effect.
b2 = 100, (b) b1 = 1000 and b2 = 100, (c) b1 = 21. In Problem 19, the current gain of Q2 is
100 and b2 = 1000. increased to 1000. What is the effect on k1 and
15. For Problem 14, using the first-level model, k2? Explain.
find the load-regulation coefficient for (a) b1 = 22. Consider a current regulator wherein Vi = 20 V
b2 = 100, (b) b1 = 1000 and b2 = 100, (c) b1 = to 30 V, Vz = 8.2 V, Re = 10 Ω, RL = 10 Ω,
100 and b2 = 1000. Rz = 3.6 kΩ and b = 100. What is the constant
output current using the first-level model?
16. In the series regulator of Problem 14, if Rb is
Apply and compare with the output current
replaced by a constant-current source regulator,
estimated with the second-level model.
then estimate the load-regulation coefficient
for (a) b1 = b2 = 100, (b) b1 = 1000 and b2 = 23. For Problem 22, find the line-regulation coeffi-
100, (c) b1 = 100 and b2 = 1000. cient.

Chapter 04.indd 191 3/12/2009 3:50:16 PM

192 Power Electronics

| ANSWERS
Fill in the Blanks
1. linear 7. Zener 15. DC; Vz
2. lesser 8. series-pass 16. independent
3. eﬃciency; input voltage; tem- 9. constant 17. dependent
perature; load 10. voltage 18. base-spreading resistance; junc-
4. Zener diode; reverse break- 11. zero tion potential
down 12. power density 19. breakdown resistance
5. reverse breakdown 13. heat sink 20. Rz RL
6. input; load 14. dependent; bib

Chapter 04.indd 192 3/12/2009 3:50:16 PM

DC–DC Switched-Mode Converters

Learning Objectives
CHAPTER

5
After reading this chapter, you will be able to:
analyze the steady-state operation of a DC–DC converter.
design non-isolated and isolated DC–DC converters.
understand the process of drawing and analyzing waveforms.
understand soft-switching converters.

I n the previous chapter DC–DC converters were discussed wherein the power devices were operated in the
linear region. As a consequence the power devices were acting as power dissipators. This results in reduced
conversion efficiency. If the power devices are operated either in the cut-off region or in the full-on or satura-
tion region, they act as switches. DC–DC converters that are based on this principle are called the switched-
mode converters. The switched-mode DC–DC converters would ideally have 100% efficiency. However,
due to switching and conduction losses this value is lower than 100%. After the voltage is switched with
a power switch, the voltage has a switched wave shape that needs to be filtered to obtain a DC output volt-
age. The filtering or averaging is done using non-dissipative components like the inductor and capacitor.
Therefore, any switched-mode converter will include at least a power switch that emulates a single pole
double throw (SPDT) mechanical switch, an inductor and a capacitor.

5.1 Single Pole Double Throw Switch

A single pole double throw (SPDT) switch is shown in Figure 5.1(a). The switch consists of a pole P and
two throws T1 and T2. The pole makes contact with either T1 or T2 at any given instant. Referring to
Chapter 1, it is seen that no single power device can behave as an SPDT switch. However, the power devices
can behave as a single pole single throw (SPST) switch. Therefore, from the point of view of implementation
using the power devices, the SPST switch is available as a single device. The SPDT switch can be constructed
using SPST switches as shown in Figure 5.1(b). Here the SPST switch S1 is linked to throw T1 and the
SPST switch S2 is linked to throw T2. At any given instant of time it should be noted that either S1 is ON
or S2 is ON. Such an operational topology will emulate an SPDT switch.
Few practical realizations of the SPDT switch are shown in Figure 5.2. These realizations are based on
the generic topology of Figure 5.1(b). In the circuits of Figure 5.2, the power switch represented as bipolar
transistor (BJT) can be replaced by either a metal oxide semiconductor ﬁeld eﬀect transistor (MOSFET) or

Chapter 05.indd 193 3/19/2009 1:30:15 PM

194 Power Electronics

T1
T1

P P

T2
T2

(a) (b)

Figure 5.1 (a) SPDT switch; (b) two SPST switches used to emulate an SPDT switch.

T1 T1 T1
T1

S1 S1 S1 S1

P P P P

S2 S2 S2 S2

T2 T2 T2 T2

(a) (b) (c) (d)

Figure 5.2 Few realizations of the SPDT switch using power devices.

an insulated gate bipolar transistor (IGBT) without loss of generality. In Figure 5.2(d), the diodes are the
internal body diodes of the BJT or MOSFET or IGBT that is used. This is in fact one of the most popular
of all topologies and is extensively used in both DC–DC converters and DC–AC inverters.

5.2 The Chopper

T he chopper is a power converter wherein the input DC voltage is chopped and sent to the output with-
out incorporating any ﬁlters exclusively within the converter. The ﬁltering of the voltage or current is the
responsibility of the applied load. The schematic of the chopper is illustrated in Figure 5.3(a). The simplest

Chapter 05.indd 194 3/19/2009 1:30:17 PM

DC–DC Switched-Mode Converters 195

v v
t
t

Vin Chopper Vo

(a)

P
T1
Vin T2 Vo

Chopper

(b)

Vin P

S2 Vo

Chopper

(c)

Figure 5.3 Basic chopper: (a) Block schematic; (b) SPDT representation; (c) realization
using semiconductor switches.

chopper can be constructed using only one SPDT switch. As the output is an unﬁltered chopped waveform,
there is no need for an inductor and capacitor. Figure 5.3(b) gives the chopper representation with an SPDT
switch and Figure 5.3(c) gives the practical realization of the chopper. The switches S1 and S2 are IGBT
switches with internal body diodes. The IGBT switches may be replaced with MOSFET or BJT switches.
The switch S1 is turned ON by appropriate application of the gate-to-emitter pulse. During this time, the
switch S2 is in the OFF-state. This duration is for a period Ton. For the period Toﬀ , the switch S1 is turned
OFF and the switch S2 is turned ON. The pole voltage at P is a switching waveform as shown in Figure 5.4.

Chapter 05.indd 195 3/19/2009 1:30:17 PM

196 Power Electronics

Vin
Ton
Toff

0 t
Ts

Figure 5.4 Chopper output waveform.

Referring to Figure 5.4,

Ts = Ton + Toff
where Ts is one switching period. A useful and important term that is widely used in the power electronic
literature is the duty ratio or the duty cycle. The duty ratio or the duty cycle (D) can be deﬁned as the ratio
of the ON-time of switch S1 when the input is connected to the pole to the total switching period. This is
given as

Ton T
D= = on (5.1)
Ton + Toff Ts

The output voltage of the chopper is a switched waveform with an average value of

Ts Ton
1 1 V
Vo = ∫ vo dt = ∫ Vidt = Ti Ton = DVi
Ts 0 Ts 0 s

The chopper circuit is used in applications like DC motor drives wherein the motor’s armature inductance
filters the armature current flowing through it. Figure 5.5(a) shows the chopper connected to the armature
circuit of a separately excited DC motor. In Figure 5.5(b), the DC motor is replaced by an equivalent circuit
that acts as the load on the chopper. The DC motor is represented by the armature resistance Ra, the arma-
ture inductance La and the speed-dependent back emf source eb.
The DC motor can operate in any one of the four operating zones as shown in the v –i characteristic of
Figure 5.6, namely, (a) forward motoring mode or first quadrant operation, (b) reverse motoring mode or
the third quadrant operation, (c) forward generation mode or second quadrant operation, (d) reverse gen-
eration mode or fourth quadrant operatio