Cat. No.

W340-E2-16A
SYSMAC CS Series
CS1G/H-CPU_-EV1,
CS1G/H-CPU_H,
CS1D-CPU_H, CS1D-CPU_S
SYSMAC CJ Series
CJ1H-CPU_H-R,
CJ1G-CPU_, CJ1G/H-CPU_H, CJ1G-CPU_P,
CJ1M-CPU_,
SYSMAC One NSJ Series

Programmable Controllers

INSTRUCTIONS
REFERENCE MANUAL
SYSMAC CS Series
CS1G/H-CPU@@-EV1
CS1G/H-CPU@@H
CS1D-CPU@@H
CS1D-CPU@@S
SYSMAC CJ Series
CJ1H-CPU@@H-R
CJ1G-CPU@@
CJ1G/H-CPU@@H
CJ1G-CPU@@P
CJ1M-CPU@@
SYSMAC One NSJ Series
Programmable Controllers
Instructions Reference Manual
Revised August 2008
iv
Notice:
OMRON products are manufactured for use according to proper procedures
by a qualified operator and only for the purposes described in this manual.
The following conventions are used to indicate and classify precautions in this
manual. Always heed the information provided with them. Failure to heed pre-
cautions can result in injury to people or damage to property.

!DANGER Indicates an imminently hazardous situation which, if not avoided, will result in death or
serious injury. Additionally, there may be severe property damage.

!WARNING Indicates a potentially hazardous situation which, if not avoided, could result in death or
serious injury. Additionally, there may be severe property damage.

!Caution Indicates a potentially hazardous situation which, if not avoided, may result in minor or
moderate injury, or property damage.

OMRON Product References

All OMRON products are capitalized in this manual. The word “Unit” is also
capitalized when it refers to an OMRON product, regardless of whether or not
it appears in the proper name of the product.
The abbreviation “Ch,” which appears in some displays and on some OMRON
products, often means “word” and is abbreviated “Wd” in documentation in
this sense.
The abbreviation “PLC” means Programmable Controller. “PC” is used, how-
ever, in some Programming Device displays to mean Programmable Control-
ler.

Visual Aids
The following headings appear in the left column of the manual to help you
locate different types of information.
Note Indicates information of particular interest for efficient and convenient opera-
tion of the product.

1,2,3... 1. Indicates lists of one sort or another, such as procedures, checklists, etc.

 OMRON, 1999
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form, or
by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permission of
OMRON.
No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is con-
stantly striving to improve its high-quality products, the information contained in this manual is subject to change without
notice. Every precaution has been taken in the preparation of this manual. Nevertheless, OMRON assumes no responsibility
for errors or omissions. Neither is any liability assumed for damages resulting from the use of the information contained in
this publication.

v
Unit Versions of CS/CJ-series CPU Units
Unit Versions A “unit version” has been introduced to manage CPU Units in the CS/CJ
Series according to differences in functionality accompanying Unit upgrades.
This applies to the CS1-H, CJ1-H, CJ1M, and CS1D CPU Units.
Notation of Unit Versions The unit version is given to the right of the lot number on the nameplate of the
on Products products for which unit versions are being managed, as shown below.
CS/CJ-series CPU Unit Product nameplate

CS1H-CPU67H

CPU UNIT

Lot No. Unit version

Example for Unit version 3.0

Lot No. 040715 0000 Ver.3.0

OMRON Corporation MADE IN JAPAN

• CS1-H, CJ1-H, and CJ1M CPU Units manufactured on or before Novem-

ber 4, 2003 do not have a unit version given on the CPU Unit (i.e., the
location for the unit version shown above is blank).
• The unit version of the CJ1-H-R CPU Units begins at version 4.0.
• The unit version of the CS1-H, CJ1-H, and CJ1M CPU Units, as well as
the CS1D CPU Units for Single-CPU Systems, begins at version 2.0.
• The unit version of the CS1D CPU Units for Duplex-CPU Systems, begins
at version 1.1.
• CPU Units for which a unit version is not given are called Pre-Ver. @.@
CPU Units, such as Pre-Ver. 2.0 CPU Units and Pre-Ver. 1.1 CPU Units.
Confirming Unit Versions CX-Programmer version 4.0 can be used to confirm the unit version using one
with Support Software of the following two methods.
• Using the PLC Information
• Using the Unit Manufacturing Information (This method can be used for
Special I/O Units and CPU Bus Units as well.)
Note CX-Programmer version 3.3 or lower cannot be used to confirm unit versions.
PLC Information
• If you know the device type and CPU type, select them in the Change
PLC Dialog Box, go online, and select PLC - Edit - Information from the
menus.
• If you don't know the device type and CPU type, but are connected
directly to the CPU Unit on a serial line, select PLC - Auto Online to go
online, and then select PLC - Edit - Information from the menus.
In either case, the following PLC Information Dialog Box will be displayed.

vi
 Unit version

Use the above display to confirm the unit version of the CPU Unit.
Unit Manufacturing Information
In the IO Table Window, right-click and select Unit Manufacturing informa-
tion - CPU Unit.

The following Unit Manufacturing information Dialog Box will be displayed.

vii
 Unit version

Use the above display to confirm the unit version of the CPU Unit connected
online.
Using the Unit Version The following unit version labels are provided with the CPU Unit.
Labels

These labels can be attached to the front of previous CPU Units to differenti-
ate between CPU Units of different unit versions.

viii
Unit Version Notation In this manual, the unit version of a CPU Unit is given as shown in the follow-
ing table.
Product nameplate CPU Units on which no unit version is Units on which a version is given
given (Ver. @.@)

Lot No. XXXXXX XXXX Lot No. XXXXXX XXXX Ver. @ .@

OMRON Corporation MADE IN JAPAN

Meaning

Designating individual Pre-Ver. 2.0 CS1-H CPU Units CS1H-CPU67H CPU Unit Ver. @.@
CPU Units (e.g., the
CS1H-CPU67H)
Designating groups of Pre-Ver. 2.0 CS1-H CPU Units CS1-H CPU Units Ver. @.@
CPU Units (e.g., the
CS1-H CPU Units)
Designating an entire Pre-Ver. 2.0 CS-series CPU Units CS-series CPU Units Ver. @.@
series of CPU Units
(e.g., the CS-series CPU
Units)

ix
Unit Versions
CS Series
Units Models Unit version
CS1-H CPU Units CS1@-CPU@@H Unit version 4.2
Unit version 4.0
Unit version 3.0
Unit version 2.0
Pre-Ver. 2.0
CS1D CPU Units Duplex-CPU Systems Unit version 1.2
CS1D-CPU@@H Unit version 1.1
Pre-Ver. 1.1
Single-CPU Systems Unit version 2.0
CS1D-CPU@@S
CS1 CPU Units CS1@-CPU@@ No unit version.
CS1 Version-1 CPU Units CS1@-CPU@@-V1 No unit version.

CJ Series
Units Models Unit version
CJ1-H CPU Units CJ1H-CPU@@H-R Unit version 4.0
CJ1@-CPU@@H Unit version 4.0
CJ1@-CPU@@P Unit version 3.0
Unit version 2.0
Pre-Ver. 2.0
CJ1M CPU Units CJ1M-CPU12/13 Unit version 4.0
CJ1M-CPU22/23 Unit version 3.0
Unit version 2.0
Pre-Ver. 2.0
CJ1M-CPU11/21 Unit version 4.0
Unit version 3.0
Unit version 2.0

NSJ Series
Units Unit version
NSJ@-TQ@@(B)-G5D Unit version 3.0
NSJ@-TQ@@(B)-M3D

x
Function Support by Unit Version

• Functions Supported for Unit Version 4.0 or Later

CX-Programmer 7.0 or higher must be used to enable using the functions
added for unit version 4.0.
CS1-H CPU Units
Function CS1@-CPU@@H
Unit version 4.0 or Other unit versions
later
Online editing of function blocks OK ---
Note This function cannot be used for simulations on the CX-Sim-
ulator.
Input-output variables in function blocks OK ---
Text strings in function blocks OK ---
New application Number-Text String Conversion Instructions: OK ---
instructions NUM4, NUM8, NUM16, STR4, STR8, and STR16
TEXT FILE WRITE (TWRIT) OK ---

CS1D CPU Units

Unit version 4.0 is not supported.

CJ1-H/CJ1M CPU Units

Function CJ1H-CPU@@H-R, CJ1@-CPU@@H,
CJ1G-CPU@@P, CJ1M-CPU@@
Unit version 4.0 or Other unit versions
later
Online editing of function blocks OK ---
Note This function cannot be used for simulations on the CX-Sim-
ulator.
Input-output variables in function blocks OK ---
Text strings in function blocks OK ---
New application Number-Text String Conversion Instructions: OK ---
instructions NUM4, NUM8, NUM16, STR4, STR8, and STR16
TEXT FILE WRITE (TWRIT) OK ---

User programs that contain functions supported only by CPU Units with unit
version 4.0 or later cannot be used on CS/CJ-series CPU Units with unit ver-
sion 3.0 or earlier. An error message will be displayed if an attempt is made to
download programs containing unit version 4.0 functions to a CPU Unit with a
unit version of 3.0 or earlier, and the download will not be possible.
If an object program file (.OBJ) using these functions is transferred to a CPU
Unit with a unit version of 3.0 or earlier, a program error will occur when oper-
ation is started or when the unit version 4.0 function is executed, and CPU
Unit operation will stop.

xi
• Functions Supported for Unit Version 3.0 or Later
CX-Programmer 5.0 or higher must be used to enable using the functions
added for unit version 3.0.
CS1-H CPU Units
Function CS1@-CPU@@H
Unit version 3.0 or Other unit versions
later
Function blocks OK ---
Serial Gateway (converting FINS commands to CompoWay/F OK ---
commands at the built-in serial port)
Comment memory (in internal flash memory) OK ---
Expanded simple backup data OK ---
New application TXDU(256), RXDU(255) (support no-protocol OK ---
instructions communications with Serial Communications
Units with unit version 1.2 or later)
Model conversion instructions: XFERC(565), OK ---
DISTC(566), COLLC(567), MOVBC(568),
BCNTC(621)
Special function block instructions: GETID(286) OK ---
Additional TXD(235) and RXD(236) instructions (support OK ---
instruction func- no-protocol communications with Serial Commu-
tions nications Boards with unit version 1.2 or later)

CS1D CPU Units

Unit version 3.0 is not supported.

CJ1-H/CJ1M CPU Units

Function CJ1H-CPU@@H-R, CJ1@-CPU@@H,
CJ1G-CPU@@P, CJ1M-CPU@@
Unit version 3.0 or Other unit versions
later
Function blocks OK ---
Serial Gateway (converting FINS commands to CompoWay/F OK ---
commands at the built-in serial port)
Comment memory (in internal flash memory) OK ---
Expanded simple backup data OK ---
New application TXDU(256), RXDU(255) (support no-protocol OK ---
instructions communications with Serial Communications
Units with unit version 1.2 or later)
Model conversion instructions: XFERC(565), OK ---
DISTC(566), COLLC(567), MOVBC(568),
BCNTC(621)
Special function block instructions: GETID(286) OK ---
Additional PRV(881) and PRV2(883) instructions: Added OK ---
instruction func- high-frequency calculation methods for calculat-
tions ing pulse frequency. (CJ1M CPU Units only)

xii
User programs that contain functions supported only by CPU Units with unit
version 3.0 or later cannot be used on CS/CJ-series CPU Units with unit ver-
sion 2.0 or earlier. An error message will be displayed if an attempt is made to
download programs containing unit version 3.0 functions to a CPU Unit with a
unit version of 2.0 or earlier, and the download will not be possible.
If an object program file (.OBJ) using these functions is transferred to a CPU
Unit with a unit version of 2.0 or earlier, a program error will occur when oper-
ation is started or when the unit version 3.0 function is executed, and CPU
Unit operation will stop.

xiii
• Functions Supported for Unit Version 2.0 or Later
CX-Programmer 4.0 or higher must be used to enable using the functions
added for unit version 2.0.
CS1-H CPU Units
Function CS1-H CPU Units
(CS1@-CPU@@H)
Unit version 2.0 or Other unit versions
later
Downloading and Uploading Individual Tasks OK ---
Improved Read Protection Using Passwords OK ---
Write Protection from FINS Commands Sent to OK ---
CPU Units via Networks
Online Network Connections without I/O Tables OK ---
Communications through a Maximum of 8 Net- OK ---
work Levels
Connecting Online to PLCs via NS-series PTs OK OK from lot number 030201
Setting First Slot Words OK for up to 64 groups OK for up to 8 groups
Automatic Transfers at Power ON without a OK ---
Parameter File
Automatic Detection of I/O Allocation Method for --- ---
Automatic Transfer at Power ON
Operation Start/End Times OK ---
New Application MILH, MILR, MILC OK ---
Instructions =DT, <>DT, <DT, <=DT, >DT, OK ---
>=DT
BCMP2 OK ---
GRY OK OK from lot number 030201
TPO OK ---
DSW, TKY, HKY, MTR, 7SEG OK ---
EXPLT, EGATR, ESATR, OK ---
ECHRD, ECHWR
Reading/Writing CPU Bus OK OK from lot number 030418
Units with IORD/IOWR
PRV2 --- ---

xiv
CS1D CPU Units
Function CS1D CPU Units for CS1D CPU Units for Duplex-CPU
Single-CPU Systems Systems (CS1D-CPU@@H)
(CS1D-CPU@@S)
Unit version 2.0 Unit version 1.1 or Pre-Ver. 1.1
later
Functions Duplex CPU Units --- OK OK
unique to CS1D Online Unit Replacement OK OK OK
CPU Units
Duplex Power Supply Units OK OK OK
Duplex Controller Link OK OK OK
Units
Duplex Ethernet Units --- OK OK
Unit removal without a Pro- --- OK (Unit version 1.2 or ---
gramming Device later)
Downloading and Uploading Individual Tasks OK --- ---
Improved Read Protection Using Passwords OK --- ---
Write Protection from FINS Commands Sent OK --- ---
to CPU Units via Networks
Online Network Connections without I/O OK --- ---
Tables
Communications through a Maximum of 8 OK --- ---
Network Levels
Connecting Online to PLCs via NS-series OK --- ---
PTs
Setting First Slot Words OK for up to 64 groups --- ---
Automatic Transfers at Power ON without a OK --- ---
Parameter File
Automatic Detection of I/O Allocation Method --- --- ---
for Automatic Transfer at Power ON
Operation Start/End Times OK OK ---
New Applica- MILH, MILR, MILC OK --- ---
tion Instructions =DT, <>DT, <DT, <=DT, OK --- ---
>DT, >=DT
BCMP2 OK --- ---
GRY OK --- ---
TPO OK --- ---
DSW, TKY, HKY, MTR, OK --- ---
7SEG
EXPLT, EGATR, ESATR, OK --- ---
ECHRD, ECHWR
Reading/Writing CPU Bus OK --- ---
Units with IORD/IOWR
PRV2 OK --- ---

xv
CJ1-H/CJ1M CPU Units
Function CJ1-H CPU Units CJ1M CPU Units
CJ1H-CPU@@H-R
CJ1M-
CJ1@-CPU@@H CJ1M-CPU12/13/22/23
CPU11/21
CJ1G-CPU@@P
Unit version Other unit Unit version Other unit Other unit
2.0 or versions 2.0 or versions versions
later later
Downloading and Uploading Individual Tasks OK --- OK --- OK
Improved Read Protection Using Passwords OK --- OK --- OK
Write Protection from FINS Commands Sent OK --- OK --- OK
to CPU Units via Networks
Online Network Connections without I/O OK --- OK --- OK
Tables (Supported if (Supported if
I/O tables are I/O tables are
automatically automatically
generated at generated at
startup.) startup.)
Communications through a Maximum of 8 OK --- OK --- OK
Network Levels
Connecting Online to PLCs via NS-series OK OK from lot OK OK from lot OK
PTs number number
030201 030201
Setting First Slot Words OK for up to OK for up to 8 OK for up to OK for up to 8 OK for up to
64 groups groups 64 groups groups 64 groups
Automatic Transfers at Power ON without a OK --- OK --- OK
Parameter File
Automatic Detection of I/O Allocation Method --- --- --- --- ---
for Automatic Transfer at Power ON
Operation Start/End Times OK --- OK --- OK
New Applica- MILH, MILR, MILC OK --- OK --- OK
tion Instructions =DT, <>DT, <DT, <=DT, OK --- OK --- OK
>DT, >=DT
BCMP2 OK --- OK OK OK
GRY OK OK from lot OK OK from lot OK
number number
030201 030201
TPO OK --- OK --- OK
DSW, TKY, HKY, MTR, OK --- OK --- OK
7SEG
EXPLT, EGATR, ESATR, OK --- OK --- OK
ECHRD, ECHWR
Reading/Writing CPU Bus OK --- OK --- OK
Units with IORD/IOWR
PRV2 --- --- OK, but only --- OK, but only
for CPU Units for CPU Units
with built-in with built-in
I/O I/O

User programs that contain functions supported only by CPU Units with unit
version 2.0 or later cannot be used on CS/CJ-series Pre-Ver. 2.0 CPU Units.
An error message will be displayed if an attempt is made to download pro-
grams containing unit version s.0 functions to a Pre-Ver. 2.0 CPU Unit, and
the download will not be possible.

xvi
If an object program file (.OBJ) using these functions is transferred to a Pre-
Ver. 2.0 CPU Unit, a program error will occur when operation is started or
when the unit version 2.0 function is executed, and CPU Unit operation will
stop.

xvii
Unit Versions and Programming Devices
The following tables show the relationship between unit versions and CX-Pro-
grammer versions.
Unit Versions and Programming Devices
CPU Unit Functions (See note 1.) CX-Programmer Program-
Ver. 3.3 Ver. 4.0 Ver. 5.0 Ver. 7.0 ming Con-
or lower or higher sole
Ver. 6.0
CS/CJ-series unit Functions added Using new functions --- --- --- OK (See No
Ver. 4.0 for unit version note 2 restrictions
4.0 and 3.)
Not using new functions OK OK OK OK
CS/CJ-series unit Functions added Using new functions --- --- OK OK
Ver. 3.0 for unit version Not using new functions OK OK OK OK
3.0
CS/CJ-series unit Functions added Using new functions --- OK OK OK
Ver. 2.0 for unit version Not using new functions OK OK OK OK
2.0
CS1D CPU Units Functions added Using new functions --- OK OK OK
for Single-CPU for unit version Not using new functions
Systems, unit Ver. 2.0
2.0
CS1D CPU Units Functions added Using function blocks --- OK OK OK
for Duplex-CPU for unit version Not using function blocks OK OK OK OK
Systems, unit 1.1
Ver.1.

Note 1. As shown above, there is no need to upgrade to CX-Programmer version

as long as the functions added for unit versions are not used.
2. CX-Programmer version 7.1 or higher is required to use the new functions
added for unit version 4.0 of the CJ1-H-R CPU Units. CX-Programmer ver-
sion 7.22 or higher is required to use unit version 4.1 of the CJ1-H-R CPU
Units. CX-Programmer version 7.0 or higher is required to use unit version
4.2 of the CJ1-H-R CPU Units. You can check the CX-Programmer version
using the About menu command to display version information.
3. CX-Programmer version 7.0 or higher is required to use the functional im-
provements made for unit version 4.0 of the CS/CJ-series CPU Units. With
CX-Programmer version 7.2 or higher, you can use even more expanded
functionality.

xviii
Device Type Setting The unit version does not affect the setting made for the device type on the
CX-Programmer. Select the device type as shown in the following table
regardless of the unit version of the CPU Unit.
Series CPU Unit group CPU Unit model Device type setting on
CX-Programmer Ver. 4.0 or higher
CS Series CS1-H CPU Units CS1G-CPU@@H CS1G-H
CS1H-CPU@@H CS1H-H
CS1D CPU Units for Duplex-CPU Systems CS1D-CPU@@H CS1D-H (or CS1H-H)
CS1D CPU Units for Single-CPU Systems CS1D-CPU@@S CS1D-S
CJ Series CJ1-H CPU Units CJ1G-CPU@@H CJ1G-H
CJ1G-CPU@@P
CJ1H-CPU@@H-R CJ1H-H
(See note.)
CJ1H-CPU@@H
CJ1M CPU Units CJ1M-CPU@@ CJ1M

Note Select one of the following CPU types: CPU67-R, CPU66-R, CPU65-R, or
CPU64-R.

xix
Troubleshooting Problems with Unit Versions on the CX-Programmer
Problem Cause Solution
An attempt was made to down- Check the program or change
load a program containing to a CPU Unit with a later unit
instructions supported only by version.
later unit versions or a CPU Unit
to a previous unit version.

After the above message is displayed, a compiling

error will be displayed on the Compile Tab Page in the
Output Window.
An attempt was to download a Check the settings in the PLC
PLC Setup containing settings Setup or change to a CPU Unit
supported only by later unit ver- with a later unit version.
sions or a CPU Unit to a previous
unit version.
“????” is displayed in a program transferred from the An attempt was made to upload a New instructions cannot be
PLC to the CX-Programmer. program containing instructions uploaded to lower versions of
supported only by higher versions CX-Programmer. Use a higher
of CX-Programmer to a lower ver- version of CX-Programmer.
sion.

xx
 TABLE OF CONTENTS
PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxi
1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxii
2 General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxii
3 Safety Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxii
4 Operating Environment Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiv
5 Application Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiv
6 Conformance to EC Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxviii

SECTION 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1-1 General Instruction Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1-2 Instruction Execution Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SECTION 2
Summary of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2-1 Instruction Classifications by Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2-2 Instruction Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2-3 Alphabetical List of Instructions by Mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
2-4 List of Instructions by Function Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

SECTION 3
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
3-1 Notation and Layout of Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3-2 Instruction Upgrades and New Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3-3 Sequence Input Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3-4 Sequence Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
3-5 Sequence Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3-6 Timer and Counter Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
3-7 Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
3-8 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
3-9 Data Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
3-10 Increment/Decrement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
3-11 Symbol Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
3-12 Conversion Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
3-13 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
3-14 Special Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
3-15 Floating-point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) . . . . 651
3-17 Table Data Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
3-18 Data Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
3-19 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
3-20 Interrupt Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

xxi
 TABLE OF CONTENTS
3-21 High-speed Counter/Pulse Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
3-22 Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
3-23 Basic I/O Unit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
3-24 Serial Communications Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
3-25 Network Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
3-26 File Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
3-27 Display Instructions: DISPLAY MESSAGE: MSG(046) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
3-28 Clock Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
3-29 Debugging Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
3-30 Failure Diagnosis Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
3-31 Other Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
3-32 Block Programming Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
3-33 Text String Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
3-34 Task Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
3-35 Model Conversion Instructions (Unit Ver. 3.0 or Later) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261

SECTION 4
Instruction Execution Times and Number of Steps. . . . . . . 1281
4-1 CS-series Instruction Execution Times and Number of Steps. . . . . . . . . . . . . . . . . . . . . . . . 1283
4-2 CJ-series Instruction Execution Times and Number of Steps . . . . . . . . . . . . . . . . . . . . . . . . 1312

Appendix
A ASCII Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361

xxii
About this Manual:
This manual describes the ladder diagram programming instructions of the CPU Units for CS/CJ-
series Programmable Controllers (PLCs). The CS Series, CJ Series and NSJ Series are subdivided as
shown in the following figure.
CS Series CJ Series NSJ Series

CS1-H CPU Units CJ2 CPU Units NSJ Controllers

CS1H-CPU@@H CJ2H-CPU@@-@@@ NSJ5-TQ@@(B)-G5D

CS1G-CPU@@H NSJ5-SQ@@(B)-G5D
NSJ8-TV@@(B)-G5D
NSJ10-TV@@(B)-G5D
CJ1-H CPU Units NSJ12-TS@@(B)-G5D
CS1 CPU Units
CJ1H-CPU@@H-R
CS1H-CPU@@(-V1)
CJ1H-CPU@@H NSJ Controllers
CS1G-CPU@@(-V1)
CJ1G-CPU@@H
CJ1G -CPU@@P
(Loop-control CPU Units) NSJ5-TQ@@(B)-M3D
NSJ5-SQ@@(B)-M3D
CS1D CPU Units
NSJ8-TV@@(B)-M3D
CS1D CPU Units for
Duplex Systems
CJ1M CPU Units

CS1D-CPU@@H
CJ1M-CPU@@
CS1D CPU Units for
Simplex Systems

CS1D-CPU@@S
CJ1 CPU Units

CS1D Process-control CPU Units

CJ1G-CPU@@
CS1D-CPU@@P

CS-series Basic I/O Units CJ-series Basic I/O Units NSJ-series Expansion Units

CS-series Special I/O Units CJ-series Special I/O Units

CS-series CPU Bus Units CJ-series CPU Bus Units

CS-series Power Supply Units CJ-series Power Supply Units

Note: A special Power Supply Unit must
be used for CS1D CPU Units.

NSJ-series Controller Notation

For information in this manual on the Controller Section of NSJ-series Controllers, refer to the informa-
tion of the equivalent CJ-series PLC. The following models are equivalent.
NSJ-series Controllers Equivalent CJ-series CPU Unit
NSJ@-TQ@@(B)-G5D CJ1G-CPU45H CPU Unit with unit version 3.0
NSJ@-TQ@@(B)-M3D CJ1G-CPU45H CPU Unit with unit version 3.0 (See note.)
Note: The following points differ between the NSJ@-TQ@@(B)-M3D and the CJ1G-CPU45H.
Item CJ-series CPU Unit Controller Section in
CJ1G-CPU45H NSJ@-@@@@(B)-M3D
I/O capacity 1280 points 640 points
Program capacity 60 Ksteps 20 Ksteps
No. of Expansion Racks 3 max. 1 max.
EM Area 32 Kwords x 3 banks None
E0_00000 to E2_32767
Function blocks Max. No. of definitions 1024 128
Max. No. of instances 2048 256
Capacity in built-in FB program memory 1024 KB 256 KB
file memory Variable tables 128 KB 64K KB

Please read this manual and all related manuals listed in the table on the next page and be sure you
understand information provided before attempting to program or use CS/CJ-series CPU Units in a
PLC System.

xxiii
 Section 1 introduces the CS/CJ-series PLCs in terms of the instruction set that they support.
Section 2 provides various lists of instructions that can be used for reference.
Section 3 individually describes the instructions in the CS/CJ-series instruction set.
Section 4 provides instruction execution times and the number of steps for each CS/CJ-series instruc-
tion.

xxiv
 About this Manual, Continued
Name Cat. No. Contents
SYSMAC CS/CJ/NSJ Series W340 Describes the ladder diagram programming
CS1G/H-CPU@@-EV1, CS1G/H-CPU@@H, instructions supported by CS/CJ/NSJ-series
CS1D-CPU@@H, CS1D-CPU@@S, CJ1H-CPU@@H-R, PLCs. (This manual)
CJ1G-CPU@@, CJ1G/H-CPU@@H, CJ1G-CPU@@P,
CJ1M-CPU@@, NSJ@-@@@@(B)-G5D,
NSJ@-@@@@(B)-M3D
Programmable Controllers Instructions Reference Manual
SYSMAC CS/CJ/NSJ Series W394 This manual describes programming and other
CS1G/H-CPU@@-EV1, CS1G/H-CPU@@H, methods to use the functions of the CS/CJ/NSJ-
CS1D-CPU@@H, CS1D-CPU@@S, CJ1H-CPU@@H-R, series PLCs.
CJ1G-CPU@@, CJ1G/H-CPU@@H, CJ1G-CPU@@P,
CJ1M-CPU@@, NSJ@-@@@@(B)-G5D,
NSJ@-@@@@(B)-M3D
Programmable Controllers Programming Manual
SYSMAC CS Series W339 Provides an outlines of and describes the design,
CS1G/H-CPU@@-EV1, CS1G/H-CPU@@H installation, maintenance, and other basic opera-
Programmable Controllers Operation Manual tions for the CS-series PLCs.
SYSMAC CJ Series W393 Provides an outlines of and describes the design,
CJ1H-CPU@@H-R, CJ1G/H-CPU@@H, CJ1G-CPU@@P, installation, maintenance, and other basic opera-
CJ1G-CPU@@, CJ1M-CPU@@ tions for the CJ-series PLCs.
Programmable Controllers Operation Manual
SYSMAC CJ Series W395 Describes the functions of the built-in I/O for
CJ1M-CPU21/22/23 CJ1M CPU Units.
Built-in I/O Functions Operation Manual
SYSMAC CS Series W405 Provides an outline of and describes the design,
CS1D-CPU@@H CPU Units installation, maintenance, and other basic opera-
CS1D-CPU@@S CPU Units tions for a Duplex System based on CS1D CPU
CS1D-DPL1 Duplex Unit Units.
CS1D-PA207R Power Supply Unit
Duplex System Operation Manual
SYSMAC CS/CJ Series W341 Provides information on how to program and
CQM1H-PRO01-E, C200H-PRO27-E, CQM1-PRO01-E operate CS/CJ-series PLCs using a Programming
Programming Consoles Operation Manual Console.
SYSMAC CS/CJ/NSJ Series W342 Describes the C-series (Host Link) and FINS
CJ1H-CPU@@H-R, CS1G/H-CPU@@-EV1, communications commands used with CS/CJ-
CS1G/H-CPU@@H, CS1D-CPU@@H, CS1D-CPU@@S, series PLCs.
CJ1M-CPU@@, CJ1G-CPU@@, CJ1G-CPU@@P,
CJ1G/H-CPU@@H, CS1W-SCB@@-V1,
CS1W-SCU@@-V1, CJ1W-SCU@@-V1, CP1H-X@@@@-@,
CP1H-XA@@@@-@, CP1H-Y@@@@-@,
NSJ@-@@@@(B)-G5D, NSJ@-@@@@(B)-M3D
Communications Commands Reference Manual

xxv
 Name Cat. No. Contents
NSJ Series W452 Provides the following information about the NSJ-
NSJ5-TQ@@(B)-G5D, NSJ5-SQ@@(B)-G5D, series NSJ Controllers:
NSJ8-TV@@(B)-G5D, NSJ10-TV@@(B)-G5D, Overview and features
NSJ12-TS@@(B)-G5D Designing the system configuration
Operation Manual Installation and wiring
I/O memory allocations
Troubleshooting and maintenance
Use this manual in combination with the following
manuals: SYSMAC CS Series Operation Manual
(W339), SYSMAC CJ Series Operation Manual
(W393), SYSMAC CS/CJ Series Programming
Manual (W394), and NS-V1/-V2 Series Setup
Manual (V083)
SYSMAC WS02-CX@@-V@ W446 Provides information on how to use the CX-Pro-
CX-Programmer Operation Manual grammer for all functionality except for function
blocks.
SYSMAC WS02-CX@@-V@ W447 Describes the functionality unique to the CX-Pro-
CX-Programmer Ver. 7.0 Operation Manual grammer and CP-series CPU Units or CS/CJ-
Function Blocks series CPU Units with unit version 3.0 or later
(CS1G-CPU@@H, CS1H-CPU@@H, based on function blocks. Functionality that is the
same as that of the CX-Programmer is described
CJ1G-CPU@@H, CJ1H-CPU@@H,
in W446 (enclosed).
CJ1M-CPU@@, CP1H-X@@@@-@,
CP1H-XA@@@@-@, CP1H-Y@@@@-@
CPU Units)
SYSMAC CS/CJ Series W336 Describes the use of Serial Communications Unit
CS1W-SCB@@-V1, CS1W-SCU@@-V1, and Boards to perform serial communications
CJ1W-SCU@@-V1 with external devices, including the usage of stan-
Serial Communications Boards/Units Operation Manual dard system protocols for OMRON products.
SYSMAC WS02-PSTC1-E W344 Describes the use of the CX-Protocol to create
CX-Protocol Operation Manual protocol macros as communications sequences
to communicate with external devices.
CXONE-AL@@C-V3/AL@@D-V3 W464 Describes operating procedures for the CX-Inte-
CX-Integrator Operation Manual grator Network Configuration Tool for CS-, CJ-,
CP-, and NSJ-series Controllers.
CXONE-AL@@C-V3/AL@@D-V3 W463 Installation and overview of CX-One FA Inte-
CX-One Setup Manual grated Tool Package.

!WARNING Failure to read and understand the information provided in this manual may result in per-
sonal injury or death, damage to the product, or product failure. Please read each section
in its entirety and be sure you understand the information provided in the section and
related sections before attempting any of the procedures or operations given.

xxvi
Read and Understand this Manual
Please read and understand this manual before using the product. Please consult your OMRON
representative if you have any questions or comments.

Warranty and Limitations of Liability

WARRANTY
OMRON's exclusive warranty is that the products are free from defects in materials and workmanship for a
period of one year (or other period if specified) from date of sale by OMRON.

OMRON MAKES NO WARRANTY OR REPRESENTATION, EXPRESS OR IMPLIED, REGARDING NON-

INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR PARTICULAR PURPOSE OF THE
PRODUCTS. ANY BUYER OR USER ACKNOWLEDGES THAT THE BUYER OR USER ALONE HAS
DETERMINED THAT THE PRODUCTS WILL SUITABLY MEET THE REQUIREMENTS OF THEIR
INTENDED USE. OMRON DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED.

LIMITATIONS OF LIABILITY
OMRON SHALL NOT BE RESPONSIBLE FOR SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES,
LOSS OF PROFITS OR COMMERCIAL LOSS IN ANY WAY CONNECTED WITH THE PRODUCTS,
WHETHER SUCH CLAIM IS BASED ON CONTRACT, WARRANTY, NEGLIGENCE, OR STRICT
LIABILITY.

In no event shall the responsibility of OMRON for any act exceed the individual price of the product on which
liability is asserted.

IN NO EVENT SHALL OMRON BE RESPONSIBLE FOR WARRANTY, REPAIR, OR OTHER CLAIMS

REGARDING THE PRODUCTS UNLESS OMRON'S ANALYSIS CONFIRMS THAT THE PRODUCTS
WERE PROPERLY HANDLED, STORED, INSTALLED, AND MAINTAINED AND NOT SUBJECT TO
CONTAMINATION, ABUSE, MISUSE, OR INAPPROPRIATE MODIFICATION OR REPAIR.

xxvii
Application Considerations
SUITABILITY FOR USE
OMRON shall not be responsible for conformity with any standards, codes, or regulations that apply to the
combination of products in the customer's application or use of the products.

At the customer's request, OMRON will provide applicable third party certification documents identifying
ratings and limitations of use that apply to the products. This information by itself is not sufficient for a
complete determination of the suitability of the products in combination with the end product, machine,
system, or other application or use.

The following are some examples of applications for which particular attention must be given. This is not
intended to be an exhaustive list of all possible uses of the products, nor is it intended to imply that the uses
listed may be suitable for the products:

• Outdoor use, uses involving potential chemical contamination or electrical interference, or conditions or
uses not described in this manual.
• Nuclear energy control systems, combustion systems, railroad systems, aviation systems, medical
equipment, amusement machines, vehicles, safety equipment, and installations subject to separate
industry or government regulations.
• Systems, machines, and equipment that could present a risk to life or property.

Please know and observe all prohibitions of use applicable to the products.

NEVER USE THE PRODUCTS FOR AN APPLICATION INVOLVING SERIOUS RISK TO LIFE OR
PROPERTY WITHOUT ENSURING THAT THE SYSTEM AS A WHOLE HAS BEEN DESIGNED TO
ADDRESS THE RISKS, AND THAT THE OMRON PRODUCTS ARE PROPERLY RATED AND INSTALLED
FOR THE INTENDED USE WITHIN THE OVERALL EQUIPMENT OR SYSTEM.

PROGRAMMABLE PRODUCTS
OMRON shall not be responsible for the user's programming of a programmable product, or any
consequence thereof.

xxviii
Disclaimers
CHANGE IN SPECIFICATIONS
Product specifications and accessories may be changed at any time based on improvements and other
reasons.

It is our practice to change model numbers when published ratings or features are changed, or when
significant construction changes are made. However, some specifications of the products may be changed
without any notice. When in doubt, special model numbers may be assigned to fix or establish key
specifications for your application on your request. Please consult with your OMRON representative at any
time to confirm actual specifications of purchased products.

DIMENSIONS AND WEIGHTS

Dimensions and weights are nominal and are not to be used for manufacturing purposes, even when
tolerances are shown.

PERFORMANCE DATA
Performance data given in this manual is provided as a guide for the user in determining suitability and does
not constitute a warranty. It may represent the result of OMRON's test conditions, and the users must
correlate it to actual application requirements. Actual performance is subject to the OMRON Warranty and
Limitations of Liability.

ERRORS AND OMISSIONS

The information in this manual has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for clerical, typographical, or proofreading errors, or omissions.

xxix
xxx
 PRECAUTIONS
This section provides general precautions for using the CS/CJ-series Programmable Controllers (PLCs) and related devices.
The information contained in this section is important for the safe and reliable application of Programmable
Controllers. You must read this section and understand the information contained before attempting to set up or
operate a PLC system.

1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxii

2 General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxii
3 Safety Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxii
4 Operating Environment Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiv
5 Application Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiv
6 Conformance to EC Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxviii
6-1 Applicable Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxviii
6-2 Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxviii
6-3 Conformance to EC Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxix
6-4 Relay Output Noise Reduction Methods . . . . . . . . . . . . . . . . . . . . . xxxix

xxxi
Intended Audience 1

1 Intended Audience
This manual is intended for the following personnel, who must also have
knowledge of electrical systems (an electrical engineer or the equivalent).
• Personnel in charge of installing FA systems.
• Personnel in charge of designing FA systems.
• Personnel in charge of managing FA systems and facilities.

2 General Precautions
The user must operate the product according to the performance specifica-
tions described in the operation manuals.
Before using the product under conditions which are not described in the
manual or applying the product to nuclear control systems, railroad systems,
aviation systems, vehicles, combustion systems, medical equipment, amuse-
ment machines, safety equipment, and other systems, machines, and equip-
ment that may have a serious influence on lives and property if used
improperly, consult your OMRON representative.
Make sure that the ratings and performance characteristics of the product are
sufficient for the systems, machines, and equipment, and be sure to provide
the systems, machines, and equipment with double safety mechanisms.
This manual provides information for programming and operating the Unit. Be
sure to read this manual before attempting to use the Unit and keep this man-
ual close at hand for reference during operation.

!WARNING It is extremely important that a PLC and all PLC Units be used for the speci-
fied purpose and under the specified conditions, especially in applications that
can directly or indirectly affect human life. You must consult with your OMRON
representative before applying a PLC System to the above-mentioned appli-
cations.

3 Safety Precautions
!WARNING The CPU Unit refreshes I/O even when the program is stopped (i.e., even in
PROGRAM mode). Confirm safety thoroughly in advance before changing the
status of any part of memory allocated to I/O Units, Special I/O Units, or CPU
Bus Units. Any changes to the data allocated to any Unit may result in unex-
pected operation of the loads connected to the Unit. Any of the following oper-
ation may result in changes to memory status.

• Transferring I/O memory data to the CPU Unit from a Programming

Device.
• Changing present values in memory from a Programming Device.
• Force-setting/-resetting bits from a Programming Device.
• Transferring I/O memory files from a Memory Card or EM file memory to
the CPU Unit.
• Transferring I/O memory from a host computer or from another PLC on a
network.

!WARNING Do not attempt to take any Unit apart while the power is being supplied. Doing
so may result in electric shock.

xxxii
Safety Precautions 3

!WARNING Do not touch any of the terminals or terminal blocks while the power is being
supplied. Doing so may result in electric shock.

!WARNING Do not attempt to disassemble, repair, or modify any Units. Any attempt to do
so may result in malfunction, fire, or electric shock.

!WARNING Provide safety measures in external circuits (i.e., not in the Programmable
Controller), including the following items, to ensure safety in the system if an
abnormality occurs due to malfunction of the PLC or another external factor
affecting the PLC operation. Not doing so may result in serious accidents.

• Emergency stop circuits, interlock circuits, limit circuits, and similar safety
measures must be provided in external control circuits.
• The PLC will turn OFF all outputs when its self-diagnosis function detects
any error or when a severe failure alarm (FALS) instruction is executed.
As a countermeasure for such errors, external safety measures must be
provided to ensure safety in the system.
• The PLC outputs may remain ON or OFF due to deposition or burning of
the output relays or destruction of the output transistors. As a counter-
measure for such problems, external safety measures must be provided
to ensure safety in the system.
• When the 24-V-DC output (service power supply to the PLC) is over-
loaded or short-circuited, the voltage may drop and result in the outputs
being turned OFF. As a countermeasure for such problems, external
safety measures must be provided to ensure safety in the system.

!Caution Confirm safety before transferring data files stored in the file memory (Mem-
ory Card or EM file memory) to the I/O area (CIO) of the CPU Unit using a
peripheral tool. Otherwise, the devices connected to the output unit may mal-
function regardless of the operation mode of the CPU Unit.

!Caution Fail-safe measures must be taken by the customer to ensure safety in the
event of incorrect, missing, or abnormal signals caused by broken signal lines,
momentary power interruptions, or other causes. Serious accidents may
result from abnormal operation if proper measures are not provided.

!Caution Execute online edit only after confirming that no adverse effects will be
caused by extending the cycle time. Otherwise, the input signals may not be
readable.

!Caution The CS1-H, CJ1-H, CJ1M, and CS1D CPU Units automatically back up the
user program and parameter data to flash memory when these are written to
the CPU Unit. I/O memory (including the DM, EM, and HR Areas), however, is
not written to flash memory. The DM, EM, and HR Areas can be held during
power interruptions with a battery. If there is a battery error, the contents of
these areas may not be accurate after a power interruption. If the contents of
the DM, EM, and HR Areas are used to control external outputs, prevent inap-
propriate outputs from being made whenever the Battery Error Flag (A40204)
is ON.

!Caution Confirm safety at the destination node before transferring a program to

another node or changing contents of the I/O memory area. Doing either of
these without confirming safety may result in injury.

xxxiii
Operating Environment Precautions 4

!Caution Tighten the screws on the terminal block of the AC Power Supply Unit to the
torque specified in the operation manual. The loose screws may result in
burning or malfunction.

!Caution Do not touch the Power Supply Unit when power is being supplied or immedi-
ately after the power supply is turned OFF. The Power Supply Unit will be hot
and you may be burned.

!Caution Be careful when connecting personal computers or other peripheral devices

to a PLC to which is mounted a non-insulated Unit (CS1W-CLK12/52(-V1) or
CS1W-ETN01) connected to an external power supply. A short-circuit will be
created if the 24 V side of the external power supply is grounded and the 0 V
side of the peripheral device is grounded. When connecting a peripheral
device to this type of PLC, either ground the 0 V side of the external power
supply or do not ground the external power supply at all.

4 Operating Environment Precautions

!Caution Do not operate the control system in the following locations:

• Locations subject to direct sunlight.

• Locations subject to temperatures or humidity outside the range specified
in the specifications.
• Locations subject to condensation as the result of severe changes in tem-
perature.
• Locations subject to corrosive or flammable gases.
• Locations subject to dust (especially iron dust) or salts.
• Locations subject to exposure to water, oil, or chemicals.
• Locations subject to shock or vibration.

!Caution Take appropriate and sufficient countermeasures when installing systems in

the following locations:

• Locations subject to static electricity or other forms of noise.

• Locations subject to strong electromagnetic fields.
• Locations subject to possible exposure to radioactivity.
• Locations close to power supplies.

!Caution The operating environment of the PLC System can have a large effect on the
longevity and reliability of the system. Improper operating environments can
lead to malfunction, failure, and other unforeseeable problems with the PLC
System. Be sure that the operating environment is within the specified condi-
tions at installation and remains within the specified conditions during the life
of the system.

5 Application Precautions
Observe the following precautions when using the PLC System.
• You must use the CX-Programmer (programming software that runs on
Windows) if you need to program more than one task. A Programming
Console can be used to program only one cyclic task plus interrupt tasks.

xxxiv
Application Precautions 5

A Programming Console can, however, be used to edit multitask pro-

grams originally created with the CX-Programmer.

!WARNING Always heed these precautions. Failure to abide by the following precautions
could lead to serious or possibly fatal injury.

• Always connect to a ground of 100 Ω or less when installing the Units. Not
connecting to a ground of 100 Ω or less may result in electric shock.
• A ground of 100 Ω or less must be installed when shorting the GR and LG
terminals on the Power Supply Unit.
• Always turn OFF the power supply to the PLC before attempting any of
the following. Not turning OFF the power supply may result in malfunction
or electric shock.
• Mounting or dismounting Power Supply Units, I/O Units, CPU Units, In-
ner Boards, or any other Units.
• Assembling the Units.
• Setting DIP switches or rotary switches.
• Connecting cables or wiring the system.
• Connecting or disconnecting the connectors.

!Caution Failure to abide by the following precautions could lead to faulty operation of
the PLC or the system, or could damage the PLC or PLC Units. Always heed
these precautions.

• The user program and parameter area data in the CS1-H, CS1D, CJ1-H,
and CJ1M CPU Units are backed up in the built-in flash memory. The
BKUP indicator will light on the front of the CPU Unit when the backup
operation is in progress. Do not turn OFF the power supply to the CPU
Unit when the BKUP indicator is lit. The data will not be backed up if
power is turned OFF.
• When using a CS-series CS1 CPU Unit for the first time, install the
CS1W-BAT1 Battery provided with the Unit and clear all memory areas
from a Programming Device before starting to program. When using the
internal clock, turn ON power after installing the battery and set the clock
from a Programming Device or using the DATE(735) instruction. The clock
will not start until the time has been set.
• When the CPU Unit is shipped from the factory, the PLC Setup is set so
that the CPU Unit will start in the operating mode set on the Programming
Console mode switch. When a Programming Console is not connected, a
CS-series CS1 CPU Unit will start in PROGRAM mode, but a CS1-H,
CS1D, CJ1, CJ1-H, or CJ1M CPU Unit will start in RUN mode and opera-
tion will begin immediately. Do not advertently or inadvertently allow oper-
ation to start without confirming that it is safe.
• When creating an AUTOEXEC.IOM file from a Programming Device (a
Programming Console or the CX-Programmer) to automatically transfer
data at startup, set the first write address to D20000 and be sure that the
size of data written does not exceed the size of the DM Area. When the
data file is read from the Memory Card at startup, data will be written in
the CPU Unit starting at D20000 even if another address was set when
the AUTOEXEC.IOM file was created. Also, if the DM Area is exceeded
(which is possible when the CX-Programmer is used), the remaining data
will be written to the EM Area.

xxxv
Application Precautions 5

• Always turn ON power to the PLC before turning ON power to the control
system. If the PLC power supply is turned ON after the control power sup-
ply, temporary errors may result in control system signals because the
output terminals on DC Output Units and other Units will momentarily turn
ON when power is turned ON to the PLC.
• Fail-safe measures must be taken by the customer to ensure safety in the
event that outputs from Output Units remain ON as a result of internal cir-
cuit failures, which can occur in relays, transistors, and other elements.
• Fail-safe measures must be taken by the customer to ensure safety in the
event of incorrect, missing, or abnormal signals caused by broken signal
lines, momentary power interruptions, or other causes.
• Interlock circuits, limit circuits, and similar safety measures in external cir-
cuits (i.e., not in the Programmable Controller) must be provided by the
customer.
• Do not turn OFF the power supply to the PLC when data is being trans-
ferred. In particular, do not turn OFF the power supply when reading or
writing a Memory Card. Also, do not remove the Memory Card when the
BUSY indicator is lit. To remove a Memory Card, first press the memory
card power supply switch and then wait for the BUSY indicator to go out
before removing the Memory Card.
• If the I/O Hold Bit is turned ON, the outputs from the PLC will not be
turned OFF and will maintain their previous status when the PLC is
switched from RUN or MONITOR mode to PROGRAM mode. Make sure
that the external loads will not produce dangerous conditions when this
occurs. (When operation stops for a fatal error, including those produced
with the FALS(007) instruction, all outputs from Output Unit will be turned
OFF and only the internal output status will be maintained.)
• The contents of the DM, EM, and HR Areas in the CPU Unit are backed
up by a Battery. If the Battery voltage drops, this data may be lost. Provide
countermeasures in the program using the Battery Error Flag (A40204) to
re-initialize data or take other actions if the Battery voltage drops.
• When supplying power at 200 to 240 V AC with a CS-series PLC, always
remove the metal jumper from the voltage selector terminals on the Power
Supply Unit (except for Power Supply Units with wide-range specifica-
tions). The product will be destroyed if 200 to 240 V AC is supplied while
the metal jumper is attached.
• Always use the power supply voltages specified in the operation manuals.
An incorrect voltage may result in malfunction or burning.
• Take appropriate measures to ensure that the specified power with the
rated voltage and frequency is supplied. Be particularly careful in places
where the power supply is unstable. An incorrect power supply may result
in malfunction.
• Install external breakers and take other safety measures against short-cir-
cuiting in external wiring. Insufficient safety measures against short-cir-
cuiting may result in burning.
• Do not apply voltages to the Input Units in excess of the rated input volt-
age. Excess voltages may result in burning.
• Do not apply voltages or connect loads to the Output Units in excess of
the maximum switching capacity. Excess voltage or loads may result in
burning.

xxxvi
Application Precautions 5

• Separate the line ground terminal (LG) from the functional ground termi-
nal (GR) on the Power Supply Unit before performing withstand voltage
tests or insulation resistance tests. Not doing so may result in burning.
• Install the Units properly as specified in the operation manuals. Improper
installation of the Units may result in malfunction.
• With CS-series PLCs, be sure that all the Unit and Backplane mounting
screws are tightened to the torque specified in the relevant manuals.
Incorrect tightening torque may result in malfunction.
• Be sure that all terminal screws, and cable connector screws are tight-
ened to the torque specified in the relevant manuals. Incorrect tightening
torque may result in malfunction.
• Leave the label attached to the Unit when wiring. Removing the label may
result in malfunction if foreign matter enters the Unit.
• Remove the label after the completion of wiring to ensure proper heat dis-
sipation. Leaving the label attached may result in malfunction.
• Use crimp terminals for wiring. Do not connect bare stranded wires
directly to terminals. Connection of bare stranded wires may result in
burning.
• Wire all connections correctly.
• Double-check all wiring and switch settings before turning ON the power
supply. Incorrect wiring may result in burning.
• Mount Units only after checking terminal blocks and connectors com-
pletely.
• Be sure that the terminal blocks, Memory Units, expansion cables, and
other items with locking devices are properly locked into place. Improper
locking may result in malfunction.
• Check switch settings, the contents of the DM Area, and other prepara-
tions before starting operation. Starting operation without the proper set-
tings or data may result in an unexpected operation.
• Check the user program for proper execution before actually running it on
the Unit. Not checking the program may result in an unexpected opera-
tion.
• Confirm that no adverse effect will occur in the system before attempting
any of the following. Not doing so may result in an unexpected operation.
• Changing the operating mode of the PLC (including the setting of the
startup operating mode).
• Force-setting/force-resetting any bit in memory.
• Changing the present value of any word or any set value in memory.
• Do not pull on the cables or bend the cables beyond their natural limit.
Doing either of these may break the cables.
• Do not place objects on top of the cables or other wiring lines. Doing so
may break the cables.
• Do not use commercially available RS-232C personal computer cables.
Always use the special cables listed in this manual or make cables
according to manual specifications. Using commercially available cables
may damage the external devices or CPU Unit.
• Never connect pin 6 (5-V power supply) on the RS-232C port on the CPU
Unit to any device other than an NT-AL001 or CJ1W-CIF11 Adapter. The
external device or the CPU Unit may be damaged.

xxxvii
Conformance to EC Directives 6

• When replacing parts, be sure to confirm that the rating of a new part is
correct. Not doing so may result in malfunction or burning.
• Before touching a Unit, be sure to first touch a grounded metallic object in
order to discharge any static build-up. Not doing so may result in malfunc-
tion or damage.
• When transporting or storing circuit boards, cover them in antistatic mate-
rial to protect them from static electricity and maintain the proper storage
temperature.
• Do not touch circuit boards or the components mounted to them with your
bare hands. There are sharp leads and other parts on the boards that
may cause injury if handled improperly.
• Do not short the battery terminals or charge, disassemble, heat, or incin-
erate the battery. Do not subject the battery to strong shocks. Doing any
of these may result in leakage, rupture, heat generation, or ignition of the
battery. Dispose of any battery that has been dropped on the floor or oth-
erwise subjected to excessive shock. Batteries that have been subjected
to shock may leak if they are used.
• UL standards require that batteries be replaced only by experienced tech-
nicians. Do not allow unqualified persons to replace batteries.
• Dispose of the product and batteries according to local ordi-
nances as they apply. Have qualified specialists properly dis-
pose of used batteries as industrial waste.

• With a CJ-series PLC, the sliders on the tops and bottoms of the Power
Supply Unit, CPU Unit, I/O Units, Special I/O Units, and CPU Bus Units
must be completely locked (until they click into place). The Unit may not
operate properly if the sliders are not locked in place.
• With a CJ-series PLC, always connect the End Plate to the Unit on the
right end of the PLC. The PLC will not operate properly without the End
Plate
• Unexpected operation may result if inappropriate data link tables or
parameters are set. Even if appropriate data link tables and parameters
have been set, confirm that the controlled system will not be adversely
affected before starting or stopping data links.
• CPU Bus Units will be restarted when routing tables are transferred from
a Programming Device to the CPU Unit. Restarting these Units is required
to read and enable the new routing tables. Confirm that the system will
not be adversely affected before allowing the CPU Bus Units to be reset.

6 Conformance to EC Directives
6-1 Applicable Directives
• EMC Directives
• Low Voltage Directive

6-2 Concepts
EMC Directives
OMRON devices that comply with EC Directives also conform to the related
EMC standards so that they can be more easily built into other devices or the
overall machine. The actual products have been checked for conformity to
EMC standards (see the following note). Whether the products conform to the

xxxviii
Conformance to EC Directives 6

standards in the system used by the customer, however, must be checked by

the customer.
EMC-related performance of the OMRON devices that comply with EC Direc-
tives will vary depending on the configuration, wiring, and other conditions of
the equipment or control panel on which the OMRON devices are installed.
The customer must, therefore, perform the final check to confirm that devices
and the overall machine conform to EMC standards.
Note Applicable EMC (Electromagnetic Compatibility) standards are as follows:
EMS (Electromagnetic Susceptibility): EN61131-2 (CS-series)/
EN61000-6-2 (CJ-series)
EMI (Electromagnetic Interference): EN61000-6-4
(Radiated emission: 10-m regulations)
Low Voltage Directive
Always ensure that devices operating at voltages of 50 to 1,000 V AC and 75
to 1,500 V DC meet the required safety standards for the PLC (EN61131-2).

6-3 Conformance to EC Directives

The CS/CJ-series PLCs comply with EC Directives. To ensure that the
machine or device in which the CS/CJ-series PLC is used complies with EC
Directives, the PLC must be installed as follows:
1,2,3... 1. The CS/CJ-series PLC must be installed within a control panel.
2. You must use reinforced insulation or double insulation for the DC power
supplies used for the communications power supply and I/O power sup-
plies.
3. CS/CJ-series PLCs complying with EC Directives also conform to the
Common Emission Standard (EN61000-6-4). Radiated emission charac-
teristics (10-m regulations) may vary depending on the configuration of the
control panel used, other devices connected to the control panel, wiring,
and other conditions. You must therefore confirm that the overall machine
or equipment complies with EC Directives.

6-4 Relay Output Noise Reduction Methods

The CS/CJ-series PLCs conforms to the Common Emission Standards
(EN61000-6-4) of the EMC Directives. However, noise generated by relay out-
put switching may not satisfy these Standards. In such a case, a noise filter
must be connected to the load side or other appropriate countermeasures
must be provided external to the PLC.
Countermeasures taken to satisfy the standards vary depending on the
devices on the load side, wiring, configuration of machines, etc. Following are
examples of countermeasures for reducing the generated noise.

Countermeasures
(Refer to EN61000-6-4 for more details.)
Countermeasures are not required if the frequency of load switching for the
whole system with the PLC included is less than 5 times per minute.
Countermeasures are required if the frequency of load switching for the whole
system with the PLC included is more than 5 times per minute.

xxxix
Conformance to EC Directives 6

Countermeasure Examples
When switching an inductive load, connect an surge protector, diodes, etc., in
parallel with the load or contact as shown below.
Circuit Current Characteristic Required element
AC DC
CR method Yes Yes If the load is a relay or solenoid, thereThe capacitance of the capacitor must
is a time lag between the moment the be 1 to 0.5 µF per contact current of
circuit is opened and the moment the 1 A and resistance of the resistor must
load is reset. be 0.5 to 1 Ω per contact voltage of 1 V.
Inductive

If the supply voltage is 24 or 48 V, These values, however, vary with the

load

insert the surge protector in parallel load and the characteristics of the
Power relay. Decide these values from experi-
supply with the load. If the supply voltage is
100 to 200 V, insert the surge protector ments, and take into consideration that
between the contacts. the capacitance suppresses spark dis-
charge when the contacts are sepa-
rated and the resistance limits the
current that flows into the load when
the circuit is closed again.
The dielectric strength of the capacitor
must be 200 to 300 V. If the circuit is an
AC circuit, use a capacitor with no
polarity.
Diode method No Yes The diode connected in parallel with The reversed dielectric strength value
the load changes energy accumulated of the diode must be at least 10 times
by the coil into a current, which then as large as the circuit voltage value.
Inductive

flows into the coil so that the current The forward current of the diode must
will be converted into Joule heat by the be the same as or larger than the load
load

Power resistance of the inductive load. current.

supply
This time lag, between the moment the The reversed dielectric strength value
circuit is opened and the moment the of the diode may be two to three times
load is reset, caused by this method is larger than the supply voltage if the
longer than that caused by the CR surge protector is applied to electronic
method. circuits with low circuit voltages.
Varistor method Yes Yes The varistor method prevents the impo- ---
sition of high voltage between the con-
tacts by using the constant voltage
characteristic of the varistor. There is
Inductive

time lag between the moment the cir-

load

cuit is opened and the moment the load

Power
supply is reset.
If the supply voltage is 24 or 48 V,
insert the varistor in parallel with the
load. If the supply voltage is 100 to
200 V, insert the varistor between the
contacts.

When switching a load with a high inrush current such as an incandescent

lamp, suppress the inrush current as shown below.
Countermeasure 1 Countermeasure 2

R
OUT OUT
R
COM COM
Providing a dark current of Providing a limiting resistor
approx. one-third of the rated
value through an incandescent
lamp

xl
 SECTION 1
Introduction

This section provides information on general instruction characteristics as well as the errors that can occur during
instruction execution.

1-1 General Instruction Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1-1-1 Program Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1-1-2 Differentiated Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1-1-3 Instruction Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1-1-4 Instruction Location and Execution Conditions . . . . . . . . . . . . . . . . 5
1-1-5 Inputting Data in Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1-1-6 Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1-2 Instruction Execution Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1-2-1 Errors Occurring at Instruction Execution . . . . . . . . . . . . . . . . . . . . 13
1-2-2 Fatal Errors (Program Errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1
General Instruction Characteristics Section 1-1

1-1 General Instruction Characteristics

1-1-1 Program Capacity
The program capacity tells the size of the user program area in the CPU Unit
and is expressed as the number of program steps. The number of steps
required in the user program area for each of the CS/CJ-series instructions
varies from 1 to 7 steps, depending upon the instruction and the operands
used with it.
CS Series
The following tables show the maximum number of steps that can be pro-
grammed in each CS-series CPU Unit.
• CS1-H CPU Units
Model Program capacity I/O points
CS1H-CPU67H 250K steps 5,120
CS1H-CPU66H 120K steps
CS1H-CPU65H 60K steps
CS1H-CPU64H 30K steps
CS1H-CPU63H 20K steps
CS1G-CPU45H 60K steps
CS1G-CPU44H 30K steps 1,280
CS1G-CPU43H 20K steps 960
CS1G-CPU42H 10K steps

• CS1 CPU Units

Model Program capacity I/O points
CS1H-CPU67-E 250K steps 5,120
CS1H-CPU66-E 120K steps
CS1H-CPU65-E 60K steps
CS1H-CPU64-E 30K steps
CS1H-CPU63-E 20K steps
CS1G-CPU45-E 60K steps
CS1G-CPU44-E 30K steps 1,280
CS1G-CPU43-E 20K steps 960
CS1G-CPU42-E 10K steps

• CS1D CPU Units for Single-CPU Systems

Model Program capacity I/O points
CS1D-CPU67H 250K steps 5,120
CS1D-CPU65H 60K steps

CS1D CPU Units for Duplex-CPU Systems

Model Program capacity I/O points
CS1D-CPU42S 10K steps 960
CS1D-CPU44S 30K steps 1,280
CS1D-CPU65S 60K steps 5,120
CS1D-CPU67S 250K steps

CJ Series
The following tables show the maximum number of steps that can be pro-
grammed in each CJ-series CPU Unit.

2
General Instruction Characteristics Section 1-1

• CJ1-H CPU Units

Model Program capacity I/O points
CJ1H-CPU67H-R 250K steps 2,560
CJ1H-CPU66H-R 120K steps
CJ1H-CPU65H-R 60K steps
CJ1H-CPU64H-R 30K steps
CJ1H-CPU67H 250K steps
CJ1H-CPU66H 120K steps
CJ1H-CPU65H 60K steps
CJ1G-CPU45H 60K steps 1,280
CJ1G-CPU44H 30K steps
CJ1G-CPU43H 20K steps 960
CJ1G-CPU42H 10K steps

• CJ1 CPU Units

Model Program capacity I/O points
CJ1G-CPU45 60K steps 1,280
CJ1G-CPU44 30K steps

• CJ1M CPU Units

Model Program capacity I/O points
CJ1M-CPU23 20K steps 640
CJ1M-CPU22 10K steps 320
CJ1M-CPU21 5K steps 160
CJ1M-CPU13 20K steps 640
CJ1M-CPU12 10K steps 320
CJ1M-CPU11 5K steps 160

Note Program capacity for CS/CJ-series PLCs is measured in steps, whereas pro-
gram capacity for previous OMRON PLCs, such as the C-series and CV-
series PLCs, was measured in words. Basically speaking, 1 step is equivalent
to 1 word. The amount of memory required for each instruction, however, is
different for some of the CS/CJ-series instructions, and inaccuracies will occur
if the capacity of a user program for another PLC is converted for a CS/CJ-
series PLC based on the assumption that 1 word is 1 step. Refer to the infor-
mation at the end of SECTION 4 Instruction Execution Times and Number of
Steps for guidelines on converting program capacities from previous OMRON
PLCs.
The number of steps in a program is not the same as the number of instruc-
tions. For example, LD and OUT require 1 step each, but MOV(021) requires
3 steps. Other instructions require up to 15 steps each. The number of steps
required by an instruction is also increased by one step for each double-
length operand used in it. For example, MOVL(498) normally requires 3 steps,
but 4 steps will be required if a constant is specified for the source word oper-
and, S. Refer to SECTION 4 Instruction Execution Times and Number of
Steps for the number of steps required for each instruction.

1-1-2 Differentiated Instructions

Most instructions in CS/CJ-series PLCs are provided with both non-differenti-
ated and upwardly differentiated variations, and some are also provided with a
downwardly differentiated variation.
• A non-differentiated instruction is executed every time it is scanned.

3
General Instruction Characteristics Section 1-1

• An upwardly differentiated instruction is executed only once after its exe-

cution condition goes from OFF to ON.
• A downwardly differentiated instruction is executed only once after its exe-
cution condition goes from ON to OFF.
Variation Instruction type Operation Format Example
Non- Output instructions The instruction is exe- Output instruction
differentiated (instructions requiring cuted every cycle while executed each cycle MOV

an execution condi- the execution condition is

tion) true (ON).
Input instructions The bit processing (such Input instruction
executed each cycle
(instructions used as as read, comparison, or
execution conditions) test) is performed every
cycle. The execution con-
dition is true while the
result is ON.
Upwardly Output instructions The instruction is exe- Instruction executed
differentiated cuted just once when the once for upward @MOV
differentiation
(with @ prefix) execution condition goes MOV(021) executed once
from OFF to ON. for each OFF to ON transi-
tion in CIO 000102.

Input instructions The bit processing (such Upwardly differentiated

input instruction
(instructions used as as read, comparison, or
execution conditions) test) is performed every ON execution condition created
for one cycle only for each OFF
cycle. The execution con- to ON transition in CIO 000103.
dition is true for one cycle
when the result goes
from OFF to ON.
Downwardly Output instructions The instruction is exe- %Instruction 0001
differentiated cuted just once when the executed once for 02 %SET
downward SET executed once for
(with % prefix) execution condition goes differentiation each ON to OFF transition
from ON to OFF. in CIO 000102.

Input instructions The bit processing (such Downwardly differentiated 0001

(instructions used as as read, comparison, or input instruction 03

execution conditions) test) is performed every

cycle. The execution con-
dition is true for one cycle ON execution condition created
for one cycle only for each ON to
when the result goes OFF transition in CIO 000103.
from ON to OFF.

Note The downwardly differentiated option (%) is available only for the LD, AND,
OR, and RSET instructions. To create downwardly differentiated variations of
other instructions, control the execution of the instruction with work bits con-
trolled with DIFD(014) or DOWN(522).

1-1-3 Instruction Variations

The variation prefixes (@, %, and !) can be added to an instruction to create a
differentiated instruction or provide immediate refreshing.
Variation Prefix Operation
DifferentiationUpwardly dif- @ Creates an upwardly differentiated instruc-
ferentiated tion.
Downwardly % Creates a downwardly differentiated instruc-
differentiated tion.
Immediate refreshing ! The instruction’s operand data in the I/O
Area will be refreshed when the instruction
is executed.

4
General Instruction Characteristics Section 1-1

! @ MOV
Instruction mnemonic
Up-differentiation variation
Immediate-refreshing variation

1-1-4 Instruction Location and Execution Conditions

The following table shows the locations in which instructions can be pro-
grammed. The table also shows when an instruction requires an execution
condition and when it does not. Refer to SECTION 2 Summary of Instructions
for details on specific instructions.
Instruction type Location Execution Format Examples
condition
Input Instructions At the left bus or at Not required LD, LD TST, and input com-
that start the start of an parison instructions such as
logic instruction block LD >
conditions
Connecting Between a starting Required AND, OR, AND TST, input
instructions instruction and out- comparison instructions such
put instruction as AND >, UP, DOWN, NOT
Output At the right bus Required The majority of instructions
(such as OUT and MOV)

Not required Instructions such as END,

JME, FOR, and ILC

In addition to these instructions, the CS/CJ-series PLCs are equipped with

block programming instructions. Refer to the description of the block program-
ming instructions for details.
Note If an execution condition does not precede an instruction that requires one, a
program error will occur when the program is checked from a Peripheral
Device.
1-1-5 Inputting Data in Operands
Operands are parameters that are set in advance with the I/O memory
addresses or constants to be used when the instruction is executed. There
are basically three kinds of operands: Source operands, destination oper-
ands, and numbers.

MOV JMP
#0000 S (Source) &3 N (Number)
D00000 D (Destination)

Operand Usual Contents

code
Source Address containing S Source Source data other than
the data or the data operand control data
itself C Control Control data with a bit
data or bits controlling
instruction execution
Destination Address where the D ---
data will be stored
Number Contains a number N ---
such as a jump num-
ber or subroutine
number.

5
General Instruction Characteristics Section 1-1

Note An instruction’s operands may also be referred to by their position in the

instruction (first operand, second operand, ...). The codes used for the oper-
and vary with the specific function of the operand.

MOV
#0000 First operand
D00000 Second operand

Specifying Bit Addresses

Description Example Instruction example
To specify a bit address, specify the word 0001 02 0001
02
address and bit address directly.
Bit 02
@@@@ @@ Word CIO 0001
Bit number
Word address
Note The word address + bit number format is
not used for Timer/Counter Completion
Flags or Task Flags.

Specifying Word Addresses

Description Example Instruction example
To specify a word address, specify the word 0003 MOV 0003 D00200
address directly. Word CIO 0003
@@@@ D00200
Word address Word D00200

Specifying Indirect DM/EM Addresses in Binary Mode

Description Example Instruction example
When the @ prefix is input before a DM or EM --- ---
address, the contents of that word specifies
another word that is used as the operand. The
contents can be 0000 to 7FFF (0 to 32,767),
corresponding to the desired word address in the
DM or EM Area.

@D@@@@@

Content 00000 to 32767

(0000 to 7FFF)

When the contents of @D@@@@@ is between @D00300 MOV #0001

0000 and 7FFF (00000 to 32,767), the corre- @D00300
sponding word between D00000 and D32767 is 0 1 0 0
specified.
Decimal: 256

Specifies D00256.

Add the @ prefix.

6
General Instruction Characteristics Section 1-1

Description Example Instruction example

When the contents of @D@@@@@ is between @D00300 ---
8000 and FFFF (32,768 to 65,535), the corre-
sponding word between E0_00000 and E0_32767 8 0 0 1
in EM bank 0 is specified.
Decimal: 32,769

Specifies E0_00001.

When the contents of @En@_@@@@@ is between @E1_00200 MOV #0001

0000 and 7FFF (00000 to 32,767), the corre- @E1_00200
sponding word between En@_00000 and 0 1 0 1
En@_32767 is specified.
Decimal: 257

Specifies E1_00257.

When the contents of @En@_@@@@@ is between @E1_00200

8000 and FFFF (32,768 to 65,535), the corre-
sponding word between E (@+1) _00000 and E 8 0 0 2
(@+1) _32767 (in the next EM bank) is specified.
Decimal: 32770

Specifies E2_00002.

Note When binary mode is selected in the PLC Setup, the DM Area and current EM
bank addresses (bank 0 to C) are treated as consecutive memory addresses.
A word in EM bank 0 will be specified if an indirectly addressed DM word con-
tains a value greater than 32,767. For example, E00000 in bank 0 will be
specified when the indirect-addressing DM word contains a hexadecimal
value of 8000 (32,768).
A word in the next EM bank will be specified if an indirectly addressed EM
word contains a value greater than 32,767. For example, E3_00000 will be
specified when the indirect-addressing EM word in bank 2 contains a hexa-
decimal value of 8000 (32,768).

Specifying Indirect DM/EM Addresses in BCD Mode

Method Description Example Instruction example
Indirect DM/EM When the * prefix is input before a DM *D00200 MOV #0001 *D00200
addressing or EM address, the BCD contents of
(BCD mode) that word specify another word that is 0 1 0 0
used as the operand. The contents can
be 0000 to 9999, corresponding to the
desired word address in the DM or EM Specifies D00100.
Area.
Add the * prefix.
*D@@@@@

Content 0000 to 9999

(BCD)

7
General Instruction Characteristics Section 1-1

Addressing Index Registers

Method Description Example Instruction example
Directly MOVR(560) moves the PLC memory address of a IR0 MOVR 0010 IR0
addressing word or bit to an Index Register (IR0 to IR15). IR2 Stores the PLC memory address
Index Registers (MOVRW(561) moves the PLC memory address of of CIO 0010 in IR0.
a timer or counter PV to an Index Register.) MOVR 000102 IR2
Stores the PLC memory address
of CIO 000102 in IR2.
Indirect Basic opera- The word or bit at the I/O memory ,IR0 LD ,IR0
addressing with tion (no offset) address contained in IR@ is used ,IR1 Loads the status of the bit at the
Index Registers as the operand. Input a comma I/O memory address contained in
before the Index Register to indi- IR0.
cate indirect addressing. MOV #0001, IR1
(The bit/word designation can be Moves #0001 to the word at the
determined by the instruction or I/O memory address contained in
operand.) IR1.
Constant offset The offset value (–2,048 to +5 ,IR0 LD +5 ,IR0
+2,047) is added to the I/O mem- +31 ,IR1 Adds 5 to the I/O memory
ory address contained in IR@ and address contained in IR0 and
the resulting address is used as loads the status of the bit at that
the operand. address.
(The offset is converted to binary MOV #0001 +31 ,IR1
when the instruction is executed.) Adds 31 to the I/O memory
address contained in IR1 and
moves #0001 to the word at that
address.
DR offset The signed binary content of the DR0 ,IR0 LD DR0 ,IR0
Data Register is added to the I/O DR0 ,IR1 Adds the content of DR0 to the
memory address contained in I/O memory address contained in
IR@ and the resulting address is IR0 and loads the status of the bit
used as the operand. at that address.
MOV #0001 DR0 ,IR1
Adds the content of DR0 to the
I/O memory address contained in
IR1 and moves #0001 to the word
at that address.
Auto-increment After the I/O memory address is ,IR0 + + LD ,IR0 + +
read from IR@, the content of the ,IR1 + Loads the status of the bit at the
Index Register is incremented by I/O memory address contained in
one or two. IR0 and then increments the reg-
Increment by 1: ,R@+ ister by two.
Increment by 2: ,IR@++ MOV #0001 ,IR1 +
Note Index registers will be incre- Moves #0001 to the word at the
mented when the instruction I/O memory address contained in
is executed even if an error IR1 and then increments the reg-
occurs and the Error Flag ister by one.
turns ON.
Auto-decre- The content of IR@ is decre- , – – IR0 LD , – – IR0
ment mented by one or two and then , – IR1 Decrements the content of IR0 by
the I/O memory address in the two and then loads the status of
register is used as the operand. the bit at that I/O memory
Decrement by 1: ,– IR@ address.
Decrement by 2: ,– –IR@ MOV #0001 , – IR1
Note Index registers will be dec- Decrements the content of IR0 by
remented when the instruc- one and then moves #0001 to the
tion is executed even if an word at that I/O memory address.
error occurs and the Error
Flag turns ON.

Note Make sure that the contents of index registers indicate valid I/O memory
addresses.

8
General Instruction Characteristics Section 1-1

Specifying Constants
Method Applicable Data Code Range Example
operands format
Constant All binary data Unsigned # #0000 to #FFFF MOV #0100 D00000
(16-bit data) and binary data binary Stores #0100 hex (&256 decimal)
within a range in D00000.
+#0009 #0001 D00001
Stores #000A hex (&10 decimal)
in D00001.
Signed dec- ± –32,768 to +32,767 MOV −100 D00000
imal Stores −100 decimal (#FF9C hex)
in D00000.
+−9 −1 D00001
Stores −10 decimal (#FFF6 hex)
in D00001.
Unsigned & &0 to &66,535 MOV &256 D00000
decimal Stores −256 decimal (#0100 hex)
in D00000.
+&9 &1 D00001
Stores −10 decimal (#000A hex)
in D00001.
All BCD data BCD # #0000 to #9999 MOV #0100 D00000
and BCD data Stores #0100 (BCD) in D00000.
within a range +B #0009 #0001 D00001
Stores #0010 (BCD) in D00001.
Constant All binary data Unsigned # #0000 0000 to MOVL #12345678 D00000
(32-bit data) and binary data binary #FFFF FFFF Stores #12345678 hex in D00000
within a range and D00001.
D0001 D00000

1234 5678

Signed dec- + –2,147,483,648 to MOVL −12345678 D00000

imal – +2,147,483,647 Stores −12345678 decimal in
D00000 and D00001.
Unsigned & &0 to &4,294,967,295 MOVL &12345678 D00000
decimal Stores &12345678 decimal in
D00000 and D00001.
All BCD data BCD # #0000 0000 to MOVL #12345678 D00000
and BCD data #9999 9999 Stores #12345678 (BCD) in
within a range D00000 and D00001

Specifying Text Strings

Method Description Code Examples Instruction example
Text strings Text is stored in ASCII (1 byte/ "ABCDE" MOV$ D00100 D00200
character excluding special 41 42
"A" "B" D00100
characters) starting with the
"C" "D" D00101 43 44
lower byte of the lowest word
in the range. "E" NUL D00102 45 00
If there is an odd number of 41 42
characters, 00 (NULL) is 43 44
stored in the higher byte of the D00200 41 42
45 00 43 44
last word in the range. D00201
"ABCD" D00202 45 00
If there is an even number of
characters, 0000 (two NULLs) "A" "B"
are stored in the word after the "C" "D"
last in the range. NUL NUL

41 42
43 44
00 00

9
General Instruction Characteristics Section 1-1

The following diagram shows the characters that can be expressed in ASCII.

Leftmost bit

SP

Rightmost bit

Note The following instructions are executed even when the input conditions are
OFF. Therefore, when indirect memory addresses are specified using auto-
incrementing or auto-decrementing (,IR+ or ,IR-) in an operand of any of
these instructions, the value in the Index Register (IR) is refreshed each cycle
regardless of the input condition (increases or decreases one every cycle).
This must be considered when writing a program.
Classification Instructions
Sequence input LD, LD NOT, AND, AND NOT, OR, OR NOT, LD TST(350),
instructions LD TSTN(351), AND TST(350), AND TSTN(351), OR
TST(350), OR TSTN(351)
Sequence output OUT, OUT NOT, DIFU(013), DIFD(014)
instructions
Sequence control JMP(004), FOR(512)
instructions
Timer and counter TIM/TIMX(550), TIMH(015)/TIMHX(551), TMHH(540)/
instructions TMHHX(552), TIMU(541)/TIMUX(556), TMUH(544)/
TMUHX(557), TTIM(087)/TTIMX(555), TIML(542)/
TIMLX(553), MTIM(533)/MTIMX(554), CNT/CNTX(546),
CNTR(012)/CNTRX(548)
Comparison instruc- Symbol comparison instructions (LD, AND, OR =, etc.(func-
tions tion codes: 300, 305, 310, 320, and 325))
Single-precision float- Single-precision floating-point data comparison (LD, AND,
ing-point math instruc- OR = F, etc.(function codes: 329 to 334))
tions
Double-precision float- Double-precision floating-point data comparison (LD, AND,
ing-point math instruc- OR = D, etc.(function codes: 335 to 340))
tions

10
General Instruction Characteristics Section 1-1

Classification Instructions
Block programming BPPS(811), BPRS(812), EXIT(806), EXIT(806) NOT,
instructions IF(802), IF(802) NOT, WAIT(805), WAIT(805) NOT,
TIMW(813)/TIMWX(816), CNTW(814)/CNTWX(818),
TMHW(815)/TMHWX(817), LEND(810), LEND(810) NOT
Text string processing STRING COMPARISON (LD, AND, OR = $, etc. (function
instructions codes: 670 to 675))

The following ladder programming examples show how the index registers are
treated.
Example 1
Ladder Program:
LD P_Off
OUT, IR0+
Operation: When the PLC memory address 000013 is stored in IR0.
The input condition is OFF (P_Off is the Always OFF Flag), so the OUT
instruction sets 000013, which is indirectly addressed by IR0, to OFF. The
OUT instruction is executed, so IR0 is incremented. As a result, the PLC
memory address 000014, which was incremented by +1 in the IR0, is stored.
Therefore, in the following cycle the OUT instruction turns OFF 000014.
Example 2
Ladder Program:
LD P_Off
SET, IR0+
Operation: When the PLC memory address 000013 is stored in IR0.
The input condition is OFF (P_Off is the Always OFF Flag), so the SET
instruction is not executed. Therefore, IR0 is not incremented and the value
stored in IR0 remains PLC memory address 000013.

1-1-6 Data Formats

The following table shows the data formats that can be used in CS/CJ-series
PLCs.
Name Format Decimal Hexadecimal
range range
Unsigned 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 to 0000 to FFFF
binary 65,535
data
Binary 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
Decimal 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1
Hexa- 23 22 21 20 23 22 21 20 23 22 21 20 23 22 21 20
decimal

Signed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 –32,768 8000 to 7FFF

binary to
data +32,767
Binary 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
Decimal -32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1
Hexa- 23 22 21 20 23 22 21 20 23 22 21 20 23 22 21 20
decimal
Sign bit
0: Positive
1: Negative

11
General Instruction Characteristics Section 1-1

Name Format Decimal Hexadecimal

range range
BCD data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 to 9,999 0000 to 9999

BCD 23 22 21 20 23 22 21 20 23 22 21 20 23 22 21 20

Decimal 0 to 9 0 to 9 0 to 9 0 to 9

Floating- 31 30 29 23 22 21 20 19 18 17 3 2 1 0 --- ---

point deci-
mal

Sign of Exponent Mantissa

Binary
mantissa

Value = (−1)Sign x 1.[Mantissa] x 2Exponent

Sign (bit 31) 1: negative or 0: positive
Mantissa The mantissa includes 23 bits from bit 00 to bit 22
and indicates this portion below the decimal point
in 1.@@@..... in binary.
Exponent The exponent includes 8 bits from bit 23 to bit 30
and indicates n plus 127 in 2n in binary.

Note This format conforms to IEEE754 standards for single-precision floating-point data
and is used only with instructions that convert or calculate floating-point data. It can
be used to set or monitor from the I/O memory Edit and Monitor Screen on the CX-
Programmer (not supported by the Programming Consoles). As such, users do not
need to know this format although they do need to know that the formatting takes up
two words.

Double- 63 62 61 52 51 50 49 48 47 46 3 2 1 0 --- ---

precision
floating-
point deci-
mal Sign of Exponent Mantissa
mantissa Binary

Value = (−1)Sign x 1.[Mantissa] x 2Exponent

Sign (bit 63) 1: negative or 0: positive
Mantissa The 52 bits from bit 00 to bit 51 contain the mantissa,
i.e., the portion below the decimal point in 1.@@@.....,
in binary.
Exponent The 11 bits from bit 52 to bit 62 contain the exponent
The exponent is expressed in binary as 1023 plus n in
2n.
Note This format conforms to IEEE754 standards for double-precision floating-point
data and is used only with instructions that convert or calculate floating-point
data. It can be used to set or monitor from the I/O memory Edit and Monitor
Screen on the CX-Programmer (not supported by the Programming
Consoles). As such, users do not need to know this format although they do
need to know that the formatting takes up four words.

Signed Binary Numbers Negative signed-binary numbers are expressed as the 2’s complement of the
absolute hexadecimal value. For a decimal value of –12,345, the absolute
value is equivalent to 3039 hexadecimal. The 2’s complement is 10000 – 3039
(both hexadecimal) or CFC7.
To convert from a negative signed binary number (CFC7) to decimal, take the
2’s complement of that number (10000 – CFC7 = 3039), convert to decimal
(3039 hexadecimal = 12,345 decimal), and add a minus sign (–12,345).

12
Instruction Execution Checks Section 1-2

1-2 Instruction Execution Checks

1-2-1 Errors Occurring at Instruction Execution
An instruction’s operands and placement are checked when an instruction is
input from a Peripheral Device or a program check is performed from a
Peripheral Device (other than a Programming Console), but these are not final
checks. The following four errors can occur when an instruction is executed.
Instruction Processing Error (ER Flag ON)
Normally, Instruction Processing Errors are non-fatal errors, but the PLC
Setup can be set to treat Instruction Processing Errors as fatal errors. If this
setting has been made, the Instruction Processing Error Flag (A29508) will be
turned ON and program execution will stop when an Instruction Processing
Error occurs.
Access Error (AER Flag ON)
Normally, Access Errors are non-fatal errors, but the PLC Setup can be set to
treat these errors as fatal errors. If this setting has been made, the Illegal
Access Error Flag (A29510) and the Indirect DM/EM BCD Error Flag
(A29509) will be turned ON and program execution will stop when an Access
Error occurs.
Illegal Instruction Error
The Illegal Instruction Error Flag (A29514) will be turned ON and program
execution will stop when this error occurs.
UM (User Program Memory) Overflow Error
The UM Overflow Error Flag (A29515) will be turned ON and program execu-
tion will stop when this error occurs.

1-2-2 Fatal Errors (Program Errors)

Program execution will be stopped when one of the following program errors
occurs. When a program error has occurred, the task number of the task that
was being executed when program execution was stopped is written to A294
and the program address is written to A298 and A299.
Use the contents of these words to locate the program error and correct it as
necessary.
Address Description
A294 The task number of the current task is written to this word when pro-
gram execution is stopped because of a program error.
Cyclic tasks have task numbers 0000 to 001F (cyclic tasks 0 to 31).
Interrupt tasks have task numbers 8000 to 80FF (interrupt tasks 0 to
255).
A298 and The current program address is written to these words when program
A299 execution is stopped because of a program error.
A299 contains the leftmost digits of the program address and A298
contains the rightmost digits of the program address.

13
Instruction Execution Checks Section 1-2

All errors for which the Error Flag or Access Error Flag turns ON is treated as
a program error The following table lists program errors. The PLC Setup can
be set to stop program execution when one of these errors occurs.
Error type Description Related flags
No END Instruction There is no END(001) instruction in the program. No END Error Flag
(A29511)
Task Error There are three possible causes of a task error: Task Error Flag (A29512)
1) There is not an executable cyclic task.
2) There is not a program allocated to the task.
3) An interrupt was generated but the corresponding interrupt
task does not exist.
Instruction Processing The CPU attempted to execute an instruction, but the data Error (ER) Flag,
Error* provided in the instruction’s operand was incorrect. Instruction Processing
*If the PLC Setup has been set to treat instruction errors as Error Flag (A29508)
fatal errors (program errors), the Instruction Processing Error
Flag (A29508) will be turned ON and program execution will
stop.
Access Error* There are five possible causes of an access error: Access Error (AER) Flag,
1) Reading/writing to the parameter area. Illegal Access Error Flag
2) Writing to memory that is not installed. (A29510)
3) Reading/writing to an EM bank that is EM file memory.
4) Writing to a read-only area.
5) The contents of a DM/EM word was not BCD although the
PLC is set for BCD indirect addressing.
*If the PLC Setup has been set to treat instruction errors as
fatal errors (program errors), the Illegal Access Error Flag
(A29510) will be turned ON and program execution will stop.
Indirect DM/EM BCD The contents of a DM/EM word was not BCD although the Access Error (AER) Flag,
Error* PLC is set for BCD indirect addressing. Indirect DM/EM BCD Error
*If the PLC Setup has been set to treat instruction errors as Flag (A29509)
fatal errors (program errors), the Indirect DM/EM BCD Error
Flag (A29509) will be turned ON and program execution will
stop.
Differentiation Overflow Differentiated instructions were repeatedly inserted and Differentiation Overflow
Error deleted during online editing (over 31,072 times). Error Flag (A29513)
UM Overflow Error The last address in UM (user program memory) has been UM Overflow Error Flag
exceeded. (A29515)
Illegal Instruction Error The program contains an instruction that cannot be executed. Illegal Instruction Error
Flag (A29514)

14
 SECTION 2
Summary of Instructions

This section provides a summary of instructions used with CS/CJ-series PLCs.

2-1 Instruction Classifications by Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2-2 Instruction Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2-2-1 Sequence Input Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2-2-2 Sequence Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2-2-3 Sequence Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2-2-4 Timer and Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2-2-5 Comparison Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2-2-6 Data Movement Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2-2-7 Data Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2-2-8 Increment/Decrement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2-2-9 Symbol Math Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2-2-10 Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2-2-11 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2-2-12 Special Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2-2-13 Floating-point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2-2-14 Double-precision Floating-point Instructions. . . . . . . . . . . . . . . . . . 71
2-2-15 Table Data Processing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 75
2-2-16 Data Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2-2-17 Subroutine Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2-2-18 Interrupt Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2-2-19 High-speed Counter and Pulse Output Instructions
(CJ1M-CPU21/22/23 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2-2-20 Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2-2-21 Basic I/O Unit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2-2-22 Serial Communications Instructions. . . . . . . . . . . . . . . . . . . . . . . . . 92
2-2-23 Network Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2-2-24 File Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2-2-25 Display Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2-2-26 Clock Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2-2-27 Debugging Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2-2-28 Failure Diagnosis Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2-2-29 Other Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2-2-30 Block Programming Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
2-2-31 Text String Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 108
2-2-32 Task Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2-2-33 Model Conversion Instructions (CPU Unit Ver. 3.0 or Later Only) . 112
2-2-34 Special Function Block Instructions. . . . . . . . . . . . . . . . . . . . . . . . . 113
2-3 Alphabetical List of Instructions by Mnemonic . . . . . . . . . . . . . . . . . . . . . . . 114
2-4 List of Instructions by Function Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

15
Instruction Classifications by Function Section 2-1

2-1 Instruction Classifications by Function

The following table lists the CS/CJ-series instructions by function. (The
instructions appear by order of their function in Section 3 Instructions.)
*Instructions or instruction groups marked with a single asterisk are supported
by CS1-H, CJ1-H, CJ1M, and CS1D CPU Units only.
**Instructions or instruction groups marked with two asterisks are supported
by CJ1M CPU Units only.
***Instructions or instruction groups marked with three asterisks are not sup-
ported by CS1D CPU Units for Duplex-CPU Systems.

Note 1. CS/CJ-series CPU Unit Ver. 2.0 or later only

2. CJ1-H-R CPU Units only.
3. CJ1M-CPU21/22/23 CPU Unit Ver. 2.0 or later only
4. CS/CJ-series CPU Unit Ver. 2.0 or later only
CJ1M CPU Unit (Pre-Ver. 2.0 or Unit Ver. 2.0 or later)
Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction
tion
Basic Input LD LOAD LD NOT LOAD NOT AND AND
instructions
AND NOT AND NOT OR OR OR NOT OR NOT
AND LD AND LOAD OR LD OR LOAD --- ---
Output OUT OUTPUT OUT NOT OUTPUT NOT --- ---
Sequence --- NOT NOT UP CONDITION DOWN CONDITION
input ON OFF
instructions
Bit test LD TST LD BIT TEST LD TSTN LD BIT TEST AND TST AND BIT
NOT TEST NOT
AND TSTN AND BIT OR TST OR BIT TEST OR TSTN OR BIT TEST
TEST NOT NOT
Sequence --- KEEP KEEP DIFU DIFFERENTI- DIFD DIFFERENTI-
output ATE UP ATE DOWN
instructions
OUTB* SINGLE BIT --- --- --- ---
OUTPUT
Set/Reset SET SET RSET RESET SETA MULTIPLE
BIT SET
RSTA MULTIPLE SETB* SINGLE BIT RSTB* SINGLE BIT
BIT RESET SET RESET
Sequence --- END END NOP NO OPERA- --- ---
control TION
instructions
Interlock IL INTERLOCK ILC INTERLOCK MILH MULTI-INTER-
CLEAR LOCK DIF-
FERENTIATIO
N HOLD
MILR MULTI-INTER- MILC MULTI-INTER- --- ---
(See note 1.) LOCK DIF- (See note 1.) LOCK CLEAR
FERENTIATIO
N RELEASE
Jump JMP JUMP JME JUMP END CJP CONDI-
TIONAL
JUMP
CJPN CONDI- JMP0 MULTIPLE JME0 MULTIPLE
TIONAL JUMP JUMP END
JUMP
Repeat FOR FOR-NEXT BREAK BREAK LOOP NEXT FOR-NEXT
LOOPS LOOPS

16
Instruction Classifications by Function Section 2-1

Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction

tion
Timer and BCD Timer TIM HUNDRED- TIMH TEN-MS TMHH ONE-MS
counter (with MS TIMER TIMER TIMER
instructions timer
numbers) TIMU TENTH-MS TMUH HUN- TTIM ACCUMULA-
(See note 2.) TIMER (See note 2.) DREDTH-MS TIVE TIMER
TIMER
Timer TIML LONG TIMER MTIM MULTI-OUT- --- ---
(without PUT TIMER
timer
numbers)
Counter CNT COUNTER CNTR REVERSIBLE CNR RESET
(with TIMER TIMER/
counter COUNTER
numbers)
Binary* Timer TIMX HUNDRED- TIMHX TEN-MS TMHHX ONE-MS
(with MS TIMER TIMER TIMER
timer
numbers) TIMUX TENTH-MS TMUHX HUN- TTIMX ACCUMULA-
(See note 2.) TIMER (See note 2.) DREDTH-MS TIVE TIMER
TIMER
Timer TIMLX LONG TIMER MTIMX MULTI-OUT- --- ---
(without PUT TIMER
timer
numbers)
Counter CNTX COUNTER CNTRX REVERSIBLE CNRX RESET
(with TIMER TIMER/
counter COUNTER
numbers)
Comparison Symbol LD, AND, OR Symbol com- LD, AND, OR Symbol com- LD, AND, OR Symbol
instructions comparison + parison + parison (dou- + comparison
=, <>, <, <=, >, (unsigned) =, <>, <, <=, >, ble-word, =, <>, <, <=, >, (signed)
>= >= + L unsigned) >= +S
LD, AND, OR Symbol com- LD, AND, OR Time compari- --- ---
+ parison (dou- + son
=, <>, <, <=, >, ble-word, = DT, <> DT, <
>= + SL signed) DT, <= DT, >
DT, >= DT
(See note 1.)
Data CMP UNSIGNED CMPL DOUBLE CPS SIGNED
comparison COMPARE UNSIGNED BINARY
(Condition Flags) COMPARE COMPARE
CPSL DOUBLE ZCP* AREA RANGE ZCPL* DOUBLE
SIGNED COMPARE AREA RANGE
BINARY COMPARE
COMPARE
Table MCMP MULTIPLE TCMP TABLE COM- BCMP UNSIGNED
compare COMPARE PARE BLOCK COM-
PARE
BCMP2 EXPANDED --- --- --- ---
(See note 3.) BLOCK COM-
PARE
Data Single/ MOV MOVE MOVL DOUBLE MVN MOVE NOT
movement double-word MOVE
instructions
MVNL DOUBLE --- --- --- ---
MOVE NOT
Bit/digit MOVB MOVE BIT MOVD MOVE DIGIT --- ---
Exchange XCHG DATA XCGL DOUBLE --- ---
EXCHANGE DATA
EXCHANGE
Block/bit transfer XFRB MULTIPLE XFER BLOCK BSET BLOCK SET
BIT TRANS- TRANSFER
FER
Distribute/ collect DIST SINGLE COLL DATA COL- --- ---
WORD DIS- LECT
TRIBUTE
Index register MOVR MOVE TO MOVRW MOVE TIMER/ --- ---
REGISTER COUNTER PV
TO REGIS-
TER

17
Instruction Classifications by Function Section 2-1

Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction

tion
Data shift 1-bit shift SFT SHIFT REG- SFTR REVERSIBLE ASLL DOUBLE
instructions ISTER SHIFT REG- SHIFT LEFT
ISTER
ASL ARITHMETIC ASR ARITHMETIC ASRL DOUBLE
SHIFT LEFT SHIFT RIGHT SHIFT RIGHT
0000 hex asynchro- ASFT ASYNCHRO- --- --- --- ---
nous NOUS SHIFT
REGISTER
Word shift WSFT WORD SHIFT --- --- --- ---
1-bit rotate ROL ROTATE LEFT ROLL DOUBLE RLNC ROTATE LEFT
ROTATE LEFT WITHOUT
CARRY
RLNL DOUBLE ROR ROTATE RORL DOUBLE
ROTATE LEFT RIGHT ROTATE
WITHOUT RIGHT
CARRY
RRNC ROTATE RRNL DOUBLE --- ---
RIGHT WITH- ROTATE
OUT CARRY RIGHT WITH-
OUT CARRY
1 digit shift SLD ONE DIGIT SRD ONE DIGIT --- ---
SHIFT LEFT SHIFT RIGHT
Shift n-bit data NSFL SHIFT N-BIT NSFR SHIFT N-BIT --- ---
DATA LEFT DATA RIGHT
Shift n-bit NASL SHIFT N-BITS NSLL DOUBLE NASR SHIFT N-BITS
LEFT SHIFT N-BITS RIGHT
LEFT
NSRL DOUBLE --- --- --- ---
SHIFT N-BITS
RIGHT
Increment/ BCD ++B INCREMENT ++BL DOUBLE – –B DECRE-
decrement BCD INCREMENT MENT BCD
instructions BCD
– –BL DOUBLE --- --- --- ---
DECRE-
MENT BCD
Binary ++ INCREMENT ++L DOUBLE –– DECRE-
BINARY INCREMENT MENT
BINARY BINARY
– –L DOUBLE --- --- --- ---
DECRE-
MENT
BINARY

18
Instruction Classifications by Function Section 2-1

Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction

tion
Symbol Binary add + SIGNED +L DOUBLE +C SIGNED
math BINARY ADD SIGNED BINARY ADD
instructions WITHOUT BINARY ADD WITH CARRY
CARRY WITHOUT
CARRY
+CL DOUBLE --- --- --- ---
SIGNED
BINARY ADD
WITH CARRY
BCD add +B BCD ADD +BL DOUBLE BCD +BC BCD ADD
WITHOUT ADD WITH CARRY
CARRY WITHOUT
CARRY
+BCL DOUBLE BCD --- --- --- ---
ADD WITH
CARRY
Binary subtract – SIGNED –L DOUBLE –C SIGNED
BINARY SUB- SIGNED BINARY
TRACT BINARY SUBTRACT
WITHOUT SUBTRACT WITH CARRY
CARRY WITHOUT
CARRY
–CL DOUBLE --- --- --- ---
SIGNED
BINARY WITH
CARRY
BCD subtract –B BCD –BL DOUBLE BCD –BC BCD
SUBTRACT SUBTRACT SUBTRACT
WITHOUT WITHOUT WITH CARRY
CARRY CARRY
–BCL DOUBLE BCD --- --- --- ---
SUBTRACT
WITH CARRY
Binary multiply * SIGNED *L DOUBLE *U UNSIGNED
BINARY SIGNED BINARY
MULTIPLY BINARY MULTIPLY
MULTIPLY
*UL DOUBLE --- --- --- ---
UNSIGNED
BINARY
MULTIPLY
BCD multiply *B BCD *BL DOUBLE BCD --- ---
MULTIPLY MULTIPLY
Binary divide / SIGNED /L DOUBLE /U UNSIGNED
BINARY SIGNED BINARY
DIVIDE BINARY DIVIDE
DIVIDE
/UL DOUBLE --- --- --- ---
UNSIGNED
BINARY
DIVIDE
BCD divide /B BCD DIVIDE /BL DOUBLE BCD --- ---
DIVIDE

19
Instruction Classifications by Function Section 2-1

Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction

tion
Conversion BCD-binary con- BIN BCD TO BINL DOUBLE BCD BCD BINARY TO
instructions versions BINARY TO DOUBLE BCD
BINARY
BCDL DOUBLE NEG 2’S COMPLE- NEGL DOUBLE 2’S
BINARY TO MENT COMPLE-
DOUBLE BCD MENT
SIGN 16-BIT TO --- --- --- ---
32-BIT
SIGNED
BINARY
Decoder/ encoder MLPX DATA DMPX DATA --- ---
DECODER ENCODER
ASCII-hexadecimal ASC ASCII CON- HEX ASCII TO HEX --- ---
conversions VERT
Line-column con- LINE COLUMN TO COLM LINE TO --- ---
versions LINE COLUMN
Signed binary-BCD BINS SIGNED BCD BISL DOUBLE BCDS SIGNED
conversions TO BINARY SIGNED BCD BINARY TO
TO BINARY BCD
BDSL DOUBLE GRY GRAY CODE --- ---
SIGNED (See note 1.) CONVER-
BINARY TO SION
BCD
Number-ASCII con- STR4 FOUR-DIGIT STR8 EIGHT-DIGIT STR16 SIXTEEN-
versions NUMBER TO NUMBER TO DIGIT NUM-
ASCII ASCII BER TO ASCII
NUM4 ASCII TO NUM8 ASCII TO NUM16 ASCII TO SIX-
FOUR-DIGIT EIGHT-DIGIT TEEN-DIGIT
NUMBER NUMBER NUMBER
Logic Logical AND/OR ANDW LOGICAL ANDL DOUBLE ORW LOGICAL OR
instructions AND LOGICAL
AND
ORWL DOUBLE XORW EXCLUSIVE XORL DOUBLE
LOGICAL OR OR EXCLUSIVE
OR
XNRW EXCLUSIVE XNRL DOUBLE --- ---
NOR EXCLUSIVE
NOR
Complement COM COMPLE- COML DOUBLE --- ---
MENT COMPLE-
MENT
Special --- ROTB BINARY ROOT BCD SQUARE APR ARITHMETIC
math ROOT ROOT PROCESS
instructions
FDIV FLOATING BCNT BIT --- ---
POINT COUNTER
DIVIDE

20
Instruction Classifications by Function Section 2-1

Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction

tion
Floating- Floating point/ FIX FLOATING TO FIXL FLOATING TO FLT 16-BIT TO
point math binary convert 16-BIT 32-BIT FLOATING
instructions
FLTL 32-BIT TO --- --- --- ---
FLOATING
Floating- point +F FLOATING- –F FLOATING- /F FLOATING-
basic math POINT ADD POINT POINT
SUBTRACT DIVIDE
*F FLOATING- --- --- --- ---
POINT
MULTIPLY
High-speed trigo- SINQ HIGH-SPEED CONQ HIGH-SPEED TANQ HIGH-SPEED
nometric functions SINE COSINE TANGENT
(See note 2.)
Floating- point RAD DEGREES TO DEG RADIANS TO SIN SINE
trigonometric func- RADIANS DEGREES
tions
COS COSINE TAN TANGENT ASIN ARC SINE
ACOS ARC COSINE ATAN ARC TAN- --- ---
GENT
Floating- point SQRT SQUARE EXP EXPONENT LOG LOGARITHM
math ROOT
PWR EXPONEN- --- --- --- ---
TIAL POWER
Symbol compari- LD, AND, OR Symbol com- FSTR* FLOATING- FVAL* ASCII TO
son and conver- + parison (sin- POINT TO FLOATING-
sion* =, <>, <, <=, >, gle-precision ASCII POINT
>= + F floating point)
Single-precision MOVF MOVE FLOAT- --- --- --- ---
floating point move ING-POINT
(See note 2.) (SINGLE)
Double-pre- Floating point/ FIXD DOUBLE FIXLD DOUBLE DBL 16-BIT TO
cision float- binary convert FLOATING TO FLOATING TO DOUBLE
ing- point 16-BIT 32-BIT FLOATING
instruc-
tions* DBLL 32-BIT TO --- --- --- ---
DOUBLE
FLOATING
Floating- point +D DOUBLE –D DOUBLE /D DOUBLE
basic math FLOATING- FLOATING- FLOATING-
POINT ADD POINT POINT
SUBTRACT DIVIDE
*D DOUBLE --- --- --- ---
FLOATING-
POINT
MULTIPLY
Floating- point RADD DOUBLE DEGD DOUBLE SIND DOUBLE
trigonometric func- DEGREES TO RADIANS TO SINE
tions RADIANS DEGREES
COSD DOUBLE TAND DOUBLE ASIND DOUBLE ARC
COSINE TANGENT SINE
ACOSD DOUBLE ARC ATAND DOUBLE ARC --- ---
COSINE TANGENT
Floating- point SQRTD DOUBLE EXPD DOUBLE LOGD DOUBLE
math SQUARE EXPONENT LOGARITHM
ROOT
PWRD DOUBLE --- --- --- ---
EXPONEN-
TIAL POWER
Symbol compari- LD, AND, OR Symbol com- --- --- --- ---
son + parison (dou-
=, <>, <, <=, >, ble-precision
>= + D floating point)

21
Instruction Classifications by Function Section 2-1

Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction

tion
Table data Stack SSET SET STACK PUSH PUSH ONTO LIFO LAST IN
processing processing STACK FIRST OUT
instructions
FIFO FIRST IN SNUM* STACK SIZE SREAD* STACK DATA
FIRST OUT READ READ
SWRIT* STACK DATA SINS* STACK DATA SDEL* STACK DATA
OVERWRITE INSERT DELETE
1-record/ DIM DIMENSION SETR SET RECORD GETR GET
multiple-word pro- RECORD LOCATION RECORD
cessing TABLE NUMBER
Record-to- word SRCH DATA MAX FIND MIN FIND
processing SEARCH MAXIMUM MINIMUM
SUM SUM FCS FRAME --- ---
CHECKSUM
Byte SWAP SWAP BYTES --- --- --- ---
processing
Data control --- PID PID CON- PIDAT* PID CON- LMT LIMIT
instructions TROL TROL WITH CONTROL
AUTOTUNING
BAND DEAD BAND ZONE DEAD ZONE TPO TIME-PRO-
CONTROL CONTROL (See note 1.) PORTIONAL
OUTPUT
SCL SCALING SCL2 SCALING 2 SCL3 SCALING 3
AVG AVERAGE --- --- --- ---
Subroutines --- SBS SUBROU- MCRO MACRO SBN SUBROU-
instructions TINE CALL TINE ENTRY
RET SUBROU- GSBS* GLOBAL GSBN* GLOBAL
TINE SUBROU- SUBROU-
RETURN TINE CALL TINE ENTRY
GRET* GLOBAL --- --- --- ---
SUBROU-
TINE
RETURN
Interrupt --- MSKS*** SET MSKR*** READ INTER- CLI*** CLEAR
control INTERRUPT RUPT MASK INTERRUPT
instructions MASK
DI DISABLE EI ENABLE --- ---
INTERRUPTS INTERRUPTS
High-speed --- INI MODE CON- PRV HIGH-SPEED PRV2 COUNTER
counter/ TROL COUNTER PV (See note 2.) FREQUENCY
pulse out- READ CONVERT
put instruc- CTBL COMPARI- SPED SPEED OUT- PULS SET PULSES
tions** SON TABLE PUT
LOAD

PLS2 PULSE OUT- ACC ACCELERA- ORG ORIGIN

PUT TION Control SEARCH
Step --- PWM PULSE WITH STEP STEP DEFINE SNXT STEP START
instructions VARIABLE
DUTY FAC-
TOR
Basic I/O --- IORF I/O REFRESH FIORF SPECIAL I/O DLNK* CPU BUS
Unit instruc- (See note 2.) UNIT I/O UNIT I/O
tions REFRESH REFRESH
SDEC 7-SEGMENT DSW DIGITAL TKY TEN KEY
DECODER (See note 1.) SWITCH (See note 1.) INPUT
INPUT
HKY HEXADECI- MTR MATRIX 7SEG 7-SEGMENT
(See note 1.) MAL KEY (See note 1.) INPUT (See note 1.) DISPLAY
INPUT OUTPUT
IORD INTELLI- IOWR INTELLI- DLNK* CPU BUS
GENT I/O GENT I/O UNIT I/O
READ WRITE REFRESH

22
Instruction Classifications by Function Section 2-1

Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction

tion
Serial com- --- PMCR PROTOCOL TXD TRANSMIT RXD RECEIVE
munica- MACRO
tions
instructions STUP CHANGE --- --- --- ---
SERIAL PORT
SETUP
Network --- SEND NETWORK RECV NETWORK CMND DELIVER
instructions SEND RECEIVE COMMAND
EXPLT SEND GEN- EGATR EXPLICIT ESATR EXPLICIT
(See note 1.) ERAL (See note 1.) GET (See note 1.) SET
EXPICIT ATTRIBUTE ATTRIBUTE
ECHRD EXPLICIT ECHWR EXPLICIT --- ---
(See note 1.) WORD READ (See note 1.) WORD
WRITE
Display --- MSG DISPLAY --- --- --- ---
instructions MESSAGE
File mem- --- FREAD READ DATA FWRIT WRITE DATA TWRIT WRITE TEXT
ory instruc- FILE FILE FILE
tions
Clock --- CADD CALENDAR CSUB CALENDAR SEC HOURS TO
instructions ADD SUBTRACT SECONDS
HMS SECONDS TO DATE CLOCK --- ---
HOURS ADJUST-
MENT
Debugging --- TRSM TRACE --- --- --- ---
instructions MEMORY
SAMPLING
Failure --- FAL FAILURE FALS SEVERE FPD FAILURE
diagnosis ALARM FAILURE POINT
instructions ALARM DETECTION
Other --- STC SET CARRY CLC CLEAR EMBC SELECT EM
instructions CARRY BANK
WDT EXTEND CCS* SAVE CONDI- CCL* LOAD CONDI-
MAXIMUM TION FLAGS TION FLAGS
CYCLE TIME
FRMCV* CONVERT TOCV* CONVERT IOSP*** DISABLE
ADDRESS ADDRESS TO PERIPH-
FROM CV CV ERAL SER-
VICING
IORS*** ENABLE --- --- --- ---
PERIPH-
ERAL SER-
VICING

23
Instruction Classifications by Function Section 2-1

Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction

tion
Block Define block pro- BPRG BLOCK PRO- BEND BLOCK PRO- --- ---
program- gram area GRAM BEGIN GRAM END
ming
instructions Block BPPS BLOCK BPRS BLOCK --- ---
program start/stop PROGRAM PROGRAM
PAUSE RESTART
EXIT EXIT Conditional EXIT NOT Conditional input_condition Conditional
bit_address END bit_address END NOT EXIT END
IF branch IF CONDI- IF NOT CONDI- ELSE CONDI-
processing bit_address TIONAL bit_address TIONAL TIONAL
BLOCK BLOCK BLOCK
BRANCHING BRANCHING BRANCHING
(NOT) (ELSE)
IEND CONDI- --- --- --- ---
TIONAL
BLOCK
BRANCHING
END
WAIT WAIT ONE CYCLE WAIT NOT ONE CYCLE input_condition ONE CYCLE
bit_address AND WAIT bit_address AND WAIT WAIT AND WAIT
NOT
Timer/ BCD TIMW HUNDRED- CNTW COUNTER TMHW TEN-MS
counter MS TIMER WAIT TIMER WAIT
WAIT
Binary* TIMWX HUNDRED- CNTWX COUNTER TMHWX TEN-MS
MS TIMER WAIT TIMER WAIT
WAIT
Repeat LOOP LOOP BLOCK LEND LOOP BLOCK LEND NOT LOOP BLOCK
bit_address END bit_address END NOT
input_ LOOP BLOCK --- --- --- ---
condition END
LEND
Text string --- MOV$ MOV STRING +$ CONCATE- LEFT$ GET STRING
processing NATE LEFT
instructions STRING
RIGHT$ GET STRING MID$ GET STRING FIND$ FIND IN
RIGHT MIDDLE STRING
LEN$ STRING RPLC$ REPLACE IN DEL$ DELETE
LENGTH STRING STRING
XCHG$ EXCHANGE CLR$ CLEAR INS$ INSERT INTO
STRING STRING STRING
LD, AND, OR STRING --- --- --- ---
+ COMPARI-
=$, <>$, <$, SON
<=$, >$, >=$
Task control --- TKON TASK ON TKOF TASK OFF --- ---
instructions

24
Instruction Functions Section 2-2

2-2 Instruction Functions

2-2-1 Sequence Input Instructions
*1
: Not supported by CS1D CPU Units for Duplex-CPU Systems.
*2
: Supported by CS1-H, CJ1-H, CJ1M, and CS1D CPU Units only.
*3
: Supported by CS1-H, CJ1-H, and CJ1M CPU Units only.
Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
LOAD Bus bar Indicates a logical start and creates an ON/OFF execution condition Start of logic 161
LD based on the ON/OFF status of the specified operand bit. Not required
@LD
%LD
!LD*1
!@LD*1 Starting
!%LD*1 point of
block

LOAD NOT Indicates a logical start and creates an ON/OFF execution condition Start of logic 163
Bus bar based on the reverse of the ON/OFF status of the specified operand
LD NOT Not required
bit.
@LD NOT*2
%LD NOT*2
!LD NOT*1
!@LD NOT*3 Starting
!%LD NOT*3 point of
block

AND Takes a logical AND of the status of the specified operand bit and the Continues on 165
AND current execution condition. rung
@AND Required
%AND
!AND*1
!@AND*1
!%AND*1
AND NOT Reverses the status of the specified operand bit and takes a logical Continues on 167
AND NOT AND with the current execution condition. rung
@AND NOT*2 Required
%AND NOT*2
!AND NOT*1
!@AND NOT*3
!%AND NOT*3
OR Bus bar Takes a logical OR of the ON/OFF status of the specified operand bit Continues on 169
OR and the current execution condition. rung
@OR Required
%OR
!OR*1
!@OR*1
!%OR*1
OR NOT Bus bar Reverses the status of the specified bit and takes a logical OR with the Continues on 171
OR NOT current execution condition rung
@OR NOT*2 Required
%OR NOT*2
!OR NOT*1
!@OR NOT*3
!%OR NOT*3

25
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
AND LOAD Logic block Logic block Takes a logical AND between logic blocks. Continues on 172
AND LD rung
LD Required
Logic block A
to

LD
Logic block B
to

AND LD Serial connection between logic block A and

logic block B.

OR LOAD Takes a logical OR between logic blocks. Continues on 174

OR LD Logic block rung
LD Required
Logic block Logic block A
to

LD
Logic block B
to

OR LD Parallel connection between logic block A

and logic block B.

NOT --- Reverses the execution condition. Continues on 180

NOT rung
520 Required
CONDITION ON UP(521) turns ON the execution condition for one cycle when the exe- Continues on 181
UP UP(521) cution condition goes from OFF to ON. rung
521 Required
CONDITION OFF DOWN(522) turns ON the execution condition for one cycle when the Continues on 181
DOWN(522) execution condition goes from ON to OFF. rung
DOWN
522 Required
BIT TEST LD TST(350), AND TST(350), and OR TST(350) are used in the pro- Continues on 182
TST(350) gram like LD, AND, and OR; the execution condition is ON when the rung
LD TST
specified bit in the specified word is ON and OFF when the bit is OFF. Not required
350 S
N
S: Source word
N: Bit number

BIT TEST LD TSTN(351), AND TSTN(351), and OR TSTN(351) are used in the Continues on 182
LD TSTN TSTN(351) program like LD NOT, AND NOT, and OR NOT; the execution condition rung
351 is OFF when the specified bit in the specified word is ON and ON when Not required
S the bit is OFF.
N
S: Source word
N: Bit number
BIT TEST LD TST(350), AND TST(350), and OR TST(350) are used in the pro- Continues on 182
AND TST AND TST(350) gram like LD, AND, and OR; the execution condition is ON when the rung
specified bit in the specified word is ON and OFF when the bit is OFF. Required
350 S
N
S: Source word
N: Bit number
BIT TEST LD TSTN(351), AND TSTN(351), and OR TSTN(351) are used in the Continues on 182
AND TSTN AND TSTN(351) program like LD NOT, AND NOT, and OR NOT; the execution condition rung
is OFF when the specified bit in the specified word is ON and ON when Required
351 S the bit is OFF.
N
S: Source word
N: Bit number

26
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
BIT TEST LD TST(350), AND TST(350), and OR TST(350) are used in the pro- Continues on 182
OR TST TST(350) gram like LD, AND, and OR; the execution condition is ON when the rung
specified bit in the specified word is ON and OFF when the bit is OFF. Required
350 S
N
S: Source word
N: Bit number
BIT TEST LD TSTN(351), AND TSTN(351), and OR TSTN(351) are used in the Continues on 182
OR TSTN TSTN(351) program like LD NOT, AND NOT, and OR NOT; the execution condition rung
is OFF when the specified bit in the specified word is ON and ON when Required
351 S the bit is OFF.
N
S: Source word
N: Bit number

2-2-2 Sequence Output Instructions

*1
: Not supported by CS1D CPU Units for Duplex-CPU Systems.
Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
OUTPUT Outputs the result (execution condition) of the logical processing to the Output 185
OUT specified bit. Required
!OUT*1

OUTPUT NOT Reverses the result (execution condition) of the logical processing, and Output 187
OUT NOT outputs it to the specified bit. Required
!OUT NOT*1

KEEP Operates as a latching relay. Output 188

S (Set) KEEP(011)
KEEP Required
B Set
!KEEP*1
R (Reset)
011
B: Bit
Reset

S execution
condition

R execution
condition

Status of B
DIFFERENTIATE DIFU(013) turns the designated bit ON for one cycle when the Output 193
UP DIFU(013) execution condition goes from OFF to ON (rising edge). Required
DIFU B
!DIFU*1
B: Bit Execution condition
013

Status of B

One cycle

27
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DIFFERENTIATE DIFD(014) turns the designated bit ON for one cycle when the Output 193
DOWN DIFD(014) Required
execution condition goes from ON to OFF (falling edge).
DIFD B
!DIFD*1
Execution condition
B: Bit
014

Status of B
One cycle
SET SET turns the operand bit ON when the execution condition is ON. Output 195
SET SET Required
@SET B Execution condition
%SET of SET
!SET*1 B: Bit
!@SET*1
!%SET*1 Status of B

RESET RSET turns the operand bit OFF when the execution condition is ON. Output 195
RSET RSET Required
@RSET Execution condition
%RSET B
of RSET
!RSET*1 B: Bit
!@RSET*1
Status of B
!%RSET*1
MULTIPLE BIT SETA(530) turns ON the specified number of consecutive bits. Output 198
SET SETA(530) Required
SETA D
@SETA
530 N1 N2 bits are set to 1
(ON).
N2
D: Beginning
word
N1: Beginning bit
N2: Number of
bits

MULTIPLE BIT RSTA(531) turns OFF the specified number of consecutive bits. Output 198
RESET RSTA(531) Required
RSTA
@RSTA D
531 N1 N2 bits are reset to
0 (OFF).
N2
D: Beginning
word
N1: Beginning bit
N2: Number of
bits
SINGLE BIT SET SETB(532) turns ON the specified bit in the specified word when the exe- Output 201
(CS1-H, CJ1-H, SETB(532) cution condition is ON. Required
CJ1M, or CS1D Unlike the SET instruction, SETB(532) can be used to set a bit in a DM or
only) D EM word.
SETB N
@SETB
*1 D: Word address
!SETB
!@SETB*1 N: Bit number

28
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
SINGLE BIT RSTB(533) turns OFF the specified bit in the specified word when the Output 201
RESET (CS1-H, RSTB(533) execution condition is ON. Required
CJ1-H, CJ1M, or Unlike the RSET instruction, RSTB(533) can be used to reset a bit in a
CS1D only) D DM or EM word.
RSTB N
@RSTB
*1
!RSTB D: Word address
!@RSTB*1 N: Bit number

SINGLE BIT OUTB(534) outputs the result (execution condition) of the logical pro- Output 204
OUTPUT (CS1-H, OUTB(534) cessing to the specified bit. Required
CJ1-H, CJ1M, or Unlike the OUT instruction, OUTB(534) can be used to control a bit in a
CS1D only) D DM or EM word.
OUTB N
@OUTB
!OUTB *1
D: Word address
N: Bit number

29
Instruction Functions Section 2-2

2-2-3 Sequence Control Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
END Indicates the end of a program. Output 206
END END(001) Not required
END(001) completes the execution of a program for that cycle. No
001 instructions written after END(001) will be executed. Execution
proceeds to the program with the next task number. When the
program being executed has the highest task number in the program,
END(001) marks the end of the overall main program.

Task 1 Program A

To the next task number

Task 2 Program B

To the next task number

Task n Program Z

End of the main program

I/O refreshing

NO OPERATION This instruction has no function. (No processing is performed for Output 207
NOP NOP(000).) Not required
000
INTERLOCK Interlocks all outputs between IL(002) and ILC(003) when the Output 210
IL IL(002) execution condition for IL(002) is OFF. IL(002) and ILC(003) are Required
002 normally used in pairs.
Execution Execution
Execution condition ON condition OFF
condition

Interlocked section Normal Outputs

of the program execution interlocked.

30
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
INTERLOCK All outputs between IL(002) and ILC(003) are interlocked when the Output 210
CLEAR ILC(003) execution condition for IL(002) is OFF. IL(002) and ILC(003) are nor- Not required
ILC mally used in pairs.
003
MULTI-INTER- When the execution condition for MILH(517) is OFF, the outputs for all Output 214
LOCK DIFFER- MILH (517) instructions between that MILH(517) instruction and the next Required
ENTIATION MILC(519) instruction are interlocked. MILH(517) and MILC(519) are
HOLD N used as a pair.
MILH D MILH(517)/MILC(519) interlocks can be nested (e.g., MILH(517)—
517 MILH(517)—MILC(519)—MILC(519)).
CS/CJ-series CPU N: Interlock number If there is a differentiated instruction (DIFU, DIFD, or instruction with a
Unit Ver. 2.0 or later D: Interlock Status Bit @ or% prefix) between MILH(517) and the corresponding MILC(519),
only that instruction will be executed after the interlock is cleared if the dif-
ferentiation condition of the instruction was established while it was
interlocked.
MULTI-INTER- When the execution condition for MILR(518) is OFF, the outputs for all Output 214
LOCK DIFFER- MILR (518) instructions between that MILR(518) instruction and the next Required
ENTIATION MILC(519) instruction are interlocked.MILR(518) and MILC(519) are
RELEASE N used as a pair.
MILR D MILR(518)/MILC(519) interlocks can be nested (e.g., MILR(518)—
518 MILR(518)—MILC(519)—MILC(519)).
CS/CJ-series CPU N: Interlock number If there is a differentiated instruction (DIFU, DIFD, or instruction with a
Unit Ver. 2.0 or later D: Interlock Status Bit @ or % prefix) between MILR(518) and the corresponding MILC(519),
only that instruction will not be executed after the interlock is cleared even if
the differentiation condition of the instruction was established.
MULTI-INTER- Clears an interlock started by an MILH(517) or MILR(518) with the Output 214
LOCK CLEAR MILC (519) same interlock number. Not required
MILC N All outputs between MILH(517)/MILR(518) and the corresponding
519 MILC(519) with the same interlock number are interlocked when the
N: Interlock number execution condition for MILH(517)/MILR(518) is OFF.
CS/CJ-series CPU
Unit Ver. 2.0 or later
only
JUMP When the execution condition for JMP(004) is OFF, program Output 228
JMP JMP(004) execution jumps directly to the first JME(005) in the program with Required
004 N the same jump number. JMP(004) and JME(005) are used in pairs.

N: Jump number Execution condition

Instructions
jumped
Instructions in this section
are not executed and out-
put status is maintained.
Instructions The instruction execution
executed time for these instructions
is eliminated.

CONDITIONAL The operation of CJP(510) is the basically the opposite of JMP(004). Output 232
JUMP CJP(510) When the execution condition for CJP(510) is ON, program execution Required
CJP jumps directly to the first JME(005) in the program with the same jump
N
510 number. CJP(510) and JME(005) are used in pairs.
N: Jump number
Execution Execution
condition OFF condition ON
Instructions
jumped

Instructions in this section

Instructions are not executed and out-
put status is maintained.
executed The instruction execution
time for these instructions
is eliminated.

31
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
JUMP END Indicates the end of a jump initiated by JMP(004) or CJP(510). Output 228
JME JME(005) Not required
005 N
N: Jump number

CONDITIONAL The operation of CJPN(511) is almost identical to JMP(004). Output 232

JUMP CJPN(511) When the execution condition for CJP(004) is OFF, program execution Not required
CJPN jumps directly to the first JME(005) in the program with the same jump
N
511 number. CJPN(511) and JME(005) are used in pairs.
N: Jump number
Execution Execution
condition ON condition OFF
Instructions
jumped

Instructions in this section

are not executed and out-
Instructions put status is maintained.
executed The instruction execution
time for these instructions
is eliminated.

MULTIPLE JUMP When the execution condition for JMP0(515) is OFF, all instructions Output 236
JMP0 JMP0(515) from JMP0(515) to the next JME0(516) in the program are processed Required
515 as NOP(000). Use JMP0(515) and JME0(516) in pairs. There is no
limit on the number of pairs that can be used in the program.

Execution Execution
condition a ON condition a OFF
Instructions
jumped
Instructions
executed

Jumped instructions
are processed as
Execution Execution NOP(000). Instruction
condition b ON condition b OFF execution times are
the same as
NOP(000).

Instructions
executed

Instructions
jumped

MULTIPLE JUMP When the execution condition for JMP0(515) is OFF, all instructions Output 236
END JME0(516) from JMP0(515) to the next JME0(516) in the program are processed Not required
JME0 as NOP(000). Use JMP0(515) and JME0(516) in pairs. There is no
limit on the number of pairs that can be used in the program.
516

32
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
FOR-NEXT The instructions between FOR(512) and NEXT(513) are repeated a Output 238
LOOPS FOR(512) specified number of times. FOR(512) and NEXT(513) are used in Not required
FOR pairs.
N
512
N: Number of Repeated N times
loops

Repeated program section

BREAK LOOP Programmed in a FOR-NEXT loop to cancel the execution of the loop Output 241
BREAK BREAK(514) for a given execution condition. The remaining instructions in the loop Required
514 are processed as NOP(000) instructions.
Condition a ON
N repetitions

Repetitions
forced to end.

Processed as
NOP(000).

FOR-NEXT The instructions between FOR(512) and NEXT(513) are repeated a Output 238
LOOPS NEXT(513) specified number of times. FOR(512) and NEXT(513) are used in Not required
NEXT pairs.
513

33
Instruction Functions Section 2-2

2-2-4 Timer and Counter Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
HUNDRED-MS TIM/TIMX(550) operates a decrementing timer with units of 0.1-s. Output 245
TIMER TIM Required
The setting range for the set value (SV) is 0 to 999.9 s for BCD
TIM
(BCD) N and 0 to 6,553.5 s for binary (decimal or hexadecimal).
S Timer input
TIMX
(Binary) N: Timer number
(CS1-H, CJ1-H, S: Set value Timer PV SV
CJ1M, or CS1D
only)
TIMX(550) Completion
N Flag
S
Timer input
N: Timer number
S: Set value
Timer PV SV

Completion
Flag

TEN-MS TIMER TIMH(015)/TIMHX(551) operates a decrementing timer with units of Output 249
TIMH TIMH(015) 10-ms. The setting range for the set value (SV) is 0 to 99.99 s for BCD Required
and 0 to 655.35 s for binary (decimal or hexadecimal).
015 N
(BCD)
S Timer input
TIMHX
N: Timer number
551 SV
(Binary) S: Set value Timer PV
(CS1-H, CJ1-H,
CJ1M, or CS1D
only) TIMHX(551)
Completion
N Flag
S
Timer input
N: Timer number
S: Set value
Timer PV SV

Completion
Flag

ONE-MS TIMER TMHH(540)/TMHHX(552) operates a decrementing timer with units of Output 253
TMHH TMHH(540) 1-ms. The setting range for the set value (SV) is 0 to 9.999 s for BCD Required
and 0 to 65.535 s for binary (decimal or hexadecimal).
540 N
(BCD)
S Timer input
TMHHX
N: Timer number SV
552 Timer PV
(BCD) S: Set value
(CS1-H, CJ1-H,
CJ1M, or CS1D
only) TMHHX(552)
Completion
N Flag
S
Timer input
N: Timer number
S: Set value SV
Timer PV

Completion
Flag

34
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
TENTH-MS TIMU(541)/TIMUX(556) operates an decrementing timer with units of Output 256
TIMU(541)
TIMER (CJ1-H-R 0.1-s. The setting range for the set value (SV) is 0 to 0.999 s for BCD Required
only) N and 0 to 6,553.5 s for binary (decimal or hexadecimal).
TIMU S ON
541 Timer input OFF
(BCD) N: Timer number
S: Set value SV
Timer PV 0
TIMUX
TIMUX(556)
556
(BCD) N Completion ON
S Flag OFF

N: Timer number
S: Set value
Timer Input Turns OFF before Completion Flag Turns ON

ON
Timer input OFF
SV
Timer PV 0

Completion ON
Flag OFF
Note: The timer’s present value cannot be accessed for a TENTH-MS
TIMER instruction.
HUNDREDTH-MS TMUH(554)/TMUHX(557) operates an decrementing timer with units of Output 259
TMUH(554)
TIMER (CJ1-H-R 0.01-s. The setting range for the set value (SV) is 0 to 0.0999 s for BCD Required
only) N and 0 to 0.65535 s for binary (decimal or hexadecimal).
TMUH S ON
554 Timer input OFF
N: Timer number
(BCD) S: Set value
SV
Timer PV 0
TMUHX
TMUHX(557)
557
N Completion ON
(BCD)
S Flag OFF

N: Timer number
S: Set value
Timer Input Turns OFF before Completion Flag Turns ON

ON
Timer input OFF

SV
Timer PV
0

Completion ON
Flag OFF
Note: The timer’s present value cannot be accessed for a HUN-
DREDTH-MS TIMER instruction.

35
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
ACCUMULATIVE Timer TTIM(087)/TTIMX(555) operates an incrementing timer with units of Output 262
TIMER input TTIM(087)
0.1-s. The setting range for the set value (SV) is 0 to 999.9 s for Required
TTIM N BCD and 0 to 6,553.5 s for binary (decimal or hexadecimal).
087 S
(BCD) Timer input
Reset
input
TTIMX
Timer PV SV
555 N: Timer number
(Binary) S: Set value
(CS1-H, CJ1-H, Timing resumes.
CJ1M, or CS1D
only) Timer TTIMX(555) PV maintained.
input
N
S Completion
Reset Flag
input
Reset input
N: Timer number
S: Set value

LONG TIMER TIML(542)/TIMLX(553) operates a decrementing timer with units of Output 266
TIML TIML(542) Required
0.1-s that can time up to approx. 115 days for BCD and 49,710 days
542 D1 for binary (decimal or hexadecimal).
(BCD)
D2 Timer input
TIMLX S SV
553 Timer PV
(Binary) D1: Completion
(CS1-H, CJ1-H, Flag
CJ1M, or CS1D D2: PV word
only) S: SV word
Completion Flag
(Bit 00 of D1)
TIMLX(553)

D1
D2
S

D1: Completion
Flag
D2: PV word
S: SV word

36
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
MULTI-OUTPUT MTIM(543)/MTIMX(554) operates a 0.1-s incrementing timer with 8 Output 269
TIMER MTIM(543) Required
independent SVs and Completion Flags. The setting range for the
MTIM D1 set value (SV) is 0 to 999.9 s for BCD and 0 to 6,553.5 s for binary
543 (decimal or hexadecimal).
(BCD) D2 Timer PV
S
MTIMX
554 D1: Completion
(Binary) Timer SVs 0
(CS1-H, CJ1-H, Flags
CJ1M, or CS1D D2: PV word
only) S: 1st SV word
to
to
MTIMX(554)

D1
D2 Timer input
S
SV 7
D1: Completion to
Flags SV 2
D2: PV word
S: 1st SV word Timer PV (D2) SV 1
SV 0
0

Completion Bit 7
Flags (D1) to
Bit 2

Bit 1

Bit 0

COUNTER Count CNT/CNTX(546) operates a decrementing counter. The setting range Output 275
CNT input CNT Required
for the set value (SV) is 0 to 9,999 for BCD and 0 to 65,535 for binary
(BCD) N (decimal or hexadecimal).
S
CNTX Count input
Reset
546 input
(Binary) Reset input
(CS1-H, CJ1-H, N: Counter
CJ1M, or CS1D number
only) S: Set value SV
Counter PV
Count CNTX(546)
input
N
S Completion
Flag
Reset
input
N: Counter
number
S: Set value

37
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
REVERSIBLE Incre- Output 278
CNTR(012) CNTR(012)/CNTRX(548) operates a reversible counter.
COUNTER ment Required
CNTR input N
012 Decre- S
ment Increment input
(BCD)
input

CNTRX Reset
input Decrement input
548
(Binary)
(CS1-H, CJ1-H, N: Counter
CJ1M, or CS1D number
S: Set value
only) Counter PV
Incre-
ment CNTRX(548)
input SV
N Counter PV
Decre-
ment S
input +1
Reset
input
Completion Flag
N: Counter
number
S: Set value
SV 1
Counter PV

Completion Flag

RESET TIMER/ CNR(545)/CNRX(547) resets the timers or counters within the speci- Output 282
COUNTER CNR(545) fied range of timer or counter numbers. Sets the set value (SV) to the Required
CNR maximum of 9999.
N1
@CNR
545 N2
(BCD)
N1: 1st number in
range
CNRX
@CNRX N2: Last number
in range
547
(Binary)
(CS1-H, CJ1-H,
CJ1M, or CS1D CNRX(547)
only)
N1
N2

N1: 1st number

in range
N2: Last number
in range

38
Instruction Functions Section 2-2

2-2-5 Comparison Instructions

*1
: Not supported by CS1D CPU Units for Duplex-CPU Systems.
Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
Symbol Compari- Symbol comparison instructions (unsigned) compare two values LD: Not 291
son (Unsigned) Symbol & options required
(constants and/or the contents of specified words) in 16-bit binary
LD, AND, OR + =, data and create an ON execution condition when the comparison AND, OR:
S1 condition is true. There are three types of symbol comparison Required
<>, <, <=, >, >=
300 (=) S2 instructions, LD (LOAD), AND, and OR.
305 (<>)
310 (<) LD ON execution condition when
S1: Comparison
315 (<=) comparison result is true.
data 1
320 (>) S2: Comparison <
325(>=) data 2

ON execution condition
AND when comparison result
is true.
<

OR

<

ON execution condition when

comparison result is true.

Symbol Compari- S1: Comparison Symbol comparison instructions (double-word, unsigned) compare two LD: Not 291
son (Double- data 1 values (constants and/or the contents of specified double-word data) in required
word, unsigned) S2: Comparison unsigned 32-bit binary data and create an ON execution condition when AND, OR:
LD, AND, OR + =, the comparison condition is true. There are three types of symbol com- Required
data 2 parison instructions, LD (LOAD), AND, and OR.
<>, <, <=, >, >= +
L
301 (=)
306 (<>)
311 (<)
316 (<=)
321 (>)
326 (>=)
Symbol Compari- S1: Comparison Symbol comparison instructions (signed) compare two values (con- LD: Not 291
son (Signed) data 1 stants and/or the contents of specified words) in signed 16-bit binary (4- required
LD, AND, OR + =, S2: Comparison digit hexadecimal) and create an ON execution condition when the com- AND, OR:
<>, <, <=, >, >= parison condition is true. There are three types of symbol comparison Required
data 2 instructions, LD (LOAD), AND, and OR.
+S
302 (=)
307 (<>)
312 (<)
317 (<=)
322 (>)
327 (>=)

39
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
Symbol Compari- S1: Comparison Symbol comparison instructions (double-word, signed) compare two LD: Not 291
son (Double- data 1 values (constants and/or the contents of specified double-word data) in required
word, signed) S2: Comparison signed 32-bit binary (8-digit hexadecimal) and create an ON execution AND, OR:
LD, AND, OR + =, condition when the comparison condition is true. There are three types Required
data 2 of symbol comparison instructions, LD (LOAD), AND, and OR.
<>, <, <=, >, >=
+SL
303 (=)
308 (<>)
313 (<)
318 (<=)
323 (>)
328 (>=)
Time Compari- LD (LOAD): Time comparison instructions compare two BCD time values and create LD: Not 297
son an ON execution condition when the comparison condition is true. required
LD, AND, OR + = Symbol There are three types of time comparison instructions, LD (LOAD), AND, OR:
DT, <> DT, < DT, AND, and OR. Time values (year, month, day, hour, minute, and second) Required
<= DT, > DT, >= C can be masked/unmasked in the comparison so it is easy to create cal-
DT endar timer functions.
S1
341 (= DT)
342 (<> DT) S2
343 (< DT)
344 (<= DT)
345 (> DT) AND:
346 (>= DT)
(CS/CJ-series Symbol
CPU Unit Ver. 2.0 C
or later only)
S1
S2

OR:
Symbol
C
S1
S2

C: Control word
S1: 1st word of
present time
S2: 1st word of
comparison
time

UNSIGNED COM- Compares two unsigned binary values (constants and/or the contents Output 303
PARE CMP(020)
of specified words) and outputs the result to the Arithmetic Flags in Required
CMP S1 the Auxiliary Area.
!CMP*1
S2 Unsigned binary
020 comparison
S1: Comparison
data 1
S2: Comparison Arithmetic Flags
data 2 (>, >=, =, <=, <, <>)

DOUBLE Compares two double unsigned binary values (constants and/or the Output 306
UNSIGNED CMPL(060) contents of specified words) and outputs the result to the Arithmetic Required
COMPARE Flags in the Auxiliary Area.
S1
CMPL
Unsigned binary
060 S2 comparison

S1: Comparison S1+1 S2+1

data 1
S2: Comparison Arithmetic Flags
data 2 (>, >=, =, <=, <, <>)

40
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
SIGNED BINARY Compares two signed binary values (constants and/or the contents of Output 309
COMPARE CPS(114) specified words) and outputs the result to the Arithmetic Flags in the Required
CPS Auxiliary Area.
S1
!CPS*1 Signed binary
114 S2 comparison
S1: Comparison
data 1
S2: Comparison Arithmetic Flags
data 2 (>, >=, =, <=, <, <>)

DOUBLE Compares two double signed binary values (constants and/or the Output 312
SIGNED BINARY CPSL(115)
contents of specified words) and outputs the result to the Arithmetic Required
COMPARE Flags in the Auxiliary Area.
S1
CPSL
115 S2 Signed binary
comparison
S1: Comparison S1+1 S2+1
data 1
S2: Comparison
data 2 Arithmetic Flags
(>, >=, =, <=, <, <>)

MULTIPLE COM- Compares 16 consecutive words with another 16 consecutive words Output 315
PARE MCMP(019) and turns ON the corresponding bit in the result word where the Required
MCMP contents of the words are not equal.
@MCMP S1
Comparison R
019 S2
0: Words
R are equal.
1: Words
S1: 1st word of aren't
set 1 equal.
S2: 1st word of
set 2
R: Result word

TABLE COM- Compares the source data to the contents of 16 words and turns Output 317
PARE TCMP(085) Required
ON the corresponding bit in the result word when the contents are
TCMP S
@TCMP equal.
Comparison R
085 T 1: Data are
equal.
R
0: Data aren't
equal.
S: Source data
T: 1st word of
table
R: Result word

UNSIGNED Compares the source data to 16 ranges (defined by 16 lower limits Output 320
BLOCK COM- BCMP(068) and 16 upper limits) and turns ON the corresponding bit in the result Required
PARE word when the source data is within the range.
S
BCMP
@BCMP T Ranges
1: In range
068 0: Not in range
R
Lower limit Upper limit R
S: Source data T to T+1 0
T: 1st word of
table T+2 to T+3 1
Source data
R: Result word
S

T+28 to T+29 14
T+30 to T+31 15

41
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
EXPANDED Compares the source data to up to 256 ranges (defined by upper and Output 322
BLOCK COM- BCMP2(502)
lower limits) and turns ON the corresponding bit in the result word when Required
PARE
S the source data is within a range.
BCMP2
@BCMP2 T 1: In range
502 T N n=255 max. 0: Not in range

(CS1-H, CJ1-H, or R D Bit

CS1D CPU Unit T+1 Range 0 A Range 0 B T+2 0
S: Source data
Ver. 2.0 or later T: 1st word of T+3 Range 1 A Range 1 B T+4 1
only) Source data
block
CJ1M CPU Unit R: Result word S
(Pre-Ver. 2.0 or
Unit Ver. 2.0 or D+15 max.
later) T+2N+1 Range N A Range N B T+2N+2

Note: A can be less than

or equal to B or
greater the B.

AREA RANGE Compares the 16-bit unsigned binary value in CD (word contents or Output 326
COMPARE ZCP(088) constant) to the range defined by LL and UL and outputs the results to Required
ZCP the Arithmetic Flags in the Auxiliary Area.
CD
@ZCP
088 LL
(CS1-H, CJ1-H,
CJ1M, or CS1D UL
only)
CD: Compare
data (1 word)
LL: Lower limit of
range
UL: Upper limit of
range

DOUBLE AREA Compares the 32-bit unsigned binary value in CD and CD+1 (word con- Output 329
RANGE COM- ZCPL(116) tents or constant) to the range defined by LL and UL and outputs the Required
PARE results to the Arithmetic Flags in the Auxiliary Area.
CD
ZCPL
@ZCPL LL
116
(CS1-H, CJ1-H, UL
CJ1M, or CS1D
only) CD: Compare
data (2 words)
LL: Lower limit of
range
UL: Upper limit of
range

42
Instruction Functions Section 2-2

2-2-6 Data Movement Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
MOVE Output 331
MOV(021) Transfers a word of data to the specified word.
MOV Required
@MOV S Source word
!MOV
!@MOV D
021
S: Source
D: Destination Bit status not
changed.

Destination word

DOUBLE MOVE Transfers two words of data to the specified words. Output 334
MOVL(498)
MOVL S S+1 Required
@MOVL S
498
D
Bit status not
S: 1st source
word changed.
D: 1st destination D D+1
word

MOVE NOT Transfers the complement of a word of data to the specified word. Output 333
MVN MVN(022) Required
@MVN Source word
S
022
D
S: Source
D: Destination Bit status
inverted.

Destination word

DOUBLE MOVE Output 336

NOT MVNL(499) Transfers the complement of two words of data to the specified words.
S S+1
Required
MVNL S
@MVNL
499 D
Bit status
S: 1st source inverted.
word
D: 1st destination D D+1
word

MOVE BIT Transfers the specified bit. Output 337

MOVB MOVB(082) Required
@MOVB
S
082
C
D
S: Source word or
data
C: Control word
D: Destination
word

43
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
MOVE DIGIT Transfers the specified digit or digits. (Each digit is made up of 4 bits.) Output 339
MOVD MOVD(083) Required
@MOVD S
083
C
D
S: Source word or
data
C: Control word
D: Destination
word

MULTIPLE BIT Transfers the specified number of consecutive bits. Output 342
TRANSFER XFRB(062) Required
XFRB C
@XFRB
062 S
D
C: Control word
S: 1st source
word
D: 1st destination
word

BLOCK Output 344

TRANSFER XFER(070) Transfers the specified number of consecutive words.
Required
XFER N
@XFER
070 S N words
to to
D D+(N−1)
S+(N−1)
N: Number of
words
S: 1st source
word
D: 1st destination
word
BLOCK SET Copies the same word to a range of consecutive words. Output 347
BSET BSET(071) Required
@BSET S Source word Destination words
071
St St

S: Source word
St: Starting word
E: End word
E

DATA Output 349

XCHG(073) Exchanges the contents of the two specified words.
EXCHANGE Required
XCHG E1 E1 E2
@XCHG
073 E2
E1: 1st exchange
word
E2: Second
exchange word

44
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DOUBLE DATA Exchanges the contents of a pair of consecutive words with another Output 350
EXCHANGE XCGL(562) Required
pair of consecutive words.
XCGL E1
@XCGL E1 E1+1 E2 E2+1
562 E2
E1: 1st exchange
word
E2: Second
exchange word

SINGLE WORD Transfers the source word to a destination word calculated by adding Output 352
DISTRIBUTE DIST(080) an offset value to the base address. Required
DIST S
@DIST S Bs Of
080 Bs
Of

S: Source word
Bs: Destination
base address
Of: Offset Bs+n

DATA COLLECT Transfers the source word (calculated by adding an offset value to the Output 354
COLL COLL(081) base address) to the destination word. Required
@COLL Bs
081 Bs Of
Of
D

Bs: Source base Bs+n

address
Of: Offset
D: Destination
word

MOVE TO REGIS- Sets the internal I/O memory address of the specified word, bit, or Output 356
TER MOVR(560)
timer/counter Completion Flag in the specified Index Register. (Use Required
MOVR S MOVRW(561) to set the internal I/O memory address of a
@MOVR timer/counter PV in an Index Register.)
560 D
I/O memory address of S
S: Source
(desired word or
bit)
D: Destination
(Index Register)

Index Register

MOVE TIMER/ Sets the internal I/O memory address of the specified timer or Output 358
COUNTER PV TO MOVRW(561) counter's PV in the specified Index Register. (Use MOVR(560) to set Required
REGISTER the internal I/O memory address of a word, bit, or timer/counter
S
MOVRW Completion Flag in an Index Register.)
@MOVRW D
561 I/O memory address of S
S: Source
(desired TC
number)
D: Destination Timer/counter PV only
(Index Register)

Index Register

45
Instruction Functions Section 2-2

2-2-7 Data Shift Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
SHIFT REGISTER Data Operates a shift register. Output 361
SFT input SFT(010)
E St+1, St+2 St Required
010 Shift St
input
Reset E
input
Lost Status of data
input for each shift
St: Starting word input
E: End word

REVERSIBLE Creates a shift register that shifts data to either the right or the left. Output 362
SHIFT REGISTER SFTR(084) Required
SFTR C
@SFTR
084 St
E St Data input
E
Shift
C: Control word E St direc-
St: Starting word Data tion
E: End word input

ASYNCHRO- Output 365

Shifts all non-zero word data within the specified word range either
NOUS SHIFT ASFT(017) Required
REGISTER towards St or toward E, replacing 0000Hex word data.
C
ASFT
@ASFT St
017
E St Shift direction
C: Control word Shift enabled
Shift
St: Starting word
•••

E: End word Clear

Shift

St

Zero data
•••

Non-zero data
E

WORD SHIFT Shifts data between St and E in word units. Output 368
WSFT WSFT(016) Required
@WSFT S E St
016 Lost
St
E

S: Source word
St: Starting word
E: End word
ARITHMETIC Shifts the contents of Wd one bit to the left. Output 370
SHIFT LEFT ASL(025) Required
ASL Wd
@ASL
025 Wd: Word

46
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DOUBLE SHIFT Shifts the contents of Wd and Wd +1 one bit to the left. Output 371
LEFT ASLL(570) Required
ASLL Wd+1 Wd
@ASLL Wd
570 Wd: Word

ARITHMETIC Shifts the contents of Wd one bit to the right. Output 373
SHIFT RIGHT ASR(026) Required
ASR
@ASR Wd
026 Wd: Word

DOUBLE SHIFT Output 374

RIGHT ASRL(571) Shifts the contents of Wd and Wd +1 one bit to the right.
Required
ASRL Wd Wd+1 Wd
@ASRL
571 Wd: Word

ROTATE LEFT Output 376

ROL(027) Shifts all Wd bits one bit to the left including the Carry Flag (CY).
ROL Required
@ROL Wd
027
Wd: Word

DOUBLE Output 378

ROTATE LEFT ROLL(572)
Shifts all Wd and Wd + 1 bits one bit to the left including the Carry Flag
(CY). Required
ROLL Wd
@ROLL Wd+1 Wd
572
Wd: Word

ROTATE LEFT Output 383

WITHOUT RLNC(574) Shifts all Wd bits one bit to the left not including the Carry Flag (CY).
Required
CARRY
Wd Wd
RLNC
@RLNC
Wd: Word
574

DOUBLE Shifts all Wd and Wd +1 bits one bit to the left not including the Carry Output 385
ROTATE LEFT RLNL(576) Flag (CY). Required
WITHOUT
CARRY Wd Wd+1 Wd
RLNL
@RLNL Wd: Word
576
ROTATE RIGHT Shifts all Wd bits one bit to the right including the Carry Flag (CY). Output 380
ROR ROR(028) Required
@ROR Wd+1 Wd
Wd
028
Wd: Word

DOUBLE Shifts all Wd and Wd +1 bits one bit to the right including the Carry Output 381
ROTATE RIGHT RORL(573) Required
Flag (CY).
RORL
@RORL Wd Wd+1 Wd
573 Wd: Word

47
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
ROTATE RIGHT Shifts all Wd bits one bit to the right not including the Carry Flag (CY). Output 387
WITHOUT RRNC(575) The contents of the rightmost bit of Wd shifts to the leftmost bit and to Required
CARRY the Carry Flag (CY).
Wd
RRNC
@RRNC Wd: Word
575
Wd

DOUBLE Shifts all Wd and Wd +1 bits one bit to the right not including the Carry Output 388
ROTATE RIGHT RRNL(577) Flag (CY). The contents of the rightmost bit of Wd +1 is shifted to the Required
WITHOUT leftmost bit of Wd, and to the Carry Flag (CY).
CARRY Wd
RRNL Wd+1 Wd
Wd: Word
@RRNL
577

ONE DIGIT SHIFT Shifts data by one digit (4 bits) to the left. Output 390
LEFT SLD(074) Required
SLD E S t
St
@SLD
074 E Lost

St: Starting word

E: End word

ONE DIGIT SHIFT Output 392

RIGHT SRD(075) Shifts data by one digit (4 bits) to the right.
E S t Required
SRD St
@SRD Lost
075 E
St: Starting word
E: End word
SHIFT N-BIT Output 393
DATA LEFT NSFL(578) Shifts the specified number of bits to the left.
Required
NSFL D
@NSFL
578 C
N

D: Beginning
word for shift Shifts one bit to the left
N−1 bit
C: Beginning bit
N: Shift data
length
N−1 bit

SHIFT N-BIT Shifts the specified number of bits to the right. Output 395
DATA RIGHT NSFR(579) Required
NSFR D
@NSFR
579 C
N
D: Beginning Shifts one bit to the right
word for shift N−1 bit
C: Beginning bit
N: Shift data
length
N−1 bit

48
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
SHIFT N-BITS Shifts the specified 16 bits of word data to the left by the specified Output 397
LEFT NASL(580) Required
number of bits.
NASL D
@NASL
580 C
D: Shift word Shift n-bits
C: Control word

Contents of
shifted in "a"
Lost or "0"

N bits

DOUBLE SHIFT Shifts the specified 32 bits of word data to the left by the specified Output 400
N-BITS LEFT NSLL(582)
number of bits. Required
NSLL D
@NSLL
582 C

D: Shift word Shift n-bits

C: Control word
Contents of
"a" or "0"
shifted in
Lost

N bits

SHIFT N-BITS Shifts the specified 16 bits of word data to the right by the specified Output 403
RIGHT NASR(581)
number of bits. Required
NASR D
@NASR
581 C
Contents of "a" or
D: Shift word "0" shifted in
C: Control word Lost

N bits

DOUBLE SHIFT Shifts the specified 32 bits of word data to the right by the specified Output 405
N-BITS RIGHT NSRL(583) Required
number of bits.
NSRL D
@NSRL
583 C Shift n-bits
D: Shift word
C: Control word Contents of
"a" or "0"
shifted in Lost
N bits

49
Instruction Functions Section 2-2

2-2-8 Increment/Decrement Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
INCREMENT Output 409
BINARY ++(590) Increments the 4-digit hexadecimal content of the specified word by 1.
Required
++ Wd Wd Wd
@++
590 Wd: Word

DOUBLE INCRE- Increments the 8-digit hexadecimal content of the specified words by Output 411
MENT BINARY ++L(591) Required
1.
++L Wd
@++L Wd+1 Wd Wd+1 Wd
591 Wd: Word

DECREMENT Decrements the 4-digit hexadecimal content of the specified word by Output 413
BINARY − − (592) Required
1.
–– Wd
@– – Wd Wd
592 Wd: Word

DOUBLE DEC- Decrements the 8-digit hexadecimal content of the specified words by Output 415
REMENT − − L(593) Required
BINARY 1.
Wd
– –L Wd+1 Wd Wd+1 Wd
@– –L
Wd: 1st word
593
INCREMENT Increments the 4-digit BCD content of the specified word by 1. Output 417
BCD ++B(594) Required
++B Wd Wd Wd
@++B
594 Wd: Word

DOUBLE INCRE- Increments the 8-digit BCD content of the specified words by 1. Output 419
MENT BCD ++BL(595) Required
++BL
@++BL Wd
Wd+1 Wd Wd+1 Wd
595 Wd: 1st word

DECREMENT Decrements the 4-digit BCD content of the specified word by 1. Output 421
BCD − − B(596) Required
– –B Wd
@– –B Wd −1 Wd
596 Wd: Word

DOUBLE DEC- Output 423

REMENT BCD − − BL(597) Decrements the 8-digit BCD content of the specified words by 1.
Required
– –BL Wd
@– –BL Wd+1 Wd Wd+1 Wd
597 Wd: 1st word

50
Instruction Functions Section 2-2

2-2-9 Symbol Math Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
SIGNED BINARY Adds 4-digit (single-word) hexadecimal data and/or constants. Output 426
ADD WITHOUT +(400) Required
CARRY
+
Au Au (Signed binary)
@+ Ad
400 + Ad (Signed binary)
R
CY will turn ON
Au: Augend word when there is a CY R (Signed binary)
Ad: Addend word carry.
R: Result word

DOUBLE Adds 8-digit (double-word) hexadecimal data and/or constants. Output 428
SIGNED BINARY +L(401) Required
ADD WITHOUT Au+1 (Signed binary)
CARRY Au Au
+L Ad
@+L + Ad+1 Ad (Signed binary)
401 R
CY will turn
ON when CY R+1 R (Signed binary)
Au: 1st augend there is a
word carry.
Ad: 1st addend
word
R: 1st result word
SIGNED BINARY Adds 4-digit (single-word) hexadecimal data and/or constants with the Output 430
ADD WITH +C(402) Carry Flag (CY). Required
CARRY
+C
Au Au (Signed binary)
@+C Ad
402 Ad (Signed binary)
R
Au: Augend word + CY
Ad: Addend word CY will turn ON
R: Result word when there is a CY R (Signed binary)
carry.

DOUBLE Adds 8-digit (double-word) hexadecimal data and/or constants with the Output 432
SIGNED BINARY +CL(403) Carry Flag (CY). Required
ADD WITH
CARRY Au Au+1 Au (Signed binary)
+CL Ad
@+CL Ad+1 Ad (Signed binary)
403 R
+ CY
Au: 1st augend
word CY will turn ON
Ad: 1st addend when there is a CY R+1 R (Signed binary)
word carry.
R: 1st result word
BCD ADD WITH- Output 434
OUT CARRY +B(404) Adds 4-digit (single-word) BCD data and/or constants.
Required
+B Au Au (BCD)
@+B
404 Ad Ad (BCD)
+
R
CY will turn ON
Au: Augend word when there is a CY R (BCD)
Ad: Addend word carry.
R: Result word

51
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DOUBLE BCD Adds 8-digit (double-word) BCD data and/or constants. Output 435
ADD WITHOUT +BL(405) Required
CARRY Au+1 Au (BCD)
Au
+BL
@+BL Ad (BCD)
Ad+1 Ad
405 +
R
CY will turn ON (BCD)
Au: 1st augend when there is a CY R+1 R
word carry.
Ad: 1st addend
word
R: 1st result
word

BCD ADD WITH Adds 4-digit (single-word) BCD data and/or constants with the Carry Output 437
CARRY +BC(406) Required
Flag (CY).
+BC Au (BCD)
@+BC
Au
406 Ad Ad (BCD)
R
+ CY
Au: Augend word CY will turn ON
Ad: Addend word when there is a
R: Result word carry. CY R (BCD)

DOUBLE BCD Adds 8-digit (double-word) BCD data and/or constants with the Carry Output 439
ADD WITH +BCL(407) Flag (CY). Required
CARRY
Au Au+1 Au (BCD)
+BCL
@+BCL Ad
Ad+1 Ad (BCD)
407
R
+ CY
Au: 1st augend
word
Ad: 1st addend CY will turn
ON when there CY R+1 R (BCD)
word
R: 1st result word is a carry.

SIGNED BINARY Output 440

SUBTRACT −(410) Subtracts 4-digit (single-word) hexadecimal data and/or constants.
Required
WITHOUT Mi (Signed binary)
CARRY Mi
– Su − (Signed binary)
@– Su
410 R
CY will turn ON CY R (Signed binary)
Mi: Minuend word when there is a
Su: Subtrahend borrow.
word
R: Result word

DOUBLE Output 442

SIGNED BINARY − L(411) Subtracts 8-digit (double-word) hexadecimal data and/or constants.
Required
SUBTRACT
WITHOUT Mi Mi+1 Mi (Signed binary)
CARRY Su
–L − Su+1 Su (Signed binary)
@–L R
411 CY will turn
Mi: Minuend word ON when CY R+1 R (Signed binary)
Su: Subtrahend there is a
word borrow.
R: Result word

52
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
SIGNED BINARY Subtracts 4-digit (single-word) hexadecimal data and/or constants Output 446
SUBTRACT −C(412) Required
WITH CARRY with the Carry Flag (CY).
Mi Mi (Signed binary)
–C
@–C Su Su (Signed binary)
412
R
− CY
Mi: Minuend word
Su: Subtrahend CY will turn ON
word when there is a CY R (Signed binary)
R: Result word borrow.

DOUBLE Subtracts 8-digit (double-word) hexadecimal data and/or constants Output 448
SIGNED BINARY −CL(413) with the Carry Flag (CY). Required
WITH CARRY
Mi
–CL Mi+1 Mi (Signed binary)
@–CL Su
413
R Su+1 Su (Signed binary)

Mi: Minuend word − CY

Su: Subtrahend CY will turn
word ON when
R: Result word there is a CY R+1 R (Signed binary)
borrow.
BCD SUBTRACT Subtracts 4-digit (single-word) BCD data and/or constants. Output 451
WITHOUT −B(414) Required
CARRY Mi (BCD)
Mi
–B
@–B Su − Su (BCD)
414
R
CY will turn ON
when there is a CY R (BCD)
Mi: Minuend word
Su: Subtrahend carry.
word
R: Result word

DOUBLE BCD Subtracts 8-digit (double-word) BCD data and/or constants. Output 452
SUBTRACT −BL(415) Required
WITHOUT
CARRY Mi Mi +1 Mi (BCD)
–BL Su
@–BL − Su+1 Su (BCD)
415 R
Mi: 1st minuend CY will turn ON CY R+1 R (BCD)
word when there is a
Su: 1st borrow.
subtrahend word
R: 1st result word

BCD SUBTRACT Subtracts 4-digit (single-word) BCD data and/or constants with the Output 456
WITH CARRY −BC(416) Carry Flag (CY). Required
–BC
@–BC Mi Mi (BCD)
416 Su
Su (BCD)
R
− CY
Mi: Minuend word
Su: Subtrahend
word CY will turn ON (BCD)
R: Result word when there is a CY R
borrow.

53
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DOUBLE BCD Subtracts 8-digit (double-word) BCD data and/or constants with the Output 457
SUBTRACT −BCL(417) Carry Flag (CY). Required
WITH CARRY
–BCL Mi Mi +1 Mi (BCD)
@–BCL Su
417 Su+1 Su (BCD)
R
− CY
Mi: 1st minuend
word
Su: 1st CY will turn ON (BCD)
subtrahend word when there is a CY R+1 R
R: 1st result word borrow.

SIGNED BINARY Output 459

MULTIPLY *(420) Multiplies 4-digit signed hexadecimal data and/or constants.
Required
* Md Md (Signed binary)
@*
420 Mr
× Mr (Signed binary)
R
Md: Multiplicand R +1 R (Signed binary)
word
Mr: Multiplier
word
R: Result word
DOUBLE Multiplies 8-digit signed hexadecimal data and/or constants. Output 461
SIGNED BINARY *L(421) Required
MULTIPLY
*L
Md Md + 1 Md (Signed binary)
@*L Mr
421 × Mr + 1 Mr (Signed binary)
R

Md: 1st
multiplicand word R+3 R+2 R+1 R (Signed binary)
Mr: 1st multiplier
word
R: 1st result word
UNSIGNED Output 463
BINARY *U(422) Multiplies 4-digit unsigned hexadecimal data and/or constants.
Required
MULTIPLY
*U
Md Md (Unsigned binary)
@*U Mr
422 (Unsigned binary)
R × Mr

Md: Multiplicand
word R +1 R (Unsigned binary)
Mr: Multiplier
word
R: Result word

DOUBLE Output 465

UNSIGNED *UL(423) Multiplies 8-digit unsigned hexadecimal data and/or constants.
Required
BINARY
MULTIPLY Md Md + 1 Md (Unsigned binary)
*UL Mr
@*UL
423 R × Mr + 1 Mr (Unsigned binary)

Md: 1st
multiplicand word
Mr: 1st multiplier R+3 R+2 R+1 R (Unsigned binary)
word
R: 1st result word

54
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
BCD MULTIPLY Multiplies 4-digit (single-word) BCD data and/or constants. Output 467
*B *B(424) Required
@*B Md (BCD)
Md
424
Mr
× Mr (BCD)
R
Md: Multiplicand
R +1 R (BCD)
word
Mr: Multiplier
word
R: Result word

DOUBLE BCD Multiplies 8-digit (double-word) BCD data and/or constants. Output 469
MULTIPLY *BL(425) Required
*BL Md (BCD)
@*BL Md + 1 Md
425 Mr
× Mr + 1 Mr (BCD)
R
Md: 1st
multiplicand word (BCD)
Mr: 1st multiplier R+3 R+2 R+1 R
word
R: 1st result word

SIGNED BINARY Divides 4-digit (single-word) signed hexadecimal data and/or Output 471
DIVIDE /(430) constants. Required
/ Dd Dd (Signed binary)
@/
430 Dr
÷ Dr (Signed binary)
R

Dd: Dividend word (Signed binary)

R +1 R
Dr: Divisor word
R: Result word Remainder Quotient

DOUBLE Divides 8-digit (double-word) signed hexadecimal data and/or Output 473
SIGNED BINARY /L(431) constants. Required
DIVIDE
/L
Dd Dd + 1 Dd (Signed binary)
@/L Dr
431 ÷ (Signed binary)
R Dr + 1 Dr

Dd: 1st dividend

word R+3 R+2 R+1 R (Signed binary)
Dr: 1st divisor
word
R: 1st result word Remainder Quotient

UNSIGNED Divides 4-digit (single-word) unsigned hexadecimal data and/or Output 475
BINARY DIVIDE /U(432) Required
constants.
/U Dd
@/U Dd (Unsigned binary)
432 Dr
R ÷ Dr (Unsigned binary)
Dd: Dividend
word
Dr: Divisor word R +1 R (Unsigned binary)
R: Result word
Remainder Quotient

55
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DOUBLE Divides 8-digit (double-word) unsigned hexadecimal data and/or Output 477
UNSIGNED /UL(433) Required
BINARY DIVIDE constants.
/UL Dd Dd + 1 Dd (Unsigned binary)
@/UL Dr
433
R ÷ Dr + 1 Dr (Unsigned binary)

Dd: 1st dividend

word
Dr: 1st divisor R+3 R+2 R+1 R (Unsigned binary)
word
R: 1st result word Remainder Quotient

BCD DIVIDE Output 479

/B /B(434) Divides 4-digit (single-word) BCD data and/or constants. Required
@/B Dd
434 Dd (BCD)
Dr
R ÷ Dr (BCD)

Dd: Dividend
word
R +1 R (BCD)
Dr: Divisor word
R: Result word Remainder Quotient

DOUBLE BCD Output 481

/BL(435) Divides 8-digit (double-word) BCD data and/or constants.
DIVIDE Required
/BL Dd (BCD)
@/BL Dd + 1 Dd
435 Dr
R ÷ Dr + 1 Dr (BCD)

Dd: 1st dividend

word
Dr: 1st divisor R+3 R+2 R+1 R (BCD)
word
R: 1st result word Remainder Quotient

2-2-10 Conversion Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
BCD TO BINARY Output 483
BIN(023) Converts BCD data to binary data.
BIN Required
@BIN S (BCD) (BIN)
R
023
R
S: Source word
R: Result word
DOUBLE BCD TO Converts 8-digit BCD data to 8-digit hexadecimal (32-bit binary) data. Output 485
DOUBLE BINL(058) Required
BINARY
BINL
S (BCD) R (BIN)
@BINL R (BCD) R+1 (BIN)
058
S: 1st source
word
R: 1st result word

56
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
BINARY TO BCD Output 487
BCD(024) Converts a word of binary data to a word of BCD data.
BCD Required
@BCD (BIN) R (BCD)
S
024
R
S: Source word
R: Result word
DOUBLE Output 489
BINARY TO DOU- BCDL(059) Converts 8-digit hexadecimal (32-bit binary) data to 8-digit BCD data.
Required
BLE BCD
S (BIN) R (BCD)
BCDL
@BCDL R (BIN) R+1 (BCD)
059
S: 1st source
word
R: 1st result word

2’S COMPLE- Output 491

MENT NEG(160) Calculates the 2's complement of a word of hexadecimal data.
Required
NEG S 2's complement
@NEG (Complement + 1)
160 R (S) (R)
S: Source word
R: Result word

DOUBLE 2’S Calculates the 2's complement of two words of hexadecimal data. Output 493
COMPLEMENT NEGL(161) Required
NEGL S 2's complement
@NEGL (Complement + 1)
161 R (S+1, S) (R+1, R)

S: 1st source
word
R: 1st result word
16-BIT TO 32-BIT Expands a 16-bit signed binary value to its 32-bit equivalent. Output 494
SIGNED BINARY SIGN(600) Required
SIGN S MSB
@SIGN
600 R S

S: Source word MSB = 0:

MSB = 1:
0000 Hex
R: 1st result word FFFF Hex

D+1 D
D = Contents of S

57
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DATA DECODER Reads the numerical value in the specified digit (or byte) in the source Output 496
MLPX MLPX(076) Required
word, turns ON the corresponding bit in the result word (or 16-word
@MLPX S range), and turns OFF all other bits in the result word (or 16-word
076 range).
C 4-to-16 bit conversion
R C

S: Source word l=1 (Convert 2 digits.)

C: Control word
R: 1st result word
n=2 (Start with second digit.)

4-to-16 bit decoding

(Bit m of R is turned ON.)

R
R+1

8-to-256 bit conversion

C
l=1 (Convert 2 bytes.)

n=1 (Start with first byte.)

8-to-256 bit decoding

(Bit m of R to R+15 is turned ON.)

R+1

R+14
R+15
R+16
R+17
Two 16-word ranges are
used when l specifies 2
bytes.
R+30
R+31

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Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DATA ENCODER FInds the location of the first or last ON bit within the source word (or Output 500
DMPX DMPX(077) 16-word range), and writes that value to the specified digit (or byte) in Required
@DMPX S the result word.
077 16-to-4 bit conversion
R C
Finds leftmost bit
C (Highest bit address)
S: 1st source l=1 (Convert
word 2 words.)
R: Result word
C: Control word

16-to-4 bit decoding

(Location of leftmost Leftmost bit Rightmost bit
bit (m) is written to R.)

n=2 (Start with digit 2.)

256-to-8 bit conversion

C
l=0 (Convert one 16-word range.)

Leftmost bit

Finds leftmost bit

(Highest bit address)

256-to-8 bit decoding (The location of

the leftmost bit in the 16-word range
(m) is written to R.)
n=1 (Start with byte 1.)

ASCII CONVERT Converts 4-bit hexadecimal digits in the source word into their 8-bit Output 504
ASC ASC(086) Required
ASCII equivalents.
@ASC Di
S
086
Di First digit to convert

S: Source word
Di: Digit
designator
D: 1st destination Number of
word digits (n+1)

Left (1) Right (0)

59
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
ASCII TO HEX Converts up to 4 bytes of ASCII data in the source word to their Output 508
HEX HEX(162) hexadecimal equivalents and writes these digits in the specified Required
@HEX destination word.
S
162 C: 0021
Di Di
D First byte to convert

S: 1st source Left (1) Right (0)

word
Di: Digit
designator
D: Destination
word
Number of digits (n+1)

First digit to write

COLUMN TO Converts a column of bits from a 16-word range (the same bit number Output 512
LINE LINE(063) Required
in 16 consecutive words) to the 16 bits of the destination word.
LINE S
@LINE N
Bit Bit
063 N 15 00
D
S 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1
S: 1st source S+1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1
word
N: Bit number S+2 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1
D: Destination S+3 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1
word . . . .
. . . .
. . . .
S+15 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0

Bit Bit
15 00

D 0 . . . 0 1 1 1
LINE TO Converts the 16 bits of the source word to a column of bits in a Output 514
COLUMN COLM(064)
16-word range of destination words (the same bit number in 16 Required
COLM S consecutive words).
@COLM
064 D Bit Bit
15 00
N
S 0 . . . . . . . 0 1 1 1
S: Source word
D: 1st destination
word
N: Bit number
Bit Bi Bit
15 00
D 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1
D+1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1
D+2 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1
D+3 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1
. . . .
. . . .
. . . .
D+15 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0

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Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
SIGNED BCD TO Converts one word of signed BCD data to one word of signed binary Output 517
BINARY BINS(470)
data. Required
BINS C
@BINS
470 S Signed BCD format
D specified in C

C: Control word Signed BCD Signed binary

S: Source word
D: Destination
word
DOUBLE Converts double signed BCD data to double signed binary data. Output 520
SIGNED BCD TO BISL(472) Required
BINARY
C
BISL
@BISL S Signed BCD format
472 specified in C
D
Signed BCD Signed binary
C: Control word
S: 1st source Signed BCD Signed binary
word
D: 1st destination
word

SIGNED BINARY Converts one word of signed binary data to one word of signed BCD Output 523
TO BCD BCDS(471)
data. Required
BCDS C
@BCDS
471 S Signed BCD format
specified in C
D
Signed binary Signed BCD
C: Control word
S: Source word
D: Destination
word

DOUBLE Converts double signed binary data to double signed BCD data. Output 525
SIGNED BINARY BDSL(473) Required
TO BCD
C
BDSL
@BDSL S Signed BCD format
473
D specified in C

C: Control word Signed binary Signed BCD

S: 1st source Signed binary Signed BCD
word
D: 1st destination
word
GRAY CODE Converts the Gray code data in the specified word to binary, BCD, or Output 529
CONVERSION GRY (474) angle (°) data at the specified resolution. Required
GRY C
474
S
(CS/CJ-series
Unit Ver. 2.0 or D
later only, includ-
ing CS1-H, CJ1-H, C: Control word
and CJ1M CPU S: Source word
Units from lot D: 1st destination
number 030201
and later) word

61
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
FOUR-DIGIT Converts a 4-digit hexadecimal number (#0000 to #FFFF) to ASCII Output 534
NUMBER TO STR4 data (4 characters). Required
ASCII
S
STR4
@STR4 D
601
S: Numeric
(CS/CJ-series D: ASCII text
CPU Units with
unit version 4.0 or
later only)
EIGHT-DIGIT Converts an 8-digit hexadecimal number (#0000 0000 to #FFFF FFFF) Output 537
NUMBER TO- STR8 to ASCII data (8 characters). Required
ASCII
S
STR8
@STR8 D
602
S: Numeric
(CS/CJ-series D: ASCII text
CPU Units with
unit version 4.0 or
later only)
SIXTEEN-DIGIT Converts a 16-digit hexadecimal number (#0000 0000 0000 0000 to Output 539
NUMBER TO STR16 #FFFF FFFF FFFF FFFF) to ASCII data (16 characters). Required
ASCII
S
STR16
@STR16 D
603
S: Numeric
(CS/CJ-series D: ASCII text
CPU Units with
unit version 4.0 or
later only)
ASCII TO FOUR- Converts 4 characters of ASCII data to a 4-digit hexadecimal number. Output 541
DIGIT NUMBER NUM4 Required
NUM4 S
@NUM4
604 D
(CS/CJ-series S: ASCII text
CPU Units with D: Numeric
unit version 4.0 or
later only)
ASCII TO EIGHT- Converts 8 characters of ASCII data to an 8-digit hexadecimal number. Output 544
DIGIT NUMBER NUM8 Required
NUM8 S
@NUM8
605 D
(CS/CJ-series S: ASCII text
CPU Units with D: Numeric
unit version 4.0 or
later only)
ASCII TO SIX- Converts 16 characters of ASCII data to a 16-digit hexadecimal num- Output 545
TEEN-DIGIT NUM16 ber. Required
NUMBER
S
NUM16
@NUM16 D
606
S: ASCII text
(CS/CJ-series D: Numeric
CPU Units with
unit version 4.0 or
later only)

62
Instruction Functions Section 2-2

2-2-11 Logic Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
LOGICAL AND Takes the logical AND of corresponding bits in single words of word Output 548
ANDW ANDW(034) Required
data and/or constants.
@ANDW
I1
034 I1. I2→ R
I2
I1 I2 R
R
1 1 1
I1: Input 1
I2: Input 2 1 0 0
R: Result word
0 1 0
0 0 0

DOUBLE Takes the logical AND of corresponding bits in double words of word Output 550
LOGICAL AND ANDL(610) Required
data and/or constants.
ANDL I1
@ANDL
(I1, I1+1). (I2, I2+1)→ (R, R+1)
610 I2
I1, I1+1 I2, I2+1 R, R+1
R
1 1 1
I1: Input 1
I2: Input 2 1 0 0
R: Result word
0 1 0
0 0 0

LOGICAL OR Output 551

ORW(035) Takes the logical OR of corresponding bits in single words of word
ORW data and/or constants. Required
@ORW I1
035 I1 + I2 → R
I2
R I1 I2 R
1 1 1
I1: Input 1
I2: Input 2 1 0 1
R: Result word
0 1 1
0 0 0

DOUBLE Takes the logical OR of corresponding bits in double words of word Output 553
LOGICAL OR ORWL(611)
data and/or constants. Required
ORWL I1
@ORWL
(I1, I1+1) + (I2, I2+1) →(R, R+1)
611 I2
I1, I1+1 I2, I2+1 R, R+1
R
1 1 1
I1: Input 1
I2: Input 2 1 0 1
R: Result word 0 1
1
0 0 0

EXCLUSIVE OR Output 555

XORW XORW(036) Takes the logical exclusive OR of corresponding bits in single words Required
@XORW of word data and/or constants.
I1
036 I1. I2 + I1.I2 → R
I2
R I1 I2 R
I1: Input 1
1 1 0
I2: Input 2 1 0 1
R: Result word
0 1 1
0 0 0

63
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DOUBLE EXCLU- Output 557
SIVE OR XORL(612) Takes the logical exclusive OR of corresponding bits in double words
of word data and/or constants. Required
XORL I1
@XORL (I1, I1+1). (I2, I2+1) + (I1, I1+1). (I2, I2+1) → (R, R+1)
612 I2
R I1, I1+1 I2, I2+1 R, R+1
1 1 0
I1: Input 1
I2: Input 2 1 0 1
R: Result word
0 1 1
0 0 0

EXCLUSIVE NOR Takes the logical exclusive NOR of corresponding single words of Output 559
XNRW(037)
XNRW word data and/or constants. Required
@XNRW I1
037 I1. I2 + I1.I2 →R
I2
I1 I2 R
R
I1: Input 1
1 1 1
I2: Input 2 1 0 0
R: Result word
0 1 0
0 0 1

DOUBLE EXCLU- Takes the logical exclusive NOR of corresponding bits in double Output 560
SIVE NOR XNRL(613) Required
words of word data and/or constants.
XNRL I1
@XNRL (I1, I1+1). (I2, I2+1) + (I1, I1+1). (I2, I2+1) → (R, R+1)
613 I2
R I1, I1+1 I2, I2+1 R, R+1
1 1 1
I1: Input 1
I2: Input 2 1 0 0
R: 1st result word 0 1 0
0 0 1

COMPLEMENT Output 562

COM(029) Turns OFF all ON bits and turns ON all OFF bits in Wd.
COM Required
@COM Wd→Wd: 1 → 0 and 0 → 1
Wd
029
Wd: Word

DOUBLE COM- Output 564

PLEMENT COML(614) Turns OFF all ON bits and turns ON all OFF bits in Wd and Wd+1.
Required
COML Wd (Wd+1, Wd) → (Wd+1, Wd)
@COML
614
Wd: Word

64
Instruction Functions Section 2-2

2-2-12 Special Math Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
BINARY ROOT Computes the square root of the 32-bit binary content of the specified Output 565
ROTB(620) words and outputs the integer portion of the result to the specified
ROTB Required
@ROTB result word.
S
620
R
S+1 S R
S: 1st source
word Binary data (32 bits) Binary data (16 bits)
R: Result word

BCD SQUARE Computes the square root of an 8-digit BCD number and outputs the Output 567
ROOT ROOT(072) integer portion of the result to the specified result word. Required
ROOT
@ROOT
S
072 R
S+1 S R
S: 1st source
BCD data (8 digits) BCD data (4 digits)
word
R: Result word

ARITHMETIC Calculates the sine, cosine, or a linear extrapolation of the source data. Output 571
PROCESS APR(069)
The linear extrapolation function allows any relationship between X and Required
APR C Y to be approximated with line segments.
@APR
069 S
R
C: Control word
S: Source data
R: Result word

FLOATING Divides one 7-digit floating-point number by another. The floating- Output 583
POINT DIVIDE FDIV(079) Required
point numbers are expressed in scientific notation (7-digit mantissa
FDIV Dd and 1-digit exponent).
@FDIV
Quotient
079 Dr
R+1 R
R
Dd: 1st dividend Dr+1 Dr Dd+1 Dd
word
Dr: 1st divisor
word
R: 1st result word

BIT COUNTER Counts the total number of ON bits in the specified word(s). Output 587
BCNT BCNT(067) Required
@BCNT N
067 N words
S Counts the number
to of ON bits.
R
S+(N −1) Binary result
N: Number of
words
S: 1st source R
word
R: Result word

65
Instruction Functions Section 2-2

2-2-13 Floating-point Math Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
FLOATING TO Converts a 32-bit floating-point value to 16-bit signed binary data and Output 594
16-BIT FIX(450) places the result in the specified result word. Required
FIX
@FIX S
S+1 S Floating-point data
450 R (32 bits)
S: 1st source
word R Signed binary data
R: Result word (16 bits)

FLOATING TO Converts a 32-bit floating-point value to 32-bit signed binary data and Output 596
32-BIT FIXL(451) Required
places the result in the specified result words.
FIXL S
@FIXL S+1 S Floating-point data
451 R
(32 bits)
S: 1st source
word R+1 R Signed binary data
R: 1st result word (32 bits)

16-BIT TO Converts a 16-bit signed binary value to 32-bit floating-point data and Output 597
FLOATING FLT(452) places the result in the specified result words. Required
FLT S
@FLT
R S Signed binary data
452
(16 bits)
S: Source word
R: 1st result word R+1 R Floating-point data
(32 bits)
32-BIT TO Converts a 32-bit signed binary value to 32-bit floating-point data and Output 599
FLOATING FLTL(453) places the result in the specified result words. Required
FLTL S
@FLTL S+1 S
R Signed binary data
453
(32 bits)
S: 1st source
word R+1 R Floating-point data
R: 1st result word (32 bits)
FLOATING- Adds two 32-bit floating-point numbers and places the result in the Output 601
POINT ADD +F(454) Required
specified result words.
+F Au
@+F Augend (floating-
454 Ad Au+1 Au
point data, 32 bits)
R
Addend (floating-
Au: 1st augend + Ad+1 Ad
point data, 32 bits)
word
AD: 1st addend
word R+1 R Result (floating-
R: 1st result word point data, 32 bits)
FLOATING- Subtracts one 32-bit floating-point number from another and places Output 603
POINT SUB- F(455) the result in the specified result words. Required
TRACT
–F
Mi
@–F Mi+1 Mi Minuend (floating-
Su
455 point data, 32 bits)
R
Mi: 1st Minuend
− Su+1 Su Subtrahend (floating-
point data, 32 bits)
word
Su: 1st
Subtrahend word R+1 R Result (floating-point
R: 1st result word data, 32 bits)

66
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
FLOATING- Multiplies two 32-bit floating-point numbers and places the result in Output 605
POINT MULTIPLY *F(456) the specified result words. Required
*F Md
@*F Md+1 Md Multiplicand (floating-
456 Mr point data, 32 bits)
R × Mr+1 Mr Multiplier (floating-
point data, 32 bits)
Md: 1st
Multiplicand word
Mr: 1st Multiplier R+1 R Result (floating-point
word data, 32 bits)
R: 1st result word
FLOATING- Divides one 32-bit floating-point number by another and places the Output 607
POINT DIVIDE /F(457) result in the specified result words. Required
/F Dd
@/F Dd+1 Dd Dividend (floating-
457 Dr point data, 32 bits)
R
÷ Dr+1 Dr Divisor (floating-
Dd: 1st Dividend point data, 32 bits)
word
Dr: 1st Divisor
word R+1 R Result (floating-
R: 1st result word point data, 32 bits)

DEGREES TO Converts a 32-bit floating-point number from degrees to radians and Output 609
RADIANS RAD(458) Required
places the result in the specified result words.
RAD S
@RAD
S+1 S Source (degrees, 32-bit
458 R floating-point data)
S: 1st source
word R+1 R Result (radians, 32-bit
R: 1st result word floating-point data)
RADIANS TO Converts a 32-bit floating-point number from radians to degrees and Output 610
DEGREES DEG(459) Required
places the result in the specified result words.
DEG S
@DEG
459 R S+1 S Source (radians, 32-bit
floating-point data)
S: 1st source
word
R: 1st result word R+1 R Result (degrees, 32-bit
floating-point data)
SINE Calculates the sine of a 32-bit floating-point number (in radians) and Output 612
SIN SIN(460) Required
places the result in the specified result words.
@SIN S
460 Source (32-bit
R SIN S+1 S
floating-point
S: 1st source data)
word
R: 1st result word R+1 R Result (32-bit
floating-point
data)

HIGH-SPEED Calculates the sine of a 32-bit floating-point number (in radians) and Output 614
SINE (CJ1-H-R SINQ(475) places the result in the specified result words. Required
only)
S SIN S+1 S Source (32-bit
SINQ
R floating-point
@SINQ data)
475 S: 1st source
word R+1 R Result (32-bit
R: 1st result word floating-point
data)

67
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
COSINE Calculates the cosine of a 32-bit floating-point number (in radians) Output 615
COS COS(461) and places the result in the specified result words. Required
@COS S
461 COS S+1 S Source (32-bit
R floating-point
S: 1st source
data)
word R+1 R Result (32-bit
R: 1st result word
floating-point
data)
HIGH-SPEED Calculates the cosine of a 32-bit floating-point number (in radians) and Output 617
COSINE (CJ1-H- COSQ(476) places the result in the specified result words. Required
R only) S
COSQ COS S+1 S Source (32-bit
@COSQ R
floating-point
476 data)
S: 1st source
word
R: 1st result word R+1 R Result (32-bit
floating-point
data)
TANGENT Calculates the tangent of a 32-bit floating-point number (in radians) Output 619
TAN TAN(462) Required
and places the result in the specified result words.
@TAN S
462 S+1 Source (32-bit
R TAN S
floating-point
S: 1st source data)
word
R: 1st result word R+1 R Result (32-bit
floating-point
data)
HIGH-SPEED Calculates the tangent of a 32-bit floating-point number (in radians) Output 621
TANGENT (CJ1- TANQ(477) and places the result in the specified result words. Required
H-R only)
S TAN S+1 S Source (32-bit
TANQ
floating-point
@TANQ R
data)
477 S: 1st source
word R+1 R Result (32-bit
R: 1st result word floating-point
data)
ARC SINE Calculates the arc sine of a 32-bit floating-point number and places Output 623
ASIN ASIN(463) Required
the result in the specified result words. (The arc sine function is the
@ASIN S inverse of the sine function; it returns the angle that produces a given
463 sine value between −1 and 1.)
R
S: 1st source Source (32-bit
SIN−1 S+1 S
floating-point
word
R: 1st result word data)

R+1 R Result (32-bit

floating-point
data)

ARC COSINE Calculates the arc cosine of a 32-bit floating-point number and places Output 625
ACOS(464)
ACOS the result in the specified result words. (The arc cosine function is the Required
@ACOS S inverse of the cosine function; it returns the angle that produces a
464 given cosine value between −1 and 1.)
R
S: 1st source Source (32-bit
word COS−1 S+1 S floating-point
R: 1st result word data)

Result (32-bit
R+1 R
floating-point
data)

68
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
ARC TANGENT Output 627
ATAN(465) Calculates the arc tangent of a 32-bit floating-point number and
ATAN places the result in the specified result words. (The arc tangent Required
@ATAN S function is the inverse of the tangent function; it returns the angle that
465 produces a given tangent value.)
R
Source (32-bit
S: 1st source TAN−1 S+1 S floating-point
word
R: 1st result word data)

R+1 R Result (32-bit

floating-point
data)

SQUARE ROOT Calculates the square root of a 32-bit floating-point number and Output 629
SQRT(466)
SQRT places the result in the specified result words. Required
@SQRT S
466
R S+1 S Source (32-bit
floating-point
S: 1st source data)
word
R: 1st result word R+1 R Result (32-bit
floating-point
data)
EXPONENT Calculates the natural (base e) exponential of a 32-bit floating-point Output 631
EXP(467) number and places the result in the specified result words.
EXP Required
@EXP S
467 Source (32-bit
R S+1 S floating-point
data)
S: 1st source
word
e
R: 1st result word
R+1 R Result (32-bit
floating-point
data)
LOGARITHM Calculates the natural (base e) logarithm of a 32-bit floating-point Output 633
LOG LOG(468) number and places the result in the specified result words. Required
@LOG S
468 Source (32-bit
R loge S+1 S floating-point
S: 1st source data)
word
R: 1st result word R+1 R Result (32-bit
floating-point
data)

EXPONENTIAL Raises a 32-bit floating-point number to the power of another 32-bit Output 635
POWER PWR(840)
floating-point number. Required
PWR
@PWR
B Power
840 E E+1 E
R B+1 S R+1 R
B: 1st base word Base
E: 1st exponent
word
R: 1st result word

69
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
FLOATING SYM- Using LD: Compares the specified single-precision data (32 bits) or constants LD: 636
BOL COMPARI- and creates an ON execution condition if the comparison result is true. Not required
SON (CS1-H, Symbol, option
Three kinds of symbols can be used with the floating-point symbol
CJ1-H, CJ1M, or S1 comparison instructions: LD (Load), AND, and OR. AND or OR:
CS1D only) S2 Required
LD, AND. or OR
+ Using AND:
=F (329), Symbol, option
<>F (330),
<F (331), S1
<=F (332), S2
>F (333),
or >=F (334) Using OR:

Symbol, option

S1
S2
S1: Comparison data 1
S2: Comparison data 2

FLOATING- Converts the specified single-precision floating-point data (32-bit deci- Output 640
POINT TO ASCII FSTR(448) mal-point or exponential format) to text string data (ASCII) and outputs required
(CS1-H, CJ1-H, the result to the destination word.
CJ1M, or CS1D S
only)
FSTR
C
@FSTR D
448
S: 1st source
word
C: Control word
D: Destination
word

ASCII TO FLOAT- Converts the specified text string (ASCII) representation of single-pre- Output 645
ING-POINT (CS1- FVAL(449) cision floating-point data (decimal-point or exponential format) to 32-bit required
H, CJ1-H, CJ1M, single-precision floating-point data and outputs the result to the desti-
or CS1D only) S nation words.
FVAL
@FVAL D
449
S: Source word
D: 1st destination
word
MOVE FLOAT- Transfers the specified 32-bit floating-point number to the destination Output 649
ING-POINT MOVF(469) words. required
(SINGLE)
(CJ1-H-R only) S S+1 S
MOVF D
@MOVF
469 S: First source
word D+1 D
D: First destination
word

70
Instruction Functions Section 2-2

2-2-14 Double-precision Floating-point Instructions

The Double-precision Floating-point Instructions are supported only by the
CS1-H, CJ1-H, CJ1M, or CS1D CPU Units.
Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
DOUBLE FLOAT- Converts the specified double-precision floating-point data (64 bits) to 16- Output 657
ING TO 16-BIT FIXD(841) bit signed binary data and outputs the result to the destination word. Required
BINARY
FIXD S
@FIXD
D
841
S: 1st source
word
D: Destination
word

DOUBLE FLOAT- Converts the specified double-precision floating-point data (64 bits) to 32- Output 658
ING TO 32-BIT FIXLD(842) bit signed binary data and outputs the result to the destination words. Required
BINARY
FIXLD S
@FIXLD
D
842
S: 1st source
word
D: 1st destination
word

16-BIT BINARY Converts the specified 16-bit signed binary data to double-precision float- Output 660
TO DOUBLE DBL(843) ing-point data (64 bits) and outputs the result to the destination words. Required
FLOATING
DBL S
@DBL D
843
S: Source word
D: 1st destination
word

32-BIT BINARY Converts the specified 32-bit signed binary data to double-precision float- Output 661
TO DOUBLE DBLL(844) ing-point data (64 bits) and outputs the result to the destination words. Required
FLOATING
DBLL S
@DBLL
D
844
S: 1st source
word
D: 1st destination
word

DOUBLE FLOAT- Adds the specified double-precision floating-point values (64 bits each) Output 663
ING-POINT ADD +D(845) and outputs the result to the result words. Required
+D
@+D Au
845 Ad
R
Au: 1st augend
word
Ad: 1st addend
word
R: 1st result word

71
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DOUBLE FLOAT- Subtracts the specified double-precision floating-point values (64 bits Output 665
ING-POINT SUB- −D(846) each) and outputs the result to the result words. Required
TRACT
−D Mi
@− D Su
846
R
Mi: 1st minuend
word
Su: 1st subtra-
hend word
R: 1st result word

DOUBLE FLOAT- Multiplies the specified double-precision floating-point values (64 bits Output 667
ING-POINT MUL- *D(847) each) and outputs the result to the result words. Required
TIPLY
*D Md
@*D Mr
847
R
Md: 1st multipli-
cand word
Mr: 1st multiplier
word
R: 1st result word

DOUBLE FLOAT- Divides the specified double-precision floating-point values (64 bits each) Output 669
ING-POINT /D(848) and outputs the result to the result words. Required
DIVIDE
/D Dd
@/D Dr
848
R
Dd: 1st Dividend
word
Dr: 1st divisor
word
R: 1st result word

DOUBLE Converts the specified double-precision floating-point data (64 bits) from Output 671
DEGREES TO RADD(849) degrees to radians and outputs the result to the result words. Required
RADIANS
RADD S
@RADD R
849
S: 1st source
word
R: 1st result word

DOUBLE RADI- Converts the specified double-precision floating-point data (64 bits) from Output 673
ANS TO DEGD(850) radians to degrees and outputs the result to the result words. Required
DEGREES
DEGD S
@DEGD R
850
S: 1st source
word
R: 1st result word

DOUBLE SINE Calculates the sine of the angle (radians) in the specified double-precision Output 674
SIND SIND(851) floating-point data (64 bits) and outputs the result to the result words. Required
@SIND
S
851
R
S: 1st source
word
R: 1st result word

72
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DOUBLE Calculates the cosine of the angle (radians) in the specified double-preci- Output 676
COSINE COSD(852) sion floating-point data (64 bits) and outputs the result to the result words. Required
COSD
@COSD S
852 R
S: 1st source
word
R: 1st result word

DOUBLE TAN- Calculates the tangent of the angle (radians) in the specified double-preci- Output 678
GENT TAND(853) sion floating-point data (64 bits) and outputs the result to the result words. Required
TAND
@TAND S
853 R
S: 1st source
word
R: 1st result word

DOUBLE ARC Calculates the angle (in radians) from the sine value in the specified dou- Output 680
SINE ASIND(854) ble-precision floating-point data (64 bits) and outputs the result to the Required
ASIND result words. (The arc sine function is the inverse of the sine function; it
@ASIND S returns the angle that produces a given sine value between -1 and 1.)
854 R
S: 1st source
word
R: 1st result word

DOUBLE ARC Calculates the angle (in radians) from the cosine value in the specified Output 682
COSINE ACOSD(855) double-precision floating-point data (64 bits) and outputs the result to the Required
ACOSD result words. (The arc cosine function is the inverse of the cosine function;
@ACOSD S it returns the angle that produces a given cosine value between -1 and 1.)
855 R
S: 1st source
word
R: 1st result word

DOUBLE ARC Calculates the angle (in radians) from the tangent value in the specified Output 684
TANGENT ATAND(856) double-precision floating-point data (64 bits) and outputs the result to the Required
ATAND result words. (The arc tangent function is the inverse of the tangent func-
@ATAND S tion; it returns the angle that produces a given tangent value.)
856 R
S: 1st source
word
R: 1st result word

DOUBLE Calculates the square root of the specified double-precision floating-point Output 686
SQUARE ROOT SQRTD(857) data (64 bits) and outputs the result to the result words. Required
SQRTD
@SQRTD S
857 R
S: 1st source
word
R: 1st result word

DOUBLE EXPO- Calculates the natural (base e) exponential of the specified double-preci- Output 688
NENT EXPD(858) sion floating-point data (64 bits) and outputs the result to the result words. Required
EXPD
@EXPD S
858 R
S: 1st source
word
R: 1st result word

73
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DOUBLE LOGA- Calculates the natural (base e) logarithm of the specified double-precision Output 690
RITHM LOGD(859) floating-point data (64 bits) and outputs the result to the result words. Required
LOGD
@LOGD S
859 R
S: 1st source
word
R: 1st result word

DOUBLE EXPO- Raises a double-precision floating-point number (64 bits) to the power of Output 692
NENTIAL PWRD(860) another double-precision floating-point number and outputs the result to Required
POWER the result words.
PWRD B
@PWRD E
860
R
B: 1st base word
E: 1st exponent
word
R: 1st result word

DOUBLE SYM- Using LD: Compares the specified double-precision data (64 bits) and creates an ON LD: 694
BOL COMPARI- execution condition if the comparison result is true. Not
SON Symbol, option
Three kinds of symbols can be used with the floating-point symbol com- required
LD, AND. or OR S1 parison instructions: LD (Load), AND, and OR.
+ S2 AND or
=D (335), OR:
<>D (336), Using AND: Required
<D (337), Symbol, option
<=D (338),
>D (339), S1
or >=D (340) S2

Using OR:

Symbol, option

S1
S2
S1: Comparison data 1
S2: Comparison data 2

74
Instruction Functions Section 2-2

2-2-15 Table Data Processing Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
SET STACK Defines a stack of the specified length beginning at the specified word Output 703
SSET(630)
SSET and initializes the words in the data region to all zeroes. Required
@SSET TB
630 Internal I/O
N memory address
TB
TB: 1st stack m+(N−1)
TB+1 N words
address
N: Number of TB+2 in stack
words Last word
TB+3
in stack
Stack
pointer
m+(N −1)

PUSH ONTO Writes one word of data to the specified stack. Output 706
STACK PUSH(632) Required
PUSH Internal I/O Internal I/O
@PUSH
TB memory address memory address
632 S
TB TB

TB: 1st stack TB+1 TB+1

TB+2 TB+2
address TB+3 PUSH(632) TB+3
S: Source word

LAST IN FIRST Reads the last word of data written to the specified stack (the newest Output 712
OUT LIFO(634) Required
data in the stack).
LIFO TB
@LIFO Stack Internal I/O Internal I/O
634 D pointer memory address memory address
TB: 1st stack TB TB
address TB+1 Newest TB+1
D: Destination TB+2 data TB+2
word TB+3 TB+3 m −1
Stack
pointer
m −1 m −1
A is left
un-
changed.

The pointer is Last-in first-out

decremented.

FIRST IN FIRST Reads the first word of data written to the specified stack (the oldest Output 709
OUT FIFO(633) data in the stack). Required
FIFO TB Internal I/O Internal I/O
@FIFO memory address memory address
633 D TB TB
Stack TB+1
Oldest TB+1
TB: 1st stack pointer data
address TB+2 TB+2
m −1
D: Destination TB+3 TB+3
word Stack
pointer
m−1

First-in first-out

75
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DIMENSION Defines a record table by declaring the length of each record and the Output 715
RECORD TABLE DIM(631) Required
number of records. Up to 16 record tables can be defined.
DIM
@DIM N Table number (N)
631 LR
NR Record 1

TB
N: Table number
LR: Length of Number of records LR × NR words
each record
NR: Number of
records
TB: 1st table Record NR
word
SET RECORD Writes the location of the specified record (the internal I/O memory Output 718
LOCATION SETR(635) address of the beginning of the record) in the specified Index Required
SETR N Register.
@SETR Internal I/O
635 R Table number (N) memory address
D SETR(635) writes the internal I/O
memory address (m) of the first word of
R record R to Index Register D.
N: Table number
R: Record Record
number number (R)
D: Destination
Index Register

GET RECORD Returns the record number of the record at the internal I/O memory Output 720
NUMBER GETR(636) address contained in the specified Index Register. Required
GETR
@GETR N
636 IR Table number (N) Internal I/O
memory address
D
N: Table number GETR(636) writes the
IR: Index IR Record number
record number of the
Register record that includes
(R)
D: Destination I/O memory address
word (m) to D.

DATA SEARCH Searches for a word of data within a range of words. Output 722
SRCH SRCH(181) Required
@SRCH Internal I/O
C memory address
181
R1
R1 Search
Cd
C Cd
C: 1st control
word
R1: 1st word in
range R1+(C−1)
Cd: Comparison
Match
data

76
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
SWAP BYTES Switches the leftmost and rightmost bytes in all of the words in the Output 725
SWAP(637)
SWAP range. Required
@SWAP N Byte position is swapped.
637
R1
N: Number of R1
words
R1: 1st word in N
range

FIND MAXIMUM Finds the maximum value in the range. Output 727
MAX MAX(182) Required
@MAX Internal I/O
C memory address
182
R1 R1

D C words
C: 1st control Max.
word value
R1: 1st word in R1+(W −1)
range
D: Destination
word

FIND MINIMUM Finds the minimum value in the range. Output 731
MIN MIN(183) Required
@MIN Internal I/O
C memory address
183 R1
R1
D C words
C: 1st control
word Min. value
R1: 1st word in R1+(W −1)
range
D: Destination
word

SUM Adds the bytes or words in the range and outputs the result to two Output 735
SUM SUM(184) Required
words.
@SUM
C
184
R1
D R1

C: 1st control
word
R1: 1st word in R1+(W−1)
range )
D: 1st destination
word

FRAME CHECK- Calculates the ASCII FCS value for the specified range. Output 738
SUM FCS(180) Required
FCS C R1
@FCS
180 R1 C units
D
C: 1st control ASCII conversion
word Calculation
R1: 1st word in FCS value
range
D: 1st destination
word

77
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
STACK SIZE Counts the amount of stack data (number of words) in the specified stack. Output 742
READ (CS1-H, SNUM(638) required
CJ1-H, CJ1M, or
CS1D only) TB
SNUM D
@SNUM
638 TB: First stack
address
D: Destination
word

STACK DATA Reads the data from the specified data element in the stack. The offset Output 744
READ (CS1-H, SREAD(639) value indicates the location of the desired data element (how many data required
CJ1-H, CJ1M, or elements before the current pointer position).
CS1D only) TB
SREAD C
@SREAD
639 D

TB: First stack

address
C: Offset value
D: Destination
word

STACK DATA Writes the source data to the specified data element in the stack (overwrit- Output 747
OVERWRITE SWRIT(640) ing the existing data). The offset value indicates the location of the desired required
(CS1-H, CJ1-H, data element (how many data elements before the current pointer posi-
CJ1M, or CS1D TB tion).
only)
C
SWRIT
@SWRIT S
640
TB: First stack
address
C: Offset value
S: Source data

STACK DATA Inserts the source data at the specified location in the stack and shifts the Output 750
INSERT (CS1-H, SINS(641) rest of the data in the stack downward. The offset value indicates the loca- required
CJ1-H, CJ1M, or tion of the insertion point (how many data elements before the current
CS1D only) TB pointer position).
SINS C
@SINS
641 S

TB: First stack

address
C: Offset value
S: Source data

STACK DATA Deletes the data element at the specified location in the stack and shifts Output 753
DELETE (CS1-H, SDEL(642) the rest of the data in the stack upward. The offset value indicates the required
CJ1-H, CJ1M, or location of the deletion point (how many data elements before the current
CS1D only) TB pointer position).
SDEL C
@SDEL
642 D

TB: First stack

address
C: Offset value
D: Destination
word

78
Instruction Functions Section 2-2

2-2-16 Data Control Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
PID CONTROL Executes PID control according to the specified parameters. Output 757
PID PID(190) Required
Parameters (C to C+8)
190 S
C
D PV input (S) PID control

S: Input word
C: 1st parameter
word
D: Output word Manipulated variable (D)

PID CONTROL Executes PID control according to the specified parameters. The PID Output 769
WITH AUTOTUN- PIDAT(191) constants can be auto-tuned with PIDAT(191). required
ING
PIDAT S
191 C
(CS1-H, CJ1-H,
or CJ1M only) D

S: Input word
C: 1st parameter
word
D: Output word

LIMIT CONTROL Controls output data according to whether or not input data is within Output 779
LMT LMT(680) Required
upper and lower limits.
@LMT
S
680
C
D
S: Input word Upper limit
C: 1st limit word C+1
D: Output word

Lower limit
C

DEAD BAND Controls output data according to whether or not input data is within Output 781
CONTROL BAND(681)
the dead band range. Required
BAND S Output
@BAND
681 C
D
Lower limit (C)
S: Input word
C: 1st limit word Input
D: Output word
Upper limit (C+1)

79
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DEAD ZONE Adds the specified bias to input data and outputs the result. Output 784
CONTROL ZONE(682)
Required
ZONE Output
S
@ZONE
682 C
Positive bias (C+1)
D
S: Input word Input
C: 1st limit word
D: Output word
Negative bias (C)

TIME-PROPOR- Inputs the duty ratio or manipulated variable from the specified word, Output 787
TIONAL OUTPUT converts the duty ratio to a time-proportional output based on the spec- Required
TPO (685)
TPO ified parameters, and outputs the result from the specified output.
685 S
(CS/CJ-series C
Unit Ver. 2.0 or
later only) R
S: Input word
C: 1st parameter
word
R: Pulse Output
Bit

SCALING Converts unsigned binary data into unsigned BCD data according to Output 795
SCL SCL(194) the specified linear function. Required
@SCL
S R (unsigned BCD) Scaling is performed according
194
P1 to the linear function defined by
points A and B.
R
Point B P (BCD)
S: Source word Converted
P1: 1st parameter P1 + 1 (BIN) value
Point A
word P1 + 2 (BCD)
R: Result word Converted
P1 + 3 (BIN) value
S (unsigned binary)

80
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
SCALING 2 Converts signed binary data into signed BCD data according to the Output 800
SCL2 SCL2(486) Required
specified linear function. An offset can be input in defining the linear
@SCL2 function.
S
486
P1 Positive Offset Negative Offset
R R (signed BCD) R (signed BCD)

S: Source word
P1: 1st parameter
word ∆Y
R: Result word ∆Y
Offset ∆X
∆X

S (signed binary) S (signed

Offset binary)

Offset of 0000
P1 Offset (Signed binary) R (signed BCD)
P1 + 1 ∆Y (Signed binary)
P1 + 2 ∆X (Signed BCD)

∆Y
Offset = 0000 hex
∆X
S (signed
binary)

81
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
SCALING 3 Output 804
SCL3(487) Converts signed BCD data into signed binary data according to the
SCL3 specified linear function. An offset can be input in defining the linear Required
@SCL3 function.
S
487
P1 Positive Offset Negative Offset

R R (signed binary) R (signed binary)

S: Source word Max conversion
P1: 1st parameter
Max
word conver-
R: Result word sion
∆Y ∆Y

∆X ∆X
Offset Offset S (signed BCD)
Min.
conver- S (signed BCD)
sion Min. conversion

Offset of 0000

R (signed binary)

Max
conver-
sion
∆Y

∆X
S (signed BCD)

Min. conversion

AVERAGE Calculates the average value of an input word for the specified Output 807
AVG AVG(195) number of cycles. Required
195 S S: Source word
N
R
S: Source word
N: Number of N: Number of cycles
cycles
R: Result word

R+1 Pointer

Average Valid Flag Average

R+2

R+3

N values

R+N+1

82
Instruction Functions Section 2-2

2-2-17 Subroutine Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
SUBROUTINE Calls the subroutine with the specified subroutine number and Output 811
CALL SBS(091) executes that program. Required
SBS N Execution condition ON
@SBS
091 N: Subroutine
number

Main program

Subroutine
program
(SBN(092) to
RET(093))

Program end

MACRO Calls the subroutine with the specified subroutine number and Output 817
MCRO MCRO(099) executes that program using the input parameters in S to S+3 and the Required
@MCRO N output parameters in D to D+3.
099
S MCRO(099)

D
N: Subroutine
number
S: 1st input Execution of sub-
parameter word routine between
SBN(092) and
D: 1st output RET(093).

parameter word MCRO(099)

The subroutine uses A600 to

A603 as inputs and A604 to
A607 as outputs.

SUBROUTINE Indicates the beginning of the subroutine program with the specified Output 821
ENTRY SBN(092) subroutine number. Not required
SBN N
092
N: Subroutine
number or

Subroutine region

SUBROUTINE Indicates the end of a subroutine program. Output 824

RETURN RET(093) Not required
RET
093

83
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
GLOBAL SUB- Calls the subroutine with the specified subroutine number and exe- Output 824
ROUTINE CALL GSBS(750) cutes that program. Not required
(CS1-H, CJ1-H,
CJ1M, or CS1D N
only)
GSBS N: Subroutine
number
750
GLOBAL SUB- Indicates the beginning of the subroutine program with the specified Output 832
ROUTINE ENTRY GSBN(751) subroutine number. Not required
(CS1-H, CJ1-H,
CJ1M, or CS1D N
only)
GSBN N: Subroutine
number
751
GLOBAL SUB- Indicates the end of a subroutine program. Output 835
ROUTINE GRET(752) Not required
RETURN (CS1-H,
CJ1-H, CJ1M, or
CS1D only)
GRET
752

2-2-18 Interrupt Control Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
SET INTERRUPT Sets up interrupt processing for I/O interrupts or scheduled Output 839
MASK MSKS(690) Required
(Not supported interrupts. Both I/O interrupt tasks and scheduled interrupt tasks
by CS1D CPU N are masked (disabled) when the PC is first turned on.
Units for Duplex- MSKS(690) can be used to unmask or mask I/O interrupts and
CPU Systems.) C set the time intervals for scheduled interrupts.
MSKS N: Interrupt Interrupt Input Unit 0 to 3
@MSKS
identifier
690
C: Control data I/O
interrupt
Mask (1) or unmask (0)
interrupt inputs 0 to 7.

Time interval
Scheduled
interrupt Set scheduled
interrupt time interval.

READ Reads the current interrupt processing settings that were set with Output 846
INTERRUPT MSKR(692) MSKS(690). Required
MASK
(Not supported N
by CS1D CPU D
Units for Duplex-
CPU Systems.) N: Interrupt
MSKR identifier
@MSKR D: Destination
692 word

84
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
CLEAR Output 851
CLI(691) Clears or retains recorded interrupt inputs for I/O interrupts
INTERRUPT Required
(Not supported or sets the time to the first scheduled interrupt for scheduled
by CS1D CPU N interrupts.
Units for Duplex-
CPU Systems.) C N = 0 to 3
CLI N: Interrupt
@CLI identifier Interrupt Interrupt
input n input n
691 C: Control data

Internal Internal
status status

Recorded interrupt cleared Recorded interrupt retained

N = 4 to 5
MSKS(690)
Execution of scheduled
interrupt task.

Time to first
scheduled interrupt

DISABLE INTER- Disables execution of all interrupt tasks except the power OFF Output 855
RUPTS DI(693) interrupt. Required
DI
@DI
693

Disables execution of all

interrupt tasks (except
the power OFF interrupt).

ENABLE INTER- Enables execution of all interrupt tasks that were disabled with Output 858
RUPTS EI(694) DI(693). Not required
EI
694

Disables execution of all

interrupt tasks (except the
power OFF interrupt).

Enables execution of all

disabled interrupt tasks.

85
Instruction Functions Section 2-2

2-2-19 High-speed Counter and Pulse Output Instructions

(CJ1M-CPU21/22/23 Only)
Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
MODE CONTROL INI(880) is used to start and stop target value comparison, to Output 864
INI
INI change the present value (PV) of a high-speed counter, to Required
@INI P change the PV of an interrupt input (counter mode), to change
880
C
the PV of a pulse output, or to stop pulse output.
NV

P: Port specifier
C: Control data
NV: 1st word with
new PV
HIGH-SPEED PRV(881) is used to read the present value (PV) of a high- Output 868
COUNTER PV PRV
speed counter, pulse output, or interrupt input (counter mode). Required
READ P
PRV
@PRV C
881 D

P: Port specifier
C: Control data
D: 1st destination
word
COUNTER FRE- Reads the pulse frequency input from a high-speed counter and either Output 874
QUENCY CON- PRV2 converts the frequency to a rotational speed (number of revolutions) or Required
VERT C1 converts the counter PV to the total number of revolutions. The result is
PRV2 output to the destination words as 8-digit hexadecimal. Pulses can be
883 C2 input from high-speed counter 0 only.
(CJ1M CPU Unit D
Ver. 2.0 or later
only) C1: Control data
C2: Pulses/revo-
lution
D: 1st destination
word

COMPARISON CTBL(882) is used to perform target value or range comparisons for Output 878
TABLE LOAD CTBL the present value (PV) of a high-speed counter. Required
CTBL P
@CTBL
C
882
TB

P: Port specifier
C: Control data
TB: 1st compari-
son table word
SPEED OUTPUT SPED(885) is used to specify the frequency and perform pulse output Output 882
SPED without acceleration or deceleration.
SPED Required
@SPED P
885
M
F

P: Port specifier
M: Output mode
F: 1st pulse fre-
quency word

86
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
SET PULSES PULS(886) is used to set the number of pulses for pulse output. Output 887
PULS
PULS Required
@PULS P
886
T
N

P: Port specifier
T: Pulse type
N: Number of
pulses
PULSE OUTPUT PLS2(887) is used to set the pulse frequency and acceleration/deceler- Output 890
PLS2 ation rates, and to perform pulse output with acceleration/deceleration Required
PLS2
@PLS2 P (with different acceleration/deceleration rates). Only positioning is pos-
sible.
887
M
S
F

P: Port specifier
M: Output mode
S: 1st word of set-
tings table
F: 1st word of
starting frequency
ACCELERATION ACC(888) is used to set the pulse frequency and acceleration/deceler- Output 896
CONTROL ACC ation rates, and to perform pulse output with acceleration/deceleration Required
ACC P (with the same acceleration/deceleration rate). Both positioning and
@ACC speed control are possible.
M
888
S

P: Port specifier
M: Output mode
S: 1st word of set-
tings table
ORIGIN SEARCH ORG(889) is used to perform origin searches and returns. Output 903
ORG
ORG Required
@ORG P
889
C

P: Port specifier
C: Control data
PULSE WITH PWM(891) is used to output pulses with a variable duty factor. Output 906
VARIABLE DUTY PWM
Required
FACTOR P
PWM
@ F
891 D

P: Port specifier
F: Frequency
D: Duty factor

87
Instruction Functions Section 2-2

2-2-20 Step Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
STEP DEFINE STEP(008) functions in following 2 ways, depending on its position and Output 909
STEP STEP(008) whether or not a control bit has been specified. Required
008 B (1)Starts a specific step.
(2)Ends the step programming area (i.e., step execution).
B: Bit

STEP START SNXT(009) is used in the following three ways: Output 909
SNXT SNXT(009) (1)To start step programming execution. Required
009 B (2)To proceed to the next step control bit.
(3)To end step programming execution.
B: Bit

2-2-21 Basic I/O Unit Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
I/O REFRESH Refreshes the specified I/O words. Output 926
IORF IORF(097) Required
@IORF I/O bit area or I/O Unit or
St
097 Special I/O Unit bit area Special I/O Unit
E
St: Starting word St
E: End word I/O refreshing

SPECIAL I/O Performs I/O refreshing immediately for the specified Special I/O Unit's Output 929
UNIT I/O FIORF(225) allocated CIO Area and DM Area words.t with the specified unit num- Required
REFRESH ber.
(CJ1-H-R only) N
FIORF N: Unit number
@FIORF
225
CPU BUS UNIT Immediately refreshes the I/O in the CPU Bus Unit with the specified Output 932
I/O REFRESH DLNK(226) unit number. required
(CS1-H, CJ1-H,
CJ1M, or CS1D N
only)
DLNK N: Unit number
@DLNK
226

88
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
7-SEGMENT Converts the hexadecimal contents of the designated digit(s) into Output 937
DECODER SDEC(078) 8-bit, 7-segment display code and places it into the upper or lower Required
SDEC 8-bits of the specified destination words.
@SDEC
S
078 Di
D Di
Number of digits
S: Source word First digit to convert
Di: Digit
designator
D: 1st destination
word

Rightmost 8 bits (0)

7-segment

DIGITAL SWITCH Reads the value set on an external digital switch (or thumbwheel Output 940
INPUT DSW (210) switch) connected to an Input Unit or Output Unit and stores the 4-digit Required
DSW or 8-digit BCD data in the specified words.
I
210
(CS/CJ-series O
CPU Unit Ver. 2.0
or later only) D
C1
C2
I: Data input word
(D0 to D3)
O: Output word
D: 1st result
word
C1: Number of
digits
C2: System word

TEN KEY INPUT Reads numeric data from a ten-key keypad connected to an Input Unit Output 945
TKY TKY (211) and stores up to 8 digits of BCD data in the specified words. Required
211 I
(CS/CJ-series
CPU Unit Ver. 2.0 D1
or later only)
D2

I: Data input
word
D1: 1st register
word
D2: Key input
word

89
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
HEXADECIMAL Reads numeric data from a hexadecimal keypad connected to an Input Output 948
KEY INPUT HKY (212) Unit and Output Unit and stores up to 8 digits of hexadecimal data in Required
HKY the specified words.
I
212
(CS/CJ-series O
CPU Unit Ver. 2.0
or later only) D
C
I: Data input
word
O: Output word
D: 1st register
word
C: System word

MATRIX INPUT Inputs up to 64 signals from an 8 × 8 matrix connected to an Input Unit Output 953
MTR MTR (213) and Output Unit (using 8 input points and 8 output points) and stores Required
that 64-bit data in the 4 destination words.
213 I
(CS/CJ-series
CPU Unit Ver. 2.0 O
or later only)
D
C
I: Data input
word
O: Output word
D: 1st
destination
word
C: System word

7-SEGMENT DIS- Converts the source data (either 4-digit or 8-digit BCD) to 7-segment Output 957
PLAY OUTPUT 7SEG (214) display data, and outputs that data to the specified output word. Required
7SEG
S
214
(CS/CJ-series O
CPU Unit Ver. 2.0
or later only) C
D
S: 1st source
word
O: Output word
C: Control data
D: System word

90
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
INTELLIGENT I/O Reads the contents of the memory area for the Special I/O Unit Output 962
READ IORD(222) Required
or CPU Bus Unit (see note).
IORD
@IORD C S
222 S S+1
D
Unit number of Special I/O Unit
C: Control data
S: Transfer
source and
number of words Desig-
D: Transfer nated
destination and number
of words
number of words read.

Note: CS/CJ-series CPU Unit Ver. 2.0 or later (including CS1-H, CJ1-H,
and CJ1M CPU Units from lot number 030418 or later) can read
from CPU Bus Units.
INTELLIGENT I/O Outputs the contents of the CPU Unit's I/O memory area to the Output 967
WRITE IOWR(223) Required
Special I/O Unit or the CPU Bus Unit (see note).
IOWR C
@IOWR D
223 S D+1
D
Unit number of Special I/O Unit
C: Control data
S: Transfer
source and
number of words
D: Transfer
destination and
number of words Desig-
nated
number of
words writ-
ten.

Note: CS/CJ-series CPU Unit Ver. 2.0 or later (including CS1-H, CJ1-H,
and CJ1M CPU Units from lot number 030418 or later) can write
to CPU Bus Units.

91
Instruction Functions Section 2-2

2-2-22 Serial Communications Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
PROTOCOL Calls and executes a communications sequence registered in a Serial Output 974
MACRO PMCR(260) Communications Board (CS Series only) or Serial Communications Required
PMCR Unit.
@PMCR C1 CPU Unit Serial Communications Unit
260 C2 Port
S
S
R to
C1: Control word 1
C2: Control word 2
S: 1st send word
R: 1st receive word
R
External
to device

TRANSMIT Outputs the specified number of bytes of data from the RS-232C port Output 983
TXD TXD(236) built into the CPU Unit or the serial port of a Serial Communications Required
@TXD Board (version 1.2 or later).
S
236
C
N
S: 1st source
word
C: Control word
N: Number of
bytes
0000 to 0100 hex
(0 to 256 decimal)

RECEIVE Reads the specified number of bytes of data from the RS-232C port Output 993
RXD RXD(235) built into the CPU Unit or the serial port of a Serial Communications Required
@RXD Board (version 1.2 or later).
D
235
C
N
D: 1st destination
word
C: Control word
N: Number of
bytes to store
0000 to 0100 hex
(0 to 256 decimal)

TRANSMIT VIA Outputs the specified number of bytes of data from the serial port of a Output 1005
SERIAL COMMU- TXDU(256) Serial Communications Unit (version 1.2 or later). The data is output in Required
NICATIONS UNIT no-protocol mode with the start code and end code (if any) specified in
TXDU S the allocated DM Setup Area.
@TXDU C
256
N
S: 1st source word
C: 1st control
word
N: Number of
bytes
0000 to 0256 BCD

92
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
RECEIVE VIA Reads the specified number of bytes of data from the serial port of a Output 1013
SERIAL COMMU- RXDU(255) Serial Communications Unit (version 1.2 or later). The data is read in Required
NICATIONS UNIT no-protocol mode with the start code and end code (if any) specified in
RXDU
D the allocated DM Setup Area.
@RXDU C
255
N
D: 1st destination
word
C: 1st control
word
N: Number of
bytes to store
0000 to 0256 BCD

CHANGE SERIAL Changes the communications parameters of a serial port on the CPU Output 1021
PORT SETUP STUP(237) Unit, Serial Communications Unit (CPU Bus Unit), or Serial Communi- Required
STUP cations Board. STUP(237) thus enables the protocol mode to be
@STUP C changed during PLC operation.
237 S

C: Control word
(port)
S: First source
word

2-2-23 Network Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
NETWORK SEND Transmits data to a node in the network. Output 1044
SEND SEND(090) Required
@SEND S Local node Destination node
090 15 0 15 0
D
S D
C n: No.
of send n
S: 1st source words
word
D: 1st destination
word
C: 1st control
word
NETWORK Requests data to be transmitted from a node in the network and Output 1050
RECEIVE RECV(098) receives the data. Required
RECV S
@RECV
D Local node Source node
098
15 0 15 0
C D S
S: 1st source m n
word
D: 1st destination
word
C: 1st control
word

93
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DELIVER Sends FINS commands and receives the response. Output 1056
COMMAND CMND(490) Required
CMND S Local node Destination node
@CMND
15 0
490 D
S
C Com- Command
mand
S: 1st command data (n Interpret
word (S−1)
bytes)
D: 1st response + n
word 2
C: 1st control
word

15 0
D Response
Re-
sponse Execute
(D−1) data (m
+ m bytes)
2

EXPLICIT MES- Sends an explicit message with any Service Code. Output 1066
SAGE SEND EXPLT (720) Required
EXPLT S
720
(CS/CJ-series D
CPU Unit Ver. 2.0
or later only)
C
S: 1st word of
send
message
D: 1st word of
received
message
C: 1st control
word

EXPLICIT GET Reads status information with an explicit message (Get Attribute Sin- Output 1074
ATTRIBUTE EGATR (721) gle, Service Code: 0E hex). Required
EGATR S
721
(CS/CJ-series D
CPU Unit Ver. 2.0
or later only) C
S: 1st word of
send
message
D: 1st word of
received
message
C: 1st control
word
message

EXPLICIT SET Writes status information with an explicit message Output 1081
ATTRIBUTE ESATR (722) (Set Attribute Single, Service Code: 0E hex) Required
ESATR
S
722
(CS/CJ-series C
CPU Unit Ver. 2.0
or later only) S: First word of
send message
C: First control
word

94
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
EXPLICIT WORD Reads data to the local CPU Unit from a remote CPU Unit in the net- Output 1087
READ ECHRD (723)
work. (The remote CPU Unit must support explicit messages.) Required
ECHRD
723 S
(CS/CJ-series D
CPU Unit Ver. 2.0
or later only) C
S: 1st source
word in remote
CPU Unit
D: 1st destination
word in local
CPU Unit
C: 1st control
word

EXPLICIT WORD Writes data from the local CPU Unit to a remote CPU Unit in the net- Output 1091
WRITE work. (The remote CPU Unit must support explicit messages.) Required
ECHWR ECHWR (724)
724
S
(CS/CJ-series
CPU Unit Ver. 2.0 D
or later only)
C
S: 1st source
word in local
CPU Unit
D: 1st destination
word in remote
CPU Unit
C: 1st control
word

95
Instruction Functions Section 2-2

2-2-24 File Memory Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
READ DATA FILE Reads the specified data or amount of data from the specified data file Output 1099
FREAD FREAD(700) in file memory to the specified data area in the CPU Unit. Required
@FREAD
C
700 Starting read ad-
S1 dress specified in File specified
S2 S1+2 and S1+3 in S2 CPU Unit

D
C: Control word Number of
S1: 1st source words specified
word in S1 and S1+1
S2: Filename
D: 1st destination
word Memory Card or Number
EM file memory of words
written to
(Specified by the D and
4th digit of C.) D+1.
File specified
in S2 CPU Unit

Number of
words

Memory Card or EM file memory

(Specified by the 4th digit of C.)

96
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
WRITE DATA Overwrites or appends data in the specified data file in file memory Output 1106
FILE FWRIT(701) Required
with the specified data from the data area in the CPU Unit. If the
FWRIT C specified file doesn't exist, a new file is created with that filename.
@FWRIT
701 D1 CPU Unit Starting word File specified in D2
specified in
Starting D1+2 and
D2 address D1+3
S specified
Number of words
in S specified in D1
C: Control word and D1+1
D1: 1st
destination word Overwrite
D2: Filename
S: 1st source Memory Card or EM file memory
word (Specified by the 4th digit of C.)

CPU Unit
File specified in D2
Starting End of
file Existing
address data
specified
Number of words
in S specified in D1
and D1+1

Append
Memory Card or EM file memory
(Specified by the 4th digit of C.)
Beginning
of file File speci-
CPU Unit New file created
fied in D2
Starting
address
specified Number of words
in S specified in D1
and D1+1

Memory Card or EM file memory

(Specified by the 4th digit of C.)

WRITE TEXT Reads ASCII data from I/O memory and stores that data in the Memory Output 1113
FILE TWRIT Card as a text file (writing a new file or appending a file). The data is Required
TWRIT stored in the TXT format.
C
@TWRIT
704 S1
(CS/CJ-series S2
CPU Units with
unit version 4.0 or S3
later only)
S4
C: Control word
S1: Number of
bytes to write
S2: Directory and
file name
S3: Write data
S4: Delimiter

97
Instruction Functions Section 2-2

2-2-25 Display Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
DISPLAY Reads the specified sixteen words of extended ASCII and displays the Output 1119
MESSAGE MSG(046) message on a Peripheral Device such as a Programming Console. Required
MSG N
@MSG
046 M
N: Message
number
M: 1st message
word

2-2-26 Clock Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
CALENDAR ADD Adds time to the calendar data in the specified words. Output 1122
CADD CADD(730) Required
@CADD C
730 C Minutes Seconds
T C+1 Day Hour
R C+2 Year Month

C: 1st calendar
word
T: 1st time word
T Minutes Seconds
R: 1st result word
T+1 Hours

R Minutes Seconds
R+1 Day Hour
R+2 Year Month

CALENDAR Subtracts time from the calendar data in the specified words. Output 1126
SUBTRACT CSUB(731) Required
CSUB C
@CSUB C Minutes Seconds
731 T C+1 Day Hour
R C+2 Year Month
−
C: 1st calendar
word
T: 1st time word T
R: 1st result word Minutes Seconds
T+1 Hours

R Minutes Seconds
R+1 Day Hour
R+2 Year Month

98
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
HOURS TO Converts time data in hours/minutes/seconds format to an equivalent Output 1129
SECONDS SEC(065) time in seconds only. Required
SEC S
@SEC
065 D
Minutes Seconds
S: 1st source Hours
word
D: 1st destination
word

Seconds

SECONDS TO Output 1131

HOURS HMS(066) Converts seconds data to an equivalent time in hours/minutes/
seconds format. Required
HMS S
@HMS
066 D
S: 1st source Seconds
word
D: 1st destination
word

Minutes Seconds
Hours

CLOCK Changes the internal clock setting to the setting in the specified Output 1134
ADJUSTMENT DATE(735) source words. Required
DATE S
@DATE CPU Unit
735 S: 1st source
word
Internal clock

Minutes Seconds
New
setting Day Hour
Year Month
00 Day of week

2-2-27 Debugging Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
TRACE When TRSM(045) is executed, the status of a preselected bit or word Output 1136
MEMORY TRSM(045) is sampled and stored in Trace Memory. TRSM(045) can be used any- Not required
SAMPLING where in the program, any number of times.
TRSM
045

99
Instruction Functions Section 2-2

2-2-28 Failure Diagnosis Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
FAILURE ALARM Output 1140
FAL(006) Generates or clears user-defined non-fatal errors. Non-fatal errors
FAL do not stop PC operation. Required
@FAL N Also generates non-fatal errors with the system.
006 FAL Error Flag ON
S Execution of Corresponding Executed FAL
N: FAL number FAL(006) Number Flag ON
S: 1st message generates a Error code written to A400
non-fatal error Error code and time written to Error
word or error Log Area
code to gener- with FAL
ate number N.
ERR Indicator flashes

Message
displayed on
Programming
Console
SEVERE Generates user-defined fatal errors. Fatal errors stop PC operation. Output 1148
FAILURE ALARM FALS(007) Required
Also generates fatal errors with the system.
FALS N FALS Error Flag ON
007 Execution of
S Error code written to A400
FALS(007) Error code and time/date written to
generates a Error Log Area
N: FALS number
fatal error
S: 1st message with FALS
word or error number N. ERR Indicator lit
code to gener-
ate
Message displayed
on Programming
Console

FAILURE POINT Diagnoses a failure in an instruction block by monitoring the time Output 1156
DETECTION FPD(269) Required
between execution of FPD(269) and execution of a diagnostic output
FPD C and finding which input is preventing an output from being turned ON.
269
T Time monitoring function:
Starts timing when execution condition A goes
R ON. Generates a non-fatal error if output B
isn't turned ON within the monitoring time.
C: Control word
T: Monitoring time
R: 1st register Execution
word condition A

T Error-pro-
cessing
R block (op-
tional)
Next instruction block

Logic diagnosis block*

Logic diagnosis
execution condition C

Diagnostic output B

Logic diagnosis function

Determines which input in C
prevents output B from going ON.

100
Instruction Functions Section 2-2

2-2-29 Other Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
SET CARRY Sets the Carry Flag (CY). Output 1166
STC STC(040) Required
@STC
040
CLEAR CARRY Turns OFF the Carry Flag (CY). Output 1166
CLC CLC(041) Required
@CLC
041
SELECT EM Changes the current EM bank. Output 1167
BANK EMBC(281) Required
EMBC
@EMBC N
281 N: EM bank
number
EXTEND Extends the maximum cycle time, but only for the cycle in which this Output 1169
MAXIMUM WDT(094) instruction is executed. Required
CYCLE TIME
WDT
T
@WDT
T: Timer setting
094
SAVE CONDI- Saves the status of the condition flags. Output 1171
TION FLAGS CCS(282) Required
(CS1-H, CJ1-H,
CJ1M, or CS1D
only)
CCS
@CCS
282
LOAD CONDI- Reads the status of the condition flags that was saved. Output 1173
TION FLAGS CCL(283) Required
(CS1-H, CJ1-H,
CJ1M, or CS1D
only)
CCL
@CCL
283
CONVERT Converts a CV-series PLC memory address to its equivalent CS/CJ- Output 1174
ADDRESS FROM FRMCV(284) series PLC memory address. Required
CV (CS1-H, CJ1-
H, CJ1M, or S
CS1D only)
D
FRMCV
@FRMCV S: Word contain-
284 ing CV-series
memory address
D: Destination
Index Register

CONVERT Converts a CS/CJ-series PLC memory address to its equivalent CV- Output 1179
ADDRESS TO CV TOCV(285) series PLC memory address. Required
(CS1-H, CJ1-H,
CJ1M, or CS1D S
only) D
TOCV
@TOCV
S: Index Register
285 containing CS-
series memory
address
D: Destination
word

101
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
DISABLE Disables peripheral servicing during program execution in one of the Output 1183
PERIPHERAL IOSP(287) Parallel Processing Modes or Peripheral Servicing Priority Mode. Required
SERVICING
(CS1D CPU Units
for Single-CPU
Systems, CS1-H,
CJ1-H, or CJ1M
only)
IOSP
@IOSP
287
ENABLE Enables peripheral servicing that was disabled by IOSP(287) for pro- Output 1185
PERIPHERAL IORS(288) gram execution in one of the Parallel Processing Modes or Peripheral Not required
SERVICING Servicing Priority Mode.
(CS1D CPU Unit
for Single-CPU
Systems, CS1-H,
CJ1-H, or CJ1M
only)
IORS
288

2-2-30 Block Programming Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
BLOCK Define a block programming area. For every BPRG(096) there must Output 1191
PROGRAM BPRG(096) Required
be a corresponding BEND(801).
BEGIN
BPRG N
096 N: Block program
number
Block program

Executed when the execu-

tion condition is ON.

BLOCK Define a block programming area. For every BPRG(096) there must be Block program 1191
PROGRAM END a corresponding BEND(801). Required
BEND
801
BLOCK BPPS Pause and restart the specified block program from another block Block program 1193
PROGRAM (811) program. Required
PAUSE
BPPS N
811 N: Block program
number
to

to BPPS(811) executed
for block program n.

to Block program n. Once

paused this block program
will not be executed even
if bit "a" is ON.

102
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
BLOCK BPRS Pause and restart the specified block program from another block Block program 1193
PROGRAM (812) program. Required
RESTART
BPRS N
812
N: Block program
number
to

to BPRS(812) executed
for block program n.

Block program n. This block

to
program will now be executed
as long as bit "a" is ON.

CONDITIONAL EXIT(806) EXIT(806) without an operand bit exits the program if the execution Block program 1199
BLOCK EXIT condition is ON. Required
EXIT B: Bit operand
Execution Execution
806 condition condition
OFF ON

"A" executed. "A" executed.

Execution condition

"B" executed.

Block ended.

CONDITIONAL EXIT(806)B EXIT(806) without an operand bit exits the program if the execution Block program 1199
BLOCK EXIT condition is ON. Required
EXIT B: Bit operand
Operand bit Operand bit
806 OFF ON
(ON for (OFF for EXIT
EXIT NOT) NOT)

"A" executed. "A" executed.

"B" executed.

Block ended.

CONDITIONAL EXIT NOT(806) EXIT(806) without an operand bit exits the program if the execution Block program 1199
BLOCK EXIT B condition is OFF. Required
NOT
EXIT NOT B: Bit operand
806

103
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
CONDITIONAL IF (802) If the execution condition is ON, the instructions between IF(802) and Block program 1196
BLOCK ELSE(803) will be executed and if the execution condition is OFF, the Required
BRANCHING instructions between ELSE(803) and IEND(804) will be executed.
IF
802 Execution
Execution
condition condition ON?

"A" executed (be- "B" executed

tween IF and ELSE). (after ELSE).

CONDITIONAL IF (802) Block program 1196

BLOCK If the operand bit is ON, the instructions between IF(802) and
B ELSE(803) will be executed. If the operand bit is OFF, the instructions Required
BRANCHING
between ELSE(803) and IEND(804) will be executed.
IF
B: Bit operand
802
Operand bit
ON?
IF R (IF NOT R)

"A" executed "B" executed

(between IF and
ELSE). (after ELSE).

CONDITIONAL IF (802) NOT The instructions between IF(802) and ELSE(803) will be executed and Block program 1196
BLOCK B if the operand bit is ON, the instructions be ELSE(803) and IEND(804) Required
BRANCHING will be executed is the operand bit is OFF.
(NOT)
IF NOT B: Bit operand
802
CONDITIONAL --- If the ELSE(803) instruction is omitted and the operand bit is ON, the Block program 1196
BLOCK instructions between IF(802) and IEND(804) will be executed Required
BRANCHING
(ELSE)
ELSE
803
CONDITIONAL --- If the operand bit is OFF, only the instructions after IEND(804) will be Block program 1196
BLOCK executed. Required
BRANCHING
END
IEND
804

104
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
ONE CYCLE AND WAIT(805) If the execution condition is ON for WAIT(805), the rest of the Block program 1202
WAIT instruction in the block program will be skipped. Required
WAIT Execution Execution Execution
805 condition condition condition
OFF OFF ON

"A"
executed.

Execution "B" executed.

condition

"C" "C" "C" executed.

executed. executed.

Wait

ONE CYCLE AND WAIT(805) If the operand bit is OFF (ON for WAIT NOT(805)), the rest of the Block program 1202
WAIT B instructions in the block program will be skipped. In the next cycle, Required
WAIT none of the block program will be executed except for the execution
805 B: Bit operand condition for WAIT(805) or WAIT(805) NOT. When the execution condi-
tion goes ON (OFF for WAIT(805) NOT), the instruction from
WAIT(805) or WAIT(805) NOT to the end of the program will be exe-
cuted.
ONE CYCLE AND WAIT(805) NOT If the operand bit is OFF (ON for WAIT NOT(805)), the rest of the Block program 1202
WAIT (NOT) B instructions in the block program will be skipped. In the next cycle, Required
WAIT NOT none of the block program will be executed except for the execution
condition for WAIT(805) or WAIT(805) NOT. When the execution condi-
805 B: Bit operand
tion goes ON (OFF for WAIT(805) NOT), the instruction from
WAIT(805) or WAIT(805) NOT to the end of the program will be exe-
cuted.
HUNDRED-MS TIMW(813) Delays execution of the block program until the specified time has Block program 1206
TIMER WAIT N elapsed. Execution continues from the next instruction after Required
TIMW SV TIMW(813)/TIMWX(816) when the timer times out.
813 SV: 0 to 999.9 s for BCD and
(BCD)
N: Timer number 0 to 6,553.5 s for binary
SV: Set value
TIMWX
816 TIMWX(816) "A"
(Binary) N executed.
(CS1-H, CJ1-H, SV
CJ1M, or CS1D
only)
N: Timer number SV
SV: Set value preset. Time elapsed.

"B" executed.

BEND
"C" executed.
C

105
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
COUNTER WAIT CNTW(814) Delays execution of the rest of the block program until the specified count Block program 1209
CNTW N has been achieved. Execution will be continued from the next instruction Required
814 SV after CNTW(814)/CNTWX(818) when the counter counts out.
(BCD) SV: 0 to 9,999 times for BCD and
0 to 65,535 times for binary
CNTWX N: Counter
818 number
(Binary) SV: Set value
(CS1-H, CJ1-H, "A"
CJ1M, or CS1D I: Count input executed.
only) CNTWX(818)
N
SV SV
preset. Time elapsed.

N: Counter "B" executed.

number
SV: Set value
I: Count input "C" executed.
"C" "C"
C executed. executed.

TEN-MS TIMER TMHW(815) Delays execution of the rest of the block program until the specified Block program 1212
WAIT N time has elapsed. Execution will be continued from the next Required
TMHW SV instruction after TMHW(815)/TMHWX(818) when the timer times out.
815 SV: 0 to 99.99 s for BCD
(BCD)
N: Timer number and 0 to 655.35 s for binary
SV: Set value
TMHWX
817 TMHWX(817) "A"
(Binary) N executed.
(CS1-H, CJ1-H, SV
CJ1M, or CS1D
only)
N: Timer number SV
SV: Set value preset. Time elapsed.

"B" executed.

BEND
"C" executed.
C

106
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
LOOP --- Block program 1215
LOOP(809) designates the beginning of the loop program.
LOOP Required
809
Execution Execution Execution Execution
condition condition condition condition
ON OFF OFF OFF

Execution condition

Loop repeated

LEND LEND (810) LEND(810) or LEND(810) NOT specifies the end of the loop. When Block program 1215
LEND LEND(810) or LEND(810) NOT is reached, program execution will loop Required
back to the next previous LOOP(809) until the operand bit for
810 LEND(810) or LEND(810) NOT turns ON or OFF (respectively) or until
the execution condition for LEND(810) turns ON.
LEND LEND (810) If the operand bit is OFF for LEND(810) (or ON for LEND(810) NOT), Block program 1215
LEND B execution of the loop is repeated starting with the next instruction after Required
810 LOOP(809). If the operand bit is ON for LEND(810) (or OFF for
B: Bit operand LEND(810) NOT), the loop is ended and execution continues to the
next instruction after LEND(810) or LEND(810) NOT.
Operand Operand Operand Operand
bit ON bit OFF bit OFF bit OFF

Loop repeated

Note The status of the operand bit would be

reversed for LEND(810) NOT.

LEND NOT LEND(810) NOT LEND(810) or LEND(810) NOT specifies the end of the loop. When Block program 1215
LEND NOT LEND(810) or LEND(810) NOT is reached, program execution will loop Required
back to the next previous LOOP(809) until the operand bit for
810 B: Bit operand LEND(810) or LEND(810) NOT turns ON or OFF (respectively) or until
the execution condition for LEND(810) turns ON.

107
Instruction Functions Section 2-2

2-2-31 Text String Processing Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
MOV STRING Output 1221
MOV$(664) Transfers a text string.
MOV$ Required
@MOV$ S
664
D
S: 1st source
word
D: 1st destination
word

CONCATENATE Links one text string to another text string. Output 1223
STRING +$(656) Required
+$ → → → →
@+$ S1 +
656 S2
D
S1: Text string 1
S2: Text string 2
D: First
destination word

GET STRING Fetches a designated number of characters from the left (beginning) Output 1226
LEFT LEFT$(652) Required
of a text string.
LEFT$ S1
@LEFT$
652 S2
D
S1: Text string
first word
S2: Number of
characters
D: First
destination word

GET STRING Reads a designated number of characters from the right (end) of a Output 1228
RIGHT RGHT$(653) Required
text string.
RGHT$
@RGHT$ S1
00
653 S2
D
S1: Text string
first word
S2: Number of
characters
D: First
destination word

GET STRING Reads a designated number of characters from any position in the Output 1230
MIDDLE MID$(654) middle of a text string. Required
MID$
@MID$ S1
654 S2
→ →
S3
D
S1: Text string
first word
S2: Number of
characters
S3: Beginning
position
D: First
destination word

108
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
FIND IN STRING Finds a designated text string from within a text string. Output 1233
FIND FIND$(660) Required
@FIND$ Found data
S1 → → →
660
S2
D
S1: Source text
string first word
S2: Found text
string first word
D: First
destination word
STRING LENGTH Calculates the length of a text string. Output 1235
LEN$ LEN$(650) Required
@LEN$ S → 1 2
650 3 4
D 5

S: Text string first

word
D: 1st destination
word
REPLACE IN Output 1237
STRING RPLC$(654)
Replaces a text string with a designated text string from a designated
position. Required
RPLC$
@RPLC$ S1
661 S2
→ →
S3
S4
D
S1: Text string
first word
S2: Replacement
text string first
word
S3: Number of
characters
S4: Beginning
position
D: First
destination word

DELETE STRING Deletes a designated text string from the middle of a text string. Output 1240
DEL$ DEL$(658) Required
@DEL$ Number of characters to be
S1 deleted (designated by S2).
658
→ →
S2
S3
G
D
S1: Text string
first word
S2: Number of
characters
S3: Beginning
position
D: First
destination word

109
Instruction Functions Section 2-2

Instruction Symbol/Operand Function Location Page

Mnemonic Execution
Code condition
EXCHANGE Replaces a designated text string with another designated text string. Output 1242
STRING XCHG$(665)
Required
XCHG$ Ex1 Ex1
@XCHG$ Ex1
665 Ex2
Ex1: 1st Ex2 Ex2
exchange word 1
Ex2: 1st
exchange word 2
CLEAR STRING Clears an entire text string with NUL (00 hex). Output 1245
CLR$ CLR$(666) Required
@CLR$ S S→ A B S→
666 C D
NUL NUL
S: Text string first
word

INSERT INTO Deletes a designated text string from the middle of a text string. Output 1246
STRING INS$(657) Required
INS$ →
@INS$ S1
NUL
657 S2
→ →
S3
Inserted
D characters
S1: Base text
string first word
S2: Inserted text
string first word
S3: Beginning
position
D: First
destination word

String Compari- Sting comparison instructions (=$, <>$, <$, <=$, >$, >=$) compare two 1250
son LD text strings from the beginning, in terms of value of the ASCII codes. If LD: Not
LD, AND, OR + Symbol the result of the comparison is true, an ON execution condition is cre- required
=$, <>$, <$, <=$, ated for a LOAD, AND, or OR. AND, OR:
>$, >=$ S1 Required
670 (=$) S2
671 (<>$)
672 (<$)
673 (<=$) AND
674 (>$) Symbol
675 (>=$)
S1
S2

OR
Symbol
S1
S2
S1: Text string 1
S2: Text string 2

110
Instruction Functions Section 2-2

2-2-32 Task Control Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
TASK ON Output 1255
TKON(820) Makes the specified task executable.
TKON Required
@TKON N The specified task's task number The specified task's task number
820 is higher than the local task's is lower than the local task's task
N: Task number task number (m<n). number (m>n).

Task m Task m

Be-
comes
Becomes execut-
execut- able in
able in that the next
cycle. cycle.

Task n Task n

TASK OFF Puts the specified task into standby status. Output 1258
TKOF TKOF(821) Required
@TKOF The specified task's task num- The specified task's task num-
N ber is higher than the local ber is lower than the local
821
N: Task number task's task number (m<n). task's task number (m>n).

Task m Task m

In stand- In stand-
by status by status
that the next
cycle. cycle.

Task n Task n

111
Instruction Functions Section 2-2

2-2-33 Model Conversion Instructions (CPU Unit Ver. 3.0 or Later Only)
Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
BLOCK Output 1263
TRANSFER Transfers the specified number of consecutive words.
XFERC(565) Required
XFERC
@XFERC N
565 S N words
to to
D S+(N−1) D+(N−1)

N: Number of
words
S: 1st source
word
D: 1st destination
word
SINGLE WORD Output 1266
DISTRIBUTE DISTC(566) Transfers the source word to a destination word calculated by adding
an offset value to the base address. Can also write to a stack (Stack Required
DISTC S Push Operation).
@DISTC
566 Bs S Bs Of
Of

S: Source word
Bs: Destination
base address
Of: Offset
Bs+n
DATA COLLECT Output 1269
COLLC(567) Transfers the source word (calculated by adding an offset value to the
COLLC base address) to the destination word. Can also read data from a Required
@COLLC Bs stack in FIFO or LIFO order (Stack Read Operation).
567
Of Bs Of
D

Bs: Source base

address Bs+n
Of: Offset
D: Destination
word

MOVE BIT Transfers the specified bit. Output 1273

MOVBC MOVBC(568) Required
@MOVBC S
568
C
D
S: Source word or
data
C: Control word
D: Destination
word

BIT COUNTER Output 1275

BCNTC(621) Counts the total number of ON bits in the specified word(s).
BCNTC Required
@BCNTC N
621 N words
S Counts the number
to of ON bits.
R
S+(N −1) BCD result
N: Number of
words (BCD)
S: 1st source R
word
R: Result word

112
Instruction Functions Section 2-2

2-2-34 Special Function Block Instructions

Instruction Symbol/Operand Function Location Page
Mnemonic Execution
Code condition
GET VARIABLE Outputs the FINS command variable type (data area) code and word Output 1277
ID GETID(286) address for the specified variable or address. This instruction is gener- Required
GETID ally used to get the assigned address of a variable in a function block.
@GETID
S
286 D1
D2
S: Variable or
address
D1: ID code
D2: Destination
word

113
Alphabetical List of Instructions by Mnemonic Section 2-3

2-3 Alphabetical List of Instructions by Mnemonic

A
Mnemonic Instruction Function code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
ACC ACCELERATION CON- 888 @ACC --- --- 896
TROL
ACOS ARC COSINE 464 @ACOS --- --- 625
ACOSD DOUBLE ARC 855 @ACOSD --- --- 682
COSINE
AND AND --- @AND %AND !AND 165
AND < AND LESS THAN 310 --- --- --- 291
AND <$ AND STRING LESS 672 --- --- --- 1250
THAN
AND <> AND NOT EQUAL 305 --- --- --- 291
AND <>$ AND STRING NOT 671 --- --- --- 1250
EQUAL
AND <>D AND DOUBLE FLOAT- 336 --- --- --- 694
ING NOT EQUAL
AND <> DT AND TIME NOT 342 --- --- --- 297
EQUAL
AND <>F AND FLOATING NOT 330 --- --- --- 636
EQUAL
AND <>L AND DOUBLE NOT 306 --- --- --- 291
EQUAL
AND <>S AND SIGNED NOT 307 --- --- --- 291
EQUAL
AND <>SL AND DOUBLE 308 --- --- --- 291
SIGNED NOT EQUAL
AND <D AND DOUBLE FLOAT- 337 --- --- --- 694
ING LESS THAN
AND <DT AND TIME LESS 343 --- --- --- 297
THAN
AND <F AND FLOATING LESS 331 --- --- --- 636
THAN
AND <L AND DOUBLE LESS 311 --- --- --- 291
THAN
AND <S AND SIGNED LESS 312 --- --- --- 291
THAN
AND <SL AND DOUBLE 313 --- --- --- 291
SIGNED LESS THAN
AND = AND EQUAL 300 --- --- --- 291
AND =$ AND STRING EQUALS 670 --- --- --- 1250
AND =D AND DOUBLE FLOAT- 335 --- --- --- 694
ING EQUAL
AND =DT AND TIME EQUAL 341 --- --- --- 297
AND =F AND FLOATING 329 --- --- --- 636
EQUAL
AND =L AND DOUBLE EQUAL 301 --- --- --- 291
AND =S AND SIGNED EQUAL 302 --- --- --- 291
AND =SL AND DOUBLE 303 --- --- --- 291
SIGNED EQUAL
AND > AND GREATER THAN 320 --- --- --- 291
AND >$ AND STRING 674 --- --- --- 1250
GREATER THAN
AND >D AND DOUBLE FLOAT- 339 --- --- --- 694
ING GREATER THAN
AND >DT AND TIME GREATER 345 --- --- --- 297
THAN
AND >F AND FLOATING 333 --- --- --- 636
GREATER THAN

114
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction Function code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
AND >L AND DOUBLE 321 --- --- --- 291
GREATER THAN
AND >S AND SIGNED 322 --- --- --- 291
GREATER THAN
AND >SL AND DOUBLE 323 --- --- --- 291
SIGNED GREATER
THAN
AND LD AND LOAD --- --- --- --- 172
AND NOT AND NOT --- --- --- !AND NOT 167
AND TST AND BIT TEST 350 --- --- --- 182
AND TSTN AND BIT TEST 351 --- --- --- 182
AND <= AND LESS THAN OR 315 --- --- --- 291
EQUAL
AND <=$ AND STRING LESS 673 --- --- --- 1250
THAN OR EQUAL
AND <=D AND DOUBLE FLOAT- 338 --- --- --- 694
ING LESS THAN OR
EQUAL
AND <=DT AND TIME LESS 344 --- --- --- 297
THAN OR EQUAL
AND <=F AND FLOATING LESS 332 --- --- --- 636
THAN OR EQUAL
AND <=L AND DOUBLE LESS 316 --- --- --- 291
THAN OR EQUAL
AND <=S AND SIGNED LESS 317 --- --- --- 291
THAN OR EQUAL
AND <=SL AND DOUBLE 318 --- --- --- 291
SIGNED LESS THAN
OR EQUAL
AND >= AND GREATER THAN 325 --- --- --- 291
OR EQUAL
AND >=$ AND STRING 675 --- --- --- 1250
GREATER THAN OR
EQUALS
AND >=D AND DOUBLE FLOAT- 340 --- --- --- 694
ING GREATER THAN
OR EQUAL
AND >=DT AND TIME GREATER 346 --- --- --- 297
THAN OR EQUAL
AND >=F AND FLOATING 334 --- --- --- 636
GREATER THAN OR
EQUAL
AND >=L AND DOUBLE 326 --- --- --- 291
GREATER THAN OR
EQUAL
AND >=S AND SIGNED 327 --- --- --- 291
GREATER THAN OR
EQUAL
AND >=SL AND DOUBLE 328 --- --- --- 291
SIGNED GREATER
THAN OR EQUAL
ANDL DOUBLE LOGICAL 610 @ANDL --- --- 550
AND
ANDW LOGICAL AND 034 @ANDW --- --- 548
APR ARITHMETIC 069 @APR --- --- 571
PROCESS
ASC ASCII CONVERT 086 @ASC --- --- 504
ASFT ASYNCHRONOUS 017 @ASFT --- --- 365
SHIFT REGISTER
ASIN ARC SINE 463 @ASIN --- --- 623
ASIND DOUBLE ARC SINE 854 @ASIND --- --- 680
ASL ARITHMETIC SHIFT 025 @ASL --- --- 370
LEFT

115
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction Function code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
ASLL DOUBLE SHIFT LEFT 570 @ASLL --- --- 371
ASR ARITHMETIC SHIFT 026 @ASR --- --- 373
RIGHT
ASRL DOUBLE SHIFT 571 @ASRL --- --- 374
RIGHT
ATAN ARC TANGENT 465 @ATAN --- --- 627
ATAND DOUBLE ARC TAN- 856 @ATAND --- --- 684
GENT
AVG AVERAGE 195 --- --- --- 807

B
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
BAND DEAD BAND CON- 681 @BAND --- --- 781
TROL
BCD BINARY TO BCD 024 @BCD --- --- 487
BCDL DOUBLE BINARY TO 059 @BCDL --- --- 489
BCD
BCDS SIGNED BINARY TO 471 @BCDS --- --- 523
BCD
BCMP UNSIGNED BLOCK 068 @BCMP --- --- 320
COMPARE
BCMP2 EXPANDED BLOCK 502 @BCMP2 --- --- 322
COMPARE
BCNT BIT COUNTER 067 @BCNT --- --- 587
BCNTC BIT COUNTER 621 @BCNTC --- --- 1275
BDSL DOUBLE SIGNED 473 @BDSL --- --- 525
BINARY TO BCD
BEND BLOCK PROGRAM 801 --- --- --- 1191
END
BIN BCD TO BINARY 023 @BIN --- --- 483
BINL DOUBLE BCD TO 058 @BINL --- --- 485
DOUBLE BINARY
BINS SIGNED BCD TO 470 @BINS --- --- 517
BINARY
BISL DOUBLE SIGNED 472 @BISL --- --- 520
BCD TO BINARY
BPPS BLOCK PROGRAM 811 --- --- --- 1193
PAUSE
BPRG BLOCK PROGRAM 096 --- --- --- 1191
BEGIN
BPRS BLOCK PROGRAM 812 --- --- --- 1193
RESTART
BREAK BREAK LOOP 514 --- --- --- 241
BSET BLOCK SET 071 @BSET --- --- 347

C
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
CADD CALENDAR ADD 730 @CADD --- --- 1122
CCL LOAD CONDITION 283 @CCL --- --- 1173
FLAGS
CCS SAVE CONDITION 282 @CCS --- --- 1171
FLAGS
CJP CONDITIONAL JUMP 510 --- --- --- 232
CJPN CONDITIONAL JUMP 511 --- --- --- 232
CLC CLEAR CARRY 041 @CLC --- --- 1166

116
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
CLI CLEAR INTERRUPT 691 @CLI --- --- 851
CLR$ CLEAR STRING 666 @CLR$ --- --- 1245
CMND DELIVER COMMAND 490 @CMND --- --- 1056
CMP COMPARE 020 --- --- !CMP 303
CMPL DOUBLE COMPARE 060 --- --- --- 306
CNR RESET TIMER/ 545 @CNR --- --- 282
COUNTER
CNRX RESET TIMER/ 548 @CNRX --- --- 282
COUNTER
CNT COUNTER --- --- --- --- 275
CNTX COUNTER 546 --- --- --- 275
CNTR REVERSIBLE 012 --- --- --- 278
COUNTER
CNTRX REVERSIBLE 548 --- --- --- 278
COUNTER
CNTW COUNTER WAIT 814 --- --- --- 1209
CNTWX COUNTER WAIT 818 --- --- --- 1209
COLL DATA COLLECT 081 @COLL --- --- 354
COLLC DATA COLLECT 567 @COLLC --- --- 1269
COLM LINE TO COLUMN 064 @COLM --- --- 514
COM COMPLEMENT 029 --- --- --- 562
COML DOUBLE 614 @COML --- --- 564
COMPLEMENT
COS COSINE 461 @COS --- --- 615
COSD DOUBLE COSINE 852 @COSD --- --- 676
COSQ HIGH-SPEED COSINE 476 @COSQ --- --- 617
CPS SIGNED BINARY 114 --- --- !CPS 309
COMPARE
CPSL DOUBLE SIGNED 115 --- --- --- 312
BINARY COMPARE
CSUB CALENDAR 731 @CSUB --- --- 1126
SUBTRACT
CTBL COMPARISON TABLE 882 @CTBL --- --- 878
LOAD

D
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
DATE CLOCK ADJUSTMENT 735 @DATE --- --- 1134
DBL 16-BIT BINARY TO 843 @DBL --- --- 660
DOUBLE FLOATING
DBLL 32-BIT BINARY TO 844 @DBLL --- --- 661
DOUBLE FLOATING
DEG RADIANS-TO 459 @DEG --- --- 610
DEGREES
DEGD DOUBLE RADIANS TO 850 @RADD --- --- 671
DEGREES
DEL$ DELETE STRING 658 @DEL$ --- --- 1240
DI DISABLE INTER- 693 @DI --- --- 855
RUPTS
DIFD DIFFERENTIATE 014 --- --- !DIFD 193
DOWN
DIFU DIFFERENTIATE UP 013 --- --- !DIFU 193
DIM DIMENSION RECORD 631 @DIM --- --- 715
TABLE
DIST SINGLE WORD 080 @DIST --- --- 352
DISTRIBUTE

117
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
DISTC SINGLE WORD 566 @DISTC --- --- 1266
DISTRIBUTE
DLNK CPU BUS UNIT I/O 226 @DLNK --- --- 932
REFRESH
DMPX DATA ENCODER 077 @DMPX --- --- 500
DOWN CONDITION OFF 522 --- --- --- 181
DSW DIGITAL SWITCH 210 --- --- --- 940
INPUT

E
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
ECHRD EXPLICIT WORD 723 @ECHRD --- --- 1087
READ
ECHWR EXPLICIT WORD 724 @ECHWR --- --- 1091
WRITE
EGATR EXPLICIT GET 721 @EGATR --- --- 1074
ATTRIBUTE
EI ENABLE 694 --- --- --- 858
INTERRUPTS
ELSE ELSE 803 --- --- --- 1196
EMBC SELECT EM BANK 281 @EMBC --- --- 1167
END END 001 --- --- --- 206
ESATR EXPLICIT SET 722 @ESATR --- --- 1081
ATTRIBUTE
EXIT NOT CONDITIONAL BLOCK 806 --- --- --- 1199
(operand) EXIT NOT
EXIT (input con- CONDITIONAL BLOCK 806 --- --- --- 1199
dition) EXIT
EXIT (operand) CONDITIONAL BLOCK 806 --- --- --- 1199
EXIT
EXP EXPONENT 467 @EXP --- --- 631
EXPD DOUBLE EXPONENT 858 @EXPD --- --- 688
EXPLT EXPLICIT MESSAGE 720 @EXPLT --- --- 1066
SEND

F
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
FAL FAILURE ALARM 006 @FAL --- --- 1140
FALS SEVERE FAILURE 007 --- --- --- 1148
ALARM
FCS FRAME CHECKSUM 180 @FCS --- --- 738
FDIV FLOATING POINT 079 @FDIV --- --- 583
DIVIDE
FIFO FIRST IN FIRST OUT 633 @FIFO --- --- 709
FIND$ FIND IN STRING 660 @FIND$ --- --- 1233
FIORF SPECIAL I/O UNIT I/O 225 @FIORF --- --- 929
REFRESH
FIX FLOATING TO 16-BIT 450 @FIX --- --- 594
FIXD DOUBLE FLOATING 841 @FIXD --- --- 657
TO 16-BIT BINARY
FIXL FLOATING TO 32-BIT 451 @FIXL --- --- 596
FIXLD DOUBLE FLOATING 842 @FIXLD --- --- 658
TO 32-BIT BINARY
FLT 16-BIT TO FLOATING 452 @FLT --- --- 597
FLTL 32-BIT TO FLOATING 453 @FLTL --- --- 599

118
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
FOR FOR-NEXT LOOPS 512 --- --- --- 238
FPD FAILURE POINT 269 --- --- --- 1156
DETECTION
FREAD READ DATA FILE 700 @FREAD --- --- 1099
FRMCV CONVERT ADDRESS 284 @FRMCV --- --- 1174
FROM CV
FSTR FLOATING POINT TO 448 @FSTR --- --- 640
ASCII
FWRIT WRITE DATA FILE 701 @FWRIT --- --- 1106
FVAL ASCII TO FLOATING 449 @FVAL --- --- 645
POINT

G
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
GETID GET VARIABLE ID 286 @GETID --- --- 1277
GETR GET RECORD 636 @GETR --- --- 720
NUMBER
GRET GLOBAL SUBROU- 752 --- --- --- 835
TINE RETURN
GRY GRAY CODE CON- 474 @GRY --- --- 529
VERSION
GSBN GLOBAL SUBROU- 751 --- --- --- 832
TINE ENTRY
GSBS GLOBAL SUBROU- 750 @GSBS --- --- 824
TINE CALL

H
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
HEX ASCII TO HEX 162 @HEX --- --- 508
HKY HEXADECIMAL KEY 212 --- --- --- 948
INPUT
HMS SECONDS TO HOURS 066 @HMS --- --- 1131

I
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
IEND IF END 804 --- --- --- 1196
IF NOT (oper- IF NOT 802 --- --- --- 1196
and)
IF (input condi- IF 802 --- --- --- 1196
tion)
IF (operand) IF 802 --- --- --- 1196
IL INTERLOCK 002 --- --- --- 210
ILC INTERLOCK CLEAR 003 --- --- --- 210
INI MODE CONTROL 880 @INI --- --- 864
INS$ INS$ 657 @INS$ --- --- 1246
IORD INTELLIGENT I/O 222 @IORD --- --- 962
READ
IORF I/O REFRESH 097 @IORF --- --- 926
IORS ENABLE PERIPH- 288 --- --- --- 1185
ERAL SERVICING

119
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
IOSP DISABLE PERIPH- 287 @IOSP --- --- 1183
ERAL SERVICING
IOWR INTELLIGENT I/O 223 @IOWR --- --- 967
WRITE

J
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
JME JUMP END 005 --- --- --- 228
JME0 MULTIPLE JUMP END 516 --- --- --- 236
JMP JUMP 004 --- --- --- 228
JMP0 MULTIPLE JUMP 515 --- --- --- 236

K
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
KEEP KEEP 011 --- --- !KEEP 188

L
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
LD LOAD --- @LD %LD !LD 161
LD < LOAD LESS THAN 310 --- --- --- 291
LD <$ LOAD STRING LESS 672 --- --- --- 1250
THAN
LD <D LOAD DOUBLE 337 --- --- --- 694
FLOATING LESS
THAN
LD <DT LOAD TIME LESS 343 --- --- --- 297
THAN
LD <F LOAD FLOATING 331 --- --- --- 636
LESS THAN
LD <> LOAD NOT EQUAL 305 --- --- --- 291
LD <>$ LOAD STRING NOT 671 --- --- --- 1250
EQUAL
LD <>D LOAD DOUBLE 336 --- --- --- 694
FLOATING NOT
EQUAL
LD <>DT LOAD TIME NOT 342 --- --- --- 297
EQUAL
LD <>F LOAD FLOATING NOT 330 --- --- --- 636
EQUAL
LD <>L LOAD DOUBLE NOT 306 --- --- --- 291
EQUAL
LD <>S LOAD SIGNED NOT 307 --- --- --- 291
EQUAL
LD <>SL LOAD DOUBLE 308 --- --- --- 291
SIGNED NOT EQUAL
LD <L LOAD DOUBLE LESS 311 --- --- --- 291
THAN
LD <S LOAD SIGNED LESS 312 --- --- --- 291
THAN
LD <SL LOAD DOUBLE 313 --- --- --- 291
SIGNED LESS THAN
LD = LOAD EQUAL 300 --- --- --- 291
LD =$ LOAD STRING 670 --- --- --- 1250
EQUALS

120
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
LD =D LOAD DOUBLE 335 --- --- --- 694
FLOATING EQUAL
LD =DT LOAD TIME EQUAL 341 --- --- --- 297
LD =F LOAD FLOATING 329 --- --- --- 636
EQUAL
LD =L LOAD DOUBLE 301 --- --- --- 291
EQUAL
LD =S LOAD SIGNED EQUAL 302 --- --- --- 291
LD =SL LOAD DOUBLE 303 --- --- --- 291
SIGNED EQUAL
LD > LOAD GREATER 320 --- --- --- 291
THAN
LD >$ LOAD STRING 674 --- --- --- 1250
GREATER THAN
LD >D LOAD DOUBLE 339 --- --- --- 694
FLOATING GREATER
THAN
LD >DT LOAD TIME GREATER 345 --- --- --- 297
THAN
LD >F LOAD FLOATING 333 --- --- --- 636
GREATER THAN
LD >L LOAD DOUBLE 321 --- --- --- 291
GREATER THAN
LD >S LOAD SIGNED 322 --- --- --- 291
GREATER THAN
LD >SL LOAD DOUBLE 323 --- --- --- 291
SIGNED GREATER
THAN
LD NOT LOAD NOT --- --- --- !LD NOT 163
LD TST LOAD BIT TEST 350 --- --- --- 182
LD TSTN LOAD BIT TEST 351 --- --- --- 182
LD <= LOAD LESS THAN OR 315 --- --- --- 291
EQUAL
LD <=$ LOAD STRING LESS 673 --- --- --- 1250
THAN OR EQUAL
LD <=D LOAD DOUBLE 338 --- --- --- 694
FLOATING LESS
THAN OR EQUAL
LD <=DT LOAD TIME LESS 344 --- --- --- 297
THAN OR EQUAL
LD <=F LOAD FLOATING 332 --- --- --- 636
LESS THAN OR
EQUAL
LD <=L LOAD DOUBLE LESS 316 --- --- --- 291
THAN OR EQUAL
LD <=S LOAD SIGNED LESS 317 --- --- --- 291
THAN OR EQUAL
LD <=SL LOAD DOUBLE 318 --- --- --- 291
SIGNED LESS THAN
OR EQUAL
LD >= LOAD GREATER 325 --- --- --- 291
THAN OR EQUAL
LD >=$ LOAD STRING 675 --- --- --- 1250
GREATER THAN OR
EQUALS
LD >=D LOAD DOUBLE 340 --- --- --- 694
FLOATING GREATER
THAN OR EQUAL
LD >=DT LOAD TIME GREATER 346 --- --- --- 297
THAN OR EQUAL
LD >=F LOAD FLOATING 334 --- --- --- 636
GREATER THAN OR
EQUAL

121
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
LD >=L LOAD DOUBLE 326 --- --- --- 291
GREATER THAN OR
EQUAL
LD >=S LOAD SIGNED 327 --- --- --- 291
GREATER THAN OR
EQUAL
LD >=SL LOAD DOUBLE 328 --- --- --- 291
SIGNED GREATER
THAN OR EQUAL
LEFT$ GET STRING LEFT 652 @LEFT$ --- --- 1226
LEN$ STRING LENGTH 650 @LEN$ --- --- 1235
LEND NOT LOOP END NOT 810 --- --- --- 1215
(operand)
LEND (input LOOP END 810 --- --- --- 1215
condition)
LEND (oper- LOOP END 810 --- --- --- 1215
and)
LIFO LAST IN FIRST OUT 634 @LIFO --- --- 712
LINE COLUMN TO LINE 063 @LINE --- --- 512
LMT LIMIT CONTROL 680 @LMT --- --- 779
LOG LOGARITHM 468 @LOG --- --- 633
LOGD DOUBLE LOGARITHM 859 @LOGD --- --- 690
LOOP LOOP 809 --- --- --- 1215

M
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
MAX FIND MAXIMUM 182 @MAX --- --- 727
MCMP MULTIPLE COMPARE 019 @MCMP --- --- 315
MCRO MACRO 099 @MCRO --- --- 817
MID$ GET STRING MIDDLE 654 @MID$ --- --- 1230
MILC MULTI-INTERLOCK 519 --- --- --- 214
CLEAR
MILH MULTI-INTERLOCK 517 --- --- --- 214
DIFFERENTIATION
HOLD
MILR MULTI-INTERLOCK 518 --- --- --- 214
DIFFERENTIATION
RELEASE
MIN FIND MINIMUM 183 @MIN --- --- 731
MLPX DATA DECODER 076 @MLPX --- --- 496
MOV MOVE 021 @MOV --- !MOV 331
MOV$ MOVE STRING 664 @MOV$ --- --- 1221
MOVB MOVE BIT 082 @MOVB --- --- 337
MOVBC MOVE BIT 568 @MOVBC --- --- 1273
MOVD MOVE DIGIT 083 @MOVD --- --- 339
MOVF MOVE FLOATING- 469 @MOVF --- --- 649
POINT (SINGLE)
MOVL DOUBLE MOVE 498 @MOVL --- --- 334
MOVR MOVE TO REGISTER 560 @MOVR --- --- 356
MOVRW MOVE TIMER/ 561 --- --- --- 358
COUNTER PV TO
REGISTER
MSG DISPLAY MESSAGE 046 @MSG --- --- 1119
MSKR READ INTERRUPT 692 @MSKR --- --- 846
MASK
MSKS SET INTERRUPT 690 @MSKS --- --- 839
MASK

122
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
MTIM MULTI-OUTPUT 543 --- --- --- 269
TIMER
MTIMX MULTI-OUTPUT 554 --- --- --- 269
TIMER
MTR MATRIX INPUT 213 --- --- --- 953
MVN MOVE NOT 022 @MVN --- --- 333
MVNL DOUBLE MOVE NOT 499 @MVNL --- --- 336

N
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
NASL SHIFT N-BITS LEFT 580 @NASL --- --- 397
NASR SHIFT N-BITS RIGHT 581 @NASR --- --- 403
NEG 2’S COMPLEMENT 160 @NEG --- --- 491
NEGL DOUBLE 2’S 161 @NEGL --- --- 493
COMPLEMENT
NEXT FOR-NEXT LOOPS 513 --- --- --- 238
NOP NO OPERATION 000 --- --- --- 207
NOT NOT 520 --- --- --- 180
NSFL SHIFT N-BIT DATA 578 @NSFL --- --- 393
LEFT
NSFR SHIFT N-BIT DATA 579 @NSFR --- --- 395
RIGHT
NSLL DOUBLE SHIFT 582 @NSLL --- --- 400
N-BITS LEFT
NSRL DOUBLE SHIFT 583 @NSRL --- --- 405
N-BITS RIGHT
NUM4 ASCII TO FOUR-DIGIT 604 @NUM4 --- --- 534
NUMBER
NUM8 ASCII TO EIGHT-DIGIT 605 @NUM8 --- --- 537
NUMBER
NUM16 ASCII TO SIXTEEN- 606 @NUM16 --- --- 539
DIGIT NUMBER

O
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
OR OR --- @OR %OR !OR 169
OR < OR LESS THAN 310 --- --- --- 291
OR <$ OR STRING LESS 672 --- --- --- 1250
THAN
OR <> OR NOT EQUAL 305 --- --- --- 291
OR <>$ OR STRING NOT 671 --- --- --- 1250
EQUAL
OR <>D OR DOUBLE FLOAT- 336 --- --- --- 694
ING NOT EQUAL
OR <>DT OR TIME NOT EQUAL 342 --- --- --- 297
OR <>F OR FLOATING NOT 330 --- --- --- 636
EQUAL
OR <>L OR DOUBLE NOT 306 --- --- --- 291
EQUAL
OR <>S OR SIGNED NOT 307 --- --- --- 291
EQUAL
OR <>SL OR DOUBLE SIGNED 308 --- --- --- 291
NOT EQUAL
OR <D OR DOUBLE FLOAT- 337 --- --- --- 694
ING LESS THAN

123
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
OR <DT OR TIME LESS THAN 343 --- --- --- 297
OR <F OR FLOATING LESS 331 --- --- --- 636
THAN
OR <L OR DOUBLE LESS 311 --- --- --- 291
THAN
OR <S OR SIGNED LESS 312 --- --- --- 291
THAN
OR <SL OR DOUBLE SIGNED 313 --- --- --- 291
LESS THAN
OR = OR EQUAL 300 --- --- --- 291
OR =$ OR STRING EQUALS 670 --- --- --- 1250
OR =D OR DOUBLE FLOAT- 335 --- --- --- 694
ING EQUAL
OR =DT OR TIME EQUAL 341 --- --- --- 297
OR =F OR FLOATING EQUAL 329 --- --- --- 636
OR =L OR DOUBLE EQUAL 301 --- --- --- 291
OR =S OR SIGNED EQUAL 302 --- --- --- 291
OR =SL OR DOUBLE SIGNED 303 --- --- --- 291
EQUAL
OR > OR GREATER THAN 320 --- --- --- 291
OR >$ OR STRING GREATER 674 --- --- --- 1250
THAN
OR >D OR DOUBLE FLOAT- 339 --- --- --- 694
ING GREATER THAN
OR >DT OR TIME GREATER 345 --- --- --- 297
THAN
OR >F OR FLOATING 333 --- --- --- 636
GREATER THAN
OR >L OR DOUBLE 321 --- --- --- 291
GREATER THAN
OR >S OR SIGNED 322 --- --- --- 291
GREATER THAN
OR >SL OR DOUBLE SIGNED 323 --- --- --- 291
GREATER THAN
OR LD OR LOAD --- --- --- --- 174
OR NOT OR NOT --- --- --- !OR NOT 171
OR TST OR BIT TEST 350 --- --- --- 182
OR TSTN OR BIT TEST 351 --- --- --- 182
OR <= OR LESS THAN OR 315 --- --- --- 291
EQUAL
OR <=$ OR STRING LESS 673 --- --- --- 1250
THAN OR EQUALS
OR <=D OR DOUBLE FLOAT- 338 --- --- --- 694
ING LESS THAN OR
EQUAL
OR <=DT OR TIME LESS THAN 344 --- --- --- 297
OR EQUAL
OR <=F OR FLOATING LESS 332 --- --- --- 636
THAN OR EQUAL
OR <=L OR DOUBLE LESS 316 --- --- --- 291
THAN OR EQUAL
OR <=S OR SIGNED LESS 317 --- --- --- 291
THAN OR EQUAL
OR <=SL OR DOUBLE SIGNED 318 --- --- --- 291
LESS THAN OR
EQUAL
OR >= OR GREATER THAN 325 --- --- --- 291
OR EQUAL
OR >=$ OR STRING GREATER 675 --- --- --- 1250
THAN OR EQUALS

124
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
OR >=D OR DOUBLE FLOAT- 340 --- --- --- 694
ING GREATER THAN
OR EQUAL
OR >=DT OR TIME GREATER 346 --- --- --- 297
THAN OR EQUAL
OR >=F OR FLOATING 334 --- --- --- 636
GREATER THAN OR
EQUAL
OR >=L OR DOUBLE 326 --- --- --- 291
GREATER THAN OR
EQUAL
OR >=S OR SIGNED 327 --- --- --- 291
GREATER THAN OR
EQUAL
OR >=SL OR DOUBLE SIGNED 328 --- --- --- 291
GREATER THAN OR
EQUAL
ORG ORIGIN SEARCH 889 @ORG --- --- 903
ORW LOGICAL OR 035 @ORW --- --- 551
ORWL DOUBLE LOGICAL OR 611 @ORWL --- --- 553
OUT OUTPUT --- --- --- !OUT 185
OUTB SINGLE BIT OUTPUT 534 @OUTB --- !OUTB 204
OUT NOT OUTPUT NOT --- --- --- !OUT NOT 187

P
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
PID PID CONTROL 190 --- --- --- 757
PIDAT PID CONTROL WITH 191 --- --- --- 769
AUTOTUNING
PMCR PROTOCOL MACRO 260 @PMCR --- --- 974
PRV HIGH-SPEED 881 @PRV --- --- 868
COUNTER PV READ
PRV2 COUNTER FRE- 883 @PRV2 --- --- 874
QUENCY CONVERT
PULS SET PULSES 886 @PULS --- --- 887
PLS2 PULSE OUTPUT 887 @PLS2 --- --- 890
PUSH PUSH ONTO STACK 632 @PUSH --- --- 706
PWM PULSE WITH VARI- 891 @PWM --- --- 906
ABLE DUTY FACTOR
PWR EXPONENTIAL 840 @PWR --- --- 635
POWER
PWRD DOUBLE EXPONEN- 860 @PWRD --- --- 692
TIAL POWER

R
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
RAD DEGREES TO 458 @RAD --- --- 633
RADIANS
RADD DOUBLE DEGREES 849 @RADD --- --- 671
TO RADIANS
RECV NETWORK RECEIVE 098 @RECV --- --- 1050
RET SUBROUTINE 093 --- --- --- 824
RETURN
RGHT$ GET STRING RIGHT 653 @RGHT$ --- --- 1228
RLNC ROTATE LEFT 574 @RLNC --- --- 383
WITHOUT CARRY

125
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
RLNL DOUBLE ROTATE 576 @RLNL --- --- 385
LEFT WITHOUT
CARRY
ROL ROTATE LEFT 027 @ROL --- --- 376
ROLL DOUBLE ROTATE 572 @ROLL --- --- 378
LEFT
ROOT BCD SQUARE ROOT 072 @ROOT --- --- 567
ROR ROTATE RIGHT 028 @ROR --- --- 380
RORL DOUBLE ROTATE 573 @RORL --- --- 381
RIGHT
ROTB BINARY ROOT 620 @ROTB --- --- 565
RPLC$ REPLACE IN STRING 661 @RPLC$ --- --- 1237
RRNC ROTATE RIGHT 575 @RRNC --- --- 387
WITHOUT CARRY
RRNL DOUBLE ROTATE 577 @RRNL --- --- 388
RIGHT WITHOUT
CARRY
RSET RESET --- @RSET %RSET !RSET 195
RSTA MULTIPLE BIT RESET 531 @RSTA --- --- 198
RSTB SINGLE BIT RESET 533 @RSTB --- !RSTB 201
RXD RECEIVE 235 @RXD --- --- 993
RXDU RECEIVE VIA SERIAL 255 @RXDU --- --- 1013
COMMUNICATIONS
UNIT

S
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
SBN SUBROUTINE ENTRY 092 --- --- --- 821
SBS SUBROUTINE CALL 091 @SBS --- --- 811
SCL SCALING 194 @SCL --- --- 795
SCL2 SCALING 2 486 @SCL2 --- --- 800
SCL3 SCALING 3 487 @SCL3 --- --- 804
SDEC 7-SEGMENT 078 @SDEC --- --- 974
DECODER
SDEL STACK DATA DELETE 642 @SDEL --- --- 753
SEC HOURS TO SECONDS 065 @SEC --- --- 1129
SEND NETWORK SEND 090 @SEND --- --- 1044
SET SET --- @SET %SET !SET 195
SETA MULTIPLE BIT SET 530 @SETA --- --- 198
SETB SINGLE BIT SET 532 @SETB --- !SETB 201
SETR SET RECORD 635 @SETR --- --- 718
LOCATION
SFT SHIFT REGISTER 010 --- --- --- 361
SFTR REVERSIBLE SHIFT 084 @SFTR --- --- 362
REGISTER
SIGN 16-BIT TO 32-BIT 600 @SIGN --- --- 494
SIGNED BINARY
SIN SINE 460 @SIN --- --- 612
SIND DOUBLE SINE 851 @SIND --- --- 674
SINQ HIGH-SPEED SINE 475 @SINQ --- --- 614
SINS STACK DATA INSERT 641 @SINS --- --- 750
SLD ONE DIGIT SHIFT 074 @SLD --- --- 390
LEFT
SNUM STACK SIZE READ 638 @SNUM --- --- 742
SNXT STEP START 009 --- --- --- 909

126
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
SPED SPEED OUTPUT 885 @SPED --- --- 882
SQRT SQUARE ROOT 466 @SQRT --- --- 629
SQRTD DOUBLE SQUARE 857 @SQRTD --- --- 686
ROOT
SRCH DATA SEARCH 181 @SRCH --- --- 722
SRD ONE DIGIT SHIFT 075 @SRD --- --- 392
RIGHT
SREAD STACK DATA READ 639 @SREAD --- --- 744
SSET SET STACK 630 @SSET --- --- 703
STC SET CARRY 040 @STC --- --- 1166
STEP STEP DEFINE 008 --- --- --- 909
STR4 FOUR-DIGIT NUM- 601 @STR4 --- --- 541
BER TO ASCII
STR8 EIGHT-DIGIT NUMBER 602 @STR8 --- --- 544
TO ASCII
STR16 SIXTEEN-DIGIT NUM- 603 @STR16 --- --- 545
BER TO ASCII
STUP CHANGE SERIAL 237 @STUP --- --- 1021
PORT SETUP
SUM SUM 184 @SUM --- --- 735
SWAP SWAP BYTES 637 @SWAP --- --- 725
SWRIT STACK DATA WRITE 640 @SWRIT --- --- 747

T
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
TAN TANGENT 462 @TAN --- --- 619
TAND DOUBLE TANGENT 853 @TAND --- --- 678
TANQ HIGH-SPEED TAN- 477 @TANQ --- --- 621
GENT
TCMP TABLE COMPARE 085 @TCMP --- --- 317
TIM HUNDRED-MS TIMER --- --- --- --- 245
TIMH TEN-MS TIMER 015 --- --- --- 249
TIMHX TEN-MS TIMER 551 --- --- --- 249
TIML LONG TIMER 542 --- --- --- 266
TIMLX LONG TIMER 553 --- --- --- 266
TIMU TENTH-MS TIMER 541 --- --- --- 256
TIMUX TENTH-MS TIMER 556 --- --- --- 256
TIMW HUNDRED-MS TIMER 813 --- --- --- 1206
WAIT
TIMWX HUNDRED-MS TIMER 816 --- --- --- 1206
WAIT
TIMX HUNDRED-MS TIMER 550 --- --- --- 245
TKOF TASK OFF 821 @TKOF --- --- 1258
TKON TASK ON 820 @TKON --- --- 1255
TKY TEN KEY INPUT 211 @TKY --- --- 945
TMHH ONE-MS TIMER 540 --- --- --- 253
TMHHX ONE-MS TIMER 552 --- --- --- 253
TMHW TEN-MS TIMER WAIT 815 --- --- --- 1212
TMHWX TEN-MS TIMER WAIT 817 --- --- --- 1212
TMUH HUNDREDTH-MS 544 --- --- --- 259
TIMER
TMUHX HUNDREDTH-MS 557 --- --- --- 259
TIMER

127
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
TOCV CONVERT ADDRESS 285 @TOCV --- --- 1179
TO CV
TPO TIME-PROPOR- 685 --- --- --- 787
TIONAL OUTPUT
TRSM TRACE MEMORY 045 --- --- --- 1136
SAMPLING
TTIM ACCUMULATIVE 087 --- --- --- 262
TIMER
TTIMX ACCUMULATIVE 555 --- --- --- 262
TIMER
TWRIT WRITE TEXT FILE 704 @TWRIT --- --- 1113
TXD TRANSMIT 236 @TXD --- --- 983
TXDU TRANSMIT VIA 256 @TXDU --- --- 1005
SERIAL COMMUNICA-
TIONS UNIT

U
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
UP CONDITION ON 521 --- --- --- 181

W
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
WAIT NOT ONE CYCLE AND 805 --- --- --- 1202
(operand) WAIT NOT
WAIT (input ONE CYCLE AND 805 --- --- --- 1202
condition) WAIT
WAIT (operand) ONE CYCLE AND 805 --- --- --- 1202
WAIT
WDT EXTEND MAXIMUM 094 @WDT --- --- 1169
CYCLE TIME
WSFT WORD SHIFT 016 @WSFT --- --- 368

X
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
XCGL DOUBLE DATA 562 @XCGL --- --- 350
EXCHANGE
XCHG DATA EXCHANGE 073 @XCHG --- --- 349
XCHG$ EXCHANGE STRING 665 @XCHG$ --- --- 1242
XFER BLOCK TRANSFER 070 @XFER --- --- 344
XFERC BLOCK TRANSFER 565 @XFERC --- --- 1263
XFRB MULTIPLE BIT 062 @XFRB --- --- 342
TRANSFER
XNRL DOUBLE EXCLUSIVE 613 @XNRL --- --- 560
NOR
XNRW EXCLUSIVE NOR 037 @XNRW --- --- 559
XORL DOUBLE EXCLUSIVE 612 @XORL --- --- 557
OR
XORW EXCLUSIVE OR 036 @XORW --- --- 555

128
Alphabetical List of Instructions by Mnemonic Section 2-3

Z
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
ZCP AREA RANGE COM- 088 --- --- --- 326
PARE
ZCPL DOUBLE AREA 116 --- --- --- 329
RANGE COMPARE
ZONE DEAD ZONE 682 @ZONE --- --- 784
CONTROL

Symbols
Mnemonic Instruction FUN code Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
7SEG 7-SEGMENT DISPLAY 214 --- --- --- 957
OUTPUT
+ SIGNED BINARY ADD 400 @+ --- --- 426
WITHOUT CARRY
+$ CONCATENATE 656 @+$ --- --- 1223
STRING
++ INCREMENT BINARY 590 @++ --- --- 409
++B INCREMENT BCD 594 @++B --- --- 417
++BL DOUBLE 595 @++BL --- --- 419
INCREMENT BCD
++L DOUBLE 591 @++L --- --- 411
INCREMENT BINARY
+B BCD ADD WITHOUT 404 @+B --- --- 434
CARRY
+BC BCD ADD WITH 406 @+BC --- --- 437
CARRY
+BCL DOUBLE BCD ADD 407 @+BCL --- --- 439
WITH CARRY
+BL DOUBLE BCD ADD 405 @+BL --- --- 435
WITHOUT CARRY
+C SIGNED BINARY ADD 402 @+C --- --- 430
WITH CARRY
+CL DOUBLE SIGNED 403 @+CL --- --- 432
BINARY ADD WITH
CARRY
+D DOUBLE FLOATING- 845 @+D --- --- 663
POINT ADD
+F FLOATING-POINT 454 @+F --- --- 601
ADD
+L DOUBLE SIGNED 401 @+L --- --- 428
BINARY ADD
WITHOUT CARRY
– SIGNED BINARY 410 @– --- --- 440
SUBTRACT
WITHOUT CARRY
–– DECREMENT BINARY 592 @– – --- --- 413
– –B DECREMENT BCD 596 @– –B --- --- 421
– –BL DOUBLE 597 @– –BL --- --- 423
DECREMENT BCD
– –L DOUBLE 593 @– –L --- --- 415
DECREMENT BINARY
–B BCD SUBTRACT 414 @–B --- --- 451
WITHOUT CARRY
–BC BCD SUBTRACT 416 @–BC --- --- 456
WITH CARRY
–BCL DOUBLE BCD 417 @–BCL --- --- 457
SUBTRACT WITH
CARRY

129
Alphabetical List of Instructions by Mnemonic Section 2-3

Mnemonic Instruction FUN code Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
–BL DOUBLE BCD 415 @–BL --- --- 452
SUBTRACT
WITHOUT CARRY
–C SIGNED BINARY 412 @–C --- --- 446
SUBTRACT WITH
CARRY
–CL DOUBLE SIGNED 413 @–CL --- --- 448
BINARY SUBTRACT
WITH CARRY
−D DOUBLE FLOATING- 846 @−D --- --- 665
POINT SUBTRACT
–F FLOATING-POINT 455 @–F --- --- 603
SUBTRACT
* SIGNED BINARY 420 @* --- --- 459
MULTIPLY
*B BCD MULTIPLY 424 @*B --- --- 467
*BL DOUBLE BCD 425 @*BL --- --- 469
MULTIPLY
*D DOUBLE FLOATING- 847 @*D --- --- 667
POINT MULTIPLY
*F FLOATING-POINT 456 @*F --- --- 605
MULTIPLY
*L DOUBLE SIGNED 421 @*L --- --- 461
BINARY MULTIPLY
*U UNSIGNED BINARY 422 @*U --- --- 463
MULTIPLY
*UL DOUBLE UNSIGNED 423 @*UL --- --- 465
BINARY MULTIPLY
–L DOUBLE SIGNED 411 @–L --- --- 442
BINARY SUBTRACT
WITHOUT CARRY
/ SIGNED BINARY 430 @/ --- --- 471
DIVIDE
/B BCD DIVIDE 434 @/B --- --- 479
/BL DOUBLE BCD DIVIDE 435 @/BL --- --- 481
/D DOUBLE FLOATING- 848 @/D --- --- 669
POINT DIVIDE
/F FLOATING-POINT 457 @/F --- --- 607
DIVIDE
/L DOUBLE SIGNED 431 @/L --- --- 473
BINARY DIVIDE
/U UNSIGNED BINARY 432 @/U --- --- 475
DIVIDE
/UL DOUBLE UNSIGNED 433 @/UL --- --- 477
BINARY DIVIDE

130
List of Instructions by Function Code Section 2-4

2-4 List of Instructions by Function Code

Function code Mnemonic Instruction Upward Downward Immediate Page
Differentiation Differentiation Refreshing
Specification
--- LD LOAD @LD %LD !LD 161
--- LD NOT LOAD NOT --- --- !LD NOT 163
--- AND AND @AND %AND !AND 165
--- AND NOT AND NOT --- --- !AND NOT 167
--- OR OR @OR %OR !OR 169
--- OR NOT OR NOT --- --- !OR NOT 171
--- AND LD AND LOAD --- --- --- 172
--- OR LD OR LOAD --- --- --- 174
--- OUT OUTPUT --- --- !OUT 185
--- OUT NOT OUTPUT NOT --- --- !OUT NOT 187
--- SET SET @SET %SET !SET 195
--- RSET RESET @RSET %RSET !RSET 195
--- TIM HUNDRED-MS TIMER --- --- --- 245
--- CNT COUNTER --- --- --- 275
000 NOP NO OPERATION --- --- --- 207
001 END END --- --- --- 206
002 IL INTERLOCK --- --- --- 210
003 ILC INTERLOCK CLEAR --- --- --- 210
004 JMP JUMP --- --- --- 228
005 JME JUMP END --- --- --- 228
006 FAL FAILURE ALARM @FAL --- --- 1140
007 FALS SEVERE FAILURE --- --- --- 1148
ALARM
008 STEP STEP DEFINE --- --- --- 909
009 SNXT STEP START --- --- --- 909
010 SFT SHIFT REGISTER --- --- --- 361
011 KEEP KEEP --- --- !KEEP 188
012 CNTR REVERSIBLE --- --- --- 278
COUNTER
013 DIFU DIFFERENTIATE UP --- --- !DIFU 193
014 DIFD DIFFERENTIATE --- --- !DIFD 193
DOWN
015 TIMH TEN-MS TIMER --- --- --- 249
016 WSFT WORD SHIFT @WSFT --- --- 368
017 ASFT ASYNCHRONOUS @ASFT --- --- 365
SHIFT REGISTER
019 MCMP MULTIPLE COMPARE @MCMP --- --- 315
020 CMP UNSIGNED COMPARE --- --- !CMP 303
021 MOV MOVE @MOV --- !MOV 331
022 MVN MOVE NOT @MVN --- --- 333
023 BIN BCD TO BINARY @BIN --- --- 483
024 BCD BINARY TO BCD @BCD --- --- 487
025 ASL ARITHMETIC SHIFT @ASL --- --- 370
LEFT
026 ASR ARITHMETIC SHIFT @ASR --- --- 373
RIGHT
027 ROL ROTATE LEFT @ROL --- --- 376
028 ROR ROTATE RIGHT @ROR --- --- 380
029 COM COMPLEMENT @COM --- --- 562
034 ANDW LOGICAL AND @ANDW --- --- 548
035 ORW LOGICAL OR @ORW --- --- 551
036 XORW EXCLUSIVE OR @XORW --- --- 555

131
List of Instructions by Function Code Section 2-4

Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
037 XNRW EXCLUSIVE NOR @XNRW --- --- 559
040 STC SET CARRY @STC --- --- 1166
041 CLC CLEAR CARRY @CLC --- --- 1166
045 TRSM TRACE MEMORY --- --- --- 1136
SAMPLING
046 MSG DISPLAY MESSAGE @MSG --- --- 1119
058 BINL DOUBLE BCD TO @BINL --- --- 485
DOUBLE BINARY
059 BCDL DOUBLE BINARY TO @BCDL --- --- 489
BCD
060 CMPL DOUBLE UNSIGNED --- --- --- 306
COMPARE
062 XFRB MULTIPLE BIT @XFRB --- --- 342
TRANSFER
063 LINE COLUMN TO LINE @LINE --- --- 512
064 COLM LINE TO COLUMN @COLM --- --- 514
065 SEC HOURS TO SECONDS @SEC --- --- 1129
066 HMS SECONDS TO HOURS @HMS --- --- 1131
067 BCNT BIT COUNTER @BCNT --- --- 587
068 BCMP UNSIGNED BLOCK @BCMP --- --- 320
COMPARE
069 APR ARITHMETIC @APR --- --- 571
PROCESS
070 XFER BLOCK TRANSFER @XFER --- --- 344
071 BSET BLOCK SET @BSET --- --- 347
072 ROOT BCD SQUARE ROOT @ROOT --- --- 567
073 XCHG DATA EXCHANGE @XCHG --- --- 349
074 SLD ONE DIGIT SHIFT @SLD --- --- 390
LEFT
075 SRD ONE DIGIT SHIFT @SRD --- --- 392
RIGHT
076 MLPX DATA DECODER @MLPX --- --- 496
077 DMPX DATA ENCODER @DMPX --- --- 500
078 SDEC 7-SEGMENT @SDEC --- --- 974
DECODER
079 FDIV FLOATING POINT @FDIV --- --- 583
DIVIDE
080 DIST SINGLE WORD @DIST --- --- 352
DISTRIBUTE
081 COLL DATA COLLECT @COLL --- --- 354
082 MOVB MOVE BIT @MOVB --- --- 337
083 MOVD MOVE DIGIT @MOVD --- --- 339
084 SFTR REVERSIBLE SHIFT @SFTR --- --- 362
REGISTER
085 TCMP TABLE COMPARE @TCMP --- --- 317
086 ASC ASCII CONVERT @ASC --- --- 504
087 TTIM ACCUMULATIVE --- --- --- 262
TIMER
088 ZCP AREA RANGE COM- --- --- --- 326
PARE
090 SEND NETWORK SEND @SEND --- --- 1044
091 SBS SUBROUTINE CALL @SBS --- --- 811
092 SBN SUBROUTINE ENTRY --- --- --- 821
093 RET SUBROUTINE --- --- --- 824
RETURN
094 WDT EXTEND MAXIMUM @WDT --- --- 1169
CYCLE TIME

132
List of Instructions by Function Code Section 2-4

Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
096 BPRG BLOCK PROGRAM --- --- --- 1191
BEGIN
097 IORF I/O REFRESH @IORF --- --- 926
098 RECV NETWORK RECEIVE @RECV --- --- 1050
099 MCRO MACRO @MCRO --- --- 817
114 CPS SIGNED BINARY --- --- !CPS 309
COMPARE
115 CPSL DOUBLE SIGNED --- --- --- 312
BINARY COMPARE
116 ZCPL DOUBLE AREA --- --- --- 329
RANGE COMPARE
160 NEG 2’S COMPLEMENT @NEG --- --- 491
161 NEGL DOUBLE 2’S @NEGL --- --- 493
COMPLEMENT
162 HEX ASCII TO HEX @HEX --- --- 508
180 FCS FRAME CHECKSUM @FCS --- --- 738
181 SRCH DATA SEARCH @SRCH --- --- 722
182 MAX FIND MAXIMUM @MAX --- --- 727
183 MIN FIND MINIMUM @MIN --- --- 731
184 SUM SUM @SUM --- --- 735
190 PID PID CONTROL --- --- --- 757
191 PIDAT PID CONTROL WITH --- --- --- 769
AUTOTUNING
194 SCL SCALING @SCL --- --- 795
195 AVG AVERAGE --- --- --- 807
210 DSW DIGITAL SWITCH --- --- --- 940
INPUT
211 TKY TEN KEY INPUT @TKY --- --- 945
212 HKY HEXADECIMAL KEY --- --- --- 948
INPUT
213 MTR MATRIX INPUT --- --- --- 953
214 7SEG 7-SEGMENT DISPLAY --- --- --- 957
OUTPUT
222 IORD INTELLIGENT I/O @IORD --- --- 962
READ
223 IOWR INTELLIGENT I/O @IOWR --- --- 967
WRITE
225 FIORF SPECIAL I/O UNIT I/O @FIORF --- --- 929
REFRESH
226 DLNK CPU BUS UNIT I/O @DLNK --- --- 932
REFRESH
235 RXD RECEIVE @RXD --- --- 993
236 TXD TRANSMIT @TXD --- --- 983
255 RXDU RECEIVE VIA SERIAL @RXDU --- --- 1013
COMMUNICATIONS
UNIT
256 TXDU TRANSMIT VIA @TXDU --- --- 1005
SERIAL COMMUNICA-
TIONS UNIT
237 STUP CHANGE SERIAL @STUP --- --- 1021
PORT SETUP
260 PMCR PROTOCOL MACRO @PMCR --- --- 974
269 FPD FAILURE POINT --- --- --- 1156
DETECTION
281 EMBC SELECT EM BANK @EMBC --- --- 1167
282 CCS SAVE CONDITION @CCS --- --- 1171
FLAGS
283 CCL LOAD CONDITION @CCL --- --- 1173
FLAGS

133
List of Instructions by Function Code Section 2-4

Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
284 FRMCV CONVERT ADDRESS @FRMCV --- --- 1174
FROM CV
285 TOCV CONVERT ADDRESS @TOCV --- --- 1179
TO CV
286 GETID GET VARIABLE ID @GETID --- --- 1277
287 IOSP DISABLE PERIPH- @IOSP --- --- 1183
ERAL SERVICING
288 IORS ENABLE PERIPH- --- --- --- 1185
ERAL SERVICING
300 AND = AND EQUAL --- --- --- 291
300 LD = LOAD EQUAL --- --- --- 291
300 OR = OR EQUAL --- --- --- 291
301 AND =L AND DOUBLE EQUAL --- --- --- 291
301 LD =L LOAD DOUBLE --- --- --- 291
EQUAL
301 OR =L OR DOUBLE EQUAL --- --- --- 291
302 AND =S AND SIGNED EQUAL --- --- --- 291
302 LD =S LOAD SIGNED EQUAL --- --- --- 291
302 OR =S OR SIGNED EQUAL --- --- --- 291
303 AND =SL AND DOUBLE --- --- --- 291
SIGNED EQUAL
303 LD =SL LOAD DOUBLE --- --- --- 291
SIGNED EQUAL
303 OR =SL OR DOUBLE SIGNED --- --- --- 291
EQUAL
305 AND <> AND NOT EQUAL --- --- --- 291
305 LD <> LOAD NOT EQUAL --- --- --- 291
305 OR <> OR NOT EQUAL --- --- --- 291
306 AND <>L AND DOUBLE NOT --- --- --- 291
EQUAL
306 LD <>L LOAD DOUBLE NOT --- --- --- 291
EQUAL
306 OR <>L OR DOUBLE NOT --- --- --- 291
EQUAL
307 AND <>S AND SIGNED NOT --- --- --- 291
EQUAL
307 LD <>S LOAD SIGNED NOT --- --- --- 291
EQUAL
307 OR <>S OR SIGNED NOT --- --- --- 291
EQUAL
308 AND <>SL AND DOUBLE --- --- --- 291
SIGNED NOT EQUAL
308 LD <>SL LOAD DOUBLE --- --- --- 291
SIGNED NOT EQUAL
308 OR <>SL OR DOUBLE SIGNED --- --- --- 291
NOT EQUAL
310 AND < AND LESS THAN --- --- --- 291
310 LD < LOAD LESS THAN --- --- --- 291
310 OR < OR LESS THAN --- --- --- 291
311 AND <L AND DOUBLE LESS --- --- --- 291
THAN
311 LD <L LOAD DOUBLE LESS --- --- --- 291
THAN
311 OR <L OR DOUBLE LESS --- --- --- 291
THAN
312 AND <S AND SIGNED LESS --- --- --- 291
THAN
312 LD <S LOAD SIGNED LESS --- --- --- 291
THAN

134
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Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
312 OR <S OR SIGNED LESS --- --- --- 291
THAN
313 AND <SL AND DOUBLE --- --- --- 291
SIGNED LESS THAN
313 LD <SL LOAD DOUBLE --- --- --- 291
SIGNED LESS THAN
313 OR <SL OR DOUBLE SIGNED --- --- --- 291
LESS THAN
315 AND <= AND LESS THAN OR --- --- --- 291
EQUAL
315 LD <= LOAD LESS THAN OR --- --- --- 291
EQUAL
315 OR <= OR LESS THAN OR --- --- --- 291
EQUAL
316 AND <=L AND DOUBLE LESS --- --- --- 291
THAN OR EQUAL
316 LD <=L LOAD DOUBLE LESS --- --- --- 291
THAN OR EQUAL
316 OR <=L OR DOUBLE LESS --- --- --- 291
THAN OR EQUAL
317 AND <=S AND SIGNED LESS --- --- --- 291
THAN OR EQUAL
317 LD <=S LOAD SIGNED LESS --- --- --- 291
THAN OR EQUAL
317 OR <=S OR SIGNED LESS --- --- --- 291
THAN OR EQUAL
318 AND <=SL AND DOUBLE --- --- --- 291
SIGNED LESS THAN
OR EQUAL
318 LD <=SL LOAD DOUBLE --- --- --- 291
SIGNED LESS THAN
OR EQUAL
318 OR <=SL OR DOUBLE SIGNED --- --- --- 291
LESS THAN OR
EQUAL
320 AND > AND GREATER THAN --- --- --- 291
320 LD > LOAD GREATER --- --- --- 291
THAN
320 OR > OR GREATER THAN --- --- --- 291
321 AND >L AND DOUBLE --- --- --- 291
GREATER THAN
321 LD >L LOAD DOUBLE --- --- --- 291
GREATER THAN
321 OR >L OR DOUBLE --- --- --- 291
GREATER THAN
322 AND >S AND SIGNED --- --- --- 291
GREATER THAN
322 LD >S LOAD SIGNED --- --- --- 291
GREATER THAN
322 OR >S OR SIGNED --- --- --- 291
GREATER THAN
323 AND >SL AND DOUBLE --- --- --- 291
SIGNED GREATER
THAN
323 LD >SL LOAD DOUBLE --- --- --- 291
SIGNED GREATER
THAN
323 OR >SL OR DOUBLE SIGNED --- --- --- 291
GREATER THAN
325 AND >= AND GREATER THAN --- --- --- 291
OR EQUAL
325 LD >= LOAD GREATER --- --- --- 291
THAN OR EQUAL

135
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Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
325 OR >= OR GREATER THAN --- --- --- 291
OR EQUAL
326 AND >=L AND DOUBLE --- --- --- 291
GREATER THAN OR
EQUAL
326 LD >=L LOAD DOUBLE --- --- --- 291
GREATER THAN OR
EQUAL
326 OR >=L OR DOUBLE --- --- --- 291
GREATER THAN OR
EQUAL
327 AND >=S AND SIGNED --- --- --- 291
GREATER THAN OR
EQUAL
327 LD >=S LOAD SIGNED --- --- --- 291
GREATER THAN OR
EQUAL
327 OR >=S OR SIGNED --- --- --- 291
GREATER THAN OR
EQUAL
328 AND >=SL AND DOUBLE --- --- --- 291
SIGNED GREATER
THAN OR EQUAL
328 LD >=SL LOAD DOUBLE --- --- --- 291
SIGNED GREATER
THAN OR EQUAL
328 OR >=SL OR DOUBLE SIGNED --- --- --- 291
GREATER THAN OR
EQUAL
329 AND =F AND FLOATING --- --- --- 636
EQUAL
329 LD =F LOAD FLOATING --- --- --- 636
EQUAL
329 OR =F OR FLOATING EQUAL --- --- --- 636
330 AND <>F AND FLOATING NOT --- --- --- 636
EQUAL
330 LD <>F LOAD FLOATING NOT --- --- --- 636
EQUAL
330 OR <>F OR FLOATING NOT --- --- --- 636
EQUAL
331 AND <F AND FLOATING LESS --- --- --- 636
THAN
331 LD <F LOAD FLOATING --- --- --- 636
LESS THAN
331 OR <F OR FLOATING LESS --- --- --- 636
THAN
332 AND <=F AND FLOATING LESS --- --- --- 636
THAN OR EQUAL
332 LD <=F LOAD FLOATING --- --- --- 636
LESS THAN OR
EQUAL
332 OR <=F OR FLOATING LESS --- --- --- 636
THAN OR EQUAL
333 AND >F AND FLOATING --- --- --- 636
GREATER THAN
333 LD >F LOAD FLOATING --- --- --- 636
GREATER THAN
333 OR >F OR FLOATING --- --- --- 636
GREATER THAN
334 AND >=F AND FLOATING --- --- --- 636
GREATER THAN OR
EQUAL
334 LD >=F LOAD FLOATING --- --- --- 636
GREATER THAN OR
EQUAL

136
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Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
334 OR >=F OR FLOATING --- --- --- 636
GREATER THAN OR
EQUAL
335 AND =D AND DOUBLE FLOAT- --- --- --- 694
ING EQUAL
335 LD =D LOAD DOUBLE --- --- --- 694
FLOATING EQUAL
335 OR =D OR DOUBLE FLOAT- --- --- --- 694
ING EQUAL
336 AND <>D AND DOUBLE FLOAT- --- --- --- 694
ING NOT EQUAL
336 LD <>D LOAD DOUBLE --- --- --- 694
FLOATING NOT
EQUAL
336 OR <>D OR DOUBLE FLOAT- --- --- --- 694
ING NOT EQUAL
337 AND <D AND DOUBLE FLOAT- --- --- --- 694
ING LESS THAN
337 LD <D LOAD DOUBLE --- --- --- 694
FLOATING LESS
THAN
337 OR <D OR DOUBLE FLOAT- --- --- --- 694
ING LESS THAN
338 AND <=D AND DOUBLE FLOAT- --- --- --- 694
ING LESS THAN OR
EQUAL
338 LD <=D LOAD DOUBLE --- --- --- 694
FLOATING LESS
THAN OR EQUAL
338 OR <=D OR DOUBLE FLOAT- --- --- --- 694
ING LESS THAN OR
EQUAL
339 AND >D AND DOUBLE FLOAT- --- --- --- 694
ING GREATER THAN
339 LD >D LOAD DOUBLE --- --- --- 694
FLOATING GREATER
THAN
339 OR >D OR DOUBLE FLOAT- --- --- --- 694
ING GREATER THAN
340 AND >=D AND DOUBLE FLOAT- --- --- --- 694
ING GREATER THAN
OR EQUAL
340 LD >=D LOAD DOUBLE --- --- --- 694
FLOATING GREATER
THAN OR EQUAL
340 OR >=D OR DOUBLE FLOAT- --- --- --- 694
ING GREATER THAN
OR EQUAL
341 AND = DT AND TIME EQUAL --- --- --- 297
341 LD = DT LOAD TIME EQUAL --- --- --- 297
341 OR = DT OR TIME EQUAL --- --- --- 297
342 AND <> DT AND TIME NOT --- --- --- 297
EQUAL
342 LD <> DT LOAD TIME NOT --- --- --- 297
EQUAL
342 OR <> DT OR TIME NOT EQUAL --- --- --- 297
343 AND < DT AND TIME LESS --- --- --- 297
THAN
343 LD < DT LOAD TIME LESS --- --- --- 297
THAN
343 OR < DT OR TIME LESS THAN --- --- --- 297
344 AND <= DT AND TIME LESS --- --- --- 297
THAN OR EQUAL

137
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Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
344 LD <= DT LD TIME LESS THAN --- --- --- 297
OR EQUAL
344 OR <= DT OR TIME LESS THAN --- --- --- 297
OR EQUAL
345 AND > DT AND TIME GREATER --- --- --- 297
THAN
345 LD > DT LOAD TIME GREATER --- --- --- 297
THAN
345 OR > DT OR TIME GREATER --- --- --- 297
THAN
346 AND >= DT AND TIME GREATER --- --- --- 297
THAN OR EQUAL
346 LD >= DT LOAD TIME GREATER --- --- --- 297
THAN OR EQUAL
346 OR >= DT OR TIME GREATER --- --- --- 297
THAN OR EQUAL
350 AND TST AND BIT TEST --- --- --- 182
350 LD TST LOAD BIT TEST --- --- --- 182
350 OR TST OR BIT TEST --- --- --- 182
351 AND TSTN AND BIT TEST NOT --- --- --- 182
351 LD TSTN LOAD BIT TEST NOT --- --- --- 182
351 OR TSTN OR BIT TEST NOT --- --- --- 182
400 + SIGNED BINARY ADD @+ --- --- 426
WITHOUT CARRY
401 +L DOUBLE SIGNED @+L --- --- 428
BINARY ADD
WITHOUT CARRY
402 +C SIGNED BINARY ADD @+C --- --- 430
WITH CARRY
403 +CL DOUBLE SIGNED @+CL --- --- 432
BINARY ADD WITH
CARRY
404 +B BCD ADD WITHOUT @+B --- --- 437
CARRY
405 +BL DOUBLE BCD ADD @+BL --- --- 435
WITHOUT CARRY
406 +BC BCD ADD WITH @+BC --- --- 437
CARRY
407 +BCL DOUBLE BCD ADD @+BCL --- --- 439
WITH CARRY
410 – SIGNED BINARY @– --- --- 440
SUBTRACT
WITHOUT CARRY
411 –L DOUBLE SIGNED @–L --- --- 442
BINARY SUBTRACT
WITHOUT CARRY
412 –C SIGNED BINARY @–C --- --- 446
SUBTRACT WITH
CARRY
413 –CL DOUBLE SIGNED @–CL --- --- 448
BINARY SUBTRACT
WITH CARRY
414 –B BCD SUBTRACT @–B --- --- 451
WITHOUT CARRY
415 –BL DOUBLE BCD @–BL --- --- 452
SUBTRACT
WITHOUT CARRY
416 –BC BCD SUBTRACT @–BC --- --- 456
WITH CARRY
417 –BCL DOUBLE BCD @–BCL --- --- 457
SUBTRACT WITH
CARRY

138
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Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
420 * SIGNED BINARY @* --- --- 459
MULTIPLY
421 *L DOUBLE SIGNED @*L --- --- 461
BINARY MULTIPLY
422 *U UNSIGNED BINARY @*U --- --- 463
MULTIPLY
423 *UL DOUBLE UNSIGNED @*UL --- --- 465
BINARY MULTIPLY
424 *B BCD MULTIPLY @*B --- --- 467
425 *BL DOUBLE BCD @*BL --- --- 469
MULTIPLY
430 / SIGNED BINARY @/ --- --- 471
DIVIDE
431 /L DOUBLE SIGNED @/L --- --- 473
BINARY DIVIDE
432 /U UNSIGNED BINARY @/U --- --- 475
DIVIDE
433 /UL DOUBLE UNSIGNED @/UL --- --- 477
BINARY DIVIDE
434 /B BCD DIVIDE @/B --- --- 479
435 /BL DOUBLE BCD DIVIDE @/BL --- --- 481
448 FSTR FLOATING POINT TO @FSTR --- --- 640
ASCII
449 FVAL ASCII TO FLOATING @FVAL --- --- 645
POINT
450 FIX FLOATING TO 16-BIT @FIX --- --- 594
451 FIXL FLOATING TO 32-BIT @FIXL --- --- 596
452 FLT 16-BIT TO FLOATING @FLT --- --- 597
453 FLTL 32-BIT TO FLOATING @FLTL --- --- 599
454 +F FLOATING-POINT @+F --- --- 601
ADD
455 –F FLOATING-POINT @–F --- --- 603
SUBTRACT
456 *F FLOATING-POINT @*F --- --- 605
MULTIPLY
457 /F FLOATING-POINT @/F --- --- 607
DIVIDE
458 RAD DEGREES TO @RAD --- --- 633
RADIANS
459 DEG RADIANS-TO @DEG --- --- 610
DEGREES
460 SIN SINE @SIN --- --- 612
461 COS COSINE @COS --- --- 615
462 TAN TANGENT @TAN --- --- 619
463 ASIN ARC SINE @ASIN --- --- 623
464 ACOS ARC COSINE @ACOS --- --- 625
465 ATAN ARC TANGENT @ATAN --- --- 627
466 SQRT SQUARE ROOT @SQRT --- --- 629
467 EXP EXPONENT @EXP --- --- 631
468 LOG LOGARITHM @LOG --- --- 633
469 MOVF MOVE FLOATING- @MOVF --- --- 649
POINT (SINGLE)
470 BINS SIGNED BCD TO @BINS --- --- 517
BINARY
471 BCDS SIGNED BINARY TO @BCDS --- --- 523
BCD
472 BISL DOUBLE SIGNED @BISL --- --- 520
BCD TO BINARY

139
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Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
473 BDSL DOUBLE SIGNED @BDSL --- --- 525
BINARY TO BCD
474 GRY GRAY CODE CON- @GRY --- --- 529
VERSION
475 SINQ HIGH-SPEED SINE @SINQ --- --- 614
476 COSQ HIGH-SPEED COSINE @COSQ --- --- 617
477 TANQ HIGH-SPEED TAN- @TANQ --- --- 621
GENT
486 SCL2 SCALING 2 @SCL2 --- --- 800
487 SCL3 SCALING 3 @SCL3 --- --- 804
490 CMND DELIVER COMMAND @CMND --- --- 1056
498 MOVL DOUBLE MOVE @MOVL --- --- 334
499 MVNL DOUBLE MOVE NOT @MVNL --- --- 336
502 BCMP2 EXPANDED BLOCK @BCMP2 --- --- 322
COMPARE
510 CJP CONDITIONAL JUMP --- --- --- 232
511 CJPN CONDITIONAL JUMP --- --- --- 232
512 FOR FOR-NEXT LOOPS --- --- --- 238
513 NEXT FOR-NEXT LOOPS --- --- --- 238
514 BREAK BREAK LOOP --- --- --- 241
515 JMP0 MULTIPLE JUMP --- --- --- 236
516 JME0 MULTIPLE JUMP END --- --- --- 236
517 MILH MULTI-INTERLOCK --- --- --- 214
DIFFERENTIATION
HOLD
518 MILR MULTI-INTERLOCK --- --- --- 214
DIFFERENTIATION
RELEASE
519 MILC MULTI-INTERLOCK --- --- --- 214
CLEAR
520 NOT NOT --- --- --- 180
521 UP CONDITION ON --- --- --- 181
522 DOWN CONDITION OFF --- --- --- 181
530 SETA MULTIPLE BIT SET @SETA --- --- 198
531 RSTA MULTIPLE BIT RESET @RSTA --- --- 198
532 SETB SINGLE BIT SET @SETB --- !SETB 201
533 RSTB SINGLE BIT RESET @RSTB --- !RSTB 201
534 OUTB SINGLE BIT OUTPUT @OUTB --- !OUTB 204
540 TMHH ONE-MS TIMER --- --- --- 253
541 TIMU TENTH-MS TIMER --- --- --- 256
542 TIML LONG TIMER --- --- --- 266
543 MTIM MULTI-OUTPUT --- --- --- 269
TIMER
544 TMUH HUNDREDTH-MS --- --- --- 259
TIMER
545 CNR RESET TIMER/ @CNR --- --- 282
COUNTER
546 CNTX COUNTER --- --- --- 275
547 CNRX RESET TIMER/ --- --- --- 282
COUNTER
548 CNTRX REVERSIBLE --- --- --- 278
COUNTER
550 TIMX HUNDRED-MS TIMER --- --- --- 245
551 TIMHX TEN-MS TIMER --- --- --- 249
552 TMHHX ONE-MS TIMER --- --- --- 253
553 TIMLX LONG TIMER --- --- --- 266

140
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Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
554 MTIMX MULTI-OUTPUT --- --- --- 269
TIMER
555 TTIMX ACCUMULATIVE --- --- --- 262
TIMER
556 TIMUX TENTH-MS TIMER --- --- --- 256
557 TMUHX HUNDREDTH-MS --- --- --- 259
TIMER
560 MOVR MOVE TO REGISTER @MOVR --- --- 356
561 MOVRW MOVE TIMER/ @MOVRW --- --- 358
COUNTER PV TO
REGISTER
562 XCGL DOUBLE DATA @XCGL --- --- 350
EXCHANGE
565 XFERC BLOCK TRANSFER @XFERC --- --- 1263
566 DISTC SINGLE WORD @DISTC --- --- 1266
DISTRIBUTE
567 COLLC DATA COLLECT @COLLC --- --- 1269
568 MOVBC MOVE BIT @MOVBC --- --- 1273
570 ASLL DOUBLE SHIFT LEFT @ASLL --- --- 371
571 ASRL DOUBLE SHIFT @ASRL --- --- 374
RIGHT
572 ROLL DOUBLE ROTATE @ROLL --- --- 378
LEFT
573 RORL DOUBLE ROTATE @RORL --- --- 381
RIGHT
574 RLNC ROTATE LEFT @RLNC --- --- 383
WITHOUT CARRY
575 RRNC ROTATE RIGHT @RRNC --- --- 387
WITHOUT CARRY
576 RLNL DOUBLE ROTATE @RLNL --- --- 385
LEFT WITHOUT
CARRY
577 RRNL DOUBLE ROTATE @RRNL --- --- 388
RIGHT WITHOUT
CARRY
578 NSFL SHIFT N-BIT DATA @NSFL --- --- 393
LEFT
579 NSFR SHIFT N-BIT DATA @NSFR --- --- 395
RIGHT
580 NASL SHIFT N-BITS LEFT @NASL --- --- 397
581 NASR SHIFT N-BITS RIGHT @NASR --- --- 403
582 NSLL DOUBLE SHIFT @NSLL --- --- 400
N-BITS LEFT
583 NSRL DOUBLE SHIFT @NSRL --- --- 405
N-BITS RIGHT
590 ++ INCREMENT BINARY @++ --- --- 409
591 ++L DOUBLE @++L --- --- 411
INCREMENT BINARY
592 –– DECREMENT BINARY @– – --- --- 413
593 – –L DOUBLE @– –L --- --- 415
DECREMENT BINARY
594 ++B INCREMENT BCD @++B --- --- 417
595 ++BL DOUBLE @++BL --- --- 419
INCREMENT BCD
596 – –B DECREMENT BCD @– –B --- --- 421
597 – –BL DOUBLE DECRE- @– –BL --- --- 423
MENT BCD
600 SIGN 16-BIT TO 32-BIT @SIGN --- --- 494
SIGNED BINARY
601 STR4 FOUR-DIGIT NUM- @STR4 --- --- 534
BER TO ASCII

141
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Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
602 STR8 EIGHT-DIGIT NUMBER @STR8 --- --- 537
TO ASCII
603 STR16 SIXTEEN-DIGIT NUM- @STR16 --- --- 539
BER TO ASCII
604 NUM4 ASCII TO FOUR-DIGIT @NUM4 --- --- 541
NUMBER
605 NUM8 ASCII TO EIGHT-DIGIT @NUM8 --- --- 544
NUMBER
606 NUM16 ASCII TO SIXTEEN- @NUM16 --- --- 545
DIGIT NUMBER
610 ANDL DOUBLE LOGICAL @ANDL --- --- 550
AND
611 ORWL DOUBLE LOGICAL OR @ORWL --- --- 553
612 XORL DOUBLE EXCLUSIVE @XORL --- --- 557
OR
613 XNRL DOUBLE EXCLUSIVE @XNRL --- --- 560
NOR
614 COML DOUBLE @COML --- --- 564
COMPLEMENT
620 ROTB BINARY ROOT @ROTB --- --- 565
621 BCNTC BIT COUNTER @BCNTC --- --- 1275
630 SSET SET STACK @SSET --- --- 703
631 DIM DIMENSION RECORD @DIM --- --- 715
TABLE
632 PUSH PUSH ONTO STACK @PUSH --- --- 706
633 FIFO FIRST IN FIRST OUT @FIFO --- --- 709
634 LIFO LAST IN FIRST OUT @LIFO --- --- 712
635 SETR SET RECORD LOCA- @SETR --- --- 718
TION
636 GETR GET RECORD @GETR --- --- 720
NUMBER
637 SWAP SWAP BYTES @SWAP --- --- 725
638 SNUM STACK SIZE READ @SNUM --- --- 742
639 SREAD STACK DATA READ @SREAD --- --- 744
640 SWRIT STACK DATA WRITE @SWRIT --- --- 747
641 SINS STACK DATA INSERT @SINS --- --- 750
642 SDEL STACK DATA DELETE @SDEL --- --- 753
650 LEN$ STRING LENGTH @LEN$ --- --- 1235
652 LEFT$ GET STRING LEFT @LEFT$ --- --- 1226
653 RGHT$ GET STRING RIGHT @RGHT$ --- --- 1228
654 MID$ GET STRING MIDDLE @MID$ --- --- 1230
656 +$ CONCATENATE @+$ --- --- 1223
STRING
657 INS$ INS$ @INS$ --- --- 1246
658 DEL$ DELETE STRING @DEL$ --- --- 1240
660 FIND$ FIND IN STRING @FIND$ --- --- 1233
661 RPLC$ REPLACE IN STRING @RPLC$ --- --- 1237
664 MOV$ MOV STRING @MOV$ --- --- 1221
665 XCHG$ EXCHANGE STRING @XCHG$ --- --- 1242
666 CLR$ CLEAR STRING @CLR$ --- --- 1245
670 AND =$ AND STRING EQUALS --- --- --- 1250
670 LD =$ LOAD STRING --- --- --- 1250
EQUALS
670 OR =$ OR STRING EQUALS --- --- --- 1250
671 AND <>$ AND STRING NOT --- --- --- 1250
EQUAL

142
List of Instructions by Function Code Section 2-4

Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
671 LD <>$ LOAD STRING NOT --- --- --- 1250
EQUAL
671 OR <>$ OR STRING NOT --- --- --- 1250
EQUAL
672 AND <$ AND STRING LESS --- --- --- 1250
THAN
672 LD <$ LOAD STRING LESS --- --- --- 1250
THAN
672 OR <$ OR STRING LESS --- --- --- 1250
THAN
673 AND <=$ AND STRING LESS --- --- --- 1250
THAN OR EQUALS
673 LD <=$ LOAD STRING LESS --- --- --- 1250
THAN OR EQUAL
673 OR <=$ OR STRING LESS --- --- --- 1250
THAN OR EQUALS
674 AND >$ AND STRING --- --- --- 1250
GREATER THAN
674 LD >$ LOAD STRING --- --- --- 1250
GREATER THAN
674 OR >$ OR STRING GREATER --- --- --- 1250
THAN
675 AND >=$ AND STRING --- --- --- 1250
GREATER THAN OR
EQUALS
675 LD >=$ LOAD STRING --- --- --- 1250
GREATER THAN OR
EQUALS
675 OR >=$ OR STRING GREATER --- --- --- 1250
THAN OR EQUALS
680 LMT LIMIT CONTROL @LMT --- --- 779
681 BAND DEAD BAND @BAND --- --- 781
CONTROL
682 ZONE DEAD ZONE @ZONE --- --- 784
CONTROL
685 TPO TIME-PROPOR- --- --- --- 787
TIONAL OUTPUT
690 MSKS SET INTERRUPT @MSKS --- --- 839
MASK
691 CLI CLEAR INTERRUPT @CLI --- --- 851
692 MSKR READ INTERRUPT @MSKR --- --- 846
MASK
693 DI DISABLE @DI --- --- 855
INTERRUPTS
694 EI ENABLE --- --- --- 858
INTERRUPTS
700 FREAD READ DATA FILE @FREAD --- --- 1099
701 FWRIT WRITE DATA FILE @FWRIT --- --- 1106
704 TWRIT WRITE TEXT TILE @TWRIT --- --- 1113
720 EXPLT EXPLICIT MESSAGE @EXPLT --- --- 1066
SEND
721 EGATR EXPLICIT GET @EGATR --- --- 1074
ATTRIBUTE
722 ESATR EXPLICIT SET @ESATR --- --- 1081
ATTRIBUTE
723 ECHRD EXPLICIT WORD @ECHRD --- --- 1087
READ
724 ECHWR EXPLICIT WORD @ECHWR --- --- 1091
CLEAR
730 CADD CALENDAR ADD @CADD --- --- 1122
731 CSUB CALENDAR @CSUB --- --- 1126
SUBTRACT

143
List of Instructions by Function Code Section 2-4

Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
735 DATE CLOCK ADJUSTMENT @DATE --- --- 1134
750 GSBS GLOBAL SUBROU- @GSBS --- --- 824
TINE CALL
751 GSBN GLOBAL SUBROU- --- --- --- 832
TINE ENTRY
752 GRET GLOBAL SUBROU- --- --- --- 835
TINE RETURN
801 BEND BLOCK PROGRAM --- --- --- 1191
END
802 IF CONDITIONAL --- --- --- 1196
BRANCHING BLOCK
802 IF CONDITIONAL --- --- --- 1196
BRANCHING BLOCK
802 IF NOT CONDITIONAL --- --- --- 1196
BRANCHING BLOCK
NOT
803 ELSE ELSE --- --- --- 1196
804 IEND IF END --- --- --- 1196
805 WAIT ONE CYCLE AND --- --- --- 1202
WAIT
805 WAIT ONE CYCLE AND --- --- --- 1202
WAIT
805 WAIT NOT ONE CYCLE AND --- --- --- 1202
WAIT NOT
806 EXIT CONDITIONAL BLOCK --- --- --- 1199
EXIT
806 EXIT CONDITIONAL BLOCK --- --- --- 1199
EXIT
806 EXIT NOT CONDITIONAL BLOCK --- --- --- 1199
EXIT NOT
809 LOOP LOOP --- --- --- 1215
810 LEND LOOP END --- --- --- 1215
810 LEND LOOP END --- --- --- 1215
810 LEND NOT LOOP END NOT --- --- --- 1215
811 BPPS BLOCK PROGRAM --- --- --- 1193
PAUSE
812 BPRS BLOCK PROGRAM --- --- --- 1193
RESTART
813 TIMW HUNDRED-MS TIMER --- --- --- 1206
WAIT
814 CNTW COUNTER WAIT --- --- --- 1209
815 TMHW TEN-MS TIMER WAIT --- --- --- 1212
816 TIMWX HUNDRED-MS TIMER --- --- --- 1206
WAIT
817 TMHWX TEN-MS TIMER WAIT --- --- --- 1212
818 CNTWX COUNTER WAIT --- --- --- 1209
820 TKON TASK ON @TKON --- --- 1255
821 TKOF TASK OFF @TKOF --- --- 1258
840 PWR EXPONENTIAL @PWR --- --- 635
POWER
841 FIXD DOUBLE FLOATING @FIXD --- --- 657
TO 16-BIT BINARY
842 FIXLD DOUBLE FLOATING @FIXLD --- --- 658
TO 32-BIT BINARY
843 DBL 16-BIT BINARY TO @DBL --- --- 660
DOUBLE FLOATING
844 DBLL 32-BIT BINARY TO @DBLL --- --- 661
DOUBLE FLOATING
845 +D DOUBLE FLOATING- @+D --- --- 663
POINT ADD

144
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Function code Mnemonic Instruction Upward Downward Immediate Page

Differentiation Differentiation Refreshing
Specification
846 −D DOUBLE FLOATING- @−D --- --- 665
POINT SUBTRACT
847 *D DOUBLE FLOATING- @*D --- --- 667
POINT MULTIPLY
848 /D DOUBLE FLOATING- @/D --- --- 669
POINT DIVIDE
849 RADD DOUBLE DEGREES @RADD --- --- 671
TO RADIANS
850 DEGD DOUBLE RADIANS TO @RADD --- --- 673
DEGREES
851 SIND DOUBLE SINE @SIND --- --- 674
852 COSD DOUBLE COSINE @COSD --- --- 676
853 TAND DOUBLE TANGENT @TAND --- --- 678
854 ASIND DOUBLE ARC SINE @ASIND --- --- 680
855 ACOSD DOUBLE ARC @ACOSD --- --- 682
COSINE
856 ATAND DOUBLE ARC TAN- @ATAND --- --- 684
GENT
857 SQRTD DOUBLE SQUARE @SQRTD --- --- 686
ROOT
858 EXPD DOUBLE EXPONENT @EXPD --- --- 688
859 LOGD DOUBLE LOGARITHM @LOGD --- --- 690
860 PWRD DOUBLE EXPONEN- @PWRD --- --- 692
TIAL POWER
880 INI MODE CONTROL @INI --- --- 864
881 PRV HIGH-SPEED @PRV --- --- 868
COUNTER PV READ
882 CTBL COMPARISON TABLE @CTBL --- --- 878
LOAD
883 PRV2 COUNTER FRE- @PRV2 --- --- 874
QUENCY CONVERT
885 SPED SPEED OUTPUT @SPED --- --- 882
886 PULS SET PULSES @PULS --- --- 887
887 PLS2 PULSE OUTPUT @PLS2 --- --- 890
888 ACC ACCELERATION CON- @ACC --- --- 896
TROL
889 ORG ORIGIN SEARCH @ORG --- --- 903
891 PWN PULSE WITH VARI- @PWN --- --- 906
ABLE DUTY FACTOR

145
List of Instructions by Function Code Section 2-4

146
 SECTION 3
Instructions

This section describes each of the instructions that can be used in programming CS/CJ-series PLCs. Instructions are
described in order of function, as classified in Section 2 Summary of Instructions.

3-1 Notation and Layout of Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

3-2 Instruction Upgrades and New Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3-2-1 Upgrades for CS1-H/CJ1-H CPU Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3-3 Sequence Input Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3-3-1 LOAD: LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3-3-2 LOAD NOT: LD NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
3-3-3 AND: AND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
3-3-4 AND NOT: AND NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
3-3-5 OR: OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
3-3-6 OR NOT: OR NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
3-3-7 AND LOAD: AND LD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
3-3-8 OR LOAD: OR LD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
3-3-9 Differentiated and Immediate Refreshing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 177
3-3-10 Operation Timing for I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
3-3-11 TR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
3-3-12 NOT: NOT(520) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
3-3-13 CONDITION ON/OFF: UP(521) and DOWN(522) . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
3-3-14 BIT TEST: TST(350) and TSTN(351) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3-4 Sequence Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
3-4-1 OUTPUT: OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
3-4-2 OUTPUT NOT: OUT NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
3-4-3 KEEP: KEEP(011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3-4-4 DIFFERENTIATE UP/DOWN: DIFU(013) and DIFD(014). . . . . . . . . . . . . . . . . . . . . 193
3-4-5 SET and RESET: SET and RSET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
3-4-6 MULTIPLE BIT SET/RESET: SETA(530)/RSTA(531) . . . . . . . . . . . . . . . . . . . . . . . . 198
3-4-7 SINGLE BIT SET/RESET: SETB(532)/RSTB(533) . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
3-4-8 SINGLE BIT OUTPUT: OUTB(534) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
3-5 Sequence Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3-5-1 END: END(001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3-5-2 NO OPERATION: NOP(000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
3-5-3 Overview of Interlock Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
3-5-4 INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003) . . . . . . . . . . . . . . . . 210
3-5-5 MULTI-INTERLOCK DIFFERENTIATION HOLD,
MULTI-INTERLOCK DIFFERENTIATION RELEASE, and
MULTI-INTERLOCK CLEAR: MILH(517), MILR(518), and MILC(519). . . . . . . . . 214
3-5-6 JUMP and JUMP END: JMP(004) and JME(005). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
3-5-7 CONDITIONAL JUMP: CJP(510)/CJPN(511) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
3-5-8 MULTIPLE JUMP and JUMP END: JMP0(515) and JME0(516) . . . . . . . . . . . . . . . . 236
3-5-9 FOR-NEXT LOOPS: FOR(512)/NEXT(513) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
3-5-10 BREAK LOOP: BREAK(514) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
3-6 Timer and Counter Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
3-6-1 HUNDRED-MS TIMER: TIM/TIMX(550). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
3-6-2 TEN-MS TIMER: TIMH(015)/TIMHX(551) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
3-6-3 ONE-MS TIMER: TMHH(540)/TMHHX(552). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
3-6-4 TENTH-MS TIMER: TIMU(541)/TIMUX(556). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
3-6-5 HUNDREDTH-MS TIMER: TMUH(544)/TMUHX(557) . . . . . . . . . . . . . . . . . . . . . . 259
3-6-6 ACCUMULATIVE TIMER: TTIM(087)/TTIMX(555) . . . . . . . . . . . . . . . . . . . . . . . . 262
3-6-7 LONG TIMER: TIML(542)/TIMLX(553). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

147
 3-6-8 MULTI-OUTPUT TIMER: MTIM(543)/MTIMX(554) . . . . . . . . . . . . . . . . . . . . . . . . 269
3-6-9 COUNTER: CNT/CNTX(546). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
3-6-10 REVERSIBLE COUNTER: CNTR(012)/CNTRX(548) . . . . . . . . . . . . . . . . . . . . . . . . 278
3-6-11 RESET TIMER/COUNTER: CNR(545)/CNRX(547). . . . . . . . . . . . . . . . . . . . . . . . . . 282
3-6-12 Example Timer and Counter Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
3-6-13 Indirect Addressing of Timer/Counter Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
3-7 Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
3-7-1 Input Comparison Instructions (300 to 328). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
3-7-2 Time Comparison Instructions (341 to 346). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
3-7-3 COMPARE: CMP(020) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
3-7-4 DOUBLE COMPARE: CMPL(060) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
3-7-5 SIGNED BINARY COMPARE: CPS(114) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
3-7-6 DOUBLE SIGNED BINARY COMPARE: CPSL(115) . . . . . . . . . . . . . . . . . . . . . . . . 312
3-7-7 MULTIPLE COMPARE: MCMP(019) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
3-7-8 TABLE COMPARE: TCMP(085) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
3-7-9 BLOCK COMPARE: BCMP(068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
3-7-10 EXPANDED BLOCK COMPARE: BCMP2(502). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
3-7-11 AREA RANGE COMPARE: ZCP(088). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
3-7-12 DOUBLE AREA RANGE COMPARE: ZCPL(116) . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
3-8 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
3-8-1 MOVE: MOV(021). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
3-8-2 MOVE NOT: MVN(022) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
3-8-3 DOUBLE MOVE: MOVL(498) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
3-8-4 DOUBLE MOVE NOT: MVNL(499) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
3-8-5 MOVE BIT: MOVB(082) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
3-8-6 MOVE DIGIT: MOVD(083) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
3-8-7 MULTIPLE BIT TRANSFER: XFRB(062). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
3-8-8 BLOCK TRANSFER: XFER(070) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
3-8-9 BLOCK SET: BSET(071) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
3-8-10 DATA EXCHANGE: XCHG(073) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
3-8-11 DOUBLE DATA EXCHANGE: XCGL(562) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
3-8-12 SINGLE WORD DISTRIBUTE: DIST(080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
3-8-13 DATA COLLECT: COLL(081) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
3-8-14 MOVE TO REGISTER: MOVR(560) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
3-8-15 MOVE TIMER/COUNTER PV TO REGISTER: MOVRW(561). . . . . . . . . . . . . . . . . 358
3-9 Data Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
3-9-1 SHIFT REGISTER: SFT(010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
3-9-2 REVERSIBLE SHIFT REGISTER: SFTR(084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
3-9-3 ASYNCHRONOUS SHIFT REGISTER: ASFT(017). . . . . . . . . . . . . . . . . . . . . . . . . . 365
3-9-4 WORD SHIFT: WSFT(016). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
3-9-5 ARITHMETIC SHIFT LEFT: ASL(025). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
3-9-6 DOUBLE SHIFT LEFT: ASLL(570). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
3-9-7 ARITHMETIC SHIFT RIGHT: ASR(026) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
3-9-8 DOUBLE SHIFT RIGHT: ASRL(571) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
3-9-9 ROTATE LEFT: ROL(027). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
3-9-10 DOUBLE ROTATE LEFT: ROLL(572) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
3-9-11 ROTATE RIGHT: ROR(028) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
3-9-12 DOUBLE ROTATE RIGHT: RORL(573) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
3-9-13 ROTATE LEFT WITHOUT CARRY: RLNC(574) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
3-9-14 DOUBLE ROTATE LEFT WITHOUT CARRY: RLNL(576). . . . . . . . . . . . . . . . . . . . 385
3-9-15 ROTATE RIGHT WITHOUT CARRY: RRNC(575) . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
3-9-16 DOUBLE ROTATE RIGHT WITHOUT CARRY: RRNL(577) . . . . . . . . . . . . . . . . . . 388
3-9-17 ONE DIGIT SHIFT LEFT: SLD(074) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
3-9-18 ONE DIGIT SHIFT RIGHT: SRD(075). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
3-9-19 SHIFT N-BIT DATA LEFT: NSFL(578) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
3-9-20 SHIFT N-BIT DATA RIGHT: NSFR(579). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
3-9-21 SHIFT N-BITS LEFT: NASL(580) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

148
 3-9-22 DOUBLE SHIFT N-BITS LEFT: NSLL(582) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
3-9-23 SHIFT N-BITS RIGHT: NASR(581) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
3-9-24 DOUBLE SHIFT N-BITS RIGHT: NSRL(583) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
3-10 Increment/Decrement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
3-10-1 INCREMENT BINARY: ++(590) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
3-10-2 DOUBLE INCREMENT BINARY: ++L(591) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
3-10-3 DECREMENT BINARY: – –(592). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
3-10-4 DOUBLE DECREMENT BINARY: – –L(593). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
3-10-5 INCREMENT BCD: ++B(594) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
3-10-6 DOUBLE INCREMENT BCD: ++BL(595) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
3-10-7 DECREMENT BCD: – –B(596) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
3-10-8 DOUBLE DECREMENT BCD: – –BL(597). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
3-11 Symbol Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
3-11-1 SIGNED BINARY ADD WITHOUT CARRY: +(400) . . . . . . . . . . . . . . . . . . . . . . . . . 426
3-11-2 DOUBLE SIGNED BINARY ADD WITHOUT CARRY: +L(401) . . . . . . . . . . . . . . . 428
3-11-3 SIGNED BINARY ADD WITH CARRY: +C(402). . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
3-11-4 DOUBLE SIGNED BINARY ADD WITH CARRY: +CL(403) . . . . . . . . . . . . . . . . . . 432
3-11-5 BCD ADD WITHOUT CARRY: +B(404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
3-11-6 DOUBLE BCD ADD WITHOUT CARRY: +BL(405) . . . . . . . . . . . . . . . . . . . . . . . . . 435
3-11-7 BCD ADD WITH CARRY: +BC(406) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
3-11-8 DOUBLE BCD ADD WITH CARRY: +BCL(407). . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
3-11-9 SIGNED BINARY SUBTRACT WITHOUT CARRY: –(410) . . . . . . . . . . . . . . . . . . . 440
3-11-10 DOUBLE SIGNED BINARY SUBTRACT WITHOUT CARRY: –L(411) . . . . . . . . . 442
3-11-11 SIGNED BINARY SUBTRACT WITH CARRY: –C(412) . . . . . . . . . . . . . . . . . . . . . . 446
3-11-12 DOUBLE SIGNED BINARY SUBTRACT WITH CARRY: –CL(413) . . . . . . . . . . . . 448
3-11-13 BCD SUBTRACT WITHOUT CARRY: –B(414) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
3-11-14 DOUBLE BCD SUBTRACT WITHOUT CARRY: –BL(415) . . . . . . . . . . . . . . . . . . . 452
3-11-15 BCD SUBTRACT WITH CARRY: –BC(416). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
3-11-16 DOUBLE BCD SUBTRACT WITH CARRY: –BCL(417) . . . . . . . . . . . . . . . . . . . . . . 457
3-11-17 SIGNED BINARY MULTIPLY: *(420). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
3-11-18 DOUBLE SIGNED BINARY MULTIPLY: *L(421) . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
3-11-19 UNSIGNED BINARY MULTIPLY: *U(422) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
3-11-20 DOUBLE UNSIGNED BINARY MULTIPLY: *UL(423). . . . . . . . . . . . . . . . . . . . . . . 465
3-11-21 BCD MULTIPLY: *B(424). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
3-11-22 DOUBLE BCD MULTIPLY: *BL(425). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
3-11-23 SIGNED BINARY DIVIDE: /(430) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
3-11-24 DOUBLE SIGNED BINARY DIVIDE: /L(431) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
3-11-25 UNSIGNED BINARY DIVIDE: /U(432) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
3-11-26 DOUBLE UNSIGNED BINARY DIVIDE: /UL(433). . . . . . . . . . . . . . . . . . . . . . . . . . 477
3-11-27 BCD DIVIDE: /B(434). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
3-11-28 DOUBLE BCD DIVIDE: /BL(435) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
3-12 Conversion Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
3-12-1 BCD TO BINARY: BIN(023). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
3-12-2 DOUBLE BCD TO DOUBLE BINARY: BINL(058) . . . . . . . . . . . . . . . . . . . . . . . . . . 485
3-12-3 BINARY TO BCD: BCD(024) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
3-12-4 DOUBLE BINARY TO DOUBLE BCD: BCDL(059) . . . . . . . . . . . . . . . . . . . . . . . . . 489
3-12-5 2’S COMPLEMENT: NEG(160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
3-12-6 DOUBLE 2’S COMPLEMENT: NEGL(161) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
3-12-7 16-BIT TO 32-BIT SIGNED BINARY: SIGN(600) . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
3-12-8 DATA DECODER: MLPX(076) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
3-12-9 DATA ENCODER: DMPX(077) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
3-12-10 ASCII CONVERT: ASC(086) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
3-12-11 ASCII TO HEX: HEX(162) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
3-12-12 COLUMN TO LINE: LINE(063). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
3-12-13 LINE TO COLUMN: COLM(064) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
3-12-14 SIGNED BCD TO BINARY: BINS(470). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
3-12-15 DOUBLE SIGNED BCD TO BINARY: BISL(472) . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

149
 3-12-16 SIGNED BINARY TO BCD: BCDS(471) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
3-12-17 DOUBLE SIGNED BINARY TO BCD: BDSL(473) . . . . . . . . . . . . . . . . . . . . . . . . . . 525
3-12-18 GRAY CODE CONVERT: GRY(474) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
3-12-19 FOUR-DIGIT NUMBER TO ASCII: STR4(601) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
3-12-20 EIGHT-DIGIT NUMBER TO ASCII: STR8(602). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
3-12-21 SIXTEEN-DIGIT NUMBER TO ASCII: STR16(603) . . . . . . . . . . . . . . . . . . . . . . . . . 539
3-12-22 ASCII TO FOUR-DIGIT NUMBER: NUM4(604) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
3-12-23 ASCII TO EIGHT-DIGIT NUMBER: NUM8(605). . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
3-12-24 ASCII TO SIXTEEN-DIGIT NUMBER: NUM16(606) . . . . . . . . . . . . . . . . . . . . . . . . 545
3-13 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
3-13-1 LOGICAL AND: ANDW(034) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
3-13-2 DOUBLE LOGICAL AND: ANDL(610) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
3-13-3 LOGICAL OR: ORW(035) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
3-13-4 DOUBLE LOGICAL OR: ORWL(611). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
3-13-5 EXCLUSIVE OR: XORW(036). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
3-13-6 DOUBLE EXCLUSIVE OR: XORL(612). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
3-13-7 EXCLUSIVE NOR: XNRW(037) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
3-13-8 DOUBLE EXCLUSIVE NOR: XNRL(613) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
3-13-9 COMPLEMENT: COM(029) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
3-13-10 DOUBLE COMPLEMENT: COML(614) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
3-14 Special Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
3-14-1 BINARY ROOT: ROTB(620). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
3-14-2 BCD SQUARE ROOT: ROOT(072). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
3-14-3 ARITHMETIC PROCESS: APR(069) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
3-14-4 FLOATING POINT DIVIDE: FDIV(079) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
3-14-5 BIT COUNTER: BCNT(067). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
3-15 Floating-point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
3-15-1 FLOATING TO 16-BIT: FIX(450). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
3-15-2 FLOATING TO 32-BIT: FIXL(451) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
3-15-3 16-BIT TO FLOATING: FLT(452) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
3-15-4 32-BIT TO FLOATING: FLTL(453) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
3-15-5 FLOATING-POINT ADD: +F(454). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
3-15-6 FLOATING-POINT SUBTRACT: –F(455) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
3-15-7 FLOATING-POINT MULTIPLY: *F(456) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
3-15-8 FLOATING-POINT DIVIDE: /F(457) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
3-15-9 DEGREES TO RADIANS: RAD(458) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
3-15-10 RADIANS TO DEGREES: DEG(459) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
3-15-11 SINE: SIN(460) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
3-15-12 HIGH-SPEED SINE: SINQ(475). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
3-15-13 COSINE: COS(461) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
3-15-14 HIGH-SPEED COSINE: COSQ(476) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
3-15-15 TANGENT: TAN(462) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
3-15-16 HIGH-SPEED TANGENT: TANQ(477) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
3-15-17 ARC SINE: ASIN(463) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
3-15-18 ARC COSINE: ACOS(464) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
3-15-19 ARC TANGENT: ATAN(465) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
3-15-20 SQUARE ROOT: SQRT(466) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
3-15-21 EXPONENT: EXP(467) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
3-15-22 LOGARITHM: LOG(468) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
3-15-23 EXPONENTIAL POWER: PWR(840) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
3-15-24 Single-precision Floating-point Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . 636
3-15-25 FLOATING-POINT TO ASCII: FSTR(448) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
3-15-26 ASCII TO FLOATING-POINT: FVAL(449) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
3-15-27 MOVE FLOATING-POINT (SINGLE): MOVF(469) . . . . . . . . . . . . . . . . . . . . . . . . . . 649
3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) . . . . . . . . 651
3-16-1 DOUBLE FLOATING TO 16-BIT: FIXD(841). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
3-16-2 DOUBLE FLOATING TO 32-BIT: FIXLD(842) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

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 3-16-3 16-BIT TO DOUBLE FLOATING: DBL(843) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
3-16-4 32-BIT TO DOUBLE FLOATING: DBLL(844) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
3-16-5 DOUBLE FLOATING-POINT ADD: +D(845) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
3-16-6 DOUBLE FLOATING-POINT SUBTRACT: –D(846) . . . . . . . . . . . . . . . . . . . . . . . . . 665
3-16-7 DOUBLE FLOATING-POINT MULTIPLY: *D(847). . . . . . . . . . . . . . . . . . . . . . . . . . 668
3-16-8 DOUBLE FLOATING-POINT DIVIDE: /D(848) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
3-16-9 DOUBLE DEGREES TO RADIANS: RADD(849) . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
3-16-10 DOUBLE RADIANS TO DEGREES: DEGD(850) . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
3-16-11 DOUBLE SINE: SIND(851) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
3-16-12 DOUBLE COSINE: COSD(852) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
3-16-13 DOUBLE TANGENT: TAND(853) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
3-16-14 DOUBLE ARC SINE: ASIND(854) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
3-16-15 DOUBLE ARC COSINE: ACOSD(855) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
3-16-16 DOUBLE ARC TANGENT: ATAND(856) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
3-16-17 DOUBLE SQUARE ROOT: SQRTD(857) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
3-16-18 DOUBLE EXPONENT: EXPD(858) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
3-16-19 DOUBLE LOGARITHM: LOGD(859) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
3-16-20 DOUBLE EXPONENTIAL POWER: PWRD(860) . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
3-16-21 Double-precision Floating-point Input Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
3-17 Table Data Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
3-17-1 SET STACK: SSET(630) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
3-17-2 PUSH ONTO STACK: PUSH(632) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
3-17-3 FIRST IN FIRST OUT: FIFO(633) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
3-17-4 LAST IN FIRST OUT: LIFO(634) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
3-17-5 DIMENSION RECORD TABLE: DIM(631). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
3-17-6 SET RECORD LOCATION: SETR(635) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
3-17-7 GET RECORD NUMBER: GETR(636) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
3-17-8 DATA SEARCH: SRCH(181) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
3-17-9 SWAP BYTES: SWAP(637). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
3-17-10 FIND MAXIMUM: MAX(182) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
3-17-11 FIND MINIMUM: MIN(183) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
3-17-12 SUM: SUM(184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
3-17-13 FRAME CHECKSUM: FCS(180) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
3-17-14 STACK SIZE READ: SNUM(638) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
3-17-15 STACK DATA READ: SREAD(639). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
3-17-16 STACK DATA OVERWRITE: SWRIT(640) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
3-17-17 STACK DATA INSERT: SINS(641). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
3-17-18 STACK DATA DELETE: SDEL(642) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
3-18 Data Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
3-18-1 PID CONTROL: PID(190) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
3-18-2 PID CONTROL WITH AUTOTUNING: PIDAT(191) . . . . . . . . . . . . . . . . . . . . . . . . . 769
3-18-3 LIMIT CONTROL: LMT(680) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
3-18-4 DEAD BAND CONTROL: BAND(681) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
3-18-5 DEAD ZONE CONTROL: ZONE(682) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
3-18-6 TIME-PROPORTIONAL OUTPUT: TPO(685) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
3-18-7 SCALING: SCL(194). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
3-18-8 SCALING 2: SCL2(486) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
3-18-9 SCALING 3: SCL3(487) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
3-18-10 AVERAGE: AVG(195) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
3-19 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
3-19-1 SUBROUTINE CALL: SBS(091) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
3-19-2 MACRO: MCRO(099) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
3-19-3 SUBROUTINE ENTRY: SBN(092). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
3-19-4 SUBROUTINE RETURN: RET(093) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
3-19-5 GLOBAL SUBROUTINE CALL: GSBS(750) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
3-19-6 GLOBAL SUBROUTINE ENTRY: GSBN(751) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
3-19-7 GLOBAL SUBROUTINE RETURN: GRET(752) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835

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 3-20 Interrupt Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
3-20-1 SET INTERRUPT MASK: MSKS(690) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
3-20-2 READ INTERRUPT MASK: MSKR(692) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
3-20-3 CLEAR INTERRUPT: CLI(691) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
3-20-4 DISABLE INTERRUPTS: DI(693) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
3-20-5 ENABLE INTERRUPTS: EI(694) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
3-20-6 Summary of Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
3-21 High-speed Counter/Pulse Output Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
3-21-1 MODE CONTROL: INI(880) (CJ1M-CPU21/22/23 Only). . . . . . . . . . . . . . . . . . . . . . 864
3-21-2 HIGH-SPEED COUNTER PV READ: PRV(881) (CJ1M-CPU21/22/23 Only). . . . . . 868
3-21-3 COUNTER FREQUENCY CONVERT: PRV2(883). . . . . . . . . . . . . . . . . . . . . . . . . . . 874
3-21-4 REGISTER COMPARISON TABLE: CTBL(882) (CJ1M-CPU21/22/23 Only) . . . . . 878
3-21-5 SPEED OUTPUT: SPED(885) (CJ1M-CPU21/22/23 Only) . . . . . . . . . . . . . . . . . . . . . 882
3-21-6 SET PULSES: PULS(886) (CJ1M-CPU21/22/23 Only) . . . . . . . . . . . . . . . . . . . . . . . . 887
3-21-7 PULSE OUTPUT: PLS2(887) (CJ1M-CPU21/22/23 Only) . . . . . . . . . . . . . . . . . . . . . 890
3-21-8 ACCELERATION CONTROL: ACC(888) (CJ1M-CPU21/22/23 Only) . . . . . . . . . . . 896
3-21-9 ORIGIN SEARCH: ORG(889) (CJ1M-CPU21/22/23 Only). . . . . . . . . . . . . . . . . . . . . 903
3-21-10 PULSE WITH VARIABLE DUTY FACTOR: PWM(891) (CJ1M-CPU21/22/23 Only) 906
3-22 Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
3-22-1 STEP DEFINE and STEP START: STEP(008)/SNXT(009) . . . . . . . . . . . . . . . . . . . . . 909
3-23 Basic I/O Unit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
3-23-1 I/O REFRESH: IORF(097). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
3-23-2 SPECIAL I/O UNIT I/O REFRESH: FIORF(225) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
3-23-3 CPU BUS UNIT I/O REFRESH: DLNK(226) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
3-23-4 7-SEGMENT DECODER: SDEC(078) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
3-23-5 DIGITAL SWITCH INPUT – DSW(210) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
3-23-6 TEN KEY INPUT – TKY(211) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
3-23-7 HEXADECIMAL KEY INPUT – HKY(212) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
3-23-8 MATRIX INPUT: MTR(213) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
3-23-9 7-SEGMENT DISPLAY OUTPUT – 7SEG(214) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
3-23-10 INTELLIGENT I/O READ: IORD(222) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
3-23-11 INTELLIGENT I/O WRITE: IOWR(223) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
3-24 Serial Communications Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
3-24-1 Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
3-24-2 PROTOCOL MACRO: PMCR(260) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
3-24-3 TRANSMIT: TXD(236) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
3-24-4 RECEIVE: RXD(235) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
3-24-5 TRANSMIT VIA SERIAL COMMUNICATIONS UNIT: TXDU(256). . . . . . . . . . . . 1005
3-24-6 RECEIVE VIA SERIAL COMMUNICATIONS UNIT: RXDU(255) . . . . . . . . . . . . . 1013
3-24-7 CHANGE SERIAL PORT SETUP: STUP(237) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
3-25 Network Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
3-25-1 About SYSMAC NET Link/SYSMAC LINK Operations . . . . . . . . . . . . . . . . . . . . . . . 1026
3-25-2 About Explicit Message Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
3-25-3 NETWORK SEND: SEND(090) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
3-25-4 NETWORK RECEIVE: RECV(098) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
3-25-5 DELIVER COMMAND: CMND(490) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
3-25-6 EXPLICIT MESSAGE SEND: EXPLT(720). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
3-25-7 EXPLICIT GET ATTRIBUTE: EGATR(721) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
3-25-8 EXPLICIT SET ATTRIBUTE: ESATR(722). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
3-25-9 EXPLICIT WORD READ: ECHRD(723) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
3-25-10 EXPLICIT WORD WRITE: ECHWR(724) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
3-26 File Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
3-26-1 Precautions when Using Memory Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
3-26-2 READ DATA FILE: FREAD(700) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
3-26-3 WRITE DATA FILE: FWRIT(701) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
3-26-4 WRITE TEXT FILE: TWRIT(704) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113

152
3-27 Display Instructions: DISPLAY MESSAGE: MSG(046). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
3-28 Clock Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
3-28-1 CALENDAR ADD: CADD(730) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
3-28-2 CALENDAR SUBTRACT: CSUB(731) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
3-28-3 HOURS TO SECONDS: SEC(065) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
3-28-4 SECONDS TO HOURS: HMS(066) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
3-28-5 CLOCK ADJUSTMENT: DATE(735) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
3-29 Debugging Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
3-29-1 Trace Memory Sampling: TRSM(045). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
3-30 Failure Diagnosis Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
3-30-1 FAILURE ALARM: FAL(006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
3-30-2 SEVERE FAILURE ALARM: FALS(007) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
3-30-3 FAILURE POINT DETECTION: FPD(269) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156
3-31 Other Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
3-31-1 SET CARRY: STC(040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
3-31-2 CLEAR CARRY: CLC(041) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
3-31-3 SELECT EM BANK: EMBC(281) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
3-31-4 EXTEND MAXIMUM CYCLE TIME: WDT(094) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
3-31-5 SAVE CONDITION FLAGS: CCS(282) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
3-31-6 LOAD CONDITION FLAGS: CCL(283) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
3-31-7 CONVERT ADDRESS FROM CV: FRMCV(284) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
3-31-8 CONVERT ADDRESS TO CV: TOCV(285) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
3-31-9 DISABLE PERIPHERAL SERVICING: IOSP(287) (CS1-H/CJ1-H/CJ1M Only). . . . 1183
3-31-10 ENABLE PERIPHERAL SERVICING: IORS(288) (CS1-H/CJ1-H/CJ1M Only) . . . . 1185
3-32 Block Programming Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
3-32-1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
3-32-2 BLOCK PROGRAM BEGIN/END: BPRG(096)/BEND(801) . . . . . . . . . . . . . . . . . . . 1191
3-32-3 BLOCK PROGRAM PAUSE/RESTART: BPPS(811)/BPRS(812) . . . . . . . . . . . . . . . . 1193
3-32-4 Branching: IF(802), ELSE(803), and IEND(804) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
3-32-5 CONDITIONAL BLOCK EXIT (NOT): EXIT (NOT)(806) . . . . . . . . . . . . . . . . . . . . . 1199
3-32-6 ONE CYCLE AND WAIT (NOT): WAIT(805)/WAIT(805) NOT . . . . . . . . . . . . . . . . 1202
3-32-7 HUNDRED-MS TIMER WAIT: TIMW(813) and TIMWX(816) . . . . . . . . . . . . . . . . . 1206
3-32-8 COUNTER WAIT: CNTW(814) and CNTWX(818) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
3-32-9 TEN-MS TIMER WAIT: TMHW(815) and TMHWX(817) . . . . . . . . . . . . . . . . . . . . . 1212
3-32-10 Loop Control: LOOP(809)/LEND(810)/LEND(810) NOT . . . . . . . . . . . . . . . . . . . . . . 1215
3-33 Text String Processing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
3-33-1 Text String Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
3-33-2 MOV STRING: MOV$(664) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221
3-33-3 CONCATENATE STRING: +$(656) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
3-33-4 GET STRING LEFT: LEFT$(652) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
3-33-5 GET STRING RIGHT: RGHT$(653) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228
3-33-6 GET STRING MIDDLE: MID$(654) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
3-33-7 FIND IN STRING: FIND$(660) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
3-33-8 STRING LENGTH: LEN$(650) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
3-33-9 REPLACE IN STRING: RPLC$(661) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
3-33-10 DELETE STRING: DEL$(658) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
3-33-11 EXCHANGE STRING: XCHG$(665). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
3-33-12 CLEAR STRING: CLR$(666) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
3-33-13 INSERT INTO STRING: INS$(657) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246
3-33-14 String Comparison Instructions (670 to 675) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
3-34 Task Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
3-34-1 TASK ON: TKON(820) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
3-34-2 TASK OFF: TKOF(821). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
3-35 Model Conversion Instructions (Unit Ver. 3.0 or Later) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
3-35-1 BLOCK TRANSFER: XFERC(565) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
3-35-2 SINGLE WORD DISTRIBUTE: DISTC(566) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
3-35-3 DATA COLLECT: COLLC(567) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269

153
 3-35-4 MOVE BIT: MOVBC(568). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
3-35-5 BIT COUNTER: BCNTC(621) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
3-35-6 GET VARIABLE ID: GETID(286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277

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Notation and Layout of Instruction Descriptions Section 3-1

3-1 Notation and Layout of Instruction Descriptions

Instructions are described in groups by function. Refer to 2-3 Alphabetical List
of Instructions by Mnemonic for a list of instructions by mnemonic that lists the
page number in this section for each instruction.
The description of each instruction is organized as described in the following
table.
Item Contents
Name and Mnemonic The heading of each section consists of the name of the instruction followed by the
mnemonic with the function code in parentheses. Example: MOVE BIT: MOVB(082)
Purpose The basic purpose of the instruction is described after the section heading.
Ladder Symbol and Operand The ladder symbol used to represent the instruction on the CX-Programmer is
Names shown, as in the example for the MOVE BIT instruction given below. The name of
each operand is also provided with the ladder symbol.

MOVB(082)

S S: Source word or data

C C: Control word

D D: Destination word

Variations Variations The variations that can be used to control execution of the instruction under special
conditions are given using the mnemonic form. Any variation that is not supported by
an instruction is given as “Not supported.”
• Executed Each Cycle for ON Condition: The instruction is executed as long as
it receives an ON execution condition.
• Executed Once for Upward Differentiation: The instruction is executed during
the next cycle only after the execution condition changes from OFF to ON.
• Executed Once for Downward Differentiation: The instruction is executed dur-
ing the next cycle only after the execution condition changes from ON to OFF.
• Always Executed: The instruction does not require an execution condition and
is executed each cycle.
• Creates ON Condition....: The instruction is executed each cycle to create an
execution condition for the next instruction.

Variations Executed Each Cycle for ON Condition MOVB(082)

Variations Variations Executed Once for Upward Differentia- @MOVB(082)
tion
Executed Once for Downward Differenti- Not supported.
ation

Immediate Immediate refreshing can be specified for some instructions to refresh I/O when the
Refreshing instruction is executed. If immediate refreshing is supported, the specification is
Specification given using the mnemonic form. If immediate refreshing is not support by an instruc-
tion “Not supported” is given.

Immediate Refreshing Specification Not supported.

Applicable Program Areas The program areas in which the instruction can be used are specified. “OK” indicates
the areas in which the instruction can be used.

Block program Step program Subroutines Interrupt tasks

areas areas
OK OK OK OK

155
Notation and Layout of Instruction Descriptions Section 3-1

Item Contents
Operands Where necessary, the meaning of words and bits used in specific operands, such
as control words, is given.
15 8 7 0
C m n

Source bit: 00 to 0F
(0 to 15 decimal)
Destination bit: 00 to 0F
(0 to 15 decimal)

Operand Specifications The memory areas addresses that can be used each operand are listed in a table
like the following one. The letters used in the column headings on the left are the
same as those used in the ladder symbol. “---” is used to indicate when an area can-
not be specific for an operand.

Area S C D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without E00000 to E32767
bank

Description The function of the instruction and the operands used in the instruction are
described.
Flags The flags table indicates the status of the condition flags immediately after execution
of the instruction. Any flags that are not listed are not affected by the instruction.
“OFF” indicates that a flag is turned OFF immediately after execution of the instruc-
tion regardless of the results of executing the instruction.

Name Label Operation

Error Flag ER ON if control data is within ranges.
OFF in all other cases.
Equals Flag = OFF
Negative Flag N OFF

Precautions Special precautions required in using the instruction are provided. Be sure to read
and follow these precautions.
Example An example of using the instruction with specific operands is provided to further
explain the function of the instruction.

Constants Constants input for operands are given as listed below.

Operand Descriptions and Operand Specifications
• Operands Specifying Bit Strings (Normally Input as Hexadecimal):
Only the hexadecimal form is given for operands specifying bit strings,
e.g., only “#0000 to #FFFF” is specified as the S operand for the
MOV(021) instruction. On the CX-Programmer, however, bit strings can
be input in decimal form by using the & prefix.
• Operands Specifying Numeric Values (Normally Input as Decimal, Includ-
ing Jump Numbers):
Both the decimal and hexadecimal forms are given for operands specify-
ing numeric values, e.g., “#0000 to #FFFF” and “&0 to &65535” are given
for the N operand for the XFER(070) instruction.

156
Notation and Layout of Instruction Descriptions Section 3-1

• Operands Indicating Control Numbers (Except for Jump Numbers):

The decimal form is given for control numbers, e.g., “0 to 1023” is given
for the N operand for the SBS(091) instruction.
Examples
In the examples, constants are given using the CX-Programmer notation, e.g.,
operands specifying numeric values are given in decimal for with an & prefix,
as shown in the following example.

XFER
&10
D00100
D00200

The input methods for constants for the Programming Devices are given in the
following table.
Operand CX- Programming Console
Programmer
Operands specify- Input as deci- The Cont/# Key can be pressed to input hexa-
ing bit strings (nor- mal with an & decimal values by default with an # prefix. The
mally input as prefix or input CHG Key can then be pressed to rotate
hexadecimal) as hexadeci- between hexadecimal (with # prefix), signed
Operands specify- mal with an # decimal (with +/–), and unsigned decimal (with
ing numeric values prefix. (See & prefix).
(normally input as note.)
decimal)
Operands specify- Input as deci- Input directly in decimal form.
ing control numbers mal with an # If the & prefix is automatically added, the CHG
(except for jump prefix. (See Key can be pressed to rotate between
numbers) note.) unsigned decimal (with & prefix), hexadecimal
(with # prefix), and signed decimal (with +/–).
If no prefix is displayed, the value must be
entered in decimal form.

Note When operands are input on the CX-Programmer, the input ranges will be dis-
played along with the appropriate prefixes.

Condition Flags Programming Console labels are used for condition flags in this section. With
the CX-Programmer, the condition flags are registered in advance as global
symbols with “P_” in front of the symbol name.
Flag CX-Programmer label Programming Console label
Error Flag P_ER ER
Access Error P_AER AER
Flag
Carry Flag P_CY CY
Greater Than P_GT >
Flag
Equals Flag P_EQ =
Less Than Flag P_LT <
Negative Flag P_N N
Overflow Flag P_OF OF
Underflow Flag P_UF UF
Greater Than or P_GE >=
Equals Flag
Not Equal Flag P_NE <>

157
Instruction Upgrades and New Instructions Section 3-2

Flag CX-Programmer label Programming Console label

Less Than or P_LE <=
Equals Flag
Always ON Flag P_On ON
Always OFF P_Off OFF
Flag

Symbol Instructions Some of the C/CV-series PLC instructions have been changed to different
instructions with the same functionality for the CS/CJ-series PLCs.
Instruction group C/CV Series CS/CJ Series
Sequence Control JMP #0 / JME #0 JMP0 / JME0
Comparison EQU AND=
Data Movement MOVQ MOV
Increment/Decre- INC ++B
ment INCL ++BL
INCB ++
INBL ++L
DEC --B
DECL --BL
DECB --
DCBL --L
Symbol Math ADB +C
ADBL +CL
ADD +BC
ADDL +BCL
SBB -C
SBBL -CL
SUB -BC
SUBL -BCL
MBS *
MBSL *L
MLB *U
MUL *B
MULL *BL
DBS /
DBSL /L
DVB /U
DIV /B
DIVL /BL
Interrupt Control INT MSKS / MSKR / CLIDI / EI

3-2 Instruction Upgrades and New Instructions

This section lists the instruction upgrades for CS1 CPU Units with the -EV1
suffix and CS1-H/CJ1-H CPU Units.

3-2-1 Upgrades for CS1-H/CJ1-H CPU Units

New Instructions The following instructions have been added to the CS1-H and CJ1-H CPU
Units.

158
Instruction Upgrades and New Instructions Section 3-2

Sequence Output Instructions

SINGLE BIT SET, SETB(532)
SINGLE BIT RESET, RSTB(533)
SINGLE BIT OUTPUT, OUTB(534)
Data Comparison Instructions
AREA RANGE COMPARE, ZCP(088)
DOUBLE AREA RANGE COMPARE, ZCPL(116)
Floating Point Calculation and Conversion Instructions
Floating Point Data Comparison Instructions: =F, <>F, <F, <=F, >F, and >=F (329 to
334)
FLOATING POINT TO ASCII, FSTR(448)
ASCII TO FLOATING POINT, VAL(449)
Double-precision Floating Point Calculation and Conversion Instructions
Double-precision Comparison Instructions: =D, <>D, <D, <=D, >D, and >=D (335 to
340)
DOUBLE FLOATING TO 16-BIT BINARY, FIXD(841)
DOUBLE FLOATING TO 32-BIT BINARY, FIXLD(8420)
16-BIT BINARY TO DOUBLE FLOATING, DBL(843)
32-BIT BINARY TO DOUBLE FLOATING, DBLL(844)
DOUBLE FLOATING-POINT ADD, +D(845)
DOUBLE FLOATING-POINT SUBTRACT, −D(846)
DOUBLE FLOATING-POINT MULTIPLY, *D(847)
DOUBLE FLOATING-POINT DIVIDE, /D(848)
DOUBLE DEGREES TO RADIANS, RADD(849)
DOUBLE RADIANS TO DEGREES, DEGD(850)
DOUBLE SINE, SIND(851)
DOUBLE COSINE, COSD(852)
DOUBLE TANGENT, TAND(853)
DOUBLE ARC SINE, ASIND(854)
DOUBLE ARC COSINE, ACOSD(855)
DOUBLE ARC TANGENT, ATAND(856)
DOUBLE SQUARE ROOT, SQRTD(857)
DOUBLE EXPONENT, EXPD(858)
DOUBLE LOGARITHM, LOGD(859)
DOUBLE EXPONENTIAL POWER, PWRD(860)
Table Data Processing Instructions
STACK SIZE READ, SNUM(638)
STACK DATA READ, SREAD(639)
STACK DATA WRITE, SWRIT(640)
STACK DATA INSERT, SINS(641)
STACK DATA DELETE, SDEL(642)
Data Control Instructions
PID CONTROL WITH AUTOTUNING, PIDAT(191)
Subroutine Instructions
GLOBAL SUBROUTINE CALL, GSBS(750)
GLOBAL SUBROUTINE ENTRY, GSBN(751)
GLOBAL SUBROUTINE RETURN, GRET(752)
I/O Unit Instructions
CPU BUS UNIT I/O REFRESH, DLNK(226)
Other Instructions
SAVE CONDITION FLAGS, CCS(282)
LOAD CONDITION FLAGS, CCL(283)
CONVERT ADDRESS FROM CV, FRMCV(284)
CONVERT ADDRESS TO CV, TOCV(285)
DISABLE PERIPHERAL SERVICING, IOSP(287)
ENABLE PERIPHERAL SERVICING, IORS(288)

159
Instruction Upgrades and New Instructions Section 3-2

New Instructions The following instructions have been upgraded for the CS1-H and CJ1-H CPU
Units.
Special Math Instructions
ARITHMETIC PROCESS, APR(069)
Failure Diagnosis Instructions
FAILURE ALARM, FAL(006)
SEVERE FAILURE ALARM, FALS(007)

160
Sequence Input Instructions Section 3-3

3-3 Sequence Input Instructions

3-3-1 LOAD: LD
Purpose Indicates a logical start and creates an ON/OFF execution condition based on
the ON/OFF status of the specified operand bit.

Ladder Symbol Bus bar Starting point of block

Variations
Variations Restarts Logic and Creates ON Each Cycle LD
Operand Bit is ON
Restarts Logic and Creates ON Once for @LD
Upward Differentiation
Restarts Logic and Creates ON Once for %LD
Downward Differentiation
Immediate Refreshing Specification (See note.) !LD
Combined Refreshes Input Bit, Restarts Logic, and !@LD
Variations Creates ON Once for Upward Differentiation
(See note.)
Refreshes Input Bit, Restarts Logic, and !%LD
Creates ON Once for Downward Differentiation
(See note.)

Note Immediate refreshing is not supported by CS1D CPU Units for Duplex-CPU
Systems.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area LD operand bit
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A00000 to A95915
Timer Area T0000 to T4095
Counter Area C0000 to C4095
Task Flag Area TK0000 to TK0031
Condition Flags ER, CY, N, OF, UF, >, =, <, >=, <>, <=, A1, A0
Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area TR0 to TR15
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---

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Sequence Input Instructions Section 3-3

Area LD operand bit

Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
, –(– –)IR0 to, –(– –)IR15

Description LD is used for the first normally open bit from the bus bar or for the first nor-
mally open bit of a logic block. If there is no immediate refreshing specifica-
tion, the specified bit in I/O memory is read. If there is an immediate
refreshing specification, the status of the Basic Input Unit’s input terminal is
read and used.
LD is used in the following circumstances as an instruction for indicating a log-
ical start.
• When directly connecting to the bus bar.
• When logic blocks are connected by AND LD or OR LD, i.e., at the begin-
ning of a logic block.
The AND LOAD and OR LOAD instructions are used to connect in series or in
parallel logic blocks beginning with LD or LD NOT.
At least one LOAD or LOAD NOT instruction is required for the execution con-
dition when output-related instructions cannot be connected directly to the
bus bar. If there is no LOAD or LOAD NOT instruction, a programming error
will occur with the program check by the Peripheral Device.
When logic blocks are connected by AND LOAD or OR LOAD instructions, the
total number of AND LOAD/OR LOAD instructions must match the total num-
ber of LOAD/LOAD NOT instructions minus1. If they do not match, a program-
ming error will occur. For details, refer to 3-3-7 AND LOAD: AND LD and 3-3-
8 OR LOAD: OR LD.
Flags There are no flags affected by this instruction.

Precautions Differentiate up (@) or differentiate down (%) can be specified for LD. If differ-
entiate up (@) is specified, the execution condition is turned ON for one cycle
only after the status of the operand bit goes from OFF to ON. If differentiate
down (%) is specified, the execution condition is turned ON for one cycle only
after the status of the operand bit goes from ON to OFF.
Immediate refreshing (!) can be specified for LD. An immediate refresh
instruction updates the status of the input bit just before the instruction is exe-
cuted for Basic Input Units (but not Basic Input Units on Slave Racks or for
C200H Group 2 Multi-point Input Units).
For LD, it is possible to combine immediate refreshing and up or down differ-
entiation (!@ or !%). If either of these is specified, the input is refreshed from
the Basic Input Unit just before the instruction is executed and the execution
condition is turned ON for one cycle only after the status goes from OFF to
ON, or from ON to OFF.

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Sequence Input Instructions Section 3-3

Example

Instruction Operand
AND LD
LD 000000 OR LD
LD 000001
LD 000002 OR LD
AND 000003
OR LD ---
AND LD ---
LD NOT 000004
AND 000005
OR LD ---
OUT 000100

3-3-2 LOAD NOT: LD NOT

Purpose Indicates a logical start and creates an ON/OFF execution condition based on
the reverse of the ON/OFF status of the specified operand bit.

Ladder Symbol Bus bar Starting point of block

Variations
Variations Restarts Logic and Creates ON Each Cycle Operand LD NOT
Bit is OFF
Restarts Logic and Creates ON Once for Upward @LD NOT
Differentiation (See note 1.)
Restarts Logic and Creates ON Once for Downward %LD NOT
Differentiation (See note 1.)
Immediate Refreshing Specification (See note 2.) !LD NOT
Combined Refreshes Input Bit, Restarts Logic, and Creates ON !@LD NOT
Variations Once for Upward Differentiation (See note 3.)
Refreshes Input Bit, Restarts Logic, and Creates ON !%LD NOT
Once for Downward Differentiation (See note 3.)

Note 1. The following variations are supported by only the CS1-H, CJ1-H, CJ1M,
or CS1D CPU Units: @LD NOT, %LD NOT, !@LD NOT, and !%LD NOT.
2. Immediate refreshing is not supported by CS1D CPU Units for Duplex-
CPU Systems.
3. Combined variations are supported by CS1D CPU Units for Single-CPU
Systems and CS1-H, CJ1-H, and CJ1M CPU Units only.

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Sequence Input Instructions Section 3-3

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area LD NOT bit operand
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A00000 to A95915
Timer Area T0000 to T4095
Counter Area C0000 to C4095
Task Flag Area TK0000 to TK0031
Condition Flags ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER
Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area ---
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description LD NOT is used for the first normally closed bit from the bus bar, or for the first
normally closed bit of a logic block. If there is no immediate refreshing specifi-
cation, the specified bit in I/O memory is read and reversed. If there is an
immediate refreshing specification, the status of the Basic Input Unit’s input
terminal is read, reversed, and used.
LD NOT is used in the following circumstances as an instruction for indicating
a logical start.
• When directly connecting to the bus bar.
• When logic blocks are connected by AND LD or OR LD. (Used at the
beginning of a logic block.)
The AND LOAD and OR LOAD instructions are used to connect in series or in
parallel logic blocks beginning with LD or LD NOT.
At least one LOAD or LOAD NOT instruction is required for the execution con-
dition when output-related instructions cannot be connected directly to the
bus bar. If there is no LOAD or LOAD NOT instruction, a program error will
occur with the program check by the Peripheral Device.
When logic blocks are connected by AND LOAD or OR LOAD instructions, the
total number of AND LOAD/OR LOAD instructions must match the total num-
ber of LOAD/LOAD NOT instructions minus1. If they do not match, a program-
ming error will occur.

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Sequence Input Instructions Section 3-3

Flags There are no flags affected by this instruction.

Precautions Immediate refreshing (!) can be specified for LD NOT. An immediate refresh
instruction updates the status of the input bit just before the instruction is exe-
cuted for Basic Input Units (but not Basic Input Units on Slave Racks or for
C200H Group 2 Multi-point Input Units).
Example

Instruction Operand
LD 000000 AND LD
OR LD
LD 000001
LD 000002 OR LD
AND 000003
OR LD ---
AND LD ---
LD NOT 000004
AND 000005
OR LD ---
OUT 000100

3-3-3 AND: AND

Purpose Takes a logical AND of the status of the specified operand bit and the current
execution condition.

Ladder Symbol

Variations
Variations Creates ON Each Cycle AND Result is ON AND
Creates ON Once for Upward Differentiation @AND
Creates ON Once for Downward Differentiation %AND
Immediate Refreshing Specification (See note.) !AND
Combined Refreshes Input Bit and Creates ON Once for !@AND
Variations Upward Differentiation (See note.)
Refreshes Input Bit and Creates ON Once for !%AND
Downward Differentiation (See note.)

Note Immediate refreshing is not supported by CS1D CPU Units for Duplex-CPU
Systems.
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

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Sequence Input Instructions Section 3-3

Operand Specifications
Area AND bit operand
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A00000 to A95915
Timer Area T0000 to T4095
Counter Area C0000 to C4095
Task Flag Area TK0000 to TK0031
Condition Flags ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER
Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area ---
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description AND is used for a normally open bit connected in series. AND cannot be
directly connected to the bus bar, and cannot be used at the beginning of a
logic block. If there is no immediate refreshing specification, the specified bit
in I/O memory is read. If there is an immediate refreshing specification, the
status of the Basic Input Unit’s input terminal is read.

Flags There are no flags affected by this instruction.

Precautions Differentiate up (@) or differentiate down (%) can be specified for AND. If dif-
ferentiate up (@) is specified, the execution condition is turned ON for one
cycle only after the status of the operand bit goes from OFF to ON. If differen-
tiate down (%) is specified, the execution condition is turned ON for one cycle
only after the status of the operand bit goes from ON to OFF.
Immediate refreshing (!) can be specified for AND. An immediate refresh
instruction updates the status of the input bit just before the instruction is exe-
cuted from the Basic Input Unit (but not Basic Input Units on Slave Racks or
for C200H Group 2 Multi-point Input Units).
For AND, it is possible to combine immediate refreshing and up or down differ-
entiation (!@ or !%). If either of these is specified, the input is refreshed from
the Basic Input Unit just before the instruction is executed and the execution
condition is turned ON for one cycle only after the status goes from OFF to
ON, or from ON to OFF.
AND cannot be used for addresses in the DM and EM Areas. Use AND
TST(350) instead.

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Sequence Input Instructions Section 3-3

Example

Instruction Operand
LD 000000
AND 000001
LD 000002
AND 000003
LD 000004
AND NOT 000005
OR LD ---
AND LD ---
OUT 000006

3-3-4 AND NOT: AND NOT

Purpose Reverses the status of the specified operand bit and takes a logical AND with
the current execution condition.
Ladder Symbol

Variations
Variations Creates ON Each Cycle AND NOT Result is ON AND NOT
Creates ON Once for Upward Differentiation (See @AND NOT
note 1.)
Creates ON Once for Downward Differentiation (See %AND NOT
note 1.)
Immediate Refreshing Specification (See note 2.) !AND NOT
Combined Refreshes Input Bit and Creates ON Once for !@AND NOT
Variations Upward Differentiation (See note 3.)
Refreshes Input Bit and Creates ON Once for !%AND NOT
Downward Differentiation (See note 3.)

Note 1. The following variations are supported by only the CS1-H, CJ1-H, CJ1M,
or CS1D CPU Units: @AND NOT, %AND NOT, !@AND NOT, and !%AND
NOT.
2. Immediate refreshing is not supported by CS1D CPU Units for Duplex-
CPU Systems.
3. Combined variations are supported by CS1D CPU Units for Single-CPU
Systems and CS1-H, CJ1-H, and CJ1M CPU Units only.
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area AND NOT bit operand
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115

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Sequence Input Instructions Section 3-3

Area AND NOT bit operand

Holding Bit Area H00000 to H51115
Auxiliary Bit Area A00000 to A95915
Timer Area T0000 to T4095
Counter Area C0000 to C4095
Task Flag Area TK0000 to TK0031
Condition Flags ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER
Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area ---
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description AND NOT is used for a normally closed bit connected in series. AND NOT
cannot be directly connected to the bus bar, and cannot be used at the begin-
ning of a logic block. If there is no immediate refreshing specification, the
specified bit in I/O memory is read. If there is an immediate refreshing specifi-
cation, the status the Basic Input Unit’s input terminals is read.

Flags There are no flags affected by this instruction.

Precautions Immediate refreshing (!) can be specified for AND NOT. An immediate refresh
instruction updates the status of input bit just before the instruction is exe-
cuted from Basic Input Units (but not for Basic Input Units on Slave Racks or
for C200H Group 2 Multi-point Input Units).

Example

Instruction Operand
LD 000000
AND 000001
LD 000002
AND 000003
LD 000004
AND NOT 000005

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Sequence Input Instructions Section 3-3

Instruction Operand
OR LD ---
AND LD ---
OUT 000006

3-3-5 OR: OR
Purpose Takes a logical OR of the ON/OFF status of the specified operand bit and the
current execution condition.

Ladder Symbol Bus bar

Variations
Variations Creates ON Each Cycle OR Result is ON OR
Creates ON Once for Upward Differentiation @OR
Creates ON Once for Downward Differentiation %OR
Immediate Refreshing Specification (See note.) !OR
Combined Refreshes Input Bit and Creates ON Once for !@OR
Variations Upward Differentiation (See note.)
Refreshes Input Bit and Creates ON Once for !%OR
Downward Differentiation (See note.)

Note Immediate refreshing is not supported by CS1D CPU Units for Duplex-CPU
Systems.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area OR bit operand
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A00000 to A95915
Timer Area T0000 to T4095
Counter Area C0000 to C4095
Task Flag Area TK0000 to TK0031
Condition Flags ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER
Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---

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Sequence Input Instructions Section 3-3

Area OR bit operand

Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description OR is used for a normally open bit connected in parallel. A normally open bit
is configured to form a logical OR with a logic block beginning with a LOAD or
LOAD NOT instruction (connected to the bus bar or at the beginning of the
logic block). If there is no immediate refreshing specification, the specified bit
in I/O memory is read. If there is an immediate refreshing specification, the
status of the Basic Input Unit’s input terminal is read.

Flags There are no flags affected by this instruction.

Precautions Differentiate up (@) or differentiate down (%) can be specified for OR. If differ-
entiate up (@) is specified, the execution condition is turned ON for one cycle
only after the status of the operand bit goes from OFF to ON. If differentiate
down (%) is specified, the execution condition is turned ON for one cycle only
after the status of the operand bit goes from ON to OFF.
Immediate refreshing (!) can be specified for OR. An immediate refresh
instruction updates the status of the input bit just before the instruction is exe-
cuted from the Basic Input Unit (but not for Basic Input Units on Slave Racks
or for C200H Group 2 Multi-point Input Units).
For OR, it is possible to combine immediate refreshing and up or down differ-
entiation (!@ or !%). If either of these is specified, the input is refreshed from
the Basic Input Unit just before the instruction is executed and the execution
condition is turned ON for one cycle only after the status of the operand bit
goes from OFF to ON, or from ON to OFF.

Example

Instruction Operand
LD 000000
AND 000001
AND 000002
OR 000003
AND 000004
LD 000005
AND 000006
OR NOT 000007
AND LD ---
OUT 000008

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Sequence Input Instructions Section 3-3

3-3-6 OR NOT: OR NOT

Purpose Reverses the status of the specified bit and takes a logical OR with the current
execution condition.
Ladder Symbol Bus bar

Variations
Variations Creates ON Each Cycle OR NOT Result is ON OR NOT
Creates ON Once for Upward Differentiation (See @OR NOT
note 1.)
Creates ON Once for Downward Differentiation (See %OR NOT
note 1.)
Immediate Refreshing Specification (See note 2.) !OR NOT
Combined Refreshes Input Bit and Creates ON Once for !@OR NOT
Variations Upward Differentiation (See note 3.)
Refreshes Input Bit and Creates ON Once for !%OR NOT
Downward Differentiation (See note 3.)

Note 1. The following variations are supported by only the CS1-H, CJ1-H, CJ1M,
or CS1D CPU Units: @OR NOT, %OR NOT, !@OR NOT, and !%OR NOT.
2. Immediate refreshing is not supported by CS1D CPU Units for Duplex-
CPU Systems.
3. Combined variations are supported by CS1D CPU Units for Single-CPU
Systems and CS1-H, CJ1-H, and CJ1M CPU Units only.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area OR NOT bit operand
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A00000 to A95915
Timer Area T0000 to T4095
Counter Area C0000 to C4095
Task Flag Area TK0000 to TK0031
Condition Flags ER, CY, N, OF, UF, >, =, <, >=, <>, <=, A1, A0
Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area ---
DM Area ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---

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Sequence Input Instructions Section 3-3

Area OR NOT bit operand

Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description OR NOT is used for a normally closed bit connected in parallel. A normally
closed bit is configured to form a logical OR with a logic block beginning with a
LOAD or LOAD NOT instruction (connected to the bus bar or at the beginning
of the logic block). If there is no immediate refreshing specification, the speci-
fied bit in I/O memory is read. If there is an immediate refreshing specification,
the status of the Basic Input Unit’s input terminal is read.

Flags There are no flags affected by this instruction.

Precautions Immediate refresh (!) can be specified for OR NOT. An immediate refresh
instruction updates the status of the input bit just before the instruction is exe-
cuted from a Basic Input Unit (but not Basic Input Units on Slave Racks or for
C200H Group 2 Multi-point Input Units).

Example

Instruction Operand
LD 000000
AND 000001
AND 000002
OR 000003
AND 000004
LD 000005
AND 000006
OR NOT 000007
AND LD ---
OUT 000008

3-3-7 AND LOAD: AND LD

Purpose Takes a logical AND between logic blocks.

Ladder Symbol
Logic block Logic block

Variations
Variations Creates ON Each Cycle AND Result is ON AND LD
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

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Sequence Input Instructions Section 3-3

Description AND LD connects in series the logic block just before this instruction with
another logic block.

LD
to Logic block A

LD

to Logic block B

AND LD Serial connection between logic block A and logic block B.

The logic block consists of all the instructions from a LOAD or LOAD NOT
instruction until just before the next LOAD or LOAD NOT instruction on the
same rungs.
In the following diagram, the two logic blocks are indicated by dotted lines.
Studying this example shows that an ON execution condition will be produced
when either of the execution conditions in the left logic block is ON (i.e., when
either CIO 000000 or CIO 000001 is ON) and either of the execution condi-
tions in the right logic block is ON (i.e., when either CIO 000002 is ON or
CIO 000003 is OFF).

Flags There are no flags affected by this instruction.

Precautions Three or more logic blocks can be connected in series using this instruction to
first connect two of the logic blocks and then to connect the next and subse-
quent ones in order. It is also possible to continue placing this instruction after
three or more logic blocks and connect them together in series.
When a logic block is connected by AND LOAD or OR LOAD instructions, the
total number of AND LOAD/OR LOAD instructions must match the total num-
ber of LOAD/LOAD NOT instructions minus 1. If they do not match, a program
error will occur.

Example

Coding Example (1)

Instruction Operand
LD 000000
OR NOT 000001
LD NOT 000002
OR 000003
AND LD ---
LD 000004
OR 000005

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Sequence Input Instructions Section 3-3

Instruction Operand
AND LD ---
. .
. .
OUT 000500
Coding Example (2)
Instruction Operand
LD 000000
OR NOT 000001
LD NOT 000002
OR 000003
LD 000004
OR 000005
. .
. .
AND LD ---
AND LD ---
. .
. .
OUT 000500

The AND LOAD instruction can be used repeatedly. In programming method

(2) above, however, the number of AND LOAD instructions becomes one less
than the number of LOAD and LOAD NOT instructions before that.
In method (2), make sure that the total number of LOAD and LOAD NOT
instructions before AND LOAD is not more than eight. To use nine or more,
program using method (1). If there are nine or more with method (2), then a
program error will occur during the program check by the Peripheral Device.
Coding
Address Instruction Operand
000000 LD 000000
000001 OR 000001
000002 LD 000002
000003 OR NOT 000003
000004 AND LD ---
000005 OUT 000500
Second LD: Used for first bit of next block connected in series to previous block.

3-3-8 OR LOAD: OR LD
Purpose Takes a logical OR between logic blocks.

Ladder Symbol
Logic block

Logic block

Variations
Variations Creates ON Each Cycle AND Result is ON OR LD
Immediate Refreshing Specification Not supported.

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Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK
Description AND LD connects in parallel the logic block just before this instruction with
another logic block.

LD
to Logic block A

LD
to Logic block B

OR LD Parallel connection between logic block A and logic block B.

The logic block consists of all the instructions from a LOAD or LOAD NOT
instruction until just before the next LOAD or LOAD NOT instruction on the
same rungs.
The following diagram requires an OR LOAD instruction between the top logic
block and the bottom logic block. An ON execution condition would be pro-
duced either when CIO 000000 is ON and CIO 000001 is OFF or when
CIO 000002 and CIO 000003 are both ON. The operation of and mnemonic
code for the OR LOAD instruction is exactly the same as those for a AND
LOAD instruction except that the current execution condition is ORed with the
last unused execution condition.

Flags There are no flags affected by this instruction.

Precautions Three or more logic blocks can be connected in parallel using this instruction
to first connect two of the logic blocks and then to connect the next and subse-
quent ones in order. It is also possible to continue placing this instruction after
three or more logic blocks and connect them together in parallel.
When a logic block is connected by AND LOAD or OR LOAD instructions, the
total number of AND LOAD/OR LOAD instructions must match the total num-
ber of LOAD/LOAD NOT instructions minus 1. If they do not match, a pro-
gramming error will occur.

Example

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Coding Example (1)

Instruction Operand
LD 000000
AND NOT 000001
LD NOT 000002
AND NOT 000003
OR LD ---
LD 000004
AND 000005
OR LD ---
. .
. .
OUT 000501

Coding Example (2)

Instruction Operand
LD 000000
AND NOT 000001
LD NOT 000002
AND NOT 000003
LD 000004
AND 000005
. .
. .
OR LD ---
OR LD ---
. .
. .
OUT 000501

The OR LOAD instruction can be used repeatedly. In programming method

(2) above, however, the number of OR LOAD instructions becomes one less
than the number of LOAD and LOAD NOT instructions before that.
In method (2), make sure that the total number of LOAD and LOAD NOT
instructions before OR LOAD is not more than eight. To use nine or more, pro-
gram using method (1). If there are nine or more with method (2), then a pro-
gram error will occur during the program check by the Peripheral Device.
Coding
Address Instruction Operand
000100 LD 000000
000101 AND NOT 000001
000102 LD 000002
000103 AND 000003
000104 OR LD ---
000105 OUT 000501

Second LD: Used for first bit of next block connected in series to previous block.

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3-3-9 Differentiated and Immediate Refreshing Instructions

The LOAD, AND, and OR instructions have differentiated and immediate
refreshing variations in addition to their ordinary forms, and there are also two
combinations available.
The LOAD NOT, AND NOT, OR NOT, OUT, and OUT NOT instructions have
immediate refreshing variations in addition to their ordinary forms.
The I/O timing for data handled by instructions differs for ordinary and differ-
entiated instructions, immediate refreshing instructions, and immediate
refreshing differentiated instructions.
Ordinary and differentiated instructions are executed using data input by pre-
vious I/O refresh processing, and the results are output with the next I/O pro-
cessing. Here “I/O refreshing” means the data exchanged between the CPU’s
internal memory and the I/O Unit.
In addition to the above I/O refreshing, an immediate refresh instruction
exchanges data with the I/O Unit for those words that are accessed by the
instruction. An immediate refresh instruction refreshes eight bits simulta-
neously (leftmost or rightmost eight bits) in addition to the specified bit.
Immediate refresh instructions cannot be used for Units on Slave Racks.
Instruction variation Mnemonic Function I/O refresh
Ordinary LD, AND, OR, LD NOT, The ON/OFF status of the specified bit Cyclic refreshing
AND NOT, OR NOT is taken by the CPU with cyclic refresh-
ing, and it is reflected in the next instruc-
tion execution.
OUT, OUT NOT After the instruction is executed, the ON/
OFF status of the specified bit is output
with the next cyclic refreshing.
Differentiated up @LD, @AND, @OR The instruction is executed once when
the specified bit turns from OFF to ON
and the ON state is held for one cycle.
Differentiated down %LD, %AND, %OR The instruction is executed once when
the specified bit turns from ON to OFF
and the ON state is held for one cycle.
Immediate refresh !LD, !AND, !OR, !LD NOT, The input data for the specified bit is Before instruction execu-
!AND NOT, !OR NOT taken by the CPU and the instruction is tion
executed.
!OUT, !OUT NOT After the instruction is executed, the After instruction execution
data for the specified bit is output.
Differentiated up / !@LD, !@AND, !@OR The input data for the specified bit is Before instruction execu-
immediate refresh refreshed by the CPU, and the instruc- tion
tion is executed once when the bit turns
from OFF to ON and the ON state is
held for one cycle.
Differentiated down / !%LD, !%AND, !%OR The input data for the specified bit is
immediate refresh refreshed by the CPU, and the instruc-
tion is executed once when the bit turns
from ON to OFF and the ON state is
held for one cycle.

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3-3-10 Operation Timing for I/O Instructions

The following chart shows the differences in the timing of instruction opera-
tions for a program configured from LD and OUT.

Input
received
Input
received

Input
↑ received

Input
↓ received
Input
Input received
! received

Input
!↑ received

Input
!↓ received
Input received
Input
! ! received

Input
↑ ! received

Input
↓ ! received

! !

!↑ !

!↓ !

CPU
processing

Instruction execution I/O refreshing

3-3-11 TR Bits
TR bits are used to temporarily retain the ON/OFF status of execution condi-
tions in a program when programming in mnemonic code. They are not used
when programming directly in ladder program form because the processing is
automatically executed by the Peripheral Device. The following diagram
shows a simple application using two TR bits.

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Sequence Input Instructions Section 3-3

Address Instruction Operands

000000 LD 000000
000001 OUT TR0
000002 AND 000001
000003 OUT TR1
000004 AND 000002
000005 OUT 000500
000006 LD TR1
000007 AND 000003
000008 OUT 000501
000009 LD TR0
000010 AND 000004
000011 OUT 000502
000012 LD TR0
000013 AND NOT 000005
000014 OUT 000503

Using TR0 to TR15 TR0 to TR15 are used only with LOAD and OUTPUT instructions. There are
no restrictions on the order in which the bit addresses are used.
Sometimes it is possible to simplify a program by rewriting it so that TR bits
are not required. The following diagram shows one case in which a TR bit is
unnecessary and one in which a TR bit is required.

(1)

(2)

In instruction block (1), the ON/OFF status at point A is the same as for output
CIO 00200, so AND 000001 and OUT 000201 can be coded without requiring
a TR bit. In instruction block (2), the status of the branching point and that of
output CIO 000202 are not necessarily the same, so a TR bit must be used. In
this case, the number of steps in the program could be reduced by using
instruction block (1) in place of instruction block (2).

TR0 to TR15 TR bits are used only for retaining (OUT TR0 to TR15) and restoring (LD TR0
Considerations to TR15) the ON/OFF status of branching points in programs with many out-
put branches. They are thus different from general bits, and cannot be used
with AND or OR instructions, or with instructions that include NOT.

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Sequence Input Instructions Section 3-3

TR0 to TR15 output A TR bit address cannot be repeated within the same block in a program with
Duplication many output branches, as shown in the following diagram. It can, however, be
used again in a different block.

to

3-3-12 NOT: NOT(520)

Purpose Reverses the execution condition.

Ladder Symbol
NOT(520)
Variations
Variations Reverses the Execution Condition Each Cycle NOT(520)
Immediate Refreshing Specification Not supported
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK
Description NOT(520) is placed between an execution condition and another instruction to
invert the execution condition.

Flags There are no flags affected by NOT(520).

Precautions NOT(520) is an intermediate instruction, i.e., it cannot be used as a right-hand

instruction. Be sure to program a right-hand instruction after NOT(520).

Example NOT(520) reverses the execution condition in the following example.

The following table shows the operation of this program section.

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Sequence Input Instructions Section 3-3

Input bit status Output bit status

CIO 000000 CIO 000001 CIO 000002 CIO 000003
1 1 1 0
1 1 0 0
1 0 1 1
0 1 1 0
1 0 0 1
0 1 0 1
0 0 1 1
0 0 0 1

3-3-13 CONDITION ON/OFF: UP(521) and DOWN(522)

Purpose UP(521) turns ON the execution condition for the next instruction for one cycle
when the execution condition it receives goes from OFF to ON. DOWN(522)
turns ON the execution condition for the next instruction for one cycle when
the execution condition it receives goes from ON to OFF.

Ladder Symbols
UP(521)

DOWN(522)

Variations
Variations Creates ON Once for Upward Differentiation UP(521)
Immediate Refreshing Specification Not supported

Variations Creates ON Once for Downward Differentiation UP(522)

Immediate Refreshing Specification Not supported
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Description UP(521) is placed between an execution condition and another instruction to

turn the execution condition into an up-differentiated condition. UP(521)
causes the connecting instruction to be executed just once when the execu-
tion condition goes from OFF to ON.
DOWN(522) is placed between an execution condition and another instruction
to turn the execution condition into a down-differentiated condition.
DOWN(522) causes the connecting instruction to be executed just once when
the execution condition goes from ON to OFF.
The DIFU(013) and DIFD(014) instructions can also be used for the same
purpose, but they require work bits. UP(521) and DOWN(522) simplify pro-
gramming by reducing the number of work bits and program addresses
needed.

Flags There are no flags affected by UP(521) and DOWN(522).

Precautions UP(521) and DOWN(522) are intermediate instructions, i.e., they cannot be
used as right-hand instructions. Be sure to program a right-hand instruction
after UP(521) or DOWN(522).
The operation of UP(521) and DOWN(522) depends on the execution condi-
tion for the instruction as well as the execution condition for the program sec-
tion when it is programmed in an interlocked program section, a jumped

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program section, or a subroutine. Refer to 3-5-4 INTERLOCK and INTER-

LOCK CLEAR: IL(002) and ILC(003), 3-5-6 JUMP and JUMP END: JMP(004)
and JME(005), and 3-20 Interrupt Control Instructions for details.
Note Observe the following precaution when using UP(521) in a function
block definition.
The operation of UP(521) will not be consistent if the same function block
instance is executed more than once in the same cycle.
An instance will not be executed while EN is OFF. Caution is thus required
when using UP(521) in a function block definition. For details, refer to informa-
tion on restrictions on using ladder programming instructions in the CX-Pro-
grammer Operation Manual: Function Blocks.
Observe the following precaution when using UP(521) in a subroutine.
The operation of UP(521) will not be consistent if the same subroutine is exe-
cuted more than once in the same cycle.
An subroutine will not be executed while the input condition for the subroutine
is OFF. Caution is thus required when using UP(521) in a function block defini-
tion. For details, refer to information on SBS(091).

Examples When CIO 000000 goes from OFF to ON in the following example,
CIO 000001 is turned ON for just one cycle.

Cycle
time

Cycle
time

3-3-14 BIT TEST: TST(350) and TSTN(351)

Purpose LD TST(350), AND TST(350), and OR TST(350) are used in the program like
LD, AND, and OR; the execution condition is ON when the specified bit in the
specified word is ON, and OFF when the bit is OFF.
LD TSTN(351), AND TSTN(351), and OR TSTN(351) are used in the program
like LD NOT, AND NOT, and OR NOT; the execution condition is OFF when
the specified bit in the specified word is ON, and ON when the bit is OFF.

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Ladder Symbols
TST(350)

S S: Source word

N N: Bit number

TSTN(351)

S S: Source word

N N: Bit number

Variations
Variations Executed Each Cycle TST(350)
Immediate Refreshing Specification Not supported

Variations Executed Each Cycle TSTN(351)

Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands N: Bit number

The bit number must be between 0000 and 000F hexadecimal or between
&0000 and &0015 decimal. Only the rightmost bit (0 to F hexadecimal) of the
contents of the word is valid when a word address is specified.
Operand Specifications
Area S N
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM addresses @ D00000 to @ D32767
in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM addresses *D00000 to *D32767
in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- #0000 to #000F (binary) or
&0 to &15
Data Registers DR0 to DR15

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Area S N
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 , IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description LD TST(350), AND TST(350), and OR TST(350) can be used in the program
like LD, AND, and OR; the execution condition is ON when the specified bit in
the specified word is ON and OFF when the bit is OFF. Unlike LD, AND, and
OR, bits in the DM and EM areas can be used as operands in TST(350).
LD TSTN(351), AND TSTN(351), and OR TSTN(351) can be used in the pro-
gram like LD NOT, AND NOT, and OR NOT; the execution condition is OFF
when the specified bit in the specified word is ON and ON when the bit is OFF.
Unlike LD NOT, AND NOT, and OR NOT, bits in the DM and EM areas can be
used as operands in TSTN(351).
Flags
Name Label Operation
Error Flag ER OFF or unchanged (See note.)
Equals Flag = OFF or unchanged (See note.)
Negative Flag N OFF or unchanged (See note.)

Note In CS1 and CJ1 CPU Units, these are turned OFF.
In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, these Flags are left
unchanged.

Precautions TST(350) and TSTN(351) are intermediate instructions, i.e., they cannot be
used as right-hand instructions. Be sure to program a right-hand instruction
after TST(350) or TSTN(351).

Examples LD TST(350) and LD TSTN(351)

In the following example, CIO 000001 is turned ON when bit 3 of D00010 is
ON.

&3

In the following example, CIO 000001 is turned ON when bit 3 of D00010 is

OFF.

&3

AND TST(350) and AND TSTN(351)

In the following example, CIO 000001 is turned ON when CIO 000000 and bit
3 of D00010 are both ON.

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Sequence Output Instructions Section 3-4

&3

In the following example, CIO 000001 is turned ON when CIO 000000 is ON

and bit 5 of D00010 is OFF.

&5

OR TST(350) and OR TSTN(351)

In the following example, CIO 000001 is turned ON when CIO 000000 or bit 3
of D00010 is ON.

&3

In the following example, CIO 000001 is turned ON when CIO 000000 is ON

or bit 3 of D00010 is OFF.

&3

3-4 Sequence Output Instructions

3-4-1 OUTPUT: OUT
Purpose Outputs the result (execution condition) of the logical processing to the speci-
fied bit.
Ladder Symbol

Variations
Variations Executed Each Cycle for ON Condition OUT
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification (See note.) !OUT

Note Immediate refreshing is not supported by CS1D CPU Units.

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Sequence Output Instructions Section 3-4

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Operand Specifications
Area OUT bit operand
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A44800 to A95915
Timer Area ---
Counter Area ---
TR Area TR0 to TR15
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to ,IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description If there is no immediate refreshing specification, the status of the execution

condition (power flow) is written to the specified bit in I/O memory. If there is
an immediate refreshing specification, the status of the execution condition
(power flow) is also written to the Basic Output Unit’s output terminal in addi-
tion to the output bit in I/O memory.

Flags There are no flags affected by this instruction.

Precautions Immediate refreshing (!) can be specified for OUT and OUT NOT. An immedi-
ate refresh instruction updates the status of the output terminal just after the
instruction is executed for the Basic Output Unit (but not for Basic Output
Units on Slave Racks or for C200H Group 2 Multi-point Input Units), at the
same time as it writes the status of the execution condition (power flow) to the
specified output bit in I/O memory.
OUT cannot be used for addresses in the DM and EM Areas. Use OUTB(534)
instead.

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Example

Instruction Operand
LD 000000
OUT 000001
OUT NOT 000002

Note Difference between SET/RSET and OUT

For OUT, the operand bit is turned ON when the input condition turns ON and
is turned OFF when the input condition turns OFF. For SET and RSET, the
operand bit turns ON or OFF, respectively, when the input condition turns ON
and the operand bit does not change when the input condition turns OFF.
Note Precaution for Index Registers
OUT is executed even when the input condition turns OFF. Be particularly
careful when programming OUT using an indirect index register address.

Input condition

MOVR
W0.0
IR0

,IR0
When the input condition is OFF,
MOVR(560) is not executed, but OUT
is executed for the address stored in
the index register.

3-4-2 OUTPUT NOT: OUT NOT

Purpose Reverses the result (execution condition) of the logical processing, and out-
puts it to the specified bit.
Ladder Symbol

Variations
Variations Executed Each Cycle for ON Condition OUT NOT
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification (See note.) !OUT NOT

Note Immediate refreshing is not supported by CS1D CPU Units.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Operand Specifications
Area OUT bit operand
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115

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Sequence Output Instructions Section 3-4

Area OUT bit operand

Holding Bit Area H00000 to H51115
Auxiliary Bit Area A44800 to A95915
Timer Area ---
Counter Area ---
TR Area TR0 to TR15
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to ,IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description If there is no immediate refreshing specification, the status of the execution

condition (power flow) is reversed and written to a specified bit in I/O memory.
If there is an immediate refreshing specification, the status of the execution
condition (power flow) is reversed and also written to the Basic Output Unit’s
output terminal in addition to the output bit in I/O memory.
Flags There are no flags affected by this instruction.

Example

Instruction Operand
LD 000000
OUT 000001
OUT NOT 000002

3-4-3 KEEP: KEEP(011)

Purpose Operates as a latching relay.
Ladder Symbol S (Set) KEEP(011)

B B: Bit

R (Reset)

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Sequence Output Instructions Section 3-4

Variations
Variations Executed Each Cycle for ON Condition KEEP(011)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification (See note.) !KEEP(011)

Note Immediate refreshing is not supported by CS1D CPU Units.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Operand Specifications
Area B
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A44800 to A95915
Timer Area ---
Counter Area ---
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description When S turns ON, the designated bit will go ON and stay ON until reset,
regardless of whether S stays ON or goes OFF. When R turns ON, the desig-
nated bit will go OFF. The relationship between execution conditions and
KEEP(011) bit status is shown below.
Set

Reset

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Sequence Output Instructions Section 3-4

ON
S execution condition OFF
ON
R execution condition OFF
ON
Status of C OFF

If S and R are ON simultaneously, the reset input takes precedence.

Set

Reset

Status of C

The set input (S) cannot be received while R is ON.

Set

Reset

Status of C

KEEP(011) has an immediate refreshing variation (!KEEP(011)). When an

external output bit has been specified for B in a !KEEP(011) instruction, any
changes to B will be refreshed when !KEEP(011) is executed and reflected
immediately in the output bit. (The changes will not be reflected immediately if
the bit is allocated to a Group-2 High-density I/O Unit, High-density Special
I/O Unit, or a Unit mounted in a SYSMAC BUS Remote I/O Slave Rack.)
KEEP(011) operates like the self-maintaining bit, but a self-maintaining bit
programmed with KEEP(011) requires one less instruction.

Self-maintaining bits programmed with KEEP(011) will maintain status even in

an interlock program section, unlike the self-maintaining bit programmed with-
out KEEP(011).

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Sequence Output Instructions Section 3-4

Output bit C will maintain its Output bit C will be turned

previous status in an interlock. OFF in an interlock.

KEEP(011) can be used to create flip-flops as shown below.

If a holding bit is used for B, the bit status will be retained even during a power
interruption. KEEP(011) can thus be used to program bits that will maintain
status after restarting the PLC following a power interruption. An example of
this that can be used to produce a warning display following a system shut-
down for an emergency situation is shown below.

Indicates
emergency
situation

Reset input

Activates
warning
display

The status of I/O Area bits can be retained in the event of a power interruption
by turning ON the IOM Hold Bit and setting IOM Hold Bit Hold in the PLC
Setup. In this case, I/O Area bits used in KEEP(011) will maintain status after
restarting the PLC following a power interruption, just like holding bits. Be sure
to restart the PLC after changing the PLC Setup; otherwise the new settings
will not be used.

Flags No flags are affected by KEEP(011).

Precautions Never use an input bit in a normally closed condition on the reset (R) for
KEEP(011) when the input device uses an AC power supply. The delay in
shutting down the PLC’s DC power supply (relative to the AC power supply to

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Sequence Output Instructions Section 3-4

the input device) can cause the operand bit of KEEP(011) to be reset. This sit-
uation is shown below.
Input Unit

A S
KEEP
120000

A NEVER R

The operands for KEEP(011) are input in a different order in ladder diagrams
and mnemonic code.
Ladder diagram order: Set input → KEEP(011) → Reset input
Mnemonic code order: Set input → Reset input → KEEP(011)

Example When CIO 000000 goes ON in the following example, CIO 00500 is turned
ON. CIO 00500 remains ON until CIO 000001 goes ON.
When CIO 000002 goes ON and CIO 000003 goes OFF in the following
example, CIO 00100 is turned ON. CIO 00100 remains ON until CIO 000004
or CIO 000005 goes ON.

Coding
Address Instruction Operand
000100 LD 000000
000101 LD 000001
000102 KEEP (011) 000500
000103 LD 000002
000104 AND NOT 000003
000105 LD 000004
000106 OR 000005
000107 KEEP (011) 000100

Note KEEP(011) is input in different orders on in ladder and mnemonic form. In lad-
der form, input the set input, KEEP(011), and then the reset input. In mne-
monic form, input the set input, the reset input, and then KEEP(011).

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3-4-4 DIFFERENTIATE UP/DOWN: DIFU(013) and DIFD(014)

Purpose DIFU(013) turns the designated bit ON for one cycle when the execution con-
dition goes from OFF to ON (rising edge).
DIFD(014) turns the designated bit ON for one cycle when the execution con-
dition goes from ON to OFF (falling edge).

Ladder Symbols
DIFU(013)

B B: Bit

DIFD(014)

B B: Bit

Variations
Variations Executed Each Cycle for ON Condition Not supported
Executed Once for Upward Differentiation DIFU(013)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification (See note.) !DIFU(013)

Note Immediate refreshing is not supported by CS1D CPU Units.

Variations Executed Each Cycle for ON Condition Not supported

Executed Once for Upward Differentiation DIFD(014)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification (See note.) !DIFD(014)

Note Immediate refreshing is not supported by CS1D CPU Units.

Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Operand Specifications
Area B
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A44800 to A95915
Timer Area ---
Counter Area ---
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---

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Sequence Output Instructions Section 3-4

Area B
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to ,15–(– –) IR

Description When the execution condition goes from OFF to ON, DIFU(013) turns B ON.
When DIFU(013) is reached in the next cycle, B is turned OFF.

Execution condition

Status of B

1 cycle

When the execution condition goes from ON to OFF, DIFD(014) turns B ON.
When DIFD(014) is reached in the next cycle, B is turned OFF.

Execution condition

Status of B
1 cycle

DIFU(013) and DIFD(014) have immediate refreshing variations (!DIFU(013)

and !DIFD(014)). When an external output bit has been specified for B in one
of these instructions, any changes to B will be refreshed when the instruction
is executed and reflected immediately in the output bit. (The changes will not
be reflected immediately if the bit is allocated to a Group-2 High-density I/O
Unit, High-density Special I/O Unit, or a Unit mounted in a SYSMAC BUS
Remote I/O Slave Rack.)
UP(521) and DOWN(522) can be used to execute an instruction for just one
cycle when the execution condition goes from OFF → ON or ON → OFF.
Refer to 3-3-13 CONDITION ON/OFF: UP(521) and DOWN(522) for details.

Flags No flags are affected by DIFU(013) and DIFD(014).

Precautions The operation of DIFU(013) or DIFD(014) depends on the execution condition

for the instruction itself as well as the execution condition for the program sec-
tion when it is programmed in an interlocked program section, a jumped pro-
gram section, or a subroutine. Refer to 3-5-4 INTERLOCK and INTERLOCK
CLEAR: IL(002) and ILC(003), 3-5-6 JUMP and JUMP END: JMP(004) and
JME(005), and 3-20 Interrupt Control Instructions for details.
If DIFU(013) is used in a FOR-NEXT loop and the loop repeats in a cycle, the
controlled bit will be always ON or always OFF within that loop.

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Examples Operation of DIFU(013)

When CIO 000000 goes from OFF to ON in the following example,
CIO 001000 is turned ON for one cycle.

001000

1 cycle 1 cycle

Operation of DIFD(014)
When CIO 000000 goes from ON to OFF in the following example,
CIO 001000 is turned ON for one cycle.

001000

001000

1 cycle 1 cycle

Note Observe the following precaution when using DIFU(013) in a function

block definition.
The operation of DIFU(013) will not be consistent if the same function block
instance is executed more than once in the same cycle.
An instance will not be executed while EN is OFF. Caution is thus required
when using DIFU(013) in a function block definition. For details, refer to infor-
mation on restrictions on using ladder programming instructions in the CX-
Programmer Operation Manual: Function Blocks.
Observe the following precaution when using DIFU(013) in a subroutine.
The operation of DIFU(013) will not be consistent if the same subroutine is
executed more than once in the same cycle.
An subroutine will not be executed while the input condition for the subroutine
is OFF. Caution is thus required when using DIFU(013) in a function block def-
inition. For details, refer to information on SBS(091).

3-4-5 SET and RESET: SET and RSET

Purpose SET turns the operand bit ON when the execution condition is ON.
RSET turns the operand bit OFF when the execution condition is ON.

Ladder Symbols
SET

B B: Bit

RSET

B B: Bit

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Sequence Output Instructions Section 3-4

Variations
Variations Executed Each Cycle for ON Condition SET
Executed Once for Upward Differentiation @SET
Executed Once for Downward Differentiation %SET
Immediate Refreshing Specification (See note.) !SET
Combined Executed Once and Bit Refreshed !@SET
variations Immediately for Upward Differentiation (See
note.)
Executed Once and Bit Refreshed !%SET
Immediately for Downward Differentiation
(See note.)

Note Immediate refreshing is not supported by CS1D CPU Units.

Variations Executed Each Cycle for ON Condition RSET

Executed Once for Upward Differentiation @RSET
Executed Once for Downward Differentiation %RSET
Immediate Refreshing Specification (See note.) !RSET
Combined Immediate Refreshing Once for Upward !@RSET
Variations Differentiation (See note.)
Immediate Refreshing Once for Downward !%RSET
Differentiation (See note.)

Note Immediate refreshing is not supported by CS1D CPU Units.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area B
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A44800 to A95915
Timer Area ---
Counter Area ---
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to ,–(– –) IR15

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Sequence Output Instructions Section 3-4

Description SET turns the operand bit ON when the execution condition is ON, and does
not affect the status of the operand bit when the execution condition is OFF.
Use RSET to turn OFF a bit that has been turned ON with SET.

Execution condition
of SET

Status of B

RSET turns the operand bit OFF when the execution condition is ON, and
does not affect the status of the operand bit when the execution condition is
OFF. Use SET to turn ON a bit that has been turned OFF with RSET.

Execution condition
of RSET

Status of B

SET and RSET have immediate refreshing variations (!SET and !RSET).
When an external output bit has been specified for B in one of these instruc-
tions, any changes to B will be refreshed when the instruction is executed and
reflected immediately in the output bit. (The changes will not be reflected
immediately if the bit is allocated to a Group-2 High-density I/O Unit, High-
density Special I/O Unit, or a Unit mounted in a SYSMAC BUS Remote I/O
Slave Rack.)
The set and reset inputs for a KEEP(011) instruction must be programmed
with the instruction, but the SET and RSET instructions can be programmed
completely independently. Furthermore, the same bit may be used as the
operand in any number of SET or RSET instructions.

Flags No flags are affected by SET and RSET.

Precautions SET and RSET cannot be used to set and reset timers and counters.
When SET or RSET is programmed between IL(002) and ILC(003) or
JMP(004) and JME(005), the status of the specified bit will not be changed if
the program section is interlocked or jumped.
Note SET cannot be used for addresses in the DM and EM Areas. Use SETB(531)
instead.
Note RSET cannot be used for addresses in the DM and EM Areas. Use
RSTB(533) instead.

Example Differences between OUT/OUT NOT and SET/RSET

The operation of SET differs from that of OUT because the OUT instruction
turns the operand bit OFF when its execution condition is OFF. Likewise,
RSET differs from OUT NOT because OUT NOT turns the operand bit ON
when its execution condition is OFF.

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Sequence Output Instructions Section 3-4

000000 010000 CIO 010000 is turned ON/OFF

when CIO 000000 goes ON/OFF.

000001
CIO 010000 is turned ON when
CIO 000001 goes ON; it remains
ON until CIO 000002 goes ON.
000002

3-4-6 MULTIPLE BIT SET/RESET: SETA(530)/RSTA(531)

Purpose SETA(530) turns ON the specified number of consecutive bits.
RSTA(531) turns OFF the specified number of consecutive bits.
Ladder Symbols
SETA(530)

D D: Beginning word

N1 N1: Beginning bit

N2 N2: Number of bits

RSTA(531)

D D: Beginning word

N1 N1: Beginning bit

N2 N2: Number of bits

Variations
Variations Executed Each Cycle for ON Condition SETA(530)
Executed Once for Upward Differentiation @SETA(530)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Variations Executed Each Cycle for ON Condition RSTA(531)

Executed Once for Upward Differentiation @RSTA(531)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands D: Beginning Word

Specifies the first word in which bits will be turned ON or OFF.
N1: Beginning Bit
Specifies the first bit which will be turned ON or OFF. N1 must be #0000 to
#000F (&0 to &15).
N2: Number of Bits
Specifies the number of bits which will be turned ON or OFF. N2 must be
#0000 to #FFFF (&0 to &65535).

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Note The bits being turned ON or OFF must be in the same data area. (The range
of words is roughly D to D+N2÷16.)

to
D: 256 words max.

Operand Specifications
Area D N1 N2
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959 A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM addresses in @ D00000 to @ D32767
binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM addresses in *D00000 to *D32767
BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- #0000 to #000F #0000 to #FFFF
(binary) or &0 to (binary) or &0 to
&15 &65535
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description The operation of SETA(530) and RSTA(531) are described separately below.
Operation of SETA(530)
SETA(530) turns ON N2 bits, beginning from bit N1 of D, and continuing to the
left (more-significant bits). All other bits are left unchanged. (No changes will
be made if N2 is set to 0.)
Bits turned ON by SETA(530) can be turned OFF by any other instructions,
not just RSTA(531).

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N2 bits are set to 1 (ON).

SETA(530) can be used to turn ON bits in data areas that are normally
accessed by words only, such as the DM and EM areas.
Operation of RSTA(531)
RSTA(531) turns OFF N2 bits, beginning from bit N1 of D, and continuing to
the left (more-significant bits). All other bits are left unchanged. (No changes
will be made if N2 is set to 0.)
Bits turned OFF by RSTA(531) can be turned ON by any other instructions,
not just SETA(530).

N2 bits are reset to 0 (OFF).

RSTA(531) can be used to turn OFF bits in data areas that are normally
accessed by words only, such as the DM and EM areas.
Flags
Name Label Operation
Error Flag ER ON if N1 is not within the specified range of 0000 to 000F.
OFF in all other cases.

Examples SETA(530) Example

When CIO 000000 is turned ON in the following example, the 20 bits (0014
hexadecimal) beginning with bit 5 of CIO 0100 are turned ON.

N1: Bit 5

&5 N2: 20 bits

&20

RSTA(531) Example
When CIO 000000 is turned ON in the following example, the 20 bits (0014
hexadecimal) beginning with bit 3 of CIO 0100 are turned OFF.

N1: Bit 3

&3 N2: 20 bits

&20

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Sequence Output Instructions Section 3-4

3-4-7 SINGLE BIT SET/RESET: SETB(532)/RSTB(533)

Purpose SETB(532) turns ON the specified bit.
RSTB(533) turns OFF the specified bit.
These instructions are supported by CS1-H, CJ1-H, CJ1M, and CS1D CPU
Units only.
Ladder Symbols

SETB(532) D: Word address

D N: Bit number
N

RSTB(533)
D: Word address
D N: Bit number
N
Variations
Variations Executed Each Cycle for ON Condition SETB(532)
Executed Once for Upward Differentiation @SETB(532)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification (See note.) !SETB(532)
Combined Executed Once and Bit Refreshed !@SETB(532)
Variations Immediately for Upward Differentiation (See
note.)
Executed Once and Bit Refreshed Not supported
Immediately for Downward Differentiation

Note Immediate refreshing is not supported by CS1D CPU Units.

Variations Executed Each Cycle for ON Condition RSTB(533)

Executed Once for Upward Differentiation @RSTB(533)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification (See note.) !RSTB(533)
Combined Executed Once and Bit Refreshed !@RSTB(533)
Variations Immediately for Upward Differentiation (See
note.)
Executed Once and Bit Refreshed Not supported
Immediately for Downward Differentiation

Note Immediate refreshing is not supported by CS1D CPU Units.

Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands D: Word Address

Specifies the word in which the bit will be turned ON or OFF.
N: Beginning Bit
Specifies the bit which will be turned ON or OFF. N must be #0000 to #000F
(&0 to &15).

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Operand Specifications
Area D N
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959 A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM addresses in @ D00000 to @ D32767
binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM addresses in *D00000 to *D32767
BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- #0000 to #000F (binary)
or &0 to &15
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description The functions of SETB(532) and RSTB(533) are described separately below.
Operation of SETB(532)
SETB(532) turns ON bit N of word D when the execution condition is ON. The
status of the bit is not affected when the execution condition is OFF. Unlike
SET, SETB(532) can turn ON a bit in the DM area or EM area.
15

This bit is turned ON.

Execution condition ON
OFF

Bit N of word D ON
OFF

Bits turned ON by SETB(532) can be turned OFF by any other instruction, not
just RSTB(533).
SETB(532) is supported by CS1-H, CJ1-H, and CJ1M CPU Units only.

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Sequence Output Instructions Section 3-4

Operation of RSTB(533)
RSTB(533) turns OFF bit N of word D when the execution condition is ON.
The status of the bit is not affected when the execution condition is OFF. (Use
SETB(532) to turn ON the bit.) Unlike RST, RSTB(533) can turn OFF a bit in
the DM area or EM area.
15

This bit is turned OFF.

ON
Execution condition OFF

Bit N of word D ON
OFF

Bits turned OFF by RSTB(533) can be turned ON by any other instruction, not
just SETB(532).
RSTB(533) is supported by CS1-H, CJ1-H, and CJ1M CPU Units only.
Flags
Name Label Operation
Error Flag ER ON if N is not within the specified range of 0000 to 000F
(&0 to &15).
OFF in all other cases.

Precautions SETB(532) and RSTB(533) cannot set/reset timers and counters.

When SETB(532) or RSTB(533) is programmed between IL(002) and
ILC(003) or JMP(004) and JME(005), the status of the specified bit will not be
changed if the program section is interlocked or jumped, i.e., when the inter-
lock condition or jump condition is OFF.
SETB(532) and RSTB(533) have immediate refreshing variations
(!SETB(532) and !RSTB(533)). When an external output bit has been speci-
fied in one of these instructions, any changes to the specified bit will be
refreshed when the instruction is executed and reflected immediately in the
output bit. (The changes will not be reflected immediately if the bit is allocated
to a Group-2 High-density I/O Unit, High-density Special I/O Unit, or a Unit
mounted in a SYSMAC BUS Remote I/O Slave Rack.)
Differences between SET/RSET and SETB(532)/RSTB(533)
The SET and RSET instructions operate somewhat differently from
SETB(532) and RSTB(533).
1. The instructions operate in the same way when the specified bit is in the
CIO, W, H, or A Area.
2. The SETB(532) and RSTB(533) instructions can control bits in the DM and
EM Areas, unlike SET and RSET.
Differences between OUTB(534) and SETB(532)/RSTB(533)
The OUTB(534) instruction operates somewhat differently from SETB(532)
and RSTB(533).
1. The SETB(532) and RSTB(533) instructions change the status of the
specified bit only when their execution condition is ON. These instructions
have no effect on the status of the specified bit when their execution con-
dition is OFF.

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Sequence Output Instructions Section 3-4

2. The OUTB(534) instruction turns ON the specified bit when its execution
condition is ON and turns OFF the specified bit when its execution condi-
tion is OFF.
3. The set and reset inputs for a KEEP(011) instruction must be programmed
with the instruction, but the SETB(532) and RSTB(533) instructions can be
programmed completely independently. Furthermore, the same bit may be
used as the operand in any number of SETB(532) and RSTB(533) instruc-
tions.
000000
SETB Bit 02 of D00000 is turned ON
D00000 when CIO 000000 is ON.
&2

000001
RSTB
Bit 02 of D00000 is turned OFF
D00000
when CIO 000001 is ON.
&2

3-4-8 SINGLE BIT OUTPUT: OUTB(534)

Purpose OUTB(534) outputs the status of the instruction’s execution condition to the
specified bit. OUTB(534) can control a bit in the DM Area or EM Area, unlike
OUT.
This instruction is supported by CS1-H, CJ1-H, CJ1M, and CS1D CPU Units
only.
Ladder Symbols

OUTB(534)
D: Word address
D N: Bit number
N
Variations
Variations Executed Each Cycle for ON Condition OUTB(534)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification (See note.) !OUTB(534)

Note Immediate refreshing is not supported by CS1D CPU Units.

Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Operands D: Word Address

Specifies the word containing the bit to be controlled.
N: Beginning Bit
Specifies the bit to be controlled. N must be #0000 to #000F (&0 to &15).

Operand Specifications
Area D N
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959 A000 to A959

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Sequence Output Instructions Section 3-4

Area D N
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM addresses in @ D00000 to @ D32767
binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM addresses in *D00000 to *D32767
BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- #0000 to #000F (binary)
or &0 to &15
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description When the execution condition is ON, OUTB(534) turns ON bit N of word D.
When the execution condition is OFF, OUTB(534) turns OFF bit N of word D.
15 N 0
D

This bit is turned OFF.

ON
Execution condition
OFF

ON
Bit N of word D
OFF

If the immediate refreshing version is not used, the status of the execution
condition (power flow) is written to the specified bit in I/O memory. If the imme-
diate refreshing version is used, the status of the execution condition (power
flow) is written to the Basic Output Unit’s output terminal as well as the output
bit in I/O memory.
OUTB(534) is supported by CS1-H, CJ1-H, and CJ1M CPU Units only.

Flags There are no flags affected by this instruction.

Precautions Immediate refreshing (!OUTB(534)) can be specified. An immediate refresh

instruction updates the status of the output terminal just after the instruction is
executed on an output bit allocated to a Basic Output Unit (but not for C200H
Group 2 Multi-point Output Units or Basic Output Units on Slave Racks), at

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Sequence Control Instructions Section 3-5

the same time as it writes the status of the execution condition (power flow) to
the specified output bit in I/O memory.
When OUTB(534) is programmed between IL(002) and ILC(003), the speci-
fied bit will be turned OFF if the program section is interlocked. (This is the
same as an OUT instruction in an interlocked program section.)
When a word is specified for the bit number (N), only bits 00 to 03 of N are
used. For example, if N contains FFFA hex, OUTB(534) will control bit 10 of
word D.
Note Difference between SETB(532)/RSTB(533) and OUTB(534)
For OUTB(534), the operand bit is turned ON when the input condition turns
ON and is turned OFF when the input condition turns OFF. For SETB(532)
and RSTB(533), the operand bit turns ON or OFF, respectively, when the input
condition turns ON and the operand bit does not change when the input con-
dition turns OFF.

Example
000000
OUTB Bit 10 of D00000 is turned OFF
D00000
when CIO 000000 is OFF.
&10

Note Precaution for Index Registers

OUTB(534) is executed even when the input condition turns OFF. Be particu-
larly careful when programming OUT using an indirect index register address.
Input condition

MOVR
D100
IR0

OUTB When the input condition is OFF,

MOVR(560) is not executed, but
,IR0
OUTB(534) is executed for the address
&15 stored in the index register.

3-5 Sequence Control Instructions

3-5-1 END: END(001)
Purpose Indicates the end of a program.

Ladder Symbol
END(001)
Variations
Variations Executed Each Cycle for ON Condition END(001)
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed Not allowed Not allowed OK

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Sequence Control Instructions Section 3-5

Description END(001) completes the execution of a program for that cycle. No instructions
written after END(001) will be executed.
Execution proceeds to the program with the next task number. When the pro-
gram being executed has the highest task number in the program, END(001)
marks the end of the overall main program.

Task 1 Program A

To the next task number

Task 2 Program B

To the next task number

Task n Program Z

End of the main program

I/O refreshing

Precautions Always place END(001) at the end of each program. A programming error will
occur if there is not an END(001) instruction in the program.

3-5-2 NO OPERATION: NOP(000)

Purpose This instruction has no function. (No processing is performed for NOP(000).)
Ladder Symbol There is no ladder symbol associated with NOP(000).

Variations
Variations Executed Each Cycle for ON Condition NOP(000)
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Description No processing is performed for NOP(000), but this instruction can be used to
set aside lines in the program where instructions will be inserted later. When
the instructions are inserted later, there will be no change in program
addresses.

Flags No flags are affected by NOP(000).

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Sequence Control Instructions Section 3-5

Precautions NOP(000) can only be used with mnemonic displays, not with ladder pro-
grams.

3-5-3 Overview of Interlock Instructions

Interlock Instructions The following instruction combinations can be used to interlock outputs in a
program section.
• INTERLOCK and INTERLOCK CLEAR (IL(002) and IL(003))
• MULTI-INTERLOCK DIFFERENTIATION HOLD and MULTI-INTERLOCK
CLEAR (MILH(517) and MILC(519))*
Note MILH(517) holds the status of the Differentiation Flag, so differentiat-
ed instructions that were interlocked are executed after the interlock
is cleared.
• MULTI-INTERLOCK DIFFERENTIATION RELEASE and MULTI-INTER-
LOCK CLEAR (MILR(518) and MILC(519))*
Note MILR(518) does not hold the status of the Differentiation Flag, so dif-
ferentiated instructions that were interlocked are not executed after
the interlock is cleared.
* These instructions are supported only by CS/CJ-series CPU Unit Ver. 2.0
or later.

Differences between Regular interlocks (IL(002) and IL(003)) cannot be nested, but multiple inter-
Interlocks and Multiple locks (MILH(517), MILR(518), and MILC(519)) can be nested. Ladder pro-
Interlocks gramming can be simplified by nesting multiple interlocks, as shown in the
following diagram.
Interlocks with MILH and MILC Interlocks with IL and ILC
a a
MILH IL
0
A1

A1
ILC
b
a b
MILH
IL
1

A2
A2
ILC
c
MILH a b c
2 IL

A3
A3
ILC
MILC
2

MILC
1

MILC
0

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Sequence Control Instructions Section 3-5

Differences between Differentiated instructions (DIFU, DIFD, or instructions with a @ or % prefix)

MILH(517) and MILR(518) operate differently in interlocks created with MILH(517) and MILR(518).
The operation of differentiated instructions in an interlock created with
MILH(517) is identical to the operation in an interlock created with IL(002).
For details, refer to 3-5-5 MULTI-INTERLOCK DIFFERENTIATION HOLD,
MULTI-INTERLOCK DIFFERENTIATION RELEASE, and MULTI-INTER-
LOCK CLEAR: MILH(517), MILR(518), and MILC(519).

Precautions Do not combine interlocks created with different interlock instructions (IL-ILC,
MILH-MILC, and MILR-MILC). The interlocks may not operate properly if dif-
ferent interlock methods are used together. For details on combining instruc-
tions, refer to 3-5-5 MULTI-INTERLOCK DIFFERENTIATION HOLD, MULTI-
INTERLOCK DIFFERENTIATION RELEASE, and MULTI-INTERLOCK
CLEAR: MILH(517), MILR(518), and MILC(519).
For example, an MILH(517) instruction cannot be inserted between IL(002)
and IL(003).

IL

MILH(517) is in an interlocked area

MILH between IL(002) and ILC.(003).

ILC

Note The different interlocks (IL-ILC, MILH-MILC, and MILR-MILC) can be used
together as long as the interlocked program sections do not overlap.
For example, all three interlock methods can be used without overlapping, as
shown in the following diagram.

IL

ILC

MILH

Different interlock methods can be

used as long as the interlocked
MILC
areas do not overlap.

MILR

MILC

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Sequence Control Instructions Section 3-5

Differences between The following table shows the differences between interlocks (created with
Interlocks and Jumps IL(002)/ILC(003), MILH(517)/MILC(519), or MILR(518)/MILC(519)) and jumps
created with JMP(004)/JME(005).
Item Treatment in IL(002)/ILC(003), MILH(517)/ Treatment in
MILC(519), or MILR(518)/MILC(519)) JMP(004)/JME(005)
Instruction execution Instructions other than OUT, OUT NOT, No instructions are executed.
OUTB(534), and timer instructions are not
executed.
Output status in instructions Except for outputs in OUT, OUT NOT, All outputs retain their previous status.
OUTB(534), and timer instructions, all out-
puts retain their previous status.
Bits in OUT, OUT NOT, OFF All outputs retain their previous status.
OUTB(534)
Status of timer instructions Reset Operating timers (TIM, TIMX(550),
(except (TTIM(087), TIMH(015), TIMHX(551), TMHH(540),
TTIMX(555), MTIM(543), and TMHHX(552), TIMU(541), TIMUX(556),
MTIMX(554)) TMUH(544), TMUHX(557) only) continue
timing because the PVs are updated even
when the timer instruction is not being exe-
cuted.

3-5-4 INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003)

Purpose Interlocks all outputs between IL(002) and ILC(003) when the execution con-
dition for IL(002) is OFF. IL(002) and ILC(003) are normally used in pairs.

Ladder Symbols
IL(002)

ILC(003)

Variations
Variations Interlocks when OFF/Does Not interlock when ON IL(002)
Immediate Refreshing Specification Not supported

Variations Executed Each Cycle for ON Condition ILC(003)

Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed Not allowed OK OK

Description When the execution condition for IL(002) is OFF, the outputs for all instruc-
tions between IL(002) and ILC(003) are interlocked. When the execution con-
dition for IL(002) is ON, the instructions between IL(002) and ILC(003) are
executed normally.
Execution Execution
Execution condition ON condition OFF
condition

Normal Outputs
Interlocked section execution interlocked.
of the program

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Sequence Control Instructions Section 3-5

The following table shows the treatment of various outputs in an interlocked

section between IL(002) and ILC(003).
Instruction Treatment
Bits specified in OUT, OUT NOT, or OUTB(534) OFF
TIM, TIMX(550), TIMH(015), Completion Flag OFF (reset)
TIMHX(551), TMHH(540), PV Time set value (reset)
TMHHX(552), TIML(542), and
TIMXL(553)
TIMU(541), TIMUX(556), Cannot be refer-
TMUH(544), and TMUHX(557) enced.
(See note 1.)
Bits/words specified in all other instructions (See note 2.) Retain previous status.

Note 1. These instructions are supported by the CJ1-H-R CPU Units only.
2. Bits and words in all other instructions including TTIM(087), TTIMX(555),
MTIM(543), MTIMX(554), SET, RSET, CNT, CNTX(546), CNTR(012), CN-
TRX(548), SFT, and KEEP(011) retain their previous status.
If there are bits which you want to remain ON in an interlocked program sec-
tion, set these bits to ON with SET just before IL(002).
It is often more efficient to switch a program section with IL(002) and
ILC(003). When several processes are controlled with the same execution
condition, it takes fewer program steps to put these processes between
IL(002) and ILC(003).

The following table shows the differences between IL(002)/ILC(003) and

JMP(004)/JME(005).
Item Treatment in Treatment in
IL(002)/ILC(003) JMP(004)/JME(005)
Instruction execution Instructions other than OUT, OUT NOT, No instructions are executed.
OUTB(534), and timer instructions are
not executed.
Output status in instructions Except for outputs in OUT, OUT NOT, All outputs retain their previous status.
OUTB(534), and timer instructions, all
outputs retain their previous status.
Bits in OUT, OUT NOT, OUTB(534) OFF All outputs retain their previous status.
Status of timer instructions Reset Operating timers (TIM, TIMX(550),
(except (TTIM(087), TTIMX(555), TIMH(015), TIMHX(551), TMHH(540),
MTIM(543), and MTIMX(554)) TMHHX(552) only) continue timing
because the PVs are updated even
when the timer instruction is not being
executed.

Flags
Name Label Operation
Error Flag ER Unchanged (See note.)
Equals Flag = Unchanged (See note.)
Negative Flag N Unchanged (See note.)

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Sequence Control Instructions Section 3-5

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units, the
Equals and Negative Flags are left unchanged.
In CS1 and CJ1 CPU Units, the Equals and Negative Flags are turned OFF.

Precautions The cycle time is not shortened when a section of the program is interlocked
because the interlocked instructions are executed internally.
The operation of DIFU(013), DIFD(014), and differentiated instructions is not
dependent solely on the status of the execution condition when they are pro-
grammed between IL(002) and ILC(003). Changes in the execution condition
for DIFU(013), DIFD(014), or a differentiated instruction are not recorded if the
DIFU(013) or DIFD(014) is in an interlocked section and the execution condi-
tion for the IL(002) is OFF.
In general, IL(002) and ILC(003) are used in pairs, although it is possible to
use more than one IL(002) with a single ILC(003) as shown in the following
diagram. If IL(002) and ILC(003) are not paired, an error message will appear
when the program check is performed but the program will be executed prop-
erly.

Execution Program section

condition
a b A B
OFF ON Interlocked Interlocked
OFF OFF Interlocked Interlocked
ON OFF Not interlocked Interlocked
ON ON Not interlocked Not interlocked

IL(002) and ILC(003) cannot be nested, as in the following diagram. (Use

MILH(517)/MILR(518) and MILC(519) when it is necessary to nest interlocks.)

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Examples When CIO 000000 is OFF in the following example, all outputs between
IL(002) and ILC(003) are interlocked. When CIO 000000 is ON in the follow-
ing example, the instructions between IL(002) and ILC(003) are executed nor-
mally.

CIO 000000 CIO 000000

ON OFF

OFF

OFF

Normal Outputs
execution
interlocked
Reset

Retained

Retained

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Sequence Control Instructions Section 3-5

3-5-5 MULTI-INTERLOCK DIFFERENTIATION HOLD, MULTI-INTERLOCK

DIFFERENTIATION RELEASE, and MULTI-INTERLOCK CLEAR:
MILH(517), MILR(518), and MILC(519)
Purpose Interlocks all outputs between MILH(517) (or MILR(518)) and MILC(519)
when the execution condition for MILH(517) (or MILR(518)) is OFF. MILH(517)
(or MILR(518)) and MILC(519) are normally used in pairs.
Unlike the IL(002)/ILC(003) interlocks, the MILH(517)/MILC(519) and
MILR(518)/MILC(519) interlocks can be nested. The operation of differenti-
ated instructions is different for interlocks created with MILH(517) and
MILR(518).
These instructions are supported only by CS/CJ-series CPU Unit Ver. 2.0 or
later.
Ladder Symbols
MILH(517)
N N: Interlock Number
D D: Interlock Status Bit

MILR(518)
N N: Interlock Number
D D: Interlock Status Bit

MILC(519)
N N: Interlock Number

Operands N: Interlock Number

The interlock number must be between 0 and 15. Match the interlock number
of the MILH(517) (or MILR(518)) instruction with the same number in the cor-
responding MILC(519) instruction.
The interlock numbers can be used in any order.
D: Interlock Status Bit
• ON when the program section is not interlocked.
• OFF when the program section is interlocked.
When the interlock is engaged, the Interlock Status Bit can be force-set to
release the interlock. Conversely, when the interlock is not engaged, the Inter-
lock Status Bit can be force-reset to engage the interlock.
Operand Specifications
Area N D
CIO Area --- CIO 000000 to CIO 614315
Work Area --- W00000 to W51115
Holding Bit Area --- H00000 to H51115
Auxiliary Bit Area --- A00000 to A95915
Timer Area --- ---
Counter Area --- ---
DM Area --- ---
EM Area without bank --- ---
EM Area with bank --- ---
Indirect DM/EM --- ---
addresses in binary

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Sequence Control Instructions Section 3-5

Area N D
Indirect DM/EM --- ---
addresses in BCD
Constants 0 to 15 ---
Data Registers --- ---
Index Registers --- ---
Indirect addressing --- ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –
2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15

Variations
Variations Interlocks when OFF/Does Not interlock when ON MILH(517) and
MILR(518)
Immediate Refreshing Specification Not supported

Variations Executed Each Cycle for ON Condition MILC(519)

Immediate Refreshing Specification Not supported

Applicable Program Areas The following table shows the applicable program areas for MILH(517),
MILR(518), and MILC(519).
Block program areas Step program areas Subroutines Interrupt tasks
Not allowed Not allowed OK OK

Description When the execution condition for MILH(517) (or MILR(518)) with interlock
number N is OFF, the outputs for all instructions between that MILH(517)/
MILR(518) instruction and the next MILC(519) with interlock number N are
interlocked.
When the execution condition for MILH(517) (or MILR(518)) with interlock
number N is ON, the instructions between that MILH(517)/MILR(518) instruc-
tion and the next MILC(519) with interlock number N are executed normally.
Interlock Status
The following table shows the treatment of various outputs in an interlocked
section between MILH(517)/MILR(518) instruction and the next MILC(519).
Instruction Treatment
Bits specified in OUT, OUT NOT, or OUTB(534) OFF
TIM, TIMX(550), TIMH(015), Completion Flag OFF (reset)
TIMHX(551), TMHH(540), PV Time set value (reset)
TMHHX(552), TIML(542), and
TIMXL(553)
TIMU(541), TIMUX(556), Cannot be refer-
TMUH(544), and TMUHX(557) enced.
(See note 1.)
Bits/words specified in all other instructions (See note 2.) Retain previous status.

Note 1. These instructions are supported by the CJ1-H-R CPU Units only.
2. Bits and words in all other instructions including TTIM(087), TTIMX(555),
MTIM(543), MTIMX(554), SET, RSET, CNT, CNTX(546), CNTR(012), CN-
TRX(548), SFT, and KEEP(011) retain their previous status.

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Sequence Control Instructions Section 3-5

The MILH(517)/MILR(518) instruction turns OFF the Interlock Status Bit

(operand D) when the interlock is in engaged and turns ON the bit when the
interlock is not engaged. Consequently, the Interlock Status Bit can be moni-
tored to check whether or not the interlock for a given interlock number is
engaged.
Input condition ON
(Normal operation) Input condition OFF

MILH
Input condition n
d
Normal Outputs interlocked.
operation (Outputs OFF,
Interlock timers reset, etc.)
Interlocked program Status Bit Interlock Status Bit
section (d) ON (d) OFF

MILC
n

Nesting
Interlocks are nested when an interlocked program section (MILH(517)/
MILR(518) and MILC(519) combination) is placed within another interlocked
program section (MILH(517)/MILR(518) and MILC(519) combination). Inter-
locks can be nested up to 16 levels.
Nesting can be used for the following kinds of applications.
• Example 1
Interlocking the entire program with one condition and interlocking a part
of the program with another condition (1 nesting level)
Global interlock
(Emergency stop)
A1 (Peripheral processing)

Partial interlock
(Conveyor RUN)

A2 (Conveyor operation)

• A1 and A2 are interlocked when the Emergency Stop Button is ON.

• A2 is interlocked when Conveyor RUN is OFF.

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Sequence Control Instructions Section 3-5

Global interlock
(Emergency stop)
MILH When the Emergency Stop is ON (input
condition OFF), both A1 and A2 are
0 interlocked.
When the Emergency Stop is OFF (input
condition ON), A1 is executed normally
and A2 is controlled by the Conveyor
A1 (Peripheral processing) RUN switch as described below.

Partial interlock
(Conveyor RUN)
MILH When the Conveyor RUN switch is OFF
(input condition OFF), A2 is interlocked.
1 When the Conveyor RUN switch is ON
(input condition ON), A2 is executed
normally.

A2 (Conveyor operation)

MILC
1

MILC
0

• Example 2
Interlocking the entire program with one condition and interlocking two
overlapping parts of the program with other conditions (2 nesting levels)
Global interlock
(Emergency stop)
A1 (Peripheral processing)
Partial interlock
(Conveyor RUN)
A2 (Conveyor operation)
Partial interlock
(Arm RUN)
A3 (Arm operation)

• A1, A2, and A3 are interlocked when the Emergency Stop Button is
ON.
• A2 and A3 are interlocked when Conveyor RUN is OFF.
• A3 is interlocked when Arm RUN is OFF.

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Sequence Control Instructions Section 3-5

Global interlock
(Emergency stop)
MILH When the Emergency Stop is ON (input
0 condition OFF), A1, A2, and A3 are
interlocked.
When the Emergency Stop is OFF (input
condition ON), A1 is executed normally and A2
and A3 are controlled by the Conveyor RUN
A1 (Peripheral processing)
and Arm RUN switches as described below.

Partial interlock
(Conveyor RUN)
MILH When the Conveyor RUN switch is OFF (input
1 condition OFF), both A2 and A3 are interlocked.
When the Conveyor RUN switch is ON (input
condition ON), A2 is executed normally and A3 is
controlled by the Arm RUN switch as described
below.
A2 (Conveyor operation)

Partial interlock
(Arm RUN)
MILH When the Arm RUN switch is OFF (input
2 condition OFF), A3 is interlocked.
When the Arm RUN switch is ON (input
condition ON), A3 is executed normally.

A3 (Arm operation)

MILC
2

MILC
1

MILC
0

Differences between MILH(517) and MILR(518)

Differentiated instructions (DIFU, DIFD, or instructions with a @ or % prefix)
operate differently in interlocks created with MILH(517) and MILR(518).
When a program section is interlocked with MILR(518), a differentiated
instruction will not be executed when the interlock is cleared even if the differ-
entiation condition was activated during the interlock (comparing the status of
the execution condition when the interlock started to its status when the inter-
lock was cleared).
When a program section is interlocked with MILH(517), a differentiated
instruction will be executed when the interlock is cleared if the differentiation
condition was activated during the interlock (comparing the status of the exe-
cution condition when the interlock started to its status when the interlock was
cleared).

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Sequence Control Instructions Section 3-5

Instruction Operation of Differentiated Instructions

MILH(517) A differentiated instruction (DIFU, DIFD, or
MULTI-INTERLOCK DIFFER- instruction with a @ or % prefix) will be exe-
ENTIATION HOLD cuted after the interlock is cleared if the differ-
entiation condition of the instruction was
established while the instruction was inter-
locked. (The status of the execution condition
when the interlock started is compared to its
status when the interlock was cleared.)
MILR(518) A differentiated instruction (DIFU, DIFD, or
MULTI-INTERLOCK DIFFER- instruction with a @ or % prefix) will not be
ENTIATION RELEASE executed after the interlock is cleared even if
the differentiation condition of the instruction
was established while the instruction was inter-
locked.

• Operation of Differentiated Instructions in an MILH(517) Interlock

If there is a differentiated instruction (DIFU, DIFD, or instruction with a @
or % prefix) between MILH(517) and the corresponding MILC(519), that in-
struction will be executed after the interlock is cleared if the differentiation
condition of the instruction was established. (The system compares the ex-
ecution condition’s status when the interlock started to its status when the
interlock was cleared.)
In the same way, a differentiated instruction will be executed if its execution
condition is established at the same time that the interlock is started or
cleared.
Many other conditions in the program may cause the differentiation condi-
tion to be reset even if it was established during the interlock. In this case,
the differentiation instruction will not be executed when the interlock is
cleared.
• Example
When a DIFFERENTIATE UP (DIFU(013)) instruction is being used
and the input condition is OFF when the interlock starts and ON when
the interlock is cleared, DIFU(013) will be executed when the interlock
is cleared. (Differentiated instructions operate the same in the
MILH(517) interlock as they would in an IL(002) interlock.)
000000
MILH
0

1. When CIO 000000 is OFF (interlock starts), the DIFU's CIO 000001 input condition is OFF.
2. The DIFU's CIO 000001 input condition goes from OFF to ON while CIO 000000 is OFF (DIFU interlocked),
3. When CIO 000000 goes from OFF to ON (interlock cleared), DIFU is executed if CIO 000001 is still ON.
000001
DIFU
001000

MILC
0

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Sequence Control Instructions Section 3-5

Timing Chart
Not interlocked Interlocked Not interlocked

ON
000000
OFF
Status (OFF) at
start of interlock ON Differentiation condition established
ON
000001
OFF
OFF Status (ON) when
MILH(517) interlock interlock is cleared
DIFU(013) is executed.

ON
001000
OFF

1 cycle

• Operation of Differentiated Instructions in an MILR(518) Interlock

If there is a differentiated instruction (DIFU, DIFD, or instruction with a @
or % prefix) between MILR(518) and the corresponding MILC(519), that in-
struction will not be executed after the interlock is cleared even if the dif-
ferentiation condition of the instruction was established. (The system
compares the execution condition’s status in the cycle when the interlock
started to its status in the cycle when the interlock was cleared.)
In the same way, a differentiated instruction will not be executed if its exe-
cution condition is established at the same time that the interlock is started
or cleared.
• Example
When a DIFFERENTIATE UP (DIFU(013)) instruction is being used
and the input condition is OFF when the interlock starts and ON when
the interlock is cleared, DIFU(013) will not be executed when the in-
terlock is cleared.
000000
MILR
0

1. When CIO 000000 is OFF (interlock starts), the DIFU's CIO 000001 input condition is OFF.
2. The DIFU's CIO 000001 input condition goes from OFF to ON while CIO 000000 is OFF (DIFU interlocked),
3. When CIO 000000 goes from OFF to ON (interlock cleared), DIFU is not executed even though CIO 000001 is still ON.
000001
DIFU
001000

MILC
0

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Sequence Control Instructions Section 3-5

Timing Chart
Not interlocked Interlocked Not interlocked

ON
000000
OFF

ON
ON
000001
OFF
OFF

MILR(518) interlock
ON DIFU(013) is not executed.
001000
OFF

Controlling Interlock Status from a Programming Device

An interlock can be engaged or released manually by force-resetting or force-
setting the Interlock Status Bit (specified with operand D of MILH(517) and
MILR(518)) from a Programming Device. The forced status of the Interlock
Status Bit has priority and overrides the interlock status calculated by program
execution.
Force-set: Releases the interlock.
OFF
MILH
n
010000 CIO 010000 is OFF when the interlock is engaged.

Program section
controlled by interlock If CIO 010000 is force-set (ON), the interlock is released.

MILC
n

Force-reset: Engages the interlock.

ON
MILH
n
010000 CIO 010000 is ON when the interlock is not engaged.

Program section
controlled by interlock If CIO 010000 is force-reset (OFF), the interlock is engaged.

MILC
n

Note Program operation can be switched more efficiently by using interlocks with
MILH(517) or MILR(518).
Instead of switching processing with compound conditions, insert an
MILH(517) or MILR(518) instruction before each process and an MILC(519)
instruction after each process.

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Sequence Control Instructions Section 3-5

a a
A1 MILH
0

b
A2 A1

b
MILH
1

A2

MILC
1

MILC
0

Unlike the IL(002) interlocks, MILH(517) and MILR(518) interlocks can be

nested, so the operation of similar programs will be different if MILH(517) or
MILR(518) is used instead of ILC(002).
Program with MILH(517)/MILC(519) Interlocks
a
MILH
0
010000

A1

b
MILH
1
010001

A2

MILC
1

A3

MILC
0

Execution Program section

condition
a b A1 A2 A3
OFF ON Interlocked Interlocked Not interlocked
OFF
ON OFF Not interlocked Interlocked Not interlocked
ON ON Not interlocked Not interlocked Not interlocked

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Sequence Control Instructions Section 3-5

Program with IL(002)/ILC(003) Interlocks

a
IL

A1

b
IL

A2

ILC

This program section is not

A3 controlled by the interlock.

ILC This ILC(003)

instruction is ignored
so ...

Execution Program section

condition
a b A1 A2 A3
OFF ON Interlocked Interlocked Not interlocked
OFF (Not controlled by
ON OFF Not interlocked Interlocked the IL(002)/
ILC(003) interlock.)
ON ON Not interlocked Not interlocked

If there are bits which you want to remain ON in a program section interlocked
by MILH(517) or MILR(518), set these bits to ON with SET just before the
MILH(517) or MILR(518) instruction.

Flags
Name Label Operation
Error Flag ER OFF

Precautions The cycle time is not shortened when a section of the program is interlocked
by MILH(517) or MILR(518) because the interlocked instructions are executed
internally.

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Sequence Control Instructions Section 3-5

When nesting interlocks, assign interlock numbers so that the nested program
section does not exceed the outer program section.
a
MILH
0

A1

b
MILH
1

A2

MILC
0

A3
The nested program section
MILC must not go beyond the outer
program section.
1

Execution Program section

condition
a b A1 A2 A3
OFF ON Interlocked Interlocked Not interlocked
OFF
ON OFF Not interlocked Interlocked Interlocked
ON Not interlocked Not interlocked Not interlocked

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Sequence Control Instructions Section 3-5

Other instructions can be input between the MILC(519) instructions, as shown

in the following diagram.
a
MILH
0
010000

A1

b
MILH
1
010001

A2

MILC
1
Other instructions can be inserted between
two MILC(519) instructions. In this case,
A3 sections A1 and A3 operate together. (They
are interlocked when "a" is OFF, regardless
of the ON/OFF status of "b".)
MILC
0

If there is an ILC(003) instruction between an MILH(517) and MILC(519) pair,

the program section between MILH(517) and ILC(003) will be interlocked.
a
MILH When input condition "a" is OFF, only
program section A1 is interlocked.
0

A1

If there is an ILC(003) instruction,

ILC the interlock is cleared at that point.

A2

The MILC(519) instruction is ignored.

MILC
0

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Sequence Control Instructions Section 3-5

If there is an ILC(003) instruction between an MILR(518) and MILC(519) pair,

the ILC(003) instruction will be ignored and the full program section between
MILR(518) and MILC(519) will be interlocked.
a
MILR When input condition "a" is OFF, program
sections A1 and A2 are interlocked.
0

A1

The ILC(003) instruction is ignored.

ILC

A2

MILC
0

If there is another MILH(517) or MILR(518) instruction with the same interlock

number between an MILH(517) and MILC(519) pair and the first MILH(517)
instruction’s interlock is engaged, the second MILH(517)/MILR(518) will not
operate.
If there is another MILH(517) or MILR(518) instruction with the same interlock
number between an MILH(517) and MILC(519) pair and the first MILH(517)
instruction’s interlock is not engaged, the second MILH(517)/MILR(518) will
operate normally.
a
MILH When input condition "a" is OFF, program
sections A1 and A2 are both interlocked,
0 even if input condition "b" is ON.

A1

b
MILH When input condition "a" is ON and "b"
is OFF, only program section A2 is
0
interlocked.

A2

MILC
0

Note The MILR(518) interlocks operate in the same way if there is another
MILH(517) or MILR(518) instruction with the same interlock number between
an MILR(518) and MILC(519) pair.
If there is an MILC(519) instruction with a different interlock number between
an MILH(517)/MILR(518) and MILC(519) pair, that MILC(519) instruction will
be ignored.

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Sequence Control Instructions Section 3-5

a
MILH When input condition "a" is OFF, program
sections A1 and A2 are both interlocked.
0

A1

This MILC(519) instruction is ignored.

MILC
1

A2

MILC
0

If there is an MILH(517) instruction between an IL(002) and ILC(003) pair and

the IL(002) interlock is engaged, the MILH(517) instruction has no effect. In
this case, the program section between IL(002) and ILC(003) will be inter-
locked.
If the IL(002) interlock is not engaged and the MILH(517) instruction’s execu-
tion condition (b in this case) is OFF, the program section between MILH(517)
and ILC(003) will be interlocked.
a
IL When input condition "a" is OFF, program
sections A1 and A2 are both interlocked.

A1

b
If the program section is not interlocked
MILH by IL(002) and "b" is OFF, program
0 section A2 is interlocked.

A2

ILC

If there is an MILC(519) instruction between an IL(002) and ILC(003) pair, that

MILC(519) instruction will be ignored and the entire program section between
IL(002) and ILC(003) will be interlocked.
a
IL When input condition "a" is OFF, program
sections A1 and A2 are both interlocked.

A1

The MILC(519) instruction is ignored.

MILC
0

A2

ILC

Examples When W00000 and W00001 are both ON, the instructions between
MILH(517) with interlock number 0 and MILC(519) with interlock number 0 are
executed normally.

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When W00000 is OFF, the instructions between MILH(517) with interlock

number 0 and MILC(519) with interlock number 0 are interlocked.
When W00000 is ON and W00001 are OFF, the instructions between
MILH(517) with interlock number 1 and MILC(519) with interlock number 1 are
interlocked. The other instructions are executed normally.
W00000 and W00001 W00000 ON and W00001
both ON W0000 OFF OFF
W00000
MILH
0
010000
Executed
normally.
000001 000200
OFF

W00001
MILH
1
010001

000002 H0000
Executed
OFF
normally.
Outputs
interlocked.
SET Held Outputs
interlocked.
000003

MILC
1

CNT
1 Executed
Held normally.
#0010

MILC
0

3-5-6 JUMP and JUMP END: JMP(004) and JME(005)

Purpose When the execution condition for JMP(004) is OFF, program execution jumps
directly to the first JME(005) in the program with the same jump number.
JMP(004) and JME(005) are used in pairs.

Ladder Symbols
JMP(004)

N N: Jump number

JME(005)

N N: Jump number

Variations
Variations Jumps when OFF/Does Not Jump when ON JMP(004)
Immediate Refreshing Specification Not supported

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Sequence Control Instructions Section 3-5

Variations Executed Each Cycle for ON Condition JME(005)

Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK Not allowed OK OK

Operands N: Jump Number

The jump number must be 0000 to 03FF (&0 to &1,023 decimal).
Note For CJ1M-CPU11 and CJ1M-CPU21 CPU Units, the jump number must be
between the range 0000 to 00FF hex or &0 to &255 decimal.

Operand Specifications
Area N
JMP(004) JME(005)
CIO Area CIO 0000 to CIO 6143 ---
Work Area W000 to W511 ---
Holding Bit Area H000 to H511 ---
Auxiliary Bit Area A000 to A959 ---
Timer Area T0000 to T4095 ---
Counter Area C0000 to C4095 ---
DM Area D00000 to D32767 ---
EM Area without bank E00000 to E32767 ---
EM Area with bank En_00000 to En_32767 ---
(n = 0 to C)
Indirect DM/EM addresses @ D00000 to @ D32767 ---
in binary @ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)
Indirect DM/EM addresses *D00000 to *D32767 ---
in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #03FF (binary) or #0000 to #03FF (binary) or
&0 to &1023 (See note.) &0 to &1023 (See note.)
Data Registers DR0 to DR15 ---
Index Registers --- ---
Indirect addressing using ,IR0 to ,IR15 ---
Index Registers –2048 to +2047, IR0 to
–2048 to +2047, IR15
DR0 to DR15, IR0 to IR15

Note For CJ1M-CPU11 and CJ1M-CPU21 CPU Units, the range is #0000 to #00FF
(binary) or &0 to &1023 (decimal).

Description When the execution condition for JMP(004) is ON, no jump is made and the
program is executed consecutively as written.
When the execution condition for JMP(004) is OFF, program execution jumps
directly to the first JME(005) in the program with the same jump number. The
instructions between JMP(004) and JME(005) are not executed, so the status
of outputs between JMP(004) and JME(005) is maintained. In block programs,

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Sequence Control Instructions Section 3-5

the instructions between JMP(004) and JME(005) are skipped regardless of

the status of the execution condition.
Execution condition
Instructions
jumped

Instructions in this section are not

Instructions executed and output status is
executed maintained. The instruction execution
time for these instructions is eliminated.

Because all of instructions between JMP(004)/CJP(510)/CJPN(511) and

JME(005) are skipped when the execution condition for JMP(004) is OFF, the
cycle time is reduced by the total execution time of the skipped instructions. In
contrast, processing time equivalent to NOP(000) processing is required for
instructions between JMP0(515) and JME0(516), so the cycle time is not
reduced as much with those jump instructions.
The following table compares the various jump instructions.
Item JMP(004) CJP(510) CJPN(511) JMP0(515)
JME(005) JME(005) JME(005) JME0(516)
Execution condition for jump OFF ON OFF OFF
Number allowed 1,024 total (256 for CJ1M-CPU11/21.) No limit
Instruction processing when jumped Not executed. NOP(000) processing
Instruction execution time when None Equivalent to
jumped NOP(000) instructions
Status of outputs (bits and words) Bits and words maintain their previous status.
when jumped
Status of operating timers when Operating timers continue timing.
jumped
Processing in block programs Always jump. Jump when ON. Jump when OFF. Not allowed.

Flags (JMP)
Name Label Operation
Error Flag ER ON if N is not within the specified range of 0000 to 03FF.
(See note.)
ON if there is a JMP(004) in the program without a
JME(005) with the same jump number.
ON if there is a JMP(004) in the task without a JME(005)
with the same jump number in the task.
OFF in all other cases.

Note For CJ1M-CPU11 and CJ1M-CPU21 CPU Units, the range is 0 to 255 (0000
to 00FF hex).

Precautions All of the outputs (bits and words) in jumped instructions retain their previous
status. Operating timers (TIM, TIMX(550), TIMH(015), TIMHX(551),
TMHH(540), TMHHX(552), TIMU(541), TIMUX(556), TMUH(544), and
TMUHX(557)) continue timing because the PVs are updated even when the
timer instruction is not being executed.
When there are two or more JME(005) instructions with the same jump num-
ber, only the instruction with the lower address will be valid. The JME(005)
with the higher program address will be ignored.

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Sequence Control Instructions Section 3-5

When JME(005) precedes JMP(004) in the program, the instructions between

JME(005) and JMP(004) will be executed repeatedly as long as the execution
condition for JMP(004) is OFF. A Cycle Time Too Long error will occur if the
execution condition is not turned ON or END(001) is not executed within the
maximum cycle time.

Program section A is executed

repeatedly as long as
execution condition a is OFF.

In block programs, the instructions between JMP(004) and JME(005) are

always skipped regardless of the status of the execution condition for
JMP(004).

Block program section

JMP &1
to
JME &1

JMP(004) and JME(005) pairs must be in the same task because jumps
between tasks are not allowed. An error will occur if a JME(005) instruction is
not programmed in the same task as its corresponding JMP(004) instruction.
The operation of DIFU(013), DIFD(014), and differentiated instructions is not
dependent solely on the status of the execution condition when they are pro-
grammed between JMP(004) and JME(005). When DIFU(013), DIFD(014), or
a differentiated instruction is executed in an jumped section immediately after
the execution condition for the JMP(004) has gone ON, the execution condi-
tion for the DIFU(013), DIFD(014), or differentiated instruction will be com-
pared to the execution condition that existed before the jump became effective
(i.e., before the execution condition for JMP(004) went OFF).
Examples Basic Operation
When CIO 000000 is OFF in the following example, the instructions between
JMP(004) and JME(005) are not executed and the outputs maintain their pre-
vious status.
When CIO 000000 is ON in the following example, the instructions between
JMP(004) and JME(005) are executed normally.

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Sequence Control Instructions Section 3-5

CIO 000000 CIO 000000

&1 ON OFF

Normal Instructions
execution not executed.
(Outputs re-
main un-
changed.)

&1

3-5-7 CONDITIONAL JUMP: CJP(510)/CJPN(511)

Purpose The operation of CJP(510) is the basically the opposite of JMP(004). When
the execution condition for CJP(510) is ON, program execution jumps directly
to the first JME(005) in the program with the same jump number. CJP(510)
and JME(005) are used in pairs.
The operation of CJPN(511) is almost identical to JMP(004). When the execu-
tion condition for CJP(004) is OFF, program execution jumps directly to the
first JME(005) in the program with the same jump number. CJPN(511) and
JME(005) are used in pairs.
Ladder Symbols
CJP(510)

N N: Jump number

CJPN(511)

N N: Jump number
Variations
Variations Jumps when ON/Does Not Jump when OFF CJP(510)
Immediate Refreshing Specification Not supported

232
Sequence Control Instructions Section 3-5

Variations Jumps when OFF/Does Not Jump when ON CJPN(511)

Immediate Refreshing Specification Not supported

Variations Executed Each Cycle for ON Condition JME(005)

Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK Not allowed OK OK

Operands N: Jump Number

The jump number must be 0000 to 03FF (0 to 1,023 decimal).
Note For CJ1M-CPU11 and CJ1M-CPU21 CPU Units, the jump number must be
between the range 0000 to 00FF hex or &0 to &255 decimal.

Operand Specifications
Area N
CJP(510) CJPN(511) JME(005)
CIO Area CIO 0000 to CIO 6143 ---
Work Area W000 to W511 ---
Holding Bit Area H000 to H511 ---
Auxiliary Bit Area A000 to A959 ---
Timer Area T0000 to T4095 ---
Counter Area C0000 to C4095 ---
DM Area D00000 to D32767 ---
EM Area without E00000 to E32767 ---
bank
EM Area with bank En_00000 to En_32767 ---
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767 ---
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767 ---
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #03FF (binary) or &0 to &1023 #0000 to #03FF
(See note.) (binary) or &0 to
&1023 (See note.)
Data Registers DR0 to DR15 ---
Index Registers --- ---
Indirect addressing ,IR0 to ,IR15 ---
using Index Regis- –2048 to +2047, IR0 to –2048 to +2047,
ters IR15
DR0 to DR15, IR0 to IR15

Note For CJ1M-CPU11 and CJ1M-CPU21 CPU Units, the range is #0000 to #00FF
(binary) or &0 to &1023 (decimal).

Description The operation of CJP(510) and CJPN(511) differs only in the execution condi-
tion. CJP(510) jumps to the first JME(005) when the execution condition is ON

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Sequence Control Instructions Section 3-5

and CJPN(511) jumps to the first JME(005) when the execution condition is
OFF.
Because the jumped instructions are not executed, the cycle time is reduced
by the total execution time of the jumped instructions.
Operation of CJP(510)
When the execution condition for CJP(510) is OFF, no jump is made and the
program is executed consecutively as written.
When the execution condition for CJP(510) is ON, program execution jumps
directly to the first JME(005) in the program with the same jump number.
Execution Execution
condition OFF condition ON
Instructions
jumped

Instructions in this section are not

Instructions executed and output status is
executed maintained. The instruction execution
time for these instructions is eliminated.

Operation of CJPN(511)
When the execution condition for CJPN(511) is ON, no jump is made and the
program is executed consecutively as written.
When the execution condition for CJPN(511) is OFF, program execution
jumps directly to the first JME(005) in the program with the same jump num-
ber.
Execution Execution
condition ON condition OFF
Instructions
jumped

Instructions in this section are not

executed and output status is
Instructions maintained. The instruction execution
executed time for these instructions is eliminated.

Flags The following table shows the flags affected by CJP(510) and CJPN(511).
Name Label Operation
Error Flag ER ON if there is not a JME(005) with the same jump number
as CJP(510) or CJPN(511). (See note.)
ON if N is not within the specified range of 0000 to 03FF.
ON if there is a CJP(510) or CJPN(511) instruction in a
task without a JME(005) with the same jump number.
OFF in all other cases.

Note For CJ1M-CPU11 and CJ1M-CPU21 CPU Units, the jump number must be
between the range 0 to 255 (0000 to 00FF hex).

Precautions All of the outputs (bits and words) in jumped instructions retain their previous
status. Operating timers (TIM, TIMX(550), TIMH(015), TIMHX(551),
TMHH(540), and TMHHX(552)) continue timing be-cause the PVs are
updated even when the timer instruction is not being executed.

234
Sequence Control Instructions Section 3-5

When there are two or more JME(005) instructions with the same jump num-
ber, only the instruction with the lower address will be valid. The JME(005)
with the higher program address will be ignored.
When JME(005) precedes the CJP(510) or CJPN(511) instruction in the pro-
gram, the instructions in-between will be executed repeatedly as long as the
execution condition remains OFF (CJP(510)) or ON (CJPN(511)). A Cycle
Time Too Long error will occur if the jump is not completed by changing the
execution condition executing END(001) within the maximum cycle time.
The CJP(510) or CJPN(511) instructions will operate normally in block pro-
grams.
When the execution condition for the CJP(510) is ON or the execution condi-
tion for CJPN(511) is OFF, program execution will jump directly to the JME
instruction without executing instructions between CJP(510)/CJPN(511) and
JME. No execution time will be required for these instructions and the cycle
time will thus be reduced.
When the execution condition for the JMP0 is OFF, NOP processing is exe-
cuted between the JMP0 and JME0, requiring execution time. Therefore, the
cycle time will not be reduced.
When a CJP(510) or CJPN(511) instruction is programmed in a task, there
must be a JME(005) with the same jump number because jumps between
tasks are not allowed. An error will occur if a corresponding JME(005) instruc-
tion is not programmed in the same task.
The operation of DIFU(013), DIFD(014), and differentiated instructions is not
dependent solely on the status of the execution condition when they are pro-
grammed in a jumped program section. When DIFU(013), DIFD(014), or a dif-
ferentiated instruction is executed in an jumped section immediately after the
execution condition for the CJP(510) has gone OFF (ON for CJPN(511)), the
execution condition for the DIFU(013), DIFD(014), or differentiated instruction
will be compared to the execution condition that existed before the jump
became effective.

Example When CIO 000000 is ON in the following example, the instructions between
CJP(510) and JME(005) are not executed and the outputs maintain their pre-
vious status.
When CIO 000000 is OFF in the following example, the instructions between
CJP(510) and JME(005) are executed normally.

235
Sequence Control Instructions Section 3-5

CIO 000000 CIO 000000

ON OFF
&1

Instructions
not Normal
executed. execution
(Outputs
remain un-
changed.)

&1

Note For CJPN(511), the ON/OFF status of CIO 000000 would be reversed.

3-5-8 MULTIPLE JUMP and JUMP END: JMP0(515) and JME0(516)

Purpose When the execution condition for JMP0(515) is OFF, all instructions from
JMP0(515) to the next JME0(516) in the program are processed as
NOP(000). Use JMP0(515) and JME0(516) in pairs. There is no limit on the
number of pairs that can be used in the program.

Ladder Symbols
JMP0(515)

JME0(516)

Variations
Variations Jumps when OFF/Does Not Jump when ON JMP0(515)
Immediate Refreshing Specification Not supported

Variations Executed Each Cycle for ON Condition JME0(516)

Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed Not allowed OK OK

236
Sequence Control Instructions Section 3-5

Description When the execution condition for JMP0(515) is ON, no jump is made and the
program executed consecutively as written.
When the execution condition for JMP0(515) is OFF, all instructions from
JMP0(515) to the next JME0(516) in the program are processed as
NOP(000). Unlike JMP(004), CJP(510), and CJPN(511), JMP0(515) does not
use jump numbers, so these instructions can be placed anywhere in the pro-
gram.
Execution Execution
condition a ON condition a OFF
Instructions
jumped
Instructions
executed

Jumped instructions are processed as

NOP(000). Instruction execution times
Execution are the same as NOP(000).
condition b ON Execution
condition b OFF

Instructions
executed

Instructions
jumped

Unlike JMP(004), CJP(510), and CJPN(511) which jump directly to the first
JME(005) instruction in the program, all of the instructions between
JMP0(515) and JME0(516) are executed as NOP(000). The execution time of
the jumped instructions will be reduced, but not eliminated. The jumped
instructions themselves are not executed and their outputs (bits and words)
maintain their previous status.

Precautions Multiple pairs of JMP0(515) and JME0(516) instructions can be used in the
program, but the pairs cannot be nested.
JMP0(515) and JME0(516) cannot be used in block programs.
JMP0(515) and JME0(516) pairs must be in the same tasks because jumps
between tasks are not allowed.
The operation of DIFU(013), DIFD(014), and differentiated instructions is not
dependent solely on the status of the execution condition when they are pro-
grammed between JMP0(515) and JME0(516). When DIFU(013), DIFD(014),
or a differentiated instruction is executed in an jumped section immediately
after the execution condition for the JMP0(515) has gone ON, the execution
condition for the DIFU(013), DIFD(014), or differentiated instruction will be
compared to the execution condition that existed before the jump became
effective (i.e., before the execution condition for JMP0(515) went OFF).
Example When CIO 000000 is OFF in the following example, the instructions between
JMP0(515) and JME0(516) are processed as NOP(000) instructions and the
outputs maintain their previous status.
When CIO 000000 is ON in the following example, the instructions between
JMP0(515) and JME0(516) are executed normally.

237
Sequence Control Instructions Section 3-5

CIO 000000 CIO 000000

ON OFF

Normal Instructions
execution processed
as
NOP(000).
(Outputs re-
main un-
changed.)

3-5-9 FOR-NEXT LOOPS: FOR(512)/NEXT(513)

Purpose The instructions between FOR(512) and NEXT(513) are repeated a specified
number of times. FOR(512) and NEXT(513) are used in pairs.

Ladder Symbols
FOR(512)

N N: Number of loops

NEXT(513)
Variations
Variations Executed Each Cycle for ON Condition FOR(512)
Executed Each Cycle for ON Condition NEXT(513)
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Operands N: Number of Loops

The number of loops must be 0000 to FFFF (0 to 65,535 decimal).

238
Sequence Control Instructions Section 3-5

Operand Specifications
Area N
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF (binary) or &0 to &65,535
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description The instructions between FOR(512) and NEXT(513) are executed N times
and then program execution continues with the instruction after NEXT(513).
The BREAK(514) instruction can be used to cancel the loop.
If N is set to 0, the instructions between FOR(512) and NEXT(513) are pro-
cessed as NOP(000) instructions.
Loops can be used to process tables of data with a minimum amount of pro-
gramming.

Repeated N times

Repeated program section

FOR-NEXT loops can be nested up to 15 levels. In the example below, pro-

gram sections A, B, and C are executed as follows:
A → B → B → C, A → B → B → C, and A → B → B → C

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Sequence Control Instructions Section 3-5

&3

&2

Use BREAK(514) to escape from a FOR-NEXT loop. Several BREAK(514)

instructions (the number of levels nested) are required to escape from nested
loops. The remaining instructions in the loop after BREAK(514) are processed
as NOP(000) instructions.

&3 Escapes from &3

loop when
condition a is
ON.
&2
Remaining
Breaks FOR-NEXT loop 2.
instructions are
processed as 1 2
NOP(000).

Breaks FOR-NEXT loop 1.

Alternative Looping Methods

There are two ways to repeat a program section until a given execution condi-
tion is input.
1,2,3... 1. FOR-NEXT Loop with BREAK
Start a FOR-NEXT loop with a maximum of N repetitions. Program
BREAK(514) within the loop with the desired execution condition. The loop
will end before N repetitions if the execution condition is input.
2. JME(005)-JMP(004) Loop
Program a loop with JME(005) before JMP(004). The instructions between
JME(005) and JMP(004) will be executed repeatedly as long as the execu-
tion condition for JMP(004) is OFF. (A Cycle Time Too Long error will occur
if the execution condition is not turned ON or END(001) is not executed
within the maximum cycle time.)

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Sequence Control Instructions Section 3-5

Flags
Name Label Operation
Error Flag ER ON if more than 15 loops are nested.
OFF in all other cases.
Equals Flag = OFF
Negative Flag N OFF
Precautions Program FOR(512) and NEXT(513) in the same task. Execution will not be
repeated if these instructions are not in the same task.
A jump instruction such as JMP(004) may be executed within a FOR-NEXT
loop, but do not jump beyond the FOR-NEXT loop.
The following instructions cannot be used within FOR-NEXT loops:
• Block programming instructions
• MULTIPLE JUMP and JUMP END: JMP(515) and JME(516)
• STEP DEFINE and STEP START: STEP(008)/SNXT(009)
Note If a loop repeats in one cycle and a differentiated bit is used in the FOR-NEXT
loop, that bit will be always ON or always OFF within that loop.

Example In the following example, the looped program section transfers the content of
D00100 to the address indicated in D00200 and then increments the content
of D00200 by 1.

&3 Repeated 3 times.

D00100
@D00200

D00200

#0000

3-5-10 BREAK LOOP: BREAK(514)

Purpose Programmed in a FOR-NEXT loop to cancel the execution of the loop for a
given execution condition. The remaining instructions in the loop are pro-
cessed as NOP(000) instructions.

Ladder Symbol
BREAK(514)

Variations
Variations Executed Each Cycle for ON Condition BREAK(514)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

241
Timer and Counter Instructions Section 3-6

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Description Program BREAK(514) between FOR(512) and NEXT(513) to cancel the

FOR-NEXT loop when BREAK(514) is executed. When BREAK(514) is exe-
cuted, the rest of the instructions up to NEXT(513) are processed as
NOP(000).
Condition a ON
N repetitions

Repetitions
forced to end.

Processed as NOP(000).

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = OFF
Negative Flag N OFF

Precautions A BREAK(514) instruction cancels only one loop, so several BREAK(514)

instructions (the number of levels nested) are required to escape from nested
loops.
BREAK(514) can be used only in a FOR-NEXT loop.

3-6 Timer and Counter Instructions

This section describes instructions used to define and handle timers and
counters.
Instruction Mnemonic Function code Page
HUNDRED-MS TIMER TIM/TIMX ---/551 245
TEN-MS TIMER TIMH/TIMHX 015/551 249
ONE-MS TIMER TMHH/TIMHHX 540/552 253
TENTH-MS TIMER (See note.) TIMU/TIMUX 541/556 256
HUNDREDTH-MS TIMER (See note.) TMUH/TMUHX 544/557 259
ACCUMULATIVE TIMER TTIM/TTIMX 087/555 262
LONG TIMER TIML/TIMLX 542/553 266
MULTI-OUTPUT TIMER MTIM/MTIMX 543/554 269
COUNTER CNT/CNTX ---/546 275
REVERSIBLE COUNTER CNTR/CNTRX 012/548 278
RESET TIMER/COUNTER CNR/CNRX 545/547 282

Note TIMU(541), TIIMUX(556), TMUH(544), and TMUHX(557) are supported by

CJ1-H-R CPU Units only.

242
Timer and Counter Instructions Section 3-6

Refresh Methods for Timer/Counter PV

■ Overview
In the CS1-H, CS1D, CJ1-H, and CJ1M CPU Units, the PV refresh method
can be set to either BCD or binary for all of the timer/counter-related instruc-
tions. (See notes 1 and 2.)
Using binary data instead of BCD allows the SV range for timers and counter
to be increased from 0 to 9999 to 0 to 65535. It also enables using binary data
calculated with other instructions directly as a timer/counter SV. The refresh
method is valid even when setting an SV indirectly (i.e., using the contents of
memory word). (That is, the contents of the addressed word is taken as either
BCD or binary data according to the refresh method that is set.)
Refer to 6-4 Changing the Timer/Counter PV Refresh Mode in the CS/CJ
Series Programming Manual (W394) for details on refresh methods.
Note 1. With CS1-H and CJ1-H CPU Units manufactured prior to 31 May 2002, the
binary instructions will be displayed on the Programming Console with the
mnemonic of the equivalent instruction for BCD operation. (For example,
TIMX0 &16 will be displayed as TIM0 &16.) The instruction, however, will
operate using binary mode.
2. The refresh method can be selected only with CX-Programmer version 3.0
or later. It cannot be selected with version 2.1 or early, or from a Program-
ming Console.
3. User programs that use the binary update mode cannot be read with CX-
Programmer version 2.1 or lower. They can be read only by changing to
BCD mode.
■ Applicable Instructions
Classification Instruction Mnemonic
BCD Binary
Timer/counter HUNDRED-MS TIMER TIM TIMX(550)
instructions TEN-MS TIMER TIMH(015) TIMHX(551)
ONE-MS TIMER TMHH(540) TMHHX(552)
TENTH-MS TIMER (See note.) TIMU(541) TIMUX(556)
HUNDREDTH-MS TIMER (See note.) TMUH(544) TMUHX(557)
ACCUMULATIVE TIMER TTIM(087) TTIMX(555)
LONG TIMER TIML(542) TIMLX(553)
MULTI-OUTPUT TIMER MTIM(543) MTIMX(554)
COUNTER CNT CNTX(546)
REVERSIBLE COUNTER CNTR(012) CNTRX(548)
RESET TIMER/COUNTER CNR(545) CNRX(547)
Block HUNDRED-MS TIMER WAIT TIMW(813) TIMWX(816)
programming TEN-MS TIMER WAIT TMHW(815) TMHWX(817)
instructions
COUNTER WAIT CNTW(814) CNTWX(818)

Note TIMU(541), TIMUX(556), TMUH(544), and TMUHX(557) are supported by

CJ1-H-R CPU Units only.

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Basic Timer Specifications

The following table shows the basic specifications of the timers.
Item TIM/ TIMH(015)/ TMHH(540)/ TIMU(541)/ TMUH(544)/ TTIM(087)/ TIML(542)/ MTIM(543)/
TIMX(550) TIMHX(551) TMHHX(552) TIMUX(556) TMUHX(557) TTIMX(555) TIMLX(553) MTIMX(554)
(See note 3.) (See note 3.)
Timing method Decrement- Decrementing Decrementing Decrementing Decrementing Incrementing Decrementing Incrementing
ing
Timing units 100 ms 10 ms 1 ms 0.1 ms 0.01 ms 100 ms 100 ms 100 ms
Maximum SV TIM: 999.9 s TIMH: 99.99 s TMHH: TIMU: TMUH: TTIM: 999.9 s TIML: MTIM: 999.9 s
TIMX: TIMHX: 9.999 s 0.9999 s 0.09999 s TTIMX: 115 days MTIMX:
6,553.5 s 655.35 s TMHHX: TIMUX: TMUHX: 6,553.5 s TIMLX: 6,553.5 s
65.535 s 6.5535 s 0.65535 s 49,710 days
Outputs/instruc- 1 1 1 1 1 1 1 8
tion
Timer numbers Used Used Used Used Used Used Not used Not used
Completion Flag At execution At execution At execution At execution At execution At execution At execution At execution
refreshing
Timer PV See note 1. See note 2. Every 1 ms At execution At execution At execution At execution At execution
refreshing At execution
(See note 5.)
Value Com- OFF OFF OFF OFF OFF OFF OFF OFF
after pletion
reset Flags
PVs SV SV SV --- (See note 4.) 0 SV 0

Note 1. TIM PVs are refreshed at execution, at the end of program execution each
cycle, or every 80 ms by interrupt if the cycle time exceeds 80 ms.
2. TIMH(015)/TIMHX(551) PVs are refreshed at execution, at the end of pro-
gram execution each cycle, and every 10 ms by interrupt.
3. TIMU(541), TIMUX(556), TMUH(544), and TMUHX(557) are supported by
CJ1-H-R CPU Units only.
4. It is not possible to read the timer PVs of TIMU(541), TIMUX(556),
TMUH(544), and TMUHX(557).
5. Timers are refreshed at different times depending on the timer number.
Refer to the descriptions of individual timer instructions for details.

Timer Operation
The following table shows the effects of operating and programming condi-
tions on the operation of the timers.
Item TIM/ TIMH(015)/ TMHH(540)/ TIMU(541)/ TMUH(544)/ TTIM(087)/ TIML(542)/ MTIM(543)/
TIMX(550) TIMHX(551) TMHHX(552) TIMUX(556) TMUHX(557) TTIMX(555) TIMLX(553) MTIMX(554)
Operating mode PV = 0 --- ---
change Completion Flag = OFF
Power interrupt/reset PV = 0 --- ---
Completion Flag = OFF
Execution of Binary: PV = FFFF, Completion Flag = OFF Not applica- Not applica-
CNR(545)/CNRX(547) BCD: PV = FFFF or 9999, Completion Flag = OFF ble ble
Operation in jumped Operating timers continue timing. Timer status is maintained.
program section
(JMP(004)-JME(005))
Operation in inter- PV = SV Timer status PV = SV Timer sta-
locked program sec- Completion Flag = OFF maintained. Completion tus main-
tion (IL(002)-ILC(003)) Flag = OFF tained.
Forced Comple- ON --- ---
set tion Flag
PVs Set to 0. --- (See note 2.) Set to 0. --- ---
Forced Comple- OFF --- ---
reset tion Flags
PVs Reset to SV. --- (See note 2.) Set to 0. --- ---

Note 1. TIMU(541), TIMUX(556), TMUH(544), and TMUHX(557) are supported by

CJ1-H-R CPU Units only.

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2. It is not possible to read the timer PVs of TIMU(541), TIMUX(556),

TMUH(544), and TMUHX(557).

3-6-1 HUNDRED-MS TIMER: TIM/TIMX(550)

Purpose TIM or TIMX(550) operates a decrementing timer with units of 0.1-s. The set-
ting range for the set value (SV) is 0 to 999.9 s for TIM and 0 to 6,553.5 s for
TIMX(550). The timer accuracy is 0 to 0.01 s.
Note The timer accuracy for CS1D CPU Units is 10 ms + the cycle time. The timer
accuracy for unit version 4.1 of the CJ1-H-R CPU Units is −0.1 to 0 s. The
timer accuracy for other unit versions of the CJ1-H-R CPU Units is 0 to 0.01 s.

Ladder Symbol
PV Symbol Operands
refresh
method
BCD N: 0000 to 4095 (decimal)
TIM S: #0000 to #9999 (BCD)
N N: Timer number

S S: Set value
Binary N: 00000 to 4095 (decimal)
TIMX(550) S: &0 to &65535 (decimal)
#0000 to #FFFF (hex)
N N: Timer number
S S: Set value

Variations
Variations Executed Each Cycle for ON Condition TIM/TIMX(550)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK Not allowed

Operands N: Timer Number

The timer number must be between 0000 and 4095 (decimal).
S: Set Value
The set value must be between #0000 and 9999 (BCD).
(If the set value is set to #0000, the Completion Flag will be turned ON when
TIM/TIMX(550) is executed.)
Operand Specifications
Area N S
CIO Area --- CIO 0000 to CIO 6143
Work Area --- W000 to W511
Holding Bit Area --- H000 to H511
Auxiliary Bit Area --- A000 to A959
Timer Area 0000 to 4095 (decimal) T0000 to T4095
Counter Area --- C0000 to C4095
DM Area --- D00000 to D32767

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Timer and Counter Instructions Section 3-6

Area N S
EM Area without bank --- E00000 to E32767
EM Area with bank --- En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM --- @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)
Indirect DM/EM --- *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_032767
(n = 0 to C)
Constants --- BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers --- DR0 to DR15
Index Registers --- ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15

Description When the timer input is OFF, the timer specified by N is reset, i.e., the timer’s
PV is reset to the SV and its Completion Flag is turned OFF.
When the timer input goes from OFF to ON, TIM/TIMX(550) starts decrement-
ing the PV. The PV will continue timing down as long as the timer input
remains ON and the timer’s Completion Flag will be turned ON when the PV
reaches 0000.
The status of the timer’s PV and Completion Flag will be maintained after the
timer times out. To restart the timer, the timer input must be turned OFF and
then ON again or the timer’s PV must be changed to a non-zero value (by
MOV(021), for example).

Timer input

Timer PV SV

Completion
Flag

The following timing chart shows the behavior of the timer’s PV and Comple-
tion Flag when the timer input is turned OFF before the timer times out.
Timer input

Timer PV SV

Completion
Flag

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Timer and Counter Instructions Section 3-6

Flags
Name Label Operation
Error Flag ER ON if N is indirectly addressed through an Index Register
but the address in the Index Register is not the address of
a timer Completion Flag or timer PV.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.
Equals Flag = OFF or unchanged (See note.)
Negative Flag N OFF or unchanged (See note.)

Note In CS1 and CJ1 CPU Units, these are turned OFF.
In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, these Flags are left
unchanged.

Precautions Timer numbers are shared with other timer instructions. If two timers share
the same timer number, but are not used simultaneously, a duplication error
will be generated when the program is checked, but the timers will operate
normally. Timers which share the same timer number will not operate properly
if they are used simultaneously.
Timers created with timer numbers 2048 to 4095 will not operate properly
when the CPU Unit cycle time exceeds 80 ms. Use timer numbers 0000 to
2047 when the cycle time is longer than 80 ms.
The present value of timers programmed with timer numbers 0000 to 2047 will
be updated even when the timer is on standby. The present value of timers
programmed with timer numbers 2048 to 4095 will be held when the timer is
on standby.
Timers will be reset or paused in the following cases. (When a timer is reset,
its PV is reset to the SV and its Completion Flag is turned OFF.)
Condition PV Completion Flag
Operating mode changed from RUN or 0000 OFF
MONITOR mode to PROGRAM mode
or vice versa.1
Power supply interrupted and reset2 0000 OFF
Execution of CNR(545)/CNRX(547), BCD: 9999 OFF
the RESET TIMER/COUNTER Binary: FFFF
instructions3
Operation in interlocked program sec- Reset to SV. OFF
tion
(IL(002)–ILC(003))
Operation in jumped program section PV continues decre- Retains previous sta-
(JMP(004)–JME(005)) menting. tus.

Note 1. If the IOM Hold Bit (A50012) has been turned ON, the status of timer Com-
pletion Flags and PVs will be maintained when the operating mode is
changed.
2. If the IOM Hold Bit (A50012) has been turned ON and the status of the IOM
Hold Bit itself is protected in the PLC Setup, the status of timer Completion
Flags and PVs will be maintained even when the power is interrupted.
3. The PV will be set to the SV when TIM/TIMX(550) is executed.
When TIM/TIMX(550) is in a program section between IL(002) and ILC(003)
and the program section is interlocked, the PV will be reset to the SV and the
Completion Flag will be turned OFF.
When an operating TIM/TIMX(550) timer created with a timer number
between 0000 and 2047 is in a jumped program section (JMP(004),
CJMP(510), CJPN(511), JME(005)), the timer’s PV will continue timing. (See

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Timer and Counter Instructions Section 3-6

note.) The jumped TIM/TIMX(550) instruction will not be executed, but the PV
will be refreshed each cycle after all tasks have been executed.
Note With the CS1D CPU Units, the PV will not be refreshed in the above case.
When a TIM/TIMX(550) timer is forced set, its Completion Flag will be turned
ON and its PV will be set to 0000. When a TIM/TIMX(550) timer is forced
reset, its Completion Flag will be turned OFF and its PV will be reset to the
SV.
The operation of the = Flag and N Flag depends on the model of the CPU
Unit. Refer to Flags, above, for details.
The timer’s Completion Flag is refreshed only when TIM/TIMX(550) is exe-
cuted, so a delay of up to one cycle may be required for the Completion Flag
to be turned ON after the timer times out.
If online editing is used to overwrite a timer instruction, always reset the Com-
pletion Flag. The timer will not operate properly unless the Completion Flag is
reset.
A TIM/TIMX(550) instruction’s PV and Completion Flag can be refreshed in
the following ways depending on the timer number that is used.
Timers Created with Timer Numbers 0000 to 2047
Execution of TIM/ The PV is updated every time that TIM/TIMX(550) is exe-
TIMX(550) cuted.
The Completion Flag is turned ON if the PV is 0000.
The Completion Flag is turned OFF if the PV is not 0000.
After executing all tasks The PV is also updated every cycle at the end of pro-
gram execution.
80-ms interval refreshing If the cycle time exceeds 80 ms, the timer’s PV is
updated every 80 ms.

Timers Created with Timer Numbers 2048 to 4095

Execution of TIM The PV is updated every time that TIM is executed.
The Completion Flag is turned ON if the PV is 0000.
The Completion Flag is turned OFF if the PV is not 0000.

Timers are reset (PV = SV, Completion Flag OFF) by power interruptions
unless the IOM Hold Bit (A50012) is ON and the bit is protected in the PLC
Setup. It is also possible use a clock pulse bit and a counter instruction to pro-
gram a timer that will retain its PV in the event of a power interruption, as
shown in the following diagram.
Execution 1-s clock
condition pulse bit
Count input

Reset input

Example When timer input CIO 000000 goes from OFF to ON in the following example,
the timer PV will begin counting down from the SV. Timer Completion Flag
T0000 will be turned ON when the PV reaches 0000.
When CIO 000000 goes OFF, the timer PV will be reset to the SV and the
Completion Flag will be turned OFF.

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Timer and Counter Instructions Section 3-6

or

Timer input
&0100
CIO 000000

Timer PV
T0000

Timer
Completion
Flag
T0000

3-6-2 TEN-MS TIMER: TIMH(015)/TIMHX(551)

Purpose TIMH(015)/TIMHX(551) operates a decrementing timer with units of 10-ms.
The setting range for the set value (SV) is 0 to 99.99 s for TIMH(015) and 0 to
655.35 s for TIMHX(551). The timer accuracy is 0 to 0.01 s.
Note The timer accuracy for CS1D CPU Units is 10 ms + the cycle time

Ladder Symbol
PV Symbol Operands
refresh
method
BCD N: 0000 to 4095 (decimal)
TIMH(015) S: #0000 to #9999 (BCD)

N N: Timer number

S S: Set value

Binary N: 00000 to 4095 (decimal)

TIMHX(551) S: &0 to &65535 (decimal)
#0000 to #FFFF (hex)
N N: Timer number

S S: Set value

Variations
Variations Executed Each Cycle for ON Condition TIMH(015)/
TIMHX(551)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK Not allowed

Operands N: Timer Number

The timer number must be between 0000 and 4095 (decimal).
S: Set Value
The set value must be between #0000 and 9999 in BCD mode.

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Timer and Counter Instructions Section 3-6

Operand Specifications
Area N S
CIO Area --- CIO 0000 to CIO 6143
Work Area --- W000 to W511
Holding Bit Area --- H000 to H511
Auxiliary Bit Area --- A000 to A959
Timer Area 0000 to 4095 (decimal) T0000 to T4095
Counter Area --- C0000 to C4095
DM Area --- D00000 to D32767
EM Area without bank --- E00000 to E32767
EM Area with bank --- En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM --- @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)
Indirect DM/EM --- *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers --- DR0 to DR15
Index Registers --- ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15

Description When the timer input is OFF, the timer specified by N is reset, i.e., the timer’s
PV is reset to the SV and its Completion Flag is turned OFF.
When the timer input goes from OFF to ON, TIMH(015)/TIMHX(551) starts
decrementing the PV. The PV will continue timing down as long as the timer
input remains ON and the timer’s Completion Flag will be turned ON when the
PV reaches 0000.
The status of the timer’s PV and Completion Flag will be maintained after the
timer times out. To restart the timer, the timer input must be turned OFF and
then ON again or the timer’s PV must be changed to a non-zero value (by
MOV(021), for example).

Timer input

Timer PV SV

Completion
Flag

The following timing chart shows the behavior of the timer’s PV and Comple-
tion Flag when the timer input is turned OFF before the timer times out.

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Timer and Counter Instructions Section 3-6

Timer input

Timer PV SV

Completion
Flag
Flags
Name Label Operation
Error Flag ER ON if N is indirectly addressed through an Index Register
but the address in the Index Register is not the address of
a timer Completion Flag or timer PV.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.
Equals Flag = Unchanged (See note.)
Negative Flag N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these are turned OFF.

Precautions Timer numbers are shared with other timer instructions. If two timers share
the same timer number, but are not used simultaneously, a duplication error
will be generated when the program is checked, but the timers will operate
normally. Timers which share the same timer number will not operate properly
if they are used simultaneously.
Timers created with timer numbers 2048 to 4095 will not operate properly
when the CPU Unit cycle time exceeds 80 ms. Use timer numbers 0000 to
2047 when the cycle time is longer than 80 ms.
TIMH(015)/TIMHX(551) timers created with timer numbers 0000 to 0255 are
refreshed every 10 ms. Use these timer numbers when the PV is being refer-
enced in the user program.
The present value of timers programmed with timer numbers 0000 to 2047 will
be updated even when the timer is on standby. The present value of timers
programmed with timer numbers 2048 to 4095 will be held when the timer is
on standby.
The operation of the = Flag and N Flag depends on the model of the CPU
Unit. Refer to Flags, above, for details.
The Completion Flags for TIMH(015)/TIMHX(551) timers will be updated
when the instruction is executed. (This operation differs from that for CV-
series and CVM1 PLCs.)
Timers will be reset or paused in the following cases. (When a timer is reset,
its PV is reset to the SV and its Completion Flag is turned OFF.)
Condition PV Completion Flag
Operating mode changed from RUN or 0000 OFF
MONITOR mode to PROGRAM mode or
vice versa.1
Power supply interrupted and reset2 0000 OFF
Execution of CNR(545)/CNRX(547), the BCD: 9999 OFF
RESET TIMER/COUNTER instructions3 Binary: FFFF
Operation in interlocked program section Reset to SV. OFF
(IL(002)–ILC(003))
Operation in jumped program section PV continues Retains previous status.
(JMP(004)–JME(005)) decrementing.

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Timer and Counter Instructions Section 3-6

Note 1. If the IOM Hold Bit (A50012) has been turned ON, the status of timer Com-
pletion Flags and PVs will be maintained when the operating mode is
changed.
2. If the IOM Hold Bit (A50012) has been turned ON and the status of the IOM
Hold Bit itself is protected in the PLC Setup, the status of timer Completion
Flags and PVs will be maintained even when the power is interrupted.
3. The PV will be set to the SV when TIMH(015)/TIMHX(551) is executed.
When an operating TIMH(015)/TIMHX(551) timer created with a timer number
between 0000 and 2047 is in a jumped program section (JMP(004),
CJMP(510), CJPN(511), JME(005)), the timer’s PV will continue timing. (See
note.) (The jumped TIMH(015)/TIMHX(551) instruction will not be executed,
but the PV will be refreshed every 10 ms and each cycle after all tasks have
been executed.)
Note With the CS1D CPU Units, the PV will not be refreshed in the above case.
When TIMH(015)/TIMHX(551) is in a program section between IL(002) and
ILC(003) and the program section is interlocked, the PV will be reset to the SV
and the Completion Flag will be turned OFF.
When a TIMH(015)/TIMHX(551) timer is forced set, its Completion Flag will
be turned ON and its PV will be set to 0000. When a TIMH(015)/TIMHX(551)
timer is forced reset, its Completion Flag will be turned OFF and its PV will be
reset to the SV.
The operation of the = Flag and N Flag depends or the model of CPU Unit.
Refer to Flags for details.
The timer’s Completion Flag is refreshed only when TIMH(015)/TIMHX(551)
is executed, so a delay of up to one cycle may be required for the Completion
Flag to be turned ON after the timer times out.
If online editing is used to overwrite a timer instruction, always reset the Com-
pletion Flag. The timer will not operate properly unless the Completion Flag is
reset.
A TIMH(015)/TIMHX(551) instruction’s PV and Completion Flag can be
refreshed in the following ways depending on the timer number that is used.
Timers Created with Timer Numbers 0000 to 0255
Execution of The Completion Flag is turned ON if the PV is 0000.
TIMH(015)/ The Completion Flag is turned OFF if the PV is not 0000.
TIMHX(551)
10-ms interval The timer’s PV is updated every 10 ms.
refreshing

Timers Created with Timer Numbers 0256 to 2047

Execution of The PV is updated every time that TIMH(015)/TIMHX(551) is
TIMH(015)/ executed.
TIMHX(551) The Completion Flag is turned ON if the PV is 0000.
The Completion Flag is turned OFF if the PV is not 0000.
After executing all The PV is also updated every cycle at the end of program execu-
tasks tion.
80-ms interval If the cycle time exceeds 80 ms, the timer’s PV is updated every
refreshing 80 ms.

Timers Created with Timer Numbers 2048 to 4095

Execution of The PV is updated every time that TIMH(015) is executed.
TIMH(015)/ The Completion Flag is turned ON if the PV is 0000.
TIMHX(551) The Completion Flag is turned OFF if the PV is not 0000.

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Timer and Counter Instructions Section 3-6

Example When timer input CIO 000000 goes from OFF to ON in the following example,
the timer PV will begin counting down from the SV (#0064 = 100 = 1.00 s).
The Timer Completion Flag, T0000, will be turned ON when the PV reaches
0000.
When CIO 000000 goes OFF, the timer PV will be reset to the SV and the
Completion Flag will be turned OFF.
Timer input
CIO 000000

Timer PV
T0000 #0100
(1.00 s)
or Timer Completion
Flag
TIMHX T0000

&0100

3-6-3 ONE-MS TIMER: TMHH(540)/TMHHX(552)

Purpose TMHH(540)/TMHHX(552) operates a decrementing timer with units of 1-ms.
The setting range for the set value (SV) is 0 to 9.999 s for TMHH(540) and 0
to 65.535 for TMHHX(552). The timer accuracy is –0.001 to 0 s.
Note The timer accuracy for CS1D CPU Units is 10 ms + the cycle time. The timer
accuracy for unit version 4.1 of the CJ1-H-R CPU Units is −0.01 to 0 s. The
timer accuracy for other unit versions of the CJ1-H-R CPU Units is −0.001 to
0 s.
Ladder Symbol
PV Symbol Operands
refresh
method
BCD N: 0 to 15 decimal, or
TMHH(540) 0 to 4,095 decimal
(See note.)
N N: Timer number S: #0000 to #9999 (BCD)
S S: Set value

Binary N: 0 to 15 decimal, or
TMHHX(552) 0 to 4,095 decimal
(See note.)
N N: Timer number S: &0 to &65535 decimal
#0000 to #FFFF hex
S S: Set value

Note In CJ1-H-R CPU Units other than those with unit version 4.1, N can be set to
between 0 and 4,095 decimal. In CJ1-H-R CPU Units with unit version 4.1, N
can be set only to between 16 and 4095 decimal. For details, refer to Refresh-
ing of TMHH(540) and TMHHX(552) PVs and Completion Flags on page 256.
Variations
Variations Executed Each Cycle for ON Condition TMHH(540)/
TMHHX(552)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

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Timer and Counter Instructions Section 3-6

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK in CJ1-H-R CPU OK OK Not allowed
Units only

Operands N: Timer Number

The timer number must be between 0000 and 0015 (decimal).
S: Set Value
The set value must be between #0000 and 9999 (BCD).
Operand Specifications
Area N S
CIO Area --- CIO 0000 to CIO 6143
Work Area --- W000 to W511
Holding Bit Area --- H000 to H511
Auxiliary Bit Area --- A000 to A959
Timer Area 0000 to 0015 decimal, or T0000 to T4095
0000 to 4095 (See note.)
Counter Area --- C0000 to C4095
DM Area --- D00000 to D32767
EM Area without bank --- E00000 to E32767
EM Area with bank --- En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM --- @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)
Indirect DM/EM --- *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers --- DR0 to DR15
Index Registers --- ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15

Note In CJ1-H-R CPU Units other than those with unit version 4.1, N can be set to
between 0 and 4,095 decimal. In CJ1-H-R CPU Units with unit version 4.1, N
can be set only to between 16 and 4095 decimal. For details, refer to Refresh-
ing of TMHH(540) and TMHHX(552) PVs and Completion Flags on page 256.

Description When the timer input is OFF, the timer specified by N is reset, i.e., the timer’s
PV is reset to the SV and its Completion Flag is turned OFF.
When the timer input goes from OFF to ON, TMHH(540)/TMHHX(552) starts
decrementing the PV. The PV will continue timing down as long as the timer

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Timer and Counter Instructions Section 3-6

input remains ON and the timer’s Completion Flag will be turned ON when the
PV reaches 0000.
The status of the timer’s PV and Completion Flag will be maintained after the
timer times out. To restart the timer, the timer input must be turned OFF and
then ON again or the timer’s PV must be changed to a non-zero value (by
MOV(021), for example).
Flags
Name Label Operation
Error Flag ER ON if N is indirectly addressed through an Index Register
but the address in the Index Register is not the address of
a timer Completion Flag or timer PV.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.
Equals Flag = Unchanged (See note.)
Negative Flag N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these are turned OFF.

Precautions Timer numbers are shared with other timer instructions. If two timers share
the same timer number, but are not used simultaneously, a duplication error
will be generated when the program is checked, but the timers will operate
normally. Timers which share the same timer number will not operate properly
if they are used simultaneously.
The Completion Flag is updated only when TMHH(540)/TMHHX(552) is exe-
cuted. The Completion Flag can thus be delayed by up to one cycle time from
the actual set value.
The present value of a high-speed timer with a timer number from 0 to 15 will
be refreshed even if the task is on standby. The present value of a high-speed
timer with a timer number from 16 to 4095 will be held if the task is on standby.
Timers will be reset or paused in the following cases. (When a timer is reset,
its PV is reset to the SV and its Completion Flag is turned OFF.)
Condition PV Completion Flag
Operating mode changed from RUN or 0000 OFF
MONITOR mode to PROGRAM mode or
vice versa.1
Power supply interrupted and reset2 0000 OFF
Execution of CNR(545)/CNRX(547), the BCD: 9999 OFF
RESET TIMER/COUNTER instructions3 Binary: FFFF
Operation in interlocked program section Reset to SV. OFF
(IL(002)–ILC(003))
Operation in jumped program section PV continues Retains previous status.
(JMP(004)–JME(005)) decrement-
ing.

Note 1. If the IOM Hold Bit (A50012) has been turned ON, the status of timer Com-
pletion Flags and PVs will be maintained when the operating mode is
changed.
2. If the IOM Hold Bit (A50012) has been turned ON and the status of the IOM
Hold Bit itself is protected in the PLC Setup, the status of timer Completion
Flags and PVs will be maintained even when the power is interrupted.
3. The PV will be set to the SV when TMHH(540)/TMHHX(552) is executed.

255
Timer and Counter Instructions Section 3-6

For all CPU Units except CS1D CPU Units, the present value of all operating
timers with timer numbers 0 to 15 will be refreshed even if the timer is in a pro-
gram section that is jumped using JMP(004), CJMP(510), CJPN(511),
JME(005). (The jumped timer instruction will not be executed, but the PV will
be refreshed every 1 ms.) The present values will not be updated with a CS1D
CPU Unit.
When TMHH(540)/TMHHX(552) is in a program section between IL(002) and
ILC(003) and the program section is interlocked, the PV will be reset to the SV
and the Completion Flag will be turned OFF.
When a TMHH(540)/TMHHX(552) timer is forced set, its Completion Flag will
be turned ON and its PV will be set to 0000. When a TMHH(540)/
TMHHX(552) timer is forced reset, its Completion Flag will be turned OFF and
its PV will be reset to the SV.
The operation of the = Flag and N Flag depends on the model of the CPU
Unit. Refer to Flags, above, for details.
If online editing is used to overwrite a timer instruction, always reset the Com-
pletion Flag. The timer will not operate properly unless the Completion Flag is
reset.

Refreshing of TMHH(540) A TMHH(540)/TMHHX(552) instruction’s PV and Completion Flag are

and TMHHX(552) PVs and refreshed as shown in the following tables.
Completion Flags Timer numbers 0 to 15 (Cannot be used with unit version 4.1 of the CJ1-H-R
CPU Units, but can be used with other unit versions of the CJ1-H-R CPU
Units.):
Refresh timing Data refreshed
Execution of The Completion Flag is turned ON if the PV is 0000.
TMHH(540)/ The Completion Flag is turned OFF if the PV is not 0000.
TMHHX(552)
1-ms interval refreshing The timer’s PV is refreshed every 1 ms.

Timer numbers 16 to 4,095 (CJ1-H-R CPU Units only):

Refresh timing Data refreshed
Execution of The Completion Flag is turned ON if the PV is 0000.
TMHH(540)/ The Completion Flag is turned OFF if the PV is not 0000.
TMHHX(552)

3-6-4 TENTH-MS TIMER: TIMU(541)/TIMUX(556)

Purpose TIMU(541)/TIMUX(556) operates a decrementing timer with units of 0.1-ms.
The setting range for the set value (SV) is 0 to 0.9999 s for TIMU(541) and 0
to 6.5535 s for TIMUX(556). The timer accuracy is –0.1 to 0 ms.
Note These instructions can be used in the CJ1-H-R CPU Units only.

256
Timer and Counter Instructions Section 3-6

Ladder Symbol
PV Symbol Operands
refresh
method
BCD N: 0000 to 4095 (decimal)
TIMU(541) S: #0000 to #9999 (BCD)
N N: Timer number

S S: Set value

Binary N: 0000 to 4095 (decimal)

TIMUX(556) S: &0 to &65535 (decimal)
#0000 to #FFFF (hex)
N N: Timer number

S S: Set value

Variations
Variations Executed Each Cycle for ON Condition TIMU(541)/
TIMUX(556)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Function block Block program Step program Subroutines Interrupt
definitions areas areas tasks
OK Not allowed OK OK Not allowed

Operands N: Timer Number

The timer number must be between 0000 and 4095 (decimal).
S: Set Value
The set value must be between #0000 and 9999 (BCD).
Operand Specifications
Area N S
CIO Area --- CIO 0000 to CIO 6143
Work Area --- W000 to W511
Holding Bit Area --- H000 to H511
Auxiliary Bit Area --- A000 to A959
Timer Area 0000 to 4095 (decimal) T0000 to T4095
Counter Area --- C0000 to C4095
DM Area --- D00000 to D32767
EM Area without bank --- E00000 to E32767
EM Area with bank --- En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM --- @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)

257
Timer and Counter Instructions Section 3-6

Area N S
Indirect DM/EM --- *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers --- DR0 to DR15
Index Registers --- ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15

Description When the timer input is OFF, the timer specified by N is reset, i.e., the timer’s
Completion Flag is turned OFF.
When the timer input goes from OFF to ON, TIMU(541)/TIMUX(556) starts
decrementing the PV. If the set value is reached while the timer input is ON,
the timer’s Completion Flag will be turned ON (the timer times out).
The status of the timer’s Completion Flag will be maintained after the timer
times out. To restart the timer, the timer input must be turned OFF and then
ON again.
Read this timer’s Completion Flag only. The timer’s PV is used by the system,
so it cannot be read.
Flags
Name Label Operation
Error Flag ER ON if timer number N is indirectly addressed through an
Index Register but the address in the Index Register is not
the address of a timer’s Completion Flag or PV.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.
Equals Flag = Unchanged
Negative Flag N Unchanged

Precautions Timer numbers are shared with other timer instructions. If two timers share
the same timer number, but are not used simultaneously, a duplication error
will be generated when the program is checked, but the timers will operate
normally. Timers which share the same timer number will not operate properly
if they are used simultaneously.
The timer PV cannot be read.
The Completion Flag is updated only when TIMU(541)/TIMUX(556) is exe-
cuted. The Completion Flag can thus be delayed by up to one cycle time from
the actual set value.
The timer will not operate properly when the cycle time exceeds 100 ms.
Timers will be reset or paused in the following cases. (When a timer is reset,
its PV is reset to the SV and its Completion Flag is turned OFF.)
Condition Completion Flag
Operating mode changed from RUN or MONITOR mode OFF
to PROGRAM mode or vice versa. (See note 1.)
Power supply interrupted and reset (See note 2.) OFF

258
Timer and Counter Instructions Section 3-6

Condition Completion Flag

Execution of CNR(545)/CNRX(547), the RESET TIMER/ OFF
COUNTER instructions
Operation in interlocked program section OFF
(IL(002)–ILC(003))
Operation in jumped program section Retains previous status.
(JMP(004)–JME(005))

Note 1. If the IOM Hold Bit (A50012) has been turned ON, the status of timer Com-
pletion Flags and PVs will be maintained when the operating mode is
changed.
2. If the IOM Hold Bit (A50012) has been turned ON and the status of the IOM
Hold Bit itself is protected in the PLC Setup, the status of timer Completion
Flags and PVs will be maintained even when the power is interrupted.
Note When TIMU(541)/TIMUX(556) is in a program section between IL(002) and
ILC(003) and the program section is interlocked, the PV will be reset to the SV
and the Completion Flag will be turned OFF.
TIMU(541)/TIMUX(556) timers may not time accurately when used in a pro-
gram section jumped by the JMP(004), CJMP(510), CJPN(511), and
JME(005) instructions.
When a TIMU(541)/TIMUX(556) timer is forced set, its Completion Flag will
be turned ON. When a TIMU(541)/TIMUX(556) timer is forced reset, its Com-
pletion Flag will be turned OFF.
If online editing is used to overwrite a timer instruction, always reset the Com-
pletion Flag. The timer will not operate properly unless the Completion Flag is
reset.
A TIMU(541)/TIMUX(556) instruction’s Completion Flag is refreshed as
shown in the following table.
Execution of TIMU(541)/ The Completion Flag is turned ON if the SV is reached.
TIMUX(556) The Completion Flag is turned OFF if the SV has not been
reached.

Operation Example

TIMU

#0123
or

TIMUX

&0123

When timer input CIO 000000 goes from OFF to ON in this example, the timer
PV will begin counting down. The Timer Completion Flag, T0000, will be
turned ON after 12.3 ms.
When CIO 000000 goes OFF, the Timer Completion Flag, T0000, will be
turned OFF.

3-6-5 HUNDREDTH-MS TIMER: TMUH(544)/TMUHX(557)

Purpose TMUH(544)/TMUHX(557) operates a decrementing timer with units of 0.01-
ms. The setting range for the set value (SV) is 0 to 0.09999 s for TMUH(544)
and 0 to 0.65535 s for TMUHX(557). The timer accuracy is –0.01 to 0 ms.
Note These instructions can be used in the CJ1-H-R CPU Units only.

259
Timer and Counter Instructions Section 3-6

Ladder Symbol
PV Symbol Operands
refresh
method
BCD N: 0000 to 4095 (decimal)
TMUH(541) S: #0000 to #9999 (BCD)
N N: Timer number

S S: Set value

Binary N: 0000 to 4095 (decimal)

TMUHX(557) S: &0 to &65535 (decimal)
#0000 to #FFFF (hex)
N N: Timer number

S S: Set value

Variations
Variations Executed Each Cycle for ON Condition TMUH(544)/
TMUHX(557)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Function block Block program Step program Subroutines Interrupt
definitions areas areas tasks
OK Not allowed OK OK Not allowed

Operands N: Timer Number

The timer number must be between 0000 and 4095 (decimal).
S: Set Value
The set value must be between #0000 and 9999 (BCD).
Operand Specifications
Area N S
CIO Area --- CIO 0000 to CIO 6143
Work Area --- W000 to W511
Holding Bit Area --- H000 to H511
Auxiliary Bit Area --- A000 to A959
Timer Area 0000 to 4095 (decimal) T0000 to T4095
Counter Area --- C0000 to C4095
DM Area --- D00000 to D32767
EM Area without bank --- E00000 to E32767
EM Area with bank --- En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM --- @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)

260
Timer and Counter Instructions Section 3-6

Area N S
Indirect DM/EM --- *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers --- DR0 to DR15
Index Registers --- ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15

Description When the timer input is OFF, the timer specified by N is reset, i.e., the timer’s
Completion Flag is turned OFF.
When the timer input goes from OFF to ON, TMUH(544)/TMUHX(557) starts
decrementing the PV. If the set value is reached while the timer input is ON,
the timer’s Completion Flag will be turned ON (the timer times out).
The status of the timer’s Completion Flag will be maintained after the timer
times out. To restart the timer, the timer input must be turned OFF and then
ON again.
Read this timer’s Completion Flag only. The timer’s PV is used by the system,
so it cannot be read.
Flags
Name Label Operation
Error Flag ER ON if timer number N is indirectly addressed through an
Index Register but the address in the Index Register is not
the address of a timer’s Completion Flag or PV.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.
Equals Flag = Unchanged
Negative Flag N Unchanged

Precautions Timer numbers are shared with other timer instructions. If two timers share
the same timer number, but are not used simultaneously, a duplication error
will be generated when the program is checked, but the timers will operate
normally. Timers which share the same timer number will not operate properly
if they are used simultaneously.
The timer PV cannot be read.
The Completion Flag is updated only when TIMU(541)/TIMUX(556) is exe-
cuted. The Completion Flag can thus be delayed by up to one cycle time from
the actual set value.
The timer will not operate properly when the cycle time exceeds 100 ms.
Timers will be reset or paused in the following cases. (When a timer is reset,
its PV is reset to the SV and its Completion Flag is turned OFF.)
Condition Completion Flag
Operating mode changed from RUN or MONITOR mode OFF
to PROGRAM mode or vice versa. (See note 1.)
Power supply interrupted and reset (See note 2.) OFF

261
Timer and Counter Instructions Section 3-6

Condition Completion Flag

Execution of CNR(545)/CNRX(547), the RESET TIMER/ OFF
COUNTER instructions
Operation in interlocked program section OFF
(IL(002)–ILC(003))
Operation in jumped program section Retains previous status.
(JMP(004)–JME(005))

Note 1. If the IOM Hold Bit (A50012) has been turned ON, the status of timer Com-
pletion Flags and PVs will be maintained when the operating mode is
changed.
2. If the IOM Hold Bit (A50012) has been turned ON and the status of the IOM
Hold Bit itself is protected in the PLC Setup, the status of timer Completion
Flags and PVs will be maintained even when the power is interrupted.
Note When TIMU(541)/TIMUX(556) is in a program section between IL(002) and
ILC(003) and the program section is interlocked, the PV will be reset to the SV
and the Completion Flag will be turned OFF.
TIMUH(544)/TIMUHX(557) timers may not time accurately when used in a
program section jumped by the JMP(004), CJMP(510), CJPN(511), and
JME(005) instructions.
When a TIMU(541)/TIMUX(556) timer is forced set, its Completion Flag will
be turned ON. When a TIMU(541)/TIMUX(556) timer is forced reset, its Com-
pletion Flag will be turned OFF.
If online editing is used to overwrite a timer instruction, always reset the Com-
pletion Flag. The timer will not operate properly unless the Completion Flag is
reset.
A TIMU(541)/TIMUX(556) instruction’s Completion Flag is refreshed as
shown in the following table.
Execution of TMUH(544) The Completion Flag is turned ON if the SV is reached.
/TMUHX(557) The Completion Flag is turned OFF if the SV has not been
reached.

Operation Example

TMUH

#0123
or

TMUHX

&0123

When timer input CIO 000000 goes from OFF to ON in this example, the timer
PV will begin counting down. The Timer Completion Flag, T0000, will be
turned ON after 1.23 ms.
When CIO 000000 goes OFF, the Timer Completion Flag, T0000, will be
turned OFF.

3-6-6 ACCUMULATIVE TIMER: TTIM(087)/TTIMX(555)

Purpose TTIM(087)/TTIMX(555) operates an incrementing timer with units of 0.1-s.
The setting range for the set value (SV) is 0 to 999.9 s for TTIM(087) and 0 to
6,553.5 s for TTIMX(555). The timer accuracy is –0.01 to 0 s.
Note The timer accuracy for CS1D CPU Units is 10 ms + the cycle time

262
Timer and Counter Instructions Section 3-6

Ladder Symbol
PV Symbol Operands
refresh
method
BCD N: 0000 to 15
Timer input TTIM(087) (decimal)
S: #0000 to #9999
N N: Timer number (BCD)

S S: Set value
Reset input
Binary N: 00000 to 15
Timer input TTIMX(555) (decimal)
S: &0 to &65535
N N: Timer number (decimal)
#0000 to #FFFF
S S: Set value (hex)
Reset input

Variations
Variations Executed Each Cycle for ON Condition TTIM(087)/
TTIMX(555)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK Not allowed
Operands N: Timer Number
The timer number must be between 0000 to 4095 (decimal).
S: Set Value
The set value must be between #0000 and 9999 (BCD).
Operand Specifications
Area N S
CIO Area --- CIO 0000 to CIO 6143
Work Area --- W000 to W511
Holding Bit Area --- H000 to H511
Auxiliary Bit Area --- A000 to A959
Timer Area 0000 to 4095 (decimal) T0000 to T4095
Counter Area --- C0000 to C4095
DM Area --- D00000 to D32767
EM Area without bank --- E00000 to E32767
EM Area with bank --- En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM --- @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)

263
Timer and Counter Instructions Section 3-6

Area N S
Indirect DM/EM --- *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers --- DR0 to DR15
Index Registers --- ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15

Description When the timer input is ON, TTIM(087)/TTIMX(555) increments the PV. When
the timer input goes OFF, the timer will stop incrementing the PV, but the PV
will retain its value. The PV will resume timing when the timer input goes ON
again. The timer’s Completion Flag will be turned ON when the PV reaches
the SV.
The status of the timer’s PV and Completion Flag will be maintained after the
timer times out. There are three ways to restart the timer: the timer’s PV can
be changed to a non-zero value (by MOV(021), for example), the reset input
can be turned ON, or CNR(545)/CNRX(547) can be executed.

Timer input

Timer PV SV

Timing resumes.
PV maintained.

Completion
Flag

Reset input

Flags
Name Label Operation
Error Flag ER ON if N is indirectly addressed through an Index Register
but the address in the Index Register is not the address of
a timer Completion Flag or timer PV.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.

Precautions Timer numbers are shared with other timer instructions. If two timers share
the same timer number, but are not used simultaneously, a duplication error
will be generated when the program is checked, but the timers will operate
normally. Timers which share the same timer number will not operate properly
if they are used simultaneously.

264
Timer and Counter Instructions Section 3-6

Timers will be reset or paused in the following cases. (When a TTIM(087)/

TTIMX(555) timer is reset, its PV is reset to 0000 and its Completion Flag is
turned OFF.)
Condition PV Completion Flag
Operating mode changed from RUN or 0000 OFF
MONITOR mode to PROGRAM mode or
vice versa.1
Power supply interrupted and reset2 0000 OFF
Execution of CNR(545)/CNRX(547), the BCD: 9999 OFF
RESET TIMER/COUNTER instructions3 Binary: FFFF
Operation in interlocked program section Retains previ- Retains previous status.
(IL(002)–ILC(003)) ous status.
Operation in jumped program section Retains previ- Retains previous status.
(JMP(004)–JME(005)) ous status.

Note 1. If the IOM Hold Bit (A50012) has been turned ON, the status of timer Com-
pletion Flags and PVs will be maintained when the operating mode is
changed.
2. If the IOM Hold Bit (A50012) has been turned ON and the status of the IOM
Hold Bit itself is protected in the PLC Setup, the status of timer Completion
Flags and PVs will be maintained even when the power is interrupted.
3. The PV will be set to the SV when TTIM(087)/TTIMX(555) is executed.
When TTIM(087)/TTIMX(555) is in a program section between IL(002) and
ILC(003) and the program section is interlocked, the PV will retain its previous
value (it will not be reset). Be sure to take this fact into account when
TTIM(087)/TTIMX(555) is programmed between IL(002) and ILC(003).
When an operating TTIM(087)/TTIMX(555) timer is in a program section
between JMP(004) and JME(005) and the program section is jumped, the PV
will retain its previous value. Be sure to take this fact into account when
TTIM(087)/TTIMX(555) is programmed between JMP(004) and JME(005).
When a TTIM(087)/TTIMX(555) timer is forced set, its Completion Flag will be
turned ON and its PV will be reset to 0000. When a TTIM(087)/TTIMX(555)
timer is forced reset, its Completion Flag will be turned OFF and its PV will be
reset to 0000. The forced set and forced reset operations take priority over the
status of the timer and reset inputs.
The timer’s PV is refreshed only when TTIM(087)/TTIMX(555) is executed, so
the timer will not operate properly when the cycle time exceeds 100 ms
because the timer increments in 100-ms units.
The timer’s Completion Flag is refreshed only when TTIM(087)/TTIMX(555) is
executed, so a delay of up to one cycle may be required for the Completion
Flag to be turned ON after the timer times out.
Typical timers such as TIM/TIMX(550) are decrementing counters and the PV
shows the time remaining until the timer times out. The PV of TTIM(087)/
TTIMX(555) shows how much time has elapsed, so the PV can be used
unchanged in many calculations and display outputs.
Example When timer input CIO 000000 is ON in the following example, the timer PV
will begin counting up from 0. Timer Completion Flag T0001 will be turned ON
when the PV reaches the SV.
If the reset input is turned ON, the timer PV will be reset to 0000 and the Com-
pletion Flag (T0001) will be turned OFF. (Usually the reset input is turned ON
to reset the timer and then the timer input is turned ON to start timing.)

265
Timer and Counter Instructions Section 3-6

If the timer input is turned OFF before the SV is reached, the timer will stop
timing but the PV will be maintained. The timer will resume from its previous
PV when the timer input is turned ON again.

TTIM TTIMX
000000 0001 000000 0001
or
#0100 &0100

000001 000001

Timer input ON ON
CIO 000000 OFF OFF

Timer PV # #0100 ##0100

T0001
Timing resumes.

PV maintained.
Timer Completion 0 0
Flag ON ON
T0001 OFF OFF

ON ON
Reset input OFF OFF
CIO 000001

3-6-7 LONG TIMER: TIML(542)/TIMLX(553)

Purpose TIML(542)/TIMLX(553) operates a decrementing timer with units of 0.1 s that
can time up to 115 days for TIML(542) and 4,971 days for TIMLX(543). The
timer accuracy is 0 to 0.01 s.
Note The timer accuracy for CS1D CPU Units is 10 ms + the cycle time

Ladder Symbol BCD

TIML(542)

D1 D1: Completion Flag

D2 D2: PV word

S S: SV word

Binary

TIMLX(543)

D1 D1: Completion Flag

D2 D2: PV word

S S: SV word
Variations
Variations Executed Each Cycle for ON Condition TIML(542)/
TIMLX(553)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

266
Timer and Counter Instructions Section 3-6

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK Not allowed

Operands D1: Completion Flag

Bit 0 of D1 acts as the Completion Flag for TIML(542)/TIMLX(553).
15 0
D1

Do not use. Completion Flag

D2: PV Word
D2+1 and D2 contain the 8-digit binary or BCD PV. (D2 and D2+1 must be in
the same data area.) The PV can range from #00000000 to #99999999 for
TIML(542) and &00000000 to &4294967294 (decimal) or #00000000 to
#FFFFFFFF (hexadecimal) for TIMLX(553).
D2 D2+1 D2

S: SV Word
S+1 and S contain the 8-digit binary or BCD SV. (S and S+1 must be in the
same data area.) The SV must be between #00000000 to #99999999 for
TIML(542) and &00000000 to &4294967294 (decimal) or #00000000 to
#FFFFFFFF (hexadecimal) for TIMLX(553).
S S+1 S

Operand Specifications
Area D1 D2 S
CIO Area CIO 0000 to CIO 0000 to CIO 6142
CIO 6143
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A448 to A959 A448 to A958 A000 to A958
Timer Area --- --- T0000 to T4094
Counter Area --- --- C0000 to C4094
DM Area D00000 to D00000 to D32766
D32767
EM Area without bank E00000 to E00000 to E32766
E32767
EM Area with bank En_00000 to En_00000 to En_32766
En_32767 (n = 0 to C)
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)

267
Timer and Counter Instructions Section 3-6

Area D1 D2 S
Constants --- BCD:
#00000000 to
99999999 (BCD)
“&” cannot be
used.
Binary:
&00000000 to
&4294967294
(decimal) or
#00000000 to
#FFFFFFFF (hex)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15

Description TIML(542)/TIMLX(553) is a decrementing ON-delay timer with units of 0.1-s

that uses an 8-digit SV and an 8-digit PV.
When the timer input is OFF, the timer is reset, i.e., the timer’s PV is reset to
the SV and its Completion Flag is turned OFF.
When the timer input goes from OFF to ON, TIML(542)/TIMLX(553) starts
decrementing the PV in D2+1 and D2. The PV will continue timing down as
long as the timer input remains ON and the timer’s Completion Flag will be
turned ON when the PV reaches 0000 0000.
The status of the timer’s PV and Completion Flag will be maintained after the
timer times out. To restart the timer, the timer input must be turned OFF and
then ON again or the timer’s PV must be changed to a non-zero value (by
MOV(021), for example).

Timer input

SV
Timer PV

Completion Flag
(Bit 00 of D1)
Flags
Name Label Operation
Error Flag ER ON if the PV contained in D2+1 and D2 is not BCD.
ON if the SV contained in S+1 and S is not BCD.
OFF in all other cases.

Precautions Unlike most timers, TIML(542)/TIMLX(553) does not use a timer number.
(Timer area PV refreshing is not performed for TIML(542)/TIMLX(553).)
Since the Completion Flag for TIML(542)/TIMLX(553) is in a data area it can
be forced set or forced reset like other bits, but the PV will not change.
The timer’s PV is refreshed only when TIML(542)/TIMLX(553) is executed, so
the timer will not operate properly when the cycle time exceeds 100 ms
because the timer increments in 100-ms units.
The timer’s Completion Flag is refreshed only when TIML(542)/TIMLX(553) is
executed, so a delay of up to one cycle may be required for the Completion
Flag to be turned ON after the timer times out.

268
Timer and Counter Instructions Section 3-6

When TIML(542)/TIMLX(553) is in a program section between IL(002) and

ILC(003) and the program section is interlocked, the PV will be reset to the SV
and the Completion Flag will be turned OFF.
When an operating TIML(542)/TIMLX(553) timer is in a program section
between JMP(004) and JME(005) and the program section is jumped, the PV
will retain its previous value. Be sure to take this fact into account when
TIML(542)/TIMLX(553) is programmed between JMP(004) and JME(005).
Be sure that the words specified for the Completion Flag and PV (D1, D2, and
D2+1) are not used in other instructions. If these words are affected by other
instructions, the timer might not time out properly.

Example When timer input CIO 000000 is ON in the following example, the timer PV (in
D00101 and D00100) will be set to the SV (in D00101 and D00100) and the
PV will begin counting down. The timer Completion Flag (CIO 020000) will be
turned ON when the PV reaches 0000 0000.
When CIO 000000 goes OFF, the timer PV will be reset to the SV and the
Completion Flag will be turned OFF.

Timer input
CIO 000000

Timer PV
(D00101 and D00100)
Timer SV:
(D00201 and D00200)

Timer Completion
Flag
(CIO 020000)

D1: 00200
Timer Completion
Flag
(CIO 020000)

D2: D00100 Timer's PV (LSB)

D00101 Timer's PV (MSB)

S: D00200 C 0 0 Timer SV:

D00201 1 0 (100,000 decimal= 10,000 s)

3-6-8 MULTI-OUTPUT TIMER: MTIM(543)/MTIMX(554)

Purpose MTIM(543)/MTIMX(554) operates a 0.1-s incrementing timer with eight inde-
pendent SVs and Completion Flags. The set value is 0 to 999.9 s for
MTIM(543) and 0 to 6,553.5 s for MTIMX(554), and the timer accuracy is 0 to
0.01 s.
Note The timer accuracy for CS1D CPU Units is 10 ms + the cycle time

269
Timer and Counter Instructions Section 3-6

Ladder Symbol BCD

MTIM(543)

D1 D1: Completion Flags

D2 D2: PV word

S S: First SV word

Binary

MTIMX(554)

D1 D1: Completion Flags

D2 D2: PV word

S S: First SV word
Variations
Variations Executed Each Cycle for ON Condition MTIM(543)/
MTIMX(554)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK Not allowed
Operands D1: Completion Flags
D1 contains the eight Completion Flags as well as the pause and reset bits.
15 9 87 65 4 3 2 1 0
D1

Do not use.
Completion Flags
Reset bit
Pause bit
D2: PV Word
D2 contains the 4-digit binary or BCD PV.
Data Range
BCD #0000 to #9999
Binary &0 to &65535 (decimal)
#0000 to #FFFF (hex)

S: First SV Word
S through S+7 contain the eight independent SVs.
Each SV must be as follows:
Data Range
BCD #0000 to #9999
Binary &0 to &65535 (decimal)
#0000 to #FFFF (hex)

270
Timer and Counter Instructions Section 3-6

Corresponding bit
(Completion Flag) in D1

Data Range
BCD One word for each of 8 timer SV:
#0000 to #9999
Binary One word for each of 8 timer SV:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)

Note S through S+7 must be in the same data area.

Operand Specifications
Area D1 D2 S
CIO Area CIO 0000 to CIO 6143 CIO 0000 to
CIO 6136
Work Area W000 to W511 W000 to W504
Holding Bit Area H000 to H511 H000 to H504
Auxiliary Bit Area A448 to A959 A000 to A952
Timer Area T0000 to T4095 T0000 to T4088
Counter Area C0000 to C4095 C0000 to C4088
DM Area D00000 to D32767 D00000 to
D32760
EM Area without bank E00000 to E32767 E00000 to
E32760
EM Area with bank En_00000 to En_32767 En_00000 to
(n = 0 to C) En_32760
(n = 0 to C)
Indirect DM/EM addresses in @ D00000 to @ D32767
binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM addresses in *D00000 to *D32767
BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers --- DR0 to DR15 ---
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Description When the execution condition for MTIM(543)/MTIMX(554) is ON and the reset
and timer bits are both OFF, MTIM(543)/MTIMX(554) increments the PV in
D2. If the pause bit is turned ON, the timer will stop incrementing the PV, but
the PV will retain its value. MTIM(543)/MTIMX(554) will resume timing when
the pause bit goes OFF again.

271
Timer and Counter Instructions Section 3-6

The PV (content of D2) is compared to the eight SVs in S through S+7 each
time that MTIM(543)/MTIMX(554) is executed, and if any of the SVs is less
than or equal to the PV, the corresponding Completion Flag (D1 bits 00
through 07) is turned ON.
When the PV reaches 9999, the PV will be reset to 0000 and all of the Com-
pletion Flags will be turned OFF. If the reset bit is turned ON while the timer is
operating or paused, the PV will be reset to 0000 and all of the Completion
Flags will be turned OFF.
Timer PV

Timer SVs
0

to to

Timer input

SV 7
SV 2
Timer PV (D2) SV 1
SV 0
0

Bit 7
Completion Bit 2
flags (D1)
Bit 1
Bit 0

The following table shows the operation of MTIM(543)/MTIMX(554) for the

four possible combinations of the reset and pause bits.
Reset bit Pause bit Operation
(Bit 08) (Bit 09)
OFF OFF The PV will be updated and the corresponding Completion
Flag will be turned ON when SV ≤ PV.
ON The PV will not be updated and MTIM(543)/MTIMX(554)
will be treated as NOP(000).
ON OFF The PV will be reset to 0000 and the Completion Flags will
ON be turned OFF. The PV will not be updated.

The reset and pause bits are effective only when the execution condition for
MTIM(543)/MTIMX(554) is ON.
Flags
Name Label Operation
Error Flag ER ON if the PV contained in D2 is not BCD.
OFF in all other cases.

Precautions Unlike most timers, MTIM(543)/MTIMX(554) does not use a timer number.
(Timer area PV refreshing is not performed for MTIM(543)/MTIMX(554).)
When the PV reaches 9999, the PV will be reset to 0000 and all of the Com-
pletion Flags will be turned OFF.

272
Timer and Counter Instructions Section 3-6

If in BCD mode and an SV in S through S+7 does not contain BCD data, that
SV will be ignored. An error will not occur and the Error Flag will not be turned
ON.
Since the Completion Flag for MTIM(543)/MTIMX(554) is in a data area it can
be forced set or forced reset like other bits, but the PV will not change.
When eight or fewer SVs are required, set the word after the last SV to 0000.
MTIM(543)/MTIMX(554) will ignore the SV that is set to 0000 and all of the
remaining SVs.

to to

These SVs
are ignored.

The timer’s PV is refreshed only when MTIM(543)/MTIMX(554) is executed,

so the timer will not operate properly when the cycle time exceeds 100 ms
because the timer increments in 100-ms units. To ensure precise timing and
prevent problems caused by long cycle times, input the same MTIM(543)/
MTIMX(554) instruction at several points in the program.
The timer’s Completion Flag is refreshed only when MTIM(543)/MTIMX(554)
is executed, so a delay of up to one cycle may be required for the Completion
Flag to be turned ON after the timer times out.
When MTIM(543)/MTIMX(554) is in a program section between IL(002) and
ILC(003) and the program section is interlocked, the PV will retain its previous
value (it will not be reset). Be sure to take this fact into account when
MTIM(543)/MTIMX(554) is programmed between IL(002) and ILC(003).
When an operating MTIM(543)/MTIMX(554) timer is in a program section
between JMP(004) and JME(005) and the program section is jumped, the PV
will retain its previous value. Be sure to take this fact into account when
MTIM(543)/MTIMX(554) is programmed between JMP(004) and JME(005).
Be sure that the words specified for the Completion Flags and PV (D1 and
D2) are not used in other instructions. If these words are affected by other
instructions, the timer might not time out properly.
If a word in the CIO area is specified for D1, the SET and RSET instructions
can be used to control the pause and reset bits.
Example When CIO 000000 is ON and the pause bit (CIO 010009) is OFF in the follow-
ing example, the timer will start operating when the reset bit (CIO 010009) is
turned from ON to OFF. The timer’s PV will begin timing up from 0000.
The eight SVs in D00200 through D00207 are compared to the PV and the
corresponding Completion Flags (CIO 010000 through CIO 010007) are
turned on when the SV ≤ PV.

273
Timer and Counter Instructions Section 3-6

D1: 0100CH

Completion Flags

Reset bit
Pause bit

Timer PV
(Incrementing)
D2: D00100
Corresponding completion
flag ON when SV ≤ PV.
Timer SVs
S: D00200
S+1: D00201
S+2: D00202
S+3: D00203
S+4: D00204
S+5: D00205
S+6: D00206
S+7: D00207

Timer input
CIO 000000 Timer input must remain ON
while the timer is timing.
Reset bit
CIO 010008

Pause bit
CIO 010009

Max. PV = 9999 Timing resumes.

Timer SVs
SV 7

SV 1
PV maintained.
SV 0

Completion Flags

274
Timer and Counter Instructions Section 3-6

3-6-9 COUNTER: CNT/CNTX(546)

Purpose CNT/CNTX(546) operates a decrementing counter. The setting range 0 to
9,999 for CNT and 0 to 65,535 for CNTX(546).
Ladder Symbol BCD

Count input CNT

N N: Counter number

S S: Set value
Reset input
Binary

Count input CNTX(546)

N N: Counter number

S S: Set value

Reset input
Variations
Variations Executed Each Cycle for ON Condition CNT/
CNTX(546)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Operands N: Counter Number

The counter number must be between 0000 and 4095 (decimal).
S: Set Value
Data Range
BCD #0000 to #9999
Binary &0 to &65535 (decimal)
#0000 to #FFFF (hex)

Operand Specifications
Area N S
CIO Area --- CIO 0000 to CIO 6143
Work Area --- W000 to W511
Holding Bit Area --- H000 to H511
Auxiliary Bit --- A000 to A959
Area
Timer Area --- T0000 to T4095
Counter Area 0000 to 4095 (decimal) C0000 to C4095
DM Area --- D00000 to D32767
EM Area with- --- E00000 to E32767
out bank
EM Area with --- En_00000 to En_32767
bank (n = 0 to C)

275
Timer and Counter Instructions Section 3-6

Area N S
Indirect DM/EM --- @ D00000 to @ D32767
addresses in @ E00000 to @ E32767
binary
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM --- *D00000 to *D32767
addresses in *E00000 to *E32767
BCD
*En_00000 to *En_32767
(n = 0 to C)
Constants --- BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers --- DR0 to DR15
Index Registers --- ---
Indirect address- ,IR0 to ,IR15
ing using Index –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
Registers
DR0 to DR15, IR0 to IR15

Description The counter PV is decremented by 1 every time that the count input goes from
OFF to ON. The Completion Flag is turned ON when the PV reaches 0.
Once the Completion Flag is turned ON, reset the counter by turning the reset
input ON or by using the CNR(545)/CNRX(547) instruction. Otherwise, the
counter cannot be restarted.
The counter is reset and the count input is ignored when the reset input is ON.
(When a counter is reset, its PV is reset to the SV and the Completion Flag is
turned OFF.)

Count input

Reset input

Counter PV SV

Completion
Flag

Flags
Name Label Operation
Error Flag ER ON if N is indirectly addressed through an Index Register
but the address in the Index Register is not the address of
a counter Completion Flag or counter PV.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.
Equals Flag = Unchanged (See note.)
Negative Flag N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these are turned OFF.

276
Timer and Counter Instructions Section 3-6

Precautions Counter numbers are shared by the CNT, CNTX(546), CNTR(012),

CNTRX(548), CNTW(814), and CNTWX(818) instructions. If two counters
share the same counter number but are not used simultaneously, a duplica-
tion error will be generated when the program is checked but the counters will
operate normally. Counters which share the same counter number will not
operate properly if they are used simultaneously.
A counter’s PV is refreshed when the count input goes from OFF to ON and
the Completion Flag is refreshed each time that CNT/CNTX(546) is executed.
The Completion Flag is turned ON if the PV is 0 and it is turned OFF if the PV
is not 0.
When a CNT/CNTX(546) counter is forced set, its Completion Flag will be
turned ON and its PV will be reset to 0000. When a CNT/CNTX(546) counter
is forced reset, its Completion Flag will be turned OFF and its PV will be set to
the SV.
Be sure to reset the counter by turning the reset input from
OFF → ON → OFF before beginning counting with the count input, as shown
in the following diagram. The count input will not be received if the reset input
is ON.

Reset input

Count input

SV
Counter PV

Completion
Flag

Ready to start
counting

The reset input will take precedence and the counter will be reset if the reset
input and count input are both ON at the same time. (The PV will be reset to
the SV and the Completion Flag will be turned OFF.)

Reset input

Count input

SV
Counter PV

Completion
Flag

Count input Reset input Count input

can be re- takes pre- can be re-
ceived. cedence. ceived.

The operation of the = Flag and N Flag depends on the model of the CPU
Unit. Refer to Flags, above, for details.
Note If online editing is used to add a counter, the counter must be reset before it
will work properly. If the counter is not reset, the previous value will be used as
the counter’s present value (PV), and the counter may not operate properly
after it is written.

277
Timer and Counter Instructions Section 3-6

Counter PVs are retained even through a power interruption. If you want to
restart counting from the SV instead of resuming the count from the retained
PV, add the First Cycle Flag (A20011) as a reset input to the counter.

First Cycle Flag

(A20011)

3-6-10 REVERSIBLE COUNTER: CNTR(012)/CNTRX(548)

Purpose CNTR(012)/CNTRX(548) operates a reversible counter.
Ladder Symbol BCD

Increment input CNTR(012)

N N: Counter number

S S: Set value

Decrement input
Reset input
Binary

Increment input CNTRX(548)

N N: Counter number

S S: Set value

Decrement input
Reset input
Variations
Variations Executed Each Cycle for ON Condition CNTR(012)/
CNTRX(548)
Executed Once for Upward Differentiation Not supported.
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Operands N: Counter Number

The counter number must be between 0000 and 4095 (decimal).
S: Set Value
Data Range
BCD #0000 to #9999
Binary &0 to &65535 (decimal)
#0000 to #FFFF (hex)

278
Timer and Counter Instructions Section 3-6

Operand Specifications
Area N S
CIO Area --- CIO 0000 to CIO 6143
Work Area --- W000 to W511
Holding Bit Area --- H000 to H511
Auxiliary Bit --- A000 to A959
Area
Timer Area --- T0000 to T4095
Counter Area 0000 to 4095 (decimal) C0000 to C4095
DM Area --- D00000 to D32767
EM Area with- --- E00000 to E32767
out bank
EM Area with --- En_00000 to En_32767
bank (n = 0 to C)
Indirect DM/EM --- @ D00000 to @ D32767
addresses in @ E00000 to @ E32767
binary
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM --- *D00000 to *D32767
addresses in *E00000 to *E32767
BCD
*En_00000 to *En_32767
(n = 0 to C)
Constants --- BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers --- DR0 to DR15
Index Registers --- ---
Indirect address- ,IR0 to ,IR15
ing using Index –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
Registers
DR0 to DR15, IR0 to IR15

Description The counter PV is incremented by 1 every time that the increment input goes
from OFF to ON and it is decremented by 1 every time that the decrement
input goes from OFF to ON. The PV can fluctuate between 0 and the SV.

Increment input

Decrement input

Counter PV

When incrementing, the Completion Flag will be turned ON when the PV is

incremented from the SV back to 0 and it will be turned OFF again when the
PV is incremented from 0 to 1.

279
Timer and Counter Instructions Section 3-6

SV
Counter PV

+1

Completion Flag

When decrementing, the Completion Flag will be turned ON when the PV is

decremented from 0 up to the SV and it will be turned OFF again when the PV
is decremented from the SV to SV–1.
SV −1
Counter PV

Completion Flag

Flags
Name Label Operation
Error Flag ER ON if N is indirectly addressed through an Index Register
but the address in the Index Register is not the PV
address of a counter.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.

Precautions Counter numbers are shared by the CNT, CNTX(546), CNTR(012),

CNTRX(548), CNTW(814), and CNTWX(818) instructions. If two counters
share the same counter number but are not used simultaneously, a duplica-
tion error will be generated when the program is checked but the counters will
operate normally. Counters which share the same counter number will not
operate properly if they are used simultaneously.
The PV will not be changed if the increment and decrement inputs both go
from OFF to ON at the same time. When the reset input is ON, the PV will be
reset to 0 and both count inputs will be ignored.
The Completion Flag will be ON only when the PV has been incremented
from the SV to 0 or decremented from 0 to the SV; it will be OFF in all other
cases.
When inputting the CNTR(012)/CNTRX(548) instruction with mnemonics, first
enter the increment input (II), then the decrement input (DI), the reset input
(R), and finally the CNTR(012)/CNTRX(548) instruction. When entering with
the ladder diagrams, first input the increment input (II), then the CNTR(012)/
CNTRX(548) instruction, the decrement input (DI), and finally the reset input
(R).
Examples Basic Operation of CNTR(012)/CNTRX(548)
The counter PV is reset to 0 by turning the reset input (CIO 000002) ON and
OFF. The PV is incremented by 1 each time that the increment input
(CIO 000000) goes from OFF to ON. When the PV is incremented from the
SV (3), it is automatically reset to 0 and the Completion Flag is turned ON.
Likewise, the PV is decremented by 1 each time that the decrement input
(CIO 000001) goes from OFF to ON. When the PV is decremented from 0, it
is automatically set to the SV (3) and the Completion Flag is turned ON.

280
Timer and Counter Instructions Section 3-6

000000 Increment input

CNTR
Decrement 0001
000001 input
#0003
ON
000002 Reset input
Increment input
CIO 000000 OFF

ON
Decrement input
CIO 000001 OFF
or

000000 Increment input Reset input ON

CNTRX CIO 000002 OFF
Decrement 0001
000001 input
&0003 SV
Counter PV 3
C0001
000002 0
Reset input

ON
Completion Flag
C0001 OFF

Specifying the SV in a Word

In the following example, the SV for CNTR(012) 0007 is determined by the
content of CIO 0001. When the content of CIO 0001 is controlled by an exter-
nal switch, the set value can be changed manually from the switch.

Fixed SV:
5000

SV:
CIO 0001

Increment input

Decrement input

Completion Flag
Roll-over Roll-over

281
Timer and Counter Instructions Section 3-6

3-6-11 RESET TIMER/COUNTER: CNR(545)/CNRX(547)

Purpose Resets the timers or counters within the specified range of timer or counter
numbers.
Ladder Symbol BCD

CNR(545)

N1 N1: First number in range

N2 N2: Last number in range

Binary

CNRX(547)

N1 N1: First number in range

N2 N2: Last number in range

Variations
Variations Executed Each Cycle for ON Condition CNR(545)/
CNRX(547)
Executed Once for Upward Differentiation @CNR(545)/
CNRX(547)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands N1: First Number in Range

N1 must be a timer number between T0000 and T4095 or a counter number
between C0000 and C4095.
N2: Last Number in Range
N2 must be a timer number between T0000 and T4095 or a counter number
between C0000 and C4095.
Note N1 and N2 must be in the same data area, i.e., N1 and N2 must be timer num-
bers or counter numbers.
Operand Specifications
Area N1 N2
CIO Area --- ---
Work Area --- ---
Holding Bit Area --- ---
Auxiliary Bit Area --- ---
Timer Area C0000 to C4095 C0000 to C4095
Counter Area T0000 to T4095 T0000 to T4095
DM Area --- ---
EM Area without bank --- ---
EM Area with bank --- ---
Indirect DM/EM --- ---
addresses in binary
Indirect DM/EM --- ---
addresses in BCD

282
Timer and Counter Instructions Section 3-6

Area N1 N2
Constants --- ---
Data Registers --- ---
Index Registers --- ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description CNR(545)/CNRX(547) resets the Completion Flags of all timers or counters

from N1 to N2. At the same time, the PVs will all be set to the maximum value
(9999 for BCD and FFFF for binary). (The PV will be set to the SV the next
time that the timer or counter instruction is executed.)
Operation of CNR(545)
The following table shows the timer and counter instructions (with BCD PVs),
which are reset by CNR(545).
Instructions reset Operation of CNR(545)
TIM: HUNDRED-MS TIMER The PV is set to its maximum value
TIMH(015): TEN-MS TIMER (9,999 BCD) and the Completion Flag
TMHH(540): ONE-MS TIMER is turned OFF.
TTIM(087): ACCUMULATIVE TIMER
TIMW(813): HUNDRED-MS TIMER WAIT
TMHW(815): TEN-MS TIMER WAIT
CNT: COUNTER
CNTR(012): REVERSIBLE COUNTER
CNTW(814): COUNTER WAIT
TIMU(541): TENTH-MS TIMER The Completion Flag is turned OFF.
TMUH(544): HUNDREDTH-MS TIMER (The PV cannot be read.)
(TIMU(541) and TMUH(544) are supported
by CJ1-H-R CPU Units only.)

Operation of CNRX(547)
The following table shows the timer and counter instructions (with binary
PVs), which are reset by CNRX(547).
Instructions reset Operation of CNR(545)
TIMX(550): HUNDRED-MS TIMER The PV is set to its maximum value
TIMHX(551): TEN-MS TIMER (FFFF hex) and the Completion Flag is
TMHHX(552): ONE-MS TIMER turned OFF.
TTIMX(555): ACCUMULATIVE TIMER
TIMWX(816): HUNDRED-MS TIMER WAIT
TMHWX(817):TEN-MS TIMER WAIT
CNTX(546): COUNTER
CNTRX(548): REVERSIBLE COUNTER
CNTWX(818): COUNTER WAIT
TIMUX(556): TENTH-MS TIMER The Completion Flag is turned OFF.
TMUHX(557): HUNDREDTH-MS TIMER (The PV cannot be read.)
(TIMUX(556) and TMUHX(557) are sup-
ported by CJ1-H-R CPU Units only.)

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Timer and Counter Instructions Section 3-6

Flags
Name Label Operation
Error Flag ER ON if N1 is indirectly addressed through an Index Register
but the address in the Index Register is not the PV
address of a timer or counter.
ON if N2 is indirectly addressed through an Index Register
but the address in the Index Register is not the PV
address of a timer or counter.
ON if N1 and N2 are not in the same data area.
OFF in all other cases.

Precautions The CNR(545)/CNRX(547) instructions do not reset TIML(542), TIMLX(553),

MTIM(543), and MTIMX(554), because these timers do not use timer num-
bers.
The CNR(545)/CNRX(547) instructions do not reset the timer/counter instruc-
tions themselves, they reset the PVs and Completion Flags allocated to those
instructions. In most cases, the effect of CNR(545)/CNRX(547) is different
from directly resetting the instructions. For example, when a TIM/TIMX(550)
instruction is reset directly its PV is set to the SV, but when that timer is reset
by CNR(545)/CNRX(547) its PV is set to the maximum value (9999 for BCD
and FFFF for binary).
When N1 and N2 are specified with N1>N2, only the Completion Flag for the
timer/counter number will be reset.

Example When CIO 000000 is ON in the following example, the Completion Flags for
timers T0002 to T0005 are turned OFF and the timers’ PVs are set to the
maximum value (9999 for BCD and FFFF for binary).
When CIO 000001 is ON, the Completion Flags for counters C0003 to C0007
are turned OFF and the counters’ PVs are set to the maximum value (9999 for
BCD and FFFF for binary).
000000
CNR
T0002
T0005

000001
CNR
C0003
C0007

000000
CNRX
T0002
T0005

000001
CNRX
C0003
C0007

3-6-12 Example Timer and Counter Applications

The following examples show various applications of timer and counter
instructions including long-term timers, a two-stage counter, ON/OFF delay,
one-shot bit, and flicker bit.

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Timer and Counter Instructions Section 3-6

Example 1: The following program examples show three ways to create long-term timers
Long-term Timers with standard TIM and CNT instructions.
Two TIM Instructions
In this example, two TIM instructions are combined to make a 30-minute
timer.
000000
Address Instruction Operands
000000 LD 000000
000001 TIM 0001
T0001
#9000
000002 LD T0001
000003 TIM 0002
#9000
T0002 000004 LD T0002
000005 OUT 000200

TIM and CNT Instructions

In this example, a TIM instruction and a CNT instruction are combined to
make a 500-second timer.
TIM 0001 generates a pulse every 5 s and CNT 0002 counts these pulses.
The set value for this combination is the timer interval × counter SV. In this
case, the timer SV would be 5 s × 100 = 500 s. With this combination, the
long-term timer’s PV is actually the PV of a counter, which is maintained
through power interruptions.

Address Instruction Operands

000000 LD 010000
000001 LD 000001
000002 CNT 0002
#0100
000003 LD 000000
000004 AND NOT 010000
Start Count up 000005 AND NOT C0002
000006 TIM 0001
#0050
000007 LD T0001
000008 OUT 010000
000009 LD C0002
000010 OUT 000201

Clock Pulse and CNT Instruction

In this example, a CNT instruction counts the pulses from the 1-s clock pulse
to make a 700-second timer.
If the First Cycle Flag (A20011) is ORed with the counter’s reset input
(CIO 000001), the counter’s PV will be reset to the SV (0700) when program
execution begins rather than resuming the count from the previous PV.

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Timer and Counter Instructions Section 3-6

000000 1 s (1-s clock)

Address Instruction Operands
000000 LD 000000
000001 AND 1s
000001
000002 LD 000001
000003 OR A20011
A20011 000004 CNT 0001
#0700
C0001 000005 LD C0001
000006 OUT 000202

Example 2: When an SV higher than 9999 is required, two counters can be combined as
Two-stage Counter shown in the following example. In this case, two CNT instructions are com-
bined to make a BCD counter with an SV of 20,000.

Address Instruction Operands

000000 LD 000000
000001 AND 000001
000002 LD NOT 000002
000003 OR C0001
000004 OR C0002
000005 CNT 0001
#0100
000006 LD C0001
000007 LD NO 000002
000008 CNT 0002
#0200
000009 LD C0002
000010 OUT 000203

Example 3: In this example two TIM timers are combined with KEEP(011) to make an ON
ON/OFF Delay delay and an OFF delay. CIO 000500 will be turned ON 5.0 seconds after
CIO 000000 goes ON and it will be turned OFF 3.0 seconds after CIO 000000
goes OFF.

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Timer and Counter Instructions Section 3-6

Address Instruction Operands

000000 LD 000000
000001 TIM 0001
#0050
000002 LD 000500
000003 AND NOT 000000
000004 TIM 0002
#0030
000005 LD T0001
000006 LD T0002
000007 KEEP(011) 000500

CIO 000000

CIO 000500

5.0 s 3.0 s

Example 4: A TIM timer can be combined with OUT or OUT NOT to control how long a
One-shot Bit particular bit is ON or OFF. In this example, CIO 000204 will be ON for 1.5
seconds (the SV of T0001) after CIO 000000 goes ON.

Address Instruction Operands

000000 LD 000000
000001 LD 001000
000002 AND NOT 010000
000003 OR 000000
000004 OUT 001000
000005 LD 001000
000006 TIM 0001
#0015
000007 LD T0001
000008 OUT 010000
000009 LD 001000
000010 AND NOT 010000
000011 OUT 000204

CIO 000000

CIO 000204

1.5 s 1.5 s

Example 4: The following program examples show two ways to create flicker bits. The
Flicker Bit second example just mimics a clock pulse.
Two TIM Instructions
Two TIM timers can be combined to make a bit turn ON and OFF at regular
intervals while the execution condition is ON. In this example, CIO 000205 will
be OFF for 1.0 second and then ON for 1.5 seconds as long as CIO 000000 is
ON.

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Timer and Counter Instructions Section 3-6

Address Instruction Operands

000000 LD 000000
000001 AND T0002
000002 TIM 0001
#0010
000003 LD 000205
000004 TIM 0002
#0015
000005 LD T0001
000006 OUT 000205

CIO 000000

CIO 000205
1.0 s 1.5 s 1.0 s 1.5 s

Clock Pulse
The desired execution condition can be combined with a clock pulse to mimic
the clock pulse (0.1 s, 0.2 s, or 1.0 s).
1-s clock pulse Address Instruction Operands
000000 LD 000000
000001 AND 1s
000002 OUT 000206

1-s clock
pulse

3-6-13 Indirect Addressing of Timer/Counter Numbers

Timer and counter numbers can be indirectly addressed using Index Regis-
ters. When Index Registers will be used for indirect addressing, use
MOVRW(561) (MOVE TIMER/COUNTER PV TO REGISTER) to set the PLC
memory address of the desired timer or counter’s PV to the desired Index
Register.
The following timers and counters can be indirectly addressed using Index
Registers: TIM, TIMX(550), TIMH(015), TIMHX(551), TTIM(087),
TTIMX(555), TMHH(540), TMHHX(552), TIMW(813), TIMWX(816),
TMHW(815), TMHWX(817), CNT, CNTX(546), CNTR(012), CNTRX(548),
CNTW(814), and CNTWX(818). (These are the timers and counters that use
timer and counter numbers.)
The timer or counter instruction will not be executed if the PLC memory
address in the specified Index Register is not the address of a timer or counter
PV.
Using Index Registers to indirectly address timers and counters can reduce
the size of the program and increase flexibility. For example, common subrou-
tines can be created.

Example The following example shows a program section that uses indirect addressing
to define and start 100 timers with SVs contained in D00100 through D00199.

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Timer and Counter Instructions Section 3-6

IR0 contains the PLC memory address of the timer PV and IR1 contains the
PLC memory address of the timer Completion Flag.
DM address Content Function
D00100 0010 SV for T0000
D00101 0100 SV for T0001
D00102 0050 SV for T0002
. . .
. . .
. . .
D00199 0999 SV for T0099

P_On
1
(Always ON
Flag)

4
&100

FOR
&100

5
@D00000

P_On
++
(Always ON
Flag)

NEXT

1,2,3... 1. MOVRW(561) moves the PLC memory address of the PV for timer T0000
to IR0. Afterwards IR0 can be used in place of the timer number.
2. MOVR(560) moves the PLC memory address of the Completion Flag for
timer T0000 to IR1.
3. MOVR(560) moves the PLC memory address of CIO 200000 into IR2.
4. MOV(021) moves &100 into D00000 for indirect addressing of the timer
SVs.
5. The content of IR0, IR1, IR2, and D00000 are incremented by 1 each time
as this loop is executed 100 times, starting timers T0000 through T0099.

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Timer and Counter Instructions Section 3-6

The loop in the program above has 4 input parameters which are used to start
all 100 timers with this common subroutine.
IR0 The PLC memory address of the timer’s PV
IR1 The PLC memory address of the timer’s Completion Flag
IR2 The PLC memory address of the timer’s execution condition
D00000 The DM address of the word containing the timer’s SV
The subroutine above is equivalent to the 400 instructions below.

Address Instruction Operands

200000
000000 LD NOT 200000
000001 TIM 0000
D00100
000002 LD T0000
T0000
000003 OUT 200000
000004 LD NOT 200001
200001
000005 TIM 0001
D00101
000006 LD T0001
000007 OUT 200001
000008 LD NOT 200002
T0001
000009 TIM 0002
D00102
200602
000010 LD T0002
000011 OUT 200002

T0099 000396 LD NOT 200602

000397 TIM 0099
D00199
000398 LD T0000
000399 OUT 200602

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Comparison Instructions Section 3-7

3-7 Comparison Instructions

This section describes instructions used to compare data of various lengths
and in various ways.
Instruction Mnemonic Function Page
code
Input Comparison Instructions =, <>, <, <=, >, >= 300 to 328 291
(S, L) (LD, AND, OR)
Time Comparison Instructions =DT, <>DT, <DT, <=DT, >DT, 341 to 346 297
>=DT (LD, AND, OR)
COMPARE CMP 020 303
DOUBLE COMPARE CMPL 060 306
SIGNED BINARY COMPARE CPS 114 309
DOUBLE SIGNED BINARY CPSL 115 312
COMPARE
MULTIPLE COMPARE MCMP 019 315
TABLE COMPARE TCMP 085 317
BLOCK COMPARE BCMP 068 320
EXPANDED BLOCK COMPARE BCMP2 502 322
AREA RANGE COMPARE ZCP 088 326
DOUBLE AREA RANGE COM- ZCPL 116 329
PARE

3-7-1 Input Comparison Instructions (300 to 328)

Purpose Input comparison instructions compare two values (constants and/or the con-
tents of specified words) and create an ON execution condition when the
comparison condition is true. Input comparison instructions are available to
compare signed or unsigned data of one-word or double length data.
Note Refer to 3-15-24 Single-precision Floating-point Comparison Instructions for
details on single-precision floating-point input comparison instructions and 3-
16-21 Double-precision Floating-point Input Instructions for details on double-
precision floating-point input comparison instructions.

Ladder Symbol
Symbol & options

S1 S1: Comparison data 1

S2 S2: Comparison data 2

Variations
Variations Creates ON Each Cycle Comparison is True Input compari-
son instruction
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
for Instructions for One- Area S1 S2
word Data CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511

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Comparison Instructions Section 3-7

Area S1 S2
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_ 32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Operand Specifications
for Instructions for Area S1 S2
Double-length Data CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF (binary)
Data Registers ---

292
Comparison Instructions Section 3-7

Area S1 S2
Index Registers IR0 to IR15 (for unsigned data only)
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The input comparison instruction compares S1 and S2 as signed or unsigned

values and creates an ON execution condition when the comparison condition
is true. Unlike instructions such as CMP(020) and CMPL(060), the result of an
input comparison instruction is reflected directly as an execution condition, so
it is not necessary to access the result of the comparison through an Arith-
metic Flag and the program is simpler and faster.
Inputting the Instructions
The input comparison instructions are treated just like the LD, AND, and OR
instructions to control the execution of subsequent instructions.
Input type Operation
LD The instruction can be connected directly to the left bus bar.
AND The instruction cannot be connected directly to the left bus bar.
OR The instruction can be connected directly to the left bus bar.

LD connection ON execution condition when

comparison result is true.
<

ON execution condition when

AND connection comparison result is true.

<

OR connection

<
ON execution condition when
comparison result is true.

Options
The input comparison instructions can compare signed or unsigned data and
they can compare one-word or double values. If no options are specified, the

293
Comparison Instructions Section 3-7

comparison will be for one-word unsigned data. With the three input types and
two options, there are 72 different input comparison instructions.
Symbol Option (data format) Option (data length)
= (Equal) None: Unsigned data None: One-word data
<> (Not equal) S: Signed data L: Double-length data
< (Less than)
<= (Less than or equal)
> (Greater than)
>= (Greater than or equal)

Unsigned input comparison instructions (i.e., instructions without the S option)

can handle unsigned binary or BCD data. Signed input comparison instruc-
tions (i.e., instructions with the S option) handle signed binary data.
Summary of Input Comparison Instructions
The following table shows the function codes, mnemonics, names, and func-
tions of the 72 input comparison instructions. (For one-word comparisons
C1=S1 and C2=S2; for double comparisons C1=S1+1, S1 and C2=S2+1, S2.)
Code Mnemonic Name Function
300 LD= LOAD EQUAL True if
AND= AND EQUAL C1 = C2
OR= OR EQUAL
301 LD=L LOAD DOUBLE EQUAL
AND=L AND DOUBLE EQUAL
OR=L OR DOUBLE EQUAL
302 LD=S LOAD SIGNED EQUAL
AND=S AND SIGNED EQUAL
OR=S OR SIGNED EQUAL
303 LD=SL LOAD DOUBLE SIGNED EQUAL
AND=SL AND DOUBLE SIGNED EQUAL
OR=SL OR DOUBLE SIGNED EQUAL
305 LD<> LOAD NOT EQUAL True if
AND<> AND NOT EQUAL C1 ≠ C2
OR<> OR NOT EQUAL
306 LD<>L LOAD DOUBLE NOT EQUAL
AND<>L AND DOUBLE NOT EQUAL
OR<>L OR DOUBLE NOT EQUAL
307 LD<>S LOAD SIGNED NOT EQUAL
AND<>S AND SIGNED NOT EQUAL
OR<>S OR SIGNED NOT EQUAL
308 LD<>SL LOAD DOUBLE SIGNED NOT EQUAL
AND<>SL AND DOUBLE SIGNED NOT EQUAL
OR<>SL OR DOUBLE SIGNED NOT EQUAL

294
Comparison Instructions Section 3-7

Code Mnemonic Name Function

310 LD< LOAD LESS THAN True if
AND< AND LESS THAN C1 < C2
OR< OR LESS THAN
311 LD<L LOAD DOUBLE LESS THAN
AND<L AND DOUBLE LESS THAN
OR<L OR DOUBLE LESS THAN
312 LD<S LOAD SIGNED LESS THAN
AND<S AND SIGNED LESS THAN
OR<S OR SIGNED LESS THAN
313 LD<SL LOAD DOUBLE SIGNED LESS THAN
AND<SL AND DOUBLE SIGNED LESS THAN
OR<SL OR DOUBLE SIGNED LESS THAN
315 LD<= LOAD LESS THAN OR EQUAL True if
AND<= AND LESS THAN OR EQUAL C1 ≤ C2
OR<= OR LESS THAN OR EQUAL
316 LD<=L LOAD DOUBLE LESS THAN OR EQUAL
AND<=L AND DOUBLE LESS THAN OR EQUAL
OR<=L OR DOUBLE LESS THAN OR EQUAL
317 LD<=S LOAD SIGNED LESS THAN OR EQUAL
AND<=S AND SIGNED LESS THAN OR EQUAL
OR<=S OR SIGNED LESS THAN OR EQUAL
318 LD<=SL LOAD DOUBLE SIGNED LESS THAN OR EQUAL True if
AND<=SL AND DOUBLE SIGNED LESS THAN OR EQUAL C1 ≤ C2
OR<=SL OR DOUBLE SIGNED LESS THAN OR EQUAL
320 LD> LOAD GREATER THAN True if
AND> AND GREATER THAN C1 > C2
OR> OR GREATER THAN
321 LD>L LOAD DOUBLE GREATER THAN
AND>L AND DOUBLE GREATER THAN
OR>L OR DOUBLE GREATER THAN
322 LD>S LOAD SIGNED GREATER THAN
AND>S AND SIGNED GREATER THAN
OR>S OR SIGNED GREATER THAN
323 LD>SL LOAD DOUBLE SIGNED GREATER THAN
AND>SL AND DOUBLE SIGNED GREATER THAN
OR>SL OR DOUBLE SIGNED GREATER THAN
325 LD>= LOAD GREATER THAN OR EQUAL True if
AND>= AND GREATER THAN OR EQUAL C1 ≥ C2
OR>= OR GREATER THAN OR EQUAL
326 LD>=L LOAD DOUBLE GREATER THAN OR EQUAL
AND>=L AND DOUBLE GREATER THAN OR EQUAL
OR>=L OR DOUBLE GREATER THAN OR EQUAL
327 LD>=S LOAD SIGNED GREATER THAN OR EQUAL
AND>=S AND SIGNED GREATER THAN OR EQUAL
OR>=S OR SIGNED GREATER THAN OR EQUAL
328 LD>=SL LOAD DBL SIGNED GREATER THAN OR EQUAL
AND>=SL AND DBL SIGNED GREATER THAN OR EQUAL
OR>=SL OR DBL SIGNED GREATER THAN OR EQUAL

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Comparison Instructions Section 3-7

Flags
Name Label Operation
Error Flag ER OFF or unchanged (See note.)
Greater Than > ON if S1 > S2 with one-word data.
Flag
ON if S1+1, S1 > S2+1, S2 with double-length data.
OFF in all other cases.
Greater Than or > = ON if S1 ≥ S2 with one-word data.
Equal Flag
ON if S1+1, S1 ≥ S2+1, S2 with double-length data.
OFF in all other cases.
Equal Flag = ON if S1 = S2 with one-word data.
ON if S1+1, S1 = S2+1, S2 with double-length data.
OFF in all other cases.
Not Equal Flag = ON if S1 ≠ S2 with one-word data.
ON if S1+1, S1 ≠ S2+1, S2 with double-length data.
OFF in all other cases.
Less Than Flag < ON if S1 < S2 with one-word data.
ON if S1+1, S1 < S2+1, S2 with double-length data.
OFF in all other cases.
Less Than or <= ON if S1 ≤ S2 with one-word data.
Equal Flag
ON if S1+1, S1 ≤ S2+1, S2 with double-length data.
OFF in all other cases.
Negative Flag N OFF or unchanged (See note.)

Note In CS1 and CJ1 CPU Units, these Flags are turned OFF.
In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, these Flags are left
unchanged.

Precautions Input comparison instructions cannot be used as right-hand instructions, i.e.,

another instruction must be used between them and the right bus bar.

Examples AND LESS THAN: AND<(310)

When CIO 000000 is ON in the following example, the contents of D00100
and D00200 are compared in as unsigned binary data. If the content of
D00100 is less than that of D00200, CIO 005000 is turned ON and execution
proceeds to the next line. If the content of D00100 is not less than that of
D00200, the remainder of the instruction line is skipped and execution moves
to the next instruction line.

000000 005000
<
Unsigned S1: D00100 S2: D00200
LESS THAN 8714 3A1C
Comparison
000001 005001 Decimal: 34,580 Decimal: 14,876
<S 34,580 > 14,876
(Will not proceed to next line.)

AND SIGNED LESS THAN: AND<S(312)

When CIO 000001 is ON in the following example, the contents of D00110
and D00210 are compared as signed binary data. If the content of D00110 is
less than that of D00210, CIO 005001 is turned ON and execution proceeds
to the next line. If the content of D00110 is not less than that of D00210, the

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Comparison Instructions Section 3-7

remainder of the instruction line is skipped and execution moves to the next
instruction line.

Signed S1: D00110 S2: D00210

LESS THAN
Comparison 8714 3A1C
Decimal: −30,956 Decimal: 14,876
−30,956 < 14,876
(Will proceed to next line.)

3-7-2 Time Comparison Instructions (341 to 346)

Purpose Time comparison instructions compare two BCD time values and create an
ON execution condition when the comparison condition is true.
The time comparison instructions are treated just like the LD, AND, and OR
instructions to control the execution of subsequent instructions.
These instructions are supported only by CS/CJ-series CPU Unit Ver. 2.0 or
later.
Ladder Symbol
LD

Symbol
C C: Control word
S1 S1: First word of present time
S2 S2: First word of comparison time

AND

Symbol
C C: Control word
S1 S1: First word of present time
S2 S2: First word of comparison time

OR

Symbol
C C: Control word
S1 S1: First word of present time
S2 S2: First word of comparison time

Variations
Variations Creates ON Each Cycle Comparison is True Time compari-
son instruction
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

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Comparison Instructions Section 3-7

Operands C: Control Word

Bits 00 to 05 of C specify whether or not the time data will be masked for the
comparison. Bits 00 to 05 mask the seconds, minutes, hours, day, month, and
year, respectively. If all 6 values are masked, the instruction will not be exe-
cuted, the execution condition will be OFF, and the Error Flag will be turned
ON.
15 8 7 6 5 4 3 2 1 0
C 0 0 0 0 0 0 0 0 0 0

Masks seconds data when ON.

Masks minutes data when ON.
Masks hours data when ON.
Masks day data when ON.
Masks month data when ON.
Masks year data when ON.

S1 through S1+2: Present Time Data

S1 through S1+2 contain the present time data. S1 through S1+2 must be in
the same data area.
15 8 7 0
S1

Seconds: 00 to 59 (BCD)

Minutes: 00 to 59 (BCD)

15 8 7 0
S1+1

Hour: 00 to 23 (BCD)

Day: 01 to 31 (BCD)

15 8 7 0
S1+2

Month: 01 to 12 (BCD)

Year: 00 to 99 (BCD)

Note When using the CPU Unit’s internal clock data for the comparison, set S1 to
A351 to specify the CPU Unit’s internal clock data (A351 to A353).

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Comparison Instructions Section 3-7

S2 through S2+2: Comparison Time Data

S2 through S2+2 contain the comparison time data. S2 through S2+2 must be
in the same data area.
15 8 7 0
S2

Seconds: 00 to 59 (BCD)

Minutes: 00 to 59 (BCD)

15 8 7 0
S2+1

Hour: 00 to 23 (BCD)

Day: 01 to 31 (BCD)

15 8 7 0
S2+2

Month: 01 to 12 (BCD)

Year: 00 to 99 (BCD)

Note The year value indicates the last two digits of the year. Values 00 to 97 are
interpreted as 2000 to 2097. Values 98 and 99 are interpreted as 1998 and
1999.

Operand Specifications
Area C S1 S2
CIO Area CIO 0000 to CIO 0000 to CIO 6141
CIO 6143
Work Area W000 to W511 W000 to W509
Holding Bit Area H000 to H511 H000 to H509
Auxiliary Bit Area A448 to A959 A000 to A957
Timer Area T0000 to T4095 T0000 to T4093
Counter Area C0000 to C4095 C0000 to C4093
DM Area D00000 to D32767 D00000 to D32765
EM Area without bank E00000 to E32767 E00000 to E32765
EM Area with bank En_00000 to En_00000 to En_32765
En_32767 (n = 0 to C)
(n = 0 to C)
Indirect DM/EM --- @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM --- *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)

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Comparison Instructions Section 3-7

Area C S1 S2
Constants See previous page. See previous page. ---

Data Registers ---

Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The time comparison instruction compares the unmasked values (corre-
sponding bit of C set to 0) of the present time data in S1 to S1+2 with the com-
parison time data in S2 to S2+2 and creates an ON execution condition when
the comparison condition is true. At the same time, the result of a time com-
parison instruction is reflected in the arithmetic flags (=, <>, <, <=, >, >=).
There are 18 possible combinations of time comparison instructions.
Any time values that are masked in the control word (C) are not included in
the comparison.
The following table shows the ON/OFF status of each flag for each compari-
son result.
Result Flag status
= <> < <= > >=
S1 = S2 ON OFF OFF ON OFF ON
S1 > S2 OFF ON OFF OFF ON ON
S1 < S2 OFF ON ON ON OFF OFF

Comparison
S1 S2

Conditions Flags
Result (=, <>, <, <=, >, >=)

Masking Time Values

Time values can be masked individually and excluded from the comparison
operation. To mask a time value, set the corresponding bit in the control word
(C) to 1. Bits 00 to 05 of C mask the seconds, minutes, hours, day, month, and
year, respectively.
Example:
When C = 39 hex, the rightmost 6 bits are 111001 (year=1, month=1, day=1,
hours=0, minutes=0, and seconds=1) so only the hours and minutes are com-
pared. This mask setting can be used to perform a particular operation at a
given time (hour and minute) each day.

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Comparison Instructions Section 3-7

Present time data Comparison time data

15 08 07 00 15 08 07 00
S1 Minute (00 to Second (00 to S2 Minute (00 to Second (00 to
59, BCD) 59, BCD) 59, BCD) 59, BCD)

S1+1 Day of month Hour (00 to S2+1 Day of month Hour (00 to
(01 to 31, BCD) 23, BCD) (01 to 31, BCD) 23, BCD)
Year (00 to Month (01 to Year (00 to Month (01 to
S1+2 99, BCD) 12, BCD) S2+2 99, BCD) 12, BCD)

Compares only hours and Year, month, day, and seconds

minutes data. data is masked.

Previous data comparison instructions compared data in 16-bit units. The

time comparison instructions are limited to comparing 8-bit time values.
The following table shows the structure of the CPU Unit’s internal Calendar/
Clock Area.
Addresses Contents
A35100 to A35107 Second (00 to 59, BCD)
A35108 to A35115 Minute (00 to 59, BCD)
A35200 to A35207 Hour (00 to 23, BCD)
A35208 to A35215 Day of month (01 to 31, BCD)
A35300 to A35307 Month (01 to 12, BCD)
A35308 to A35315 Year (00 to 99, BCD)

The Calendar/Clock Area can be set with a Programming Device (including a

Programming Console), DATE(735) instruction, or “CLOCK WRITE” FINS
command (0702 hex).
Summary of Time Comparison Instructions
The following table shows the function codes, mnemonics, names, and func-
tions of the 18 time comparison instructions.
Code Mnemonic Name Function
341 LD= DT LOAD EQUAL True if
AND=DT AND EQUAL S1 = S2
OR=DT OR EQUAL
342 LD<>DT LOAD NOT EQUAL True if
AND<>DT AND NOT EQUAL S1 ≠ S2
OR<>DT OR NOT EQUAL
343 LD<DT LOAD LESS THAN True if
AND<DT AND LESS THAN S1 < S2
OR<DT OR LESS THAN
344 LD<=DT LOAD LESS THAN OR EQUAL True if
AND<=DT AND LESS THAN OR EQUAL S1 ≤ S2
OR<=DT OR LESS THAN OR EQUAL
345 LD>DT LOAD GREATER THAN True if
AND>DT AND GREATER THAN S1 > S2
OR>DT OR GREATER THAN
346 LD>=DT LOAD GREATER THAN OR EQUAL True if
AND>=DT AND GREATER THAN OR EQUAL S1 ≥ S2
OR>=DT OR GREATER THAN OR EQUAL

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Comparison Instructions Section 3-7

Flags
Name Label Operation
Error Flag ER ON if all 6 of the mask bits (C bits 00 to 05) are ON.
OFF in all other cases.
Greater Than > ON if S1 > S2.
Flag
OFF in all other cases.
Greater Than or > = ON if S1 ≥ S2.
Equal Flag
OFF in all other cases.
Equal Flag = ON if S1 = S2.
OFF in all other cases.
Not Equal Flag = ON if S1 ≠ S2.
OFF in all other cases.
Less Than Flag < ON if S1 < S2.
OFF in all other cases.
Less Than or <= ON if S1 ≤ S2.
Equal Flag
OFF in all other cases.
Negative Flag N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these Flags are turned OFF.

Precautions Time comparison instructions cannot be used as right-hand instructions, i.e.,

another instruction must be used between them and the right bus bar.

Example When CIO 000000 is ON and the time is 13:00:00, CIO 005000 is turned ON.
The contents of A351 to A353 (the CPU Unit’s internal calendar/clock data)
are used as the present time data and the contents of D00100 to D00102 are
used as the comparison time data. The year, month, and day values are
masked, so only the hour, minute, and second data are compared.
000000 005000
=DT
C D00000
S1 A352
S2 D00100

7 6 5 4 3 2 1 0
D00000 - - 1 1 1 0 0 0 D00000 set to 0038 hex

Seconds compared.
Minutes compared.
Hours compared.
Day masked.
Month masked.
Year masked.

Shaded data is compared.

15 8 7 0 15 8 7 0
A351 Minute Second S2: D00100 00 00
A352 Day of month Hour S2+1: D00101 - 13
A353 Year Month S2+2: D00102 - -

Conditions Flags set as soon as

execution condition is turned ON.

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Comparison Instructions Section 3-7

3-7-3 COMPARE: CMP(020)

Purpose Compares two unsigned binary values (constants and/or the contents of
specified words) and outputs the result to the Arithmetic Flags in the Auxiliary
Area.
Ladder Symbol
CMP(020)

S1 S1: Comparison data 1

S2 S2: Comparison data 2

Variations
Variations Executed Each Cycle for ON Condition CMP(020)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification (See note.) !CMP(020)

Note Immediate refreshing is not supported by CS1D CPU Units for Duplex-CPU
Systems.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S1 S2
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF
(binary)
Data Registers DR0 to DR15

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Comparison Instructions Section 3-7

Area S1 S2
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description CMP(020) compares the unsigned binary data in S1 and S2 and outputs the
result to Arithmetic Flags (the Greater Than, Greater Than or Equal, Equal,
Less Than or Equal, Less Than, and Not Equal Flags) in the Auxiliary Area.
Unsigned binary
comparison

Arithmetic Flags
(>, >=, =, <=, <, <>)

Condition Flag Status

The following table shows the status of the Arithmetic Flags after execution of
CMP(020). (A status of “---” indicates that the Flag may be ON or OFF.)
CMP(020) Flag status
Result > >= = <= < <>
S1 > S2 ON ON OFF OFF OFF ON
S1 = S2 OFF ON ON ON OFF OFF
S1 < S2 OFF OFF OFF ON ON ON

Using CMP(020) Results in the Program

When CMP(020) is executed, the result is reflected in the Arithmetic Flags.
Control the desired output or right-hand instruction with a branch from the
same input condition that controls CMP(020), as shown in the following dia-
gram. In this case, the Equals Flag and output A will be turned ON when S1 =
S 2.
Correct Use of CMP(020)
CMP
S1
S2

Arithmetic Flag
(Example: Equal Flag)
A

Using CMP(020) Results in the Program

Do not program another instruction between CMP(020) and the instruction
controlled by the Arithmetic Flag because the other instruction might change
the status of the Arithmetic Flag. In this case, the results of instruction B might
change the results of CMP(020).

304
Comparison Instructions Section 3-7

Incorrect Use of CMP(020)

CMP
S1
S2

Instruction
B

Arithmetic Flag
(Example: Equal Flag)
A

The immediate-refreshing variation (!CMP(020)) can be used with words allo-

cated to external inputs specified in S1 and/or S2. When !CMP(020) is exe-
cuted, input refreshing will be performed for the external input word specified
in S1 and/or S2 and that refreshed value will be compared. (Immediate
refreshing cannot be performed on inputs allocated to Group-2 High-density
I/O Units or Units mounted to Slave Racks.)
Flags
Name CX-Programmer Programming Operation
label Console label
Error Flag P_ER ER Unchanged (See note.)
Greater Than Flag P_GT > ON if S1 > S2.
OFF in all other cases.
Greater Than or Equal Flag P_GE >= ON if S1 ≥ S2.
OFF in all other cases.
Equal Flag P_EQ = ON if S1 = S2.
OFF in all other cases.
Not Equal Flag P_NE = ON if S1 ≠ S2.
OFF in all other cases.
Less Than Flag P_LT < ON if S1 < S2.
OFF in all other cases.
Less Than or Equal Flag P_LE <= ON if S1 ≤ S2.
OFF in all other cases.
Negative Flag P_N N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these Flags are turned OFF.

Precautions Do not program another instruction between CMP(020) and an input condition
that accesses the result of CMP(020) because the other instruction might
change the status of the Arithmetic Flags.

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Comparison Instructions Section 3-7

3-7-4 DOUBLE COMPARE: CMPL(060)

Purpose Compares two double unsigned binary values (constants and/or the contents
of specified words) and outputs the result to the Arithmetic Flags in the Auxil-
iary Area.
Ladder Symbol
CMPL(060)

S1 S1: Comparison data 1

S2 S2: Comparison data 2

Variations
Variations Executed Each Cycle for ON Condition CMPL(060)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S1 S2
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF
(binary)
Data Registers ---
Index Registers IR0 to IR15
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

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Comparison Instructions Section 3-7

Description CMPL(060) compares the unsigned binary data in S1 +1, S1 and S2+1, S2
and outputs the result to Arithmetic Flags (the Greater Than, Greater Than or
Equal, Equal, Less Than or Equal, Less Than, and Not Equal Flags) in the
Auxiliary Area.
Unsigned binary
comparison
S2+1

Arithmetic Flags
(>, >=, =, <=, <, <>)

Arithmetic Flag Status

The following table shows the status of the Arithmetic Flags after execution of
CMPL(060). (A status of “---” indicates that the Flag may be ON or OFF.)
CMPL(060)Result Flag status
> >= = <= < <>
S1 +1, S1 > S2+1, S2 ON ON OFF OFF OFF ON
S1+1, S1 = S2+1, S2 OFF ON ON ON OFF OFF
S1+1, S1 < S2+1, S2 OFF OFF OFF ON ON ON

Using CMPL(060) Results in the Program

When CMPL(060) is executed, the result is reflected in the Arithmetic Flags.
Control the desired output or right-hand instruction with a branch from the
same input condition that controls CMPL(060), as shown in the following dia-
gram. Here, the Equals Flag and output A will be turned ON when S1 +1, S1 =
S2+1, S2.
Correct Use of CMPL(060)
CMPL
S1
S2

Arithmetic Flag
(Example: Equal Flag)
A

Using CMPL(060) Results in the Program

Do not program another instruction between CMPL(060) and the instruction
controlled by the Arithmetic Flag because the other instruction might change
the status of the Arithmetic Flag. In this case, the results of instruction B might
change the results of CMPL(060).

307
Comparison Instructions Section 3-7

Incorrect Use of CMPL(060)

CMPL
S1
S2

Instruction
B

Arithmetic Flag
(Example: Equals Flag)
A

Flags
Name CX-Programmer Programming Operation
label Console label
Error Flag P_ER ER Unchanged (See note.)
Greater Than Flag P_GT > ON if S1 +1, S1 > S2+1, S2.
OFF in all other cases.
Greater Than or Equal Flag P_GE >= ON if S1 +1, S1 ≥ S2+1, S2.
OFF in all other cases.
Equal Flag P_EQ = ON if S1 +1, S1 = S2+1, S2.
OFF in all other cases.
Not Equal Flag P_NE <> ON if S1 +1, S1 ≠ S2+1, S2.
OFF in all other cases.
Less Than Flag P_LT < ON if S1 +1, S1 < S2+1, S2.
OFF in all other cases.
Less Than or Equal Flag P_LE <= ON if S1 +1, S1 ≤ S2+1, S2.
OFF in all other cases.
Negative Flag P_N N Unchanged (See note.)
Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these Flags are turned OFF.

Precautions Do not program another instruction between CMPL(060) and an input condi-
tion that accesses the result of CMPL(060) because the other instruction
might change the status of the Arithmetic Flags.

Example When CIO 000000 is ON in the following example, the eight-digit unsigned
binary data in CIO 0011 and CIO 0010 is compared to the eight-digit
unsigned binary data in CIO 0009 and CIO 0008 and the result is output to
the Arithmetic Flags. The results recorded in the Greater Than, Equals, and
Less Than Flags are immediately saved to CIO 000200 (Greater Than),
CIO 000201 (Equals), and CIO 000202 (Less Than).

308
Comparison Instructions Section 3-7

Flag status
Result > (0)
Comparison = (0)
< (1)

3-7-5 SIGNED BINARY COMPARE: CPS(114)

Purpose Compares two signed binary values (constants and/or the contents of speci-
fied words) and outputs the result to the Arithmetic Flags in the Auxiliary Area.

Ladder Symbol
CPS(114)

S1 S1: Comparison data 1

S2 S2: Comparison data 2

Variations
Variations Executed Each Cycle for ON Condition CPS(114)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification (See note.) !CPS(114)

Note Immediate refreshing is not supported by CS1D CPU Units.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S1 S2
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)

309
Comparison Instructions Section 3-7

Area S1 S2
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description CPS(114) compares the signed binary data in S1 and S2 and outputs the
result to Arithmetic Flags (the Greater Than, Greater Than or Equal, Equal,
Less Than or Equal, Less Than, and Not Equal Flags) in the Auxiliary Area.
Signed binary
comparison

Arithmetic Flags
(>, >=, =, <=, <, <>)

Note CPS(114) treats the data in S1 and S2 as signed binary data which ranges
from 8000 to 7FFF (–32,768 to 32,767 decimal).
Arithmetic Flag Status
The following table shows the status of the Arithmetic Flags after execution of
CPS(114). (A status of “---” indicates that the Flag may be ON or OFF.)
CPS(114) Flag status
Result > >= = <= < <>
S1 > S2 ON ON OFF OFF OFF ON
S1 = S2 OFF ON ON ON OFF OFF
S1 < S2 OFF OFF OFF ON ON ON

Using CPS(114) Results in the Program

When CPS(114) is executed, the result is reflected in the Arithmetic Flags.
Control the desired output or right-hand instruction with a branch from the
same input condition that controls CPS(114), as shown in the following dia-
gram. In this case, the Equals Flag and output A will be turned ON when S1 =
S 2.
Correct Use of CPS(114)

CPS
S1
S2

Arithmetic Flag
(Example: Equal Flag)
A

310
Comparison Instructions Section 3-7

Using CPS(114) Results in the Program

Do not program another instruction between CPS(114) and the instruction
controlled by the Arithmetic Flag because the other instruction might change
the status of the Arithmetic Flag. In this case, the results of instruction B might
change the results of CPS(114).
Incorrect Use of CPS(114)
CPS
S1
S2

Instruction
B

Arithmetic Flag
(Example: Equal Flag)
A

The immediate-refreshing variation (!CPS(114)) can be used with words allo-

cated to external inputs specified in S1 and/or S2. When !CPS(114) is exe-
cuted, input refreshing will be performed for the external input word specified
in S1 and/or S2 and that refreshed value will be compared. (Immediate
refreshing cannot be performed on inputs allocated to Group-2 High-density
I/O Units or Units mounted to Slave Racks.)

Flags
Name Label Operation
Error Flag ER Unchanged (See note.)
Greater Than Flag > ON if S1 > S2.
OFF in all other cases.
Greater Than or Equal Flag >= ON if S1 ≥ S2.
OFF in all other cases.
Equal Flag = ON if S1 = S2.
OFF in all other cases.
Not Equal Flag <> ON if S1 ≠ S2.
OFF in all other cases.
Less Than Flag < ON if S1 < S2.
OFF in all other cases.
Less Than or Equal Flag <= ON if S1 ≤ S2.
OFF in all other cases.
Negative Flag N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these Flags are turned OFF.

Precautions Do not program another instruction between CPS(114) and an input condition
that accesses the result of CPS(114) because the other instruction might
change the status of the Arithmetic Flags.

311
Comparison Instructions Section 3-7

3-7-6 DOUBLE SIGNED BINARY COMPARE: CPSL(115)

Purpose Compares two double signed binary values (constants and/or the contents of
specified words) and outputs the result to the Arithmetic Flags in the Auxiliary
Area.
Ladder Symbol
CPSL(115)

S1 S1: Comparison data 1

S2 S2: Comparison data 2

Variations
Variations Executed Each Cycle for ON Condition CPSL(115)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S1 S2
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF
(binary)
Data Registers ---
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

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Comparison Instructions Section 3-7

Description CPSL(115) compares the double signed binary data in S1 +1, S1 and S2+1,
S2 and outputs the result to Arithmetic Flags (the Greater Than, Greater Than
or Equal, Equal, Less Than or Equal, Less Than, and Not Equal Flags) in the
Auxiliary Area.
Signed binary
comparison
S2+1

Arithmetic Flags
(>, >=, =, <=, <, <>)

Note CPSL(115) treats the data in S1 and S2 as double signed binary data which
ranges from 8000 0000 to 7FFF FFFF (–2,147,483,648 to 2,147,483,647 dec-
imal).
Arithmetic Flag Status
The following table shows the status of the Arithmetic Flags after execution of
CPSL(115). (A status of “---” indicates that the Flag may be ON or OFF.)
CPSL(115)Result Flag status
> >= = <= < <>
S1 +1, S1 > S2+1, S2 ON ON OFF OFF OFF ON
S1+1, S1 = S2+1, S2 OFF ON ON ON OFF OFF
S1+1, S1 < S2+1, S2 OFF OFF OFF ON ON ON

Using CPSL(115) Results in the Program

When CPSL(115) is executed, the result is reflected in the Arithmetic Flags.
Control the desired output or right-hand instruction with a branch from the
same input condition that controls CPSL(115), as shown in the following dia-
gram. Here, the Equals Flag and output A will be turned ON when S1 +1, S1 =
S2+1, S2.
Correct Use of CPSL(115)

CPSL
S1
S2

Arithmetic Flag
(Example: Equal Flag)
A

Using CPSL(115) Results in the Program

Do not program another instruction between CPSL(115) and the instruction
controlled by the Arithmetic Flag because the other instruction might change
the status of the Arithmetic Flag. In this case, the results of instruction B might
change the results of CPSL(115).

313
Comparison Instructions Section 3-7

Incorrect Use of CPSL(115)

CPSL
S1
S2

Instruction
B

Arithmetic Flag
(Example: Equal Flag)
A

Flags
Name Label Operation
Error Flag ER OFF or unchanged (See note.)
Greater Than Flag > ON if S1 +1, S1 > S2+1, S2.
OFF in all other cases.
Greater Than or Equal Flag >= ON if S1 +1, S1 ≥ S2+1, S2.
OFF in all other cases.
Equal Flag = ON if S1 +1, S1 = S2+1, S2.
OFF in all other cases.
Not Equal Flag = ON if S1 +1, S1 ≠ S2+1, S2.
OFF in all other cases.
Less Than Flag < ON if S1 +1, S1 < S2+1, S2.
OFF in all other cases.
Less Than or Equal Flag <= ON if S1 +1, S1 ≤ S2+1, S2.
OFF in all other cases.
Negative Flag N OFF or unchanged (See note.)

Note In CS1 and CJ1 CPU Units, these Flags are turned OFF.
In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, these Flags are left
unchanged.

Precautions Do not program another instruction between CPSL(115) and an input condi-
tion that accesses the result of CPSL(115) because the other instruction
might change the status of the Arithmetic Flags.

Example When CIO 000000 is ON in the following example, the eight-digit signed
binary data in D00002 and D00001 is compared to the eight-digit signed
binary data in D00006 and D00005 and the result is output to the Arithmetic
Flags.
• If the content of D00002 and D00001 is greater than that of D00006 and
D00005, the Greater Than Flag will be turned ON, causing CIO 002000 to
be turned ON.
• If the content of D00002 and D00001 is equal to that of D00006 and
D00005, the Equals Flag will be turned ON, causing CIO 002001 to be
turned ON.
• If the content of D00002 and D00001 is less than that of D00006 and
D00005, the Less Than Flag will be turned ON, causing CIO 002002 to
be turned ON.

314
Comparison Instructions Section 3-7

Flag status
1234 5678 > (1)
D0001 = (0)
D0005 Comparison
< (0)

ABCD EF12

3-7-7 MULTIPLE COMPARE: MCMP(019)

Purpose Compares 16 consecutive words with another 16 consecutive words and
turns ON the corresponding bit in the result word where the contents of the
words are not equal.

Ladder Symbol
MCMP(019)

S1 S1: First word of set 1

S2 S2: First word of set 2

R R: Result word
Variations
Variations Executed Each Cycle for ON Condition MCMP(019)
Executed Once for Upward Differentiation @MCMP(019)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands S1: First word of set 1

Specifies the beginning of the first 16-word range. S1 and S1+15 must be in
the same data area.
S2: First word of set 2
Specifies the beginning of the second 16-word range. S2 and S2+15 must be
in the same data area.
R: Result word
Each bit of R contains the result of a comparison between two words in the
16-word sets. Bit n of R (n = 00 to 15) contains the result of the comparison
between words S1+n and S2+n.
15 14 1 0
R
Comparison result for S1 and S2
Comparison result for S1+1 and S2+1
Comparison result for S1+14 and S2+14
Comparison result for S1+15 and S2+15

315
Comparison Instructions Section 3-7

Operand Specifications
Area S1 S2 R
CIO Area CIO 0000 to CIO 6128 CIO 0000 to
CIO 6143
Work Area W000 to W496 W000 to W511
Holding Bit Area H000 to H496 H000 to H511
Auxiliary Bit Area A000 to A944 A448 to A959
Timer Area T0000 to T4080 T0000 to T4095
Counter Area C0000 to C4080 C0000 to C4095
DM Area D00000 to D32752 D00000 to
D32767
EM Area without bank E00000 to E32752 E00000 to
E32767
EM Area with bank En_00000 to 32752 En_00000 to
(n = 0 to C) En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description MCMP(019) compares the contents of the 16 words S1 through S1+15 to the
contents of the 16 words S2 through S2+15, and turns ON the corresponding
bit in word R when the contents are not equal.
The content of S1 is compared to the content of S2, the content of S1+1 to the
content of S2+1, ..., and the content of S1+15 to the content of S2+15. Bit n of
R is turned OFF if the content of S1+n is equal to the content of S2+n; bit n of
R is turned ON if the contents are not equal. If the contents of all 16 pairs of
words are the same, the Equals Flag will turn ON after the instruction has
been executed.
Comparison R
0: Words are equal.
1: Words aren't equal.

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Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result word is 0000.
(The two 16-word sets contain the same data.)
OFF in all other cases.

Example When CIO 000000 is ON in the following example, MCMP(019) compares

words D00100 through D00115 in order to words D00200 through D00215
and turns ON the corresponding bits in D00300 when the words are not
equal.

R: D00300

S1: S2:

3-7-8 TABLE COMPARE: TCMP(085)

Purpose Compares the source data to the contents of 16 consecutive words and turns
ON the corresponding bit in the result word when the contents of the words
are equal.

Ladder Symbol
TCMP(085)

S S: Source data

T T: First word of table

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition TCMP(085)
Executed Once for Upward Differentiation @TCMP(085)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

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Comparison Instructions Section 3-7

Operands T: First word of table

Specifies the beginning of the 16-word table. T and T+15 must be in the same
data area.
R: Result word
Each bit of R contains the result of a comparison between S and a word in the
16-word table. Bit n of R (n = 00 to 15) contains the result of the comparison
between S and T+n.
Comparison data 0
Comparison data 1
to to
Comparison data 15

15 14 1 0
R
Comparison result for S and T
Comparison result for S and T+1
Comparison result for S and T+14
Comparison result for S and T+15
Operand Specifications
Area S T R
CIO Area CIO 0000 to CIO 0000 to CIO 0000 to
CIO 6143 CIO 6128 CIO 6143
Work Area W000 to W511 W000 to W496 W000 to W511
Holding Bit Area H000 to H511 H000 to H496 H000 to H511
Auxiliary Bit Area A000 to A959 A000 to A944 A448 to A959
Timer Area T0000 to T4095 T0000 to T4080 T0000 to T4095
Counter Area C0000 to C4095 C0000 to C4080 C0000 to C4095
DM Area D00000 to D00000 to D00000 to
D32767 D32752 D32767
EM Area without bank E00000 to E00000 to E00000 to
E32767 E32752 E32767
EM Area with bank En_00000 to En_00000 to En_00000 to
En_32767 En_32752 En_32767
(n = 0 to C) (n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15 --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

318
Comparison Instructions Section 3-7

Description TCMP(085) compares the source data (S) to each of the 16 words T through
T+15 and turns ON the corresponding bit in word R when the data are equal.
Bit n of R is turned ON if the content of T+n is equal to S and it is turned OFF
if they are not equal.
S is compared to the content of T and bit 00 of R is turned ON if they are
equal or OFF if they are not equal, S is compared to the content of T+1 and bit
01 of R is turned ON if they are equal or OFF if they are not equal, ..., and S is
compared to the content of T+15 and bit 15 of R is turned ON if they are equal
or OFF if they are not equal.
Comparison R
1: Data are equal.
0: Data aren't equal.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result word is 0000.
(None of the 16 words in the table equals S.)
OFF in all other cases.

Example When CIO 000000 is ON in the following example, TCMP(085) compares the
content of D00100 with the contents of words D00200 through D00215 and
turns ON the corresponding bits in D00300 when the contents are equal or
OFF when the contents are not equal.
R: D00300

S: D00100 T:

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Comparison Instructions Section 3-7

3-7-9 BLOCK COMPARE: BCMP(068)

Purpose Compares the source data to 16 ranges (defined by 16 lower limits and 16
upper limits) and turns ON the corresponding bit in the result word when the
source data is within a range.
Ladder Symbol
BCMP(068)

S S: Source data

B B: First word of block

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition BCMP(068)
Executed Once for Upward Differentiation @BCMP(068)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands B: First word of block

Specifies the beginning of a 32-word block (16 lower/upper limit pairs). B and
B+31 must be in the same data area.
R: Result word
Each bit of R contains the result of a comparison between S and one of the 16
ranges defined the 32-word block. Bit n of R (n = 00 to 15) contains the result
of the comparison between S and the nth pair of words.
15 14 1 0
R
Comparison result for S
and range B ↔ B+1
Comparison result for S
Comparison result for S and range B+2 ↔ B+3
and range B+28 ↔ B+29
Comparison result for S
and range B+30 ↔ B+31

Operand Specifications
Area S B R
CIO Area CIO 0000 to CIO 0000 to CIO 0000 to
CIO 6143 CIO 6112 CIO 6143
Work Area W000 to W511 W0000 to W480 W000 to W511
Holding Bit Area H000 to H511 H000 to H480 H000 to H511
Auxiliary Bit Area A000 to A959 A000 to A928 A448 to A959
Timer Area T0000 to T4095 T0000 to T4064 T0000 to T4095
Counter Area C0000 to C4095 C0000 to C4064 C0000 to C4095
DM Area D00000 to D00000 to D00000 to
D32767 D32736 D32767
EM Area without bank E00000 to E00000 to E00000 to
E32767 E32736 E32767

320
Comparison Instructions Section 3-7

Area S B R
EM Area with bank En_00000 to En_00000 to En_00000 to
En_32767 En_32736 En_32767
(n = 0 to C) (n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15 --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BCMP(068) compares the source data (S) to the 16 ranges defined by pairs
of lower and upper limit values in B through B+31. The first word in each pair
(B+2n) provides the lower limit and the second word (B+2n+1) provides the
upper limit of range n (n = 0 to 15). If S is within any of these ranges (inclusive
of the upper and lower limits), the corresponding bit in R is turned ON. The
rest of the bits in R will be turned OFF.
B ≤S≤ B+1 Bit 00 of R
B+2 ≤S≤ B+3 Bit 01 of R
B+4 ≤S≤ B+5 Bit 02 of R
B+6 ≤S≤ B+7 Bit 03 of R
B+8 ≤S≤ B+9 Bit 04 of R
B+10 ≤S≤ B+11 Bit 05 of R
B+12 ≤S≤ B+13 Bit 06 of R
B+14 ≤S≤ B+15 Bit 07 of R
B+16 ≤S≤ B+17 Bit 08 of R
B+18 ≤S≤ B+19 Bit 09 of R
B+20 ≤S≤ B+21 Bit 10 of R
B+22 ≤S≤ B+23 Bit 11 of R
B+24 ≤S≤ B+25 Bit 12 of R
B+26 ≤S≤ B+27 Bit 13 of R
B+28 ≤S≤ B+29 Bit 14 of R
B+30 ≤S≤ B+31 Bit 15 of R

For example, bit 00 of R is turned ON if S is within the first range (B ≤ S ≤

B+1), bit 01 of R is turned ON if S is within the second range (B+2 ≤ S ≤ B+3),
..., and bit 15 of R is turned ON if S is within the fifteenth range (B+30 ≤ S ≤
B+31). All other bits in R are turned OFF.

321
Comparison Instructions Section 3-7

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result word is 0000.
(S is not within any of the 16 ranges.)
OFF in all other cases.

Precautions An error will not occur if the lower limit is greater than the upper limit, but 0
(not within the range) will be output to the corresponding bit of R.

Example When CIO 000000 is ON in the following example, BCMP(068) compares the
content of D00100 with the 16 ranges defined in D00200 through D00231 and
turns ON the corresponding bits in D00300 when S is within the range or OFF
when S is not within the range.

R: D00300

S: D00100 to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to

3-7-10 EXPANDED BLOCK COMPARE: BCMP2(502)

Purpose Compares the source data to up to 256 ranges (defined by 256 lower limits
and 256 upper limits) and turns ON the corresponding bit in the result word
when the source data is within a range. BCMP2(502) is supported only by the
CS1-H, CJ1-H, and CS1D CPU Unit Ver. 2.0 or later, and CJ1M CPU Unit
(Pre-Ver. 2.0 or Unit Ver. 2.0 or later).

Ladder Symbol
BCMP2(502)

S S: Source data

B B: First word of block

R R: First result word

322
Comparison Instructions Section 3-7

Variations
Variations Executed Each Cycle for ON Condition BCMP2(502)
Executed Once for Upward Differentiation @BCMP2(502)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands B: First word of block

Specifies the beginning of a comparison block containing up to 513 words
including up to 256 lower/upper limit pairs). All words must be in the same
data area.
Comparison block
Word 15 8 7 0
00 hex Last range "N" N: 00 to FF hex
B (0 to 255)
Range 0 B+1 Range 0 value A
B+2 Range 0 value B
Range 1 B+3 Range 1 value A
B+4 Range 1 value B
Range 2 B+5 Range 2 value A
B+6 Range 2 value B

Range Range 15 B+31 Range 15 value A

data
B+32 Range 15 value B
Range 16 B+33 Range 16 value A
B+34 Range 16 value B
Range 17 B+35 Range 17 value A
B+36 Range 17 value B
Range 18 B+37 Range 18 value A
B+38 Range 18 value B

Range N B+2N+1 Range N value A

B+2(N+1) Range N value B

R: First result word

Each bit of each R word contains the result of a comparison between S and
one of the ranges defined the comparison block. The maximum number of
result words is 16, i.e., m equals 0 to 15.
15 14 n 0
R+m
Comparison result for
S and range 15m
Comparison result for
Comparison result for S and range 15m + n
S and range 15m + 14
Comparison result for
S and range 15m + 15

323
Comparison Instructions Section 3-7

Operand Specifications
Area S B R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM @ D00000 to @ D32767
addresses in binary
Indirect DM/EM *D00000 to *D32767
addresses in BCD
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BCMP2(502) compares the source data (S) to the ranges defined by pairs of
lower and upper limit values in the comparison block. If S is within any of
these ranges (inclusive of the upper and lower limits), the corresponding bits
in the result words (R to R+15 max.) are turned ON. The rest of the bits in R
will be turned OFF.
The number of ranges is determined by the value N set in the lower byte of B.
N can be between 0 and 255. The upper byte of B must be 00 hex.
Comparison block
15 87 0
Last range N: 00 to FF hex (0 to 255)
B 00 hex "N"
Result words
Comparison ranges R Bit
B+1 Range 0 value A Range 0 value B B+2 0
B+3 Range 1 value A Range 1 value B B+4 1
Source data
B+5 Range 2 value A Range 2 value B B+6 2
S
: :
B+31 Range 15 value A Range 15 value B B+32 15
R+1 Bit
B+33 Range 16 value A Range 16 value B B+34 0
B+35 Range 17 value A Range 17 value B B+36 1
B+37 Range 18 value A Range 18 value B B+38 2
: :
B+2N+1 Range N value A Range N value B B+2N+2
In range: ON
Ranges
Not in range: OFF

Number of Ranges
The number of ranges in the comparison block is set in the first word of the
block. Up to 256 ranges can be set.

324
Comparison Instructions Section 3-7

Setting Ranges
The values A and B for each range will determine how the comparison oper-
ates depending on which value is larger, as shown below.
· If Value A ≤ Value B
Then, Value A ≤ Comparison range ≤ Value B

Comparison range

Value A Value B

· If Value A > Value B

Then, Comparison range ≤ Value B and Value A ≤ Comparison range

Comparison Comparison
range range

Value B Value A

Example
When B+1 ≤ B+2
If B+1 ≤ S ≤ B+2, then bit 0 of R will turn ON,
If B+3 ≤ S ≤ B+4, then bit 1 of R will turn ON,
If S < B+5 and B+6 < S, then bit 2 of R will turn OFF, and
If S < B+7 and B+8 < S, then bit 3 of R will turn OFF.
When B+1 > B+2
If S ≤ B+2 and B+1 ≤ S, then bit 0 of R will turn ON,
If S ≤ B+4 and B+3 ≤ S, then bit 1 of R will turn ON,
If B+6 < S < B+5, then bit 2 of R will turn OFF, and
If B+8 < S < B+7, then bit 3 of R will turn OFF.
Results Storage Location
The results are output to corresponding bits in word R. If there are more than
16 comparison ranges, consecutive words following R will be used. The maxi-
mum number of result words is 16, i.e., m equals 0 to 15.
15 14 n 0
R+m
Comparison result for
S and range 15m
Comparison result for
Comparison result for S and range 15m + n
S and range 15m + 14
Comparison result for
S and range 15m + 15

Flags
Name Label Operation
Error Flag ER OFF

Example When CIO 000000 is ON in the following example, BCMP2(502) compares

the content of CIO 0010 with the 24 ranges defined in D00200 through
D00247 (N = 17 hex = 23 decimal, i.e., 24 ranges) and turns ON the corre-
sponding bits in CIO 0100 and CIO 0101 when S is within the range and OFF
when S is not within the range. For example, if the source data in CIO 0010 is
in the range defined by D00201 and D00202, then bit 00 of CIO 0100 is
turned ON and if it in not in the range, then bit 00 of CIO 0100 is turned OFF.
Likewise, the source data in CIO 0010 is compared to the ranges defined by
D00203 and D00204, D00247 and D00248, and the other words in the com-

325
Comparison Instructions Section 3-7

parison block, and bit 1 in CIO 0100, bit 7 in CIO 1010, and the other bits in
the result words are manipulated according to the results of comparison.
000000 0 0 1 7
R: CIO 0100
BCMP2 Bit
0010 S: CIO 0010 0 1 7 5 D00201 0 0 0 0 0 1 0 0 D00202
D00200 D00203 0 0 8 0 0 1 8 0 D00204
0100 D00205 0 1 6 0 0 2 6 0 D00206

D00231 1 2 0 0 1 8 0 0 D00232
R: CIO 0101
D00233 1 5 0 0 0 5 0 0 D00234
D00235 1 9 0 0 0 1 0 0 D00236
D00237 1 8 0 0 0 2 0 0 D00238

D00247 0 1 0 0 2 0 0 0 D00248

3-7-11 AREA RANGE COMPARE: ZCP(088)

Purpose Compares a 16-bit unsigned binary value (CD) with the range defined by
lower limit LL and upper limit UL. The results are output to the Arithmetic
Flags.
This instruction is supported by CS1-H, CJ1-H, CJ1M, and CS1D CPU Units
only.
Ladder Symbol

ZCP(088)
CD CD: Comparison Data
LL LL: Lower limit of range
UL UL: Upper limit of range
Variations
Variations Executed Each Cycle for ON Condition ZCP(088)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area CD LL UL
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767

326
Comparison Instructions Section 3-7

Area CD LL UL
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ZCP(088) compares the 16-bit signed binary data in CD with the range
defined by LL and UL and outputs the result to the Greater Than, Equals, and
Less Than Flags in the Auxiliary Area. (The Less Than or Equal, Greater
Than or Equal, and Not Equal Flags are left unchanged.)
Arithmetic Flag Status
The following table shows the status of the Arithmetic Flags after execution of
ZCP(088).
ZCP(088)Result Flag status
> = <
CD > UL ON OFF OFF
CD = UL OFF ON
LL < CD < UL
CD = LL
CD < LL OFF ON

Using ZCP(088) Results in the Program

When ZCP(088) is executed, the result is reflected in the Arithmetic Flags.
Control the desired output or right-hand instruction with a branch from the
same input condition that controls ZCP(088), as shown in the following dia-
gram. In this case, the Equals Flag and output A will be turned ON when
LL ≤ CD ≤ UL.

327
Comparison Instructions Section 3-7

Correct Use of ZCP(088)

ZCP
CD
LL
UL

Arithmetic Flag
(Example: Equal Flag)

Do not program another instruction between ZCP(088) and the instruction

controlled by the Arithmetic Flag because the other instruction might change
the status of the Arithmetic Flag. In this case, the results of instruction B might
change the results of ZCP(088).
Incorrect Use of ZCP(088)

ZCPL
CD
LL
UL

Instruction
B
A

Arithmetic Flag
(Example: Equal Flag)

Flags
Name Label Operation
Error Flag ER ON if LL > UL.
Greater Than Flag > ON if CD > UL.
OFF in all other cases.
Greater Than or Equal Flag >= Left unchanged.
Equal Flag = ON if LL ≤ CD ≤ UL.
OFF in all other cases.
Not Equal Flag <> Left unchanged.
Less Than Flag < ON if CD < LL.
OFF in all other cases.
Less Than or Equal Flag <= Left unchanged.
Negative Flag N Left unchanged.

Precautions Do not program another instruction between ZCP(088) and an input condition
that accesses the result of ZCP(088) because the other instruction might
change the status of the Arithmetic Flags.
Example When CIO 000000 is ON in the following example, the 16-bit unsigned binary
data in D00000 is compared to the range 0005 to 001F hex (5 to 31 decimal)
and the result is output to the Arithmetic Flags.
CIO 000200 is turned ON if 0005 hex ≤ content of D00000 ≤ 001F hex.
CIO 000201 is turned ON if the content of D00000 > 001F hex.
CIO 000202 is turned ON if the content of D00000 < 0005 hex.

328
Comparison Instructions Section 3-7

000000 LL CD UL Arithmetic
ZCP
D00000 Flags
CD D00000 0005Hex ≤ ≤ 001FHex = ON(1)
LL #0005
#001F D00000
UL
> 001FHex > ON(1)

002000 D00000
0005Hex > < ON(1)
=
002001

>
002002

<

3-7-12 DOUBLE AREA RANGE COMPARE: ZCPL(116)

Purpose Compares a 32-bit unsigned binary value (CD+1, CD) with the range defined
by lower limit (LL+1, LL) and upper limit (UL+1, UL). The results are output to
the Arithmetic Flags.
This instruction is supported by CS1-H, CJ1-H, CJ1M, and CS1D CPU Units
only.
Ladder Symbol

ZCPL(116)
CD CD: First word of Comparison Data
LL LL: First word of Lower Limit
UL UL: First word of Upper Limit
Variations
Variations Executed Each Cycle for ON Condition ZCP(088)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area CD LL UL
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)

329
Comparison Instructions Section 3-7

Area CD LL UL
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 0000 to #FFFF FFFF
(binary)
Data Registers ---
Index Registers IR0 to IR15
Indirect addressing using ,IR0 to ,IR15
Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ZCPL(116) compares the 32-bit signed binary data in CD+1, CD with the
range defined by LL+1, LL and UL+1, UL and outputs the result to the Greater
Than, Equals, and Less Than Flags in the Auxiliary Area. (The Less Than or
Equal, Greater Than or Equal, and Not Equal Flags are left unchanged.)
Arithmetic Flag Status
The following table shows the status of the Arithmetic Flags after execution of
ZCPL(116).
ZCPL(116)Result Flag status
> = <
CD+1, CD > UL+1, UL ON OFF OFF
CD+1, CD = UL+1, UL OFF ON
LL+1, LL < CD+1, CD < UL+1, UL
CD+1, CD = LL+1, LL
CD+1, CD < LL+1, LL OFF ON

Using ZCPL(116) Results in the Program

When ZCPL(116) is executed, the result is reflected in the Arithmetic Flags.
Control the desired output or right-hand instruction with a branch from the
same input condition that controls ZCPL(116).
Do not program another instruction between ZCPL(116) and the instruction
controlled by the Arithmetic Flag because the other instruction might change
the status of the Arithmetic Flag.
The operation of ZCPL(116) is almost identical to that of ZCP(088) except that
ZCPL(116) compares 32-bit values instead of 16-bit values. Refer to 3-7-11
AREA RANGE COMPARE: ZCP(088) for diagrams showing how to use
results in the program and an example program section.

Flags
Name Label Operation
Error Flag ER ON if LL+1, LL > UL+1, UL.
Greater Than Flag > ON if CD > UL+1, UL.
OFF in all other cases.

330
Data Movement Instructions Section 3-8

Name Label Operation

Greater Than or Equal Flag >= Left unchanged.
Equal Flag = ON if LL+1, LL ≤ CD+1, CD ≤ UL+1, UL.
OFF in all other cases.
Not Equal Flag <> Left unchanged.
Less Than Flag < ON if CD+1, CD < LL+1, LL.
OFF in all other cases.
Less Than or Equal Flag <= Left unchanged.
Negative Flag N Left unchanged.

Precautions Do not program another instruction between ZCPL(116) and an input condi-
tion that accesses the result of ZCPL(116) because the other instruction
might change the status of the Arithmetic Flags.

3-8 Data Movement Instructions

3-8-1 MOVE: MOV(021)
Purpose Transfers a word of data to the specified word.

Ladder Symbol
MOV(021)

S S: Source

D D: Destination
Variations
Variations Executed Each Cycle for ON Condition MOV(021)
Executed Once for Upward Differentiation @MOV(021)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification (See note.) !MOV(021)
Combined Executed Once and Destination Refreshed !@MOV(021)
Variations Immediately for Upward Differentiation (See
note.)

Note Immediate refreshing is not supported by CS1D CPU Units.

Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)

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Area S D
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF (binary) ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description Transfers S to D. If S is a constant, the value can be used for a data setting.

Source word Bit status not Destination word

changed.

MOV(021) has an immediate refreshing variation (!MOV(021)). An external

input bits can be specified for S and external output bits can be specified for
D. Input bits used for S will refreshed just before, and output bits used for D
will be refreshed just after execution unless the bits are allocated to a Group-2
High-density I/O Unit, High-density Special I/O Unit, or a Unit mounted in a
SYSMAC BUS Remote I/O Slave Rack.
Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the data being transferred is 0000.
OFF in all other cases.
Negative Flag N ON if the leftmost bit of the data being transferred is 1.
OFF in all other cases.

Example When CIO 000000 is ON in the following example, the content of CIO 0100 is
copied to D00100.

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00001
MOV
#1234 15 12 11 8 7 4 3 0

D00010 D00010 1 2 3 4 (Hexadecimal 1234)

00002
MOV
+1234 15 12 11 8 7 4 3 0

D00011 D00011 0 4 D 2 (Decimal 1234)

00003
MOV
-1234 15 12 11 8 7 4 3 0

D00012 D00012 F B 2 E (Decimal -1234)

3-8-2 MOVE NOT: MVN(022)

Purpose Transfers the complement of a word of data to the specified word.

Ladder Symbol
MVN(022)

S S: Source

D D: Destination
Variations
Variations Executed Each Cycle for ON Condition MVN(022)
Executed Once for Upward Differentiation @MVN(022)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK
Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF (binary) ---
Data Registers DR0 to DR15

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Area S D
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description MVN(022) inverts the bits in S and transfers the result to D. The content of S
is left unchanged.

Source word Destination word

Bit status
inverted.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the content of D is 0000 after execution.
OFF in all other cases.
Negative Flag N ON if the leftmost bit of D is 1 after execution.
OFF in all other cases.

Example When CIO 000000 is ON in the following example, the status of the bits in
CIO 0100 is inverted and the result is copied to D00100.

3-8-3 DOUBLE MOVE: MOVL(498)

Purpose Transfers two words of data to the specified words.

Ladder Symbol
MOVL(498)

S S: First source word

D D: First destination word

Variations
Variations Executed Each Cycle for ON Condition MOVL(498)
Executed Once for Upward Differentiation @MOVL(498)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

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Data Movement Instructions Section 3-8

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers IR0 to IR15
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, 1–(– –) IR5

Description MOVL(498) transfers S+1 and S to D+1 and D. If S+1 and S are constants,
the value can be used for a data setting.
S S+1 D D+1

Bit status
not changed.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the contents of D+1 and D are 0000 0000 after exe-
cution.
OFF in all other cases.
Negative Flag N ON if the leftmost bit of D+1 is 1 after execution.
OFF in all other cases.

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Data Movement Instructions Section 3-8

Example When CIO 000000 is ON in the following example, the content of D00101 and
D00100 are copied to D00201 and D00200.

3-8-4 DOUBLE MOVE NOT: MVNL(499)

Purpose Transfers the complement of two words of data to the specified words.

Ladder Symbol
MVNL(499)

S S: First source word

D D: First destination word

Variations
Variations Executed Each Cycle for ON Condition MVNL(499)
Executed Once for Upward Differentiation @MVNL(499)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)

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Data Movement Instructions Section 3-8

Area S D
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description MVNL(499) inverts the bits in S+1 and S and transfers the result to D+1 and
D. The contents of S+1 and S are left unchanged.
S S+1 D D+1

Bit status
inverted.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the contents of D+1 and D are 0000 0000 after exe-
cution.
OFF in all other cases.
Negative Flag N ON if the leftmost bit of D+1 is 1 after execution.
OFF in all other cases.

Examples When CIO 000000 is ON in the following example, the status of the bits in
D00101 and D00100 are inverted and the result is copied to D00201 and
D00200. (The original contents of D00101 and D00100 are left unchanged.)

3-8-5 MOVE BIT: MOVB(082)

Purpose Transfers the specified bit.

Ladder Symbol
MOVB(082)

S S: Source word or data

C C: Control word

D D: Destination word

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Variations
Variations Executed Each Cycle for ON Condition MOVB(082)
Executed Once for Upward Differentiation @MOVB(082)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: Control Word

The rightmost two digits of C indicate which bit of S is the source bit and the
leftmost two digits of C indicate which bit of D is the destination bit.
15 8 7 0
C m n

Source bit: 00 to 0F
(0 to 15 decimal)
Destination bit: 00 to 0F
(0 to 15 decimal)

Operand Specifications
Area S C D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF Specified values ---
(binary) only
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

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Data Movement Instructions Section 3-8

Description MOVB(082) copies the specified bit (n) from S to the specified bit (m) in D.
The other bits in the destination word are left unchanged.

Note The same word can be specified for both S and D to copy a bit within a word.

Flags
Name Label Operation
Error Flag ER ON if the rightmost and leftmost two digits of C are not
within the specified range of 00 to 0F.
OFF in all other cases.

Examples When CIO 000000 is ON in the following example, the 5th bit of the source
word (CIO 0200) is copied to the 12th bit of the destination word (CIO 0300) in
accordance with the control word’s value of 0C05.

1 2 0 5

3-8-6 MOVE DIGIT: MOVD(083)

Purpose Transfers the specified digit or digits. (Each digit is made up of 4 bits.)

Ladder Symbol
MOVD(083)

S S: Source word or data

C C: Control word

D D: Destination word
Variations
Variations Executed Each Cycle for ON Condition MOVD(083)
Executed Once for Upward Differentiation @MOVD(083)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

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Data Movement Instructions Section 3-8

Operands S: Source Word

The source digits are read from right to left, wrapping back to the rightmost
digit (digit 0) if necessary.
15 12 11 8 7 4 3 0

S Digit 3 Digit 2 Digit 1 Digit 0

C: Control Word
The first three digits of C indicate the first source digit (m), the number of dig-
its to transfer (n), and the first destination digit (l), as shown in the following
diagram.
15 12 11 8 7 4 3 0
C 0 l n m

First digit in S (m): 0 to 3

Number of digits (n): 0 to 3

First digit in D (l): 0 to 3 0: 1 digit
1: 2 digits
2: 3 digits
3: 4 digits
Always 0.

D: Destination Word
The destination digits are written from right to left, wrapping back to the right-
most digit (digit 0) if necessary.
15 12 11 8 7 4 3 0

D Digit 3 Digit 2 Digit 1 Digit 0

Operand Specifications
Area S C D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF Specified values ---
(binary) only
Data Registers DR0 to DR15

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Data Movement Instructions Section 3-8

Area S C D
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description MOVD(083) copies the content of n digits from S (beginning at digit m) to D

(beginning at digit l). Only the specified digits are changed; the rest are left
unchanged.
If the number of digits being read or written exceeds the leftmost digit of S or
D, MOVD(083) will wrap to the rightmost digit of the same word.

Note The same word can be specified for both S and D to copy a bit within a word.

Flags
Name Label Operation
Error Flag ER ON if one of the first three digits of C is not within the
specified range of 0 to 3.
OFF in all other cases.

Examples Four-digit Transfer

When CIO 000000 is ON in the following example, four digits of data are cop-
ied from CIO 0200 to CIO 0300. The transfer begins with the digit 1 of
CIO 0200 and digit 0 or CIO 0300, in accordance with the control word’s value
of 0031.

First digit in S: Digit 1

Digit no.

Number of digits: 3 (4 digits)

Digit no.

First digit in D: Digit 0

Note After reading the leftmost digit of S (digit 3), MOVD(083) wraps to the right-
most digit (digit 0).

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Data Movement Instructions Section 3-8

Examples of C
The following diagram shows examples of data transfers for various values of
C.

Digit 0 Digit 0 Digit 0 Digit 0 Digit 0 Digit 0 Digit 0 Digit 0

Digit 1 Digit 1 Digit 1 Digit 1 Digit 1 Digit 1 Digit 1 Digit 1
Digit 2 Digit 2 Digit 2 Digit 2 Digit 2 Digit 2 Digit 2 Digit 2
Digit 3 Digit 3 Digit 3 Digit 3 Digit 3 Digit 3 Digit 3 Digit 3

3-8-7 MULTIPLE BIT TRANSFER: XFRB(062)

Purpose Transfers the specified number of consecutive bits.

Ladder Symbol
XFRB(062)

C C: Control word

S S: First source word

D D: First destination word

Variations
Variations Executed Each Cycle for ON Condition XFRB(062)
Executed Once for Upward Differentiation @XFRB(062)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: Control Word

The first three digits of C indicate the first destination bit (m), the number of
bits to transfer (n), and the first source digit (l), as shown in the following dia-
gram.
15 8 7 4 3 0
C n m l

First bit in S (ll): 0 to F

First bit in D (m): 0 to F

Number of bits (n):
00 to FF (0 to 255)

S: First Source Word

Specifies the first source word. Bits are read from right to left, continuing with
consecutive words (up to S+16) when necessary.
15 0
S

to to
S+16 max.

Note The source words must be in the same data area.

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Data Movement Instructions Section 3-8

D: First Destination Word

Specifies the first destination word. Bits are written from right to left, continu-
ing with consecutive words (up to D+16) when necessary.
15 0
D

to to
D+16 max.

Note The destination words must be in the same data area.

Operand Specifications
Area C S D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants Specified values --- ---
only
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to 5+(++)
,–(– –) IR0 to, –(– –) IR15

Description XFRB(062) transfers up to 255 consecutive bits from the source words (begin-
ning with bit l of S) to the destination words (beginning with bit m of D). Bits in
the destination words that are not overwritten by the source bits are left
unchanged.
The beginning bits and number of bits are specified in C, as shown in the fol-
lowing diagram.

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Data Movement Instructions Section 3-8

It is possible for the source words and destination words to overlap. By trans-
ferring data overlapping several words, the data can be packed more effi-
ciently in the data area. (This is particularly useful when handling position
data for position control.)
Since the source words and destination words can overlap, XFRB(062) can
be combined with ANDW(034) to shift m bits by n spaces.

Flags
Name Label Operation
Error Flag ER OFF

Precautions Up to 255 bits of data can be transferred per execution of XFRB(062).

Be sure that the source words and destination words do not exceed the end of
the data area.

Examples When CIO 000000 is ON in the following example, the 20 bits beginning with
CIO 020006 are copied to the 20 bits beginning with CIO 030000.

20 bits

3-8-8 BLOCK TRANSFER: XFER(070)

Purpose Transfers the specified number of consecutive words.

Ladder Symbol
XFER(070)

N N: Number of words

S S: First source word

D D: First destination word

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Variations
Variations Executed Each Cycle for ON Condition XFER(070)
Executed Once for Upward Differentiation @XFER(070)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands N: Number of Words

Specifies the number of words to be transferred. The possible range for N is
0000 to FFFF (0 to 65,535 decimal).
S: First Source Word
Specifies the first source word.
15 0
S

to to
S+(N−1)

D: First Destination Word

Specifies the first destination word.
15 0
D

to to
D+(N−1)

Operand Specifications
Area N S D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF --- ---
(binary) or &0 to
&65535
Data Registers DR0 to DR15 ---

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Data Movement Instructions Section 3-8

Area N S D
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description XFER(070) copies N words beginning with S (S to S+(N–1)) to the N words

beginning with D (D to D+(N–1)).

N words
to to
S+(N−1) D+
(N−1)

It is possible for the source words and destination words to overlap, so

XFER(070) can perform word-shift operations.

&10

Flags
Name Label Operation
Error Flag ER OFF

Precautions Be sure that the source words (S to S+N–1) and destination words (D to
D+N–1) do not exceed the end of the data area.
Some time will be required to complete XFER(070) when a large number of
words is being transferred. In this case, the XFER(070) transfer might not be
completed if a power interruption occurs during execution of the instruction.
Example When CIO 000000 is ON in the following example, the 10 words D00100
through D00109 are copied to D00200 through D00209.

&10

10
words

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Data Movement Instructions Section 3-8

3-8-9 BLOCK SET: BSET(071)

Purpose Copies the same word to a range of consecutive words.
Ladder Symbol
BSET(071)

S S: Source word

St St: Starting word

E E: End word

Variations
Variations Executed Each Cycle for ON Condition BSET(071)
Executed Once for Upward Differentiation @BSET(071)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands S: Source Word

Specifies the source data or the word containing the source data.
St: Starting Word
Specifies the first word in the destination range.
E: End Word
Specifies the last word in the destination range.

St

to

Source data Destination range

St

Note St and E must be in the same data area.

Operand Specifications
Area S St E
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767

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Data Movement Instructions Section 3-8

Area S St E
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, 15–(– –) IR

Description BSET(071) copies the same source word (S) to all of the destination words in
the range St to E.
Source word Destination words
St

Flags
Name Label Operation
Error Flag ER ON if St is greater than E.
OFF in all other cases.

Precautions Be sure that the starting word (St) and end word (E) are in the same data area
and that St ≤ E.
Some time will be required to complete BSET(071) when the source data is
being transferred to a large number of words. In this case, the BSET(071)
transfer might not be completed if a power interruption occurs during execu-
tion of the instruction.

Example When CIO 000000 is ON in the following example, the source data in D00100
is copied to D00200 through D00209.

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Data Movement Instructions Section 3-8

S
St
St:
E

E:

3-8-10 DATA EXCHANGE: XCHG(073)

Purpose Exchanges the contents of the two specified words.
Ladder Symbol
XCHG(073)

E1 E1: First exchange word

E2 E2: Second exchange word

Variations
Variations Executed Each Cycle for ON Condition XCHG(073)
Executed Once for Upward Differentiation @XCHG(073)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area E1 E2
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)

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Data Movement Instructions Section 3-8

Area E1 E2
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description XCHG(073) exchanges the contents of E1 and E2.

E1 E2

Flags
Name Label Operation
Error Flag ER Unchanged (See note.)
Equals Flag = Unchanged (See note.)
Negative Flag N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these Flags are turned OFF.

Example When CIO 000000 is ON in the following example, the content of D00100 is
exchanged with the content of D00200.

3-8-11 DOUBLE DATA EXCHANGE: XCGL(562)

Purpose Exchanges the contents of a pair of consecutive words with another pair of
consecutive words.

Ladder Symbol
XCGL(562)

E1 E1: First exchange word

E2 E2: Second exchange word

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Variations
Variations Executed Each Cycle for ON Condition XCGL(562)
Executed Once for Upward Differentiation @XCGL(562)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area E1 E2
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- ---
Data Registers ---
Index Registers IR0 to IR15
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

Description XCHG(073) exchanges the contents of E1+1 and E1 with the contents of
E2+1 and E2.
E1 E1+1 E2 E2+1

To exchange 3 or more words, use XFER(070) to transfer the words to a third

set of words (a buffer) as shown in the following diagram.

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Data Movement Instructions Section 3-8

E1 1st XFER(070)
operation
Buffer

2nd XFER(070)
operation

E2
3rd XFER(070)
operation

Flags
Name Label Operation
Error Flag ER Unchanged (See note.)
Equals Flag = Unchanged (See note.)
Negative Flag N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these Flags are turned OFF.

Example When CIO 000000 is ON in the following example, the contents of D00100
and D00101 are exchanged with the contents of D00200 and D00201.

3-8-12 SINGLE WORD DISTRIBUTE: DIST(080)

Purpose Transfers the source word to a destination word calculated by adding an offset
value to the base address.
Ladder Symbol
DIST(080)

S S: Source word

Bs Bs: Destination base address

Of Of: Offset

Variations
Variations Executed Each Cycle for ON Condition DIST(080)
Executed Once for Upward Differentiation @DIST(080)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

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Data Movement Instructions Section 3-8

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands Bs: Destination Base Address

Specifies the destination base address. The offset is added to this address to
calculate the destination word.
Of: Offset
This value is added to the base address to calculate the destination word. The
offset can be any value from 0000 to FFFF (0 to 65,535 decimal), but Bs and
Bs+Of must be in the same data area.
15 0

Bs
to
to
Bs+Of

Operand Specifications
Area S Bs Of
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959 A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF --- #0000 to #FFFF
(binary) (binary) or &0 to
&65535
Data Registers DR0 to DR15 --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

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Data Movement Instructions Section 3-8

Description DIST(080) copies S to the destination word calculated by adding Of to Bs.

The same DIST(080) instruction can be used to distribute the source word to
various words in the data area by changing the value of Of.

S Bs Of

Bs+n

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the source data is 0000.
OFF in all other cases.
Negative Flag N ON if the leftmost bit of the source data is 1.
OFF in all other cases.

Precautions Be sure that the offset does not exceed the end of the data area, i.e., Bs and
Bs+Of are in the same data area.

Example When CIO 000000 is ON in the following example, the contents of D00100 will
be copied to D00210 (D00200 + 10) if the contents of D00300 is 10 (0A hexa-
decimal). The contents of D00100 can be copied to other words by changing
the offset in D00300.

S: D00100
Copied by DIST(080).
S
Bs Of:
Bs: 0 0 0 A
Of
4-digit hexadecimal
Offset +10 words
D00210

3-8-13 DATA COLLECT: COLL(081)

Purpose Transfers the source word (calculated by adding an offset value to the base
address) to the destination word.

Ladder Symbol
COLL(081)

Bs Bs: Source base address

Of Of: Offset

D D: Destination word

Variations
Variations Executed Each Cycle for ON Condition COLL(081)
Executed Once for Upward Differentiation @COLL(081)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

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Data Movement Instructions Section 3-8

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands Bs: Source Base Address

Specifies the source base address. The offset is added to this address to cal-
culate the source word.
Of: Offset
This value is added to the base address to calculate the source word. The off-
set can be any value from 0000 to FFFF (0 to 65,535 decimal), but Bs and
Bs+Of must be in the same data area.
15 0

Bs

to to
Of

Operand Specifications
Area Bs Of D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- #0000 to #FFFF ---
(binary) or &0 to
&65535
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15

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Data Movement Instructions Section 3-8

Description COLL(081) copies the source word (calculated by adding Of to Bs) to the des-
tination word. The same COLL(081) instruction can be used to collect data
from various source words in the data area by changing the value of Of.

Bs Of

Bs+n

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the source data is 0000.
OFF in all other cases.
Negative Flag N ON if the leftmost bit of the source data is 1.
OFF in all other cases.

Precautions Be sure that the offset does not exceed the end of the data area, i.e., Bs and
Bs+Of are in the same data area.

Example When CIO 000000 is ON in the following example, the contents of D00110
(D00100 + 10) will be copied to D00300 if the content of D00200 is 10 (0A
hexadecimal). The contents of other words can be copied to D00300 by
changing the offset in D00200.

D00200 0 0 0 A
Bs: D00100
Bs 4-digit hexadecimal
D00101
Of
Offset +10 words
D
D00110 Copied by COLL(081).

3-8-14 MOVE TO REGISTER: MOVR(560)

Purpose Sets the PLC memory address of the specified word, bit, or timer/counter
Completion Flag in the specified Index Register. (Use MOVRW(561) to set the
PLC memory address of a timer/counter PV in an Index Register.)

Ladder Symbol
MOVR(560)

S S: Source (desired word or bit)

D D: Destination (Index Register)

Variations
Variations Executed Each Cycle for ON Condition MOVR(560)
Executed Once for Upward Differentiation @MOVR(560)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

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Data Movement Instructions Section 3-8

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands D: Destination
The destination must be an Index Register (IR0 to IR15).

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6143 ---
CIO 000000 to CIO 614315
Work Area W000 to W511 ---
W00000 to W51115
Holding Bit Area H000 to H511 ---
H00000 to H51115
Auxiliary Bit Area A000 to A447 ---
A448 to A959
A00000 to A44715
A44800 to A95915
Timer Area T0000 to T4095 ---
(Completion Flag)
Counter Area C0000 to C4095 ---
(Completion Flag)
Task Flag TK0000 to TK0031 ---
DM Area D00000 to D32767 ---
EM Area without bank E00000 to E32767 ---
EM Area with bank En_00000 to En_32767 ---
(n = 0 to C)
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers --- IR0 to IR15
Indirect addressing ---
using Index Registers

Description MOVR(560) finds the PLC memory address (absolute address) of S and
writes that address in D (an Index Register).
Internal I/O memory address of S

Index Register

If a timer or counter is specified in S, MOVR(560) will write the PLC memory

address of the timer/counter Completion Flag in D. Use MOVRW(561) to write
the PLC memory address of the timer/counter PV in D.

357
Data Movement Instructions Section 3-8

Flags
Name Label Operation
Error Flag ER Unchanged (See note.)
Equals Flag = Unchanged (See note.)
Negative Flag N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these Flags are turned OFF.

Precautions MOVR(560) cannot set the PLC memory addresses of timer/counter PVs.
Use MOVRW(561) to set the PLC memory addresses of timer/counter PVs.
The contents of an index register in an interrupt task is not predictable until it
is set. Be sure to set a register using MOVR(560) in an interrupt task before
using the register.
Any changes to the contents of an IR or DR made in an interrupt task will not
affect the contents of the register in a cyclic task.

Example When CIO 000000 is ON in the following example, MOVR(560) writes the
PLC memory address of CIO 0020 to IR0.
Internal I/O memory address
S: 0020 14

Internal I/O memory

address of CIO 0020

D: IR0 14

3-8-15 MOVE TIMER/COUNTER PV TO REGISTER: MOVRW(561)

Purpose Sets the PLC memory address of the specified timer or counter’s PV in the
specified Index Register. (Use MOVR(560) to set the PLC memory address of
a word, bit, or timer/counter Completion Flag in an Index Register.)

Ladder Symbol
MOVRW(561)

S S: Source (desired TC number)

D D: Destination (Index Register)

Variations
Variations Executed Each Cycle for ON Condition MOVR(561)
Executed Once for Upward Differentiation @MOVR(561)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands D: Destination
The destination must be an Index Register (IR0 to IR15).

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Data Movement Instructions Section 3-8

Operand Specifications
Area S D
CIO Area ---
Work Area ---
Holding Bit Area ---
Auxiliary Bit Area ---
Timer Area T0000 to T4095 ---
(present value)
Counter Area C0000 to C4095 ---
(present value)
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers --- IR0 to IR15
Indirect addressing ---
using Index Registers

Description MOVRW(561) finds the PLC memory address for the PV of the timer or
counter specified in S and writes that address in D (an Index Register).
Internal I/O memory address of S

Timer/counter PV only

Index Register

MOVRW(561) will set the PLC memory address of the timer or counter’s PV in
D. Use MOVR(560) to set the PLC memory address of the timer or counter
Completion Flag.

Flags
Name Label Operation
Error Flag ER Unchanged (See note.)
Equals Flag = Unchanged (See note.)
Negative Flag N Unchanged (See note.)

Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these Flags are turned OFF.

Precautions MOVRW(561) cannot set the PLC memory addresses of data area words,
bits, or timer/counter Completion Flags. Use MOVR(560) to set these PLC
memory addresses.

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Data Shift Instructions Section 3-9

Example When CIO 000000 is ON in the following example, MOVRW(561) writes the
PLC memory address for the PV of timer T0000 to IR1.
Internal I/O memory address
S:

3-9 Data Shift Instructions

This section describes instructions used to shift data within or between words,
but in differing amounts and directions.
Instruction Mnemonic Function code Page
SHIFT REGISTER SFT 010 361
REVERSIBLE SHIFT REGIS- SFTR 084 362
TER
ASYNCHRONOUS SHIFT ASFT 017 365
REGISTER
WORD SHIFT WSFT 016 368
ARITHMETIC SHIFT LEFT ASL 025 370
DOUBLE SHIFT LEFT ASLL 570 371
ARITHMETIC SHIFT RIGHT ASR 026 373
DOUBLE SHIFT RIGHT ASRL 571 374
ROTATE LEFT ROL 027 376
DOUBLE ROTATE LEFT ROLL 572 378
ROTATE LEFT WITHOUT RLNC 574 383
CARRY
DOUBLE ROTATE LEFT WITH- RLNL 576 385
OUT CARRY
ROTATE RIGHT ROR 028 380
DOUBLE ROTATE RIGHT RORL 573 381
ROTATE RIGHT WITHOUT RRNC 575 387
CARRY
DOUBLE ROTATE RIGHT RRNL 577 388
WITHOUT CARRY
ONE DIGIT SHIFT LEFT SLD 074 390
ONE DIGIT SHIFT RIGHT SRD 075 392
SHIFT N-BIT DATA LEFT NSFL 578 393
SHIFT N-BIT DATA RIGHT NSFR 579 395
SHIFT N-BITS LEFT NASL 580 397
DOUBLE SHIFT N-BITS LEFT NSLL 582 400
SHIFT N-BITS RIGHT NASR 581 403
DOUBLE SHIFT N-BITS NSRL 583 405
RIGHT

360
Data Shift Instructions Section 3-9

3-9-1 SHIFT REGISTER: SFT(010)

Purpose Operates a shift register.
Ladder Symbol
Data input SFT(010)

Shift input St St: Starting word

Reset input E E: End word

Variations
Variations Executed Each Cycle for ON Condition SFT(010)
Executed Once for Upward Differentiation Not supported
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
Not allowed OK OK OK

Note St and E must be in the same data area.

Operand Specifications
Area St E
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area ---
Counter Area ---
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM ---
addresses in binary
Indirect DM/EM ---
addresses in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15

361
Data Shift Instructions Section 3-9

Description When the execution condition on the shift input changes from OFF to ON, all
the data from St to E is shifted to the left by one bit (from the rightmost bit to
the leftmost bit), and the ON/OFF status of the data input is placed in the
rightmost bit.
E St+1, St+2, ... St

Lost
Status of data input
for each shift input

Flags
Name Label Operation
Error Flag ER ON if the indirect IR address for St and E is not in the CIO,
AR, HR, or WR data areas.
OFF in all other cases.

Precautions The results will not be predictable if two SFT(010) instructions are used with
overlapping shift registers. All words in the range ST to E must be used in only
one SFT(010) instruction.
The bit data shifted out of the shift register is discarded.
When the reset input turns ON, all bits in the shift register from the rightmost
designated word (St) to the leftmost designated word (E) will be reset (i.e., set
to 0). The reset input takes priority over other inputs.
St must be less than or equal to E, but even when St is set to greater than E
an error will not occur and one word of data in St will be shifted.
When St and E are designated indirectly using index registers and the actual
addresses in I/O memory are not within memory areas for data, an error will
occur and the Error Flag will turn ON.
Examples Shift Register Exceeding 16 Bits
The following example shows a 48-bit shift register using words CIO 0128 to
CIO 0130. A 1-s clock pulse is used so that the execution condition produced
by CIO 000005 is shifted into a 3-word register between CIO 012800 and
CIO 013015 every second.

Data input
E: CIO 0130 St+1: CIO 0129 St: CIO 0128 Contents of
CIO 000005
Shift input Lost
(1-s clock)
Reset

3-9-2 REVERSIBLE SHIFT REGISTER: SFTR(084)

Purpose Creates a shift register that shifts data to either the right or the left.

362
Data Shift Instructions Section 3-9

Ladder Symbol
SFTR(084)

C C: Control word

St St: Starting word

E E: End word

Variations
Variations Executed Each Cycle for ON Condition SFTR(084)
Executed Once for Upward Differentiation @SFTR(084)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: Control Word

15 14 13 12

Shift direction
1 (ON): Left
0 (OFF): Right

Data input

Shift input

Reset

Note St and E must be in the same data area.

Operand Specifications
Area C St E
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15 ---

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Data Shift Instructions Section 3-9

Area C St E
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description When the execution condition of the shift input bit (bit 14 of C) changes to ON,
all the data from St to E is moved in the designated shift direction (designated
by bit 12 of C) by 1 bit, and the ON/OFF status of the data input is placed in
the rightmost or leftmost bit. The bit data shifted out of the shift register is
placed in the Carry Flag (CY).

E St Data input

Data input E St Shift direction

Flags
Name Label Operation
Error Flag ER ON when St is greater than E.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into it.
OFF when 0 is shifted into it.
OFF when reset is set to 1.

Precautions The above shift operations are applicable when the reset bit (bit 15 of C) is set
to OFF.
When reset (bit 15 of C) turns ON all bits in the shift register, from St to E will
be reset (i.e., set to 0).
When St is greater than E, an error will be generated and the Error Flag will
turn ON.

Examples Shifting Data

If shift input CIO 030014 goes ON when CIO 000000 is ON, and the reset bit
CIO 030015 is OFF, words CIO 0100 through CIO 0102 will shift one bit in the
direction designated by CIO 030012 (e.g., 1: Right) and the contents of input
bit CIO 030013 will be shifted into the rightmost bit, CIO 010000. The con-
tents of CIO 010215 will be shifted to the Carry Flag (CY).

C
St C: 0300
E
Shift direction

Shift input bit: 1

Reset input bit: 0

Data input:
CIO 030013

364
Data Shift Instructions Section 3-9

Resetting Data
If CIO 030014 is ON when CIO 000000 is ON, and the reset bit, CIO 030015,
is ON, words CIO 0100 through CIO 0102 and the Carry Flag will be reset to
OFF.
Controlling Data
Resetting Data
All bits from St to E and the Carry Flag are set to 0 and no other data can be
received when the reset input bit (bit 15 of C) is ON.

Shifting Data Left (from Rightmost to Leftmost Bit)

When the shift input bit (bit 14 of C) is ON, the contents of the input bit (bit 13
of C) is shifted to bit 00 of the starting word, and each bit thereafter is shifted
one bit to the left. The status of bit 15 of the end word is shifted to the Carry
Flag.
Data
input

Shifting Data Right (from Leftmost to Rightmost Bit

When the shift input bit (bit 14 of C) is ON, the contents of the input bit (bit 13
of C) (I/O) is shifted to bit 15 on the end word, and each bit thereafter is
shifted one bit to the right. The status of bit 00 of the starting word is shifted to
the Carry Flag.
Data
input

3-9-3 ASYNCHRONOUS SHIFT REGISTER: ASFT(017)

Purpose Shifts all non-zero word data within the specified word range either towards St
or toward E, replacing 0000Hex word data.

Ladder Symbol
ASFT(017)

C C: Control word

St St: Starting word

E E: End word

Variations
Variations Executed Each Cycle for ON Condition ASFT(017)
Executed Once for Upward Differentiation @ASFT(017)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

365
Data Shift Instructions Section 3-9

Operands C: Control Word

15 14 13 12
Shift direction
0: Non-zero data shifted toward E
1: Non-zero data shifted toward St
Shift Enable Bit
0: Shift disabled
1: Shift enabled
Clear Bit
0: Data not reset
1: All data from St to E is reset

Note St and E must be in the same data area.

Operand Specifications
Area C St E
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description When the Shift Enable Bit (bit 14 of C) is ON, all of the words with non-zero
content within the range of words between St and E will be shifted one word in
the direction determined by the Shift Direction Bit (bit 13 of C) whenever the
word in the shift direction contains all zeros. If ASFT(017) is repeated suffi-
cient times, all all-zero words will be replaced by non-zero words. This will
result in all the data between St and E being divided into zero and non-zero
data.

366
Data Shift Instructions Section 3-9

St Shift direction

Convert Shift enabled

...
Clear
Convert

St

Non-zero data
...

Zero data
E

Note ASFT(017) can be processed in the background. Refer to the SYSMAC CS/
CJ/NSJ Series PLC Programming Manual (W394) for details.

Flags
Name Label Operation
Error Flag ER ON when St is greater than E.
ON if the Communications Port Enabled Flag for the com-
munications port number specified as the Com Port num-
ber for Background Execution is OFF when background
processing is specified.
OFF in all other cases.

Precautions When the Clear Flag (bit 15 of C) goes ON, all bits in the shift register, from St
to E, will be reset (i.e., set to 0). The Clear Flag has priority over the Shift
Enable Bit (bit 14 of C).
When St is greater than E an error will be generated and the Error Flag will
turn ON.

Examples Shifting Data:

If the Shift Enable Bit, CIO 030014, goes ON when CIO 000000 is ON, all
words with non-zero data content from CIO 0100 through CIO 0109 will be
shifted in the direction designated by the Shift Direction Bit, CIO 030013 (e.g.,
1: Toward St) if the word to the left of the non-zero data is all zeros.

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Data Shift Instructions Section 3-9

C
St
E C: 0300
Shift direction
1: Non-zero data shifted toward E
Shift Enable Bit: 1
Clear
Before ASFT(017) is executed After one execution After two executions
St:
Non-zero data is
shifted toward St

E:

3-9-4 WORD SHIFT: WSFT(016)

Purpose Shifts data between St and E in word units.
Ladder Symbol
WSFT(016)

S S: Source word

St St: Starting word

E E: End word

Variations
Variations Executed Each Cycle for ON Condition WSFT(016)
Executed Once for Upward Differentiation @WSFT(016)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Note St and E must be in the same data area.

Operand Specifications
Area S St E
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767

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Data Shift Instructions Section 3-9

Area S St E
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description WSFT(016) shifts data from St to E in word units and the data from the source
word S is places into St. The contents of E is lost.

E St
Lost

Flags
Name Label Operation
Error Flag ER ON when St is greater than E.
OFF in all other cases.

Precautions When St is greater than E, an error will be generated and the Error Flag will
turn ON.
Note When large amounts of data are shifted, the instruction execution time is quite
long. Be sure that the power is not cut while WSFT(016) is being executed,
causing the shift operation to stop halfway through.

Examples When CIO 000000 is ON, data from CIO 0100 through CIO 0102 will be
shifted one word toward E. The contents of CIO 0300 will be stored in
CIO 0100 and the contents of CIO 0102 will be lost.

St
E
S: CIO 0300

E: CIO 0100 St: CIO 0101 St: CIO 0102

Lost

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Data Shift Instructions Section 3-9

3-9-5 ARITHMETIC SHIFT LEFT: ASL(025)

Purpose Shifts the contents of Wd one bit to the left.
Ladder Symbol
ASL(025)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition ASL(025)
Executed Once for Upward Differentiation @ASL(025)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ASL(025) shifts the contents of Wd one bit to the left (from rightmost bit to left-
most bit). “0” is placed in the rightmost bit and the data from the leftmost bit is
shifted into the Carry Flag (CY).

15 0

370
Data Shift Instructions Section 3-9

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions When ASL(025) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd is zero, the Equals Flag will turn
ON.
If as a result of the shift the contents of the leftmost bit of Wd is 1, the Nega-
tive Flag will turn ON.

Examples When CIO 000000 is ON, CIO 0100 will be shifted one bit to the left. “0” will
be placed in CIO 010000 and the contents of CIO 010115 will be shifted to the
Carry Flag (CY).

Wd

3-9-6 DOUBLE SHIFT LEFT: ASLL(570)

Purpose Shifts the contents of Wd and Wd +1 one bit to the left.

Ladder Symbol
ASLL(570)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition ASLL(570)
Executed Once for Upward Differentiation @ASLL(570)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510

371
Data Shift Instructions Section 3-9

Area Wd
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ASLL(570) shifts the contents of Wd and Wd +1 one bit to the left (from right-
most bit to leftmost bit). “0” is placed in the rightmost bit of Wd and the con-
tents of the leftmost bit of Wd and Wd +1 are shifted into the Carry Flag (CY).
Wd+1 Wd

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.
Precautions When ASLL(570) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals
Flag will turn ON.
If as a result of the shift the contents of the leftmost bit of Wd +1 is 1, the Neg-
ative Flag will turn ON.
Examples When CIO 000000 is ON, word CIO 0100 and CIO 0101 will shift one bit to
the left. “0” is placed into CIO 010000 and the contents of CIO 010015 will be
shifted to the Carry Flag (CY).

372
Data Shift Instructions Section 3-9

Wd

3-9-7 ARITHMETIC SHIFT RIGHT: ASR(026)

Purpose Shifts the contents of Wd one bit to the right.
Ladder Symbol
ASR(026)

Wd Wd: Word
Variations
Variations Executed Each Cycle for ON Condition ASR(026)
Executed Once for Upward Differentiation @ASR(026)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported
Applicable Program Areas
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK
Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15

373
Data Shift Instructions Section 3-9

Area Wd
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ASR(026) shifts the contents of Wd one bit to the right (from leftmost bit to
rightmost bit). “0” will be placed in the leftmost bit and the contents of the
rightmost bit will be shifted into the Carry Flag (CY).

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N OFF

Precautions When ASR(026) is executed, the Error Flag and the Negative Flag will turn
OFF.
If as a result of the shift the contents of Wd is zero, the Equals Flag will turn
ON.

Examples When CIO 000000 is ON, word CIO 0100 will shift one bit to the right. “0” will
be placed in CIO 010015 and the contents of CIO 010000 will be shifted to the
Carry Flag (CY).

Wd

3-9-8 DOUBLE SHIFT RIGHT: ASRL(571)

Purpose Shifts the contents of Wd and Wd +1 one bit to the right.

Ladder Symbol
ASRL(571)

Wd Wd: Word

374
Data Shift Instructions Section 3-9

Variations
Variations Executed Each Cycle for ON Condition ASRL(571)
Executed Once for Upward Differentiation @ASRL(571)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ASRL(571) shifts the contents of Wd and Wd +1 one bit to the right (from left-
most bit to rightmost bit). “0” will be placed in the leftmost bit of Wd +1 and the
contents of the rightmost bit of Wd will be shifted into the Carry Flag (CY).
Wd+1 Wd

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.

375
Data Shift Instructions Section 3-9

Name Label Operation

Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N OFF

Precautions When ASRL (571) is executed, the Error Flag and the Negative Flag will turn
OFF.
If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals
Flag will turn ON.
Examples When CIO 000000 is ON, word CIO 0100 and CIO 0101 will shift one bit to
the right. “0” will be placed into CIO 010115 and the contents of CIO 010000
will be shifted to the Carry Flag (CY).

Wd

3-9-9 ROTATE LEFT: ROL(027)

Purpose Shifts all Wd bits one bit to the left including the Carry Flag (CY).

Ladder Symbol
ROL(027)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition ROL(027)
Executed Once for Upward Differentiation @ROL(027)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)

376
Data Shift Instructions Section 3-9

Area Wd
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ROL(027) shifts all bits of Wd including the Carry Flag (CY) to the left (from
rightmost bit to leftmost bit).

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions When ROL(027) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd is zero, the Equals Flag will turn
ON.
If as a result of the shift the contents of the leftmost bit of Wd is 1, the Nega-
tive Flag will turn ON.
Note It is possible to set the Carry Flag contents to 1 or 0 immediately before exe-
cuting this instruction, by using the Set Carry (STC(040)) or Clear Carry
(CLC(041)) instructions.

Examples When CIO 000000 is ON, word CIO 0100 and the Carry Flag (CY) will shift
one bit to the left. The contents of CIO 010015 will be shifted to the Carry Flag
(CY) and the Carry Flag contents will be shifted to CIO 010000.

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Data Shift Instructions Section 3-9

Wd

Wd: CIO 0100

Instruction executed once

3-9-10 DOUBLE ROTATE LEFT: ROLL(572)

Purpose Shifts all Wd and Wd +1 bits one bit to the left including the Carry Flag (CY).

Ladder Symbol
ROLL(572)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition ROLL(572)
Executed Once for Upward Differentiation @ROLL(572)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---

378
Data Shift Instructions Section 3-9

Area Wd
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ROLL(572) shifts all bits of Wd and Wd +1 including the Carry Flag (CY) to
the left (from rightmost bit to leftmost bit).
Wd+1 Wd

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions When ROLL(572) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals
Flag will turn ON.
If as a result of the shift the contents of the leftmost bit of Wd + 1 is 1, the Neg-
ative Flag will turn ON.
Note It is possible to set the Carry Flag contents to 1 or 0 immediately before exe-
cuting this instruction, by using the Set Carry (STC(040)) or Clear Carry
(CLC(041)) instructions.

Examples When CIO 000000 is ON, word CIO 0100, CIO 0101 and the Carry Flag (CY)
will shift one bit to the left. The contents of CIO 010015 will be shifted to the
Carry Flag (CY) and the Carry Flag contents will be shifted to CIO 010000.

Wd

Wd+1: CIO 0101 Wd: CIO 0100

Instruction executed once

379
Data Shift Instructions Section 3-9

3-9-11 ROTATE RIGHT: ROR(028)

Purpose Shifts all Wd bits one bit to the right including the Carry Flag (CY).
Ladder Symbol
ROR(028)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition ROR(028)
Executed Once for Upward Differentiation @ROR(028)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ROR(028) shifts all bits of Wd including the Carry Flag (CY) to the right (from
leftmost bit to rightmost bit).

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Data Shift Instructions Section 3-9

Wd

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions When ROR(028) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd is zero, the Equals Flag will turn
ON.
If as a result of the shift the contents of the leftmost bit of Wd is 1, the Nega-
tive Flag will turn ON.
Note It is possible to set the Carry Flag contents to 1 or 0 immediately before exe-
cuting this instruction, by using the Set Carry (STC(040)) or Clear Carry
(CLC(041)) instructions.

Examples When CIO 000000 is ON, word CIO 0100 and the Carry Flag (CY) will shift
one bit to the right. The contents of CIO 010000 will be shifted to the Carry
Flag (CY) and the Carry Flag contents will be shifted to CIO 010015.

Wd

Wd: CIO 0100

Instruction executed once

3-9-12 DOUBLE ROTATE RIGHT: RORL(573)

Purpose Shifts all Wd and Wd +1 bits one bit to the right including the Carry Flag (CY).

Ladder Symbol
RORL(573)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition RORL(573)
Executed Once for Upward Differentiation @RORL(573)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

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Data Shift Instructions Section 3-9

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description RORL(573) shifts all bits of Wd and Wd +1 including the Carry Flag (CY) to
the right (from leftmost bit to rightmost bit).
Wd+1 Wd

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions When RORL(573) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals
Flag will turn ON.

382
Data Shift Instructions Section 3-9

If as a result of the shift the contents of the leftmost bit of Wd + 1 is 1, the Neg-
ative Flag will turn ON.
Note It is possible to set the Carry Flag contents to 1 or 0 immediately before exe-
cuting this instruction, by using the Set Carry (STC(040)) or Clear Carry
(CLC(041)) instructions.

Examples When CIO 000000 is ON, word CIO 0100, CIO 0101 and the Carry Flag (CY)
will shift one bit to the right. The contents of CIO 010000 will be shifted to the
Carry Flag (CY) and the Carry Flag contents will be shifted to CIO 010115.

Wd

Wd+1: CIO 0101 Wd: CIO 0100

Instruction executed once

3-9-13 ROTATE LEFT WITHOUT CARRY: RLNC(574)

Purpose Shifts all Wd bits one bit to the left not including the Carry Flag (CY).

Ladder Symbol
RLNC(574)
Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition RLNC(574)
Executed Once for Upward Differentiation @RLNC(574)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)

383
Data Shift Instructions Section 3-9

Area Wd
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description RLNC(574) shifts all bits of Wd to the left (from rightmost bit to leftmost bit).
The contents of the leftmost bit of Wd shifts to the rightmost bit and to the
Carry Flag (CY).

Wd

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions When RLNC(574) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd is zero, the Equals Flag will turn
ON.
If as a result of the shift the contents of the leftmost bit of Wd is 1, the Nega-
tive Flag will turn ON.

Examples When CIO 000000 is ON, word CIO 0100 will shift one bit to the left (exclud-
ing the Carry Flag (CY)). The contents of CIO 010015 will be shifted to
CIO 010000.

384
Data Shift Instructions Section 3-9

Wd

Wd: CIO 0100

Instruction executed once

3-9-14 DOUBLE ROTATE LEFT WITHOUT CARRY: RLNL(576)

Purpose Shifts all Wd and Wd +1 bits one bit to the left not including the Carry Flag
(CY).

Ladder Symbol
RLNL(576)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition RLNL(576)
Executed Once for Upward Differentiation @RLNL(576)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---

385
Data Shift Instructions Section 3-9

Area Wd
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description RLNL(576) shifts all bits of Wd and Wd +1 to the left (from rightmost bit to left-
most bit). The contents of the leftmost bit of Wd +1 is shifted to the rightmost
bit of Wd, and to the Carry Flag (CY).
Wd+1 Wd

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions When RLNL(576) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals
Flag will turn ON.
If as a result of the shift the contents of the leftmost bit of Wd + 1 is 1, the Neg-
ative Flag will turn ON.

Examples When CIO 000000 is ON, word CIO 0100 and CIO 0101 will shift one bit to
the left (excluding the Carry Flag (CY)). The contents of CIO 010115 will be
shifted to CIO 010000.

Wd

Wd+1: CIO 0101 Wd: CIO 0100

Instruction executed once

386
Data Shift Instructions Section 3-9

3-9-15 ROTATE RIGHT WITHOUT CARRY: RRNC(575)

Purpose Shifts all Wd bits one bit to the right not including the Carry Flag (CY). The
contents of the rightmost bit of Wd shifts to the leftmost bit and to the Carry
Flag (CY).
Ladder Symbol
RRNC(575)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition RRNC(575)
Executed Once for Upward Differentiation @RRNC(575)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description RRNC(575) shifts all bits of Wd to the right (from leftmost bit to rightmost bit)
not including the Carry Flag (CY).

387
Data Shift Instructions Section 3-9

Wd

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions When RRNC(575) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd is zero, the Equals Flag will turn
ON.
If as a result of the shift the contents of the leftmost bit of Wd is 1, the Nega-
tive Flag will turn ON.

Examples When CIO 000000 is ON, word CIO 0100 will shift one bit to the right (exclud-
ing the Carry Flag (CY)). The contents of CIO 010000 will be shifted to
CIO 010015.

Wd

Wd: CIO 0100

Instruction executed once

CY

3-9-16 DOUBLE ROTATE RIGHT WITHOUT CARRY: RRNL(577)

Purpose Shifts all Wd and Wd +1 bits one bit to the right not including the Carry Flag
(CY). The contents of the rightmost bit of Wd +1 is shifted to the leftmost bit of
Wd, and to the Carry Flag (CY).

Ladder Symbol
RRNL(577)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition RRNL(577)
Executed Once for Upward Differentiation @RRNL(577)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

388
Data Shift Instructions Section 3-9

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description RRNL(577) shifts all bits of Wd and Wd +1 to the right (from leftmost bit to
rightmost bit) not including the Carry Flag (CY).
Wd+1 Wd

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions When RRNL(577) is executed, the Error Flag will turn OFF.
If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals
Flag will turn ON.

389
Data Shift Instructions Section 3-9

If as a result of the shift the contents of the leftmost bit of Wd + 1 is 1, the Neg-
ative Flag will turn ON.
Note It is possible to set the Carry Flag contents to 1 or 0 immediately before exe-
cuting this instruction, by using the Set Carry (STC(040)) or Clear Carry
(CLC(041)) instructions.

Examples When CIO 000000 is ON, words CIO 0100 and CIO 0101 will shift one bit to
the right, (excluding the Carry Flag (CY)). The contents of CIO 010000 will be
shifted to CIO 010115.

Wd

Wd+1: CIO 0101 Wd: CIO 0100

Instruction executed once

3-9-17 ONE DIGIT SHIFT LEFT: SLD(074)

Purpose Shifts data by one digit (4 bits) to the left.

Ladder Symbol
SLD(074)

St St: Starting word

E E: End word

Variations
Variations Executed Each Cycle for ON Condition SLD(074)
Executed Once for Upward Differentiation @SLD(074)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Note St and E must be in the same data area.

Operand Specifications
Area St E
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767

390
Data Shift Instructions Section 3-9

Area St E
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description SLD(074) shifts data between St and E by one digit (4 bits) to the left. “0” is
placed in the rightmost digit (bits 3 to 0 of St), and the content of the leftmost
digit (bits 15 to 12 of E) is lost.
E S t

Lost

Flags
Name Label Operation
Error Flag ER ON when St is greater than E.
OFF in all other cases.

Precautions When St is greater than E, an error will be generated and the Error Flag will
turn ON.
Note When large amounts of data are shifted, the instruction execution time is quite
long. Be sure that the power is not cut while SLD(074) is being executed,
causing the shift operation to stop halfway through.

Examples When CIO 000000 is ON, words CIO 0100 through CIO 0102 will shift by one
digit (4 bits) to the left. A zero will be placed in bits 0 to 3 of word CIO 0100
and the contents of bits 12 to 15 of CIO 0102 will be lost.

St
E
E: CIO 0102 St+1: CIO 0101 St: CIO 0100

Lost

391
Data Shift Instructions Section 3-9

3-9-18 ONE DIGIT SHIFT RIGHT: SRD(075)

Purpose Shifts data by one digit (4 bits) to the right.
Ladder Symbol
SRD(075)

E E: End word

St St: Starting word

Variations
Variations Executed Each Cycle for ON Condition SRD(075)
Executed Once for Upward Differentiation @SRD(075)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Note St and E must be in the same data area.

Operand Specifications
Area St E
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

392
Data Shift Instructions Section 3-9

Description SRD(075) shifts data between St and E by one digit (4 bits) to the right. “0” is
placed in the leftmost digit (bits 15 to 12 of E), and the content of the rightmost
digit (bits 3 to 0 of St) is lost.
E S t

Lost

Flags
Name Label Operation
Error Flag ER ON when St is greater than E.
OFF in all other cases.

Precautions When St is greater than E, an error will be generated and the Error Flag will
turn ON.
When SRD(075) is executed, the Equals Flag and Negative Flag will turn
OFF.
Note When large amounts of data are shifted, the instruction execution time is quite
long. Always take care that the power is not cut while SRD(075) is being exe-
cuted, causing the shift operation to stop halfway through.

Examples When CIO 000000 is ON, words CIO 0100 through CIO 0102 will shift by one
digit (4 bits) to the right. A zero will be placed in bits 12 to 15 of CIO 0102 and
the contents of bits 0 to 3 of word CIO 0100 will be lost.

St
E
E: CIO 0102 St+1: CIO 0101 St: CIO 0100

Lost

3-9-19 SHIFT N-BIT DATA LEFT: NSFL(578)

Purpose Shifts the specified number of bits to the left.
Ladder Symbol
NSFL(578)

D D: Beginning word for shift

C C: Beginning bit

N N: Shift data length

Variations
Variations Executed Each Cycle for ON Condition NSFL(578)
Executed Once for Upward Differentiation @NSFL(578)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: 0000 to 000F hex (0 to 15)

N: 0000 to FFFF hex (0 to 65535)

393
Data Shift Instructions Section 3-9

Note All words in the shift register must be in the same area.

Operand Specifications
Area D C N
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959 A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- #0000 to #000F #0000 to #FFFF
(binary) or &0 to (binary) or &0 to
&15 &65535
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NSFL(578) shifts the specified number of bits by the shift data length (N) from
the beginning bit (C) in the rightmost word, as designated by D one bit to the
left (towards the leftmost word and the leftmost bit). “0” is place into the begin-
ning bit and the contents of the leftmost bit in the shift area are shifted to the
Carry Flag (CY).

Shifts one bit to the left

N−1 bit

N−1 bit

394
Data Shift Instructions Section 3-9

Flags
Name Label Operation
Error Flag ER ON when C data is not between 0000 and 000F hex.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.

Precautions When the shift data length (N) is 0, the contents of the beginning bit will be
copied to the Carry Flag (CY), and its contents will not be changed.
Only the bits shifted into rightmost word in the shift area (i.e. leftmost word
data) will be changed.

Examples When CIO 000000 is ON, all bits from the beginning bit 3 to the shift data
length (B hex) will be shifted one bit to the left (from the rightmost bit to the
leftmost bit). “0” will be placed into bit 3 of CIO 0100. The contents of the left-
most bit in the shift area (bit 13 of CIO 0100) are copied into the Carry Flag
(CY).

D
C &3
N &11

C: Starting from bit 3

N: 11 bits

D: CIO 0100

D: CIO 0100
0

3-9-20 SHIFT N-BIT DATA RIGHT: NSFR(579)

Purpose Shifts the specified number of bits to the right.

Ladder Symbol
NSFR(579)

D D: Beginning word for shift

C C: Beginning bit

N N: Shift data length

Variations
Variations Executed Each Cycle for ON Condition NSFR(579)
Executed Once for Upward Differentiation @NSFR(579)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

395
Data Shift Instructions Section 3-9

Operands C: 0000 to 000F hex (0 to 15)

N: 0000 to FFFF hex (0 to 65535)
Note All words in the shift register must be in the same area.

Operand Specifications
Area D C N
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959 A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- #0000 to #000F #0000 to #FFFF
(binary) or &0 to (binary) or &0 to
&15 &65535
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NSFR(579) shifts the specified number of bits by the shift data length (N) from
the beginning bit (C) in the rightmost word as designated by D one bit to the
right (towards the rightmost word and the rightmost bit). “0” will be placed into
the beginning bit and the contents of the rightmost bit in the shift area will be
shifted to the Carry Flag (CY).

Shifts one bit to the right

N-1 bit

N-1 bit

396
Data Shift Instructions Section 3-9

Flags
Name Label Operation
Error Flag ER ON when C data is not between 0000 and 000F hex.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.

Precautions When the shift data length (N) is 0, the contents of the beginning bit will be
copied to the Carry Flag (CY), and its contents will not be changed.
Only the bits shifted into rightmost word in the shift area (i.e. leftmost word
data) will be changed.

Examples When CIO 000000 is ON, all bits from the beginning bit 2 to end of the shift
data length 11 bits (B hex), will be shifted one bit to the right, (from the left-
most bit to the rightmost bit). “0” is shifted into bit 12 of CIO 0100. The con-
tents of the rightmost bit in the shift area (bit 2 of CIO 0100) are copied into
the Carry Flag (CY).

&2
&11

C: Starting from bit 2

N: 11 bits

3-9-21 SHIFT N-BITS LEFT: NASL(580)

Purpose Shifts the specified 16 bits of word data to the left by the specified number of
bits.

Ladder Symbol
NASL(580)

D D: Shift word

C C: Control word

Variations
Variations Executed Each Cycle for ON Condition NASL(580)
Executed Once for Upward Differentiation @NASL(580)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

397
Data Shift Instructions Section 3-9

Operands C: Control Word

15 12 11 8 7 0
C
0

No. of bits to shift: 00 to 10 Hex

Always 0.
Data shifted into register
0 Hex: 0 shifted in
8 Hex: Contents of rightmost bit shifted in

Operand Specifications
Area D C
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959 A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- Specified values only
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NASL(580) shifts D (the shift word) by the specified number of binary bits
(specified in C) to the left (from the rightmost bit to the leftmost bit). Either
zeros or the value of the rightmost bit will be placed into the specified number
of bits of the shift word starting from the rightmost bit.

398
Data Shift Instructions Section 3-9

Shift n-bits

Contents of "a" or "0" shifted in

Lost

N bits

Flags
Name Label Operation
Error Flag ER ON when the control word C (the number of bits to shift) is
not within range.
OFF in all other cases.
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions For any bits which are shifted outside the specified word, the contents of the
last bit is shifted to the Carry Flag (CY), and all other data is lost.
When the number of bits to shift (specified in C) is “0,” the data will not be
shifted. The appropriate flags will turn ON and OFF, however, according to
data in the specified word.
When the contents of the control word C is out of range, an error will be gen-
erated and the Error Flag will turn ON.
If as a result of the shift the contents of D is 0000 hex, the Equals Flag will
turn ON.
If as a result of the shift the contents of the leftmost bit of D is 1, the Negative
Flag will turn ON.
Examples When CIO 000000 is ON, The contents of CIO 0100 is shifted 10 bits to the
left (from the rightmost bit to the leftmost bit). The number of bits to shift is
specified in bits 0 to 7 of word CIO 0300 (control data). The contents of bit 0 of
CIO 0100 is copied into bits from which data was shifted and the contents of
the rightmost bit which was shifted out of range is shifted into the Carry Flag
(CY). All other data is lost.

399
Data Shift Instructions Section 3-9

15 12 11 8 7 4 3 0
C 8 0 0 A

No. of bits to shift: 10 bits (0A Hex)

Always 0.
Data shifted into register
8 Hex: Contents of rightmost bit shifted in

Lost
Rightmost bit

No. of bits to shift: 10 bits

(Contents of the rightmost
bit is inserted.)

3-9-22 DOUBLE SHIFT N-BITS LEFT: NSLL(582)

Purpose Shifts the specified 32 bits of word data to the left by the specified number of
bits.

Ladder Symbol
NSLL(582)

D D: Shift word

C C: Control word

Variations
Variations Executed Each Cycle for ON Condition NSLL(582)
Executed Once for Upward Differentiation @NSLL(582)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: Control Word

400
Data Shift Instructions Section 3-9

15 12 11 8 7 0
C
0

No. of bits to shift: 00 to 20 Hex

Always 0.
Data shifted into register
0 Hex: 0 shifted in
8 Hex: Contents of rightmost bit shifted in

Operand Specifications
Area D C
CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6143
Work Area W000 to W510 W000 to W511
Holding Bit Area H000 to H510 H000 to H511
Auxiliary Bit Area A448 to A958 A000 to A959
Timer Area T0000 to T4094 T0000 to T4095
Counter Area C0000 to C4094 C0000 to C4095
DM Area D00000 to D32766 D00000 to D32767
EM Area without bank E00000 to E32766 E00000 to E32767
EM Area with bank En_00000 to En_32766 En_00000 to En_32767
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- Specified values only
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NSLL(582) shifts D and D+1 (the shift words) by the specified number of
binary bits (specified in C) to the left (from the rightmost bit to the leftmost bit).
Either zeros or the value of the rightmost bit will be placed into the specified
number of bits of the shift word starting from the rightmost bit.

Shift n-bits

Contents of "a" or "0" shifted in

Lost

N bits

401
Data Shift Instructions Section 3-9

Flags
Name Label Operation
Error Flag ER ON when the control word C (the number of bits to shift) is
not within range.
OFF in all other cases.
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions For any bits which are shifted outside the specified word, the contents of the
last bit is shifted to the Carry Flag (CY), and all other data is lost.
When the number of bits to shift (specified in C) is “0,” the data will not be
shifted. The appropriate flags will turn ON and OFF, however, according to
data in the specified word.
When the contents of the control word C are out of range, an error will be gen-
erated and the Error Flag will turn ON.
If as a result of the shift the contents of D is 0000, the Equals Flag will turn
ON.
If as a result of the shift the contents of the leftmost bit of D, D +1 is 1, the
Negative Flag will turn ON.

Examples When CIO 000000 is ON, CIO 0100 and CIO 0101 will be shifted to the left
(from the rightmost bit to the leftmost bit) by 10 bits. The number of bits to shift
is specified in bits 0 to 7 of word CIO 0300 (control data). The contents of bit 0
of CIO 0100 is copied into bits from which data was shifted and the contents
of the rightmost bit which was shifted out of range is shifted into the Carry
Flag (CY). All other data is lost.

15 12 11 8 7 4 3 0
C
8 0 0 A

No. of bits to shift: 10 bits (0A Hex)

Always 0.
Data shifted into register
8 Hex: Contents of right-
most bit shifted in

402
Data Shift Instructions Section 3-9

Lost
Rightmost bit a

0100

0100

No. of bits to shift: 10 bits

(Contents of the rightmost
bit is shifted in)

3-9-23 SHIFT N-BITS RIGHT: NASR(581)

Purpose Shifts the specified 16 bits of word data to the right by the specified number of
bits.
Ladder Symbol
NASR(581)

D D: Shift word

C C: Control word

Variations
Variations Executed Each Cycle for ON Condition NASR(581)
Executed Once for Upward Differentiation @NASR(581)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: Control Word

15 12 11 8 7 0
C 0

No. of bits to shift: 00 to 10 Hex

Always 0.
Data shifted into register
0 Hex: 0 shifted in
8 Hex: Contents of rightmost bit shifted in

Operand Specifications
Area D C
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959 A000 to A447
A448 to A959
Timer Area T0000 to T4095

403
Data Shift Instructions Section 3-9

Area D C
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- Specified values only
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NASR(581) shifts D (the shift word) by the specified number of binary bits
(specified in C) to the right (from the rightmost bit to the leftmost bit). Either
zeros or the value of the rightmost bit will be placed into the specified number
of bits of the shift word starting from the rightmost bit.

Contents of "a" or
"0" shifted in
Lost

N bits

Flags
Name Label Operation
Error Flag ER ON when the control word C (the number of bits to shift) is
not within range.
OFF in all other cases.
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions For any bits which are shifted outside the specified word, the contents of the
last bit is shifted to the Carry Flag (CY), and all other data is discarded.
When the number of bits to shift (specified in C) is “0,” the data will not be
shifted. The appropriate flags will turn ON and OFF, however, according to
data in the specified word.

404
Data Shift Instructions Section 3-9

When the contents of the control word C are out of range, an error will be gen-
erated and the Error Flag will turn ON.
If as a result of the shift the contents of D is 0000 hex, the Equals Flag will
turn ON.
If as a result of the shift the contents of the leftmost bit of D is 1, the Negative
Flag will turn ON.

Examples When CIO 000000 is ON, CIO 0100 will be shifted 10 bits to the right (from
the leftmost bit to the rightmost bit). The number of bits to shift is specified in
bits 0 to 7 of word CIO 0300. The contents of bit 15 of CIO 0100 is copied into
the bits from which data was shifted and the contents of the leftmost bit of
data which was shifted out of range, is shifted into the Carry Flag (CY). All
other data is lost.

15 12 11 8 7 4 3 0
C
8 0 0 A

No. of bits to shift: 10 bits (0A Hex)

Always 0.
Data shifted into register
8 Hex: Contents of leftmost bit shifted in

Leftmost bit
Lost

No. of bits to shift: 10 bits

(Contents of the leftmost bit is
inserted.)

3-9-24 DOUBLE SHIFT N-BITS RIGHT: NSRL(583)

Purpose Shifts the specified 32 bits of word data to the right by the specified number of
bits.

Ladder Symbol
NSRL(583)

D D: Shift word

C C: Control word

Variations
Variations Executed Each Cycle for ON Condition NSRL(583)
Executed Once for Upward Differentiation @NSRL(583)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

405
Data Shift Instructions Section 3-9

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: Control Word

15 12 11 8 7 0
C 0

No. of bits to shift: 00 to 20 Hex

Always 0.
Data shifted into register
0 Hex: 0 shifted in
8 Hex: Contents of rightmost bit shifted in

Operand Specifications
Area D C
CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6143
Work Area W000 to W510 W000 to W511
Holding Bit Area H000 to H510 H000 to H511
Auxiliary Bit Area A448 to A958 A000 to A959
Timer Area T0000 to T4094 T0000 to T4095
Counter Area C0000 to C4094 C0000 to C4095
DM Area D00000 to D32766 D00000 to D32767
EM Area without bank E00000 to E32766 E00000 to E32767
EM Area with bank En_00000 to En_32766 En_00000 to En_32767
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- Specified values only
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers -2048 to +2047 ,IR0 to -2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NSRL(583) shifts D and D+1 (the shift words) by the specified number of
binary bits (specified in C) to the right (from the leftmost bit to the rightmost
bit). Either zeros or the value of the rightmost bit will be placed into the speci-
fied number of bits of the shift word starting from the rightmost bit.

406
Data Shift Instructions Section 3-9

Shift n-bits

Contents of "a" or
"0" shifted in
Lost
N bits

Flags
Name Label Operation
Error Flag ER ON when the control word C (the number of bits to shift)
is not within range.
OFF in all other cases.
Equals Flag = ON when the shift result is 0.
OFF in all other cases.
Carry Flag CY ON when 1 is shifted into the Carry Flag (CY).
OFF in all other cases.
Negative Flag N ON when the leftmost bit is 1 as a result of the shift.
OFF in all other cases.

Precautions For any bits which are shifted outside the specified word, the contents of the
last bit is shifted to the Carry Flag (CY), and all other data is lost.
When the number of bits to shift (specified in C) is “0,” the data will not be
shifted. The appropriate flags will turn ON or OFF, however, according to data
in the specified word.
When the contents of the control word C are out of range, an error will be gen-
erated and the Error Flag will turn ON.
If as a result of the shift the contents of D +1 is 00000000 hex, the Equals Flag
will turn ON.
If as a result of the shift the contents of the leftmost bit of D +1 is 1, the Nega-
tive Flag will turn ON.

Examples When CIO 000000 is ON, CIO 0100 and CIO 0101 will be shifted 10 bits to
the right (from the leftmost bit to the rightmost bit). The number of bits to shift
is specified in bits 0 to 7 of word CIO 0300 (control data). The contents of bit
15 of CIO will be copied into the bits from which data was shifted and the con-
tents of the leftmost bit of data which was shifted out of range will be shifted
into the Carry Flag (CY). All other data is lost.

15 12 11 8 7 4 3 0
C 8 0 0 A

No. of bits to shift: 10 bits (0A Hex)

Always 0.
Data shifted into register
8 Hex: Contents of leftmost bit shifted in

407
Data Shift Instructions Section 3-9

Leftmost bit Lost

CY
1

No. of bits to shift: 10 bits

(Contents of the leftmost
bit is inserted.)

408
Increment/Decrement Instructions Section 3-10

3-10 Increment/Decrement Instructions

3-10-1 INCREMENT BINARY: ++(590)
Purpose Increments the 4-digit hexadecimal content of the specified word by 1.

Ladder Symbol
++(590)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition ++(590)
Executed Once for Upward Differentiation @++(590)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The ++(590) instruction adds 1 to the binary content of Wd. The specified
word will be incremented by 1 every cycle as long as the execution condition
of ++(590) is ON. When the up-differentiated variation of this instruction

409
Increment/Decrement Instructions Section 3-10

(@++(590)) is used, the specified word is incremented only when the execu-
tion condition has gone from OFF to ON.

Wd Wd

The Equals Flag will be turned ON if the result is 0000, the Carry Flag will be
turned ON when a digit changes from F to 0, and the Negative Flag will be
turned ON when bit 15 of Wd is ON in the result.
Both the Equals Flag and the Carry Flag will be turned ON when the content
of Wd changes from FFFF to 0000.

Flags
Name Label Operation
Error Flag ER OFF
Equals = ON if the content of Wd is 0000 after execution.
Flag OFF in all other cases.
Carry Flag CY ON if a digit in Wd went from F to 0 during execution.
OFF in all other cases.
Negative N ON if bit 15 of Wd is ON after execution.
Flag OFF in all other cases.

Examples Operation of ++(590)

In the following example, the content of D00100 will be incremented by 1
every cycle as long as CIO 000000 is ON.

Incremented every cycle

while CIO 000000 is ON.
Wd: D00100 Wd: D00100
0 0 1 9 0 0 1 A

: Execution of ++(590)

Increment Increment Increment Increment

Operation of @++(590)
The up-differentiated variation is used in the following example, so the content
of D00100 will be incremented by 1 only when CIO 000000 has gone from
OFF to ON.

@++ Incremented only for

up-differentiation.
Wd: D00100 Wd: D00100
0 0 1 9 0 0 1 A

: Execution of @++(590)

Increment Increment

410
Increment/Decrement Instructions Section 3-10

3-10-2 DOUBLE INCREMENT BINARY: ++L(591)

Purpose Increments the 8-digit hexadecimal content of the specified words by 1.
Ladder Symbol
++L(591)

Wd Wd: First word

Variations
Variations Executed Each Cycle for ON Condition ++L(591)
Executed Once for Upward Differentiation @++L(591)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers IR0 to IR15
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The ++L(591) instruction adds 1 to the 8-digit hexadecimal content of Wd+1
and Wd. The content of the specified words will be incremented by 1 every
cycle as long as the execution condition of ++L(591) is ON. When the up-dif-
ferentiated variation of this instruction (@++L(591)) is used, the content of the

411
Increment/Decrement Instructions Section 3-10

specified words is incremented only when the execution condition has gone
from OFF to ON.

Wd+1 Wd Wd+1 Wd

The Equals Flag will be turned ON if the result is 0000 0000, the Carry Flag
will be turned ON when a digit changes from F to 0, and the Negative Flag will
be turned ON if bit 15 of Wd+1 is ON in the result.
Both the Equals Flag and the Carry Flag will be turned ON when the content
of changes from FFFF FFFF to 0000 0000.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result is 0000 0000 after execution.
OFF in all other cases.
Carry Flag CY ON if a digit in Wd+1 or Wd went from F to 0 during
execution.
OFF in all other cases.
Negative Flag N ON if bit 15 of Wd+1 is ON after execution.
OFF in all other cases.

Examples Operation of ++L(591)

In the following example, the 8-digit hexadecimal content of D00101 and
D00100 will be incremented by 1 every cycle as long as CIO 000000 is ON.
Incremented every cycle
while CIO 000000 is ON.

Wd+1: D00101 Wd: D00100 Wd+1: D00101 Wd: D00100

: Execution of ++L(591)

Increment Increment Increment Increment

Operation of @++L(591)
The up-differentiated variation is used in the following example, so the content
of D00101 and D00100 will be incremented by 1 only when CIO 000000 has
gone from OFF to ON.

@++L Incremented only for

up-differentiation.

Wd+1: D00101 Wd: D00100 Wd+1: D00101 Wd: D00100

: Execution of @++L(591)

Increment Increment

412
Increment/Decrement Instructions Section 3-10

3-10-3 DECREMENT BINARY: – –(592)

Purpose Decrements the 4-digit hexadecimal content of the specified word by 1.
Ladder Symbol
− −(592)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition – – (592)
Executed Once for Upward Differentiation @– – (592)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The – –(592) instruction subtracts 1 from the binary content of Wd. The spec-
ified word will be decremented by 1 every cycle as long as the execution con-
dition of – –(592) is ON. When the up-differentiated variation of this instruction
(@– –(592)) is used, the specified word is decremented only when the execu-
tion condition has gone from OFF to ON.

Wd Wd

413
Increment/Decrement Instructions Section 3-10

The Equals Flag will be turned ON if the result is 0000, the Carry Flag will be
turned ON when a digit changes from 0 to F, and the Negative Flag will be
turned ON if bit 15 of Wd is ON in the result.
Both the Carry Flag and the Negative Flag will be turned ON when the content
of Wd changes from 0000 to FFFF.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the content of Wd is 0000 after execution.
OFF in all other cases.
Carry Flag CY ON if a digit in Wd went from 0 to F during execution.
OFF in all other cases.
Negative Flag N ON if bit 15 of Wd is ON after execution.
OFF in all other cases.

Examples Operation of – –(592)

In the following example, the content of D00100 will be decremented by 1
every cycle as long as CIO 000000 is ON.

Decremented every cycle

while CIO 000000 is ON.
Wd: D00100 Wd: D00100
−1

: Execution of − −(592)

Decrement Decrement Decrement Decrement

Operation of @– –(592)
The up-differentiated variation is used in the following example, so the content
of D00100 will be decremented by 1 only when CIO 000000 has gone from
OFF to ON.

@− − Decremented only
for up-differentiation.
Wd: D00100 Wd: D00100
−1

: Execution of @− −(592)

Decrement Decrement

414
Increment/Decrement Instructions Section 3-10

3-10-4 DOUBLE DECREMENT BINARY: – –L(593)

Purpose Decrements the 8-digit hexadecimal content of the specified words by 1.
Ladder Symbol
− −L(593)

Wd Wd: First word

Variations
Variations Executed Each Cycle for ON Condition – –L(593)
Executed Once for Upward Differentiation @– –L(593)
Executed Once for Downward Not supported
Differentiation
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers IR0 to IR15
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The – –L(593) instruction subtracts 1 from the 8-digit hexadecimal content of
Wd+1 and Wd. The content of the specified words will be decremented by 1
every cycle as long as the execution condition of – –L(593) is ON. When the
up-differentiated variation of this instruction (@– –L(593)) is used, the content

415
Increment/Decrement Instructions Section 3-10

of the specified words is decremented only when the execution condition has
gone from OFF to ON.

Wd+1 Wd Wd+1 Wd

The Equals Flag will be turned ON if the result is 0000 0000, the Carry Flag
will be turned ON when a digit changes from 0 to F, and the Negative Flag will
be turned ON if bit 15 of Wd+1 is ON in the result.
Both the Carry Flag and the Negative Flag will be turned ON when the content
changes from 0000 0000 to FFFF FFFF.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result is 0000 0000 after execution.
OFF in all other cases.
Carry Flag CY ON if a digit in Wd+1 or Wd went from 0 to F during exe-
cution.
OFF in all other cases.
Negative Flag N ON if bit 15 of Wd+1 is ON after execution.
OFF in all other cases.

Examples Operation of – –L(593)

In the following example, the 8-digit hexadecimal content of D00101 and
D00100 will be decremented by 1 every cycle as long as CIO 000000 is ON.
Decremented every cycle
while CIO 000000 is ON.

Wd+1: D00101 Wd: D00100 Wd+1: D00101 Wd: D00100

−1

: Execution of − −L(593)

Decrement Decrement Decrement Decrement

Operation of @– –L(593)
The up-differentiated variation is used in the following example, so the content
of D00101 and D00100 will be decremented by 1 only when CIO 000000 has
gone from OFF to ON.
Decremented only
for up-differentiation.
@ − −L Wd+1: D00101 Wd: D00100 Wd+1: D00101 Wd: D00100
−1

: Execution of @ − −L(593)

Decrement Decrement

416
Increment/Decrement Instructions Section 3-10

3-10-5 INCREMENT BCD: ++B(594)

Purpose Increments the 4-digit BCD content of the specified word by 1.
Ladder Symbol
++B(594)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition ++B(594)
Executed Once for Upward Differentiation @++B(594)
Executed Once for Downward Not supported
Differentiation
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n= 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in BCD @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The ++B(594) instruction adds 1 to the BCD content of Wd. The specified
word will be incremented by 1 every cycle as long as the execution condition
of ++B(594) is ON. When the up-differentiated variation of this instruction
(@++B(594)) is used, the specified word is incremented only when the execu-
tion condition has gone from OFF to ON.

417
Increment/Decrement Instructions Section 3-10

Wd Wd

The Equals Flag will be turned ON if the result is 0000 and the Carry Flag will
be turned ON when a digit changes from 9 to 0.
Both the Equals Flag and the Carry Flag will be turned ON when the content
of Wd changes from 9999 to 0000.

Flags
Name Label Operation
Error Flag ER ON if the content of Wd is not BCD.
OFF in all other cases.
Equals Flag = ON if the content of Wd is 0000 after execution.
OFF in all other cases.
Carry Flag CY ON if a digit in Wd went from 9 to 0 during execution.
OFF in all other cases.

Precautions The content of Wd must be BCD. If it is not BCD, an error will occur and the
Error Flag will be turned ON.
Examples Operation of ++B(594)
In the following example, the BCD content of D00100 will be incremented by 1
every cycle as long as CIO 000000 is ON.
Incremented every cycle
while CIO 000000 is ON.

Wd: D00100 Wd: D00100

: Execution of ++B(594)

Increment Increment Increment Increment

Operation of @++B(594)
The up-differentiated variation is used in the following example, so the content
of D00100 will be incremented by 1 only when CIO 000000 has gone from
OFF to ON.

Incremented only for

@++B up-differentiation.
Wd: D00100 Wd: D00100

: Execution of @++B(594)

Increment Increment

418
Increment/Decrement Instructions Section 3-10

3-10-6 DOUBLE INCREMENT BCD: ++BL(595)

Purpose Increments the 8-digit BCD content of the specified words by 1.
Ladder Symbol
++BL(595)

Wd Wd: First word

Variations
Variations Executed Each Cycle for ON Condition ++BL(595)
Executed Once for Upward Differentiation @++BL(595)
Executed Once for Downward Not supported
Differentiation
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in BCD @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The ++BL(595) instruction adds 1 to the 8-digit BCD content of Wd+1 and
Wd. The content of the specified words will be incremented by 1 every cycle
as long as the execution condition of ++BL(595) is ON. When the up-differen-
tiated variation of this instruction (@++BL(595)) is used, the content of the

419
Increment/Decrement Instructions Section 3-10

specified words is incremented only when the execution condition has gone
from OFF to ON.

Wd+1 Wd Wd+1 Wd

The Equals Flag will be turned ON if the result is 0000 0000 and the Carry
Flag will be turned ON when a digit changes from 9 to 0.
Both the Equals Flag and the Carry Flag will be turned ON when the content
of changes from 9999 9999 to 0000 0000.

Flags
Name Label Operation
Error Flag ER ON if the content of Wd+1 and Wd is not BCD.
OFF in all other cases.
Equals Flag = ON if the result is 0000 0000 after execution.
OFF in all other cases.
Carry Flag CY ON if a digit in Wd+1 or Wd went from 9 to 0 during exe-
cution.
OFF in all other cases.

Precautions The content of Wd+1 and Wd must be BCD. If it is not BCD, an error will occur
and the Error Flag will be turned ON.

Examples Operation of ++BL(595)

In the following example, the 8-digit BCD content of D00101 and D00100 will
be incremented by 1 every cycle as long as CIO 000000 is ON.
Incremented every cycle
while CIO 000000 is ON.
Wd+1: D00101 Wd: D00100 Wd+1: D00101 Wd: D00100

: Execution of ++BL(595)

Increment Increment Increment Increment

Operation of @++BL(595)
The up-differentiated variation is used in the following example, so the BCD
content of D00101 and D00100 will be incremented by 1 only when
CIO 000000 has gone from OFF to ON.
Incremented only for
up-differentiation.
@++BL
Wd+1: D00101 Wd: D00100 Wd+1: D00101 Wd: D00100

: Execution of @++BL(595)

Increment Increment

420
Increment/Decrement Instructions Section 3-10

3-10-7 DECREMENT BCD: – –B(596)

Purpose Decrements the 4-digit BCD content of the specified word by 1.
Ladder Symbol
− −B(596)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition – –B(596)
Executed Once for Upward Differentiation @– –B(596)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in BCD @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The – –B(596) instruction subtracts 1 from the BCD content of Wd. The spec-
ified word will be decremented by 1 every cycle as long as the execution con-
dition of – –B(596) is ON. When the up-differentiated variation of this
instruction (@– –B(596)) is used, the specified word is decremented only
when the execution condition has gone from OFF to ON.

421
Increment/Decrement Instructions Section 3-10

Wd −1 Wd

The Equals Flag will be turned ON if the result is 0000 and the Carry Flag will
be turned ON when a digit changes from 0 to 9.
Flags
Name Label Operation
Error Flag ER ON if the content of Wd is not BCD.
OFF in all other cases.
Equals Flag = ON if the content of Wd is 0000 after execution.
OFF in all other cases.
Carry Flag CY ON if a digit in Wd went from 0 to 9 during execution.
OFF in all other cases.

Precautions The content of Wd must be BCD. If it is not BCD, an error will occur and the
Error Flag will be turned ON.

Examples Operation of – –B(596)

In the following example, the BCD content of D00100 will be decremented by
1 every cycle as long as CIO 000000 is ON.
Decremented every cycle
while CIO 000000 is ON.
Wd: D00100 Wd: D00100
−1

: Execution of − − B(596)

Decrement Decrement Decrement Decrement

Operation of @– –B(596)
The up-differentiated variation is used in the following example, so the BCD
content of D00100 will be decremented by 1 only when CIO 000000 has gone
from OFF to ON.

@ − −B Decremented only
for up-differentiation.
Wd: D00100 Wd: D00100
−1

: Execution of @− −B(596)

Decrement Decrement

422
Increment/Decrement Instructions Section 3-10

3-10-8 DOUBLE DECREMENT BCD: – –BL(597)

Purpose Decrements the 8-digit BCD content of the specified words by 1.
Ladder Symbol
− −BL(597)

Wd Wd: First word

Variations
Variations Executed Each Cycle for ON Condition – –BL(597)
Executed Once for Upward Differentiation @– –BL(597)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in BCD @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The – –BL(597) instruction subtracts 1 from the 8-digit BCD content of Wd+1
and Wd. The content of the specified words will be decremented by 1 every
cycle as long as the execution condition of – –BL(597) is ON. When the up-
differentiated variation of this instruction (@– –BL(597)) is used, the content

423
Increment/Decrement Instructions Section 3-10

of the specified words is decremented only when the execution condition has
gone from OFF to ON.

Wd+1 Wd Wd+1 Wd

The Equals Flag will be turned ON if the result is 0000 0000 and the Carry
Flag will be turned ON when a digit changes from 0 to 9.

Flags
Name Label Operation
Error Flag ER ON if the content of Wd+1 and Wd is not BCD.
OFF in all other cases.
Equals Flag = ON if the result is 0000 0000 after execution.
OFF in all other cases.
Carry Flag CY ON if a digit in Wd+1 or Wd went from 0 to 9 during exe-
cution.
OFF in all other cases.

Precautions The content of Wd+1 and Wd must be BCD. If it is not BCD, an error will occur
and the Error Flag will be turned ON.

Examples Operation of – –BL(597)

In the following example, the 8-digit BCD content of D00101 and D00100 will
be decremented by 1 every cycle as long as CIO 000000 is ON.

Decremented every cycle

while CIO 000000 is ON.
Wd+1: D00101 Wd: D00100 Wd+1: D00101 Wd: D00100
−1

: Execution of − −BL(597)

Decrement Decrement Decrement Decrement

Operation of @– –BL(597)
The up-differentiated variation is used in the following example, so the BCD
content of D00101 and D00100 will be decremented by 1 only when
CIO 000000 has gone from OFF to ON.
Decremented only
for up-differentiation.
@− −BL Wd+1: D00101 Wd: D00100 Wd+1: D00101 Wd: D00100
−1

: Execution of @− −BL(597)

Decrement Decrement

424
Symbol Math Instructions Section 3-11

3-11 Symbol Math Instructions

This section describes the Symbol Math Instructions, which perform arith-
metic operations on BCD or binary data.
Instruction Mnemonic Function code Page
SIGNED BINARY ADD WITH- + 400 426
OUT CARRY
DOUBLE SIGNED BINARY +L 401 428
ADD WITHOUT CARRY
SIGNED BINARY ADD WITH +C 402 430
CARRY
DOUBLE SIGNED BINARY +CL 403 432
ADD WITH CARRY
BCD ADD WITHOUT CARRY +B 404 434
DOUBLE BCD ADD WITHOUT +BL 405 435
CARRY
BCD ADD WITH CARRY +BC 406 437
DOUBLE BCD ADD WITH +BCL 407 439
CARRY
SIGNED BINARY SUBTRACT – 410 440
WITHOUT CARRY
DOUBLE SIGNED BINARY –L 411 442
SUBTRACT WITHOUT CARRY
SIGNED BINARY SUBTRACT –C 412 446
WITH CARRY
DOUBLE SIGNED BINARY –CL 413 448
SUBTRACT WITH CARRY
BCD SUBTRACT WITHOUT –B 414 451
CARRY
DOUBLE BCD SUBTRACT –BL 415 452
WITHOUT CARRY
BCD SUBTRACT WITH –BC 416 456
CARRY
DOUBLE BCD SUBTRACT –BCL 417 457
WITH CARRY
SIGNED BINARY MULTIPLY * 420 459
DOUBLE SIGNED BINARY *L 421 461
MULTIPLY
UNSIGNED BINARY MULTI- *U 422 463
PLY
DOUBLE UNSIGNED BINARY *UL 423 465
MULTIPLY
BCD MULTIPLY *B 424 467
DOUBLE BCD MULTIPLY *BL 425 469
SIGNED BINARY DIVIDE / 430 471
DOUBLE SIGNED BINARY /L 431 473
DIVIDE
UNSIGNED BINARY DIVIDE /U 432 475
DOUBLE UNSIGNED BINARY /UL 433 477
DIVIDE
BCD DIVIDE /B 434 479
DOUBLE BCD DIVIDE /BL 435 481

425
Symbol Math Instructions Section 3-11

3-11-1 SIGNED BINARY ADD WITHOUT CARRY: +(400)

Purpose Adds 4-digit (single-word) hexadecimal data and/or constants.
Ladder Symbol
+(400)

Au Au: Augend word

Ad Ad: Addend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition +(400)
Executed Once for Upward Differentiation @+(400)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Au Ad R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

426
Symbol Math Instructions Section 3-11

Description +(400) adds the binary values in Au and Ad and outputs the result to R.

Au (Signed binary)

Ad (Signed binary)
+
CY will turn
ON when there CY R (Signed binary)
is a carry.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the addition results in a carry.
OFF in all other cases.
Overflow Flag OF ON when the result of adding two positive numbers is in
the range 8000 to FFFF hex.
OFF in all other cases.
Underflow Flag UF ON when the result of adding two negative numbers is in
the range 0000 to 7FFF hex.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When +(400) is executed, the Error Flag will turn OFF.
If as a result of the addition, the content of R is 0000 hex, the Equals Flag will
turn ON.
If the addition results in a carry, the Carry Flag will turn ON.
If the result of adding two positive numbers is negative (in the range 8000 to
FFFF hex), the Overflow Flag will turn ON.
If the result of adding two negative numbers is positive (in the range 0000 to
7FFF hex), the Underflow Flag will turn ON.
If as a result of the addition, the content of the leftmost bit of R is 1, the Nega-
tive Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00100 and D00110 will
be added as 4-digit signed binary values and the result will be output to
D00120.

427
Symbol Math Instructions Section 3-11

3-11-2 DOUBLE SIGNED BINARY ADD WITHOUT CARRY: +L(401)

Purpose Adds 8-digit (double-word) hexadecimal data and/or constants.
Ladder Symbol
+L(401)

Au Au: 1st augend word

Ad Ad: 1st addend word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition +L(401)
Executed Once for Upward Differentiation @+L(401)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Au Ad R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers IR0 to IR15
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

428
Symbol Math Instructions Section 3-11

Description +L(401) adds the binary values in Au and Au+1 and Ad and Ad+1 and outputs
the result to R.
Au+1 Au (Signed binary)

Ad+1 Ad (Signed binary)

+
CY will turn
ON when there CY R+1 R (Signed binary)
is a carry.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the addition results in a carry.
OFF in all other cases.
Overflow Flag OF ON when the result of adding two positive numbers is in
the range 80000000 to FFFFFFFF hex.
OFF in all other cases.
Underflow Flag UF ON when the result of adding two negative numbers is in
the range 00000000 to 7FFFFFFF hex.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When +L(401) is executed, the Error Flag will turn OFF.
If as a result of the addition, the content of R, R+1 is 00000000 hex, the
Equals Flag will turn ON.
If the addition results in a carry, the Carry Flag will turn ON.
If the result of adding two positive numbers is negative (in the range
80000000 to FFFFFFFF hex), the Overflow Flag will turn ON.
If the result of adding two negative numbers is positive (in the range
00000000 to 7FFFFFFF hex), the Underflow Flag will turn ON.
If as a result of the addition, the content of the leftmost bit of R+1 is 1, the
Negative Flag will turn ON.

Examples When CIO 000000 is ON, D00100 and D00110 and D00111 and D00110 will
be added as 8-digit signed binary values and the result will be output to
D00120 and D00120.

429
Symbol Math Instructions Section 3-11

3-11-3 SIGNED BINARY ADD WITH CARRY: +C(402)

Purpose Adds 4-digit (single-word) hexadecimal data and/or constants with the Carry
Flag (CY).
Ladder Symbol
+C(402)

Au Au: Augend word

Ad Ad: Addend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition +C(402)
Executed Once for Upward Differentiation @+C(402)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Au Ad R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

430
Symbol Math Instructions Section 3-11

Description +C(402) adds the binary values in Au, Ad, and CY and outputs the result to R.

Au (Signed binary)

Ad (Signed binary)

+ CY
CY will turn
ON when there CY R (Signed binary)
is a carry.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the addition result is 0.
OFF in all other cases.
Carry Flag CY ON when the addition results in a carry.
OFF in all other cases.
Overflow Flag OF ON when the addition result of adding two positive num-
bers and CY is in the range 8000 to FFFF hex.
OFF in all other cases.
Underflow Flag UF ON when the addition result of adding two negative num-
bers and CY is in the range 0000 to 7FFF hex.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When +C(402) is executed, the Error Flag will turn OFF.
If as a result of the addition, the content of R is 0000 hex, the Equals Flag will
turn ON.
If the addition results in a carry, the Carry Flag will turn ON.
If the result of adding two positive numbers and CY is negative (in the range
8000 to FFFF hex), the Overflow Flag will turn ON.
If the result of adding two negative numbers and CY is positive (in the range
0000 to 7FFF hex), the Underflow Flag will turn ON.
If as a result of the addition, the content of the leftmost bit of R is 1, the Nega-
tive Flag will turn ON.
Note To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction.

Examples When CIO 000000 is ON, D00100, D00110, and CY will be added as 4-digit
signed binary values and the result will be output to D00220.

431
Symbol Math Instructions Section 3-11

3-11-4 DOUBLE SIGNED BINARY ADD WITH CARRY: +CL(403)

Purpose Adds 8-digit (double-word) hexadecimal data and/or constants with the Carry
Flag (CY).
Ladder Symbol
+CL(403)

Au Au: 1st augend word

Ad Ad: 1st addend word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition +CL(403)
Executed Once for Upward Differentiation @+CL(403)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Au Ad R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

432
Symbol Math Instructions Section 3-11

Description +CL(403) adds the binary values in Au and Au+1, Ad and Ad+1, and CY and
outputs the result to R.

Au+1 Au (Signed binary)

Ad+1 Ad (Signed binary)

+ CY
CY will turn
ON when there (Signed binary)
CY R+1 R
is a carry.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the results in a carry.
OFF in all other cases.
Overflow Flag OF ON when the result of adding two positive numbers and
CY is in the range 80000000 to FFFFFFFF hex.
OFF in all other cases.
Underflow Flag UF ON when the result of adding two negative numbers and
CY is in the range 00000000 to 7FFFFFFF hex.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When +CL(403) is executed, the Error Flag will turn OFF.
If as a result of the addition, the content of R, R+1 is 00000000 hex, the
Equals Flag will turn ON.
If the addition results in a carry, the Carry Flag will turn ON.
If the result of adding two positive numbers and CY is negative (in the range
80000000 to FFFFFFFF hex), the Overflow Flag will turn ON.
If the result of adding two negative numbers and CY is positive (in the range
00000000 to 7FFFFFFF hex), the Underflow Flag will turn ON.
If as a result of the addition, the content of the leftmost bit of R+1 is 1, the
Negative Flag will turn ON.
Note To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction.

Examples When CIO 000000 is ON, D00201, D00200, D00211, D00210, and CY will be
added as 8-digit signed binary values, and the result will be output to D00221
and D00220.

433
Symbol Math Instructions Section 3-11

3-11-5 BCD ADD WITHOUT CARRY: +B(404)

Purpose Adds 4-digit (single-word) BCD data and/or constants.
Ladder Symbol
+B(404)

Au Au: Augend word

Ad Ad: Addend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition +B(404)
Executed Once for Upward Differentiation @+B(404)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Au Ad R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants 0000 to 9999 ---
(BCD)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

434
Symbol Math Instructions Section 3-11

Description +B(404) adds the BCD values in Au and Ad and outputs the result to R.

Au (BCD)

+ Ad (BCD)

CY will turn
ON when there CY R (BCD)
is a carry.

Flags
Name Label Operation
Error Flag ER ON when Au is not BCD.
ON when Ad is not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the addition results in a carry.
OFF in all other cases.

Precautions If Au or Ad is not BCD, an error is generated and the Error Flag will turn ON.
If as a result of the addition, the content of R is 0000 hex, the Equals Flag will
turn ON.
If an addition results in a carry, the Carry Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00100 and D00110 will
be added as 4-digit BCD values, and the result will be output to D00120.

3-11-6 DOUBLE BCD ADD WITHOUT CARRY: +BL(405)

Purpose Adds 8-digit (double-word) BCD data and/or constants.

Ladder Symbol
+BL(405)

Au Au: 1st augend word

Ad Ad: 1st addend word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition +BL(405)
Executed Once for Upward Differentiation @+BL(405)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

435
Symbol Math Instructions Section 3-11

Operand Specifications
Area Au Ad R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #99999999 ---
(BCD)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description +BL(405) adds the BCD values in Au and Au+1 and Ad and Ad+1 and outputs
the result to R, R+1.
Au +1 Au (BCD)

Ad+1 Ad (BCD)
+
CY will turn
ON when there CY R+1 R (BCD)
is a carry.

Flags
Name Label Operation
Error Flag ER ON when Au, Au +1 is not BCD.
ON when Ad, Ad +1 is not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the addition results in a carry.
OFF in all other cases.

436
Symbol Math Instructions Section 3-11

Precautions If Au, Au +1 or Ad, Ad +1 are not BCD, an error is generated and the Error
Flag will turn ON.
If as a result of the addition, the content of R, R +1 is 00000000 hex, the
Equals Flag will turn ON.
If an addition results in a carry, the Carry Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00101 and D00100 and
D00111 and D00110 will be added as 8-digit BCD values, and the result will
be output to D00121 and D00120.

3-11-7 BCD ADD WITH CARRY: +BC(406)

Purpose Adds 4-digit (single-word) BCD data and/or constants with the Carry Flag
(CY).

Ladder Symbol
+BC(406)

Au Au: Augend word

Ad Ad: Addend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition +BC(406)
Executed Once for Upward Differentiation @+BC(406)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Au Ad R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)

437
Symbol Math Instructions Section 3-11

Area Au Ad R
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to 9999 ---
(BCD)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description +BC(406) adds BCD values in Au, Ad, and CY and outputs the result to R.

Au (BCD)

Ad (BCD)

+ CY

CY will turn
ON when there CY R (BCD)
is a carry.

Flags
Name Label Operation
Error Flag ER ON when Au is not BCD.
ON when Ad is not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the addition results in a carry.
OFF in all other cases.

Precautions If Au or Ad is not BCD, an error is generated and the Error Flag will turn ON.
If as a result of the addition, the content of R is 0000 hex, the Equals Flag will
turn ON.
If an addition results in a carry, the Carry Flag will turn ON.
Note To clear the Carry Flay (CY), execute the Clear Carry (CLC(041)) instruction.

Examples When CIO 000000 is ON in the following example, D00100, D00110, and CY
will be added as 4-digit BCD values, and the result will be output to D00120.

438
Symbol Math Instructions Section 3-11

3-11-8 DOUBLE BCD ADD WITH CARRY: +BCL(407)

Purpose Adds 8-digit (double-word) BCD data and/or constants with the Carry Flag
(CY).
Ladder Symbol
+BCL(407)

Au Au: 1st augend word

Ad Ad: 1st addend word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition +BCL(407)
Executed Once for Upward Differentiation @+BCL(407)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Au Ad R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #99999999 ---
(BCD)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

439
Symbol Math Instructions Section 3-11

Description +BCL(407) adds the BCD values in Au and Au+1, Ad and Ad+1, and CY and
outputs the result to R, R+1.

Au +1 Au (BCD)

Ad+1 Ad (BCD)

+ CY

CY will turn (BCD)

ON when there CY R+1 R
is a carry.

Flags
Name Label Operation
Error Flag ER ON when Au, Au +1 is not BCD.
ON when Ad, Ad +1 is not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the addition results in a carry.
OFF in all other cases.

Precautions If Au, Au +1 or Ad, Ad +1 are not BCD, an error is generated and the Error
Flag will turn ON.
If as a result of the addition, the content of R, R +1 is 00000000 hex, the
Equals Flag will turn ON.
If an addition results in a carry, the Carry Flag will turn ON.
Note To clear the Carry Flay (CY), execute the Clear Carry (CLC(041)) instruction.

Examples When CIO 000000 is ON in the following example, D00101, D00100, D00111,
D00110, and CY will be added as 8-digit BCD values, and the result will be
output to D00121 and D00120.

3-11-9 SIGNED BINARY SUBTRACT WITHOUT CARRY: –(410)

Purpose Subtracts 4-digit (single-word) hexadecimal data and/or constants.

Ladder Symbol
−(410)

Mi Mi: Minuend word

Su Su: Subtrahend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition –(410)
Executed Once for Upward Differentiation @–(410)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

440
Symbol Math Instructions Section 3-11

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Mi Su R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D0000 to D4095
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description –(400) subtracts the binary values in Su from Mi and outputs the result to R.
When the result is negative, it is output to R as a 2’s complement. (Refer to 3-
11-10 DOUBLE SIGNED BINARY SUBTRACT WITHOUT CARRY: –L(411)
for an example of handling 2’s complements.)

Mi (Signed binary)

Su (Signed binary)
−

CY will turn ON CY R (Signed binary)

when there is a
borrow.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.

441
Symbol Math Instructions Section 3-11

Name Label Operation

Carry Flag CY ON when the subtraction results in a borrow.
OFF in all other cases.
Overflow Flag OF ON when the result of subtracting a negative number from
a positive number is in the range 8000 to FFFF hex.
OFF in all other cases.
Underflow Flag UF ON when the result of subtracting a negative number from
a positive number is in the range 0000 to 7FFF hex.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When –(410) is executed, the Error Flag will turn OFF.
If as a result of the subtraction, the content of R is 0000 hex, the Equals Flag
will turn ON.
If the subtraction results in a borrow, the Carry Flag will turn ON.
If the result of subtracting a negative number from a positive number is nega-
tive (in the range 8000 to FFFF hex), the Overflow Flag will turn ON.
If the result of subtracting a positive number from a negative number is posi-
tive (in the range 0000 to 7FFF hex), the Underflow Flag will turn ON.
If as a result of the subtraction, the content of the leftmost bit of R is 1, the
Negative Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00110 will be subtracted
from D00100 as 4-digit signed binary values and the result will be output to
D00120.

3-11-10 DOUBLE SIGNED BINARY SUBTRACT WITHOUT CARRY: –L(411)

Purpose Subtracts 8-digit (double-word) hexadecimal data and/or constants.
Ladder Symbol
−L(411)

Mi Mi: Minuend word

Su Su: Subtrahend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition –L(411)
Executed Once for Upward Differentiation @–L(411)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

442
Symbol Math Instructions Section 3-11

Operand Specifications
Area Mi Su R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers IR0 to IR15
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description –L(411) subtracts the binary values in Su and Su+1 from Mi and Mi+1 and
outputs the result to R, R+1. When the result is negative, it is output to R and
R+1 as a 2’s complement.
Mi+1 Mi (Signed binary)

− Su+1 Su (Signed binary)

CY will turn
ON when there CY R+1 R (Signed binary)
is a borrow.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the subtraction results in a borrow.
OFF in all other cases.
Overflow Flag OF ON when the result of subtracting a negative number
from a positive number is in the range 80000000 to
FFFFFFFF hex.
OFF in all other cases.

443
Symbol Math Instructions Section 3-11

Name Label Operation

Underflow Flag UF ON when the result of subtracting a positive number from
a negative number is in the range 00000000 to
7FFFFFFF hex.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When –L(411) is executed, the Error Flag will turn OFF.
If as a result of the subtraction, the content of R, R+1 is 00000000 hex, the
Equals Flag will turn ON.
If the subtraction results in a borrow, the Carry Flag will turn ON.
If the result of subtracting a negative number from a positive number is nega-
tive (in the range 80000000 to FFFFFFFF hex), the Overflow Flag will turn
ON.
If the result of subtracting a positive number from a negative number is posi-
tive (in the range 00000000 to 7FFFFFFF hex), the Underflow Flag will turn
ON.
If as a result of the subtraction, the content of the leftmost bit of R+1 is 1, the
Negative Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00111 and D00110 will
be subtracted from D00101 and D00100 as 8-digit signed binary values and
the result will be output to D00121 and D00120.

−L

Examples If the result of the subtraction is a negative number (Mi<Su or Mi+1, Mi

<Su+1, Su), the result is output as the 2’s complement and the Carry Flag
(CY) will turn ON to indicate that the result of the subtraction is negative. To
convert the 2’s complement to the true number, an instruction which subtracts
the result from 0 is necessary using the Carry Flag (CY) as an execution con-
dition.
Note 2’s Complement
A 2’s complement is the value obtained by subtracting each binary digit from 1
and adding one to the result. For example, the 2’s complement for 1101 is cal-
culated as follows: 1111 (F hexadecimal) – 1101 (D hexadecimal) + 1 (1 hexa-
decimal) = 0011 (3 hexadecimal). The 2’s complement for 3039 (hexadecimal)
is calculated as follows: FFFF (hexadecimal) – 3039 (hexadecimal) + 0001
(hexadecimal) – CFC7 (hexadecimal). Therefore, in case of 4-digit hexadeci-
mal value, the 2’s complement can be calculated as follows: FFFF (hexadeci-
mal) – a (hexadecimal) + 0001 (hexadecimal) = b (hexadecimal). To obtain the
true number from the 2’s complement b (hexadecimal): a (hexadecimal) =
10000 (hexadecimal) – b (hexadecimal). For example, to obtain the true num-
ber from the 2’s complement CFC7 (hexadecimal): 10000 (hexadecimal) –
CFC7 = 3039.

444
Symbol Math Instructions Section 3-11

Example 1 Signed data Unsigned data

FFFF Hex −1 65535 Note 1. Since the Negative Flag is ON, the result (FFFE hex) is a
−) 0001 Hex −) +1 −) 1
negative value (2's complement) and is thus −2.
FFFE Hex −2 Note 1 65534 Note 2 2. Since the Carry Flag is OFF, the result (FFFE hex) is an
unsigned positive value of 65534.
Negative Flag ON
Carry Flag OFF

Example 2 Signed data Unsigned data

FFFD Hex −3 65533 3. Since the Negative Flag is ON, the result (FFFE hex) is a
−) FFFF Hex −) −1 −) 65535
negative value (2's complement) and is thus −2.
FFFE Hex −2 Note 3 65534 Note 4 4. Since the Carry Flag is ON, the result (FFFE hex) is a
negative value (2's complement) and becomes −2 when
Negative Flag ON converted to a true value.
Carry Flag OFF

Program Example 20F55A10 – B8A360E3 = –97AE06D3.

In this example, the eight-digit binary value in CIO 0121 and CIO 0120 is sub-
tracted from the value in CIO 0201 and CIO 0200, and the result is output in
eight-digit binary to D00101 and D00100. If the result is negative, the instruc-
tion at (2) will be executed, and the actual result will then be output to D00101
and D00100.
000000
RSET
002100

−L (1)
0200
0120
D00100
CY
−L (2)
#00000000
D00100
D00100

CY
SET "−"display
002100

Subtraction at 1
Mi+1: CIO 0201 Mi: CIO 0200
2 0 F 5 5 A 1 0

Su+1: CIO 0121 Su: CIO 0120

− B 8 A 3 6 0 E 3

CY R+1: D00101 R+1: D00100

1 6 8 5 1 F 9 2 D

The Carry Flag (CY) is ON, so the result is subtracted from 0000 0000 to
obtain the actual number.

445
Symbol Math Instructions Section 3-11

Subtraction at 2
0 0 0 0 0 0 0 0

Su+1: D00101 Su: D00100

− 6 8 5 1 F 9 2 D

CY R+1: D00101 R+1: D00100

1 9 7 A E 0 6 D 3

Final Subtraction Result

Mi+1: CIO 0201 Mi: CIO 0200
2 0 F 5 5 A 1 0

Su+1: D00101 Su: D00100

− 6 8 5 1 F 9 2 D

CY R+1: D00101 R+1: D00100

1 9 7 A E 0 6 D 3

The Carry Flag (CY) is turned ON, so the actual number is –97AE06D3.
Because the content of D00101 and D00100 is negative, CY is used to turn
ON CIO 002100 to indicate this.

3-11-11 SIGNED BINARY SUBTRACT WITH CARRY: –C(412)

Purpose Subtracts 4-digit (single-word) hexadecimal data and/or constants with the
Carry Flag (CY).

Ladder Symbol
−C(412)

Mi Mi: Minuend word

Su Su: Subtrahend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition –C(412)
Executed Once for Upward Differentiation @–C(412)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Mi Su R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959

446
Symbol Math Instructions Section 3-11

Area Mi Su R
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description –C(412) subtracts the binary values in Su and CY from Mi, and outputs the
result to R. When the result is negative, it is output to R as a 2’s complement.

Mi (Signed binary)

Su (Signed binary)

– CY
CY will turn
ON when there CY R (Signed binary)
is a borrow.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the subtraction result is 0.
OFF in all other cases.
Carry Flag CY ON when the subtraction results in a borrow.
OFF in all other cases.
Overflow Flag OF ON when the result of subtracting a negative number and
CY from a positive number is in the range 8000 to FFFF
hex.
OFF in all other cases.
Underflow Flag UF ON when the result of subtracting a positive number and
CY from a negative number is in the range 0000 to 7FFF
hex.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

447
Symbol Math Instructions Section 3-11

Precautions When –C(412) is executed, the Error Flag will turn OFF.
If as a result of the subtraction, the content of R is 0000 hex, the Equals Flag
will turn ON.
If the subtraction results in a borrow, the Carry Flag will turn ON.
If the result of subtracting a negative number and CY from a positive number
is negative (in the range 8000 to FFFF hex), the Overflow Flag will turn ON.
If the result of subtracting a positive number and CY from a negative number
is positive (in the range 0000 to 7FFF hex), the Underflow Flag will turn ON.
If as a result of the subtraction, the content of the leftmost bit of R is 1, the
Negative Flag will turn ON.
Note To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction.

Examples When CIO 000000 is ON in the following example, D00110 and CY will be
subtracted from D00100 as 4-digit signed binary values and the result will be
output to D00120.

3-11-12 DOUBLE SIGNED BINARY SUBTRACT WITH CARRY: –CL(413)

Purpose Subtracts 8-digit (double-word) hexadecimal data and/or constants with the
Carry Flag (CY).

Ladder Symbol
–CL(413)

Mi Mi: Minuend word

Su Su: Subtrahend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition –CL(413)
Executed Once for Upward Differentiation @–CL(413)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Mi Su R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094

448
Symbol Math Instructions Section 3-11

Area Mi Su R
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description –CL(413) subtracts the binary values in Su and Su+1 and CY from Mi and
Mi+1, and outputs the result to R, R+1. When the result is negative, it is output
to R, R+1 as a 2’s complement.
Mi+1 Mi (Signed binary)

Su+1 Su (Signed binary)

– CY
CY will turn
ON when there CY R+1 R (Signed binary)
is a borrow.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the results in a borrow.
OFF in all other cases.
Overflow Flag OF ON when the result of subtracting a negative number and
CY from a positive number is in the range 80000000 to
FFFFFFFF hex.
OFF in all other cases.
Underflow Flag UF ON when the result of subtracting a positive number and
CY from a negative number is in the range 00000000 to
7FFFFFFF hex.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

449
Symbol Math Instructions Section 3-11

Precautions When –CL(413) is executed, the Error Flag will turn OFF.
If as a result of the subtraction, the content of R, R+1 is 00000000 hex, the
Equals Flag will turn ON.
If the subtraction results in a borrow, the Carry Flag will turn ON.
If the result of subtracting a negative number and CY from a positive number
is negative (in the range 80000000 to FFFFFFFF hex), the Overflow Flag will
turn ON.
If the result of subtracting a positive number and CY from a negative number
is positive (in the range 00000000 to 7FFFFFFF hex), the Underflow Flag will
turn ON.
If as a result of the subtraction, the content of the leftmost bit of R+1 is 1, the
Negative Flag will turn ON.
Note To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction.

Examples When CIO 000000 is ON in the following example, D00111, D00110 and CY
will be subtracted from D00101 and D00100 as 8-digit signed binary values,
and the result will be output to D00121 and D00120.

If the result of the subtraction is a negative number (Mi<Su or Mi+1, Mi

<Su+1, Su), the result is output as a 2’s complement. The Carry Flag (CY) will
turn ON. To convert the 2’s complement to the true number, a program which
subtracts the result from 0 is necessary, as an input condition of the Carry
Flag (CY). The Carry Flag turning ON thus indicates that the result of the sub-
traction is negative.
Note 2’s Complement
A 2’s complement is the value obtained by subtracting each binary digit from 1
and adding one to the result.
Example: The 2’s complement for the binary number 1101 is as follows:
1111 (F hex) – 1101 (D hex) + 1 (1 hex) = 0011 (3 hex).
Example: The 2’s complement for the 4-digit hexadecimal number 3039 is as
follows:
FFFF hex – 3039 hex + 0001 hex = CFC7 hex.
Accordingly, the 2’s complement for the 4-digit hexadecimal value “a” is as fol-
lows:
FFFF hex – a hex + 0001 hex = b hex.
And to obtain the true number “a” hex from the 2’s complement “b” hex:
a hex + 10000 hex – b hex.
Example: To obtain the true number from the 2’s complement CFC& hex:
10000 hex – CFC7 hex = 3039 hex.

450
Symbol Math Instructions Section 3-11

3-11-13 BCD SUBTRACT WITHOUT CARRY: –B(414)

Purpose Subtracts 4-digit (single-word) BCD data and/or constants.
Ladder Symbol
–B(414)

Mi Mi: Minuend word

Su Su: Subtrahend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition –B(414)
Executed Once for Upward Differentiation @–B(414)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Mi Su R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants 0000 to 9999 ---
(BCD)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

451
Symbol Math Instructions Section 3-11

Description –B(414) subtracts the BCD values in Su from Mi and outputs the result to R. If
the result of the subtraction is negative, the result is output as a 10’s comple-
ment.

Mi (BCD)

– Su (BCD)

CY will turn
ON when there CY R (BCD)
is a borrow.

Flags
Name Label Operation
Error Flag ER ON when Mi is not BCD.
ON when Su is not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the subtraction results in a borrow.
OFF in all other cases.

Precautions If Mi and/or Su are not BCD, an error is generated and the Error Flag will turn
ON.
If as a result of the subtraction, the content of R is 0000 hex, the Equals Flag
will turn ON.
If an addition results in a borrow, the Carry Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00110 is subtracted from
D00100 as 4-digit BCD values, and the result will be output to D00120.

3-11-14 DOUBLE BCD SUBTRACT WITHOUT CARRY: –BL(415)

Purpose Subtracts 8-digit (double-word) BCD data and/or constants.

Ladder Symbol
–BL(415)

Mi Mi: 1st minuend word

Su Su: 1st subtrahend word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition –BL(415)
Executed Once for Upward Differentiation @–BL(415)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

452
Symbol Math Instructions Section 3-11

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Mi Su R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #99999999 ---
(BCD)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description –BL(415) subtracts the BCD values in Su and Su+1 from Mi and Mi+1 and
outputs the result to R, R+1. If the result is negative, it is output to R, R+1 as a
10’s complement.
Mi +1 Mi (BCD)

Su+1 Su (BCD)
–
CY will turn
ON when there CY R+1 R (BCD)
is a borrow.

Flags
Name Label Operation
Error Flag ER ON when Mi and/or Mi +1 are not BCD.
ON when Su and/or Su +1 are not BCD.
OFF in all other cases.

453
Symbol Math Instructions Section 3-11

Name Label Operation

Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the subtraction results in a borrow.
OFF in all other cases.

Precautions If Mi, Mi +1 and/or Su, Su +1 are not BCD, an error is generated and the Error
Flag will turn ON.
If as a result of the subtraction, the content of R, R +1 is 00000000 hex, the
Equals Flag will turn ON.
If an addition results in a borrow, the Carry Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00111 and D00110 will
be subtracted from D00101 and D00100 as 8-digit BCD values, and the result
will be output to D00121 and D00120.

If the result of the subtraction is a negative number (Mi<Su or Mi+1, Mi

<Su+1, Su), the result is output as a 10’s complement. The Carry Flag (CY)
will turn ON. To convert the 10’s complement to the true number, a program
which subtracts the result from 0 is necessary, as an input condition of the
Carry Flag (CY). The Carry Flag turning ON thus indicates that the result of
the subtraction is negative.
Note 10’s Complement
A 10’s complement is the value obtained by subtracting each digit from 9 and
adding one to the result. For example, the 10’s complement for 7556 is calcu-
lated as follows: 9999 – 7556 + 1 = 2444. For a four digit number, the 10’s
complement of A is 9999 – A + 1 = B. To obtain the true number from the 10’s
complement B: A = 10000 – B. For example, to obtain the true number from
the 10’s complement 2444: 10000 – 2444 = 7556.

Program Example 9,583,960 – 17,072,641 = –7,488,681.

In this example, the eight-digit BCD content of CIO 0121 and CIO 0120 is
subtracted from the content of CIO 0201 and CIO 0200, and the result is out-
put in eight-digit BCD to D00101 and D00100. The result is negative, so the
instruction at (2) will be executed, and the true value will then be output to
D00101 and D00100.

454
Symbol Math Instructions Section 3-11

000000
RSET
002100

−BL (1)
0200
0120
D00100
CY
−BL (2)
#00000000
D00100
D00100

CY
SET "−" display
002100

Subtraction at 1
Mi+1: CIO 0201 Mi: CIO 0200
0 9 5 8 3 9 6 0

Su+1: CIO 0121 Su: CIO 0120

– 1 7 0 7 2 6 4 1

09583960 + (100000000 – 17072641)

CY R+1: D00101 R+1: D00100

1 9 2 5 1 1 3 1 9

The Carry Flag (CY) is ON, so the result is subtracted from 0000 0000.
Subtraction at 2
0 0 0 0 0 0 0 0

Su+1: D00101 Su: D00100

– 9 2 5 1 1 3 1 9

00000000 + (100000000 – 92511319)

CY R+1: D00101 R+1: D00100
1 0 7 4 8 8 6 8 1

Final Subtraction Result

Mi+1: CIO 0201 Mi: CIO 0200
2 0 F 5 5 A 1 0

Su+1: D00101 Su: D00100

– 6 8 5 1 F 9 2 D

CY R+1: D00101 R+1: D00100

1 0 7 4 8 8 6 8 1

The Carry Flag (CY) will be turned ON, so the actual number is –7,488,681.
Because the content of D00101 and D00100 is negative, CY is used to turn
ON CIO 002100 to indicate this.

455
Symbol Math Instructions Section 3-11

3-11-15 BCD SUBTRACT WITH CARRY: –BC(416)

Purpose Subtracts 4-digit (single-word) BCD data and/or constants with the Carry Flag
(CY).
Ladder Symbol
–BC(416)

Mi Mi: Minuend word

Su Su: Subtrahend word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition –BC(416)
Executed Once for Upward Differentiation @–BC(416)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Mi Su R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to D32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #9999 ---
(BCD)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

456
Symbol Math Instructions Section 3-11

Description –BC(416) subtracts BCD values in Su and CY from Mi and outputs the result
to R. If the result is negative, it is output to R as a 2’s complement.

Mi (BCD)

Su (BCD)

– CY

CY will turn
ON when there CY R (BCD)
is a borrow.

Flags
Name Label Operation
Error Flag ER ON when Mi is not BCD.
ON when Su is not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the subtraction results in a borrow.
OFF in all other cases.

Precautions If Mi and/or Su are not BCD, an error is generated and the Error Flag will turn
ON.
If as a result of the subtraction, the content of R is 0000 hex, the Equals Flag
will turn ON.
If an addition results in a borrow, the Carry Flag will turn ON.
Note To clear the Carry Flay (CY), execute the Clear Carry (CLC(041)) instruction.

Examples When CIO 000000 is ON in the following example, D00110 and CY will be
subtracted from D00100 as 4-digit BCD values, and the result will be output to
D00120.

3-11-16 DOUBLE BCD SUBTRACT WITH CARRY: –BCL(417)

Purpose Subtracts 8-digit (double-word) BCD data and/or constants with the Carry
Flag (CY).

Ladder Symbol
–BCL(417)

Mi Mi: 1st minuend word

Su Su: 1st subtrahend word

R R: 1st result word

457
Symbol Math Instructions Section 3-11

Variations
Variations Executed Each Cycle for ON Condition –BCL(417)
Executed Once for Upward Differentiation @–BCL(417)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Mi Su R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #99999999 ---
(BCD)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description –BCL(417)subtracts the BCD values in Su, Su+1, and CY from Mi and Mi+1
and outputs the result to R, R+1. If the result is negative, it is output to R, R+1
as a 10’s complement.

Mi +1 Mi (BCD)

Su+1 Su (BCD)

– CY

CY will turn
ON when there CY R+1 R (BCD)
is a borrow.

458
Symbol Math Instructions Section 3-11

Flags
Name Label Operation
Error Flag ER ON when Mi and/or Mi +1 are not BCD.
ON when Su and/or Su +1 are not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.
Carry Flag CY ON when the subtraction results in a borrow.
OFF in all other cases.

Precautions If Mi, Mi +1 and/or Su, Su +1 are not BCD, an error is generated and the Error
Flag will turn ON.
If as a result of the subtraction, the content of R, R +1 is 00000000 hex, the
Equals Flag will turn ON.
If an subtraction results in a borrow, the Carry Flag will turn ON.
Note To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction.

Examples When CIO 000000 is ON in the following example, D00111, D00110, and CY
will be subtracted from D00101 and D00100 as 8-digit BCD values, and the
result will be output to D00121 and D00120.

If the result of the subtraction is a negative number (Mi<Su or Mi+1, Mi

<Su+1, Su), the result is output as a 10’s complement. The Carry Flag (CY)
will turn ON. To convert the 10’s complement to the true number, a program
which subtracts the result from 0 is necessary, as an input condition of the
Carry Flag (CY). The Carry Flag turning ON thus indicates that the result of
the subtraction is negative.
Note 10’s Complement
A 10’s complement is the value obtained by subtracting each digit from 9 and
adding one to the result. For example, the 10’s complement for 7556 is calcu-
lated as follows: 9999 – 7556 + 1 = 2444. For a four digit number, the 10’s
complement of A is 9999 – A + 1 = B. To obtain the true number from the 10’s
complement B: A = 10000 – B. For example, to obtain the true number from
the 10’s complement 2444: 10000 – 2444 = 7556.

3-11-17 SIGNED BINARY MULTIPLY: *(420)

Purpose Multiplies 4-digit signed hexadecimal data and/or constants.
Ladder Symbol
*(420)

Md Md: Multiplicand word

Mr Mr: Multiplier word

R R: Result word

459
Symbol Math Instructions Section 3-11

Variations
Variations Executed Each Cycle for ON Condition *(420)
Executed Once for Upward Differentiation @*(420)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Md Mr R
CIO Area CIO 0000 to CIO 6143 CIO 0000 to
CIO 6142
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D32767 D00000 to
D32766
EM Area without bank E00000 to E32767 E00000 to
E32766
EM Area with bank En_00000 to En_32767 En_00000 to
(n = 0 to C) En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description *(420) multiplies the signed binary values in Md and Mr and outputs the result
to R, R+1.

Md (Signed binary)

× Mr (Signed binary)

R +1 R (Signed binary)

460
Symbol Math Instructions Section 3-11

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When *(420) is executed, the Error Flag will turn OFF.
If as a result of the multiplication, the content of R is 0000 hex, the Equals
Flag will turn ON.
If as a result of the multiplication, the content of the leftmost bit of R+1 and R
is 1, the Negative Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00100 and D00110 will
be multiplied as 4-digit signed hexadecimal values and the result will be out-
put to D00120.

Example in Function Block Definition

In the following example, an array variable is used to get the result from the
function block as one word.
a*b→c

* Function Block Variables

Multiplicand: a (data type: INT)
a
Multiplier: b (data type: INT)
b Result: c (data type: INT)
Temporary variable: tmp (data type: WORD, 2-element array)
tmp[0]

MOV
tmp[0]

3-11-18 DOUBLE SIGNED BINARY MULTIPLY: *L(421)

Purpose Multiplies 8-digit signed hexadecimal data and/or constants.
Ladder Symbol
*L(421)

Md Md: 1st multiplicand word

Mr Mr: 1st multiplier word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition *L(421)
Executed Once for Upward Differentiation @*L(421)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

461
Symbol Math Instructions Section 3-11

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Md Mr R
CIO Area CIO 0000 to CIO 6142 CIO 0000 to
CIO 6140
Work Area W000 to W510 W000 to W508
Holding Bit Area H000 to H510 H000 to H508
Auxiliary Bit Area A000 to A958 A448 to A956
Timer Area T0000 to T4094 T0000 to T4092
Counter Area C0000 to C4094 C0000 to C4092
DM Area D00000 to D32766 D00000 to
D32764
EM Area without bank E00000 to E32766 E00000 to
E32764
EM Area with bank En_00000 to En_32766 En_00000 to
(n = 0 to C) En_32764
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description *L(421) multiplies the signed binary values in Md and Md+1 and Mr and Mr+1
and outputs the result to R, R+1, R+2, and R+3.

Md + 1 Md (Signed binary)

× Mr + 1 Mr (Signed binary)

R+3 R+2 R+1 R (Signed binary)

462
Symbol Math Instructions Section 3-11

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When *L(421) is executed, the Error Flag will turn OFF.
If as a result of the multiplication, the content of R, R+1, R+2, R+3 is 0000
hex, the Equals Flag will turn ON.
If as a result of the multiplication, the content of the leftmost bit of R+1 is 1,
the Negative Flag will turn ON.
Examples When CIO 000000 is ON in the following example, D00100, D00110, D00111,
and D00110 will be multiplied as 8-digit signed hexadecimal values and the
result will be output to D00121 and D00120.

3-11-19 UNSIGNED BINARY MULTIPLY: *U(422)

Purpose Multiplies 4-digit unsigned hexadecimal data and/or constants.
Ladder Symbol
*U(422)

Md Md: Multiplicand word

Mr Mr: Multiplier word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition *U(422)
Executed Once for Upward Differentiation @*U(422)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Md Mr R
CIO Area CIO 0000 to CIO 6143 CIO 0000 to
CIO 6142
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094

463
Symbol Math Instructions Section 3-11

Area Md Mr R
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D32767 D00000 to
D32766
EM Area without bank E00000 to E32767 E00000 to
E32766
EM Area with bank En_00000 to En_32767 En_00000 to
(n = 0 to C) En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_ 32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description *U(420) multiplies the binary values in Md and Mr and outputs the result to R,
R+1.

Md (Unsigned binary)

× Mr (Unsigned binary)

R +1 R (Unsigned binary)

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When *U(422) is executed, the Error Flag will turn OFF.
If as a result of the multiplication, the content of R, R+1 is 0000 hex, the
Equals Flag will turn ON.
If as a result of the multiplication, the content of the leftmost bit of R+1 is 1,
the Negative Flag will turn ON.
Examples When CIO 000000 is ON in the following example, D00100 and D00110 will
be multiplied as 4-digit unsigned binary values and the result will be output to
D00121 and D00120.

464
Symbol Math Instructions Section 3-11

Example in Function Block Definition

In the following example, an array variable is used to get the result from the
function block as one word.
a*b→c
Function Block Variables
Multiplicand: a (data type: UINT)
*U
Multiplier: b (data type: UINT)
a Result: c (data type: UINT)
Temporary variable: tmp (data type: WORD, 2-element array)
b
tmp[0]

MOV
tmp[0]
c

3-11-20 DOUBLE UNSIGNED BINARY MULTIPLY: *UL(423)

Purpose Multiplies 8-digit unsigned hexadecimal data and/or constants.

Ladder Symbol
*UL(423)

Md Md: 1st multiplicand word

Mr Mr: 1st multiplier word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition *UL(423)
Executed Once for Upward Differentiation @*UL(423)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Md Mr R
CIO Area CIO 0000 to CIO 6142 CIO 0000 to
CIO 6140
Work Area W000 to W510 W000 to W508
Holding Bit Area H000 to H510 H000 to H508
Auxiliary Bit Area A000 to A958 A448 to A956
Timer Area T0000 to T4094 T0000 to T4092
Counter Area C0000 to C4094 C0000 to C4092
DM Area D00000 to D32766 D00000 to
D32764

465
Symbol Math Instructions Section 3-11

Area Md Mr R
EM Area without bank E00000 to E32766 E00000 to
E32764
EM Area with bank En_00000 to En_32766 En_00000 to
(n = 0 to C) En_32764
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description *UL(423) multiplies the unsigned binary values in Md and Md+1 and Mr and
Mr+1 and outputs the result to R, R+1, R+2, and R+3.

Md + 1 Md (Unsigned binary)

× Mr + 1 Mr (Unsigned binary)

R+3 R+2 R+1 R (Unsigned binary)

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the result is 1.
OFF in all other cases.

Precautions When *UL(423) is executed, the Error Flag will turn OFF.
If as a result of the multiplication, the content of R, R+1, R+2, R+3 is 0000
hex, the Equals Flag will turn ON.
If as a result of the multiplication, the content of the leftmost bit of R+3 is 1,
the Negative Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00100, D00110, D00111,
and D00110 will be multiplied as 8-digit unsigned binary values and the result
will be output to D00123, D00122, D00121, and D00120.

466
Symbol Math Instructions Section 3-11

3-11-21 BCD MULTIPLY: *B(424)

Purpose Multiplies 4-digit (single-word) BCD data and/or constants.

Ladder Symbol
*B(424)

Md Md: Multiplicand word

Mr Mr: Multiplier word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition *B(424)
Executed Once for Upward Differentiation @*B(424)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Md Mr R
CIO Area CIO 0000 to CIO 6143 CIO 0000 to
CIO 6142
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D32767 D00000 to
D32766
EM Area without bank E00000 to E32767 E00000 to
E32766
EM Area with bank En_00000 to En_32767 En_00000 to
(n = 0 to C) En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)

467
Symbol Math Instructions Section 3-11

Area Md Mr R
Constants #0000 to #9999 ---
(BCD)
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description *B(424) multiplies the BCD content of Md and Mr and outputs the result to R,
R+1.

Md (BCD)

× Mr (BCD)

R +1 R (BCD)

Flags
Name Label Operation
Error Flag ER ON when Md is not BCD.
ON when Mr is not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.

Precautions If Md and/or Mr are not BCD, an error will be generated and the Error Flag will
turn ON.
If as a result of the multiplication, the content of R, R+1 is 0000 hex, the
Equals Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00100 and D00110 will
be multiplied as 4-digit BCD values and the result will be output to D00121
and D00120.

468
Symbol Math Instructions Section 3-11

Example in Function Block Definition

In the following example, an array variable is used to get the result from the
function block as one word.
a*b→c
Function Block Variables
Multiplicand: a (data type: WORD)
*B
Multiplier: b (data type: WORD)
a Result: c (data type: WORD)
Temporary variable: tmp (data type: WORD, 2-element array)
b
tmp[0]

MOV
tmp[0]
c

3-11-22 DOUBLE BCD MULTIPLY: *BL(425)

Purpose Multiplies 8-digit (double-word) BCD data and/or constants.

Ladder Symbol
*BL(425)

Md Md: 1st multiplicand word

Mr Mr: 1st multiplier word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition *BL(425)
Executed Once for Upward Differentiation @*BL(425)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Md Mr R
CIO Area CIO 0000 to CIO 6142 CIO 0000 to
CIO 6140
Work Area W000 to W510 W000 to W508
Holding Bit Area H000 to H510 H000 to H508
Auxiliary Bit Area A000 to A958 A448 to A956
Timer Area T0000 to T4094 T0000 to T4092
Counter Area C0000 to C4094 C0000 to C4092
DM Area D00000 to D32766 D00000 to
D32764
EM Area without bank E00000 to E32766 E00000 to
E32764
EM Area with bank En_00000 to En_32766 En_00000 to
(n = 0 to C) En_32764
(n = 0 to C)

469
Symbol Math Instructions Section 3-11

Area Md Mr R
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #99999999 ---
(BCD)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description *BL(425) multiplies BCD values in Md and Md+1 and Mr and Mr+1 and out-
puts the result to R, R+1, R+2, and R+3.

Md + 1 Md (BCD)

× Mr + 1 Mr (BCD)

R+3 R+2 R+1 R (BCD)

Flags
Name Label Operation
Error Flag ER ON when Md and/or Md+1 are not BCD.
ON when Mr and/or Mr +1 are not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.

Precautions If Md, Md+1 and/or Mr, Mr+1 are not BCD, an error will be generated and the
Error Flag will turn ON.
If as a result of the multiplication, the content of R, R+1, R+2, R+3 is
00000000 hex, the Equals Flag will turn ON.
Examples When CIO 000000 is ON in the following example, D00101, D00100, D00111,
and D00110 will be multiplied as 8-digit unsigned BCD values and the result
will be output to D00123, D00122, D00121 and D00120.

470
Symbol Math Instructions Section 3-11

3-11-23 SIGNED BINARY DIVIDE: /(430)

Purpose Divides 4-digit (single-word) signed hexadecimal data and/or constants.
Ladder Symbol
/(430)

Dd Dd: Dividend word

Dr Dr: Divisor word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition /(430)
Executed Once for Upward Differentiation @/(430)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Dd Dr R
CIO Area CIO 0000 to CIO 6143 CIO 0000 to
CIO 6142
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D32767 D00000 to
D32766
EM Area without bank E00000 to E32767 E00000 to
E32766
EM Area with bank En_00000 to En_32767 En_00000 to
(n = 0 to C) En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF #0001 to #FFFF ---
(binary) (binary)
Data Registers DR0 to DR15 ---

471
Symbol Math Instructions Section 3-11

Area Dd Dr R
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description /(430) divides the signed binary (16 bit) values in Dd by those in Dr and out-
puts the result to R, R+1. The quotient is placed in R and the remainder in
R+1.

Dd (Signed binary)

÷ Dr (Signed binary)

R +1 R (Signed binary)

Remainder Quotient

Flags
Name Label Operation
Error Flag ER ON when the result is 0.
OFF in all other cases.
Equals Flag = ON when as a result of the division, R is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the R is 1.
OFF in all other cases.

Precautions When the content of Dr is 0, an error will be generated and the Error Flag will
turn ON.
If as a result of the division, the content of R is 0000 hex, the Equals Flag will
turn ON.
If as a result of the division, the content of the leftmost bit of R is 1, the Nega-
tive Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00100 will be divided by
D00110 as 4-digit signed binary values and the quotient will be output to
D00120 and the remainder to D00121.

472
Symbol Math Instructions Section 3-11

Example in Function Block Definition

In the following example, an array variable is used to get the quotient and
remainder from the function block.
a / b → c ··· d
Function Block Variables
Dividend: a (data type: INT)
/
Divisor: b (data type: INT)
a Quotient: c (data type: INT)
Remainder: d (data type: INT)
b Temporary variable: tmp (data type: WORD, 2-element array)
tmp[0]

MOV

tmp[0]
c

MOV

tmp[0]
d

3-11-24 DOUBLE SIGNED BINARY DIVIDE: /L(431)

Purpose Divides 8-digit (double-word) signed hexadecimal data and/or constants.

Ladder Symbol
/L(431)

Dd Dd: 1st dividend word

Dr Dr: 1st divisor word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition /L(431)
Executed Once for Upward Differentiation @/L(431)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Dd Dr R
CIO Area CIO 0000 to CIO 6142 CIO 0000 to
CIO 6140
Work Area W000 to W510 W000 to W508
Holding Bit Area H000 to H510 H000 to H508
Auxiliary Bit Area A000 to A958 A448 to A956
Timer Area T0000 to T4094 T0000 to T4092
Counter Area C0000 to C4094 C0000 to C4092
DM Area D00000 to D32766 D00000 to
D32764
EM Area without bank E00000 to E32766 E00000 to
E32764

473
Symbol Math Instructions Section 3-11

Area Dd Dr R
EM Area with bank En_00000 to En_32766 En_00000 to
(n = 0 to C) En_32764
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #00000001 to ---
#FFFFFFFF #FFFFFFFF
(binary) (binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description /L(431) divides the signed binary values in Dd and Dd+1 by those in Dr and
Dr+1 and outputs the result to R, R+1, R+2, and R+3. The quotient is output
to R and R+1 and the remainder is output to R+2 and R+3.

Dd + 1 Dd (Signed binary)

÷ Dr + 1 Dr (Signed binary)

R+3 R+2 R+1 R (Signed binary)

Remainder Quotient

Flags
Name Label Operation
Error Flag ER ON when the result is 0.
OFF in all other cases.
Equals Flag = ON when as a result of the division, R+1, R is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the R+1, R is 1.
OFF in all other cases.

Precautions When the remainder of the result, R+3, R+2 is 0,the Error Flag will turn ON.
If as a result of the division, the content of R+1, R is 00000000 hex, the
Equals Flag will turn ON.
If as a result of the division, the content of the leftmost bit of R+1, R is 1, the
Negative Flag will turn ON.
Examples When CIO 000000 is ON in the following example, D00101 and D00100 are
divided by D00111 and D00110 as 8-digit signed hexadecimal values and the

474
Symbol Math Instructions Section 3-11

quotient will be output to D00121 and D00120 and the remainder to D00123
and D00122.

3-11-25 UNSIGNED BINARY DIVIDE: /U(432)

Purpose Divides 4-digit (single-word) unsigned hexadecimal data and/or constants.

Ladder Symbol
/U(432)

Dd Dd: Dividend word

Dr Dr: Divisor word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition /U(432)
Executed Once for Upward Differentiation @/U(432)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Dd Dr R
CIO Area CIO 0000 to CIO 6143 CIO 0000 to
CIO 6142
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D32767 D00000 to
D32766
EM Area without bank E00000 to E32767 E00000 to
E32766
EM Area with bank En_00000 to En_32767 En_00000 to
(n = 0 to C) En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)

475
Symbol Math Instructions Section 3-11

Area Dd Dr R
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF #0001 to #FFFF ---
(binary) (binary)
Data Registers DR0 to 15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description /U(432) divides the unsigned binary values in Dd by those in Dr and outputs
the quotient to R and the remainder to R+1.

Dd (Unsigned binary)

÷ Dr (Unsigned binary)

R +1 R (Unsigned binary)

Remainder Quotient

Flags
Name Label Operation
Error Flag ER ON when the result is 0.
OFF in all other cases.
Equals Flag = ON when as a result of the division, R is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the R is 1.
OFF in all other cases.

Precautions If as a result of the division, the content of R+1 is 0, the Error Flag will turn
ON.
If as a result of the division, the content of R is 0000 hex, the Equals Flag will
turn ON.
If as a result of the division, the content of the leftmost bit of R is 1, the Nega-
tive Flag will turn ON.
Examples When CIO 000000 is ON in the following example, D00100 will be divided by
D00110 as 4-digit unsigned binary values and the quotient will be output to
D00120 and the remainder will be output to D00121.

476
Symbol Math Instructions Section 3-11

Example in Function Block Definition

In the following example, an array variable is used to get the quotient and
remainder from the function block.
a / b → c ··· d
Function Block Variables
Dividend: a (data type: UINT)
/U
Divisor: b (data type: UINT)
a Quotient: c (data type: UINT)
Remainder: d (data type: UINT)
b Temporary variable: tmp (data type: WORD, 2-element array)
tmp[0]

MOV
tmp[0]

MOV
tmp[0]

3-11-26 DOUBLE UNSIGNED BINARY DIVIDE: /UL(433)

Purpose Divides 8-digit (double-word) unsigned hexadecimal data and/or constants.

Ladder Symbol
/UL(433)

Dd Dd: 1st dividend word

Dr Dr: 1st divisor word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition /UL(433)
Executed Once for Upward Differentiation @/UL(433)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Dd Dr R
CIO Area CIO 0000 to CIO 6142 CIO 0000 to
CIO 6140
Work Area W000 to W510 W000 to W508
Holding Bit Area H000 to H510 H000 to H508
Auxiliary Bit Area A000 to A958 A448 to A956
Timer Area T0000 to T4094 T0000 to T4092
Counter Area C0000 to C4094 C0000 to C4092
DM Area D00000 to D32766 D00000 to
D32764
EM Area without bank E00000 to E32766 E00000 to
E32764

477
Symbol Math Instructions Section 3-11

Area Dd Dr R
EM Area with bank En_00000 to En_32766 En_00000 to
(n = 0 to C) En_32764
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #00000001 to ---
#FFFFFFFF #FFFFFFFF
(binary) (binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description /UL(433) divides the unsigned binary values in Dd and Dd+1 by those in Dr
and Dr+1 and outputs the quotient to R, R+1 and the remainder to R+2, and
R+3.

Dd + 1 Dd (Unsigned binary)

÷ Dr + 1 Dr (Unsigned binary)

R+3 R+2 R+1 R (Unsigned binary)

Remainder Quotient

Flags
Name Label Operation
Error Flag ER ON when the result is 0.
OFF in all other cases.
Equals Flag = ON when as a result of the division R+1, R is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the R+1, R is 1.
OFF in all other cases.

Precautions When the content of Dr, Dr+1 is 0, the Error Flag will turn ON.
If as a result of the division, the content of R, R+1, is 0000 hex, the Equals
Flag will turn ON.
If as a result of the division, the content of the leftmost bit of R+1 is 1, the Neg-
ative Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00100 and D00101 will
be divided by D00111 and D00110 as 8-digit unsigned hexadecimal values

478
Symbol Math Instructions Section 3-11

and the quotient will be output to D00121 and D00120 and the remainder to
D00123 and D00122.

3-11-27 BCD DIVIDE: /B(434)

Purpose Divides 4-digit (single-word) BCD data and/or constants.

Ladder Symbol
/B(434)

Dd Dd: Dividend word

Dr Dr: Divisor word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition /B(434)
Executed Once for Upward Differentiation @/B(434)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Dd Dr R
CIO Area CIO 0000 to CIO 6143 CIO 0000 to
CIO 6142
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D32767 D00000 to
D32766
EM Area without bank E00000 to E32767 E00000 to
E32766
EM Area with bank En_00000 to En_32767 En_00000 to
(n = 0 to C) En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)

479
Symbol Math Instructions Section 3-11

Area Dd Dr R
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #9999 #0001 to #9999 ---
(BCD) (BCD)
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description /B(434) divides the BCD content of Dd by those of Dr and outputs the quotient
to R and the remainder to R+1.

Dd (BCD)

÷ Dr (BCD)

R +1 R (BCD)

Remainder Quotient

Flags
Name Label Operation
Error Flag ER ON when Dd is not BCD.
ON when Dr is not BCD.
ON when the remainder is 0.
OFF in all other cases.
Equals Flag = ON when R is 0.
OFF in all other cases.

Precautions If Dd or Dr are not BCD or if the remainder (R+1) is 0, an error will be gener-
ated and the Error Flag will turn ON.
If as a result of the division, the content of R is 0000 hex, the Equals Flag will
turn ON.
If as a result of the division, the leftmost bit of R is 1, the Negative Flag will
turn ON.
Examples When CIO 000000 is ON in the following example, D00100 will be divided by
D00110 as 4-digit BCD values and the quotient will be output to D00120 and
the remainder to D00120.

Example in Function Block Definition

In the following example, an array variable is used to get the quotient and
remainder from the function block.

480
Symbol Math Instructions Section 3-11

a / b → c ··· d
Function Block Variables
Dividend: a (data type: WORD)
/B
Divisor: b (data type: WORD)
a Quotient: c (data type: WORD)
Remainder: d (data type: WORD)
b Temporary variable: tmp (data type: WORD, 2-element array)
tmp[0]

MOV

tmp[0]
c

MOV
tmp[0]

3-11-28 DOUBLE BCD DIVIDE: /BL(435)

Purpose Divides 8-digit (double-word) BCD data and/or constants.

Ladder Symbol
/BL(435)

Dd Dd: 1st dividend word

Dr Dr: 1st divisor word

R R: 1st result word

Variations
Variations Executed Each Cycle for ON Condition /BL(435)
Executed Once for Upward Differentiation @/BL(435)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program Step program Subroutines Interrupt tasks
areas areas
OK OK OK OK

Operand Specifications
Area Dd Dr R
CIO Area CIO 0000 to CIO 6142 CIO 0000 to
CIO 6140
Work Area W000 to W510 W000 to W508
Holding Bit Area H000 to H510 H000 to H508
Auxiliary Bit Area A000 to A958 A448 to A956
Timer Area T0000 to T4094 T0000 to T4092
Counter Area C0000 to C4094 C0000 to C4092
DM Area D00000 to D32766 D00000 to
D32764
EM Area without bank E00000 to E32766 E00000 to
E32764
EM Area with bank En_00000 to En_32766 En_00000 to
(n = 0 to C) En_32764
(n = 0 to C)

481
Symbol Math Instructions Section 3-11

Area Dd Dr R
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #00000001 to ---
#99999999 #99999999
(BCD) (BCD)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description /BL(435) divides BCD values in Dd and Dd+1 by those in Dr and Dr+1 and
outputs the quotient to R, R+1 and the remainder to R+2, R+3.

Dd + 1 Dd (BCD)

÷ Dr + 1 Dr (BCD)

R+3 R+2 R+1 R (BCD)

Remainder Quotient

Flags
Name Label Operation
Error Flag ER ON when Dd, Dd+1 is not BCD.
ON when Dr, Dr +1 is not BCD.
OFF in all other cases.
Equals Flag = ON when the result is 0.
OFF in all other cases.

Precautions If Dd, Dd+1 and/or Dr, Dr+1 are not BCD or the content of Dr, Dr+1 is 0, an
error will be generated and the Error Flag will turn ON.
If as a result of the division, the content of R, R+1 is 00000000 hex, the
Equals Flag will turn ON.

Examples When CIO 000000 is ON in the following example, D00101 and D00100 will
be divided by D00111 and D00110 as 8-digit BCD values and the quotient will
be output to D00121 and D00120 and the remainder to D00123 and D00122.

482
Conversion Instructions Section 3-12

3-12 Conversion Instructions

This section describes instructions used for data conversion.
Instruction Mnemonic Function code Page
BCD TO BINARY BIN 023 483
DOUBLE BCD TO DOUBLE BINL 058 485
BINARY
BINARY TO BCD BCD 024 487
DOUBLE BINARY TO DOUBLE BCDL 059 489
BCD
2’S COMPLEMENT NEG 160 491
DOUBLE 2’S COMPLEMENT NEGL 161 493
16-BIT TO 32-BIT SIGNED SIGN 600 494
BINARY
DATA DECODER MLPX 076 496
DATA ENCODER DMPX 077 500
ASCII CONVERT ASC 086 504
ASCII TO HEX HEX 162 508
COLUMN TO LINE LINE 063 512
LINE TO COLUMN COLM 064 514
SIGNED BCD TO BINARY BINS 470 517
DOUBLE SIGNED BCD TO BISL 472 520
BINARY
SIGNED BINARY TO BCD BCDS 471 523
DOUBLE SIGNED BINARY TO BDSL 473 525
BCD
GRAY CODE CONVERSION GRY 474 529
FOUR-DIGIT NUMBER TO STR4 601 534
ASCII
EIGHT-DIGIT NUMBER TO STR8 602 537
ASCII
SIXTEEN-DIGIT NUMBER TO STR16 603 539
ASCII
ASCII TO FOUR-DIGIT NUM- NUM4 604 541
BER
ASCII TO EIGHT-DIGIT NUM- NUM8 605 544
BER
ASCII TO SIXTEEN-DIGIT NUM16 606 545
NUMBER

3-12-1 BCD TO BINARY: BIN(023)

Purpose Converts BCD data to binary data.

Ladder Symbol
BIN(023)

S S: Source word

R R: Result word

483
Conversion Instructions Section 3-12

Variations
Variations Executed Each Cycle for ON Condition BIN(023)
Executed Once for Upward Differentiation @BIN(023)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BIN(023) converts the BCD data in S to binary data and writes the result to R.

(BCD) R (BIN)

Flags
Name Label Operation
Error Flag ER ON if the content of S is not BCD.
OFF in all other cases.
Equals Flag = ON if the result is 0000.
OFF in all other cases.
Negative Flag N OFF

484
Conversion Instructions Section 3-12

Example The following diagram shows an example BCD-to-binary conversion.

R
×103 ×102 ×101 ×100 ×163 ×162 ×161 ×160

In this example, N words of BCD data is converted to binary data.

If N = 3, the three words of BCD starting from D00010 will be converted to
binary data one word at a time when CIO 00000 turns ON. The resulting
binary data will be stored starting from D00100.
00000
MOVR
D10
IR0 D00010 BCD#0100
D00011 BCD#0200
MOVR D00012 BCD#0300
D100
IR1 BCD

FOR BIN
&3
D00100 Decimal &100 (Hexadecimal #0064)
00000
BIN D00101 Decimal &200 (Hexadecimal #00C8)
,IR0+ D00102 Decimal &300 (Hexadecimal #012C)
,IR1+

NEXT

3-12-2 DOUBLE BCD TO DOUBLE BINARY: BINL(058)

Purpose Converts 8-digit BCD data to 8-digit hexadecimal (32-bit binary) data.

Ladder Symbol
BINL(058)

S S: First source word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition BINL(058)
Executed Once for Upward Differentiation @BINL(058)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766

485
Conversion Instructions Section 3-12

Area S R
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BINL(058) converts the 8-digit BCD data in S and S+1 to 8-digit hexadecimal
(32-bit binary) data and writes the result to R and R+1.
S+1 S R+1 R

(BCD) (BCD) (BIN) (BIN)

Flags
Name Label Operation
Error Flag ER ON if the contents of S+1, S are not BCD.
OFF in all other cases.
Equals Flag = ON if the result is 0.
OFF in all other cases.
Negative Flag N OFF

Examples The following diagram shows an example of 8-digit BCD-to-binary conversion.

R+1 R

×107×106×105×104×103×102×101×100 ×167×166×165×164×163 ×162×161×160

When CIO 000000 is ON in the following example, the 8-digit BCD value in
CIO 0010 and CIO 0011 is converted to hexadecimal and stored in D00200
and D00201.

486
Conversion Instructions Section 3-12

S+1: CIO 0011 S: CIO 0010

0 0 2 0 0 0 5 0 200050=3X164+13X162+7X161+2X160
x107 x106 x105 x104 x103 x102 x101 x100

0 0 0 3 0 D 7 2
x167 x166 x165 x164 x163 x162 x161 x160
R+1: D00201 R: D00200

3-12-3 BINARY TO BCD: BCD(024)

Purpose Converts a word of binary data to a word of BCD data.

Ladder Symbol
BCD(024)

S S: Source word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition BCD(024)
Executed Once for Upward Differentiation @BCD(024)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands S: Source Word

S must be between 0000 and 270F hexadecimal (0000 and 9999 decimal).
Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)

487
Conversion Instructions Section 3-12

Area S R
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BCD(024) converts the binary data in S to BCD data and writes the result to
R.

(BIN) R (BCD)

Flags
Name Label Operation
Error Flag ER ON if the content of S exceeds 270F (9999 decimal).
OFF in all other cases.
Equals Flag = ON if the result is 0000.
OFF in all other cases.

Precautions The content of S must not exceed 270F (9999 decimal).

Example The following diagram shows an example BCD-to-binary conversion.

R
×163 ×162 ×161 ×160 ×103 ×102 ×101 ×100

In this example, N words of binary data is converted to BCD data.

If N = 3, the three words of binary starting from D00010 will be converted to
binary data one word at a time when CIO 00000 turns ON. The resulting BCD
data will be stored starting from D00100.

488
Conversion Instructions Section 3-12

00000
MOVR
D10
IR0 D00010 Decimal &100 (Hexadecimal #0064)
D00011 Decimal &200 (Hexadecimal #00C8)
MOVR D00012 Decimal &300 (Hexadecimal #012C)
D100
IR1 BIN

FOR BCD
&3
D00100 BCD #0100
00000
BCD D00101 BCD #0200
,IR0+ D00102 BCD #0300
,IR1+

NEXT

3-12-4 DOUBLE BINARY TO DOUBLE BCD: BCDL(059)

Purpose Converts 8-digit hexadecimal (32-bit binary) data to 8-digit BCD data.

Ladder Symbol

BCDL(059)

S S: First source word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition BCDL(059)
Executed Once for Upward Differentiation @BCDL(059)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands S: First Source Word

The content of S+1 and S must be between 0000 0000 and 05F5 E0FF hexa-
decimal (0000 0000 and 9999 9999 decimal).
Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766

489
Conversion Instructions Section 3-12

Area S R
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BCDL(059) converts the 8-digit hexadecimal (32-bit binary) data in S and S+1
to 8-digit BCD data and writes the result to R and R+1.
S+1 S R+1 R

(BCD) (BCD) (BIN) (BIN)

Flags
Name Label Operation
Error Flag ER ON if the contents of S and S+1 exceed 05F5 E0FF
(9999 9999 decimal).
OFF in all other cases.
Equals Flag = ON if the result is 0.
OFF in all other cases.

Precautions The content of S+1 and S must not exceed 05F5 E0FF (9999 9999 decimal).
Examples The following diagram shows an example of 8-digit BCD-to-binary conversion.

R+1 R

×167×166×165×164 ×163×162×161×160 ×107×106×105×104×103 ×102×101×100

When CIO 000000 is ON in the following example, the hexadecimal value in

CIO 0011 and CIO 0010 is converted to a BCD value and stored in D00200
and D00201.

490
Conversion Instructions Section 3-12

S+1: CIO 0011 S: CIO 0010

MBS 0 0 2 D 3 2 0 A LSB
x167 x166 x165 x164 x163 x162 x161 x160
2X165 +13X164+3X163+2X162+10=2961930

R+1: D00101 R: D00100

MBS 0 2 9 6 1 9 3 0 LSB
7 x106 x105 x104 x103 x102 x101 x100
x10

3-12-5 2’S COMPLEMENT: NEG(160)

Purpose Calculates the 2’s complement of a word of hexadecimal data.

Ladder Symbol
NEG(160)

S S: Source word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition NEG(160)
Executed Once for Upward Differentiation @NEG(160)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)

491
Conversion Instructions Section 3-12

Area S R
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NEG(160) calculates the 2’s complement of S and writes the result to R. The
2’s complement calculation basically reverses the status of the bits in S and
adds 1.
2's complement
(Complement + 1)
(S) (R)

Note This operation (reversing the status of the bits and adding 1) is equivalent to
subtracting the content of S from 0000.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result is 0000.
OFF in all other cases.
Negative Flag N ON if bit 15 of the result is ON.
OFF in all other cases.

Note The result for 8000 hex will be 8000 hex.

Example When CIO 000000 is ON in the following example, NEG(160) calculates the
2’s complement of the content of D00100 and writes the result to D00200.

Actual Equivalent
calculation subtraction

Reverse bit status

−)
Add 1

492
Conversion Instructions Section 3-12

3-12-6 DOUBLE 2’S COMPLEMENT: NEGL(161)

Purpose Calculates the 2’s complement of two words of hexadecimal data.
Ladder Symbol
NEGL(161)

S S: First source word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition NEGL(161)
Executed Once for Upward Differentiation @NEGL(161)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Note R and R+1 must be in the same data area.

493
Conversion Instructions Section 3-12

Description NEGL(161) calculates the 2’s complement of S+1 and S and writes the result
to R+1 and R. The 2’s complement calculation basically reverses the status of
the bits in S+1 and S and adds 1.
2's complement
(Complement + 1)
(S+1, S) (R+1, R)

Note This operation (reversing the status of the bits and adding 1) is equivalent to
subtracting the content of S+1 and S from 0000 0000.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result is 0000 0000.
OFF in all other cases.
Negative Flag N ON if bit 15 of R+1 is ON.
OFF in all other cases.

Note The result for 8000 hex will be 8000 hex.

Example When CIO 000000 is ON in the following example, NEGL(161) calculates the
2’s complement of the content of D00101 and D00100 and writes the result to
D00201 and D00200.

Actual Equivalent
calculation subtraction

Reverse bit status

−)
Add 1

3-12-7 16-BIT TO 32-BIT SIGNED BINARY: SIGN(600)

Purpose Expands a 16-bit signed binary value to its 32-bit equivalent.
Ladder Symbol
SIGN(600)

S S: Source word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition SIGN(600)
Executed Once for Upward Differentiation @SIGN(600)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

494
Conversion Instructions Section 3-12

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6143 CIO 0000 to CIO 6142
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D32767 D00000 to D32766
EM Area without bank E00000 to E32767 E00000 to E32766
EM Area with bank En_00000 to En_32767 En_00000 to En_32766
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Note R and R+1 must be in the same data area.

Description SIGN(600) converts the 16-bit signed binary number in S to its 32-bit signed
binary equivalent and writes the result in R+1 and R.
The conversion is accomplished by copying the content of S to R and writing
FFFF to R+1 if bit 15 of S is 1 or writing 0000 to R+1 if bit 15 of S is 0.

Source word (S)

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
If bit 15 of S is 1, FFFF is transferred to R+1. The content of S is
If bit 15 of S is 0, 0000 is transferred to R+1. transferred "as is" to R.

2nd result word (R+1) 1st result word (R)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

495
Conversion Instructions Section 3-12

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result is 0000 0000.
OFF in all other cases.
Negative Flag N ON if bit 15 of R+1 is ON.
OFF in all other cases.

Example When CIO 000000 is ON in the following example, SIGN(600) converts the
16-bit signed binary content of D00100 (#8000 = –32,768 decimal) to its 32-
bit equivalent (#FFFF 8000 = –32,768 decimal) and writes that result to
D00201 and D00200.

Example: 8000 Hex

3-12-8 DATA DECODER: MLPX(076)

Purpose Reads the numerical value in the specified digit (or byte) in the source word,
turns ON the corresponding bit in the result word (or 16-word range), and
turns OFF all other bits in the result word (or 16-word range).

Ladder Symbol
MLPX(076)

S S: Source word

C C: Control word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition MLPX(076)
Executed Once for Upward Differentiation @MLPX(076)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands S: Source Word

The data in the source word indicates the location of the bit(s) that will be
turned ON.
C: Control Word
The control word specifies whether MLPX(076) will perform a 4-to-16 bit con-
version or an 8-to-256 bit conversion, the number of digits or bytes to be con-
verted, and the starting digit or byte.

496
Conversion Instructions Section 3-12

Digit number: 3 2 1 0
0
Specifies the first digit/byte to be converted
4-to-16: 0 to 3 (digit 0 to 3)
8-to-256: 0 or 1 (byte 0 or 1)

Number of digits/bytes to be converted

4-to-16: 0 to 3 (1 to 4 digits)
8-to-256: 0 or 1 (1 or 2 bytes)
Conversion process
0: 4-to-16 bits (digit to word)
1: 8-to-256 bits (byte to 16-word range)

R: First result word

There can be anywhere from 1 to 32 result words, depending upon the type of
conversion process and number of digits/bytes being converted. The result
words must be in the same data area.

Operand Specifications
Area S C R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- Specified values ---
only
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description MLPX(076) can perform 4-to-16 bit or 8-to-256 bit conversions. Set the left-
most digit of C to 0 to specify 4-to-16 bit conversion and set it to 1 to specify 8-
to-256 bit conversion.
4-to-16 bit Conversion
When the leftmost digit of C is 0, MLPX(076) takes the value of the specified
digit in S (0 to F) and turns ON the corresponding bit in the result word. All

497
Conversion Instructions Section 3-12

other bits in the result word will be turned OFF. Up to four digits can be con-
verted.
C

l =1 (Convert 2 digits.)

n=2 (Start with third digit.)

4-to-16 bit decoding

(Bit m of R is turned ON.)

R
R+1

When two or more digits are being converted, MLPX(076) will read the digits
in S from right to left and will wrap around to the rightmost digit after the left-
most digit, if necessary.
The following diagram shows some example values for C and the 4-to-16 bit
conversions that they produce.
C: #0010 C: #0030 C: #0031

R R R
R+1 R+1 R+1
R+2 R+2
R+3 R+3

8-to-256 bit Conversion

When the leftmost digit of C is 1, MLPX(076) takes the value of the specified
byte in S (00 to FF) and turns ON the corresponding bit in the range of 16
result words. All other bits in the result words will be turned OFF. Up to two
bytes can be converted.

C
l=1 (Convert 2 bytes.)

n=1 (Start with second byte.)

8-to-256 bit decoding

(Bit m of R to R+15 is turned ON.)

R+1 16

R+14
R+15
R+16
R+17

R+30
R+31

When two bytes are being converted, MLPX(076) will read the bytes in S from
right to left and will wrap around to the rightmost byte if the leftmost byte
(byte 1) has been specified as the starting byte.

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Conversion Instructions Section 3-12

The following diagram shows some example values for C and the 8-to-256 bit
conversions that they produce.
C: #1010 C: #1011
Digit 1 Digit 0 Digit 1 Digit 0

Flags
Name Label Operation
Error Flag ER ON if C is not within the specified ranges.
OFF in all other cases.

Examples 4-to-16 bit Conversion

When CIO 000000 is ON in the following example, MLPX(076) will convert 3
digits in S beginning with digit 1 (the second digit), as indicated by C (#0021).
The corresponding bits in D00100, D00101, and D00102 will be turned ON.

S
C
Bits 0 to 3: Starting digit (Digit 1)
R
C: # Bits 4 to 7: Number of digits (3 digits)

Digits
S: 0100

R: Digit 1 contains 6, so bit 6 is turned ON.

Digit 2 contains A, so bit 10 is turned ON.
Digit 3 contains F, so bit 15 is turned ON.

8-to-256 bit Conversion

When CIO 000000 is ON in the following example, MLPX(076) will convert the
2 bytes in S beginning with byte 1 (the leftmost byte), as indicated by C
(#1011). The corresponding bits in D00100 to D00115 and D00116 to D00131
will be turned ON.

499
Conversion Instructions Section 3-12

000000
MLPX
S 0100
K #1011
D D00100

15 12 11 8 7 4 3 0 Bits 0 to 3: Starting byte (Byte 1)

C: # 1 0 1 1
Bits 4 to 7: Number of bytes (2 bytes)

Byte 1 Byte 0
S: 0100 2 D 1 A

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D: D00100
D00101
D00102 1
Byte 1 contains 2D, so bit 13 (D)
D00103
of R+2 is turned ON.

D00115
D00116
D00117 1
D00118 Byte 0 contains 1A, so bit 10 (A)
of R+1 is turned ON.

D00131

3-12-9 DATA ENCODER: DMPX(077)

Purpose FInds the location of the first or last ON bit within the source word (or 16-word
range), and writes that value to the specified digit (or byte) in the result word.

Ladder Symbol
DMPX(077)

S S: First source word

R R: Result word

C C: Control word

Variations
Variations Executed Each Cycle for ON Condition DMPX(077)
Executed Once for Upward Differentiation @DMPX(077)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands S: First Source Word

There can be anywhere from 1 to 32 source words, depending upon the type
of conversion process and number of digits/bytes being converted. The
source words must be in the same data area.

500
Conversion Instructions Section 3-12

R: Result Word
The locations of the bits that were ON in the source word(s) are written to the
digits/bytes in R starting with the specified first digit/byte.
C: Control Word
The control word specifies whether DMPX(077) will perform a 16-to-4 bit con-
version or an 256-to-8 bit conversion, whether the leftmost or rightmost ON bit
will be encoded, the number of digits or bytes that will be converted, and the
starting digit or byte where the results will be written.
Digit number: 3 2 1 0

Specifies the first digit/byte to receive converted data.

16-to-4: 0 to 3 (digit 0 to 3)
256-to-8: 0 or 1 (byte 0 or 1)
Number of digits/bytes to be converted
16-to-4: 0 to 3 (1 to 4 digits)
256-to-8: 0 or 1 (1 or 2 bytes)

Bit to encode
0: Leftmost bit (highest bit address)
1: Rightmost bit (lowest bit address)
Conversion process
0: 16-to-4 bits (word to digit)
1: 256-to-8 bits (16-word range to byte)

Operand Specifications
Area S R C
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959 A000 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- --- Specified values
only
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

501
Conversion Instructions Section 3-12

Description DMPX(077) can perform 16-to-4 bit or 256-to-8 bit conversions. Set the left-
most digit of C to 0 to specify 16-to-4 bit conversion and set it to 1 to specify
256-to-8 bit conversion.
16-to-4 bit Conversion
When the fourth (leftmost) digit of C is 0, DMPX(077) finds the locations of the
leftmost or rightmost ON bits in up to 4 source words and writes these loca-
tions to R beginning with the specified digit. (Set the third digit of C to 0 to find
the leftmost ON bits or 1 to find the rightmost ON bits.)
C
FInds leftmost bit
(Highest bit address)

m l=1 (Convert
2 words.)

16-to-4 bit decoding

(Location of leftmost bit (m)
is written to R.) Leftmost bit

n=2 (Start with digit 2.)

When two or more digits are being converted, DMPX(077) will write the values
to the digits in R from right to left and will wrap around to the rightmost digit
after the leftmost digit, if necessary.
The following diagram shows some example values for C and the 16-to-4 bit
conversions that they produce.
C: #0011 C: #0030 C: #0013

R Digit 3 Digit 2 Digit 1 Digit 0 R Digit 3 Digit 2 Digit 1 Digit 0

R Digit 3 Digit 2 Digit 1 Digit 0

C: #0032

R Digit 3 Digit 2 Digit 1 Digit 0

502
Conversion Instructions Section 3-12

256-to-8 bit Conversion

When the fourth (leftmost) digit of C is 1, DMPX(077) finds the locations of the
leftmost (highest bit address) or rightmost (lowest bit address) ON bits in one
or two 16-word ranges of source words. The locations of these bits are written
to R beginning with the specified byte. (Set the third digit of C to 0 to find the
leftmost ON bits or 1 to find the rightmost ON bits.)

C
l =0 (Convert one 16-word range.)

Leftmost Rightmost
bit bit

Finds leftmost bit

(Highest bit address)
256-to-8 bit decoding
(The location of the leftmost bit in the
16-word range (m) is written to R.)

n=1 (Start with byte 1.)

When two bytes are being converted, DMPX(077) will write the values to the
bytes in R from right to left and will wrap around to the rightmost byte if the
leftmost byte (byte 1) has been specified as the starting byte.
The following diagram shows some example values for C and the 256-to-8 bit
conversions that they produce.
C: #1010 C: #1011

Digit 1 Digit 0 Digit 1 Digit 0

Flags
Name Label Operation
Error Flag ER ON if any of the source words contains 0000 hex (i.e., no
bit to encode).
ON if C is not within the specified ranges.
OFF in all other cases.

Precautions If the conversion data contains 0000 hex, but other data is to be encoded,
separate the conversion by using more than one DMPX(077) instructions.
DMPX(077) D0000 D0100 #0300

503
Conversion Instructions Section 3-12

DMPX(077) D0000 D0100 #0000

DMPX(077) D0001 D0100 #0001
DMPX(077) D0002 D0100 #0002
DMPX(077) D0003 D0100 #0003

Examples When CIO 000000 is ON in the following example, DMPX(077) will find the
leftmost ON bits in CIO 0100, CIO 0101, and CIO 0102 and write those loca-
tions to 3 digits in R beginning with digit 1 (the second digit), as indicated by C
(#0021).

S
R
C C: #
DMPX(077) finds the
leftmost ON bits.

S:
Starting digit
(Digit 1)

Digits

R: D00100

3-12-10 ASCII CONVERT: ASC(086)

Purpose Converts 4-bit hexadecimal digits in the source word into their 8-bit ASCII
equivalents.

Ladder Symbol
ASC(086)

S S: Source word

Di Di: Digit designator

D D: First destination word

Variations
Variations Executed Each Cycle for ON Condition ASC(086)
Executed Once for Upward Differentiation @ASC(086)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands S: Source Word

Up to four digits in the source word can be converted. The digits are num-
bered 0 to 3, right to left.

504
Conversion Instructions Section 3-12

Di: Digit Designator

The digit designator specifies various parameters for the conversion, as
shown in the following diagram.
Digit number: 3 2 1 0

Specifies the first digit in S to be converted (0 to 3).

Number of digits to be converted (0 to 3)
0: 1 digit
1: 2 digits
2: 3 digits
3: 4 digits
First byte of D to be used.
0: Rightmost byte
1: Leftmost byte
Parity 0: None
1: Even
2: Odd

D: First destination word

The converted ASCII data is written to the destination word(s) beginning with
the specified byte in D. Three destination words (D to D+3) will be required if 4
digits are being converted and the leftmost byte is selected as the first byte in
D. The destination words must be in the same data area.
Any bytes in the destination word(s) that are not overwritten with ASCII data
will be left unchanged.

Operand Specifications
Area S Di D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- Specified values ---
only
Data Registers DR0 to DR15 ---

505
Conversion Instructions Section 3-12

Area S Di D
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ASC(086) treats the contents of S as 4 hexadecimal digits, converts the des-
ignated digit(s) of S into their 8-bit ASCII equivalents, and writes this data into
the destination word(s) beginning with the specified byte in D.

Di
First digit to convert

Number of
digits (n+1)

Left (1) Right (0)

Note Refer to Appendix A in the CS/CJ-series Programming Consoles Operation

Manual (W341) for a table of extended ASCII characters.
Parity
It is possible to specify the parity of the ASCII data for use in error control dur-
ing data transmissions. The leftmost bit of each ASCII character will be auto-
matically adjusted for even, odd, or no parity.
When no parity (0) is designated, the leftmost bit will always be zero. When
even parity (1) is designated, the leftmost bit will be adjusted so that the total
number of ON bits is even. When odd parity (2) is designated, the leftmost bit
of each ASCII character will be adjusted so that there is an odd number of ON
bits. The status of the parity bit does not affect the meaning of the ASCII code.
Examples of even parity:
When adjusted for even parity, ASCII “31” (00110001) will be “B1” (10110001:
parity bit turned ON to create an even number of ON bits); ASCII “36”
(00110110) will be “36” (00110110: parity bit remains OFF because the num-
ber of ON bits is already even).
Examples of odd parity:
When adjusted for odd parity, ASCII “36” (00110110) will be “B6” (10110110:
parity bit turned ON to create an odd number of ON bits); ASCII “46”
(01000110) will be “46” (01000110: parity bit remains OFF because the num-
ber of ON bits is already odd).
Examples of Di
When two or more digits are being converted, ASC(086) will read the bytes in
S from right to left and will wrap around to the rightmost byte if necessary. The
following diagram shows some example values for Di and the conversions that
they produce.

506
Conversion Instructions Section 3-12

Di: #0011 Di: #0112 Di: #0030

Digit 3 Digit 2 Digit 1 Digit 0 Digit 3 Digit 2 Digit 1 Digit 0 Digit 3 Digit 2 Digit 1 Digit 0

Leftmost Rightmost Leftmost Leftmost Rightmost

Rightmost Leftmost Rightmost

Di: #0130
Digit 3 Digit 2 Digit 1 Digit 0

Leftmost
Leftmost Rightmost
Rightmost

Flags
Name Label Operation
Error Flag ER ON if the content of Di is not within the specified ranges.
OFF in all other cases.

Example When CIO 000000 is ON in the following example, ASC(086) converts three
hexadecimal digits in D00100 (beginning with digit 1) into their ASCII equiva-
lents and writes this data to D00200 and D00201 beginning with the leftmost
byte in D00200. In this case, a digit designator of #0121 specifies no parity,
the starting byte (when writing) = leftmost byte, the number of digits to read =
3, and the starting digit (when reading) = digit 1.

S
Di
D
Di: #

Number of digits
Starting digit

Digits

S: D00100
Starting byte
(leftmost byte)

D:

With CPU Units with unit version 4.0 of later, there are instructions to convert
4, 8, and 16 digits of numeric data to ASCII (STR4(524), STR8(527), and
STR16(528)).

507
Conversion Instructions Section 3-12

3-12-11 ASCII TO HEX: HEX(162)

Purpose Converts up to 4 bytes of ASCII data in the source word to their hexadecimal
equivalents and writes these digits in the specified destination word.
Ladder Symbol
HEX(162)

S S: First source word

Di Di: Digit designator

D D: Destination word

Variations
Variations Executed Each Cycle for ON Condition HEX(162)
Executed Once for Upward Differentiation @HEX(162)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands S: First Source Word

The contents of the source words are treated as ASCII data. Up to three
source words can be used. (Three source words will be required if 4 bytes are
being converted and the leftmost byte is selected as the first byte in S.) The
source words must be in the same data area.
Di: Digit Designator
The digit designator specifies various parameters for the conversion, as
shown in the following diagram.
Digit number: 3 2 1 0

Specifies the first digit in D to receive converted data (0 to 3).

Number of bytes to be converted (0 to 3)
0: 1 digit
1: 2 digits
2: 3 digits
3: 4 digits
First byte of S to be converted.
0: Rightmost byte
1: Leftmost byte
Parity 0: None
1: Even
2: Odd

D: Destination word
The converted hexadecimal digits are written into D from right to left, begin-
ning with the specified first digit. Any digits in the destination word that are not
overwritten with the converted data will be left unchanged.

508
Conversion Instructions Section 3-12

Operand Specifications
Area S Di D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- Specified values ---
only
Data Registers --- DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description HEX(162) treats the contents of the source word(s) as ASCII data represent-
ing hexadecimal digits (0 to 9 and A to F), converts the specified number of
bytes to hexadecimal, and writes the hexadecimal data to the destination
word beginning at the specified digit.
An error will occur if the source words contain data which is not an ASCII
equivalent of hexadecimal digits. The following table shows hexadecimal dig-
its and their ASCII equivalents (excluding parity bits).

Flags
Hexadecimal digits (4 bits) ASCII equivalent (2 hexadecimal digits)
0 to 9 30 to 39
A to F 41 to 46

Note Refer to Appendix A in the CS/CJ-series Programming Consoles Operation

Manual (W341) for a table of extended ASCII characters.

509
Conversion Instructions Section 3-12

The following diagram shows the basic operation of HEX(162) with Di=0021.
C: 0021
Di
First byte to convert

Left (1) Right (0)

Number of digits (n+1)

First digit to write

Parity
It is possible to specify the parity of the ASCII data for use in error control dur-
ing data transmissions. The leftmost bit in each byte is the parity bit. With no
parity the parity bit should always be zero, with even parity the status of the
parity bit should result in an even number of ON bits, and with odd parity the
status of the parity bit should result in an odd number of ON bits.
The following table shows the operation of HEX(162) for each parity setting.
Parity setting Operation of HEX(162)
(leftmost digit of Di)
No parity (0) HEX(162) will be executed only when the parity bit in each
byte is 0. An error will occur if a parity bit is non-zero.
Even parity (1) HEX(162) will be executed only when there is an even num-
ber of ON bits in each byte. An error will occur if a byte has
an odd number of ON bits.
Odd parity (2) HEX(162) will be executed only when there is an odd num-
ber of ON bits in each byte. An error will occur if a byte has
an even number of ON bits.

Examples of Di
When two or more bytes are being converted, HEX(162) will write the con-
verted digits to the destination word from right to left and will wrap around to
the rightmost digit if necessary. The following diagram shows some example
values for Di and the conversions that they produce.
Di: #0112 Di: #0030 Di: #0131
Leftmost Leftmost Rightmost Leftmost
Rightmost Leftmost Rightmost Leftmost Rightmost
Rightmost

Digit 3 Digit 2 Digit 1 Digit 0 Digit 3 Digit 2 Digit 1 Digit 0

Digit 3 Digit 2 Digit 1 Digit 0

510
Conversion Instructions Section 3-12

Flags
Name Label Operation
Error Flag ER ON if there is a parity error in the ASCII data.
ON if the ASCII data in the source words is not equivalent
to hexadecimal digits
ON if the content of Di is not within the specified ranges.
OFF in all other cases.

Precautions An error will occur and the Error Flag will be turned ON if there is a parity error
in the ASCII data, the ASCII data in the source words is not equivalent to
hexadecimal digits, or the content of Di is not within the specified ranges.
Examples When CIO 000000 is ON in the following example, HEX(162) converts the
ASCII data in D00100 and D00101 according to the settings of the digit desig-
nator. (Di=#0121 specifies no parity, the starting byte (when reading) = left-
most byte, the number of bytes to read = 3, and the starting digit (when
writing) = digit 1.)
HEX(162) converts three bytes of ASCII data (3 characters) beginning with
the leftmost byte of D00100 into their hexadecimal equivalents and writes this
data to D00200 beginning with digit 1.

S
Di
D Di: #

Starting byte
(leftmost byte)

S:

Number of digits
Starting digit (digit 1)
3 digits

D: D00200

When CIO 000000 is ON in the following example, HEX(162) converts the

ASCII data in D00010 beginning with the rightmost byte and writes the hexa-
decimal equivalents in D00300 beginning with digit 1.
The digit designator setting of #1011 specifies even parity, the starting byte
(when reading) = rightmost byte, the number of bytes to read = 2, and the
starting digit (when writing) = digit 1.)

511
Conversion Instructions Section 3-12

Starting digit in D: Digit 1

Number of bytes: 2
Starting byte in S: Rightmost
Parity: Even
Parity bits: Result in even parity

S: D00100

Starting byte: rightmost

Conversion
Starting digit (digit 1)

D: D00300 Not changed

Number of bytes (2 bytes)

Not changed

With CPU Units with unit version 4.0 of later, there are instructions to convert
ASCII to 4, 8, and 16 digits of numeric data (NUM4(517), NUM8(520), and
NUM16(522)).

3-12-12 COLUMN TO LINE: LINE(063)

Purpose Converts a column of bits from a 16-word range (the same bit number in 16
consecutive words) to the 16 bits of the destination word.

Ladder Symbol
LINE(063)

S S: First source word

N N: Bit number

D D: Destination word

Variations
Variations Executed Each Cycle for ON Condition LINE(063)
Executed Once for Upward Differentiation @LINE(063)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands S: First Source Word

Specifies the first source word. S and S+15 must be in the same data area.
N: Bit Number
Specifies the bit number (0000 to 000F or &0 to &15) to be copied from the
source words.

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Conversion Instructions Section 3-12

Operand Specifications
Area S N D
CIO Area CIO 0000 to CIO 0000 to CIO 6143
CIO 6128
Work Area W000 to W496 W000 to W511
Holding Bit Area H000 to H496 H000 to H511
Auxiliary Bit Area A000 to A944 A000 to A959 A448 to A959
Timer Area T0000 to T4080 T0000 to T4095
Counter Area C0000 to C4080 C0000 to C4095
DM Area D00000 to D00000 to D32767
D32752
EM Area without bank E00000 to E00000 to E32767
E32752
EM Area with bank En_00000 to En_00000 to En_32767 (n = 0 to C)
En_32752
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- #0000 to 000F ---
(binary) or &0 to
&15
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description LINE(063) copies the 16 bits with bit number N from the 16-word range S to
S+15 to the destination word D. Bit N of S+m is copied to bit m of D, i.e., bit N
of S is copied to bit 00 of D and bit N of S+15 is copied to bit 15 of D.
N
Bit Bit
15 00
S 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1
S+1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1
S+2 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1
S+3 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1
. . . .
. . . .
. . . .
S+15 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 Bit Bit
15 00

D 0 . . . 0 1 1 1

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Conversion Instructions Section 3-12

Flags
Name Label Operation
Error Flag ER ON if N is not within the specified range of 0000 to 000F.
OFF in all other cases.
Equals Flag = ON if D is 0000 after execution.
OFF in all other cases.

Example When CIO 000000 is ON in the following example, LINE(063) copies bit 5
from D00100 to D00115 to the 16 bits in D00200.

&5 N: #0005

S:

to to

D: D00200

3-12-13 LINE TO COLUMN: COLM(064)

Purpose Converts the 16 bits of the source word to a column of bits in a 16-word range
of destination words (the same bit number in 16 consecutive words).

Ladder Symbol
COLM(064)

S S: Source word

D D: First destination word

N N: Bit number

Variations
Variations Executed Each Cycle for ON Condition COLM(064)
Executed Once for Upward Differentiation @COLM(064)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands D: First Destination Word

Specifies the first destination word. D and D+15 must be in the same data
area.

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Conversion Instructions Section 3-12

N: Bit Number
Specifies the bit number (0000 to 000F or &0 to &15) to be overwritten by the
source word.

Operand Specifications
Area S D N
CIO Area CIO 0000 to CIO 0000 to CIO 0000 to
CIO 6143 CIO 6128 CIO 6143
Work Area W000 to W511 W000 to W496 W000 to W511
Holding Bit Area H000 to H511 H000 to H496 H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A944 A000 to A959
Timer Area T0000 to T4095 T0000 to T4080 T0000 to T4095
Counter Area C0000 to C4095 C0000 to C4080 C0000 to C4095
DM Area D00000 to D00000 to D00000 to
D32767 D32752 D32767
EM Area without bank E00000 to E00000 to E00000 to
E32767 E32752 E32767
EM Area with bank En_00000 to En_00000 to En_00000 to
En_32767 En_32752 En_32767
(n = 0 to C) (n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF --- #0000 to #000F
(binary) (binary) or &0 to
&15
Data Registers DR0 to DR15 --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

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Conversion Instructions Section 3-12

Description COLM(064) copies the 16 bits from S to the 16 bits with bit number N in the
16-word range D to D+15. Bit m of S is copied to bit N of D+m, i.e., bit 00 of S
is copied to bit N of D and bit 15 of S is copied to bit N of D+15.
Bit Bit
15 00

S 0 . . . . . . . 0 1 1 1

Bit Bi Bit
15 00

D 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1
D+1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1
D+2 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1
D+3 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1
. . . .
. . . .
. . . .
D+15 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0

Flags
Name Label Operation
Error Flag ER ON if N is not within the specified range of 0000 to 000F.
OFF in all other cases.
Equals Flag = ON if bit N is 0 in all 16 words D to D+15 after execution.
OFF in all other cases.

Example When CIO 000000 is ON in the following example, COLM(064) copies the 16
bits in D00200 (bits 00 through 15) to bit 5 in D00100 through D00115.

S: D00200

D:

to to

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Conversion Instructions Section 3-12

3-12-14 SIGNED BCD TO BINARY: BINS(470)

Purpose Converts one word of signed BCD data to one word of signed binary data.
Ladder Symbol
BINS(470)

C C: Control word

S S: Source word

D D: Destination word

Variations
Variations Executed Each Cycle for ON Condition BINS(470)
Executed Once for Upward Differentiation @BINS(470)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: Control Word

Specifies the signed BCD format. C must be 0000 to 0003.
Operand Specifications
Area C S D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #0003 ---
(binary)
Data Registers DR0 to DR15

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Conversion Instructions Section 3-12

Area C S D
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BINS(470) converts signed BCD data to signed binary data. First the signed
BCD data format and range in word S are checked against the setting in the
control word (C). If the source data is correct, the signed BCD data in S is
converted to signed binary and output to D. If the source data is incorrect, the
Error Flag will be turned ON and the instruction will not be executed.

Signed BCD format

specified in C

Signed BCD Signed binary

When the converted data is negative, it will be output as the 2’s complement
and the Negative Flag be will turned ON. NEG(160) can be used to determine
the absolute value of a negative signed binary number. Refer to 3-12-52’S
COMPLEMENT: NEG(160) for details.
A value of –0 in the source data will be treated as 0 and will not cause an
error. Also, the status of bits 13 to 15 of S is not checked when C=0000.
Note Some Special I/O Units output signed BCD data. Calculations using this data
will normally be easier if it is first converted to signed binary data with
BINS(470).
The control word specifies the signed BCD format as shown below.
C = 0000 (Input Data Range: –999 to 999 BCD)

3 digits BCD, 12 bits

Sign bit (0: Positive; 1: Negative)
Status of 3 bits: 0

C = 0001 (Input Data Range: –7999 to 7999 BCD)

3 digits BCD, 12 bits

3 bits of digit 4 (0 to 7)
Sign bit (0: Positive; 1: Negative)

C = 0002 (Input Data Range: –999 to 9999 BCD)

3 digits BCD, 12 bits

0 to 9: Fourth digit BCD
F: Negative (−)
A to E: Error

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Conversion Instructions Section 3-12

C = 0003 (Input Data Range: –1999 to 9999 BCD)

3 digits BCD, 12 bits

0 to 9: Fourth digit BCD
A: Negative (−1)
F: Negative (−)
B to E: Error
The following table shows the possible BCD values for each signed BCD for-
mat and the corresponding signed binary values.
Setting Signed BCD values Signed binary values
C=0000 –999 to –1 and 0 to 999 FC19 to FFFF and 0000 to 03E7
C=0001 –7999 to –1 and 0 to 7999 E0C1 to FFFF and 0000 to 1F3F
C=0002 –999 to –1 and 0 to 9999 FC19 to FFFF and 0000 to 270F
C=0003 –1999 to –1 and 0 to 9999 F831 to FFFF and 0000 to 270F

Flags
Name Label Operation
Error Flag ER ON if C is not within the specified range of 0000 to 0003.
ON if C=0002 and the leftmost digit of S is A to E.
ON if C=0003 and the leftmost digit of S is B to E.
ON if the content of S is not BCD.
OFF in all other cases.
Equals Flag = ON if D is 0000 after execution.
OFF in all other cases.
Negative Flag N ON if bit 15 of D is ON after execution.
OFF in all other cases.

Examples BCD Format 0 (C=#0000)

When CIO 000000 is ON in the following example, the signed BCD data for-
mat and range in D00100 are checked against the format specified in the con-
trol word (0000). The source data is correct, so the signed BCD data in
D00100 is converted to signed binary and output to D00200.
S: D00100
1123 Signed BCD data (–123)

D: D00200
FF85 Signed binary data

BCD Format 0 (C=#0003)

When CIO 000001 is ON in the following example, the signed BCD data for-
mat and range in D00100 are checked against the format specified in the con-
trol word (0003). The source data is correct, so the signed BCD data in
D00300 is converted to signed binary and output to D00400.
S: D00300
A369 Signed BCD data
(–1,369)

D: D00400
FAA7 Signed binary data

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Conversion Instructions Section 3-12

3-12-15 DOUBLE SIGNED BCD TO BINARY: BISL(472)

Purpose Converts double signed BCD data to double signed binary data.
Ladder Symbol
BISL(472)

C C: Control word

S S: First source word

D D: First destination word

Variations
Variations Executed Each Cycle for ON Condition BISL(472)
Executed Once for Upward Differentiation @BISL(472)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: Control Word

Specifies the signed BCD format. C must be 0000 to 0003.
Operand Specifications
Area C S D
CIO Area CIO 0000 to CIO 0000 to CIO 6142
CIO 6143
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A000 to A958 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D00000 to D32766
D32767
EM Area without bank E00000 to E00000 to E32766
E32767
EM Area with bank En_00000 to En_00000 to En_32766
En_32767 (n = 0 to C)
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #0003 ---
(binary)
Data Registers DR0 to DR15 ---

520
Conversion Instructions Section 3-12

Area C S D
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BISL(472) converts the double signed BCD data in S+1 and S to double
signed binary data and writes the result in D+1 and D. First the signed BCD
data format and range in words S+1 and S are checked against the setting in
the control word (C). If the source data is correct, the signed BCD data S+1
and S is converted to signed binary and output to D+1 and D. If the source
data is incorrect, the Error Flag will be turned ON and the instruction will not
be executed.

Signed BCD format

specified in C
Signed BCD Signed binary
Signed BCD Signed binary

When the converted data is negative, it will be output as the 2’s complement
and the Negative Flag be will turned ON. NEGL(161) can be used to deter-
mine the absolute value of a negative double signed binary number. Refer to
3-12-6 DOUBLE 2’S COMPLEMENT: NEGL(161) for details.
Values of –0 in the source data will be treated as 0 and will not cause an error.
Also, the status of bits 13 to 15 of S+1 is not checked when C=0000.
Note Some Special I/O Units output signed BCD data. Calculations using this data
will normally be easier if it is first converted to signed binary data with
BISL(472).
The control word specifies the signed BCD format as shown below.
C = 0000 (Input Data Range: –999 9999 to 999 9999 BCD)
S+1 S

7 digits BCD, 28 bits

Sign bit (0: Positive; 1: Negative)
Status of 3 bits: 0

C = 0001 (Input Data Range: –7999 9999 to 7999 9999 BCD)

S+1 S

7 digits BCD, 28 bits

3 bits of digit 8 (0 to 7)
Sign bit (0: Positive; 1: Negative)

521
Conversion Instructions Section 3-12

C = 0002 (Input Data Range: –999 9999 to 9999 9999 BCD)

S+1 S

7 digits BCD, 28 bits

0 to 9: Eighth digit BCD
F: Negative (–)
A to E: Error

C = 0003 (Input Data Range: –1999 9999 to 9999 9999 BCD)

S+1 S

7 digits BCD, 28 bits

0 to 9: Eighth digit BCD
A: Negative (–1)
F: Negative (–)
B to E: Error
The following table shows the possible BCD values for each signed BCD for-
mat and the corresponding signed binary values.
Setting Signed BCD values Signed binary values
C=0000 –999 9999 to –1 FF67 6981 to FFFF FFFF
0 to 999 9999 0000 0000 to 0098 967F
C=0001 –7999 9999 to –1 FB3B 4C01 to FFFF FFFF
0 to 7999 9999 0000 0000 to 04C4 B3FF
C=0002 –999 9999 to –1 FF67 6981 to FFFF FFFF
0 to 9999 9999 0000 0000 to 05F5 E0FF
C=0003 –1999 9999 to –1 FECE D301 to FFFF FFFF
0 to 9999 9999 0000 0000 to 05F5 E0FF

Flags
Name Label Operation
Error Flag ER ON if C is not within the specified range of 0000 to 0003.
ON if C=0002 and the leftmost digit of S+1 is A to E.
ON if C=0003 and the leftmost digit of S+1 is B to E.
ON if the content of S+1 and S is not BCD.
OFF in all other cases.
Equals Flag = ON if D+1 contains 0000 0000 after execution.
OFF in all other cases.
Negative Flag N ON if bit 15 of D+1 is ON after execution.
OFF in all other cases.

Example When CIO 000000 is ON in the following example, the double signed BCD
data format and range in D00101 and D00100 are checked against the format
specified in the control word (0002). The source data is correct, so the double
signed BCD data in D00101 and D00100 is converted to double signed binary
and output to D00201 and D00200.
S+1: D00101 S: D00100
F345 6789
Double signed BCD data
(–3,456,789)

D+1: D00201 D: D00200

FFCB 40EB Double signed binary data

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Conversion Instructions Section 3-12

3-12-16 SIGNED BINARY TO BCD: BCDS(471)

Purpose Converts one word of signed binary data to one word of signed BCD data.
Ladder Symbol
BCDS(471)

C C: Control word

S S: Source word

D D: Destination word

Variations
Variations Executed Each Cycle for ON Condition BCDS(471)
Executed Once for Upward Differentiation @BCDS(471)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand C: Control Word

Specifies the signed BCD format. C must be 0000 to 0003.
S: Source Word
Contains the signed binary data to be converted. The content of S must be
within the valid range of the BCD format specified in C.
Setting Allowed values for S
C=0000 FC19 to FFFF or 0000 to 03E7
C=0001 E0C1 to FFFF or 0000 to 1F3F
C=0002 FC19 to FFFF or 0000 to 270F
C=0003 F831 to FFFF or 0000 to 270F

D: Destination word
Contains the converted signed BCD data. See the description section below
for an explanation of the BCD formats.

Operand Specifications
Area C S D
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)

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Conversion Instructions Section 3-12

Area C S D
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #0003 ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to 1–2048 to +2047 ,IR5
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BCDS(471) converts signed binary data to signed BCD data. First the signed
binary data in word S is checked to verify that it is within the valid range for the
signed BCD format specified in the control word (C). If the source data is cor-
rect, the signed binary data in S is converted to signed BCD and output to D.
If the source data is incorrect, the Error Flag will be turned ON and the
instruction will not be executed.

Signed BCD format

specified in C
Signed binary Signed BCD

Note 1. Values of –0 in the source data will be treated as 0 and will not cause an
error.
2. Some Special I/O Units require signed BCD data inputs. BCDS(471) can
be used to convert signed binary data for output to these Units.
The control word specifies the signed BCD format that will be used for the
result, as shown below.
C = 0000 (Output Data Range: –999 to 999 BCD)

3 digits BCD, 12 bits

Sign bit (0: Positive; 1: Negative)
Status of 3 bits: 0

C = 0001 (Output Data Range: –7999 to 7999 BCD)

3 digits BCD, 12 bits

3 bits of digit 4 (0 to 7)
Sign bit (0: Positive; 1: Negative)

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Conversion Instructions Section 3-12

C = 0002 (Output Data Range: –999 to 9999 BCD)

3 digits BCD, 12 bits

0 to 9: Fourth digit BCD
F: Negative (–)

C = 0003 (Output Data Range: –1999 to 9999 BCD)

3 digits BCD, 12 bits

0 to 9: Fourth digit BCD
A: Negative (–1)
F: Negative (–)

The following table shows the possible signed binary values for each signed
BCD format. An error will occur if the source data is not within the allowed
range for the specified signed BCD format.
Setting Signed binary values Signed BCD values
C=0000 FC19 to FFFF and 0000 to 03E7 –999 to –1 and 0 to 999
C=0001 E0C1 to FFFF and 0000 to 1F3F –7999 to –1 and 0 to 7999
C=0002 FC19 to FFFF and 0000 to 270F –999 to –1 and 0 to 9999
C=0003 F831 to FFFF and 0000 to 270F –1999 to –1 and 0 to 9999

Flags
Name Label Operation
Error Flag ER ON if C is not within the specified range of 0000 to 0003.
ON if C=0000 and the source data is not within the allowed
ranges (FC19 to FFFF or 0000 to 03E7).
ON if C=0001 and the source data is not within the allowed
ranges (E0C1 to FFFF or 0000 to 1F3F).
ON if C=0002 and the source data is not within the allowed
ranges (FC19 to FFFF or 0000 to 270F).
ON if C=0003 and the source data is not within the allowed
ranges (F831 to FFFF or 0000 to 270F).
OFF in all other cases.
Equals Flag = ON if D is 0000 after execution.
OFF in all other cases.
Negative Flag N ON if C=0000 or 0001 and the result’s sign bit is ON after
execution.
ON if C=0002 and the leftmost digit of the result is F.
ON if C=0003 and the leftmost digit of the result is A or F.
OFF in all other cases.

3-12-17 DOUBLE SIGNED BINARY TO BCD: BDSL(473)

Purpose Converts double signed binary data to double signed BCD data.
Ladder Symbol
BDSL(473)

C C: Control word

S S: First source word

D D: First destination word

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Conversion Instructions Section 3-12

Variations
Variations Executed Each Cycle for ON Condition BDSL(473)
Executed Once for Upward Differentiation @BDSL(473)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Operands C: Control Word

Specifies the signed BCD format. C must be 0000 to 0003.
S: First Source Word
Source words S+1 and S contain the double signed binary data to be con-
verted. Their content must be within the valid range of the BCD format speci-
fied in C.
Setting Allowed values for S+1 and S
C=0000 FF67 6981 to FFFF FFFF or 0000 0000 to 0098 967F
C=0001 FB3B 4C01 to FFFF FFFF or 0000 0000 to 04C4 B3FF
C=0002 FF67 6981 to FFFF FFFF or 0000 0000 to 05F5 E0FF
C=0003 FECE D301 to FFFF FFFF or 0000 0000 to 05F5 E0FF

D: First destination word

Destination words D+1 and D contain the converted double signed BCD data.
See the description section below for an explanation of the BCD formats.

Operand Specifications
Area C S D
CIO Area CIO 0000 to CIO 0000 to CIO 6142
CIO 6143
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A000 to A958 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D00000 to D32766
D32767
EM Area without bank E00000 to E00000 to E32766
E32767
EM Area with bank En_00000 to En_00000 to En_32766
En_32767 (n = 0 to C)
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #0003 ---
(binary)
Data Registers DR0 to DR15 ---

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Conversion Instructions Section 3-12

Area C S D
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BDSL(473) converts double signed binary data to double signed BCD data.
First the double signed binary data in S+1 and S is checked to verify that it is
within the valid range for the signed BCD format specified in the control word
(C). If the source data is correct, the double signed binary data in S+1 and S
is converted to double signed BCD and output to D+1 and D. If the source
data is incorrect, the Error Flag will be turned ON and the instruction will not
be executed.

Signed BCD format

specified in C

Signed binary Signed BCD

Signed binary Signed BCD

Note 1. Values of –0 in the source data will be treated as 0 and will not cause an
error.
2. Some Special I/O Units require signed BCD data inputs. BDSL(473) can
be used to convert double signed binary data for output to these Units.
The control word specifies the signed BCD format that will be used for the
result, as shown below.
C = 0000 (Output Data Range: –999 9999 to 999 9999 BCD)
S+1 S

7 digits BCD, 28 bits

Sign bit (0: Positive; 1: Negative)
Status of 3 bits: 0

C = 0001 (Output Data Range: –7999 9999 to 7999 9999 BCD)

S+1 S

7 digits BCD, 28 bits

3 bits of digit 8 (0 to 7)
Sign bit (0: Positive; 1: Negative)

C = 0002 (Output Data Range: –999 9999 to 9999 9999 BCD)

S+1 S

7 digits BCD, 28 bits

0 to 9: Eighth digit BCD
F: Negative (–)

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Conversion Instructions Section 3-12

C = 0003 (Output Data Range: –1999 9999 to 9999 9999 BCD)

S+1 S

7 digits BCD, 28 bits

0 to 9: Eighth digit BCD
A: Negative (–1)
F: Negative (–)

The following table shows the possible double signed binary values for each
signed BCD format. An error will occur if the source data is not within the
allowed range for the specified signed BCD format.
Setting Signed binary values Signed BCD values
C=0000 FF67 6981 to FFFF FFFF –999 9999 to –1
0000 0000 to 0098 967F 0 to 999 9999
C=0001 FB3B 4C01 to FFFF FFFF –7999 9999 to –1
0000 0000 to 04C4 B3FF 0 to 7999 9999
C=0002 FF67 6981 to FFFF FFFF –999 9999 to –1
0000 0000 to 05F5 E0FF 0 to 9999 9999
C=0003 FECE D301 to FFFF FFFF –1999 9999 to –1
0000 0000 to 05F5 E0FF 0 to 9999 9999

Flags
Name Label Operation
Error Flag ER ON if C is not within the specified range of 0000 to 0003.
ON if C=0000 and the source data is not within the range:
FF67 6981 to FFFF FFFF or 0000 0000 to 0098 967F.
ON if C=0001 and the source data is not within the range:
FB3B 4C01 to FFFF FFFF or 0000 0000 to 04C4 B3FF.
ON if C=0002 and the source data is not within the range:
FF67 6981 to FFFF FFFF or 0000 0000 to 05F5 E0FF.
ON if C=0003 and the source data is not within the range:
FECE D301 to FFFF FFFF or 0000 0000 to 05F5 E0FF.
OFF in all other cases.
Equals Flag = ON if D is 0000 after execution.
OFF in all other cases.
Negative Flag N ON if C=0000 or 0001 and the result’s sign bit is ON after
execution.
ON if C=0002 and the leftmost digit of the result is F.
ON if C=0003 and the leftmost digit of the result is A or F.
OFF in all other cases.

Example When CIO 000000 is ON in the following example, the double signed binary
data in D00101 and D00100 are checked against the format specified in the
control word (0003). The source data is correct, so the double signed binary
data in D00101 and D00100 is converted to double signed BCD and output to
D00201 and D00200.
S+1: D00101 S: D00100
FF8B 344F Double signed binary data

D+1: D00201 D: D00200

F765 4321 Double signed BCD data
(–7,654,321)

528
Conversion Instructions Section 3-12

3-12-18 GRAY CODE CONVERT: GRY(474)

Purpose Converts the gray binary code in a specified word to standard binary data,
BCD data, or an angle at the specified resolution.
This instruction is supported by only CS/CJ-series CPU Unit Ver. 2.0 or later
(including CS1-H, CJ1-H, and CJ1M CPU Units from lot number 030201 or
later).
Ladder Symbol
GRY(474)

C C: First control word

S S: Source word

D D: First destination word

Variations
Variations Executed Each Cycle for ON Condition GRY(474)
Executed Once for Upward Differentiation @GRY(474)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands C: Control Word

Specifies the parameters for the conversion as shown below.
15 12 11 87 43 0
Do not
C use (0).

Resolution
0 or 1 to F hex (1 to 15 decimal) bits
0 hex = User specified in bits 12 to 15 of C+2.

Conversion Mode
0 hex = Binary Mode, 1 hex = BCD Mode, 2 hex = 360° Mode
Operating Mode
0 hex = Gray binary code conversion

C+1

Zero Point Compensation (0000 to 7FFF Hex (Binary Data))

Note: Zero point compensation that exceeds the resolution set in the word C of the control
data cannot be specified.

15 12 11 0
C+2

Encoder Remainder Compensation (Binary Data)

Note: The range that can be set depends on the user-specified resolution.
User-specified Resolution
0 hex = 256, 1 hex = 360, 2 hex = 720, 3 hex = 1,024, 4 to F hex = Do not use.

Note: The above setting is valid when the resolution is set to 0 hex in bits 00 to 03 of C.

529
Conversion Instructions Section 3-12

S: Source Word
Contains the gray binary code to be converted. The range must be within the
number of bits determined by the resolution specified in bits 00 to 03 of C. All
bits outside of the number of bits for the specified resolution will be ignored.
For example, if the specified resolution is 08 hex and S contains FFFF hex,
the gray binary code will be taken as 00FF hex.

D: First destination word

Destination words D+1 and D contain the results of converting the gray binary
code at the resolution specified in bits 00 to 03 of the control data word C and
the conversion mode specified in bits 04 to 07 of the control data word C. The
leftmost word is output to D+1 and the rightmost word is output to D. The
ranges of data that are output are as follows:
Binary Mode: 0000 0000 to 0000 7FFF hex
BCD Mode: 0000 0000 to 0003 2767
360° Mode: 0000 0000 to 0000 3599
(0.0° to 359.9° in 0.1° increments, BCD)

D Rightmost word

D+1 Leftmost word

Operand Specifications
Area C S D
CIO Area CIO 0000 to CIO 0000 to CIO 0000 to
CIO 6142 CIO 6143 CIO 6142
Work Area W000 to W510 W000 to W511 W000 to W510
Holding Bit Area H000 to H510 H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A958 A000 to A959 A448 to A958
Timer Area T0000 to T4094 T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4094 C0000 to C4095 C0000 to C4094
DM Area D00000 to D00000 to D00000 to
D32766 D32767 D32766
EM Area without bank E00000 to E00000 to E00000 to
E32766 E32767 E32766
EM Area with bank En_00000 to En_00000 to En_00000 to
En_32766 En_32767 En_32766
(n = 0 to C) (n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- #0000 to #FFFF ---
(binary)
Data Registers --- DR0 to DR15 ---

530
Conversion Instructions Section 3-12

Area C S D
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description GRY(474) converts the gray binary code in the word specified in S at the res-
olution specified in C using one of the following conversion modes (binary,
BCD, or 360°), also specified in C, and places the results in D and D+1.
Conversion mode Function
Binary Mode Gray binary code is converted to binary data between
0000 0000 and 0000 7FFF hex. Zero point offset and remainder
compensation is applied and then the result is output to D and
D+1.
BCD Mode Gray binary code is converted to BCD data. Zero point offset
and remainder compensation is applied, the data is converted
to BCD between 0000 0000 and 0003 2767, and then the result
is output to D and D+1.
360° Mode Gray binary code is converted to BCD data. Zero point offset
and remainder compensation is applied, the data is converted
to an angle between 0000 0000 and 0000 3599 (0.0° to 359.9°
in 0.1° increments), and then the result is output to D and D+1.

Note 1. GRY(474) is normally used when inputting, through a DC Input Unit, a par-
allel signal (2n) from an absolute encoder that outputs a gray binary code.
2. If the word specified for S is allocated to an Input Unit, the input data con-
verted by GRY(474) will be for the gray binary code from the previous CPU
Unit cycle, i.e., it will be one cycle time old.

Restrictions The following restrictions apply to GRY(474).

■ Restrictions on the CPU Unit

GRY(474) can be used only for the following models of CPU Unit and only for
CPU Units manufactured on or after 1 February 2003 (lot number 030201 or
later, including CPU Unit Ver. 2.0 or later).
• CJ1H-CPU@@H-R
• CJ1M-CPU@@
• CJ1G-CPU@@H
• CJ1H-CPU@@H
• CS1G-CPU@@H
• CS1H-CPU@@H
• CS1D-CPU@@S
The manufacturing date can be confirmed using the lot number given on the
side or bottom of the CPU Unit. Lot numbers indicate the manufacturing date
as follows:
YYMMDD nnnn
YY = Rightmost two digits of the year, MM = Month as a numeric value,
DD = Day of month, nnnn = Serial number
Note If GRY(474) is transferred to a CPU Unit that does not support it and the pro-
gram is read from a Programming Console, “?” will be displayed for GRY(474)
to indicate an illegal instruction. If GRY(474) is executed with an ON input

531
Conversion Instructions Section 3-12

condition in a CPU Unit that does not support it, an error will occur and pro-
gram execution will stop.

■ Restrictions on the CX-Programmer

GRY(474) can be used only with CX-Programmer version 3.2 or later.

Flags
Name Label Operation
Error Flag ER ON if bits 12 to 15 of C are not 0 hex (operating mode =
gray binary code conversion).
ON if the zero point offset in C+1 is not within the specified
resolution (including user-specified resolutions).
ON if bits 04 to 07 of C are not 0 hex (= Binary Mode),
1 hex (= BCD Mode), or 2 hex (= 360° Mode).
ON if the specified encoder remainder compensation
exceeds the set user-specified resolution when bits 00 to
03 of C are 0 hex (= user-specified resolution).
ON if the converted binary value is less than the encoder
remainder compensation when bits 00 to 03 of C are 0 hex
(= user-specified resolution).
ON if the converted binary value is less than the resolution
when bits 00 to 03 of C are 0 hex (= user-specified resolu-
tion).
OFF in all other cases.
Equals Flag = OFF in all cases.
Negative Flag N OFF in all cases.

Examples When CIO 000000 is ON in the following example, the gray binary code in
CIO 0010 is converted according to the settings in the control data in D00000
to D00002 and the result is output to D00200 and D00201.
000000
GRY

C D00000

S 0010

D D00200

532
Conversion Instructions Section 3-12

■ Example 1: Converting to Binary Data with an 8-bit Resolution and Zero

Point Offset of 001A Hex
15 12 11 87 43 0
C: D00000 0 0 0 8

Resolution: 8-bit
Conversion mode: Binary Mode
Operating mode: Gray binary code conversion

C+1: D00001 001A

Zero point offset: 001A hex

C+2: D00002 0 000

User-specified resolution: Not used.

S: 0010 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 Gray binary code

Converted and offset.

D: D00200 0017 Result of binary conversion and offsetting stored.

D+1: D00201 0000

■ Example 2: Converting to Angle Data with a 10-bit Resolution and Zero

Point Offset of 0151 Hex
15 12 11 87 43 0
C: D00000 0 0 2 A

Resolution: 10-bit
Conversion mode: 360° Mode
Operating mode: Gray binary code conversion
C+1: D00001 0151
Zero point offset: 0151 hex

C+2: D00002 0 000

User-specified resolution: Not used.

S: 0010 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 Gray binary code

Converted and offset.

D: D00200 3488 Angle data stored.

D+1: D00201 0000

533
Conversion Instructions Section 3-12

■ Example 3: Converting to BCD Data with for an OMRON E6C2-AG5C

Absolute Encoder (Resolution: 360/rotation, Encoder Remainder
Compensation: 76) and Zero Point Offset of 0000 Hex
15 12 11 87 43 0
C: D00000 0 0 1 0

Resolution: User-specified
Conversion mode: BCD Mode
Operating mode: Gray binary code conversion

C+1: D00001 0000

Zero point offset: 0000 hex

C+2: D00002 1 04C

User-specified resolution: 360, Encoder remainder compensation: 04C hex (76 decimal)

S: 0010 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 Gray binary code

Converted and offset.

D: D00200 0100 Result of BCD conversion and offsetting stored.

D+1: D00201 0000

■ Example 4: Converting to BCD Data with for an OMRON E6C2-AG5C

Absolute Encoder (Resolution: 360/rotation, Encoder Remainder
Compensation: 76) and Zero Point Offset of 000A Hex
15 12 11 87 43 0
C: D00000 0 0 1 0

Resolution: User-specified
Conversion mode: BCD Mode
Operating mode: Gray binary code conversion

C+1: D00001 000A

Zero point offset: 000A hex

C+2: D00002 1 04C

User-specified resolution: 360, Encoder remainder compensation: 04C hex (76 decimal)

S: 0010 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 Gray binary code

Converted and offset.

D: D00200 0100 Result of BCD conversion and offsetting stored.

D+1: D00201 0000

3-12-19 FOUR-DIGIT NUMBER TO ASCII: STR4(601)

Purpose Converts a 4-digit hexadecimal number (#0000 to #FFFF) to ASCII data (4
characters).
This instruction is supported by CS/CJ-series CPU Units with unit version 4.0
or later only.

534
Conversion Instructions Section 3-12

Ladder Symbol
STR4
S S: Number
D D: ASCII text

Variations
Variations Executed Each Cycle for ON Condition STR4(601)
Executed Once for Upward Differentiation @STR4(601)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Function block Block program Step program Subroutines Interrupt
definitions areas areas tasks
OK OK OK OK OK

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6143 CIO 0000 to CIO 6142
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D32767 D00000 to D32766
EM Area without bank E00000 to E32767 E00000 to E32766
EM Area with bank En_00000 to En_32767 En_00000 to En_32766
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
Data Registers --- ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description STR4(601) converts the numerical data in S (4-digit hexadecimal, #0000 to

#FFFF) to ASCII data (4 characters) and writes the result to D and D+1.

535
Conversion Instructions Section 3-12

15 12 11 8 7 4 3 0

S 1 2 3 4

Hexadecimal: #1234

ASCII
15 8 7 0

D 31 32
D+1 33 34

Note If the source data is 0, the Equals Flag will turn ON.
If the leftmost bit of the source data is 1, the Negative Flag will turn ON.

Restrictions The following restrictions apply to STR4(601).

■ Restrictions on the CPU Unit

STR4(601) can be used in CPU Units with unit version 4.0 or later only.
■ Restrictions on the CX-Programmer
STR4(601) can be used in CX-Programmer version 7 or higher only.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the source data is 1.
OFF in all other cases.

Examples
■ Example 1: Converting 3 Words of Numerical Data to ASCII Data
When CIO 000000 is ON in the following example, the 3 words of numerical
data starting at D00010 are converted, one word at a time, to ASCII data. The
converted ASCII data is stored in the DM Area starting at D00100.

536
Conversion Instructions Section 3-12

000000
MOVR
15 12 11 8 7 4 3 0
D00010
IR0 S: D00010 0 1 2 3
S+1: D00011 4 5 6 7
000000
MOVR S+2: D00012 8 9 A B
D00100
IR1 Hexadecimal

FOR ASCII
15 8 7 0
&3
D: D00100 30 31
00000
STR4 D+1: D00101 32 33
S ,IR0+ D+2: D00102 34 35
D ,IR1++ D+3: D00103 36 37
D+4: D00104 38 39
D+5: D00105 41 42
NEXT

■ Example 2: Converting Hexadecimal Data to ASCII Data in BCD Format

When CIO 000001 is ON in the following example, the source data in D00000
(&1234 in decimal) is converted to BCD data and the result is stored tempo-
rarily in D00010. Next, the BCD data is converted to ASCII data and the result
is output to D00100 and D00101.

000001 15 12 11 8 7 4 3 0
BCD
&1234 Decimal
D00000 D00000 0 4 D 2
(#04D2 hexadecimal)
D00010
Binary (hexadecimal)

STR4
S D00010 BCD
15 12 11 8 7 4 3 0
D D00100
S: D00010 1 2 3 4

BCD

ASCII (BCD)
15 8 7 0

D: D00100 31 32
D+1: D00101 33 34

3-12-20 EIGHT-DIGIT NUMBER TO ASCII: STR8(602)

Purpose Converts an 8-digit hexadecimal number (#0000 0000 to #FFFF FFFF) to
ASCII data (8 characters).
This instruction is supported by CS/CJ-series CPU Units with unit version 4.0
or later only.

537
Conversion Instructions Section 3-12

Ladder Symbol
STR8
S S: Number
D D: ASCII text

Variations
Variations Executed Each Cycle for ON Condition STR8(602)
Executed Once for Upward Differentiation @STR8(602)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Function block Block program Step program Subroutines Interrupt
definitions areas areas tasks
OK OK OK OK OK

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6140
Work Area W000 to W510 W000 to W508
Holding Bit Area H000 to H510 H000 to H508
Auxiliary Bit Area A448 to A958 A448 to A956
Timer Area T0000 to T4094 T0000 to T4092
Counter Area C0000 to C4094 C0000 to C4092
DM Area D00000 to D32766 D00000 to D32764
EM Area without bank E00000 to E32766 E00000 to E32764
EM Area with bank En_00000 to En_32766 En_00000 to En_32764
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 0000 to #FFFF FFFF ---
Data Registers --- ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description STR8(602) converts the numerical data in S and S+1 (8-digit hexadecimal,
#0000 0000 to #FFFF FFFF) to ASCII data (8 characters) and writes the
result to D, D+1, D+2, and D+3.

538
Conversion Instructions Section 3-12

15 12 11 8 7 4 3 0

S 5 6 7 8
S+1 1 2 3 4
Hexadecimal: #12345678

ASCII
15 8 7 0

D 31 32
D+1 33 34
D+2 35 36
D+3 37 38

Note If the source data is 0, the Equals Flag will turn ON.
If the leftmost bit of the source data is 1, the Negative Flag will turn ON.

Restrictions The following restrictions apply to STR8(602).

■ Restrictions on the CPU Unit
STR8(602) can be used in CPU Units with unit version 4.0 or later only.

■ Restrictions on the CX-Programmer

STR8(602) can be used in CX-Programmer version 7 or higher only.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the source data is 1.
OFF in all other cases.

3-12-21 SIXTEEN-DIGIT NUMBER TO ASCII: STR16(603)

Purpose Converts a 16-digit hexadecimal number (#0000 0000 0000 0000 to
#FFFF FFFF FFFF FFFF) to ASCII data (16 characters).
This instruction is supported by CS/CJ-series CPU Units with unit version 4.0
or later only.

Ladder Symbol
STR16
S S: Number
D D: ASCII text

Variations
Variations Executed Each Cycle for ON Condition STR16(603)
Executed Once for Upward Differentiation @STR16(603)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Function block Block program Step program Subroutines Interrupt
definitions areas areas tasks
OK OK OK OK OK

539
Conversion Instructions Section 3-12

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6140 CIO 0000 to CIO 6136
Work Area W000 to W508 W000 to W504
Holding Bit Area H000 to H508 H000 to H504
Auxiliary Bit Area A448 to A956 A448 to A952
Timer Area T0000 to T4092 T0000 to T4088
Counter Area C0000 to C4092 C0000 to C4088
DM Area D00000 to D32764 D00000 to D32760
EM Area without bank E00000 to E32764 E00000 to E32760
EM Area with bank En_00000 to En_32764 En_00000 to En_32760
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- ---
Data Registers --- ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description STR16(603) converts the numerical data in S to S+3 (16-digit hexadecimal,

#0000 0000 0000 0000 to #FFFF FFFF FFFF FFFF) to ASCII data (16 char-
acters) and writes the result to D to D+7.
15 12 11 8 7 4 3 0

S C D E F
S+1 8 9 A B
S+2 4 5 6 7
S+3 0 1 2 3

Hexadecimal: #1234567890ABCDEF

ASCII
15 8 7 0

D 30 31
D+1 32 33
D+2 34 35
D+3 36 37
D+4 38 39
D+5 41 42
D+6 43 44
D+7 45 46

540
Conversion Instructions Section 3-12

Note If the source data is 0, the Equals Flag will turn ON.
If the leftmost bit of the source data is 1, the Negative Flag will turn ON.

Restrictions The following restrictions apply to STR16(603).

■ Restrictions on the CPU Unit

STR16(603) can be used in CPU Units with unit version 4.0 or later only.
■ Restrictions on the CX-Programmer
STR16(603) can be used in CX-Programmer version 7 or higher only.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the source data is 1.
OFF in all other cases.

3-12-22 ASCII TO FOUR-DIGIT NUMBER: NUM4(604)

Purpose Converts 4 characters of ASCII data to a 4-digit hexadecimal number.
This instruction is supported by CS/CJ-series CPU Units with unit version 4.0
or later only.

Ladder Symbol
NUM4
S S: ASCII text
D D: Number

Variations
Variations Executed Each Cycle for ON Condition NUM4(604)
Executed Once for Upward Differentiation @NUM4(604)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Function block Block program Step program Subroutines Interrupt
definitions areas areas tasks
OK OK OK OK OK

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6143
Work Area W000 to W510 W000 to W511
Holding Bit Area H000 to H510 H000 to H511
Auxiliary Bit Area A448 to A958 A000 to A959
Timer Area T0000 to T4094 T0000 to T4095
Counter Area C0000 to C4094 C0000 to C4095
DM Area D00000 to D32766 D00000 to D32767
EM Area without bank E00000 to E32766 E00000 to E32767
EM Area with bank En_00000 to En_32766 En_00000 to En_32767
(n = 0 to C) (n = 0 to C)

541
Conversion Instructions Section 3-12

Area S D
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- ---
Data Registers --- ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NUM4(604) converts the 4 characters of ASCII data in S and S+1 to numeri-
cal data (4-digit hexadecimal) and writes the result to D.
The Error Flag will be turned ON if the ASCII data in S and S+1 contains any
characters that are not hexadecimal digits. In this case, the instruction will not
be executed.
15 8 7 0

S 31 32
S+1 33 34

ASCII

Hexadecimal
15 12 11 8 7 4 3 0

D 1 2 3 4

Note If the numerical data is 0, the Equals Flag will turn ON.
If the leftmost bit of the numerical data is 1, the Negative Flag will turn ON.

Restrictions The following restrictions apply to NUM4(604).

■ Restrictions on the CPU Unit

NUM4(604) can be used in CPU Units with unit version 4.0 or later only.
■ Restrictions on the CX-Programmer
NUM4(604) can be used in CX-Programmer version 7 or higher only.

Flags
Name Label Operation
Error Flag ER ON if the source words contain any ASCII characters that
are not hexadecimal equivalents (0 to 9, a to f, or A to F).
OFF in all other cases.
Equals Flag = ON if the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the source data is 1.
OFF in all other cases.

542
Conversion Instructions Section 3-12

Examples
■ Example 1: Converting 3 Sets of 4 ASCII Characters to the Equivalent
Hexadecimal Digits
When CIO 000000 is ON in the following example, the 6 words of ASCII data
starting at D00010 are converted, two words at a time, to numerical data. The
converted numerical data is stored in the DM Area starting at D00100.
15 8 7 0
000000
MOVR S: D00010 31 32
D00010 S+1: D00011 41 42
IR0 S+2: D00012 38 39
S+3: D00013 45 46
000000
MOVR S+4: D00014 30 30
D00100 S+5: D00015 30 30
IR1
ASCII
FOR
&3 Hexadecimal
15 12 11 8 7 4 3 0
000000
NUM4 D: D00100 1 2 A B
S ,IR0++ D+1: D00101 8 9 E F
D ,IR1+ D+2: D00102 0 0 0 0

NEXT

■ Example 2: Converting ASCII Data in BCD Format to Hexadecimal Data

When CIO 000001 is ON in the following example, the ASCII characters in
D00000 and D00001 are converted to BCD data and the result is stored tem-
porarily in D00010. Next, the BCD data is converted to hexadecimal and the
result is output to D00100.

000001
NUM4 15 8 7 0
S D00000
S: D00000 31 32
D D00010 S+1: D00001 33 34

BIN
ASCII (BCD)
D00010
D00100
BCD
15 12 11 8 7 4 3 0

D: D00010 1 2 3 4

BCD

Binary (hexadecimal)
15 12 11 8 7 4 3 0

0 4 D 2
&1234 Decimal
D00100 (#04D2 hexadecimal)

543
Conversion Instructions Section 3-12

3-12-23 ASCII TO EIGHT-DIGIT NUMBER: NUM8(605)

Purpose Converts 8 characters of ASCII data to an 8-digit hexadecimal number.
This instruction is supported by CS/CJ-series CPU Units with unit version 4.0
or later only.
Ladder Symbol
NUM8
S S: ASCII text
D D: Number

Variations
Variations Executed Each Cycle for ON Condition NUM8(605)
Executed Once for Upward Differentiation @NUM8(605)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

Applicable Program Areas

Function block Block program Step program Subroutines Interrupt
definitions areas areas tasks
OK OK OK OK OK

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6140 CIO 0000 to CIO 6142
Work Area W000 to W508 W000 to W510
Holding Bit Area H000 to H508 H000 to H510
Auxiliary Bit Area A448 to A956 A448 to A958
Timer Area T0000 to T4092 T0000 to T4094
Counter Area C0000 to C4092 C0000 to C4094
DM Area D00000 to D32764 D00000 to D32766
EM Area without bank E00000 to E32764 E00000 to E32766
EM Area with bank En_00000 to En_32764 En_00000 to En_32766
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- ---
Data Registers --- ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NUM8(605) converts the 8 characters of ASCII data in S to S+3 to numerical

data (4-digit hexadecimal) and writes the result to D and D+1.

544
Conversion Instructions Section 3-12

The Error Flag will be turned ON if the ASCII data contains any characters
that are not hexadecimal digits. In this case, the instruction will not be exe-
cuted.
15 8 7 0

S 31 32
S+1 33 34
S+2 35 36
S+3 37 38

ASCII

Hexadecimal 15 12 11 8 7 4 3 0

D 5 6 7 8
D+1 1 2 3 4

Note If the numerical data is 0, the Equals Flag will turn ON.
If the leftmost bit of the numerical data is 1, the Negative Flag will turn ON.

Restrictions The following restrictions apply to NUM8(605).

■ Restrictions on the CPU Unit

NUM8(605) can be used in CPU Units with unit version 4.0 or later only.

■ Restrictions on the CX-Programmer

NUM8(605) can be used in CX-Programmer version 7 or higher only.
Flags
Name Label Operation
Error Flag ER ON if the source words contain any ASCII characters that
are not hexadecimal equivalents (0 to 9, a to f, or A to F).
OFF in all other cases.
Equals Flag = ON if the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the source data is 1.
OFF in all other cases.

3-12-24 ASCII TO SIXTEEN-DIGIT NUMBER: NUM16(606)

Purpose Converts 16 characters of ASCII data to an 16-digit hexadecimal number.
This instruction is supported by CS/CJ-series CPU Units with unit version 4.0
or later only.

Ladder Symbol
NUM16
S S: ASCII text
D D: Number

Variations
Variations Executed Each Cycle for ON Condition NUM16(606)
Executed Once for Upward Differentiation @NUM16(606)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification Not supported

545
Conversion Instructions Section 3-12

Applicable Program Areas

Function block Block program Step program Subroutines Interrupt
definitions areas areas tasks
OK OK OK OK OK

Operand Specifications
Area S D
CIO Area CIO 0000 to CIO 6136 CIO 0000 to CIO 6140
Work Area W000 to W504 W000 to W508
Holding Bit Area H000 to H504 H000 to H508
Auxiliary Bit Area A448 to A952 A448 to A956
Timer Area T0000 to T4088 T0000 to T4092
Counter Area C0000 to C4088 C0000 to C4092
DM Area D00000 to D32760 D00000 to D32764
EM Area without bank E00000 to E32760 E00000 to E32764
EM Area with bank En_00000 to En_32760 En_00000 to En_32764
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- ---
Data Registers --- ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description NUM16(606) converts the 16 characters of ASCII data in S to S+7 to numeri-

cal data (4-digit hexadecimal) and writes the result to D and D+3.
The Error Flag will be turned ON if the ASCII data contains any characters
that are not hexadecimal digits. In this case, the instruction will not be exe-
cuted.

546
Conversion Instructions Section 3-12

15 8 7 0

S 30 31
S+1 32 33
S+2 34 35
S+3 36 37
S+4 38 39
S+5 41 42
S+6 43 44
S+7 45 46

ASCII

Hexadecimal
15 12 11 8 7 4 3 0

D C D E F
D+1 8 9 A B
D+2 4 5 6 7
D+3 0 1 2 3

Note If the numerical data is 0, the Equals Flag will turn ON.
If the leftmost bit of the numerical data is 1, the Negative Flag will turn ON.

Restrictions The following restrictions apply to NUM16(606).

■ Restrictions on the CPU Unit

NUM16(606) can be used in CPU Units with unit version 4.0 or later only.

■ Restrictions on the CX-Programmer

NUM16(606) can be used in CX-Programmer version 7 or higher only.
Flags
Name Label Operation
Error Flag ER ON if the source words contain any ASCII characters that
are not hexadecimal equivalents (0 to 9, a to f, or A to F).
OFF in all other cases.
Equals Flag = ON if the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of the source data is 1.
OFF in all other cases.

547
Logic Instructions Section 3-13

3-13 Logic Instructions

This section describes instructions which perform logic operations on word
data.
Instruction Mnemonic Function code Page
LOGICAL AND ANDW 034 548
DOUBLE LOGICAL AND ANDL 610 550
LOGICAL OR ORW 035 551
DOUBLE LOGICAL OR ORWL 611 553
EXCLUSIVE OR XORW 036 555
DOUBLE EXCLUSIVE OR XORL 612 557
EXCLUSIVE NOR XNRW 037 559
DOUBLE EXCLUSIVE NOR XNRL 613 560
COMPLEMENT COM 029 562
DOUBLE COMPLEMENT COML 614 564

3-13-1 LOGICAL AND: ANDW(034)

Purpose Takes the logical AND of corresponding bits in single words of word data and/
or constants.

Ladder Symbol
ANDW(034)

I1 I1: Input 1

I2 I2: Input 2

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition ANDW(034)
Executed Once for Upward Differentiation @ANDW(034)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area I1 I2 R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)

548
Logic Instructions Section 3-13

Area I1 I2 R
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ANDW(034) takes the logical AND of data specified in I1 and I2 and outputs
the result to R.
• The logical AND is taken of corresponding bits in I1 and I2 in succession.
• When the content of corresponding bits in both I1 and I2 are 1 or when
either is 0, a 0 will be output to the corresponding bit in R.
I1, I2 → R
I1 I2 R
1 1 1
1 0 0
0 1 0
0 0 0

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

Precautions When ANDW(034) is executed, the Error Flag will turn OFF.
If as a result of the AND, the content of R is 0000 hex, the Equals Flag will
turn ON.
If as a result of the AND, the leftmost bit of R is 1, the Negative Flag will turn
ON.

549
Logic Instructions Section 3-13

3-13-2 DOUBLE LOGICAL AND: ANDL(610)

Purpose Takes the logical AND of corresponding bits in double words of word data and/
or constants.
Ladder Symbol
ANDL(610)

I1 I1: Input 1

I2 I2: Input 2

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition ANDL(610)
Executed Once for Upward Differentiation @ANDL(610)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area I1 I2 R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

550
Logic Instructions Section 3-13

Description ANDL(610) takes the logical AND of data specified in I1, I1+1 and I2, I2+1 and
outputs the result to R, R+1.
(I1, I1+1), (I2, I2+1) → (R, R+1)
I1, I1+1 I2, I2+1 R, R+1
1 1 1
1 0 0
0 1 0
0 0 0

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

Precautions When ANDL(610) is executed, the Error Flag will turn OFF.
If as a result of the AND, the content of R, R+1 is 00000000 hex, the Equals
Flag will turn ON.
If as a result of the AND, the leftmost bit of R+1 is 1, the Negative Flag will
turn ON.

Examples When the execution condition CIO 00000000 is ON, the logical AND is taken
of corresponding bits in CIO 0011, CIO 0010 and CIO 0021, CIO 0020 and
the results will be output to corresponding bits in D00201 and D00200.

S1: 0010 CH S2: 0020 CH D: D00200

S1+1: 0011 CH S2+1: 0021 CH D+1: D00201

Note: The vertical arrow indicates logical AND.

3-13-3 LOGICAL OR: ORW(035)

Purpose Takes the logical OR of corresponding bits in single words of word data and/or
constants.

Ladder Symbol
ORW(035)

I1 I1: Input 1

I2 I2: Input 2

R R: Result word

551
Logic Instructions Section 3-13

Variations
Variations Executed Each Cycle for ON Condition ORW(035)
Executed Once for Upward Differentiation @ORW(035)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area I1 I2 R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to+2047 ,IR0 to –2048 to+2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ORW(035) takes the logical OR of data specified in I1 and I2 and outputs the
result to R.
• The logical OR is taken of corresponding bits in I1 and I2 in succession.
• When either one of the corresponding bits in I1 and I2 are 1 or when both
of them are 0, a 0 will be output to the corresponding bit in R.
I1 + I2 → R
I1 I2 R
1 1 1
1 0 1

552
Logic Instructions Section 3-13

I1 I2 R
0 1 1
0 0 0

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

Precautions When ORW(035) is executed, the Error Flag will turn OFF.
If as a result of the OR, the content of R is 0000 hex, the Equals Flag will turn
ON.
If as a result of the OR, the leftmost bit of R is 1, the Negative Flag will turn
ON.

3-13-4 DOUBLE LOGICAL OR: ORWL(611)

Purpose Takes the logical OR of corresponding bits in double words of word data and/
or constants.

Ladder Symbol
ORWL(611)

I1 I1: Input 1

I2 I2: Input 2

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition ORWL(611)
Executed Once for Upward Differentiation @ORWL(611)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area I1 I2 R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766

553
Logic Instructions Section 3-13

Area I1 I2 R
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ORWL(611) takes the logical OR of data specified in I1 and I2 as double-word

data and outputs the result to R, R+1.
• When any of the corresponding bits in I1, I1+1, I2, and I2 +1are 1, a 1 will
be output to the corresponding bit it R+1. When any of them are 0, a 0 will
be output to the corresponding bit in R+1.
(I1, I1+1) + (I2, I2+1) → (R, R+1)
I1, I1+1 I2, I2+1 R, R+1
1 1 1
1 0 1
0 1 1
0 0 0

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

Precautions When ORWL(611) is executed, the Error Flag will turn OFF.
If as a result of the OR, the content of R, R+1 is 00000000 hex, the Equals
Flag will turn ON.
If as a result of the OR, the leftmost bit of R+1 is 1, the Negative Flag will turn
ON.

554
Logic Instructions Section 3-13

Examples When the execution condition CIO 00000000 is ON, the logical OR is taken of
corresponding bits in CIO 0021, CIO 0020 and CIO 0301, CIO 0300 and the
results will be output to corresponding bits in D00501 and D00500.

S1: 0020 CH S2: 0300 CH D: D00500

S1+1: 0021 CH S2+1: 0301 CH D+1: D00501

Note: The vertical arrow indicates logical OR.

3-13-5 EXCLUSIVE OR: XORW(036)

Purpose Takes the logical exclusive OR of corresponding bits in single words of word
data and/or constants.

Ladder Symbol
XORW(036)

I1 I1: Input 1

I2 I2: Input 2

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition XORW(036)
Executed Once for Upward Differentiation @XORW(036)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area I1 I2 R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)

555
Logic Instructions Section 3-13

Area I1 I2 R
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description XORW(036) takes the logical exclusive OR of data specified in I1 and I2 and
outputs the result to R.
• The logical exclusive OR is taken of corresponding bits in I1 and I2 in suc-
cession.
• When the content of corresponding bits of I1 and I2 are different, a 1 will
be output to the corresponding bit of R and when there are different, 0 will
be output to the corresponding bit in R.
I1, I2 + I1, I2 → R
I1 I2 R
1 1 0
1 0 1
0 1 1
0 0 0

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

Precautions When XORW(036) is executed, the Error Flag will turn OFF.
If as a result of the OR, the content of R is 0000 hex, the Equals Flag will turn
ON.
If as a result of the OR, the leftmost bit of R is 1, the Negative Flag will turn
ON.

556
Logic Instructions Section 3-13

3-13-6 DOUBLE EXCLUSIVE OR: XORL(612)

Purpose Takes the logical exclusive OR of corresponding bits in double words of word
data and/or constants.
Ladder Symbol
XORL(612)

I1 I1: Input 1

I2 I2: Input 2

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition XORL(612)
Executed Once for Upward Differentiation @XORL(612)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area I1 I2 R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

557
Logic Instructions Section 3-13

Description XORL(612) takes the logical exclusive OR of data specified in I1 and I2 as

double-word data and outputs the result to R, R+1.
• When the content of any of the corresponding bits in I1, I1+1, I2, and I2
+1are different, a 1 will be output to the corresponding bit it R, R+1. When
any of them are the same, a 0 will be output to the corresponding bit in R,
R+1.
(I1, I1+1), (I2, I2+1) + (I1, I1+1), (I2, I2+1)→ (R, R+1)
I1, I1+1 I2, I2+1 R, R+1
1 1 0
1 0 1
0 1 1
0 0 0

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

Precautions When XORL(612) is executed, the Error Flag will turn OFF.
If as a result of the exclusive OR, the content of R, R+1 is 00000000 hex, the
Equals Flag will turn ON.
If as a result of the exclusive OR, the leftmost bit of R+1 is 1, the Negative
Flag will turn ON.

Examples When the execution condition CIO 00000000 is ON, the logical exclusive OR
is taken of corresponding bits in CIO 0901, CIO 0900 and D01001, D01000
and the results will be output to corresponding bits in D01201 and D01200.

S: 0900 CH S: D01000 D: D01200

S1+1: 0901 CH S2+1: D01001 D+1: D01201

Note: The symbol indicates exclusive logical OR.

558
Logic Instructions Section 3-13

3-13-7 EXCLUSIVE NOR: XNRW(037)

Purpose Takes the logical exclusive NOR of corresponding single words of word data
and/or constants.
Ladder Symbol
XNRW(037)

I1 I1: Input 1

I2 I2: Input 2

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition XNRW(037)
Executed Once for Upward Differentiation @XNRW(037)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area I1 I2 R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

559
Logic Instructions Section 3-13

Description XNRW(037) takes the logical exclusive NOR of data specified in I1 and I2 and
outputs the result to R.
• The logical exclusive NOR is taken of corresponding bits in I1 and I2 in
succession.
• When the content of corresponding bits of I1 and I2 are different, a 0 will
be output to the corresponding bit of R and when they are different, 1 will
be output to the corresponding bit in R.
I1, I2 + I1, I2 → R
I1 I2 R
1 1 1
1 0 0
0 1 0
0 0 1

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

Precautions When XNRW(037) is executed, the Error Flag will turn OFF.
If as a result of the NOR, the content of R is 0000 hex, the Equals Flag will
turn ON.
If as a result of the NOR, the leftmost bit of R is 1, the Negative Flag will turn
ON.

3-13-8 DOUBLE EXCLUSIVE NOR: XNRL(613)

Purpose Takes the logical exclusive NOR of corresponding bits in double words of
word data and/or constants.

Ladder Symbol
XNRL(613)

I1 I1: Input 1

I2 I2: Input 2
R R: Result word

Variations
Variations Executed Each Cycle for ON Condition XNRL(613)
Executed Once for Upward Differentiation @XNRL(613)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

560
Logic Instructions Section 3-13

Operand Specifications
Area I1 I2 R
CIO Area CIO 0000 to CIO 6142
Work Area W000 toW 510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description XNRL(613) takes the logical exclusive NOR of data specified in I1 and I2 and
outputs the result to R, R+1.
• When the content of any of the corresponding bits in I1, I1+1, I2, and I2
+1are different, a 0 will be output to the corresponding bit in R, R+1.
When any of them are the same, a 1 will be output to the corresponding
bit in R, R+1.
(I1, I1+1), (I2, I2+1) + (I1, I1+1), (I2, I2+1) → (R, R+1)
I1, I1+1 I2, I2+1 R, R+1
1 1 1
1 0 0
0 1 0
0 0 1

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

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Logic Instructions Section 3-13

Precautions When XNRL(613) is executed, the Error Flag will turn OFF.
If as a result of the exclusive NOR, the content of R, R+1 is 00000000 hex, the
Equals Flag will turn ON.
If as a result of the exclusive NOR, the leftmost bit of R+1 is 1, the Negative
Flag will turn ON.

Examples When the execution condition CIO 00000000 is ON, the logical exclusive
NOR is taken of corresponding bits in CIO 0801, CIO 0800, and CIO 0101,
CIO 0100 and the results will be output to corresponding bits in D00501 and
D00500.

S1: 0800 CH S2: 0100 CH D: D00500

S1+1: 0801 CH S2+1: 0101 CH D+1: D00501

Note: The symbol indicates exclusive logical NOR.

3-13-9 COMPLEMENT: COM(029)

Purpose Turns OFF all ON bits and turns ON all OFF bits in Wd.

Ladder Symbol

COM(029)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition COM(029)
Executed Once for Upward Differentiation @COM(029)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767

562
Logic Instructions Section 3-13

Area Wd
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description COM(029) reverses the status of every specified bit in Wd.

Wd→Wd: 1 → 0 and 0 → 1
Note When using the COM instruction, be aware that the status of each bit will
change each cycle in which the execution condition is ON.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

Precautions When COM(029) is executed, the Error Flag will turn OFF.
If as a result of COM, the content of R is 0000 hex, the Equals Flag will turn
ON.
If as a result of COM, the leftmost bit of R is 1, the Negative Flag will turn ON.

Examples When CIO 000000 is ON in the following example, the status of each bit will
be D00100 is reversed.

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Logic Instructions Section 3-13

3-13-10 DOUBLE COMPLEMENT: COML(614)

Purpose Turns OFF all ON bits and turns ON all OFF bits in Wd and Wd+1.
Ladder Symbol
COML(614)

Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition COML(614)
Executed Once for Upward Differentiation @COML(614)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Wd
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description COML(614) reverses the status of every specified bit in Wd and Wd+1.
(Wd+1, Wd)→(Wd+1, Wd)
Note When using the COM instruction, be aware that the status of each bit will
change each cycle in which the execution condition is ON.

564
Special Math Instructions Section 3-14

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON when the result is 0.
OFF in all other cases.
Negative Flag N ON when the leftmost bit of R is 1.
OFF in all other cases.

Precautions When COML(614) is executed, the Error Flag will turn OFF.
If as a result of COML, the content of R, R+1 is 00000000 hex, the Equals
Flag will turn ON.
If as a result of COML, the leftmost bit of R+1 is 1, the Negative Flag will turn
ON.

Examples When CIO 000000 is ON in the following example, the status of each bit in
D00100 and D00101 will be reversed.

3-14 Special Math Instructions

This section describes instructions used for special math calculations.
Instruction Mnemonic Function code Page
BINARY ROOT ROTB 620 565
BCD SQUARE ROOT ROOT 072 567
ARITHMETIC PROCESS APR 069 571
FLOATING POINT DIVIDE FDIV 079 583
BIT COUNTER BCNT 067 587

3-14-1 BINARY ROOT: ROTB(620)

Purpose Computes the square root of the 32-bit signed binary contents (positive value)
of the specified words and outputs the integer portion of the result to the spec-
ified result word.
Ladder Symbol
ROTB(620)

S S: First source word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition ROTB(620)
Executed Once for Upward Differentiation @ROTB(620)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

565
Special Math Instructions Section 3-14

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6143
Work Area W000 to W510 W000 to W511
Holding Bit Area H000 to H510 H000 to H511
Auxiliary Bit Area A000 to A958 A448 to A959
Timer Area T0000 to T4094 T0000 to T4095
Counter Area C0000 to C4094 C0000 to C4095
DM Area D00000 to D32766 D00000 to D32767
EM Area without bank E00000 to E32766 E00000 to E32767
EM Area with bank En_00000 to En_32766 En_00000 to En_32767
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ROTB(620) computes the square root of the 32-bit binary number in S+1 and
S and outputs the integer portion of the result to R. The non-integer remainder
is eliminated.

S+1 S R

Binary data (32 bits) Binary data (16 bits)

The range of data that can be specified for words S+1 and S is 0000 0000 to
3FFF FFFF. If a number from 4000 0000 to 7FFF FFFF is specified, it will be
treated as 3FFF FFFF for the square root computation. An error will occur if
the content of the source words is greater than 7FFF FFFF, i.e., if bit 15 of
S+1 is 1.

566
Special Math Instructions Section 3-14

Flags
Name Label Operation
Error Flag ER ON if bit 15 of S+1 is 1 (ON).
OFF in all other cases.
Equals Flag = ON if the result is 0000.
OFF in all other cases.
Overflow Flag OF ON if the content of S+1 and S is 4000 0000 to
7FFF FFFF.
OFF in all other cases.
Underflow Flag UF OFF
Negative Flag N OFF

Precautions The content of S+1 and S must be less than 8000 0000.
The operands of this instruction (S+1, S, and R) are all treated as binary val-
ues. If the input data is BCD, use the ROOT(072) instruction.

Example When CIO 000000 is ON in the following example, ROTB(620) calculates the
square root of the data in CIO 0002 and CIO 0001, and writes the integer por-
tion of the result in D00100.
CIO 0002 CIO 0001
014B 5A91
Square root computation
D00100 (remainder eliminated)

1234

3-14-2 BCD SQUARE ROOT: ROOT(072)

Purpose Computes the square root of an 8-digit BCD number and outputs the integer
portion of the result to the specified result word.

Ladder Symbol
ROOT(072)

S S: First source word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition ROOT(072)
Executed Once for Upward Differentiation @ROOT(072)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6143
Work Area W000 to W510 W000 to W511
Holding Bit Area H000 to H510 H000 to H511
Auxiliary Bit Area A000 to A958 A448 to A959

567
Special Math Instructions Section 3-14

Area S R
Timer Area T0000 to T4094 T0000 to T4095
Counter Area C0000 to C4094 C0000 to C4095
DM Area D00000 to D32766 D00000 to D32767
EM Area without bank E00000 to E32766 E00000 to E32767
EM Area with bank En_00000 to En_32766 En_00000 to En_32767
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #99999999 ---
(BCD)
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description ROOT(072) computes the square root of the 8-digit BCD number in S+1 and
S and outputs the integer portion of the result to R. The non-integer remainder
is eliminated.

S+1 S R

BCD data (8 digits) BCD data (4 digits)

Flags
Name Label Operation
Error Flag ER ON if the data in S+1 and S is not BCD.
OFF in all other cases.
Equals Flag = ON if the result is 0000.
OFF in all other cases.

Precautions The operands of this instruction (S+1, S, and R) are all treated as BCD val-
ues. If the input data is binary, use the ROTB(620) instruction.

Examples Square Root of 8-digit Number

When CIO 000000 is ON in the following example, ROOT(072) calculates the
square root of the data in D00001 and D00000, and writes the integer portion
of the result in D00100.
Note Figures after the decimal point are truncated for 8-digit numbers.

568
Special Math Instructions Section 3-14

Truncated

Square Root of a 4-digit Number

The following example shows how to take the square root of a 4-digit number
and round off the result. This program example calculates the square root of
the 4-digit number in CIO 0010, rounds off the result, and writes it to
CIO 0011. (Basically, the 4-digit number is multiplied by 10,000 (1002) and the
result is divided by 100, increasing the precision of the calculation by a factor
of 100.)
Note Figures after the decimal point are rounded for 4-digit numbers.

569
Special Math Instructions Section 3-14

The values after the decimal point

should be rounded.

@BSET 1

@MOV 2

@ROOT 3

@MOV

@MOV

@MOVD

@MOVD

@INC

1,2,3... 1. The source words (D00101 and D00100) to be are cleared to 0000 0000.
D00101 D00100
0 0 0 0 0 0 0 0

0000 0000

2. The 4-digit number is moved to D00101.

010
6 0 1 7

D00101 D00100
6 0 1 7 0 0 0 0

3. ROOT(072) calculates the square root of D00101 and D00100 and writes
the result to D00102.

570
Special Math Instructions Section 3-14

D00101 D00100
6017 0000
60, 170, 000 = 7, 756.932 …
D00100 Square root computation
(Remainder eliminated)
7756

4. D00103 and the result word, CIO 0011, are cleared to 0000 0000.
D00103 CIO 0011
0 0 0 0 0 0 0 0

0000 0000

5. The result of the square root calculation is divided by 100, with the integer
portion written to CIO 0011 and the remainder going to D00103.

D00102
7 7 5 6

CIO 0011 D00103

0 0 7 7 5 6 0 0

6. If the content of D00103 is greater than 4900, CIO 0011 is incremented by

1. In this case, the result is 78.
5600 > 4900?
CIO 0011
0 0 7 8

3-14-3 ARITHMETIC PROCESS: APR(069)

Purpose Calculates the sine, cosine, or a linear extrapolation of the source data.
The linear extrapolation function allows any relationship between X and Y to
be approximated with line segments.

Ladder Symbol
APR(069)

C C: Control word

S S: Source data

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition APR(069)
Executed Once for Upward Differentiation @APR(069)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

571
Special Math Instructions Section 3-14

Operands Sine Function (C = 0000 Hex)

Operand Value Data range
C 0000 hex ---
S 0000 to 0900 (BCD) 0° to 90°
D 0000 to 9999 (BCD) 0.0000 to 0.9999
9999 (BCD) 1.0000

Cosine Function (C = 0001 Hex)

Operand Value Data range
C 0001 hex ---
S 0000 to 0900 (BCD) 0° to 90°
D 0000 to 9999 (BCD) 0.0000 to 0.9999
9999 (BCD) 1.0000

Linear Extrapolation Function (C = Data area address)

Operand Value Data range
C Data area address ---
S 16-bit unsigned BCD data 0000 to 9999
16-bit unsigned binary data 0 to 65,535
16-bit signed binary data1 −32,768 to 32,767

32-bit signed binary data 1 −2,147,483,648 to 2,147,483,647

Floating-point data 1 −∞,

−3.402823 × 1038 to −1.175494 × 10−38,
1.175494 × 10−38 to 3.402823 × 1038,
+∞
D 16-bit unsigned BCD data 0000 to 9999
16-bit unsigned binary data 0 to 65,535
16-bit signed binary data 1 −32,768 to 32,767

32-bit signed binary data1 −2,147,483,648 to 2,147,483,647

Floating-point data 1 −∞,

−3.402823 × 1038 to −1.175494 × 10−38,
1.175494 × 10−38 to 3.402823 × 1038,
+∞

Note 1. Signed binary data and floating-point data are supported by CS1-H, CJ1-
H, CJ1M, and CS1D CPU Units only.
2. If C is a word address, APR(069) extrapolates the Y value for the X value
in S based on coordinates (forming line segments) entered in advance in
a table beginning at C. Refer to the Description section below for details.

Operand Specifications
Area C S R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767
EM Area without bank E00000 to E32767

572
Special Math Instructions Section 3-14

Area C S R
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants Specified values only ---
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description The operation of APR(069) depends on the control word C. If C is 0000 or

0001, APR(069) computes the sine or cosine of S with S in units of tenths of
degrees.
If C is a word address, APR(069) extrapolates the Y value for the X value in S
based on coordinates (forming line segments) entered in advance in a table
beginning at C.
Sine Function (C=0000)
When C is 0000, APR(069) calculates the SIN(S) and writes the result to R.
The range for S is 0000 to 0900 BCD (0.0° to 90.0°) and the range for R is
0000 to 9999 BCD (0.0000 to 0.9999). The remainder of the result beyond the
fourth decimal place is eliminated.
Cosine Function (C=0001)
When C is 0001, APR(069) calculates the COS(S) and writes the result to R.
The range for S is 0000 to 0900 BCD (0.0° to 90.0°) and the range for R is
0000 to 9999 BCD (0.0000 to 0.9999). The remainder of the result beyond the
fourth decimal place is eliminated.
Linear Extrapolation
APR(069) linear extrapolation is specified when C is a word address.
The content of word C specifies the number of coordinates in a data table
starting at C+2, the form of the source data, and whether data is BCD or

573
Special Math Instructions Section 3-14

binary. In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, the source data can
also be signed binary data or floating-point data.
Unsigned Integer Data (Binary or BCD)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C 0 0 0 0 0

Number of coordinates minus one (m−1),

00 to FF hex (1 ≤ m ≤ 256)
Floating-point specification for S and D
0: Integer data
Signed data specification for S and D
0: Unsigned binary data

Source data form

0: f(x) = f(S)
1: f(x) = f(Xm − S)

Output (D) data format

0: Binary
1: BCD

Input (S) data format

0: Binary
1: BCD

Signed Integer Data (Binary)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C 0 0 0 0 1 0 0

Number of coordinates minus one (m−1),

00 to FF hex (1 ≤ m ≤ 256)
Floating-point specification for S and D
0: Integer data

Data length specification for S and D (note 1)

0: 16-bit signed binary data
1: 32-bit signed binary data

Signed data specification for S and D

1: Signed binary data

Single-precision Floating-point Data

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C 0 0 0 0 0 0 1 0

Number of coordinates minus one (m−1),

00 to FF hex (1 ≤ m ≤ 256)
Floating-point specification for S and D
1: Single-precision floating-point data

If 16-bit binary or BCD data is being used, the line-segment data is contained
in words C+ 1 through C+2m+2. If 32-bit binary or floating point data is being
used (CS1-H, CJ1-H, and CJ1M CPU Units only), the line-segment data is
contained in words C+ 1 through C+4m+4.
Bits 00 to 07 contain the number (binary) of line coordinates less 1, m–1. Bits
08 to 12 are not used. Bit 13 specifies either f(x)=f(S) or f(x)=f(Xm–S): OFF
specifies f(x)=f(S) and ON specifies f(x)=f(Xm–S). Bit 14 determines whether
the output is BCD or binary: OFF specifies binary and ON specifies BCD. Bit

574
Special Math Instructions Section 3-14

15 determines whether the input is BCD or binary: OFF specifies binary and
ON specifies BCD.
16-bit BCD16-bit binary (signed 32-bit signed binary data Floating-point data
or unsigned) or 16-bit BCD data
C+1 X0 (rightmost 16 bits) C+1 X0 (rightmost 16 bits)
C+1 X0 (*1)
C+2 X0 (leftmost 16 bits) C+2 X0 (leftmost 16 bits)
C+2 Y0
C+3 Y0 (rightmost 16 bits) C+3 Y0 (rightmost 16 bits)
C+3 X1
C+4 Y0 (leftmost 16 bits) C+4 Y0 (leftmost 16 bits)
C+4 Y1
C+5 X1 (rightmost 16 bits) C+5 X1 (rightmost 16 bits)
C+5 X2
C+6 X1 (leftmost 16 bits) C+6 X1 (leftmost 16 bits)
C+6 Y2
C+7 Y1 (rightmost 16 bits) C+7 Y1 (rightmost 16 bits)
C+8 Y1 (leftmost 16 bits) C+8 Y1 (leftmost 16 bits)
Xn
to to to to
Yn
C+ (4n+1) Xn (rightmost 16 bits) C+ (4n+1) Xn (rightmost 16 bits)
C+ (4n+2) Xn (leftmost 16 bits) C+ (4n+2) Xn (leftmost 16 bits)
C+ (2m+1) Xm
C+ (4n+3) Yn (rightmost 16 bits) C+ (4n+3) Yn (rightmost 16 bits)
C+ (2m+2) Ym
C+ (4n+4) Yn (leftmost 16 bits) C+ (4n+4) Yn (leftmost 16 bits)
Note: Write Xm (max. X
value in the table) in word to to to to
C+1 when the I/O data in C+ (4m+1) Xm (rightmost 16 bits) C+ (4m+1) Xm (rightmost 16 bits)
S and D contain unsigned
data (bit 11 of C = 0). C+ (4m+2) Xm (leftmost 16 bits) C+ (4m+2) Xm (leftmost 16 bits)
C+ (4m+3) Ym (rightmost 16 bits) C+ (4m+3) Ym (rightmost 16 bits)
C+ (4m+4) Ym (leftmost 16 bits) C+ (4m+4) Ym (leftmost 16 bits)

Note The X coordinates must be in ascending order: X1 < X2 < ... < Xm. Input all
values of (Xn, Yn) as binary data, regardless of the data format specified in
control word C.
Operation of the Linear Extrapolation Function
APR(069) processes the input data specified in S with the following equation
and the line-segment data (Xn, Yn) specified in the table beginning at C+1.
The result is output to the destination word(s) specified with D.
Y (Binary data)

Ymax

Y0

X0 Xmax
X (Binary data)
A B C

1. For S < X0
Converted value = Y0
2. For X0 ≤ S ≤ Xmax, if Xn < S < Xn+1
Converted value = Yn +[{Yn + 1 − Yn}/{Xn + 1 − Xn}] × {Input data S − Xn}

575
Special Math Instructions Section 3-14

Y (binary data)
Equation:
Yn+1−Yn
f(Y)= Yn+
Xn+1−Xn (S−Xn)
Yn+1

Calculation
D result Yn+1−Yn

Yn
Xn+1−Xn

S−Xn

Xn S Xn+1 X (binary data)

Input data

3. Xmax < S
Converted value = Ymax
Up to 256 endpoints can be stored in the line-segment data table beginning at
C+1. The following 5 kinds of I/O data can be used:
• 16-bit unsigned BCD data
• 16-bit unsigned binary data
• 16-bit signed binary data (CS1-H/CJ1-H/CJ1M Only)
• 32-bit signed binary data (CS1-H/CJ1-H/CJ1M Only)
• Single-precision floating-point data (CS1-H/CJ1-H/CJ1M Only)
Setting the Data Format in Control Word C
• 16-bit Unsigned BCD Data
The input data and/or the output data can be 16-bit unsigned BCD data.
Also, the linear extrapolation function can be set to operate on the value
specified in S directly or on Xm–S. (Xm is the maximum value of X in the
line-segment data.)
Setting name Bit in C Setting
Input data (S) format 15 0: Binary
1: BCD
Output data (D) format 14 0: Binary
1: BCD
Source data form 13 0: Operate on S
1: Operate on Xm–S
Signed data specification for S and D 11 0: Unsigned data
Data length specification for S and D 10 Invalid (fixed at 16 bits)
Floating-point specification 09 0: Integer data

576
Special Math Instructions Section 3-14

• 16-bit Unsigned Binary Data

The input data and/or the output data can be 16-bit unsigned binary data.
Also, the linear extrapolation function can be set to operate on the value
specified in S directly or on Xm–S. (Xm is the maximum value of X in the
line-segment data.)
Setting name Bit in C Setting
Input data (S) format 15 0: Binary
1: BCD
Output data (D) format 14 0: Binary
1: BCD
Source data form 13 0: Operate on S
1: Operate on Xm–S
Signed data specification for S and D 11 0: Unsigned data
Data length specification for S and D 10 Invalid (fixed at 16 bits)
Floating-point specification 09 0: Integer data

• 16-bit Signed Binary Data (CS1-H, CJ1-H, CJ1M, and CS1D Only)
Setting name Bit in C Setting
Input data (S) format 15 0: Binary
Output data (D) format 14 0: Binary
Source data form 13 0
Signed data specification for S and D 11 1: Signed data
Data length specification for S and D 10 0: 16-bit signed binary data
Floating-point specification 09 0: Integer data

• 32-bit Signed Binary Data (CS1-H, CJ1-H, CJ1M, and CS1D Only)
Setting name Bit in C Setting
Input data (S) format 15 0: Binary
Output data (D) format 14 0: Binary
Source data form 13 0
Signed data specification for S and D 11 1: Signed data
Data length specification for S and D 10 1: 32-bit signed binary data
Floating-point specification 09 0: Integer data

Note If the “Data length specification for S and D” in bit 10 of C is set to 1

and a 16-bit constant is input for S, the input data will be converted
to 32-bit signed binary before the linear extrapolation calculation.
• Floating-point Data (CS1-H, CJ1-H, CJ1M, and CS1D Only)
Setting name Bit in C Setting
Input data (S) format 15 0: Binary
Output data (D) format 14 0: Binary
Source data form 13 0
Signed data specification for S and D 11 0
Data length specification for S and D 10 0
Floating-point specification 09 1: Floating-point data

Note If the “Floating-point specification” in bit 09 of C is set to 1, a constant

cannot be input for S.

577
Special Math Instructions Section 3-14

Flags
Name Label Operation
Error Flag ER ON if C is a constant greater than 0001.
ON if C is a word address but the X coordinates are not in
ascending order (X1 ≤ X2 ≤ ... ≤ Xm).
ON if C is a word address and bits 9, 11, and 15 of C indi-
cate BCD input, but S is not BCD.
ON if C is a word address and bit 9 of C indicates floating-
point data, but S is a one-word constant.
ON if C is 0000 or 0001 but S is not BCD between 0000
and 0900.
OFF in all other cases.
Equals Flag = ON if the result is 0000.
OFF in all other cases.
Negative Flag N ON if bit 15 of R is ON.
OFF in all other cases.

Precautions The actual result for SIN(90°) and COS(0°) is 1, but 9999 (0.9999) will be out-
put to R.
An error will occur if C is a constant greater than 0001.
An error will occur if linear extrapolation is specified but the X coordinates are
not in ascending order (X1 < X2 < ... < Xn< S< Xn+1).
An error will occur if linear extrapolation is specified and BCD input is speci-
fied (bit 15 of C ON) but S is not BCD.
An error will occur if a trigonometric function is specified (C=0000 or 0001) but
S is not BCD between 0000 and 0900.

Examples Sine Function (C: #0000)

The following example shows APR(069) used to calculate the sine of 30°.
Source data Result
S: D00000 R: D00100
0 101 100 10–1 10–1 10–2 10–3 10–4
0 3 0 0 5 0 0 0
Set the source data in 10–1 degrees. Result data has four significant digits,
(0000 to 0900, BCD) fifth and higher digits are ignored.
(0000 to 9999, BCD)

Cosine Function (C: #0001)

The following example shows APR(069) used to calculate the cosine of 30°.
(SIN(30) = 0.8660)
Source data Result
S: D00010 R: D00200
0 101 100 10–1 10–1 10–2 10–3 10–4
0 3 0 0 8 6 6 0
–1
Set the source data in 10 degrees. Result data has four significant digits,
(0000 to 0900, BCD) fifth and higher digits are ignored.
(0000 to 9999, BCD)

578
Special Math Instructions Section 3-14

Linear Extrapolation (C: Word Address)

Using 16-bit Unsigned BCD or Binary Data
APR(069) processes the input data specified in S based on the control data in
C and the line-segment data specified in the table beginning at C+1. The
result is output to D.
Y Word Coordinate
C+1 Xm (max. X
Ym value)
C+2 Y0
Y4
C+3 X1
C+4 Y1
Y3
Y1 C+5 X2
C+6 Y2
Y2 ↓ ↓
Y0
C+(2m+1) Xm (max. X
X value)
X0 X1 X2 X3 X4 Xm C+(2m+2) Ym

• Yn = f(Xn), Y0 = f(X0)
• Be sure that Xn–1 < Xn in all cases.
• Input all values of (Xn, Yn) as binary data.

Y0

Y1

Y2
Y4

Y3
Ym

X0 X1 X2 X3 X4 Xm X

This example shows how to construct a linear extrapolation with 12 coordi-

nates. The block of data is continuous, as it must be, from D00000 to D00026
(C to C + (2 × 12 + 2)). The input data is taken from CIO 0010, and the result
is output to CIO 0011.

Content Coordinate Bit Bit

15 00

D00000 000B Hex 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1

D00001 05F0 Hex X12
Y0 x=S (m–1 = 11: 12 line
D00002 0000 Hex segments)
D00003 0005 Hex X1
D00004 0F00 Hex Y1 Output and input
D00005 001A Hex X2 both binary
D00006 0402 Hex Y2
↓ ↓ ↓
D00025 05F0 Hex X12
D00026 1F20 Hex Y12

In this case, the source word, CIO 0010, contains 0014, and f(0014) = 0726 is
output to R, CIO 0011.

579
Special Math Instructions Section 3-14

$1F20

$0F00

(x,y)
$0726

$0402

X
(0,0)
$0005 $0014 $001A $05F0

The linear-extrapolation calculation is shown below.

0402 – 0F00
Y = 0F00 + --------------------------------- × ( 0014 – 0015 )
001A – 0005
Ω = 0F00 – ( 0086 × 000F )
Ω = 0726 Values are all hexadecimal (Hex).

580
Special Math Instructions Section 3-14

Linear Extrapolation (C: Word Address)

Using 32-bit Signed Binary Data (CS1-H, CJ1-H, CJ1M, and CS1D Only)
In this example, APR(069) is used to convert the fluid height in a tank to fluid
volume based on the shape of the holding tank.
Fluid height to volume
conversion table
(32-bit signed binary data)
C+1 X0 (rightmost 16 bits)
C+2 X0 (leftmost 16 bits)
C+3 Y0 (rightmost 16 bits)
C+4 Y0 (leftmost 16 bits)
C+5 X1 (rightmost 16 bits)
Variation from
standard = X C+6 X1 (leftmost 16 bits)
C+7 Y1 (rightmost 16 bits)
Fluid volume= Y C+8 Y1 (leftmost 16 bits)
to to
C+ (4n+1) Xn (rightmost 16 bits)
C+ (4n+2) Xn (leftmost 16 bits)
C+ (4n+3) Yn (rightmost 16 bits)
C+ (4n+4) Yn (leftmost 16 bits)
to to
C+ (4m+1) Xm (rightmost 16 bits)
C+ (4m+2) Xm (leftmost 16 bits)
C+ (4m+3) Ym (rightmost 16 bits)
C+ (4m+4) Ym (leftmost 16 bits)
000000

APR
C
Linear extrapolation of table
S
R

Y: Fluid volume

Ym

R
R+1 X: Variation from standard
Y data range:
−2,147,483,648 to The linear extrapolation can use
2,147,483,647 signed source data if 32-bit signed
binary data is used.

Y0 0
X0

Xm

S
S+1
High-resolution 32-bit
signed binary data X data range: −2,147,483,648 to 2,147,483,647

581
Special Math Instructions Section 3-14

Linear Extrapolation (C: Word Address)

Using Floating-point Data (CS1-H, CJ1-H, CJ1M, and CS1D Only)
In this example, APR(069) is used to convert the fluid height in a tank to fluid
volume based on the shape of the holding tank.
C+1 X0 (rightmost 16 bits)
Fluid height to volume
C+2 X0 (leftmost 16 bits)
conversion table
(Floating-point data) C+3 Y0 (rightmost 16 bits)
C+4 Y0 (leftmost 16 bits)
C+5 X1 (rightmost 16 bits)
C+6 X1 (leftmost 16 bits)
C+7 Y1 (rightmost 16 bits)
C+8 Y1 (leftmost 16 bits)
Fluid volume Fluid height = X to to
=Y
C+ (4n+1) Xn (rightmost 16 bits)
C+ (4n+2) Xn (leftmost 16 bits)
C+ (4n+3) Yn (rightmost 16 bits)
C+ (4n+4) Yn (leftmost 16 bits)
to to
C+ (4m+1) Xm (rightmost 16 bits)
C+ (4m+2) Xm (leftmost 16 bits)
C+ (4m+3) Ym (rightmost 16 bits)
C+ (4m+4) Ym (leftmost 16 bits)
000000

APR
C
S
Linear extrapolation of table
R

Y: Fluid volume

Ym

Y data range:
−∞, −3.402823 × 1038 to The linear extrapolation can
R
−1.175494 × 10−38, provide a smooth, high-resolution
1.175494 × 10−38 to R+1 curve floating-point data is used.
3.402823 × 1038, or +∞

Y0
0
X0 Xm X: Fluid height

S
S+1
High-resolution
floating point data
X data range:
−∞, −3.402823 × 1038 to −1.175494 × 10−38,
1.175494 × 10−38 to 3.402823 × 1038, or +∞

582
Special Math Instructions Section 3-14

3-14-4 FLOATING POINT DIVIDE: FDIV(079)

Purpose Divides one 7-digit floating-point number by another. The floating-point num-
bers are expressed in scientific notation (7-digit mantissa and 1-digit expo-
nent).
Ladder Symbol
FDIV(079)

Dd Dd: First dividend word

Dr Dr: First divisor word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition FDIV(079)
Executed Once for Upward Differentiation @FDIV(079)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Dd Dr R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

583
Special Math Instructions Section 3-14

Description FDIV(079) divides the floating-point value in Dd and Dd+1 by that in Dr and
Dr+1 and places the result in R and R+1.
Quotient

R+1 R

Dr+1 Dr Dd+1 Dd

To represent the floating-point values, the rightmost seven digits are used for
the mantissa and the leftmost digit is used for the exponent, as shown in the
diagram below. The leftmost digit can range from 0 to F; positive exponents
range from 0 to 7 and negative exponents range from 8 to F (0 to –7). The
rightmost 7 digits must be BCD.

First word Second word

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1

mantissa (rightmost 4 digits)

exponent (0 to 7) mantissa (leftmost 3 digits)
sign of exponent 0: +
1: – = 0.1111113 x 10–2

Two more examples of floating-point values are:

6123 4567: 0.1234567 × 106 (6 = 0110 binary)
B123 4567: 0.1234567 × 10–3 (B = 1011 binary)
The following table shows the maximum and minimum values allowed.
Limit 8-digit hexadecimal Floating-point
Maximum value 7999 9999 0.9999999 × 107
Minimum value F000 0001 0.0000001 × 10–7
(Divisor and dividend)
Minimum value F100 0000 0.1000000 × 10–7
(Result)

Flags
Name Label Operation
Error Flag ER ON if the mantissa (leftmost 7 digits) in Dd+1 and Dd is
not BCD.
ON if the mantissa (leftmost 7 digits) in Dr+1 and Dr is not
BCD.
ON if the divisor (Dr+1 and Dr) is 0.
ON if the result is not between 0.1000000 × 10–7 and
0.9999999 × 107.
OFF in all other cases.
Equals Flag = ON if the result is 0.
OFF in all other cases.

Precautions The result is expressed as a floating-point value, so it has 7 significant digits.

The eighth and higher digits are eliminated.
The result must be between 0.1000000 × 10–7 and 0.9999999 × 107.

584
Special Math Instructions Section 3-14

Examples Basic Floating-point Division

When CIO 000000 is ON in the following example, FDIV(079) divides the
floating-point number in D00101 and D00100 by the floating-point number in
CIO 0021 and CIO 0020 and writes the result to D00301 and D00300.
D00101 D00100
A 5 6 7 0 0 0 0 0.5670000 × 10–2

CIO 0021 CIO 0020

÷ B 1 2 3 4 5 6 7 0.1234567 × 10–3

D00301 D00300
2 4 5 9 2 7 0 3 0.4592703 × 102

Floating-point Division of Two BCD Numbers

In this example, the 4-digit BCD number in D00000 is divided by the 4-digit
BCD number in D00001 and the floating-point result is written to D00003 and
D00002.
To perform the floating point division, the BCD value in D00000 is converted
to floating-point format in D00101 and D00100 and the BCD value in D00001
is converted to floating-point format in D00103 and D00102.

585
Special Math Instructions Section 3-14

@MOV
1

@MOV

@MOV

@MOV

@MOVD 3

@MOVD 4

@MOVD 5

@MOVD 6

@FDIV 7

1,2,3... 1. D00100 and D00102 are set to 0000.

2. D00101 and D00103 are set to 4000.

D00101 D00100 D00103 D00102

4 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0

4000 0000 4000 0000

3. MOVD(083) is used to move the digits of the original source words to the
proper digits in the 2-word floating-point formats.

586
Special Math Instructions Section 3-14

D00000 D00001
3 4 5 2 0 0 7 9

D00101 D00100 D00103 D00102

4 3 4 5 2 0 0 0 4 0 0 7 9 0 0 0

4. FDIV(079) divides the floating-point number in D00101 and D00100 by the

floating-point number in D00103 and D00102.

D00101 D00100
4 3 4 5 2 0 0 0 0.3452000 × 104

÷ D00103 D00102
4 0 0 7 9 0 0 0 0.0079000 × 104

D00003 D00002
2 4 3 6 9 6 2 0 0.4369620 × 102

3-14-5 BIT COUNTER: BCNT(067)

Purpose Counts the total number of ON bits in the specified word(s).

Ladder Symbol
BCNT(067)

N N: Number of words

S S: First source word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition BCNT(067)
Executed Once for Upward Differentiation @BCNT(067)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operands N: Number of words

The number of words must be 0001 to FFFF (1 to 65,535 words).
S: First source word
S and S+(N–1) must be in the same data area.

Operand Specifications
Area N S R
CIO Area CIO 0000 to CIO 6143
Work Area W000 to W511
Holding Bit Area H000 to H511
Auxiliary Bit Area A000 to A959 A448 to A959
Timer Area T0000 to T4095
Counter Area C0000 to C4095
DM Area D00000 to D32767

587
Special Math Instructions Section 3-14

Area N S R
EM Area without bank E00000 to E32767
EM Area with bank En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0001 to #FFFF ---
(binary) or &1 to
&65,535
Data Registers DR0 to DR15 --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description BCNT(067) counts the total number of bits that are ON in all words between S
and S+(N–1) and places the result in R.

N words
Counts the number
to of ON bits.
S+(N–1) Binary result

Flags
Name Label Operation
Error Flag ER ON if N is 0000.
ON if result exceeds FFFF.
OFF in all other cases.
Equals Flag = ON if the result is 0000.
OFF in all other cases.

Precautions An error will occur if N=0000 or the result exceeds FFFF.

Example When CIO 000000 is ON in the following example, BCNT(067) counts the
total number of ON bits in the 10 words from CIO 0100 through CIO 0109 and
writes the result to D00100.

000000
BCNT Counts the number
N &10 of ON bits (35).
to to
S D100
R D00100
R:D00100 23 hexadecimal
(35 decimal)

588
Floating-point Math Instructions Section 3-15

3-15 Floating-point Math Instructions

The Floating-point Math Instructions convert data and perform floating-point
arithmetic operations. CS/CJ-series CPU Units support the following instruc-
tions.
Instruction Mnemonic Function code Page
FLOATING TO 16-BIT FIX 450 594
FLOATING TO 32-BIT FIXL 451 596
16-BIT TO FLOATING FLT 452 597
32-BIT TO FLOATING FLTL 453 599
FLOATING-POINT ADD +F 454 601
FLOATING-POINT SUB- –F 455 603
TRACT
FLOATING-POINT MULTI- *F 456 605
PLY
FLOATING-POINT DIVIDE /F 457 607
DEGREES TO RADIANS RAD 458 609
RADIANS TO DEGREES DEG 459 610
SINE SIN 460 612
HIGH-SPEED SINE SINQ 475 614
COSINE COS 461 615
HIGH-SPEED COSINE COSQ 476 617
TANGENT TAN 462 619
HIGH-SPEED TANGENT TANQ 477 621
ARC SINE ASIN 463 623
ARC COSINE ACOS 464 625
ARC TANGENT ATAN 465 627
SQUARE ROOT SQRT 466 629
EXPONENT EXP 467 631
LOGARITHM LOG 468 633
EXPONENTIAL POWER PWR 840 635
MOVE FLOATING-POINT MOVF 469 649
(SINGLE)

In addition to the instructions listed above, the CS1-H/CJ1-H CPU Units sup-
port the following floating-point comparison and conversion instructions. Refer
to 3-16-21 Double-precision Floating-point Input Instructions for details on
double-precision floating-point instructions.
Instruction Mnemonic Function code Page
Single-precision Floating- LD, AND, OR 329 to 334 636
point Symbol Comparison +
Instructions =F, <>F, <F, <=F, >F,
(*CS1-H/CJ1-H/CJ1M or >=F
Only)
FLOATING-POINT TO FSTR 448 640
ASCII (*CS1-H/CJ1-H/
CJ1M Only)
ASCII TO FLOATING- FVAL 449 645
POINT (*CS1-H/CJ1-H/
CJ1M Only)

Data Format Floating-point data expresses real numbers using a sign, exponent, and man-
tissa. When data is expressed in floating-point format, the following formula
applies.

589
Floating-point Math Instructions Section 3-15

Real number = (–1)s 2e–127 (1.f)

s: Sign
e: Exponent
f: Mantissa
The floating-point data format conforms to the IEEE754 standards. Data is
expressed in 32 bits, as follows:
Sign Exponent Mantissa
s e f
31 30 23 22 0

Data No. of bits Contents

s: sign 1 0: positive; 1: negative
e: exponent 8 The exponent (e) value ranges from 0 to 255.
The actual exponent is the value remaining after
127 is subtracted from e, resulting in a range of
–127 to 128. “e=0” and “e=255” express special
numbers.
f: mantissa 23 The mantissa portion of binary floating-point
data fits the formal 2.0 > 1.f ≥1.0.

Number of Digits The number of effective digits for floating-point data is seven digits for deci-
mal.

Floating-point Data The following data can be expressed by floating-point data:

• –∞
• –3.402823 x 1038 ≤ value ≤ –1.402398 x 10–45
•0
• 1.402398 x 10–45 ≤ value ≤ 3.402823 x 1038
• +∞
• Not a number (NaN)
–45 –45
−1.402398 x 10 1.402398 x 10

–∞ –3.402823 x 1038 –1 0 1 3.402823 x 1038 + ∞

Special Numbers The formats for NaN, ±∞, and 0 are as follows:
NaN*: e = 255, f ≠ 0
+∞: e = 255, f = 0, s= 0
–∞: e = 255, f = 0, s= 1
0: e=0
*NaN (not a number) is not a valid floating-point number. Executing floating-
point calculation instructions will not result in NaN.

Writing Floating-point When floating-point is specified for the data format in the I/O memory edit dis-
Data play in the CX-Programmer, standard decimal numbers input in the display
are automatically converted to the floating-point format shown above
(IEEE754-format) and written to I/O Memory. Data written in the IEEE754-for-
mat is automatically converted to standard decimal format when monitored on
the display.

590
Floating-point Math Instructions Section 3-15

15 7 6 0
n f
n+1 s e

It is not necessary for the user to be aware of the IEEE754 data format when
reading and writing floating-point data. It is only necessary to remember that
floating point values occupy two words each.

Numbers Expressed as Floating-point Values

The following types of floating-point numbers can be used.
Mantissa (f) Exponent (e)
0 Not 0 and All 1’s (255)
not all 1’s
0 0 Normalized number Infinity
Not 0 Non-normalized NaN
number

Note A non-normalized number is one whose absolute value is too small to be

expressed as a normalized number. Non-normalized numbers have fewer sig-
nificant digits. If the result of calculations is a non-normalized number (includ-
ing intermediate results), the number of significant digits will be reduced.

Normalized Numbers Normalized numbers express real numbers. The sign bit will be 0 for a positive
number and 1 for a negative number.
The exponent (e) will be expressed from 1 to 254, and the real exponent will
be 127 less, i.e., –126 to 127.
The mantissa (f) will be expressed from 0 to 233 – 1, and it is assume that, in
the real mantissa, bit 233 is 1 and the binary point follows immediately after it.
Normalized numbers are expressed as follows:
(–1)(sign s) x 2(exponent e)–127 x (1 + mantissa x 2–23)
Example
31 30 23 22 0
1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Sign: –
Exponent: 128 – 127 = 1
Mantissa: 1 + (222 + 221) x 2–23 = 1 + (2–1 + 2–2) = 1 + 0.75 = 1.75
Value: –1.75 x 21 = –3.5
Non-normalized Numbers Non-normalized numbers express real numbers with very small absolute val-
ues. The sign bit will be 0 for a positive number and 1 for a negative number.
The exponent (e) will be 0, and the real exponent will be –126.
The mantissa (f) will be expressed from 1 to 233 – 1, and it is assume that, in
the real mantissa, bit 233 is 0 and the binary point follows immediately after it.
Non-normalized numbers are expressed as follows:
(–1)(sign s) x 2–126 x (mantissa x 2–23)
Example
31 30 23 22 0
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Sign: –
Exponent: –126
Mantissa: 0 + (222 + 221) x 2–23 = 0 + (2–1 + 2–2) = 0 + 0.75 = 0.75
Value: –0.75 x 2–126

591
Floating-point Math Instructions Section 3-15

Zero Values of +0.0 and –0.0 can be expressed by setting the sign to 0 for positive
or 1 for negative. The exponent and mantissa will both be 0. Both +0.0 and
–0.0 are equivalent to 0.0. Refer to Floating-point Arithmetic Results, below,
for differences produced by the sign of 0.0.

Infinity Values of +∞ and –∞ can be expressed by setting the sign to 0 for positive or 1
for negative. The exponent will be 255 (28 – 1) and the mantissa will be 0.
NaN NaN (not a number) is produced when the result of calculations, such as 0.0/
0.0, ∞/∞, or ∞–∞, does not correspond to a number or infinity. The exponent
will be 255 (28 – 1) and the mantissa will be not 0.
Note There are no specifications for the sign of NaN or the value of the mantissa
field (other than to be not 0).

Floating-point Arithmetic Results

Rounding Results The following methods will be used to round results when the number of digits
in the accurate result of floating-point arithmetic exceeds the significant digits
of internal processing expressions.
If the result is close to one of two internal floating-point expressions, the
closer expression will be used. If the result is midway between two internal
floating-point expressions, the result will be rounded so that the last digit of
the mantissa is 0.

Overflows, Underflows, Overflows will be output as either positive or negative infinity, depending on
and Illegal Calculations the sign of the result. Underflows will be output as either positive or negative
zero, depending on the sign of the result.
Illegal calculations will result in NaN. Illegal calculations include adding infinity
to a number with the opposite sign, subtracting infinity from a number with the
opposite sign, multiplying zero and infinity, dividing zero by zero, or dividing
infinity by infinity.
The value of the result may not be correct if an overflow occurs when convert-
ing a floating-point number to an integer.

Precautions in Handling The following precautions apply to handling zero, infinity, and NaN.
Special Values • The sum of positive zero and negative zero is positive zero.
• The difference between zeros of the same sign is positive zero.
• If any operand is a NaN, the results will be a NaN.
• Positive zero and negative zero are treated as equivalent in comparisons.
• Comparison or equivalency tests on one or more NaN will always be true
for != and always be false for all other instructions.

Floating-point Calculation Results

When the absolute value of the result is greater than the maximum value that
can be expressed for floating-point data, the Overflow Flag will turn ON and
the result will be output as ±∞. If the result is positive, it will be output as +∞; if
negative, then –∞.
The Equals Flag will only turn ON when both the exponent (e) and the man-
tissa (f) are zero after a calculation. A calculation result will also be output as
zero when the absolute value of the result is less than the minimum value that
can be expressed for floating-point data. In that case the Underflow Flag will
turn ON.

Example In this program example, the X-axis and Y-axis coordinates (x, y) are provided
by 4-digit BCD content of D00000 and D00001. The distance (r) from the ori-

592
Floating-point Math Instructions Section 3-15

gin and the angle (θ, in degrees) are found and output to D00100 and
D00101. In the result, everything to the right of the decimal point is truncated.

P (100, 100)
y

0 x
000000
(1)
D00000
D00200

D00001
D00201

D00200
D00202

D00201
D00204

(2)
D00202
D00202
D00206

D00204
D00204
D00208

D00206
D00208
D00210

D00210
D00212

(3)
D00204
D00202
D00214

D00214
D00216

D00216
D00218

(4)
D00212
D00220

D00218
D00221

D00220
D00100

D00221
D00101

593
Floating-point Math Instructions Section 3-15

Calculations Examples
Distance r = χ 2 + y 2
Distance r = 100 2 + 1002 = 141.4214
y
Angle θ = tan−1  --χ-  Angle θ = tan−1  100
----------  × 180 ÷ π = 45.0

100

DM Contents
D00000 #0100 x D00100 0141 r
(BCD) (BCD)
D00001 #0100 y D00101 0045
(BCD) (BCD)
1. This section of the program converts the data from BCD to floating-point.
a) The data area from D00200 onwards is used as a work area.
b) First BIN(023) is used to temporarily convert the BCD data to binary
data, and then FLT(452) is used to convert the binary data to floating-
point data.
c) The value of x that has been converted to floating-point data is output
to D00203 and D00202.
d) The value of y that has been converted to floating-point data is output
to D00205 and D00204.
2. In order to find the distance r, Floating-point Math Instructions are used to
calculate the square root of x2+y2. The result is then output to D00213 and
D00212 as floating-point data.
3. In order to find the angle θ, Floating-point Math Instructions are used to
calculate tan–1 (y/x). ATAN(465) outputs the result in radians, so DEG(459)
is used to convert to degrees. The result is then output to D00219 and
D00218 as floating-point data.
4. The data is converted back from floating-point to BCD.
a) First FIX(450) is used to temporarily convert the floating-point data to
binary data, and then BCD(024) is used to convert the binary data to
BCD data.
b) The distance r is output to D00100.
c) The angle θ is output to D00101.

3-15-1 FLOATING TO 16-BIT: FIX(450)

Purpose Converts a 32-bit floating-point value to 16-bit signed binary data and places
the result in the specified result word.

Ladder Symbol
FIX(450)

S S: First source word

R R: Result word

Variations
Variations Executed Each Cycle for ON Condition FIX(450)
Executed Once for Upward Differentiation @FIX(450)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

594
Floating-point Math Instructions Section 3-15

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6143
Work Area W000 to W510 W000 to W511
Holding Bit Area H000 to H510 H000 to H511
Auxiliary Bit Area A000 to A958 A448 to A959
Timer Area T0000 to T4094 T0000 to T4095
Counter Area C0000 to C4094 C0000 to C4095
DM Area D00000 to D32766 D00000 to D32767
EM Area without bank E00000 to E32766 E00000 to E32767
EM Area with bank En_00000 to En_32766 En_00000 to En_32767
(n = 0 to C) (n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers --- DR0 to DR15
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description FIX(450) converts the integer portion of the 32-bit floating-point number in
S+1 and S (IEEE754-format) to 16-bit signed binary data and places the
result in R.

S+1 S Floating-point data (32 bits)

R Signed binary data (16 bits)

Only the integer portion of the floating-point data is converted, and the fraction
portion is truncated. The integer portion of the floating-point data must be
within the range of –32,768 to 32,767.
Example conversions:
A floating-point value of 3.5 is converted to 3.
A floating-point value of –3.5 is converted to –3.

595
Floating-point Math Instructions Section 3-15

Flags
Name Label Operation
Error Flag ER ON if the data in S+1 and S is not a number (NaN).
ON if the integer portion of S+1 and S is not within the
range of –32,768 to 32,767.
OFF in all other cases.
Equals Flag = ON if the result is 0000.
OFF in all other cases.
Negative Flag N ON if bit 15 of the result is ON.
OFF in all other cases.

Precautions The content of S+1 and S must be floating-point data and the integer portion
must be in the range of –32,768 to 32,767.

3-15-2 FLOATING TO 32-BIT: FIXL(451)

Purpose Converts a 32-bit floating-point value to 32-bit signed binary data and places
the result in the specified result words.
Ladder Symbol
FIXL(451)

S S: First source word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition FIXL(451)
Executed Once for Upward Differentiation @FIXL(451)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)

596
Floating-point Math Instructions Section 3-15

Area S R
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –()IR15

Description FIXL(451) converts the integer portion of the 32-bit floating-point number in
S+1 and S (IEEE754-format) to 32-bit signed binary data and places the
result in R+1 and R.

S+1 S Floating-point data (32 bits)

R+1 R Signed binary data (32 bits)

Only the integer portion of the floating-point data is converted, and the fraction
portion is truncated. (The integer portion of the floating-point data must be
within the range of –2,147,483,648 to 2,147,483,647.)
Example conversions:
A floating-point value of 2,147,483,640.5 is converted to 2,147,483,640.
A floating-point value of –214,748,340.5 is converted to –214,748,340.

Flags
Name Label Operation
Error Flag ER ON if the data in S+1 and S is not a number (NaN).
ON if the integer portion of S+1 and S is not within the
range of –2,147,483,648 to 2,147,483,647.
OFF in all other cases.
Equals Flag = ON if the result is 0000 0000.
OFF in all other cases.
Negative Flag N ON if bit 15 of R+1 is ON after execution.
OFF in all other cases.

Precautions The content of S+1 and S must be floating-point data and the integer portion
must be in the range of –2,147,483,648 to 2,147,483,647.

3-15-3 16-BIT TO FLOATING: FLT(452)

Purpose Converts a 16-bit signed binary value to 32-bit floating-point data and places
the result in the specified result words.

Ladder Symbol
FLT(452)

S S: Source word

R R: First result word

597
Floating-point Math Instructions Section 3-15

Variations
Variations Executed Each Cycle for ON Condition FLT(452)
Executed Once for Upward Differentiation @FLT(452)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6143 CIO 0000 to CIO 6142
Work Area W000 to W511 W000 to W510
Holding Bit Area H000 to H511 H000 to H510
Auxiliary Bit Area A000 to A959 A448 to A958
Timer Area T0000 to T4095 T0000 to T4094
Counter Area C0000 to C4095 C0000 to C4094
DM Area D00000 to D32767 D00000 to D32766
EM Area without bank E00000 to E32767 E00000 to E32766
EM Area with bank En_00000 to En_32767 En_00000 to En_32766
(n= 0 to C) (n= 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #0000 to #FFFF ---
(binary)
Data Registers DR0 to DR15 ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description FLT(452) converts the 16-bit signed binary value in S to 32-bit floating-point
data (IEEE754-format) and places the result in R+1 and R. A single 0 is
added after the decimal point in the floating-point result.

S Signed binary data (16 bits)

R+1 R Floating-point data (32 bits)

Only values within the range of –32,768 to 32,767 can be specified for S. To
convert signed binary data outside of that range, use FLTL(453).

598
Floating-point Math Instructions Section 3-15

Example conversions:
A signed binary value of 3 is converted to 3.0.
A signed binary value of –3 is converted to –3.0.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if both the exponent and mantissa of the result are 0.
OFF in all other cases.
Negative Flag N ON if the result is negative.
OFF in all other cases.

Precautions The content of S must contain signed binary data with a (decimal) value in the
range of –32,768 to 32,767.

3-15-4 32-BIT TO FLOATING: FLTL(453)

Purpose Converts a 32-bit signed binary value to 32-bit floating-point data and places
the result in the specified result words.

Ladder Symbol
FLTL(453)

S S: First source word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition FLTL(453)
Executed Once for Upward Differentiation @FLTL(453)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area S R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)

599
Floating-point Math Instructions Section 3-15

Area S R
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

Description FLTL(453) converts the 32-bit signed binary value in S+1 and S to 32-bit float-
ing-point data (IEEE754-format) and places the result in R+1 and R. A single
0 is added after the decimal point in the floating-point result.

S+1 S Signed binary data (32 bits)

R+1 R Floating-point data (32 bits)

Signed binary data within the range of –2,147,483,648 to 2,147,483,647 can

be specified for S+1 and S. The floating point value has 24 significant binary
digits (bits). The result will not be exact if a number greater than 16,777,215
(the maximum value that can be expressed in 24-bits) is converted by
FLTL(453).
Example Conversions:
A signed binary value of 16,777,215 is converted to 16,777,215.0.
A signed binary value of –16,777,215 is converted to –15,777,215.0.

Flags
Name Label Operation
Error Flag ER OFF
Equals Flag = ON if both the exponent and mantissa of the result are 0.
OFF in all other cases.
Negative Flag N ON if the result is negative.
OFF in all other cases.

Precautions The result will not be exact if a number with an absolute value greater than
16,777,215 (the maximum value that can be expressed in 24-bits) is con-
verted.

600
Floating-point Math Instructions Section 3-15

3-15-5 FLOATING-POINT ADD: +F(454)

Purpose Adds two 32-bit floating-point numbers and places the result in the specified
result words.
Ladder Symbol
+F(454)

Au Au: First augend word

Ad AD: First addend word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition +F(454)
Executed Once for Upward Differentiation @+F(454)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Au Ad R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF ---
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

601
Floating-point Math Instructions Section 3-15

Description +F(454) adds the 32-bit floating-point number in Ad+1 and Ad to the 32-bit
floating-point number in Au+1 and Au and places the result in R+1 and R.
(The floating point data must be in IEEE754 format.)

Au+1 Au Augend (floating-point data, 32 bits)

Addend (floating-point data, 32 bits)

+ Ad+1 Ad

R+1 R Result (floating-point data, 32 bits)

If the absolute value of the result is greater than the maximum value that can
be expressed as floating-point data, the Overflow Flag will turn ON and the
result will be output as ±∞.
If the absolute value of the result is less than the minimum value that can be
expressed as floating-point data, the Underflow Flag will turn ON and the
result will be output as 0.
The various combinations of augend and addend data will produce the results
shown in the following table.
Augend
Addend 0 Numeral +∞ –∞ NaN
0 0 Numeral +∞ –∞
Numeral Numeral See note 1. +∞ –∞
(See note 2.) (See note 2.)
+∞ +∞ +∞ +∞ See note 3.
(See note 2.)
–∞ –∞ –∞ See note 3. –∞
(See note 2.)
NaN See note 3.

Note 1. The results could be zero (including underflows), a numeral, +∞, or –∞.
2. With CJ1H-CPU@@H-R CPU Units, an undetermined value will be output.
3. The Error Flag will be turned ON and the instruction will not be executed.

Flags
Name Label Operation
Error Flag ER ON if the augend or addend data is not recognized as
floating-point data.
ON if the augend or addend data is not a number (NaN).
ON if +∞ and –∞ are added.
OFF in all other cases.
Equals Flag = ON if both the exponent and mantissa of the result are 0.
OFF in all other cases.
Overflow Flag OF ON if the absolute value of the result is too large to be
expressed as a 32-bit floating-point value.
Underflow Flag UF ON if the absolute value of the result is too small to be
expressed as a 32-bit floating-point value.
Negative Flag N ON if the result is negative.
OFF in all other cases.

Precautions The augend (Au+1 and Au) and Addend (Ad+1 and Ad) data must be in
IEEE754 floating-point data format.

602
Floating-point Math Instructions Section 3-15

3-15-6 FLOATING-POINT SUBTRACT: –F(455)

Purpose Subtracts one 32-bit floating-point number from another and places the result
in the specified result words.
Ladder Symbol
–F(455)

Mi Mi: First Minuend word

Su Su: First Subtrahend word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition –F(455)
Executed Once for Upward Differentiation @–F(455)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Mi Su R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM *D00000 to *D32767
addresses in BCD *E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants #00000000 to #FFFFFFFF
(binary)
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15

603
Floating-point Math Instructions Section 3-15

Description –F(455) subtracts the 32-bit floating-point number in Su+1 and Su from the
32-bit floating-point number in Mi+1 and Mi and places the result in R+1 and
R. (The floating point data must be in IEEE754 format.)

Mi+1 Mi Minuend (floating-point data, 32 bits)

Su
– Su+1 Subtrahend (floating-point data, 32 bits)

R+1 R Result (floating-point data, 32 bits)

If the absolute value of the result is greater than the maximum value that can
be expressed as floating-point data, the Overflow Flag will turn ON and the
result will be output as ±∞.
If the absolute value of the result is less than the minimum value that can be
expressed as floating-point data, the Underflow Flag will turn ON and the
result will be output as 0.
The various combinations of minuend and subtrahend data will produce the
results shown in the following table.
Minuend
Subtrahend 0 Numeral +∞ –∞ NaN
0 0 Numeral +∞ –∞
Numeral Numeral See note 1. +∞ –∞
(See note 2.) (See note 2.)
+∞ –∞ –∞ See note 3. –∞
(See note 2.) (See note 2.)
–∞ +∞ +∞ +∞ See note 3.
NaN See note 3.

Note 1. The results could be zero (including underflows), a numeral, +∞, or –∞.
2. With CJ1H-CPU@@H-R CPU Units, an undetermined value will be output.
3. The Error Flag will be turned ON and the instruction will not be executed.

Flags
Name Label Operation
Error Flag ER ON if the minuend or subtrahend data is not recognized
as floating-point data.
ON if the minuend or subtrahend is not a number (NaN).
ON if +∞ is subtracted from +∞.
ON if –∞ is subtracted from –∞.
OFF in all other cases.
Equals Flag = ON if both the exponent and mantissa of the result are 0.
OFF in all other cases.
Overflow Flag OF ON if the absolute value of the result is too large to be
expressed as a 32-bit floating-point value.
Underflow Flag UF ON if the absolute value of the result is too small to be
expressed as a 32-bit floating-point value.
Negative Flag N ON if the result is negative.
OFF in all other cases.

Precautions The Minuend (Mi+1 and Mi) and Subtrahend (Su+1 and Su) data must be in
IEEE754 floating-point data format.

604
Floating-point Math Instructions Section 3-15

3-15-7 FLOATING-POINT MULTIPLY: *F(456)

Purpose Multiplies two 32-bit floating-point numbers and places the result in the speci-
fied result words.
Ladder Symbol
*F(456)

Md Md: First Multiplicand word

Mr Mr: First Multiplier word

R R: First result word

Variations
Variations Executed Each Cycle for ON Condition *F(456)
Executed Once for Upward Differentiation @*F(456)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK

Operand Specifications
Area Md Mr R
CIO Area CIO 0000 to CIO 6142
Work Area W000 to W510
Holding Bit Area H000 to H510
Auxiliary Bit Area A000 to A958 A448 to A958
Timer Area T0000 to T4094
Counter Area C0000 to C4094
DM Area D00000 to D32766
EM Area without bank E00000 to E32766
EM Area with bank En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM @ D00000 to @ D32767
addresses in binary @ E00000 to @ E32767
@ En_00000 to @ En_32767