TE X AS I NS TRUM E NTS - P RO DUCTION D ATA

Tiva™ TM4C1294NCPDT Microcontroller

D ATA SH E E T

D S -T M 4C 1294 NCP DT - 1 5 8 6 3 . 2 7 4 3 C o p yri g h t © 2 0 07-2014

S P M S 433B Te xa s In stru me n ts In co rporated
Copyright
Copyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are
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Table of Contents
Revision History ............................................................................................................................. 45
About This Document .................................................................................................................... 48
Audience .............................................................................................................................................. 48
About This Manual ................................................................................................................................ 48
Related Documents ............................................................................................................................... 48
Documentation Conventions .................................................................................................................. 49
1 Architectural Overview .......................................................................................... 51
1.1 Tiva™ C Series Overview .............................................................................................. 51
1.2 TM4C1294NCPDT Microcontroller Overview .................................................................. 52
1.3 TM4C1294NCPDT Microcontroller Features ................................................................... 55
1.3.1 ARM Cortex-M4F Processor Core .................................................................................. 55
1.3.2 On-Chip Memory ........................................................................................................... 57
1.3.3 External Peripheral Interface ......................................................................................... 59
1.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 61
1.3.5 Serial Communications Peripherals ................................................................................ 61
1.3.6 System Integration ........................................................................................................ 67
1.3.7 Advanced Motion Control ............................................................................................... 74
1.3.8 Analog .......................................................................................................................... 76
1.3.9 JTAG and ARM Serial Wire Debug ................................................................................ 78
1.3.10 Packaging and Temperature .......................................................................................... 78
1.4 TM4C1294NCPDT Microcontroller Hardware Details ....................................................... 78
1.5 Kits .............................................................................................................................. 79
1.6 Support Information ....................................................................................................... 79
2 The Cortex-M4F Processor ................................................................................... 80
2.1 Block Diagram .............................................................................................................. 81
2.2 Overview ...................................................................................................................... 82
2.2.1 System-Level Interface .................................................................................................. 82
2.2.2 Integrated Configurable Debug ...................................................................................... 82
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 83
2.2.4 Cortex-M4F System Component Details ......................................................................... 83
2.3 Programming Model ...................................................................................................... 84
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 84
2.3.2 Stacks .......................................................................................................................... 85
2.3.3 Register Map ................................................................................................................ 85
2.3.4 Register Descriptions .................................................................................................... 87
2.3.5 Exceptions and Interrupts ............................................................................................ 103
2.3.6 Data Types ................................................................................................................. 103
2.4 Memory Model ............................................................................................................ 103
2.4.1 Memory Regions, Types and Attributes ......................................................................... 106
2.4.2 Memory System Ordering of Memory Accesses ............................................................ 107
2.4.3 Behavior of Memory Accesses ..................................................................................... 107
2.4.4 Software Ordering of Memory Accesses ....................................................................... 108
2.4.5 Bit-Banding ................................................................................................................. 109
2.4.6 Data Storage .............................................................................................................. 111
2.4.7 Synchronization Primitives ........................................................................................... 112

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2.5 Exception Model ......................................................................................................... 113

2.5.1 Exception States ......................................................................................................... 114
2.5.2 Exception Types .......................................................................................................... 114
2.5.3 Exception Handlers ..................................................................................................... 119
2.5.4 Vector Table ................................................................................................................ 119
2.5.5 Exception Priorities ...................................................................................................... 120
2.5.6 Interrupt Priority Grouping ............................................................................................ 120
2.5.7 Exception Entry and Return ......................................................................................... 120
2.6 Fault Handling ............................................................................................................. 123
2.6.1 Fault Types ................................................................................................................. 124
2.6.2 Fault Escalation and Hard Faults .................................................................................. 124
2.6.3 Fault Status Registers and Fault Address Registers ...................................................... 125
2.6.4 Lockup ....................................................................................................................... 125
2.7 Power Management .................................................................................................... 126
2.7.1 Entering Sleep Modes ................................................................................................. 126
2.7.2 Wake Up from Sleep Mode .......................................................................................... 126
2.8 Instruction Set Summary .............................................................................................. 127
3 Cortex-M4 Peripherals ......................................................................................... 134
3.1 Functional Description ................................................................................................. 134
3.1.1 System Timer (SysTick) ............................................................................................... 135
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 136
3.1.3 System Control Block (SCB) ........................................................................................ 137
3.1.4 Memory Protection Unit (MPU) ..................................................................................... 137
3.1.5 Floating-Point Unit (FPU) ............................................................................................. 142
3.2 Register Map .............................................................................................................. 146
3.3 System Timer (SysTick) Register Descriptions .............................................................. 149
3.4 NVIC Register Descriptions .......................................................................................... 153
3.5 System Control Block (SCB) Register Descriptions ........................................................ 163
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 192
3.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 201
4 JTAG Interface ...................................................................................................... 207
4.1 Block Diagram ............................................................................................................ 208
4.2 Signal Description ....................................................................................................... 208
4.3 Functional Description ................................................................................................. 209
4.3.1 JTAG Interface Pins ..................................................................................................... 209
4.3.2 JTAG TAP Controller ................................................................................................... 211
4.3.3 Shift Registers ............................................................................................................ 212
4.3.4 Operational Considerations .......................................................................................... 212
4.4 Initialization and Configuration ..................................................................................... 215
4.5 Register Descriptions .................................................................................................. 215
4.5.1 Instruction Register (IR) ............................................................................................... 216
4.5.2 Data Registers ............................................................................................................ 217
5 System Control ..................................................................................................... 220
5.1 Signal Description ....................................................................................................... 220
5.2 Functional Description ................................................................................................. 220
5.2.1 Device Identification .................................................................................................... 220
5.2.2 Reset Control .............................................................................................................. 221
5.2.3 Non-Maskable Interrupt ............................................................................................... 228

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5.2.4 Power Control ............................................................................................................. 229

5.2.5 Clock Control .............................................................................................................. 230
5.2.6 System Control ........................................................................................................... 239
5.3 Initialization and Configuration ..................................................................................... 246
5.4 Register Map .............................................................................................................. 247
5.5 System Control Register Descriptions (System Control Offset) ....................................... 254
6 Processor Support and Exception Module ........................................................ 523
6.1 Functional Description ................................................................................................. 523
6.2 Register Map .............................................................................................................. 523
6.3 Register Descriptions .................................................................................................. 523
7 Hibernation Module .............................................................................................. 531
7.1 Block Diagram ............................................................................................................ 533
7.2 Signal Description ....................................................................................................... 533
7.3 Functional Description ................................................................................................. 534
7.3.1 Register Access Timing ............................................................................................... 535
7.3.2 Hibernation Clock Source ............................................................................................ 535
7.3.3 System Implementation ............................................................................................... 538
7.3.4 Battery Management ................................................................................................... 539
7.3.5 Real-Time Clock .......................................................................................................... 539
7.3.6 Tamper ....................................................................................................................... 542
7.3.7 Battery-Backed Memory .............................................................................................. 545
7.3.8 Power Control Using HIB ............................................................................................. 545
7.3.9 Power Control Using VDD3ON Mode ........................................................................... 546
7.3.10 Initiating Hibernate ...................................................................................................... 546
7.3.11 Waking from Hibernate ................................................................................................ 546
7.3.12 Arbitrary Power Removal ............................................................................................. 547
7.3.13 Interrupts and Status ................................................................................................... 548
7.4 Initialization and Configuration ..................................................................................... 548
7.4.1 Initialization ................................................................................................................. 548
7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 549
7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 549
7.4.4 External Wake-Up from Hibernation .............................................................................. 550
7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 551
7.4.6 Tamper Initialization ..................................................................................................... 551
7.5 Register Map .............................................................................................................. 551
7.6 Register Descriptions .................................................................................................. 553
8 Internal Memory ................................................................................................... 600
8.1 Block Diagram ............................................................................................................ 600
8.2 Functional Description ................................................................................................. 602
8.2.1 SRAM ........................................................................................................................ 602
8.2.2 ROM .......................................................................................................................... 602
8.2.3 Flash Memory ............................................................................................................. 604
8.2.4 EEPROM .................................................................................................................... 615
8.2.5 Bus Matrix Memory Accesses ...................................................................................... 621
8.3 Register Map .............................................................................................................. 621
8.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 624
8.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 650
8.6 Memory Register Descriptions (System Control Offset) .................................................. 667

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9 Micro Direct Memory Access (μDMA) ................................................................ 678

9.1 Block Diagram ............................................................................................................ 679
9.2 Functional Description ................................................................................................. 679
9.2.1 Channel Assignments .................................................................................................. 680
9.2.2 Priority ........................................................................................................................ 681
9.2.3 Arbitration Size ............................................................................................................ 682
9.2.4 Request Types ............................................................................................................ 682
9.2.5 Channel Configuration ................................................................................................. 683
9.2.6 Transfer Modes ........................................................................................................... 685
9.2.7 Transfer Size and Increment ........................................................................................ 693
9.2.8 Peripheral Interface ..................................................................................................... 693
9.2.9 Software Request ........................................................................................................ 694
9.2.10 Interrupts and Errors .................................................................................................... 694
9.3 Initialization and Configuration ..................................................................................... 694
9.3.1 Module Initialization ..................................................................................................... 694
9.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 695
9.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 696
9.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 698
9.3.5 Configuring Channel Assignments ................................................................................ 701
9.4 Register Map .............................................................................................................. 701
9.5 μDMA Channel Control Structure ................................................................................. 702
9.6 μDMA Register Descriptions ........................................................................................ 709
10 General-Purpose Input/Outputs (GPIOs) ........................................................... 742
10.1 Signal Description ....................................................................................................... 743
10.2 Pad Capabilities .......................................................................................................... 746
10.3 Functional Description ................................................................................................. 747
10.3.1 Data Control ............................................................................................................... 748
10.3.2 Interrupt Control .......................................................................................................... 750
10.3.3 Mode Control .............................................................................................................. 751
10.3.4 Commit Control ........................................................................................................... 752
10.3.5 Pad Control ................................................................................................................. 752
10.3.6 Identification ............................................................................................................... 753
10.4 Initialization and Configuration ..................................................................................... 753
10.5 Register Map .............................................................................................................. 755
10.6 Register Descriptions .................................................................................................. 758
11 External Peripheral Interface (EPI) ..................................................................... 815
11.1 EPI Block Diagram ...................................................................................................... 816
11.2 Signal Description ....................................................................................................... 817
11.3 Functional Description ................................................................................................. 818
11.3.1 Master Access to EPI .................................................................................................. 819
11.3.2 Non-Blocking Reads .................................................................................................... 819
11.3.3 DMA Operation ........................................................................................................... 820
11.4 Initialization and Configuration ..................................................................................... 821
11.4.1 EPI Interface Options .................................................................................................. 822
11.4.2 SDRAM Mode ............................................................................................................. 822
11.4.3 Host Bus Mode ........................................................................................................... 826
11.4.4 General-Purpose Mode ............................................................................................... 847
11.5 Register Map .............................................................................................................. 854

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11.6 Register Descriptions .................................................................................................. 856

12 Cyclical Redundancy Check (CRC) .................................................................... 946
12.1 Functional Description ................................................................................................. 946
12.1.1 CRC Support .............................................................................................................. 946
12.2 Initialization and Configuration ..................................................................................... 948
12.2.1 CRC Initialization and Configuration ............................................................................. 948
12.3 Register Map .............................................................................................................. 949
12.4 CRC Module Register Descriptions .............................................................................. 949
13 General-Purpose Timers ...................................................................................... 955
13.1 Block Diagram ............................................................................................................ 956
13.2 Signal Description ....................................................................................................... 957
13.3 Functional Description ................................................................................................. 958
13.3.1 GPTM Reset Conditions .............................................................................................. 959
13.3.2 Timer Clock Source ..................................................................................................... 959
13.3.3 Timer Modes ............................................................................................................... 959
13.3.4 Wait-for-Trigger Mode .................................................................................................. 968
13.3.5 Synchronizing GP Timer Blocks ................................................................................... 969
13.3.6 DMA Operation ........................................................................................................... 970
13.3.7 ADC Operation ............................................................................................................ 970
13.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 970
13.4 Initialization and Configuration ..................................................................................... 971
13.4.1 One-Shot/Periodic Timer Mode .................................................................................... 971
13.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 972
13.4.3 Input Edge-Count Mode ............................................................................................... 972
13.4.4 Input Edge Time Mode ................................................................................................. 973
13.4.5 PWM Mode ................................................................................................................. 973
13.5 Register Map .............................................................................................................. 974
13.6 Register Descriptions .................................................................................................. 975
14 Watchdog Timers ............................................................................................... 1028
14.1 Block Diagram ........................................................................................................... 1029
14.2 Functional Description ............................................................................................... 1029
14.2.1 Register Access Timing ............................................................................................. 1030
14.3 Initialization and Configuration .................................................................................... 1030
14.4 Register Map ............................................................................................................ 1030
14.5 Register Descriptions ................................................................................................. 1031
15 Analog-to-Digital Converter (ADC) ................................................................... 1053
15.1 Block Diagram ........................................................................................................... 1054
15.2 Signal Description ..................................................................................................... 1055
15.3 Functional Description ............................................................................................... 1056
15.3.1 Sample Sequencers .................................................................................................. 1056
15.3.2 Module Control .......................................................................................................... 1057
15.3.3 Hardware Sample Averaging Circuit ........................................................................... 1062
15.3.4 Analog-to-Digital Converter ........................................................................................ 1063
15.3.5 Differential Sampling .................................................................................................. 1065
15.3.6 Internal Temperature Sensor ...................................................................................... 1067
15.3.7 Digital Comparator Unit .............................................................................................. 1068
15.4 Initialization and Configuration .................................................................................... 1072

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15.4.1 Module Initialization ................................................................................................... 1072

15.4.2 Sample Sequencer Configuration ............................................................................... 1073
15.5 Register Map ............................................................................................................ 1073
15.6 Register Descriptions ................................................................................................. 1076
16 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 1161
16.1 Block Diagram ........................................................................................................... 1162
16.2 Signal Description ..................................................................................................... 1162
16.3 Functional Description ............................................................................................... 1164
16.3.1 Transmit/Receive Logic .............................................................................................. 1164
16.3.2 Baud-Rate Generation ............................................................................................... 1165
16.3.3 Data Transmission ..................................................................................................... 1166
16.3.4 Serial IR (SIR) ........................................................................................................... 1166
16.3.5 ISO 7816 Support ...................................................................................................... 1167
16.3.6 Modem Handshake Support ....................................................................................... 1168
16.3.7 9-Bit UART Mode ...................................................................................................... 1169
16.3.8 FIFO Operation ......................................................................................................... 1169
16.3.9 Interrupts .................................................................................................................. 1170
16.3.10 Loopback Operation .................................................................................................. 1171
16.3.11 DMA Operation ......................................................................................................... 1171
16.4 Initialization and Configuration .................................................................................... 1172
16.5 Register Map ............................................................................................................ 1173
16.6 Register Descriptions ................................................................................................. 1174
17 Quad Synchronous Serial Interface (QSSI) ..................................................... 1226
17.1 Block Diagram ........................................................................................................... 1226
17.2 Signal Description ..................................................................................................... 1227
17.3 Functional Description ............................................................................................... 1228
17.3.1 Bit Rate Generation ................................................................................................... 1229
17.3.2 FIFO Operation ......................................................................................................... 1229
17.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 1230
17.3.4 SSInFSS Function ..................................................................................................... 1231
17.3.5 High Speed Clock Operation ...................................................................................... 1232
17.3.6 Interrupts .................................................................................................................. 1232
17.3.7 Frame Formats ......................................................................................................... 1233
17.3.8 DMA Operation ......................................................................................................... 1240
17.4 Initialization and Configuration .................................................................................... 1240
17.4.1 Enhanced Mode Configuration ................................................................................... 1242
17.5 Register Map ............................................................................................................ 1243
17.6 Register Descriptions ................................................................................................. 1244
18 Inter-Integrated Circuit (I2C) Interface .............................................................. 1275
18.1 Block Diagram ........................................................................................................... 1276
18.2 Signal Description ..................................................................................................... 1277
18.3 Functional Description ............................................................................................... 1278
18.3.1 I2C Bus Functional Overview ...................................................................................... 1278
18.3.2 Available Speed Modes ............................................................................................. 1284
18.3.3 Interrupts .................................................................................................................. 1286
18.3.4 Loopback Operation .................................................................................................. 1287
18.3.5 FIFO and µDMA Operation ........................................................................................ 1287
18.3.6 Command Sequence Flow Charts .............................................................................. 1289

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18.4 Initialization and Configuration .................................................................................... 1297

18.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 1297
18.4.2 Configure the I2C Master to High Speed Mode ............................................................ 1298
18.5 Register Map ............................................................................................................ 1299
18.6 Register Descriptions (I2C Master) .............................................................................. 1301
18.7 Register Descriptions (I2C Slave) ............................................................................... 1330
18.8 Register Descriptions (I2C Status and Control) ............................................................ 1347
19 Controller Area Network (CAN) Module ........................................................... 1356
19.1 Block Diagram ........................................................................................................... 1357
19.2 Signal Description ..................................................................................................... 1357
19.3 Functional Description ............................................................................................... 1358
19.3.1 Initialization ............................................................................................................... 1359
19.3.2 Operation .................................................................................................................. 1359
19.3.3 Transmitting Message Objects ................................................................................... 1360
19.3.4 Configuring a Transmit Message Object ...................................................................... 1361
19.3.5 Updating a Transmit Message Object ......................................................................... 1362
19.3.6 Accepting Received Message Objects ........................................................................ 1362
19.3.7 Receiving a Data Frame ............................................................................................ 1363
19.3.8 Receiving a Remote Frame ........................................................................................ 1363
19.3.9 Receive/Transmit Priority ........................................................................................... 1363
19.3.10 Configuring a Receive Message Object ...................................................................... 1364
19.3.11 Handling of Received Message Objects ...................................................................... 1365
19.3.12 Handling of Interrupts ................................................................................................ 1367
19.3.13 Test Mode ................................................................................................................. 1368
19.3.14 Bit Timing Configuration Error Considerations ............................................................. 1370
19.3.15 Bit Time and Bit Rate ................................................................................................. 1370
19.3.16 Calculating the Bit Timing Parameters ........................................................................ 1372
19.4 Register Map ............................................................................................................ 1375
19.5 CAN Register Descriptions ......................................................................................... 1376
20 Ethernet Controller ............................................................................................ 1407
20.1 Block Diagram ........................................................................................................... 1408
20.2 Signal Description ..................................................................................................... 1408
20.3 Functional Description ............................................................................................... 1409
20.3.1 Ethernet Clock Control ............................................................................................... 1409
20.3.2 DMA Controller ......................................................................................................... 1410
20.3.3 TX/RX Controller ....................................................................................................... 1434
20.3.4 MAC Operation ......................................................................................................... 1438
20.3.5 IEEE 1588 and Advanced Timestamp Function ........................................................... 1440
20.3.6 Frame Filtering .......................................................................................................... 1449
20.3.7 Source Address, VLAN, and CRC Insertion, Replacement or Deletion .......................... 1450
20.3.8 Checksum Offload Engine .......................................................................................... 1452
20.3.9 MAC Management Counters ...................................................................................... 1453
20.3.10 Power Management Module ....................................................................................... 1454
20.3.11 Serial Management Interface ..................................................................................... 1457
20.3.12 Interrupt Configuration ............................................................................................... 1457
20.4 Ethernet PHY ............................................................................................................ 1457
20.4.1 Integrated PHY Block Diagram ................................................................................... 1457
20.4.2 Functional Description ............................................................................................... 1458

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20.4.3 Interface Configuration ............................................................................................... 1463

20.5 Initialization and Configuration .................................................................................... 1464
20.5.1 Ethernet PHY Initialization .......................................................................................... 1465
20.6 Register Map ............................................................................................................ 1467
20.7 Ethernet MAC Register Descriptions ........................................................................... 1470
20.8 Ethernet PHY Register Descriptions ........................................................................... 1589
21 Universal Serial Bus (USB) Controller ............................................................. 1644
21.1 Block Diagram ........................................................................................................... 1645
21.2 Signal Description ..................................................................................................... 1645
21.3 Register Map ............................................................................................................ 1646
22 Analog Comparators .......................................................................................... 1653
22.1 Block Diagram ........................................................................................................... 1654
22.2 Signal Description ..................................................................................................... 1654
22.3 Functional Description ............................................................................................... 1655
22.3.1 Internal Reference Programming ................................................................................ 1656
22.4 Initialization and Configuration .................................................................................... 1658
22.5 Register Map ............................................................................................................ 1659
22.6 Register Descriptions ................................................................................................. 1659
23 Pulse Width Modulator (PWM) .......................................................................... 1669
23.1 Block Diagram ........................................................................................................... 1670
23.2 Signal Description ..................................................................................................... 1672
23.3 Functional Description ............................................................................................... 1672
23.3.1 Clock Configuration ................................................................................................... 1672
23.3.2 PWM Timer ............................................................................................................... 1672
23.3.3 PWM Comparators .................................................................................................... 1673
23.3.4 PWM Signal Generator .............................................................................................. 1674
23.3.5 Dead-Band Generator ............................................................................................... 1675
23.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 1675
23.3.7 Synchronization Methods .......................................................................................... 1676
23.3.8 Fault Conditions ........................................................................................................ 1677
23.3.9 Output Control Block .................................................................................................. 1678
23.4 Initialization and Configuration .................................................................................... 1678
23.5 Register Map ............................................................................................................ 1679
23.6 Register Descriptions ................................................................................................. 1682
24 Quadrature Encoder Interface (QEI) ................................................................. 1748
24.1 Block Diagram ........................................................................................................... 1748
24.2 Signal Description ..................................................................................................... 1750
24.3 Functional Description ............................................................................................... 1750
24.4 Initialization and Configuration .................................................................................... 1753
24.5 Register Map ............................................................................................................ 1753
24.6 Register Descriptions ................................................................................................. 1754
25 Pin Diagram ........................................................................................................ 1771
26 Signal Tables ...................................................................................................... 1772
26.1 Signals by Pin Number .............................................................................................. 1773
26.2 Signals by Signal Name ............................................................................................. 1785
26.3 Signals by Function, Except for GPIO ......................................................................... 1797
26.4 GPIO Pins and Alternate Functions ............................................................................ 1808

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26.5 Possible Pin Assignments for Alternate Functions ....................................................... 1811

26.6 Connections for Unused Signals ................................................................................. 1816
27 Electrical Characteristics .................................................................................. 1818
27.1 Maximum Ratings ...................................................................................................... 1818
27.2 Operating Characteristics ........................................................................................... 1819
27.3 Recommended Operating Conditions ......................................................................... 1820
27.3.1 DC Operating Conditions ........................................................................................... 1820
27.3.2 Recommended GPIO Operating Characteristics .......................................................... 1820
27.4 Load Conditions ........................................................................................................ 1823
27.5 JTAG and Boundary Scan .......................................................................................... 1824
27.6 Power and Brown-Out ............................................................................................... 1826
27.6.1 VDDA Levels .............................................................................................................. 1826
27.6.2 VDD Levels ................................................................................................................ 1827
27.6.3 VDDC Levels .............................................................................................................. 1828
27.6.4 Response ................................................................................................................. 1829
27.7 Reset ........................................................................................................................ 1831
27.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1834
27.9 Clocks ...................................................................................................................... 1835
27.9.1 PLL Specifications ..................................................................................................... 1835
27.9.2 PIOSC Specifications ................................................................................................ 1837
27.9.3 Low-Frequency Internal Oscillator Specifications ......................................................... 1837
27.9.4 Hibernation Clock Source Specifications ..................................................................... 1837
27.9.5 Main Oscillator Specifications ..................................................................................... 1838
27.9.6 System Clock Specification with ADC Operation .......................................................... 1842
27.9.7 System Clock Specification with USB Operation .......................................................... 1842
27.10 Sleep Modes ............................................................................................................. 1843
27.11 Hibernation Module ................................................................................................... 1845
27.12 Flash Memory ........................................................................................................... 1847
27.13 EEPROM .................................................................................................................. 1848
27.14 Input/Output Pin Characteristics ................................................................................. 1849
27.14.1 Types of I/O Pins and ESD Protection ......................................................................... 1851
27.15 External Peripheral Interface (EPI) .............................................................................. 1853
27.16 Analog-to-Digital Converter (ADC) .............................................................................. 1861
27.17 Synchronous Serial Interface (SSI) ............................................................................. 1867
27.18 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1870
27.19 Ethernet Controller .................................................................................................... 1871
27.19.1 DC Characteristics .................................................................................................... 1871
27.19.2 Clock Characteristics ................................................................................................. 1871
27.19.3 AC Characteristics ..................................................................................................... 1872
27.20 Universal Serial Bus (USB) Controller ......................................................................... 1875
27.21 Analog Comparator ................................................................................................... 1877
27.22 Pulse-Width Modulator (PWM) ................................................................................... 1879
27.23 Current Consumption ................................................................................................ 1880
A Package Information .......................................................................................... 1885
A.1 Orderable Devices ..................................................................................................... 1885
A.2 Device Nomenclature ................................................................................................ 1885
A.3 Device Markings ........................................................................................................ 1885
A.4 Packaging Diagram ................................................................................................... 1887

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List of Figures
Figure 1-1. Tiva™ TM4C1294NCPDT Microcontroller High-Level Block Diagram ....................... 54
Figure 2-1. CPU Block Diagram ............................................................................................. 82
Figure 2-2. TPIU Block Diagram ............................................................................................ 83
Figure 2-3. Cortex-M4F Register Set ...................................................................................... 86
Figure 2-4. Bit-Band Mapping .............................................................................................. 111
Figure 2-5. Data Storage ..................................................................................................... 112
Figure 2-6. Vector Table ...................................................................................................... 119
Figure 2-7. Exception Stack Frame ...................................................................................... 122
Figure 3-1. SRD Use Example ............................................................................................. 140
Figure 3-2. FPU Register Bank ............................................................................................ 143
Figure 4-1. JTAG Module Block Diagram .............................................................................. 208
Figure 4-2. Test Access Port State Machine ......................................................................... 212
Figure 4-3. IDCODE Register Format ................................................................................... 218
Figure 4-4. BYPASS Register Format ................................................................................... 218
Figure 4-5. Boundary Scan Register Format ......................................................................... 218
Figure 5-1. Basic RST Configuration .................................................................................... 224
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 224
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 224
Figure 5-4. Power Architecture ............................................................................................ 229
Figure 5-5. Main Clock Tree ................................................................................................ 233
Figure 5-6. Module Clock Selection ...................................................................................... 242
Figure 7-1. Hibernation Module Block Diagram ..................................................................... 533
Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 537
Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 537
Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 538
Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 542
Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 542
Figure 7-7. Tamper Block Diagram ....................................................................................... 542
Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 543
Figure 8-1. Internal Memory Block Diagram .......................................................................... 601
Figure 8-2. Flash Memory Configuration ............................................................................... 605
Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 606
Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 606
Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 607
Figure 8-6. Prefetch Fills from Flash ..................................................................................... 608
Figure 8-7. Mirror Mode Function ......................................................................................... 609
Figure 9-1. μDMA Block Diagram ......................................................................................... 679
Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 686
Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 688
Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 689
Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 691
Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 692
Figure 10-1. Digital I/O Pads ................................................................................................. 747
Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 748
Figure 10-3. GPIODATA Write Example ................................................................................. 749

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Figure 10-4. GPIODATA Read Example ................................................................................. 749

Figure 11-1. EPI Block Diagram ............................................................................................. 817
Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 824
Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 825
Figure 11-4. SDRAM Write Cycle ........................................................................................... 826
Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 836
Figure 11-6. iRDY Signal Connection ..................................................................................... 836
Figure 11-7. PSRAM Burst Read ........................................................................................... 839
Figure 11-8. PSRAM Burst Write ........................................................................................... 839
Figure 11-9. Read Delay During Refresh Event ...................................................................... 840
Figure 11-10. Write Delay During Refresh Event ....................................................................... 841
Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 842
Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 845
Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 845
Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 846
Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or
Quad CSn ......................................................................................................... 846
Figure 11-16. Continuous Read Mode Accesses ...................................................................... 846
Figure 11-17. Write Followed by Read to External FIFO ............................................................ 847
Figure 11-18. Two-Entry FIFO ................................................................................................. 847
Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 850
Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 851
Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 851
Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 852
Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 852
Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 852
Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 852
Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 853
Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 853
Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 853
Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 854
Figure 13-1. GPTM Module Block Diagram ............................................................................ 956
Figure 13-2. Input Edge-Count Mode Example, Counting Down ............................................... 964
Figure 13-3. 16-Bit Input Edge-Time Mode Example ............................................................... 965
Figure 13-4. 16-Bit PWM Mode Example ................................................................................ 967
Figure 13-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 967
Figure 13-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 968
Figure 13-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 968
Figure 13-8. Timer Daisy Chain ............................................................................................. 969
Figure 14-1. WDT Module Block Diagram ............................................................................. 1029
Figure 15-1. Implementation of Two ADC Blocks .................................................................. 1054
Figure 15-2. ADC Module Block Diagram ............................................................................. 1055
Figure 15-3. ADC Sample Phases ....................................................................................... 1060
Figure 15-4. Doubling the ADC Sample Rate ........................................................................ 1060
Figure 15-5. Skewed Sampling ............................................................................................ 1061
Figure 15-6. Sample Averaging Example .............................................................................. 1063
Figure 15-7. ADC Input Equivalency .................................................................................... 1064

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Figure 15-8. ADC Voltage Reference ................................................................................... 1064

Figure 15-9. ADC Conversion Result ................................................................................... 1065
Figure 15-10. Differential Voltage Representation ................................................................... 1067
Figure 15-11. Internal Temperature Sensor Characteristic ....................................................... 1068
Figure 15-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1070
Figure 15-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1071
Figure 15-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1072
Figure 16-1. UART Module Block Diagram ........................................................................... 1162
Figure 16-2. UART Character Frame .................................................................................... 1165
Figure 16-3. IrDA Data Modulation ....................................................................................... 1167
Figure 17-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1227
Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1234
Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1235
Figure 17-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1236
Figure 17-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1236
Figure 17-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1237
Figure 17-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1238
Figure 17-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1238
Figure 17-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1239
Figure 18-1. I2C Block Diagram ........................................................................................... 1276
Figure 18-2. I2C Bus Configuration ....................................................................................... 1278
Figure 18-3. START and STOP Conditions ........................................................................... 1279
Figure 18-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1279
Figure 18-5. R/S Bit in First Byte .......................................................................................... 1280
Figure 18-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1280
Figure 18-7. High-Speed Data Format .................................................................................. 1286
Figure 18-8. Master Single TRANSMIT ................................................................................ 1290
Figure 18-9. Master Single RECEIVE ................................................................................... 1291
Figure 18-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1292
Figure 18-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1293
Figure 18-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1294
Figure 18-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1295
Figure 18-14. Standard High Speed Mode Master Transmit ..................................................... 1296
Figure 18-15. Slave Command Sequence .............................................................................. 1297
Figure 19-1. CAN Controller Block Diagram .......................................................................... 1357
Figure 19-2. CAN Data/Remote Frame ................................................................................. 1358
Figure 19-3. Message Objects in a FIFO Buffer .................................................................... 1367
Figure 19-4. CAN Bit Time ................................................................................................... 1371
Figure 20-1. Ethernet MAC with Integrated PHY Interface ..................................................... 1408
Figure 20-2. Ethernet MAC and PHY Clock Structure ............................................................ 1410
Figure 20-3. Enhanced Transmit Descriptor Structure ........................................................... 1414
Figure 20-4. Enhanced Receive Descriptor Structure ............................................................ 1419
Figure 20-5. TX DMA Default Operation Using Descriptors .................................................... 1426
Figure 20-6. TX DMA OSF Mode Operation Using Descriptors .............................................. 1428
Figure 20-7. RX DMA Operation Flow .................................................................................. 1431
Figure 20-8. Networked Time Synchronization ...................................................................... 1441
Figure 20-9. System Time Update Using Fine Correction Method .......................................... 1443

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Figure 20-10. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path

Correction ....................................................................................................... 1446
Figure 20-11. Wake-Up Frame Filter Register Bank ................................................................ 1454
Figure 20-12. Integrated PHY Diagram .................................................................................. 1458
Figure 20-13. Interface to Ethernet Jack ................................................................................. 1464
Figure 21-1. USB Module Block Diagram ............................................................................. 1645
Figure 22-1. Analog Comparator Module Block Diagram ....................................................... 1654
Figure 22-2. Structure of Comparator Unit ............................................................................ 1655
Figure 22-3. Comparator Internal Reference Structure .......................................................... 1656
Figure 23-1. PWM Module Diagram ..................................................................................... 1671
Figure 23-2. PWM Generator Block Diagram ........................................................................ 1671
Figure 23-3. PWM Count-Down Mode .................................................................................. 1674
Figure 23-4. PWM Count-Up/Down Mode ............................................................................. 1674
Figure 23-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1675
Figure 23-6. PWM Dead-Band Generator ............................................................................. 1675
Figure 24-1. QEI Block Diagram .......................................................................................... 1749
Figure 24-2. QEI Input Signal Logic ...................................................................................... 1750
Figure 24-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1752
Figure 25-1. 128-Pin TQFP Package Pin Diagram ................................................................ 1771
Figure 27-1. Load Conditions ............................................................................................... 1823
Figure 27-2. JTAG Test Clock Input Timing ........................................................................... 1825
Figure 27-3. JTAG Test Access Port (TAP) Timing ................................................................ 1825
Figure 27-4. Power and Brown-Out Assertions vs VDDA Levels .............................................. 1827
Figure 27-5. Power and Brown-Out Assertions vs VDD Levels ................................................ 1828
Figure 27-6. POK Assertion vs VDDC ................................................................................... 1829
Figure 27-7. POR-BOR VDD Glitch Response ....................................................................... 1829
Figure 27-8. POR-BOR VDD Droop Response ...................................................................... 1830
Figure 27-9. Digital Power-On Reset Timing ......................................................................... 1831
Figure 27-10. Brown-Out Reset Timing .................................................................................. 1832
Figure 27-11. External Reset Timing (RST) ............................................................................ 1832
Figure 27-12. Software Reset Timing ..................................................................................... 1832
Figure 27-13. Watchdog Reset Timing ................................................................................... 1832
Figure 27-14. MOSC Failure Reset Timing ............................................................................. 1833
Figure 27-15. Hibernation Module Timing ............................................................................... 1846
Figure 27-16. ESD Protection ................................................................................................ 1851
Figure 27-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 1852
Figure 27-18. SDRAM Initialization and Load Mode Register Timing ........................................ 1854
Figure 27-19. SDRAM Read Timing ....................................................................................... 1854
Figure 27-20. SDRAM Write Timing ....................................................................................... 1855
Figure 27-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 1856
Figure 27-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 1856
Figure 27-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 1857
Figure 27-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 1857
Figure 27-25. General-Purpose Mode Read and Write Timing ................................................. 1858
Figure 27-26. PSRAM Single Burst Read ............................................................................... 1859
Figure 27-27. PSRAM Single Burst Write ............................................................................... 1860
Figure 27-28. ADC External Reference Filtering ..................................................................... 1866
Figure 27-29. ADC Input Equivalency .................................................................................... 1866

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Figure 27-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1868
Figure 27-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1868
Figure 27-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1869
Figure 27-33. I2C Timing ....................................................................................................... 1870
Figure 27-34. MOSC Crystal Characteristics for Ethernet ........................................................ 1871
Figure 27-35. Single-Ended MOSC Characteristics for Ethernet .............................................. 1872
Figure 27-36. Reset Timing ................................................................................................... 1872
Figure 27-37. 100 Base-TX Transmit Timing ........................................................................... 1873
Figure 27-38. 10Base-TX Normal Link Pulse Timing ............................................................... 1873
Figure 27-39. Auto-Negotiation Fast Link Pulse Timing ........................................................... 1874
Figure 27-40. 100Base-TX Signal Detect Timing ..................................................................... 1874
Figure 27-41. ULPI Interface Timing Diagram ......................................................................... 1876
Figure A-1. Key to Part Numbers ........................................................................................ 1885
Figure A-2. TM4C1294NCPDT 128-Pin TQFP Package Diagram ......................................... 1887

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List of Tables
Table 1. Revision History .................................................................................................. 45
Table 2. Documentation Conventions ................................................................................ 49
Table 1-1. TM4C1294NCPDT Microcontroller Features .......................................................... 52
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 85
Table 2-2. Processor Register Map ....................................................................................... 86
Table 2-3. PSR Register Combinations ................................................................................. 92
Table 2-4. Memory Map ..................................................................................................... 103
Table 2-5. Memory Access Behavior ................................................................................... 107
Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 109
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 109
Table 2-8. Exception Types ................................................................................................ 115
Table 2-9. Interrupts .......................................................................................................... 116
Table 2-10. Exception Return Behavior ................................................................................. 123
Table 2-11. Faults ............................................................................................................... 124
Table 2-12. Fault Status and Fault Address Registers ............................................................ 125
Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 127
Table 3-1. Core Peripheral Register Regions ....................................................................... 134
Table 3-2. Memory Attributes Summary .............................................................................. 138
Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 140
Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 141
Table 3-5. AP Bit Field Encoding ........................................................................................ 141
Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 142
Table 3-7. QNaN and SNaN Handling ................................................................................. 145
Table 3-8. Peripherals Register Map ................................................................................... 146
Table 3-9. Interrupt Priority Levels ...................................................................................... 171
Table 3-10. Example SIZE Field Values ................................................................................ 199
Table 4-1. JTAG_SWD_SWO Signals (128TQFP) ............................................................... 208
Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 210
Table 4-3. JTAG Instruction Register Commands ................................................................. 216
Table 5-1. System Control & Clocks Signals (128TQFP) ...................................................... 220
Table 5-2. Reset Sources ................................................................................................... 221
Table 5-3. Clock Source Options ........................................................................................ 231
Table 5-4. Clock Source State Following POR ..................................................................... 231
Table 5-5. System Clock Frequency ................................................................................... 235
Table 5-6. System Divisor Factors for fvco=480 MHz ............................................................ 237
Table 5-7. Actual PLL Frequency ........................................................................................ 238
Table 5-8. Peripheral Memory Power Control ...................................................................... 243
Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 244
Table 5-10. MOSC Configurations ........................................................................................ 247
Table 5-11. System Control Register Map ............................................................................. 247
Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 277
Table 5-13. MOSC Configurations ........................................................................................ 281
Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 300
Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 303
Table 5-16. Module Power Control ........................................................................................ 451
Table 5-17. Module Power Control ........................................................................................ 453

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Table 5-18. Module Power Control ........................................................................................ 456

Table 5-19. Module Power Control ........................................................................................ 461
Table 5-20. Module Power Control ........................................................................................ 463
Table 5-21. Module Power Control ........................................................................................ 465
Table 5-22. Module Power Control ........................................................................................ 467
Table 5-23. Module Power Control ........................................................................................ 470
Table 5-24. Module Power Control ........................................................................................ 472
Table 5-25. Module Power Control ........................................................................................ 476
Table 5-26. Module Power Control ........................................................................................ 478
Table 5-27. Module Power Control ........................................................................................ 480
Table 5-28. Module Power Control ........................................................................................ 482
Table 5-29. Module Power Control ........................................................................................ 484
Table 5-30. Module Power Control ........................................................................................ 486
Table 5-31. Module Power Control ........................................................................................ 488
Table 5-32. Module Power Control ........................................................................................ 490
Table 5-33. Module Power Control ........................................................................................ 492
Table 5-34. Module Power Control ........................................................................................ 494
Table 6-1. System Exception Register Map ......................................................................... 523
Table 7-1. Hibernate Signals (128TQFP) ............................................................................. 534
Table 7-2. HIB Clock Source Configurations ........................................................................ 535
Table 7-3. Hibernation Module Register Map ....................................................................... 552
Table 8-1. MEMTIM0 Register Configuration versus Frequency ............................................ 605
Table 8-2. Flash Memory Protection Policy Combinations .................................................... 610
Table 8-3. User-Programmable Flash Memory Resident Registers ....................................... 614
Table 8-4. MEMTIM0 Register Configuration versus Frequency ............................................ 617
Table 8-5. Master Memory Access Availability ..................................................................... 621
Table 8-6. Flash Register Map ............................................................................................ 622
Table 9-1. μDMA Channel Assignments .............................................................................. 680
Table 9-2. Request Type Support ....................................................................................... 682
Table 9-3. Control Structure Memory Map ........................................................................... 684
Table 9-4. Channel Control Structure .................................................................................. 684
Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 693
Table 9-6. μDMA Interrupt Assignments .............................................................................. 694
Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 695
Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 696
Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 697
Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 697
Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 699
Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 699
Table 9-13. μDMA Register Map .......................................................................................... 701
Table 10-1. GPIO Pins With Special Considerations .............................................................. 743
Table 10-2. GPIO Pins and Alternate Functions (128TQFP) ................................................... 743
Table 10-3. GPIO Drive Strength Options .............................................................................. 753
Table 10-4. GPIO Pad Configuration Examples ..................................................................... 754
Table 10-5. GPIO Interrupt Configuration Example ................................................................ 755
Table 10-6. GPIO Pins With Special Considerations .............................................................. 756
Table 10-7. GPIO Register Map ........................................................................................... 757

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Table 10-8. GPIO Pins With Special Considerations .............................................................. 770

Table 10-9. GPIO Pins With Special Considerations .............................................................. 776
Table 10-10. GPIO Pins With Special Considerations .............................................................. 778
Table 10-11. GPIO Pins With Special Considerations .............................................................. 781
Table 10-12. GPIO Pins With Special Considerations .............................................................. 787
Table 10-13. GPIO Drive Strength Options .............................................................................. 800
Table 11-1. External Peripheral Interface Signals (128TQFP) ................................................. 817
Table 11-2. EPI Interface Options ......................................................................................... 822
Table 11-3. EPI SDRAM x16 Signal Connections .................................................................. 823
Table 11-4. CSCFGEXT + CSCFG Encodings ...................................................................... 827
Table 11-5. Dual- and Quad- Chip Select Address Mappings ................................................. 828
Table 11-6. Chip Select Configuration Register Assignment ................................................... 829
Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 829
Table 11-8. EPI Host-Bus 8 Signal Connections .................................................................... 831
Table 11-9. EPI Host-Bus 16 Signal Connections .................................................................. 833
Table 11-10. PSRAM Fixed Latency Wait State Configuration .................................................. 838
Table 11-11. Data Phase Wait State Programming .................................................................. 843
Table 11-12. EPI General-Purpose Signal Connections ........................................................... 849
Table 11-13. External Peripheral Interface (EPI) Register Map ................................................. 854
Table 11-14. CSCFGEXT + CSCFG Encodings ...................................................................... 880
Table 11-15. CSCFGEXT + CSCFG Encodings ...................................................................... 886
Table 12-1. Endian Configuration ......................................................................................... 947
Table 12-2. Endian Configuration with Bit Reversal ................................................................ 947
Table 12-3. CCM Register Map ............................................................................................ 949
Table 13-1. Available CCP Pins ............................................................................................ 956
Table 13-2. General-Purpose Timers Signals (128TQFP) ....................................................... 957
Table 13-3. General-Purpose Timer Capabilities .................................................................... 958
Table 13-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 960
Table 13-5. 16-Bit Timer With Prescaler Configurations ......................................................... 961
Table 13-6. Counter Values When the Timer is Enabled in RTC Mode .................................... 962
Table 13-7. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 963
Table 13-8. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 964
Table 13-9. Counter Values When the Timer is Enabled in PWM Mode ................................... 966
Table 13-10. Timeout Actions for GPTM Modes ...................................................................... 969
Table 13-11. Timers Register Map .......................................................................................... 974
Table 14-1. Watchdog Timers Register Map ........................................................................ 1031
Table 15-1. ADC Signals (128TQFP) .................................................................................. 1055
Table 15-2. Samples and FIFO Depth of Sequencers .......................................................... 1056
Table 15-3. Sample and Hold Width in ADC Clocks ............................................................. 1058
Table 15-4. RS and FCONV Values with Varying NSH Values and FADC = 16 MHz ..................... 1059
Table 15-5. RS and FCONV Values with Varying NSH Values and FADC = 32 MHz ..................... 1059
Table 15-6. Differential Sampling Pairs ............................................................................... 1066
Table 15-7. ADC Register Map ........................................................................................... 1073
Table 15-8. Sample and Hold Width in ADC Clocks ............................................................. 1127
Table 15-9. Sample and Hold Width in ADC Clocks ............................................................. 1139
Table 15-10. Sample and Hold Width in ADC Clocks ............................................................. 1147
Table 16-1. UART Signals (128TQFP) ................................................................................ 1163
Table 16-2. Flow Control Mode ........................................................................................... 1169

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Table 16-3. UART Register Map ......................................................................................... 1173

Table 17-1. SSI Signals (128TQFP) .................................................................................... 1228
Table 17-2. QSSI Transaction Encodings ............................................................................ 1231
Table 17-3. SSInFss Functionality ...................................................................................... 1231
Table 17-4. Legacy Mode TI, Freescale SPI Frame Format Features .................................... 1233
Table 17-5. SSI Register Map ............................................................................................. 1243
Table 18-1. I2C Signals (128TQFP) .................................................................................... 1277
Table 18-2. Examples of I2C Master Timer Period Versus Speed Mode ................................. 1284
Table 18-3. Examples of I2C Master Timer Period in High-Speed Mode ................................ 1285
Table 18-4. Inter-Integrated Circuit (I2C) Interface Register Map ........................................... 1300
Table 18-5. Write Field Decoding for I2CMCS[6:0] ............................................................... 1308
Table 19-1. Controller Area Network Signals (128TQFP) ...................................................... 1357
Table 19-2. Message Object Configurations ........................................................................ 1363
Table 19-3. CAN Protocol Ranges ...................................................................................... 1371
Table 19-4. CANBIT Register Values .................................................................................. 1371
Table 19-5. CAN Register Map ........................................................................................... 1375
Table 20-1. Ethernet Signals (128TQFP) ............................................................................. 1409
Table 20-2. Enhanced Transmit Descriptor 0 (TDES0) ......................................................... 1414
Table 20-3. Enhanced Transmit Descriptor 1 (TDES1) ......................................................... 1417
Table 20-4. Enhanced Transmit Descriptor 2 (TDES2) ......................................................... 1418
Table 20-5. Enhanced Transmit Descriptor 3 (TDES3) ......................................................... 1418
Table 20-6. Enhanced Transmit Descriptor 6 (TDES6) ......................................................... 1418
Table 20-7. Enhanced Transmit Descriptor 7 (TDES7) ......................................................... 1418
Table 20-8. Enhanced Receive Descriptor 0 (RDES0) .......................................................... 1419
Table 20-9. RDES0 Checksum Offload bits ......................................................................... 1421
Table 20-10. Enhanced Receive Descriptor 1 (RDES1) .......................................................... 1422
Table 20-11. Enhanced Receive Descriptor 2 (RDES2) .......................................................... 1422
Table 20-12. Enhanced Receive Descriptor 3 (RDES3) .......................................................... 1422
Table 20-13. Enhanced Received Descriptor 4 (RDES4) ........................................................ 1422
Table 20-14. Enhanced Receive Descriptor 6 (RDES6) .......................................................... 1424
Table 20-15. Enhanced Receive Descriptor 7 (RDES7) .......................................................... 1424
Table 20-16. TX MAC Flow Control ...................................................................................... 1437
Table 20-17. RX MAC Flow Control ...................................................................................... 1437
Table 20-18. VLAN Match Status .......................................................................................... 1450
Table 20-19. CRC Replacement Based on Bit 27 and Bit 24 of TDES0 ................................... 1452
Table 20-20. Forced Mode Configurations ............................................................................. 1458
Table 20-21. Advertised Mode Configurations ....................................................................... 1459
Table 20-22. EMACPC to PHY Register Mapping .................................................................. 1465
Table 20-23. Ethernet Register Map ..................................................................................... 1467
Table 20-24. PPSCTRL Bit Field Values ............................................................................... 1549
Table 21-1. USB Signals (128TQFP) .................................................................................. 1646
Table 21-2. List of Registers ............................................................................................... 1647
Table 22-1. Analog Comparators Signals (128TQFP) ........................................................... 1654
Table 22-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1656
Table 22-3. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1657
Table 22-4. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1658

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Table 22-5. Analog Comparators Register Map ................................................................... 1659

Table 23-1. PWM Signals (128TQFP) ................................................................................. 1672
Table 23-2. PWM Register Map .......................................................................................... 1679
Table 24-1. QEI Signals (128TQFP) ................................................................................... 1750
Table 24-2. QEI Register Map ............................................................................................ 1754
Table 26-1. GPIO Pins With Special Considerations ............................................................ 1772
Table 26-2. Signals by Pin Number ..................................................................................... 1773
Table 26-3. Signals by Signal Name ................................................................................... 1785
Table 26-4. Signals by Function, Except for GPIO ............................................................... 1797
Table 26-5. GPIO Pins and Alternate Functions ................................................................... 1808
Table 26-6. Possible Pin Assignments for Alternate Functions .............................................. 1811
Table 26-7. Connections for Unused Signals (128-Pin TQFP) ............................................... 1816
Table 27-1. Absolute Maximum Ratings .............................................................................. 1818
Table 27-2. ESD Absolute Maximum Ratings ...................................................................... 1818
Table 27-3. Temperature Characteristics ............................................................................. 1819
Table 27-4. 128-pin TQFP Power Dissipation ...................................................................... 1819
Table 27-5. Thermal Characteristics ................................................................................... 1819
Table 27-6. Recommended DC Operating Conditions .......................................................... 1820
Table 27-7. Recommended FAST GPIO Pad Operating Conditions ...................................... 1820
Table 27-8. Recommended Slow GPIO Pad Operating Conditions ........................................ 1821
Table 27-9. GPIO Current Restrictions ................................................................................ 1821
Table 27-10. Maximum GPIO Package Side Assignments ..................................................... 1822
Table 27-11. Load Conditions ............................................................................................... 1823
Table 27-12. JTAG Characteristics ....................................................................................... 1824
Table 27-13. Power and Brown-Out Levels ........................................................................... 1826
Table 27-14. Reset Characteristics ....................................................................................... 1831
Table 27-15. LDO Regulator Characteristics ......................................................................... 1834
Table 27-16. Phase Locked Loop (PLL) Characteristics ......................................................... 1835
Table 27-17. System Divisor Factors for fvco=480 MHz ........................................................... 1836
Table 27-18. Actual PLL Frequency ...................................................................................... 1836
Table 27-19. PIOSC Clock Characteristics ............................................................................ 1837
Table 27-20. Low-Frequency Oscillator Characteristics .......................................................... 1837
Table 27-21. Hibernation Internal Low Frequency Oscillator Clock Characteristics ................... 1837
Table 27-22. Hibernation External Oscillator (XOSC) Input Characteristics .............................. 1837
Table 27-23. Main Oscillator Input Characteristics ................................................................. 1838
Table 27-24. Crystal Parameters .......................................................................................... 1840
Table 27-25. System Clock Characteristics with ADC Operation ............................................. 1842
Table 27-26. System Clock Characteristics with USB Operation ............................................. 1842
Table 27-27. Wake from Sleep Characteristics ...................................................................... 1843
Table 27-28. Wake from Deep Sleep Characteristics ............................................................. 1843
Table 27-29. Hibernation Module Battery Characteristics ....................................................... 1845
Table 27-30. Hibernation Module Characteristics ................................................................... 1845
Table 27-31. Hibernation Module Tamper I/O Characteristics ................................................. 1845
Table 27-32. Flash Memory Characteristics ........................................................................... 1847
Table 27-33. EEPROM Characteristics ................................................................................. 1848
Table 27-34. Fast GPIO Module Characteristics .................................................................... 1849
Table 27-35. Slow GPIO Module Characteristics ................................................................... 1850
Table 27-36. Pad Voltage/Current Characteristics for Hibernate WAKE Pin ............................. 1851

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Table 27-37. Non-Power I/O Pad Voltage/Current Characteristics .......................................... 1852

Table 27-38. EPI Interface Load Conditions .......................................................................... 1853
Table 27-39. EPI SDRAM Characteristics ............................................................................. 1853
Table 27-40. EPI SDRAM Interface Characteristics ............................................................... 1853
Table 27-41. EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics ................................. 1855
Table 27-42. EPI General-Purpose Interface Characteristics .................................................. 1857
Table 27-43. EPI PSRAM Interface Characteristics ................................................................ 1858
Table 27-44. ADC Electrical Characteristics for ADC at 1 Msps .............................................. 1861
Table 27-45. ADC Electrical Characteristics for ADC at 2 Msps .............................................. 1863
Table 27-46. SSI Characteristics .......................................................................................... 1867
Table 27-47. Bi- and Quad-SSI Characteristics ...................................................................... 1869
Table 27-48. I2C Characteristics ........................................................................................... 1870
Table 27-49. Ethernet PHY DC Characteristics ...................................................................... 1871
Table 27-50. MOSC 25-MHz Crystal Specification ................................................................. 1871
a
Table 27-51. MOSC Single-Ended 25-MHz Oscillator Specification ....................................... 1871
Table 27-52. Ethernet Controller Enable and Software Reset Timing ...................................... 1872
Table 27-53. 100Base-TX Transmit Timing (tR/F and Jitter) ..................................................... 1872
Table 27-54. 10Base-T Normal Link Pulse Timing ................................................................. 1873
Table 27-55. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................. 1874
Table 27-56. 100Base-TX Signal Detect Timing ..................................................................... 1874
Table 27-57. ULPI Interface Timing ....................................................................................... 1875
Table 27-58. Analog Comparator Characteristics ................................................................... 1877
Table 27-59. Analog Comparator Voltage Reference Characteristics ...................................... 1877
Table 27-60. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1877
Table 27-61. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1878
Table 27-62. PWM Timing Characteristics ............................................................................. 1879
Table 27-63. Current Consumption ....................................................................................... 1880
Table 27-64. Peripheral Current Consumption ....................................................................... 1884

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List of Registers
The Cortex-M4F Processor ........................................................................................................... 80
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 88
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 88
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 88
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 88
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 88
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 88
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 88
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 88
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 88
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 88
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 88
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 88
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 88
Register 14: Stack Pointer (SP) ........................................................................................................... 89
Register 15: Link Register (LR) ............................................................................................................ 90
Register 16: Program Counter (PC) ..................................................................................................... 91
Register 17: Program Status Register (PSR) ........................................................................................ 92
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 96
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 97
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 98
Register 21: Control Register (CONTROL) ........................................................................................... 99
Register 22: Floating-Point Status Control (FPSC) .............................................................................. 101
Cortex-M4 Peripherals ................................................................................................................. 134
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 150
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 152
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 153
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 154
Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 154
Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 154
Register 7: Interrupt 96-113 Set Enable (EN3), offset 0x10C .............................................................. 154
Register 8: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 155
Register 9: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 155
Register 10: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 155
Register 11: Interrupt 96-113 Clear Enable (DIS3), offset 0x18C .......................................................... 155
Register 12: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 156
Register 13: Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 156
Register 14: Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 156
Register 15: Interrupt 96-113 Set Pending (PEND3), offset 0x20C ....................................................... 156
Register 16: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 157
Register 17: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 157
Register 18: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 157
Register 19: Interrupt 96-113 Clear Pending (UNPEND3), offset 0x28C ............................................... 157
Register 20: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 158
Register 21: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 158

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Register 22: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 158
Register 23: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 158
Register 24: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 159
Register 25: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 159
Register 26: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 159
Register 27: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 159
Register 28: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 159
Register 29: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 159
Register 30: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 159
Register 31: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 159
Register 32: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 159
Register 33: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 159
Register 34: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 159
Register 35: Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 159
Register 36: Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 159
Register 37: Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 159
Register 38: Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 159
Register 39: Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 159
Register 40: Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 161
Register 41: Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 161
Register 42: Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 161
Register 43: Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 161
Register 44: Interrupt 80-83 Priority (PRI20), offset 0x450 ................................................................... 161
Register 45: Interrupt 84-87 Priority (PRI21), offset 0x454 ................................................................... 161
Register 46: Interrupt 88-91 Priority (PRI22), offset 0x458 ................................................................... 161
Register 47: Interrupt 92-95 Priority (PRI23), offset 0x45C .................................................................. 161
Register 48: Interrupt 96-99 Priority (PRI24), offset 0x460 ................................................................... 161
Register 49: Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 161
Register 50: Interrupt 104-107 Priority (PRI26), offset 0x468 ............................................................... 161
Register 51: Interrupt 108-111 Priority (PRI27), offset 0x46C ............................................................... 161
Register 52: Interrupt 112-113 Priority (PRI28), offset 0x470 ................................................................ 161
Register 53: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 163
Register 54: Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 164
Register 55: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 166
Register 56: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 167
Register 57: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 170
Register 58: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 171
Register 59: System Control (SYSCTRL), offset 0xD10 ....................................................................... 173
Register 60: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 175
Register 61: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 177
Register 62: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 178
Register 63: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 179
Register 64: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 180
Register 65: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 184
Register 66: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 190
Register 67: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 191
Register 68: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 192
Register 69: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 193

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Register 70: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 194

Register 71: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 196
Register 72: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 197
Register 73: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 197
Register 74: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 197
Register 75: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 197
Register 76: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 199
Register 77: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 199
Register 78: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 199
Register 79: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 199
Register 80: Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 202
Register 81: Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 203
Register 82: Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 205
Register 83: Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 206
System Control ............................................................................................................................ 220
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 255
Register 2: Device Identification 1 (DID1), offset 0x004 ..................................................................... 257
Register 3: Power-Temp Brown Out Control (PTBOCTL), offset 0x038 ............................................... 259
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 261
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 263
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 265
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 267
Register 8: Power-Temperature Cause (PWRTC), offset 0x060 ......................................................... 270
Register 9: NMI Cause Register (NMIC), offset 0x064 ....................................................................... 271
Register 10: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 273
Register 11: Run and Sleep Mode Configuration Register (RSCLKCFG), offset 0x0B0 .......................... 275
Register 12: Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0), offset
0x0C0 ........................................................................................................................... 277
Register 13: Alternate Clock Configuration (ALTCLKCFG), offset 0x138 ............................................... 280
Register 14: Deep Sleep Clock Configuration Register (DSCLKCFG), offset 0x144 ............................... 281
Register 15: Divisor and Source Clock Configuration (DIVSCLK), offset 0x148 ..................................... 284
Register 16: System Properties (SYSPROP), offset 0x14C .................................................................. 286
Register 17: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 289
Register 18: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 291
Register 19: PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 292
Register 20: PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 293
Register 21: PLL Status (PLLSTAT), offset 0x168 ............................................................................... 294
Register 22: Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 295
Register 23: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 297
Register 24: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 299
Register 25: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 300
Register 26: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 302
Register 27: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC ........................................... 303
Register 28: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 ...................................... 305
Register 29: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC .................................... 306
Register 30: Reset Behavior Control Register (RESBEHAVCTL), offset 0x1D8 ..................................... 309
Register 31: Hardware System Service Request (HSSR), offset 0x1F4 ................................................ 311
Register 32: USB Power Domain Status (USBPDS), offset 0x280 ........................................................ 312

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Register 33: USB Memory Power Control (USBMPC), offset 0x284 ..................................................... 313
Register 34: Ethernet MAC Power Domain Status (EMACPDS), offset 0x288 ....................................... 314
Register 35: Ethernet MAC Memory Power Control (EMACMPC), offset 0x28C .................................... 315
Register 36: CAN 0 Power Domain Status (CAN0PDS), offset 0x298 ................................................... 316
Register 37: CAN 0 Memory Power Control (CAN0MPC), offset 0x29C ................................................ 317
Register 38: CAN 1 Power Domain Status (CAN1PDS), offset 0x2A0 .................................................. 318
Register 39: CAN 1 Memory Power Control (CAN1MPC), offset 0x2A4 ................................................ 319
Register 40: Watchdog Timer Peripheral Present (PPWD), offset 0x300 ............................................... 320
Register 41: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304 ................. 321
Register 42: General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308 ........................ 323
Register 43: Micro Direct Memory Access Peripheral Present (PPDMA), offset 0x30C .......................... 326
Register 44: EPI Peripheral Present (PPEPI), offset 0x310 .................................................................. 327
Register 45: Hibernation Peripheral Present (PPHIB), offset 0x314 ...................................................... 328
Register 46: Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset
0x318 ........................................................................................................................... 329
Register 47: Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C ............................ 331
Register 48: Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320 ...................................... 333
Register 49: Universal Serial Bus Peripheral Present (PPUSB), offset 0x328 ........................................ 335
Register 50: Ethernet PHY Peripheral Present (PPEPHY), offset 0x330 ............................................... 336
Register 51: Controller Area Network Peripheral Present (PPCAN), offset 0x334 .................................. 337
Register 52: Analog-to-Digital Converter Peripheral Present (PPADC), offset 0x338 ............................. 338
Register 53: Analog Comparator Peripheral Present (PPACMP), offset 0x33C ...................................... 339
Register 54: Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340 ................................... 340
Register 55: Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344 ........................... 341
Register 56: Low Pin Count Interface Peripheral Present (PPLPC), offset 0x348 .................................. 342
Register 57: Platform Environment Control Interface Peripheral Present (PPPECI), offset 0x350 ........... 343
Register 58: Fan Control Peripheral Present (PPFAN), offset 0x354 ..................................................... 344
Register 59: EEPROM Peripheral Present (PPEEPROM), offset 0x358 ................................................ 345
Register 60: 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), offset 0x35C ..... 346
Register 61: Remote Temperature Sensor Peripheral Present (PPRTS), offset 0x370 ........................... 347
Register 62: CRC Module Peripheral Present (PPCCM), offset 0x374 .................................................. 348
Register 63: LCD Peripheral Present (PPLCD), offset 0x390 ............................................................... 349
Register 64: 1-Wire Peripheral Present (PPOWIRE), offset 0x398 ....................................................... 350
Register 65: Ethernet MAC Peripheral Present (PPEMAC), offset 0x39C ............................................. 351
Register 66: Power Regulator Bus Peripheral Present (PPPRB), offset 0x3A0 ...................................... 352
Register 67: Human Interface Master Peripheral Present (PPHIM), offset 0x3A4 .................................. 353
Register 68: Watchdog Timer Software Reset (SRWD), offset 0x500 ................................................... 354
Register 69: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504 ...................... 355
Register 70: General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508 ............................ 357
Register 71: Micro Direct Memory Access Software Reset (SRDMA), offset 0x50C ............................... 360
Register 72: EPI Software Reset (SREPI), offset 0x510 ...................................................................... 361
Register 73: Hibernation Software Reset (SRHIB), offset 0x514 ........................................................... 362
Register 74: Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 .... 363
Register 75: Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C ................................ 365
Register 76: Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520 ........................................... 367
Register 77: Universal Serial Bus Software Reset (SRUSB), offset 0x528 ............................................ 369
Register 78: Ethernet PHY Software Reset (SREPHY), offset 0x530 .................................................... 370
Register 79: Controller Area Network Software Reset (SRCAN), offset 0x534 ....................................... 371

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Register 80: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 .................................. 372
Register 81: Analog Comparator Software Reset (SRACMP), offset 0x53C .......................................... 373
Register 82: Pulse Width Modulator Software Reset (SRPWM), offset 0x540 ....................................... 374
Register 83: Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 ............................... 375
Register 84: EEPROM Software Reset (SREEPROM), offset 0x558 .................................................... 376
Register 85: CRC Module Software Reset (SRCCM), offset 0x574 ...................................................... 377
Register 86: Ethernet MAC Software Reset (SREMAC), offset 0x59C .................................................. 378
Register 87: Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 ...................... 379
Register 88: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset
0x604 ........................................................................................................................... 380
Register 89: General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset
0x608 ........................................................................................................................... 382
Register 90: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset
0x60C ........................................................................................................................... 385
Register 91: EPI Run Mode Clock Gating Control (RCGCEPI), offset 0x610 ......................................... 386
Register 92: Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614 ............................. 387
Register 93: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART),
offset 0x618 .................................................................................................................. 388
Register 94: Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset
0x61C ........................................................................................................................... 390
Register 95: Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 ............. 391
Register 96: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), offset 0x628 ............... 393
Register 97: Ethernet PHY Run Mode Clock Gating Control (RCGCEPHY), offset 0x630 ...................... 394
Register 98: Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 ......... 395
Register 99: Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 .... 396
Register 100: Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C ............. 397
Register 101: Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), offset 0x640 .......... 398
Register 102: Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset
0x644 ........................................................................................................................... 399
Register 103: EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 ....................... 400
Register 104: CRC Module Run Mode Clock Gating Control (RCGCCCM), offset 0x674 ......................... 401
Register 105: Ethernet MAC Run Mode Clock Gating Control (RCGCEMAC), offset 0x69C ..................... 402
Register 106: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 .................... 403
Register 107: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset
0x704 ........................................................................................................................... 404
Register 108: General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset
0x708 ........................................................................................................................... 406
Register 109: Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset
0x70C ........................................................................................................................... 409
Register 110: EPI Sleep Mode Clock Gating Control (SCGCEPI), offset 0x710 ....................................... 410
Register 111: Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714 ........................... 411
Register 112: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control
(SCGCUART), offset 0x718 ............................................................................................ 412
Register 113: Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset
0x71C ........................................................................................................................... 414
Register 114: Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 ........... 415
Register 115: Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), offset 0x728 ............. 417
Register 116: Ethernet PHY Sleep Mode Clock Gating Control (SCGCEPHY), offset 0x730 .................... 418
Register 117: Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 ....... 419

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Register 118: Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset
0x738 ........................................................................................................................... 420
Register 119: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C .......... 421
Register 120: Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740 ........ 422
Register 121: Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset
0x744 ........................................................................................................................... 423
Register 122: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 ..................... 424
Register 123: CRC Module Sleep Mode Clock Gating Control (SCGCCCM), offset 0x774 ....................... 425
Register 124: Ethernet MAC Sleep Mode Clock Gating Control (SCGCEMAC), offset 0x79C .................. 426
Register 125: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 .......... 427
Register 126: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER),
offset 0x804 .................................................................................................................. 428
Register 127: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset
0x808 ........................................................................................................................... 430
Register 128: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset
0x80C ........................................................................................................................... 433
Register 129: EPI Deep-Sleep Mode Clock Gating Control (DCGCEPI), offset 0x810 ............................. 434
Register 130: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 .................. 435
Register 131: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
(DCGCUART), offset 0x818 ............................................................................................ 436
Register 132: Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset
0x81C ........................................................................................................................... 438
Register 133: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset
0x820 ........................................................................................................................... 439
Register 134: Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset
0x828 ........................................................................................................................... 441
Register 135: Ethernet PHY Deep-Sleep Mode Clock Gating Control (DCGCEPHY), offset 0x830 ........... 442
Register 136: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset
0x834 ........................................................................................................................... 443
Register 137: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset
0x838 ........................................................................................................................... 444
Register 138: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset
0x83C ........................................................................................................................... 445
Register 139: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset
0x840 ........................................................................................................................... 446
Register 140: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset
0x844 ........................................................................................................................... 447
Register 141: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 ........... 448
Register 142: CRC Module Deep-Sleep Mode Clock Gating Control (DCGCCCM), offset 0x874 .............. 449
Register 143: Ethernet MAC Deep-Sleep Mode Clock Gating Control (DCGCEMAC), offset 0x89C ......... 450
Register 144: Watchdog Timer Power Control (PCWD), offset 0x900 ..................................................... 451
Register 145: 16/32-Bit General-Purpose Timer Power Control (PCTIMER), offset 0x904 ....................... 453
Register 146: General-Purpose Input/Output Power Control (PCGPIO), offset 0x908 .............................. 456
Register 147: Micro Direct Memory Access Power Control (PCDMA), offset 0x90C ................................ 461
Register 148: External Peripheral Interface Power Control (PCEPI), offset 0x910 ................................... 463
Register 149: Hibernation Power Control (PCHIB), offset 0x914 ............................................................ 465
Register 150: Universal Asynchronous Receiver/Transmitter Power Control (PCUART), offset 0x918 ...... 467
Register 151: Synchronous Serial Interface Power Control (PCSSI), offset 0x91C .................................. 470
Register 152: Inter-Integrated Circuit Power Control (PCI2C), offset 0x920 ............................................ 472

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Register 153: Universal Serial Bus Power Control (PCUSB), offset 0x928 .............................................. 476
Register 154: Ethernet PHY Power Control (PCEPHY), offset 0x930 ..................................................... 478
Register 155: Controller Area Network Power Control (PCCAN), offset 0x934 ........................................ 480
Register 156: Analog-to-Digital Converter Power Control (PCADC), offset 0x938 .................................... 482
Register 157: Analog Comparator Power Control (PCACMP), offset 0x93C ............................................ 484
Register 158: Pulse Width Modulator Power Control (PCPWM), offset 0x940 ......................................... 486
Register 159: Quadrature Encoder Interface Power Control (PCQEI), offset 0x944 ................................. 488
Register 160: EEPROM Power Control (PCEEPROM), offset 0x958 ...................................................... 490
Register 161: CRC Module Power Control (PCCCM), offset 0x974 ........................................................ 492
Register 162: Ethernet MAC Power Control (PCEMAC), offset 0x99C .................................................... 494
Register 163: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00 ................................................ 496
Register 164: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04 ................... 497
Register 165: General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08 ......................... 499
Register 166: Micro Direct Memory Access Peripheral Ready (PRDMA), offset 0xA0C ........................... 502
Register 167: EPI Peripheral Ready (PREPI), offset 0xA10 ................................................................... 503
Register 168: Hibernation Peripheral Ready (PRHIB), offset 0xA14 ....................................................... 504
Register 169: Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset
0xA18 ........................................................................................................................... 505
Register 170: Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C ............................. 507
Register 171: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20 ....................................... 509
Register 172: Universal Serial Bus Peripheral Ready (PRUSB), offset 0xA28 ......................................... 512
Register 173: Ethernet PHY Peripheral Ready (PREPHY), offset 0xA30 ................................................ 513
Register 174: Controller Area Network Peripheral Ready (PRCAN), offset 0xA34 ................................... 514
Register 175: Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38 ............................... 515
Register 176: Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C ....................................... 516
Register 177: Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40 .................................... 517
Register 178: Quadrature Encoder Interface Peripheral Ready (PRQEI), offset 0xA44 ............................ 518
Register 179: EEPROM Peripheral Ready (PREEPROM), offset 0xA58 ................................................. 519
Register 180: CRC Module Peripheral Ready (PRCCM), offset 0xA74 ................................................... 520
Register 181: Ethernet MAC Peripheral Ready (PREMAC), offset 0xA9C ............................................... 521
Register 182: Unique ID 0 (UNIQUEID0), offset 0xF20 .......................................................................... 522
Register 183: Unique ID 1 (UNIQUEID1), offset 0xF24 .......................................................................... 522
Register 184: Unique ID 2 (UNIQUEID2), offset 0xF28 .......................................................................... 522
Register 185: Unique ID 3 (UNIQUEID3), offset 0xF2C ......................................................................... 522
Processor Support and Exception Module ............................................................................... 523
Register 1: System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000 ................................ 524
Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004 ........................................... 526
Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset 0x008 ........................... 528
Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C ........................................... 530
Hibernation Module ..................................................................................................................... 531
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 554
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 555
Register 3: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 556
Register 4: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 557
Register 5: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 562
Register 6: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 564
Register 7: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 566
Register 8: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 568

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Register 9: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 570

Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028 ............................................... 571
Register 11: Hibernation IO Configuration (HIBIO), offset 0x02C .......................................................... 572
Register 12: Hibernation Data (HIBDATA), offset 0x030-0x06F ............................................................ 574
Register 13: Hibernation Calendar Control (HIBCALCTL), offset 0x300 ................................................ 575
Register 14: Hibernation Calendar 0 (HIBCAL0), offset 0x310 ............................................................. 576
Register 15: Hibernation Calendar 1 (HIBCAL1), offset 0x314 ............................................................. 578
Register 16: Hibernation Calendar Load 0 (HIBCALLD0), offset 0x320 ................................................. 580
Register 17: Hibernation Calendar Load (HIBCALLD1), offset 0x324 ................................................... 582
Register 18: Hibernation Calendar Match 0 (HIBCALM0), offset 0x330 ................................................ 583
Register 19: Hibernation Calendar Match 1 (HIBCALM1), offset 0x334 ................................................ 585
Register 20: Hibernation Lock (HIBLOCK), offset 0x360 ...................................................................... 586
Register 21: HIB Tamper Control (HIBTPCTL), offset 0x400 ................................................................ 587
Register 22: HIB Tamper Status (HIBTPSTAT), offset 0x404 ................................................................ 589
Register 23: HIB Tamper I/O Control (HIBTPIO), offset 0x410 ............................................................. 591
Register 24: HIB Tamper Log 0 (HIBTPLOG0), offset 0x4E0 ................................................................ 595
Register 25: HIB Tamper Log 2 (HIBTPLOG2), offset 0x4E8 ................................................................ 595
Register 26: HIB Tamper Log 4 (HIBTPLOG4), offset 0x4F0 ................................................................ 595
Register 27: HIB Tamper Log 6 (HIBTPLOG6), offset 0x4F8 ................................................................ 595
Register 28: HIB Tamper Log 1 (HIBTPLOG1), offset 0x4E4 ................................................................ 596
Register 29: HIB Tamper Log 3 (HIBTPLOG3), offset 0x4EC ............................................................... 596
Register 30: HIB Tamper Log 5 (HIBTPLOG5), offset 0x4F4 ................................................................ 596
Register 31: HIB Tamper Log 7 (HIBTPLOG7), offset 0x4FC ............................................................... 596
Register 32: Hibernation Peripheral Properties (HIBPP) , offset 0xFC0 ................................................. 598
Register 33: Hibernation Clock Control (HIBCC), offset 0xFC8 ............................................................ 599
Internal Memory ........................................................................................................................... 600
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 625
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 626
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 627
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 630
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 633
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 635
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 638
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 639
Register 9: Flash Program/Erase Key (FLPEKEY), offset 0x03C ........................................................ 640
Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 641
Register 11: Flash Peripheral Properties (FLASHPP), offset 0xFC0 ..................................................... 642
Register 12: SRAM Size (SSIZE), offset 0xFC4 .................................................................................. 644
Register 13: Flash Configuration Register (FLASHCONF), offset 0xFC8 .............................................. 645
Register 14: ROM Third-Party Software (ROMSWMAP), offset 0xFCC ................................................. 647
Register 15: Flash DMA Address Size (FLASHDMASZ), offset 0xFD0 ................................................. 649
Register 16: Flash DMA Starting Address (FLASHDMAST), offset 0xFD4 ............................................ 650
Register 17: EEPROM Size Information (EESIZE), offset 0x000 .......................................................... 651
Register 18: EEPROM Current Block (EEBLOCK), offset 0x004 .......................................................... 652
Register 19: EEPROM Current Offset (EEOFFSET), offset 0x008 ........................................................ 653
Register 20: EEPROM Read-Write (EERDWR), offset 0x010 .............................................................. 654
Register 21: EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 .................................. 655
Register 22: EEPROM Done Status (EEDONE), offset 0x018 .............................................................. 656

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Register 23: EEPROM Support Control and Status (EESUPP), offset 0x01C ........................................ 658
Register 24: EEPROM Unlock (EEUNLOCK), offset 0x020 .................................................................. 659
Register 25: EEPROM Protection (EEPROT), offset 0x030 ................................................................. 660
Register 26: EEPROM Password (EEPASS0), offset 0x034 ................................................................. 662
Register 27: EEPROM Password (EEPASS1), offset 0x038 ................................................................. 662
Register 28: EEPROM Password (EEPASS2), offset 0x03C ................................................................ 662
Register 29: EEPROM Interrupt (EEINT), offset 0x040 ........................................................................ 663
Register 30: EEPROM Block Hide 0 (EEHIDE0), offset 0x050 ............................................................. 664
Register 31: EEPROM Block Hide 1 (EEHIDE1), offset 0x054 ............................................................. 665
Register 32: EEPROM Block Hide 2 (EEHIDE2), offset 0x058 ............................................................. 665
Register 33: EEPROM Debug Mass Erase (EEDBGME), offset 0x080 ................................................. 666
Register 34: EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0 ........................................... 667
Register 35: Reset Vector Pointer (RVP), offset 0x0D4 ........................................................................ 668
Register 36: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x200 .................................... 669
Register 37: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 669
Register 38: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 669
Register 39: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 669
Register 40: Flash Memory Protection Read Enable 4 (FMPRE4), offset 0x210 .................................... 669
Register 41: Flash Memory Protection Read Enable 5 (FMPRE5), offset 0x214 .................................... 669
Register 42: Flash Memory Protection Read Enable 6 (FMPRE6), offset 0x218 .................................... 669
Register 43: Flash Memory Protection Read Enable 7 (FMPRE7), offset 0x21C ................................... 669
Register 44: Flash Memory Protection Read Enable 8 (FMPRE8), offset 0x220 .................................... 669
Register 45: Flash Memory Protection Read Enable 9 (FMPRE9), offset 0x224 .................................... 669
Register 46: Flash Memory Protection Read Enable 10 (FMPRE10), offset 0x228 ................................ 669
Register 47: Flash Memory Protection Read Enable 11 (FMPRE11), offset 0x22C ................................ 669
Register 48: Flash Memory Protection Read Enable 12 (FMPRE12), offset 0x230 ................................ 669
Register 49: Flash Memory Protection Read Enable 13 (FMPRE13), offset 0x234 ................................ 669
Register 50: Flash Memory Protection Read Enable 14 (FMPRE14), offset 0x238 ................................ 669
Register 51: Flash Memory Protection Read Enable 15 (FMPRE15), offset 0x23C ................................ 669
Register 52: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x400 ............................... 671
Register 53: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 671
Register 54: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 671
Register 55: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 671
Register 56: Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 ............................... 671
Register 57: Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 ............................... 671
Register 58: Flash Memory Protection Program Enable 6 (FMPPE6), offset 0x418 ............................... 671
Register 59: Flash Memory Protection Program Enable 7 (FMPPE7), offset 0x41C ............................... 671
Register 60: Flash Memory Protection Program Enable 8 (FMPPE8), offset 0x420 ............................... 671
Register 61: Flash Memory Protection Program Enable 9 (FMPPE9), offset 0x424 ............................... 671
Register 62: Flash Memory Protection Program Enable 10 (FMPPE10), offset 0x428 ............................ 671
Register 63: Flash Memory Protection Program Enable 11 (FMPPE11), offset 0x42C ............................ 671
Register 64: Flash Memory Protection Program Enable 12 (FMPPE12), offset 0x430 ............................ 671
Register 65: Flash Memory Protection Program Enable 13 (FMPPE13), offset 0x434 ............................ 671
Register 66: Flash Memory Protection Program Enable 14 (FMPPE14), offset 0x438 ............................ 671
Register 67: Flash Memory Protection Program Enable 15 (FMPPE15), offset 0x43C ........................... 671
Register 68: Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 674
Register 69: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 677
Register 70: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 677

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Register 71: User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 677

Register 72: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 677
Micro Direct Memory Access (μDMA) ........................................................................................ 678
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 703
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 704
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 705
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 710
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 712
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 713
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 714
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 715
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 716
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 717
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 718
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 719
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 720
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 721
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 722
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 723
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 724
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 725
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 726
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 727
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 728
Register 22: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 ............................................... 729
Register 23: DMA Channel Map Select 1 (DMACHMAP1), offset 0x514 ............................................... 730
Register 24: DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 ............................................... 731
Register 25: DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C .............................................. 732
Register 26: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 733
Register 27: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 734
Register 28: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 735
Register 29: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 736
Register 30: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 737
Register 31: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 738
Register 32: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 739
Register 33: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 740
Register 34: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 741
General-Purpose Input/Outputs (GPIOs) ................................................................................... 742
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 759
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 760
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 761
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 762
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 763
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 764
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 765
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 767
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 769
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 770

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Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 772
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 773
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 774
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 775
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 776
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 778
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 780
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 781
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 783
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 784
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 786
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 787
Register 23: GPIO ADC Control (GPIOADCCTL), offset 0x530 ............................................................ 789
Register 24: GPIO DMA Control (GPIODMACTL), offset 0x534 ........................................................... 790
Register 25: GPIO Select Interrupt (GPIOSI), offset 0x538 .................................................................. 791
Register 26: GPIO 12-mA Drive Select (GPIODR12R), offset 0x53C .................................................... 792
Register 27: GPIO Wake Pin Enable (GPIOWAKEPEN), offset 0x540 .................................................. 793
Register 28: GPIO Wake Level (GPIOWAKELVL), offset 0x544 ........................................................... 795
Register 29: GPIO Wake Status (GPIOWAKESTAT), offset 0x548 ....................................................... 797
Register 30: GPIO Peripheral Property (GPIOPP), offset 0xFC0 .......................................................... 799
Register 31: GPIO Peripheral Configuration (GPIOPC), offset 0xFC4 ................................................... 800
Register 32: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 803
Register 33: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 804
Register 34: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 805
Register 35: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 806
Register 36: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 807
Register 37: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 808
Register 38: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 809
Register 39: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 810
Register 40: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 811
Register 41: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 812
Register 42: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 813
Register 43: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 814
External Peripheral Interface (EPI) ............................................................................................. 815
Register 1: EPI Configuration (EPICFG), offset 0x000 ....................................................................... 857
Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004 ................................................................. 859
Register 3: EPI Main Baud Rate (EPIBAUD2), offset 0x008 ............................................................... 861
Register 4: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 .............................................. 863
Register 5: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ............................................... 865
Register 6: EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ........................................... 870
Register 7: EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ........................................ 876
Register 8: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 .......................................... 879
Register 9: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 ....................................... 885
Register 10: EPI Address Map (EPIADDRMAP), offset 0x01C ............................................................. 892
Register 11: EPI Read Size 0 (EPIRSIZE0), offset 0x020 .................................................................... 895
Register 12: EPI Read Size 1 (EPIRSIZE1), offset 0x030 .................................................................... 895
Register 13: EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................ 896
Register 14: EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................ 896

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Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 ............................................. 897
Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 ............................................. 897
Register 17: EPI Status (EPISTAT), offset 0x060 ................................................................................ 899
Register 18: EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ...................................................... 901
Register 19: EPI Read FIFO (EPIREADFIFO0), offset 0x070 ............................................................... 902
Register 20: EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 .................................................... 902
Register 21: EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 .................................................... 902
Register 22: EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ................................................... 902
Register 23: EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 .................................................... 902
Register 24: EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 .................................................... 902
Register 25: EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 .................................................... 902
Register 26: EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ................................................... 902
Register 27: EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................ 903
Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ...................................................... 905
Register 29: EPI DMA Transmit Count (EPIDMATXCNT), offset 0x208 ................................................. 906
Register 30: EPI Interrupt Mask (EPIIM), offset 0x210 ......................................................................... 907
Register 31: EPI Raw Interrupt Status (EPIRIS), offset 0x214 .............................................................. 909
Register 32: EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................ 911
Register 33: EPI Error and Interrupt Status and Clear (EPIEISC), offset 0x21C .................................... 913
Register 34: EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), offset 0x308 .......................................... 915
Register 35: EPI Host-Bus 16 Configuration 3 (EPIHB16CFG3), offset 0x308 ....................................... 918
Register 36: EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4), offset 0x30C .......................................... 922
Register 37: EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4), offset 0x30C ...................................... 925
Register 38: EPI Host-Bus 8 Timing Extension (EPIHB8TIME), offset 0x310 ......................................... 929
Register 39: EPI Host-Bus 16 Timing Extension (EPIHB16TIME), offset 0x310 ..................................... 931
Register 40: EPI Host-Bus 8 Timing Extension (EPIHB8TIME2), offset 0x314 ....................................... 933
Register 41: EPI Host-Bus 16 Timing Extension (EPIHB16TIME2), offset 0x314 ................................... 935
Register 42: EPI Host-Bus 8 Timing Extension (EPIHB8TIME3), offset 0x318 ....................................... 937
Register 43: EPI Host-Bus 16 Timing Extension (EPIHB16TIME3), offset 0x318 ................................... 939
Register 44: EPI Host-Bus 8 Timing Extension (EPIHB8TIME4), offset 0x31C ...................................... 941
Register 45: EPI Host-Bus 16 Timing Extension (EPIHB16TIME4), offset 0x31C .................................. 943
Register 46: EPI Host-Bus PSRAM (EPIHBPSRAM), offset 0x360 ....................................................... 945
Cyclical Redundancy Check (CRC) ............................................................................................ 946
Register 1: CRC Control (CRCCTRL), offset 0x400 ........................................................................... 950
Register 2: CRC SEED/Context (CRCSEED), offset 0x410 ................................................................ 952
Register 3: CRC Data Input (CRCDIN), offset 0x414 ......................................................................... 953
Register 4: CRC Post Processing Result (CRCRSLTPP), offset 0x418 ............................................... 954
General-Purpose Timers ............................................................................................................. 955
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 976
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 977
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 982
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 986
Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010 .............................................................. 990
Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 993
Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 996
Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 999
Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024 ............................................................ 1002
Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 .............................................. 1004

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Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C .............................................. 1005
Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 ................................................ 1006
Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................ 1007
Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ..................................................... 1008
Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ..................................................... 1009
Register 16: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ......................................... 1010
Register 17: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ......................................... 1011
Register 18: GPTM Timer A (GPTMTAR), offset 0x048 ..................................................................... 1012
Register 19: GPTM Timer B (GPTMTBR), offset 0x04C ..................................................................... 1013
Register 20: GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................. 1014
Register 21: GPTM Timer B Value (GPTMTBV), offset 0x054 ............................................................ 1015
Register 22: GPTM RTC Predivide (GPTMRTCPD), offset 0x058 ...................................................... 1016
Register 23: GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C ...................................... 1017
Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 ...................................... 1018
Register 25: GPTM DMA Event (GPTMDMAEV), offset 0x06C .......................................................... 1019
Register 26: GPTM ADC Event (GPTMADCEV), offset 0x070 ........................................................... 1022
Register 27: GPTM Peripheral Properties (GPTMPP), offset 0xFC0 ................................................... 1025
Register 28: GPTM Clock Configuration (GPTMCC), offset 0xFC8 ..................................................... 1027
Watchdog Timers ....................................................................................................................... 1028
Register 1: Watchdog Load (WDTLOAD), offset 0x000 .................................................................... 1032
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................. 1033
Register 3: Watchdog Control (WDTCTL), offset 0x008 ................................................................... 1034
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C ......................................................... 1036
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ................................................ 1037
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ........................................... 1038
Register 7: Watchdog Test (WDTTEST), offset 0x418 ...................................................................... 1039
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 .................................................................... 1040
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ............................... 1041
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ............................... 1042
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ............................... 1043
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .............................. 1044
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ............................... 1045
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ............................... 1046
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ............................... 1047
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ............................... 1048
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................. 1049
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................. 1050
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................. 1051
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ................................ 1052
Analog-to-Digital Converter (ADC) ........................................................................................... 1053
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ........................................... 1077
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ......................................................... 1079
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 .................................................................... 1082
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C ................................................ 1085
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 .......................................................... 1089
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ............................................... 1091
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ......................................................... 1096
Register 8: ADC Trigger Source Select (ADCTSSEL), offset 0x01C ................................................. 1097

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Register 9: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ........................................... 1099
Register 10: ADC Sample Phase Control (ADCSPC), offset 0x024 .................................................... 1101
Register 11: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ............................... 1103
Register 12: ADC Sample Averaging Control (ADCSAC), offset 0x030 ............................................... 1105
Register 13: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ............... 1106
Register 14: ADC Control (ADCCTL), offset 0x038 ............................................................................ 1108
Register 15: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............. 1109
Register 16: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ...................................... 1111
Register 17: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 .............................. 1118
Register 18: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 .............................. 1118
Register 19: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 .............................. 1118
Register 20: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................. 1118
Register 21: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ........................... 1119
Register 22: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ........................... 1119
Register 23: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C .......................... 1119
Register 24: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC .......................... 1119
Register 25: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 .................................... 1121
Register 26: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 ............. 1123
Register 27: ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0), offset
0x058 .......................................................................................................................... 1125
Register 28: ADC Sample Sequence 0 Sample and Hold Time (ADCSSTSH0), offset 0x05C .............. 1127
Register 29: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............. 1129
Register 30: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............. 1129
Register 31: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ...................................... 1130
Register 32: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ...................................... 1130
Register 33: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 .................................... 1134
Register 34: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ................................... 1134
Register 35: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 ............. 1135
Register 36: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 ............ 1135
Register 37: ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), offset
0x078 .......................................................................................................................... 1137
Register 38: ADC Sample Sequence Extended Input Multiplexer Select 2 (ADCSSEMUX2), offset 0x098
.................................................................................................................................... 1137
Register 39: ADC Sample Sequence 1 Sample and Hold Time (ADCSSTSH1), offset 0x07C .............. 1139
Register 40: ADC Sample Sequence 2 Sample and Hold Time (ADCSSTSH2), offset 0x09C .............. 1139
Register 41: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............. 1141
Register 42: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ...................................... 1142
Register 43: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 .................................... 1144
Register 44: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 ............ 1145
Register 45: ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3), offset
0x0B8 ......................................................................................................................... 1146
Register 46: ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3), offset 0x0BC .............. 1147
Register 47: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ................... 1148
Register 48: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ..................................... 1153
Register 49: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ..................................... 1153
Register 50: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ..................................... 1153
Register 51: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C .................................... 1153
Register 52: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ..................................... 1153
Register 53: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ..................................... 1153

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Register 54: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ..................................... 1153
Register 55: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C .................................... 1153
Register 56: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ..................................... 1156
Register 57: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ..................................... 1156
Register 58: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ..................................... 1156
Register 59: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C .................................... 1156
Register 60: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ..................................... 1156
Register 61: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ..................................... 1156
Register 62: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ..................................... 1156
Register 63: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C .................................... 1156
Register 64: ADC Peripheral Properties (ADCPP), offset 0xFC0 ........................................................ 1157
Register 65: ADC Peripheral Configuration (ADCPC), offset 0xFC4 ................................................... 1159
Register 66: ADC Clock Configuration (ADCCC), offset 0xFC8 .......................................................... 1160
Universal Asynchronous Receivers/Transmitters (UARTs) ................................................... 1161
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................. 1175
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ......................... 1177
Register 3: UART Flag (UARTFR), offset 0x018 .............................................................................. 1180
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................ 1183
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 .......................................... 1184
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ..................................... 1185
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................. 1186
Register 8: UART Control (UARTCTL), offset 0x030 ........................................................................ 1188
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 .......................................... 1192
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................ 1194
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C .................................................... 1198
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ............................................... 1202
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 .............................................................. 1206
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 ........................................................ 1208
Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................. 1209
Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................. 1210
Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0 .................................................... 1211
Register 18: UART Clock Configuration (UARTCC), offset 0xFC8 ...................................................... 1213
Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ................................... 1214
Register 20: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ................................... 1215
Register 21: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ................................... 1216
Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ................................... 1217
Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 .................................... 1218
Register 24: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 .................................... 1219
Register 25: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 .................................... 1220
Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ................................... 1221
Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ...................................... 1222
Register 28: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ...................................... 1223
Register 29: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ...................................... 1224
Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ...................................... 1225
Quad Synchronous Serial Interface (QSSI) ............................................................................. 1226
Register 1: QSSI Control 0 (SSICR0), offset 0x000 ......................................................................... 1245
Register 2: QSSI Control 1 (SSICR1), offset 0x004 ......................................................................... 1247
Register 3: QSSI Data (SSIDR), offset 0x008 ................................................................................. 1249

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Register 4: QSSI Status (SSISR), offset 0x00C ............................................................................... 1250

Register 5: QSSI Clock Prescale (SSICPSR), offset 0x010 .............................................................. 1252
Register 6: QSSI Interrupt Mask (SSIIM), offset 0x014 .................................................................... 1253
Register 7: QSSI Raw Interrupt Status (SSIRIS), offset 0x018 ......................................................... 1255
Register 8: QSSI Masked Interrupt Status (SSIMIS), offset 0x01C ................................................... 1257
Register 9: QSSI Interrupt Clear (SSIICR), offset 0x020 .................................................................. 1259
Register 10: QSSI DMA Control (SSIDMACTL), offset 0x024 ............................................................. 1260
Register 11: QSSI Peripheral Properties (SSIPP), offset 0xFC0 ......................................................... 1261
Register 12: QSSI Clock Configuration (SSICC), offset 0xFC8 ........................................................... 1262
Register 13: QSSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ........................................ 1263
Register 14: QSSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ........................................ 1264
Register 15: QSSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ........................................ 1265
Register 16: QSSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ........................................ 1266
Register 17: QSSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ........................................ 1267
Register 18: QSSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ........................................ 1268
Register 19: QSSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ........................................ 1269
Register 20: QSSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ........................................ 1270
Register 21: QSSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ........................................... 1271
Register 22: QSSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ........................................... 1272
Register 23: QSSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ........................................... 1273
Register 24: QSSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .......................................... 1274
Inter-Integrated Circuit (I2C) Interface ...................................................................................... 1275
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ......................................................... 1302
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ......................................................... 1303
Register 3: I2C Master Data (I2CMDR), offset 0x008 ....................................................................... 1312
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ......................................................... 1313
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ....................................................... 1315
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ............................................... 1318
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 .......................................... 1321
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ....................................................... 1324
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 .......................................................... 1326
Register 10: I2C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 ............................. 1327
Register 11: I2C Master Bus Monitor (I2CMBMON), offset 0x02C ....................................................... 1328
Register 12: I2C Master Burst Length (I2CMBLEN), offset 0x030 ....................................................... 1329
Register 13: I2C Master Burst Count (I2CMBCNT), offset 0x034 ........................................................ 1330
Register 14: I2C Slave Own Address (I2CSOAR), offset 0x800 .......................................................... 1331
Register 15: I2C Slave Control/Status (I2CSCSR), offset 0x804 ......................................................... 1332
Register 16: I2C Slave Data (I2CSDR), offset 0x808 ......................................................................... 1335
Register 17: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ......................................................... 1336
Register 18: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................. 1338
Register 19: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 ............................................ 1341
Register 20: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 .......................................................... 1344
Register 21: I2C Slave Own Address 2 (I2CSOAR2), offset 0x81C ..................................................... 1346
Register 22: I2C Slave ACK Control (I2CSACKCTL), offset 0x820 ...................................................... 1347
Register 23: I2C FIFO Data (I2CFIFODATA), offset 0xF00 ................................................................. 1348
Register 24: I2C FIFO Control (I2CFIFOCTL), offset 0xF04 ............................................................... 1350
Register 25: I2C FIFO Status (I2CFIFOSTATUS), offset 0xF08 .......................................................... 1352

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Register 26: I2C Peripheral Properties (I2CPP), offset 0xFC0 ............................................................ 1354
Register 27: I2C Peripheral Configuration (I2CPC), offset 0xFC4 ....................................................... 1355
Controller Area Network (CAN) Module ................................................................................... 1356
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................ 1378
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................. 1380
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................. 1383
Register 4: CAN Bit Timing (CANBIT), offset 0x00C ........................................................................ 1384
Register 5: CAN Interrupt (CANINT), offset 0x010 ........................................................................... 1385
Register 6: CAN Test (CANTST), offset 0x014 ................................................................................ 1386
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ..................................... 1388
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 .............................................. 1389
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 .............................................. 1389
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 ................................................ 1390
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 ................................................ 1390
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 .............................................................. 1393
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 .............................................................. 1393
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C .............................................................. 1394
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C .............................................................. 1394
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ....................................................... 1396
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ....................................................... 1396
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ....................................................... 1397
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ....................................................... 1397
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 ................................................ 1399
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 ................................................ 1399
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ............................................................... 1402
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................ 1402
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................ 1402
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................ 1402
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ............................................................... 1402
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ............................................................... 1402
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ............................................................... 1402
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ............................................................... 1402
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 .............................................. 1403
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 .............................................. 1403
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ............................................................... 1404
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ............................................................... 1404
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ................................... 1405
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ................................... 1405
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ..................................................... 1406
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ..................................................... 1406
Ethernet Controller .................................................................................................................... 1407
Register 1: Ethernet MAC Configuration (EMACCFG), offset 0x000 ................................................. 1471
Register 2: Ethernet MAC Frame Filter (EMACFRAMEFLTR), offset 0x004 ...................................... 1478
Register 3: Ethernet MAC Hash Table High (EMACHASHTBLH), offset 0x008 .................................. 1482
Register 4: Ethernet MAC Hash Table Low (EMACHASHTBLL), offset 0x00C ................................... 1483
Register 5: Ethernet MAC MII Address (EMACMIIADDR), offset 0x010 ............................................ 1484
Register 6: Ethernet MAC MII Data Register (EMACMIIDATA), offset 0x014 ..................................... 1486
Register 7: Ethernet MAC Flow Control (EMACFLOWCTL), offset 0x018 ......................................... 1487

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Register 8: Ethernet MAC VLAN Tag (EMACVLANTG), offset 0x01C ............................................... 1489
Register 9: Ethernet MAC Status (EMACSTATUS), offset 0x024 ...................................................... 1491
Register 10: Ethernet MAC Remote Wake-Up Frame Filter (EMACRWUFF), offset 0x028 ................... 1494
Register 11: Ethernet MAC PMT Control and Status Register (EMACPMTCTLSTAT), offset 0x02C ..... 1495
Register 12: Ethernet MAC Raw Interrupt Status (EMACRIS), offset 0x038 ........................................ 1497
Register 13: Ethernet MAC Interrupt Mask (EMACIM), offset 0x03C ................................................... 1499
Register 14: Ethernet MAC Address 0 High (EMACADDR0H), offset 0x040 ........................................ 1500
Register 15: Ethernet MAC Address 0 Low Register (EMACADDR0L), offset 0x044 ............................ 1501
Register 16: Ethernet MAC Address 1 High (EMACADDR1H), offset 0x048 ........................................ 1502
Register 17: Ethernet MAC Address 1 Low (EMACADDR1L), offset 0x04C ........................................ 1504
Register 18: Ethernet MAC Address 2 High (EMACADDR2H), offset 0x050 ........................................ 1505
Register 19: Ethernet MAC Address 2 Low (EMACADDR2L), offset 0x054 ......................................... 1507
Register 20: Ethernet MAC Address 3 High (EMACADDR3H), offset 0x058 ........................................ 1508
Register 21: Ethernet MAC Address 3 Low (EMACADDR3L), offset 0x05C ........................................ 1510
Register 22: Ethernet MAC Watchdog Timeout (EMACWDOGTO), offset 0x0DC ................................ 1511
Register 23: Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100 ........................................ 1512
Register 24: Ethernet MAC MMC Receive Raw Interrupt Status (EMACMMCRXRIS), offset 0x104 ...... 1515
Register 25: Ethernet MAC MMC Transmit Raw Interrupt Status (EMACMMCTXRIS), offset 0x108 ..... 1517
Register 26: Ethernet MAC MMC Receive Interrupt Mask (EMACMMCRXIM), offset 0x10C ................ 1519
Register 27: Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM), offset 0x110 ................. 1521
Register 28: Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB), offset
0x118 .......................................................................................................................... 1523
Register 29: Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision
(EMACTXCNTSCOL), offset 0x14C .............................................................................. 1524
Register 30: Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions
(EMACTXCNTMCOL), offset 0x150 .............................................................................. 1525
Register 31: Ethernet MAC Transmit Octet Count Good (EMACTXOCTCNTG), offset 0x164 ............... 1526
Register 32: Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB), offset
0x180 .......................................................................................................................... 1527
Register 33: Ethernet MAC Receive Frame Count for CRC Error Frames (EMACRXCNTCRCERR), offset
0x194 .......................................................................................................................... 1528
Register 34: Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR),
offset 0x198 ................................................................................................................. 1529
Register 35: Ethernet MAC Receive Frame Count for Good Unicast Frames (EMACRXCNTGUNI), offset
0x1C4 ......................................................................................................................... 1530
Register 36: Ethernet MAC VLAN Tag Inclusion or Replacement (EMACVLNINCREP), offset 0x584 .... 1531
Register 37: Ethernet MAC VLAN Hash Table (EMACVLANHASH), offset 0x588 ................................ 1533
Register 38: Ethernet MAC Timestamp Control (EMACTIMSTCTRL), offset 0x700 ............................. 1534
Register 39: Ethernet MAC Sub-Second Increment (EMACSUBSECINC), offset 0x704 ....................... 1538
Register 40: Ethernet MAC System Time - Seconds (EMACTIMSEC), offset 0x708 ............................ 1539
Register 41: Ethernet MAC System Time - Nanoseconds (EMACTIMNANO), offset 0x70C .................. 1540
Register 42: Ethernet MAC System Time - Seconds Update (EMACTIMSECU), offset 0x710 .............. 1541
Register 43: Ethernet MAC System Time - Nanoseconds Update (EMACTIMNANOU), offset 0x714 .... 1542
Register 44: Ethernet MAC Timestamp Addend (EMACTIMADD), offset 0x718 ................................... 1543
Register 45: Ethernet MAC Target Time Seconds (EMACTARGSEC), offset 0x71C ............................ 1544
Register 46: Ethernet MAC Target Time Nanoseconds (EMACTARGNANO), offset 0x720 ................... 1545
Register 47: Ethernet MAC System Time-Higher Word Seconds (EMACHWORDSEC), offset 0x724 .... 1546
Register 48: Ethernet MAC Timestamp Status (EMACTIMSTAT), offset 0x728 .................................... 1547
Register 49: Ethernet MAC PPS Control (EMACPPSCTRL), offset 0x72C .......................................... 1548

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Register 50: Ethernet MAC PPS0 Interval (EMACPPS0INTVL), offset 0x760 ...................................... 1551
Register 51: Ethernet MAC PPS0 Width (EMACPPS0WIDTH), offset 0x764 ....................................... 1552
Register 52: Ethernet MAC DMA Bus Mode (EMACDMABUSMOD), offset 0xC00 .............................. 1553
Register 53: Ethernet MAC Transmit Poll Demand (EMACTXPOLLD), offset 0xC04 ............................ 1557
Register 54: Ethernet MAC Receive Poll Demand (EMACRXPOLLD), offset 0xC08 ............................ 1558
Register 55: Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR), offset 0xC0C ......... 1559
Register 56: Ethernet MAC Transmit Descriptor List Address (EMACTXDLADDR), offset 0xC10 ......... 1560
Register 57: Ethernet MAC DMA Interrupt Status (EMACDMARIS), offset 0xC14 ................................ 1561
Register 58: Ethernet MAC DMA Operation Mode (EMACDMAOPMODE), offset 0xC18 ..................... 1567
Register 59: Ethernet MAC DMA Interrupt Mask Register (EMACDMAIM), offset 0xC1C ..................... 1572
Register 60: Ethernet MAC Missed Frame and Buffer Overflow Counter (EMACMFBOC), offset
0xC20 ......................................................................................................................... 1575
Register 61: Ethernet MAC Receive Interrupt Watchdog Timer (EMACRXINTWDT), offset 0xC24 ....... 1576
Register 62: Ethernet MAC Current Host Transmit Descriptor (EMACHOSTXDESC), offset 0xC48 ...... 1577
Register 63: Ethernet MAC Current Host Receive Descriptor (EMACHOSRXDESC), offset 0xC4C ...... 1578
Register 64: Ethernet MAC Current Host Transmit Buffer Address (EMACHOSTXBA), offset 0xC50 .... 1579
Register 65: Ethernet MAC Current Host Receive Buffer Address (EMACHOSRXBA), offset 0xC54 ..... 1580
Register 66: Ethernet MAC Peripheral Property Register (EMACPP), offset 0xFC0 ............................. 1581
Register 67: Ethernet MAC Peripheral Configuration Register (EMACPC), offset 0xFC4 ..................... 1582
Register 68: Ethernet MAC Clock Configuration Register (EMACCC), offset 0xFC8 ............................ 1586
Register 69: Ethernet PHY Raw Interrupt Status (EPHYRIS), offset 0xFD0 ......................................... 1587
Register 70: Ethernet PHY Interrupt Mask (EPHYIM), offset 0xFD4 ................................................... 1588
Register 71: Ethernet PHY Masked Interrupt Status and Clear (EPHYMISC), offset 0xFD8 ................. 1589
Register 72: Ethernet PHY Basic Mode Control - MR0 (EPHYBMCR), address 0x000 ......................... 1590
Register 73: Ethernet PHY Basic Mode Status - MR1 (EPHYBMSR), address 0x001 .......................... 1592
Register 74: Ethernet PHY Identifier Register 1 - MR2 (EPHYID1), address 0x002 ............................. 1595
Register 75: Ethernet PHY Identifier Register 2 - MR3 (EPHYID2), address 0x003 ............................. 1596
Register 76: Ethernet PHY Auto-Negotiation Advertisement - MR4 (EPHYANA), address 0x004 .......... 1597
Register 77: Ethernet PHY Auto-Negotiation Link Partner Ability - MR5 (EPHYANLPA), address
0x005 .......................................................................................................................... 1599
Register 78: Ethernet PHY Auto-Negotiation Expansion - MR6 (EPHYANER), address 0x006 ............. 1601
Register 79: Ethernet PHY Auto-Negotiation Next Page TX - MR7 (EPHYANNPTR), address 0x007 .... 1602
Register 80: Ethernet PHY Auto-Negotiation Link Partner Ability Next Page - MR8 (EPHYANLNPTR),
address 0x008 ............................................................................................................. 1604
Register 81: Ethernet PHY Configuration 1 - MR9 (EPHYCFG1), address 0x009 ................................ 1606
Register 82: Ethernet PHY Configuration 2 - MR10 (EPHYCFG2), address 0x00A .............................. 1609
Register 83: Ethernet PHY Configuration 3 - MR11 (EPHYCFG3), address 0x00B .............................. 1611
Register 84: Ethernet PHY Register Control - MR13 (EPHYREGCTL), address 0x00D ....................... 1613
Register 85: Ethernet PHY Address or Data - MR14 (EPHYADDAR), address 0x00E .......................... 1615
Register 86: Ethernet PHY Status - MR16 (EPHYSTS), address 0x010 .............................................. 1616
Register 87: Ethernet PHY Specific Control- MR17 (EPHYSCR), address 0x011 ................................ 1619
Register 88: Ethernet PHY MII Interrupt Status 1 - MR18 (EPHYMISR1), address 0x012 .................... 1622
Register 89: Ethernet PHY MII Interrupt Status 2 - MR19 (EPHYMISR2), address 0x013 .................... 1625
Register 90: Ethernet PHY False Carrier Sense Counter - MR20 (EPHYFCSCR), address 0x014 ........ 1628
Register 91: Ethernet PHY Receive Error Count - MR21 (EPHYRXERCNT), address 0x015 ............... 1629
Register 92: Ethernet PHY BIST Control - MR22 (EPHYBISTCR), address 0x016 .............................. 1630
Register 93: Ethernet PHY LED Control - MR24 (EPHYLEDCR), address 0x018 ................................ 1633
Register 94: Ethernet PHY Control - MR25 (EPHYCTL), address 0x019 ............................................. 1634
Register 95: Ethernet PHY 10Base-T Status/Control - MR26 (EPHY10BTSC), address 0x01A ............ 1636

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Register 96: Ethernet PHY BIST Control and Status 1 - MR27 (EPHYBICSR1), address 0x01B ........... 1638
Register 97: Ethernet PHY BIST Control and Status 2 - MR28 (EPHYBICSR2), address 0x01C .......... 1639
Register 98: Ethernet PHY Cable Diagnostic Control - MR30 (EPHYCDCR), address 0x01E ............... 1640
Register 99: Ethernet PHY Reset Control - MR31 (EPHYRCR), address 0x01F .................................. 1641
Register 100: Ethernet PHY LED Configuration - MR37 (EPHYLEDCFG), address 0x025 ..................... 1642
Analog Comparators ................................................................................................................. 1653
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1660
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1661
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1662
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... 1663
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... 1664
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... 1664
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 ................................................... 1664
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... 1665
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1665
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 ................................................... 1665
Register 11: Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0 ................................ 1667
Pulse Width Modulator (PWM) .................................................................................................. 1669
Register 1: PWM Master Control (PWMCTL), offset 0x000 .............................................................. 1683
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ......................................................... 1685
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 ........................................................ 1686
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ..................................................... 1688
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 .............................................................. 1690
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ......................................................... 1692
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ...................................................... 1694
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C .............................................. 1697
Register 9: PWM Status (PWMSTATUS), offset 0x020 .................................................................... 1700
Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ........................................... 1702
Register 11: PWM Enable Update (PWMENUPD), offset 0x028 ......................................................... 1704
Register 12: PWM0 Control (PWM0CTL), offset 0x040 ...................................................................... 1708
Register 13: PWM1 Control (PWM1CTL), offset 0x080 ...................................................................... 1708
Register 14: PWM2 Control (PWM2CTL), offset 0x0C0 ..................................................................... 1708
Register 15: PWM3 Control (PWM3CTL), offset 0x100 ...................................................................... 1708
Register 16: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 ................................... 1713
Register 17: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 ................................... 1713
Register 18: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 ................................... 1713
Register 19: PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104 ................................... 1713
Register 20: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 ................................................... 1716
Register 21: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 ................................................... 1716
Register 22: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 .................................................. 1716
Register 23: PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108 ................................................... 1716
Register 24: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C .......................................... 1718
Register 25: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C .......................................... 1718
Register 26: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC .......................................... 1718
Register 27: PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C .......................................... 1718
Register 28: PWM0 Load (PWM0LOAD), offset 0x050 ...................................................................... 1720
Register 29: PWM1 Load (PWM1LOAD), offset 0x090 ...................................................................... 1720
Register 30: PWM2 Load (PWM2LOAD), offset 0x0D0 ...................................................................... 1720

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Register 31: PWM3 Load (PWM3LOAD), offset 0x110 ...................................................................... 1720

Register 32: PWM0 Counter (PWM0COUNT), offset 0x054 ............................................................... 1721
Register 33: PWM1 Counter (PWM1COUNT), offset 0x094 ............................................................... 1721
Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4 .............................................................. 1721
Register 35: PWM3 Counter (PWM3COUNT), offset 0x114 ............................................................... 1721
Register 36: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................ 1722
Register 37: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................ 1722
Register 38: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................ 1722
Register 39: PWM3 Compare A (PWM3CMPA), offset 0x118 ............................................................. 1722
Register 40: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................ 1723
Register 41: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................ 1723
Register 42: PWM2 Compare B (PWM2CMPB), offset 0x0DC ........................................................... 1723
Register 43: PWM3 Compare B (PWM3CMPB), offset 0x11C ............................................................ 1723
Register 44: PWM0 Generator A Control (PWM0GENA), offset 0x060 ............................................... 1724
Register 45: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ............................................... 1724
Register 46: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ............................................... 1724
Register 47: PWM3 Generator A Control (PWM3GENA), offset 0x120 ............................................... 1724
Register 48: PWM0 Generator B Control (PWM0GENB), offset 0x064 ............................................... 1727
Register 49: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ............................................... 1727
Register 50: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ............................................... 1727
Register 51: PWM3 Generator B Control (PWM3GENB), offset 0x124 ............................................... 1727
Register 52: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ............................................... 1730
Register 53: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ............................................... 1730
Register 54: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ............................................... 1730
Register 55: PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128 ............................................... 1730
Register 56: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................ 1731
Register 57: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................ 1731
Register 58: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................ 1731
Register 59: PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C ............................ 1731
Register 60: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................ 1732
Register 61: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................ 1732
Register 62: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................ 1732
Register 63: PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130 ............................ 1732
Register 64: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 .................................................. 1733
Register 65: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 .................................................. 1733
Register 66: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 .................................................. 1733
Register 67: PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134 .................................................. 1733
Register 68: PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078 .................................................. 1735
Register 69: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 .................................................. 1735
Register 70: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 .................................................. 1735
Register 71: PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138 .................................................. 1735
Register 72: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C ................................... 1738
Register 73: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC ................................... 1738
Register 74: PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC ................................... 1738
Register 75: PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C ................................... 1738
Register 76: PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 .......................................... 1739
Register 77: PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880 .......................................... 1739
Register 78: PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900 .......................................... 1739

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Register 79: PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980 .......................................... 1739
Register 80: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 ................................................... 1740
Register 81: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 ................................................... 1740
Register 82: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 ................................................... 1740
Register 83: PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984 ................................................... 1740
Register 84: PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808 ................................................... 1742
Register 85: PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888 ................................................... 1742
Register 86: PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908 ................................................... 1742
Register 87: PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988 ................................................... 1742
Register 88: PWM Peripheral Properties (PWMPP), offset 0xFC0 ...................................................... 1745
Register 89: PWM Clock Configuration (PWMCC), offset 0xFC8 ........................................................ 1747
Quadrature Encoder Interface (QEI) ........................................................................................ 1748
Register 1: QEI Control (QEICTL), offset 0x000 .............................................................................. 1755
Register 2: QEI Status (QEISTAT), offset 0x004 .............................................................................. 1758
Register 3: QEI Position (QEIPOS), offset 0x008 ............................................................................ 1759
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ..................................................... 1760
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ..................................................................... 1761
Register 6: QEI Timer (QEITIME), offset 0x014 ............................................................................... 1762
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ........................................................... 1763
Register 8: QEI Velocity (QEISPEED), offset 0x01C ........................................................................ 1764
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................. 1765
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ........................................................... 1767
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ................................................... 1769

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Revision History
The revision history table notes changes made between the indicated revisions of the
TM4C1294NCPDT data sheet.

Table 1. Revision History

Date Revision Description
June 2014 15863.2743 ■ In ADC chapter, clarified section "Sample and Hold Window Control".

■ In SSI chapter:
– Noted that during idle periods the transmit data line SSInTx is tristated.
– Added clarification to uDMA section about wait states.

■ In Ethernet chapter:
– Corrected functional description of DMA descriptors.
– Added description of Receive Checksum Offload Engine.

■ In Electrical Characteristics chapter:

– In "Power and Brown-Out Levels" table, updated VPOR with characterized values.
– In "PIOSC Clock Characteristics" table, clarified FPIOSC values.
– In "Low-Frequency Internal Oscillator Characteristics" table, updated FLFIOSC with characterized
values.
– In "Main Oscillator Input Characteristics" table, removed Pending Characterization footnote.
– In "ADC Electrical Characteristics for ADC at 1 Msps" table, updated Max value for VINCM.
– In "ADC Electrical Characteristics for ADC at 2 Msps" table, updated values for VINCM, RS,
fCONV, TS, TLT, and the Dynamic Characteristics.
– In "Current Consumption" table, updated values that were pending.

■ In Package Information appendix:

– Moved Orderable Part Numbers table to addendum.
– Deleted Packaging Materials section and put into separate packaging document.

■ Additional minor data sheet clarifications and corrections.

April 2014 15802.2729 ■ In the System Control chapter:

– Clarified Hibernation Module reset section.
– Added clarifications in Deep-Sleep Mode section.
– Added reset for DID1 register.
– Corrected description for RESC register, and changed bit 6 HIB Reset to reserved.
– Added note to DSSYSDIV bit in DSCLKCFG register that values 0x0 and 0x1 should not be
used.
– Added clarification to FLASHPM bit in DSLPPWRCFG register when using the LFIOSC as the
Deep-Sleep clock source.
– Added four registers, UNIQUEIDn, which combined provide a 128-bit unique identifier for each
device.

■ In the Hibernation chapter, added clarification to Hibernation Control (HIBCTL) register about
External Wake and Interrupt Pin Enable bit.

■ In the Internal Memory chapter, added information on soft reset handling to the EEPROM section.

■ In the GPIO chapter:

– Replaced table GPIO Pins With Non-Zero Reset Values with table GPIO Pins With Special
Considerations.
– Added note about preventing false interrupts.

■ In the Timer chapter, clarified behavior of TnMIE and TnCINTD bits in the GPTM Timer n Mode
(GPTMTnMR) registers.

■ In the ADC chapter:

– Corrected ADC maximum sample rate to two million samples/second.

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Table 1. Revision History (continued)

Date Revision Description
– Corrected figure ADC Input Equivalency.
– Removed Dither Enable bit and corrected reset for ADCCTL register.

■ In the UART chapter, clarified that for a receive timeout, the RTIM bit in the UARTIM register must
be set to see the RTMIS and RTRIS status in the UARTMIS and UARTRIS registers.

■ In the SSI chapter:

– Clarified Receive FIFO operation.
– Clarified DMA operation.
– Removed End of Transmission (EOT) bit 4 from QSSI Control 1 (SSICR1) register.

■ In the Ethernet chapter, clarified Initialization and Configuration.

■ In the USB chapter, added important note that when configured as a bus-powered Device, the USB
can operate in SUSPEND mode but produces a higher power draw than required to be compliant.

■ In the Electrical Characteristics chapter:

– In Reset Characteristics table, updated internal reset time parameter values.
– In PIOSC Clock Characteristics table, updated parameter values.
– In Hibernation External Oscillator (XOSC) Input Characteristics table, removed parameter C0
Crystal shunt capacitance.
– Updated Crystal Parameters table.
– In Hibernation Module Tamper I/O Characteristics table, updated TMPRn pull-up resistor
parameter values.
– In Flash Memory Characteristics table, updated TPROG64 nom value.
– In EEPROM Characteristics table, added values for Read access time and removed EEPROM
recovery Power-On Reset delay parameter.
– In EPI PSRAM Interface Characteristics table, updated Min value for EPI_CLK period.
– In ADC Electrical Characteristics at 1 Msps table, updated values for VADCIN parameter.
– Corrected ADC Input Equivalency diagram.
– In Bi- and Quad-SSI Characteristics table, added clarifying footnotes.
– Added PWM Timing Characteristics table.
– Updated Current Consumption table.
– In Peripheral Current Consumption table, updated IDDEMAC Nom value.

■ In Package Information appendix:

– Updated Orderable Devices section to reflect silicon revision 3 part numbers.
– Added Device Nomenclature section.
– Deleted packaging materials section and put into separate document.

■ Additional minor data sheet clarifications and corrections.

December 2013 15638.2711 ■ Changed NDA (Non-Disclosure Agreement) footer to indicate NDA only applies to USB content.

■ In System Control chapter:

– Added sections "Optional Clock Output Signal (DIVSCLK)" and "Hardware System Service
Request".
– Removed some registers and bits:
• LDORDRIS bit from Raw Interrupt Status (RIS) register, LDORDIM bit from Interrupt Mask
Control (IMC) register, and LDORDMIS bit from Masked Interrupt Status and Clear (MISC)
register
• Deep Sleep Mode Memory Timing Register 0 for Main Flash and EEPROM
(DSMEMTIM0) register
• LDO Power Calibration (LDOPCAL) register
• LDO Sleep Power Control (LDOSPCTL) register
• LMINERR bit from Sleep/Deep-Sleep Power Mode Status (SDPMST) register
– Added LDOSME, TSPDE, PIOSCPDE, SRAMSM, SRAMLPM, FLASHLPM, and LDOSEQ bits in
SYSPROP register.

■ In Internal Memory chapter:

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Table 1. Revision History (continued)

Date Revision Description
– Added subsections to "Flash Memory" section about Execute-Only Protection, Read-Only
Protection and Permanently Disabling Debug.
– Removed INVPL bit from EEPROM Done Status (EEDONE) register.
– Updated table "MEMTIM0 Register Configuration vs. Frequency" with lower wait states, and
improved performance values.
– Added EEPROM initialization code to "EEPROM Initialization and Configuration" section.

■ In the ADC chapter:

– Added section "Sample and Hold Window Control" and clarified section "Sample Phase Control".
– Clarified description of ADC Sample Phase Control (ADCSPC) register.

■ Updated Electrical Characteristics chapter based on characterization information received.

■ Additional minor data sheet clarifications and corrections.

October 2013 15440.2698 Initial release of NDA data sheet.

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About This Document

About This Document

This data sheet provides reference information for the TM4C1294NCPDT microcontroller, describing
the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M4F
core.

Audience
This manual is intended for system software developers, hardware designers, and application
developers.

About This Manual

This document is organized into sections that correspond to each major feature.

Related Documents
The following related documents are available on the Tiva™ C Series web site at
http://www.ti.com/tiva-c:

■ Tiva™ C Series TM4C129x Silicon Errata (literature number SPMZ850)

■ TivaWare™ Boot Loader for C Series User's Guide (literature number SPMU301)

■ TivaWare™ Graphics Library for C Series User's Guide (literature number SPMU300)

■ TivaWare™ for C Series Release Notes (literature number SPMU299)

■ TivaWare™ Peripheral Driver Library for C Series User's Guide (literature number SPMU298)

■ TivaWare™ USB Library for C Series User's Guide (literature number SPMU297)

■ Tiva™ C Series TM4C129x ROM User’s Guide (literature number SPMU363)

The following related documents may also be useful:

■ ARM® Cortex™-M4 Errata (literature number SPMZ637)

■ ARM® Cortex™-M4 Technical Reference Manual

■ ARM® Debug Interface V5 Architecture Specification

■ ARM® Embedded Trace Macrocell Architecture Specification

■ Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A)

■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture

This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.

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Documentation Conventions
This document uses the conventions shown in Table 2 on page 49.

Table 2. Documentation Conventions

Notation Meaning
General Register Notation
REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit A single bit in a register.
bit field Two or more consecutive and related bits.
offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 103.
Register N Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field This value in the register bit diagram indicates whether software running on the controller can
Types change the value of the bit field.
RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO Software can read this field. Always write the chip reset value.
RW Software can read or write this field.
RWC Software can read or write this field. Writing to it with any value clears the register.
RW1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation provides
the interrupt status and the write of the read value clears only the interrupts being reported at the
time the register was read.
RW1S Software can read or write a 1 to this field. A write of a 0 to a RW1S bit does not affect the bit value
in the register.
W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0 Bit cleared to 0 on chip reset.
1 Bit set to 1 on chip reset.
- Nondeterministic.
Pin/Signal Notation
[] Pin alternate function; a pin defaults to the signal without the brackets.
pin Refers to the physical connection on the package.
signal Refers to the electrical signal encoding of a pin.

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Table 2. Documentation Conventions (continued)

Notation Meaning
assert a signal Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal Change the value of the signal from the logically True state to the logically False state.
SIGNAL Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.

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1 Architectural Overview
®
Texas Instrument's Tiva™ C Series microcontrollers provide designers a high-performance ARM
Cortex™-M-based architecture with a broad set of integration capabilities and a strong ecosystem
of software and development tools. Targeting performance and flexibility, the Tiva™ C Series
architecture offers a 120 MHz Cortex-M with FPU, a variety of integrated memories and multiple
programmable GPIO. Tiva™ C Series devices offer consumers compelling cost-effective solutions
by integrating application-specific peripherals and providing a comprehensive library of software
tools which minimize board costs and design-cycle time. Offering quicker time-to-market and cost
savings, the Tiva™ C Series microcontrollers are the leading choice in high-performance 32-bit
applications.
This chapter contains an overview of the Tiva™ C Series microcontrollers as well as details on the
TM4C1294NCPDT microcontroller:

■ “Tiva™ C Series Overview” on page 51

■ “TM4C1294NCPDT Microcontroller Overview” on page 52
■ “TM4C1294NCPDT Microcontroller Features” on page 55
■ “TM4C1294NCPDT Microcontroller Hardware Details” on page 78
■ “Kits” on page 79
■ “Support Information” on page 79

1.1 Tiva™ C Series Overview

The Tiva™ C Series ARM Cortex-M4 microcontrollers provide top performance and advanced
integration. The product family is positioned for cost-effective applications requiring significant control
processing and connectivity capabilities such as:

■ Industrial communication equipment

■ Network appliances, gateways & adapters
■ Residential & commercial site monitoring & control
■ Remote connectivity & monitoring
■ Security/access systems
■ HMI control panels
■ Factory automation control
■ Test and measurement equipment
■ Fire & security systems
■ Motion control & power inversion
■ Medical instrumentation
■ Gaming equipment
■ Electronic point-of-sale (POS) displays
■ Smart Energy/Smart Grid solutions
■ Intelligent lighting control
■ Vehicle tracking

Tiva™ C Series microcontrollers integrate a large variety of rich communication features to enable
a new class of highly connected designs with the ability to allow critical, real-time control between
performance and power. The microcontrollers feature integrated communication peripherals along
with other high-performance analog and digital functions to offer a strong foundation for many
different target uses, spanning from human machine interface to networked system management
controllers.

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In addition, Tiva™ C Series microcontrollers offer the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure, and a large user community. Additionally,
these microcontrollers use ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory
requirements and, thereby, cost. Finally, the TM4C1294NCPDT microcontroller is code-compatible
to all members of the extensive Tiva™ C Series, providing flexibility to fit precise needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network.

1.2 TM4C1294NCPDT Microcontroller Overview

The TM4C1294NCPDT microcontroller combines complex integration and high performance with
the features shown in Table 1-1.

Table 1-1. TM4C1294NCPDT Microcontroller Features

Feature Description
Performance
Core ARM Cortex-M4F processor core
Performance 120-MHz operation; 150 DMIPS performance
Flash 1024 KB Flash memory
System SRAM 256 KB single-cycle System SRAM
EEPROM 6KB of EEPROM
Internal ROM Internal ROM loaded with TivaWare™ for C Series software
External Peripheral Interface (EPI) 8-/16-/32- bit dedicated interface for peripherals and memory
Security
Cyclical Redundancy Check (CRC) Hardware 16-/32-bit Hash function that supports four CRC forms
Tamper Support for four tamper inputs and configurable tamper event response
Communication Interfaces
Universal Asynchronous Receivers/Transmitter Eight UARTs
(UART)
Quad Synchronous Serial Interface (QSSI) Four SSI modules with Bi-, Quad- and advanced SSI support
Inter-Integrated Circuit (I2C) Ten I2C modules with four transmission speeds including high-speed
mode
Controller Area Network (CAN) Two CAN 2.0 A/B controllers
Ethernet MAC 10/100 Ethernet MAC
Ethernet PHY PHY with IEEE 1588 PTP hardware support
Universal Serial Bus (USB) USB 2.0 OTG/Host/Device with ULPI interface option and Link Power
Management (LPM) support
System Integration
Micro Direct Memory Access (µDMA) ARM® PrimeCell® 32-channel configurable μDMA controller
General-Purpose Timer (GPTM) Eight 16/32-bit GPTM blocks
Watchdog Timer (WDT) Two watchdog timers
Hibernation Module (HIB) Low-power battery-backed Hibernation module
General-Purpose Input/Output (GPIO) 15 physical GPIO blocks
Advanced Motion Control
Pulse Width Modulator (PWM) One PWM module, with four PWM generator blocks and a control
block, for a total of 8 PWM outputs.

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Table 1-1. TM4C1294NCPDT Microcontroller Features (continued)

Feature Description
Quadrature Encoder Interface (QEI) One QEI module
Analog Support
Analog-to-Digital Converter (ADC) Two 12-bit ADC modules, each with a maximum sample rate of two
million samples/second
Analog Comparator Controller Three independent integrated analog comparators
Digital Comparator 16 digital comparators
JTAG and Serial Wire Debug (SWD) One JTAG module with integrated ARM SWD
Package Information
Package 128-pin TQFP
Operating Range (Ambient) Industrial (-40°C to 85°C) temperature range
Extended (-40°C to 105°C) temperature range

Figure 1-1 on page 54 shows the features on the TM4C1294NCPDT microcontroller. Note that there
are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB)
bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back
access performance than the APB bus.

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Figure 1-1. Tiva™ TM4C1294NCPDT Microcontroller High-Level Block Diagram

JTAG/SWD
ARM®
Cortex™-M4F Boot Loader
ROM DriverLib
(120MHz) AES & CRC
Ethernet Boot Loader
System ETM FPU
Control and DCode bus Flash
Clocks (1024KB)
(w/ Precis. Osc.) NVIC MPU
ICode bus
System Bus

TM4C1294NCPDT Bus Matrix

SRAM
(256KB)

SYSTEM PERIPHERALS

Watchdog
DMA Timer
(2 Units)

Hibernation
EEPROM
Module
(6K)
Tamper

General-
GPIOs
(90) Purpose
Timer (8 Units)

External
CRC Peripheral
Module Interface
Advanced High-Performance Bus (AHB)

Advanced Peripheral Bus (APB)

SERIAL PERIPHERALS

USB OTG UART
(FS PHY (8 Units)
or ULPI)

SSI I2C
(4 Units) (10 Units)

CAN
Ethernet Controller
MAC/PHY
(2 Units)

ANALOG PERIPHERALS

Analog 12- Bit ADC

Comparator (2 Units /
(3 Units) 20 Channels)

MOTION CONTROL PERIPHERALS

PWM
QEI
(1 Units / (1 Units)
8 Signals)

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1.3 TM4C1294NCPDT Microcontroller Features

The TM4C1294NCPDT microcontroller component features and general function are discussed in
more detail in the following section.

1.3.1 ARM Cortex-M4F Processor Core

All members of the Tiva™ C Series, including the TM4C1294NCPDT microcontroller, are designed
around an ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a
high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.

1.3.1.1 Processor Core (see page 80)

■ 32-bit ARM Cortex-M4F architecture optimized for small-footprint embedded applications

■ 120-MHz operation; 150 DMIPS performance

■ Outstanding processing performance combined with fast interrupt handling

■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications

– Single-cycle multiply instruction and hardware divide

– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control

– Unaligned data access, enabling data to be efficiently packed into memory

■ IEEE754-compliant single-precision Floating-Point Unit (FPU)

■ 16-bit SIMD vector processing unit

■ Fast code execution permits slower processor clock or increases sleep mode time

■ Harvard architecture characterized by separate buses for instruction and data

■ Efficient processor core, system and memories

■ Hardware division and fast digital-signal-processing orientated multiply accumulate

■ Saturating arithmetic for signal processing

■ Deterministic, high-performance interrupt handling for time-critical applications

■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality

■ Enhanced system debug with extensive breakpoint and trace capabilities

■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing

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■ Migration from the ARM7™ processor family for better performance and power efficiency

■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal
Memory” on page 600 for more information.

■ Ultra-low power consumption with integrated sleep modes

1.3.1.2 System Timer (SysTick) (see page 135)

ARM Cortex-M4F includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:

■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine

■ A high-speed alarm timer using the system clock

■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter

■ A simple counter used to measure time to completion and time used

■ An internal clock-source control based on missing/meeting durations

1.3.1.3 Nested Vectored Interrupt Controller (NVIC) (see page 136)

The TM4C1294NCPDT controller includes the ARM Nested Vectored Interrupt Controller (NVIC).
The NVIC and Cortex-M4F prioritize and handle all exceptions in Handler Mode. The processor
state is automatically stored to the stack on an exception and automatically restored from the stack
at the end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the
state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 106 interrupts.

■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining (these
values reflect no FPU stacking)

■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications

■ Dynamically reprioritizable interrupts

■ Exceptional interrupt handling via hardware implementation of required register manipulations

1.3.1.4 System Control Block (SCB) (see page 137)

The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.

1.3.1.5 Memory Protection Unit (MPU) (see page 137)

The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The
MPU provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.

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1.3.1.6 Floating-Point Unit (FPU) (see page 142)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate,
and square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.

■ 32-bit instructions for single-precision (C float) data-processing operations

■ Combined multiply and accumulate instructions for increased precision (Fused MAC)

■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root

■ Hardware support for denormals and all IEEE rounding modes

■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers

■ Decoupled three stage pipeline

1.3.2 On-Chip Memory

The TM4C1294NCPDT microcontroller is integrated with the following set of on-chip memory and
features:

■ 256 KB single-cycle SRAM

■ 1024 KB Flash memory

■ 6KB EEPROM

■ Internal ROM loaded with TivaWare™ for C Series software:

– TivaWare™ Peripheral Driver Library
– TivaWare Boot Loader
– Advanced Encryption Standard (AES) cryptography tables
– Cyclic Redundancy Check (CRC) error detection functionality

1.3.2.1 SRAM (see page 602)

The TM4C1294NCPDT microcontroller provides 256 KB of single-cycle on-chip SRAM. The internal
SRAM of the device is located at offset 0x2000.0000 of the device memory map.
The SRAM is implemented using four 32-bit wide interleaving SRAM banks (separate SRAM arrays)
which allow for increased speed between memory accesses. The SRAM memory provides nearly
2 GB/s memory bandwidth at a 120 MHz clock frequency.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from SRAM by the following masters:

■ µDMA

■ USB

■ Ethernet Controller

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1.3.2.2 Flash Memory (see page 604)

The TM4C1294NCPDT microcontroller provides 1024 KB of on-chip Flash memory. The Flash
memory is configured as four banks of 16K x 128 bits (4 * 256 KB total) which are two-way
interleaved. Memory blocks can be marked as read-only or execute-only, providing different levels
of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of
those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can
only be read by the controller instruction fetch mechanism, protecting the contents of those blocks
from being read by either the controller or by a debugger.
The TM4C1294NCPDT microcontroller provides enhanced performance and power savings by
implementation of two sets of instruction prefetch buffers. Each prefetch buffer is 2 x 256 bits and
can be combined as a 4 x 256-bit prefetch buffer.
The Flash can also be accessed by the µDMA in Run Mode.

1.3.2.3 ROM (see page 602)

The TM4C1294NCPDT ROM is preprogrammed with the following software and programs:

■ TivaWare Peripheral Driver Library

■ TivaWare Boot Loader

■ Advanced Encryption Standard (AES) cryptography tables

■ Cyclic Redundancy Check (CRC) error-detection functionality

The TivaWare Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M4F core.
No special pragmas or custom assembly code prologue/epilogue functions are required. For
applications that require in-field programmability, the royalty-free TivaWare Boot Loader can act as
an application loader and support in-field firmware updates.
The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government. AES is a strong encryption method with reasonable performance and size. In
addition, it is fast in both hardware and software, is fairly easy to implement, and requires little
memory. The Texas Instruments encryption package is available with full source code, and is based
on Lesser General Public License (LGPL) source. An LGPL means that the code can be used within
an application without any copyleft implications for the application (the code does not automatically
become open source). Modifications to the package source, however, must be open source.
CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents
as when previously checked. This technique can be used to validate correct receipt of messages
(nothing lost or modified in transit), to validate data after decompression, to validate that Flash
memory contents have not been changed, and for other cases where the data needs to be validated.
A CRC is preferred over a simple checksum (for example, XOR all bits) because it catches changes
more readily.
Note: CRC software program are available in the TivaWare™ for C Series software for
backward-compatibility. A device that has enhanced CRC integrated module should utilize
this hardware for best performance. Please refer to “Cyclical Redundancy Check
(CRC)” on page 946 for more information.

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1.3.2.4 EEPROM (see page 615)

The TM4C1294NCPDT microcontroller includes an EEPROM with the following features:

■ 6Kbytes of memory accessible as 1536 32-bit words

■ 96 blocks of 16 words (64 bytes) each

■ Built-in wear leveling

■ Access protection per block

■ Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock
codes (application selectable)

■ Interrupt support for write completion to avoid polling

■ Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion)
to 15M operations (when cycling through two pages ) per each 2-page block.

1.3.3 External Peripheral Interface (see page 815)

The External Peripheral Interface (EPI) provides access to external devices using a parallel path.
Unlike communications peripherals such as SSI, UART, and I2C, the EPI is designed to act like a
bus to external peripherals and memory.
The EPI has the following features:

■ 8/16/32-bit dedicated parallel bus for external peripherals and memory

■ Memory interface supports contiguous memory access independent of data bus width, thus
enabling code execution directly from SDRAM, SRAM and Flash memory

■ Blocking and non-blocking reads

■ Separates processor from timing details through use of an internal write FIFO

■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)

– Separate channels for read and write

– Read channel request asserted by programmable levels on the internal Non-Blocking Read
FIFO (NBRFIFO)

– Write channel request asserted by empty on the internal Write FIFO (WFIFO)

The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory
(SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also
provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same
way as a communication mechanism and is speed-controlled using clocking.

■ Synchronous Dynamic Random Access Memory (SDRAM) mode

– Supports x16 (single data rate) SDRAM at up to 60 MHz

– Supports low-cost SDRAMs up to 64 MB (512 megabits)

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– Includes automatic refresh and access to all banks/rows

– Includes a Sleep/Standby mode to keep contents active with minimal power draw

– Multiplexed address/data interface for reduced pin count

■ Host-Bus mode

– Traditional x8 and x16 MCU bus interface capabilities

– Similar device compatibility options as PIC, ATmega, 8051, and others

– Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in
non-multiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with
no byte selects)

– Support for up to 512 Mb PSRAM in quad chip select mode, with dedicated configuration
register read and write enable.

– Support of both muxed and de-muxed address and data

– Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
with support for external FIFO (XFIFO) EMPTY and FULL signals

– Speed controlled, with read and write data wait-state counters

– Support for read/write burst mode to Host Bus

– Multiple chip select modes including single, dual, and quad chip selects, with and without
ALE

– External iRDY signal provided for stall capability of reads and writes

– Manual chip-enable (or use extra address pins)

■ General-Purpose mode

– Wide parallel interfaces for fast communications with CPLDs and FPGAs

– Data widths up to 32 bits

– Data rates up to 150 MB/second

– Optional "address" sizes from 4 bits to 20 bits

– Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable
input

■ General parallel GPIO

– 1 to 32 bits, FIFOed with speed control

– Useful for custom peripherals or for digital data acquisition and actuator controls

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1.3.4 Cyclical Redundancy Check (CRC) (see page 946)

The TM4C1294NCPDT microcontroller includes a CRC computation module for uses such as
message transfer and safety system checks. The CRC has the following features:

■ Support four major CRC forms:

– CRC16-CCITT as used by CCITT/ITU X.25

– CRC16-IBM as used by USB and ANSI

– CRC32-IEEE as used by IEEE802.3 and MPEG2

– CRC32C as used by G.Hn

■ Allows word and byte feed

■ Supports auto-initialization and manual initialization

■ Supports MSb and LSb

■ Supports CCITT post-processing

■ Can be fed by µDMA, Flash memory and code

1.3.5 Serial Communications Peripherals

The TM4C1294NCPDT controller supports both asynchronous and synchronous serial
communications with:

■ 10/100 Ethernet MAC with Advanced IEEE 1588 PTP hardware and both Media Independent
Interface (MII) and Reduced MII (RMII) support; integrated PHY provided

■ Two CAN 2.0 A/B controllers

■ USB 2.0 Controller OTG/Host/Device with optional high speed using external PHY through ULPI
interface

■ Eight UARTs with IrDA, 9-bit and ISO 7816 support.

■ Ten I2C modules with four transmission speeds including high-speed mode

■ Four Quad Synchronous Serial Interface modules (QSSI) with bi- and quad-SSI support

The following sections provide more detail on each of these communications functions.

1.3.5.1 Ethernet MAC and PHY (see page 1407)

The TM4C1294NCPDT Ethernet Controller consists of a fully integrated media access controller
(MAC) and network physical (PHY) interface with the following features:

■ Conforms to the IEEE 802.3 specification

– 10BASE-T/100BASE-TX IEEE-802.3 compliant

– Supports 10/100 Mbps data transmission rates

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– Supports full-duplex and half-duplex (CSMA/CD) operation

– Supports flow control and back pressure

– Full-featured and enhanced auto-negotiation

– Supports IEEE 802.1Q VLAN tag detection

■ Conforms to IEEE 1588-2002 Timestamp Precision Time Protocol (PTP) protocol and the IEEE
1588-2008 Advanced Timestamp specification

– Transmit and Receive frame time stamping

– Precision Time Protocol

– Flexible pulse per second output

– Supports coarse and fine correction methods

■ Multiple addressing modes

– Four MAC address filters

– Programmable 64-bit Hash Filter for multicast address filtering

– Promiscuous mode support

■ Processor offloading

– Programmable insertion (TX) or deletion (RX) of preamble and start-of-frame data

– Programmable generation (TX) or deletion (RX) of CRC and pad data

– IP header and hardware checksum checking (IPv4, IPv6, TCP/UDP/ICMP)

■ Highly configurable

– LED activity selection

– Supports network statistics with RMON/MIB counters

– Supports Magic Packet and wakeup frames

■ Efficient transfers using integrated Direct Memory Access (DMA)

– Dual-buffer (ring) or linked-list (chained) descriptors

– Round-robin or fixed priority arbitration between TX/RX

– Descriptors support up to 8 kB transfer blocks size

– Programmable interrupts for flexible system implementation

■ Physical media manipulation

– MDI/MDI-X cross-over support

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– Register-programmable transmit amplitude

– Automatic polarity correction and 10BASE-T signal reception

1.3.5.2 Controller Area Network (CAN) (see page 1356)

Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally
created for automotive purposes, it is now used in many embedded control applications (for example,
industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters.
Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information.
The TM4C1294NCPDT microcontroller includes two CAN units with the following features:

■ CAN protocol version 2.0 part A/B

■ Bit rates up to 1 Mbps

■ 32 message objects with individual identifier masks

■ Maskable interrupt

■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications

■ Programmable loopback mode for self-test operation

■ Programmable FIFO mode enables storage of multiple message objects

■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals

1.3.5.3 Universal Serial Bus (USB) (see page 1644)

Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected
and disconnected using a standardized interface without rebooting the system.
The TM4C1294NCPDT microcontroller has one USB controller that supports high and full speed
multi-point communications and complies with the USB 2.0 standard for high-speed function. The
USB controller can have three configurations: USB Device, USB Host, and USB On-The-Go
(negotiated on-the-go as host or device when connected to other USB-enabled systems). Support
for full-speed communication is provided by using the integrated USB PHY or optionally, a high-speed
ULPI interface can communicate to an external PHY.
The USB module has the following features:

■ Complies with USB-IF (Implementer's Forum) certification standards

■ USB 2.0 high-speed (480 Mbps) operation with the integrated ULPI interface communicating
with an external PHY

■ Link Power Management support which uses link-state awareness to reduce power usage

■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous

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■ 16 endpoints

– 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint

– 7 configurable IN endpoints and 7 configurable OUT endpoints

■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size

■ VBUS droop detection and interrupt

■ Integrated USB DMA with bus master capability

– Up to eight RX Endpoint channels and up to eight TX Endpoint channels are available.

– Each channel can be separately programmed to operate in different modes

– Incremental burst transfers of 4-, 8-, 16- or unspecified length supported

1.3.5.4 UART (see page 1161)

A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The TM4C1294NCPDT microcontroller includes eight fully programmable 16C550-type UARTs.
Although the functionality is similar to a 16C550 UART, this UART design is not register compatible.
The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, modem
status, and error conditions. The module generates a single combined interrupt when any of the
interrupts are asserted and are unmasked.
The eight UARTs have the following features:

■ Programmable baud-rate generator allowing speeds up to 7.5 Mbps for regular speed (divide
by 16) and 15 Mbps for high speed (divide by 8)

■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading

■ Programmable FIFO length, including 1-byte deep operation providing conventional

double-buffered interface

■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

■ Standard asynchronous communication bits for start, stop, and parity

■ Line-break generation and detection

■ Fully programmable serial interface characteristics

– 5, 6, 7, or 8 data bits

– Even, odd, stick, or no-parity bit generation/detection

– 1 or 2 stop bit generation

■ IrDA serial-IR (SIR) encoder/decoder providing

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– Programmable use of IrDA Serial Infrared (SIR) or UART input/output

– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex

– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations

– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration

■ Support for communication with ISO 7816 smart cards

■ Modem functionality available on the following UARTs:

– UART0 (modem flow control and modem status)

– UART1 (modem flow control and modem status)

– UART2 (modem flow control)

– UART3 (modem flow control)

– UART4 (modem flow control)

■ EIA-485 9-bit support

■ Standard FIFO-level and End-of-Transmission interrupts

■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)

– Separate channels for transmit and receive

– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level

– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level

■ Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate
baud clock

1.3.5.5 I2C (see page 1275)

The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I2C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I2C bus can be designated as either a master or a slave. I2C module supports
both sending and receiving data as either a master or a slave and can operate simultaneously as
both a master and a slave. Both the I2C master and slave can generate interrupts.
The TM4C1294NCPDT microcontroller includes I2C modules with the following features:

■ Devices on the I2C bus can be designated as either a master or a slave

– Supports both transmitting and receiving data as either a master or a slave

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– Supports simultaneous master and slave operation

■ Four I2C modes

– Master transmit

– Master receive

– Slave transmit

– Slave receive

■ Two 8-entry FIFOs for receive and transmit data

– FIFOs can be independently assigned to master or slave

■ Four transmission speeds:

– Standard (100 Kbps)

– Fast-mode (400 Kbps)

– Fast-mode plus (1 Mbps)

– High-speed mode (3.33 Mbps)

■ Glitch suppression

■ SMBus support through software

– Clock low timeout interrupt

– Dual slave address capability

– Quick command capability

■ Master and slave interrupt generation

– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)

– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected

■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode

■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)

– Separate channels for transmit and receive

– Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in
the I2C

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1.3.5.6 QSSI (see page 1226)

Quad Synchronous Serial Interface (QSSI) is a bi-directional communications interface that converts
data between parallel and serial. The QSSI module performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The QSSI module can be configured as either a master or slave device. As a slave device,
the QSSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The QSSI module also includes a programmable bit rate clock divider and prescaler to generate
the output serial clock derived from the QSSI module's input clock. Bit rates are generated based
on the input clock and the maximum bit rate is determined by the connected peripheral.
The TM4C1294NCPDT microcontroller includes four QSSI modules with the following features:

■ Four QSSI channels with Advanced, Bi- and Quad-SSI functionality

■ Programmable interface operation for Freescale SPI or Texas Instruments synchronous serial
interfaces in Legacy Mode. Support for Freescale interface in Bi- and Quad-SSI mode.

■ Master or slave operation

■ Programmable clock bit rate and prescaler

■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep

■ Programmable data frame size from 4 to 16 bits

■ Internal loopback test mode for diagnostic/debug testing

■ Standard FIFO-based interrupts and End-of-Transmission interrupt

■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)

– Separate channels for transmit and receive

– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries

– Transmit single request asserted when there is space in the FIFO; burst request asserted
when four or more entries are available to be written in the FIFO

– Maskable µDMA interrupts for receive and transmit complete

■ Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate
baud clock.

1.3.6 System Integration

The TM4C1294NCPDT microcontroller provides a variety of standard system functions integrated
into the device, including:

■ Direct Memory Access Controller (DMA)

■ System control and clocks including on-chip precision 16-MHz oscillator

■ Eight 32-bit timers (each of which can be configured as two 16-bit timers)

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■ Lower-power battery-backed Hibernation module

■ Real-Time Clock in Hibernation module

■ Two Watchdog Timers

– One timer runs off the main oscillator
– One timer runs off the precision internal oscillator

■ Up to 90 GPIOs, depending on configuration

– Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
– Independently configurable to 2-, 4-, 8-, 10-, or 12-mA drive capability
– Up to 4 GPIOs can have 18-mA drive capability

The following sections provide more detail on each of these functions.

1.3.6.1 Direct Memory Access (see page 678)

The TM4C1294NCPDT microcontroller includes a Direct Memory Access (DMA) controller, known
as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M4F processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
®
■ ARM PrimeCell 32-channel configurable µDMA controller

■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple

transfer modes

– Basic for simple transfer scenarios

– Ping-pong for continuous data flow

– Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single
request

■ Highly flexible and configurable channel operation

– Independently configured and operated channels

– Dedicated channels for supported on-chip modules

– Flexible channel assignments

– One channel each for receive and transmit path for bidirectional modules

– Dedicated channel for software-initiated transfers

– Per-channel configurable priority scheme

– Optional software-initiated requests for any channel

■ Two levels of priority

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■ Design optimizations for improved bus access performance between µDMA controller and the
processor core

– µDMA controller access is subordinate to core access

– RAM striping

– Peripheral bus segmentation

■ Data sizes of 8, 16, and 32 bits

■ Transfer size is programmable in binary steps from 1 to 1024

■ Source and destination address increment size of byte, half-word, word, or no increment

■ Maskable peripheral requests

■ Interrupt on transfer completion, with a separate interrupt per channel

1.3.6.2 System Control and Clocks (see page 220)

System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.

■ Device identification information: version, part number, SRAM size, Flash memory size, and so
on

■ Power control

– On-chip fixed Low Drop-Out (LDO) voltage regulator

– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits

– Low-power options for microcontroller: Sleep and Deep-Sleep modes with clock gating

– Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory

– 3.3-V supply brown-out detection and reporting via interrupt or reset

■ Multiple clock sources for microcontroller system clock. The TM4C1294NCPDT microcontroller
is clocked by the system clock (SYSCLK) that is distributed to the processor and integrated
peripherals after clock gating. The SYSCLK frequency is based on the frequency of the clock
source and a divisor factor. A PLL is provided for the generation of system clock frequencies in
excess of the reference clock provided. The reference clocks for the PLL are the PIOSC and the
main crystal oscillator. The following clock sources are provided to the TM4C1294NCPDT
microcontroller:

– 16-MHz Precision Oscillator (PIOSC)

– Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external
single-ended clock source is connected to the OSC0 input pin, or an external crystal is
connected across the OSC0 input and OSC1 output pins.

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– Low Frequency Internal Oscillator (LFIOSC): On-chip resource used during power-saving
modes

– Hibernate RTC oscillator (RTCOSC) clock that can be configured to be the 32.768-kHz
external oscillator source from the Hibernation (HIB) module or the HIB Low Frequency clock
source (HIB LFIOSC), which is located within the Hibernation Module.

■ Flexible reset sources

– Power-on reset (POR)

– Reset pin assertion

– Brown-out reset (BOR) detector alerts to system power drops

– Software reset

– Watchdog timer reset

– Hibernation module event

– MOSC failure

■ 128-bit unique identifier for individual device identification

1.3.6.3 Programmable Timers (see page 955)

Programmable timers can be used to count or time external events that drive the Timer input pins.
Each 16/32-bit GPTM block provides two 16-bit timers/counters that can be configured to operate
independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit
Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions
and DMA transfers.
The General-Purpose Timer Module (GPTM) contains eight 16/32-bit GPTM blocks with the following
functional options:

■ Operating modes:

– 16- or 32-bit programmable one-shot timer

– 16- or 32-bit programmable periodic timer

– 16-bit general-purpose timer with an 8-bit prescaler

– 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input

– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler

– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the
PWM signal

– The System Clock or a global Alternate Clock (ALTCLK) resource can be used as timer clock
source. The global ALTCLK can be:

• PIOSC

• Hibernation Module Real-time clock output (RTCOSC)

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• Low-frequency internal oscillator (LFIOSC)

■ Count up or down

■ Twelve 16/32-bit Capture Compare PWM pins (CCP)

■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events

■ Timer synchronization allows selected timers to start counting on the same clock cycle

■ ADC event trigger

■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding
RTC mode)

■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine

■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)

– Dedicated channel for each timer

– Burst request generated on timer interrupt

1.3.6.4 CCP Pins (see page 962)

Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM
output on the CCP pin.
The TM4C1294NCPDT microcontroller includes twelve 16/32-bit CCP pins that can be programmed
to operate in the following modes:

■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.

The GP Timer captures and stores the current timer value when a programmed event occurs.

■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.

The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.

■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.

1.3.6.5 Hibernation Module (HIB) (see page 531)

The Hibernation module provides logic to switch power off to the main processor and peripherals
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic and has the following features:

■ 32-bit real-time seconds counter (RTC) with 1/32,768 second resolution and a 15-bit sub-seconds
counter

– 32-bit RTC seconds match register and a 15-bit sub seconds match for timed wake-up and
interrupt generation with 1/32,768 second resolution

– RTC predivider trim for making fine adjustments to the clock rate

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■ Hardware Calendar Function

– Year, Month, Day, Day of Week, Hours, Minutes, Seconds

– Four-year leap compensation

– 24-hour or AM/PM configuration

■ Two mechanisms for power control

– System power control using discrete external regulator

– On-chip power control using internal switches under register control

■ VDD supplies power when valid, even if VBAT > VDD

■ Dedicated pin for waking using an external signal

■ Capability to configure external reset (RST) pin and/or up to four GPIO port pins as wake source,
with programmable wake level

■ Tamper Functionality

– Support for four tamper inputs

– Configurable level, weak pull-up, and glitch filter

– Configurable tamper event response

– Logging of up to four tamper events

– Optional BBRAM erase on tamper detection

– Tamper wake from hibernate capability

– Hibernation clock input failure detect with a switch to the internal oscillator on detection

■ RTC operational and hibernation memory valid as long as VDD or VBAT is valid

■ Low-battery detection, signaling, and interrupt generation, with optional wake on low battery

■ GPIO pin state can be retained during hibernation

■ Clock source from an internal low frequency oscillator (HIB LFIOSC) or a 32.768-kHz external
crystal or oscillator

■ Sixteen 32-bit words of battery-backed memory to save state during hibernation

■ Programmable interrupts for:

– RTC match

– External wake

– Low battery

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1.3.6.6 Watchdog Timers (see page 1028)

A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The TM4C1294NCPDT Watchdog
Timer can generate an interrupt, a non-maskable interrupt, or a reset when a time-out value is
reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate
an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second
timeout. Once the Watchdog Timer has been configured, the lock register can be written to prevent
the timer configuration from being inadvertently altered.
The TM4C1294NCPDT microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses
the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The
Watchdog Timer module has the following features:

■ 32-bit down counter with a programmable load register

■ Separate watchdog clock with an enable

■ Programmable interrupt generation logic with interrupt masking and optional NMI function

■ Lock register protection from runaway software

■ Reset generation logic with an enable/disable

■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug

1.3.6.7 Programmable GPIOs (see page 742)

General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The
TM4C1294NCPDT GPIO module is comprised of 15 physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 0-90 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 1772 for the signals available to each GPIO pin).

■ Up to 90 GPIOs, depending on configuration

■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions

■ 3.3-V-tolerant in input configuration

■ Advanced High Performance Bus accesses all ports:

– Ports A-H and J; Ports K-N and P-Q

■ Fast toggle capable of a change every clock cycle for ports on AHB

■ Programmable control for GPIO interrupts

– Interrupt generation masking

– Edge-triggered on rising, falling, or both

– Level-sensitive on High or Low values

– Per-pin interrupts available on Port P and Port Q

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■ Bit masking in both read and write operations through address lines

■ Can be used to initiate an ADC sample sequence or a μDMA transfer

■ Pin state can be retained during Hibernation mode; pins on port P can be programmed to wake
on level in Hibernation mode

■ Pins configured as digital inputs are Schmitt-triggered

■ Programmable control for GPIO pad configuration

– Weak pull-up or pull-down resistors

– 2-mA, 4-mA, 6-mA, 8-mA, 10-mA and 12-mA pad drive for digital communication; up to four
pads can sink 18-mA for high-current applications

– Slew rate control for 8-mA, 10-mA and 12-mA pad drive

– Open drain enables

– Digital input enables

1.3.7 Advanced Motion Control

The TM4C1294NCPDT microcontroller provides motion control functions integrated into the device,
including:

■ Eight advanced PWM outputs for motion and energy applications

■ Four fault inputs to promote low-latency shutdown

■ One Quadrature Encoder Input (QEI)

The following provides more detail on these motion control functions.

1.3.7.1 PWM (see page 1669)

The TM4C1294NCPDT microcontroller contains one PWM module, with four PWM generator blocks
and a control block, for a total of 8 PWM outputs. Pulse width modulation (PWM) is a powerful
technique for digitally encoding analog signal levels. High-resolution counters are used to generate
a square wave, and the duty cycle of the square wave is modulated to encode an analog signal.
Typical applications include switching power supplies and motor control. The TM4C1294NCPDT
PWM module consists of four PWM generator block and a control block. Each PWM generator block
contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a
dead-band generator, and an interrupt/ADC-trigger selector. Each PWM generator block produces
two PWM signals that can either be independent signals or a single pair of complementary signals
with dead-band delays inserted.
Each PWM generator has the following features:

■ Four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage
to the motor being controlled

■ One 16-bit counter

– Runs in Down or Up/Down mode

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– Output frequency controlled by a 16-bit load value

– Load value updates can be synchronized

– Produces output signals at zero and load value

■ Two PWM comparators

– Comparator value updates can be synchronized

– Produces output signals on match

■ PWM signal generator

– Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals

– Produces two independent PWM signals

■ Dead-band generator

– Produces two PWM signals with programmable dead-band delays suitable for driving a half-H
bridge

– Can be bypassed, leaving input PWM signals unmodified

■ Can initiate an ADC sample sequence

The control block determines the polarity of the PWM signals and which signals are passed through
to the pins. The output of the PWM generation blocks are managed by the output control block
before being passed to the device pins. The PWM control block has the following options:

■ PWM output enable of each PWM signal

■ Optional output inversion of each PWM signal (polarity control)

■ Optional fault handling for each PWM signal

■ Synchronization of timers in the PWM generator blocks

■ Synchronization of timer/comparator updates across the PWM generator blocks

■ Extended PWM synchronization of timer/comparator updates across the PWM generator blocks

■ Interrupt status summary of the PWM generator blocks

■ Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering

■ PWM generators can be operated independently or synchronized with other generators

1.3.7.2 QEI (see page 1748)

A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index
signal, can be used to reset the position counter. The TM4C1294NCPDT quadrature encoder with
index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position

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over time and determine direction of rotation. In addition, it can capture a running estimate of the
velocity of the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the
processor frequency (for example, 30 MHz for a 120-MHz system).
The TM4C1294NCPDT microcontroller includes one QEI module providing control of one motor
with the following features:

■ Position integrator that tracks the encoder position

■ Programmable noise filter on the inputs

■ Velocity capture using built-in timer

■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)

■ Interrupt generation on:

– Index pulse

– Velocity-timer expiration

– Direction change

– Quadrature error detection

1.3.8 Analog
The TM4C1294NCPDT microcontroller provides analog functions integrated into the device, including:

■ Two 12-bit Analog-to-Digital Converters (ADC), with a total of 20 analog input channels and each
with a sample rate of two million samples/second

■ Three analog comparators

■ On-chip voltage regulator

The following provides more detail on these analog functions.

1.3.8.1 ADC (see page 1053)

An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number. The TM4C1294NCPDT ADC module features 12-bit conversion resolution
and supports 20 input channels plus an internal temperature sensor. Four buffered sample
sequencers allow rapid sampling of up to 20 analog input sources without controller intervention.
Each sample sequencer provides flexible programming with fully configurable input source, trigger
events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator
function that allows the conversion value to be diverted to a comparison unit that provides eight
digital comparators.
The TM4C1294NCPDT microcontroller provides two ADC modules, each with the following features:

■ 20 shared analog input channels

■ 12-bit precision ADC

■ Single-ended and differential-input configurations

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■ On-chip internal temperature sensor

■ Maximum sample rate of two million samples/second

■ Optional, programmable phase delay

■ Sample and hold window programmability

■ Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs

■ Flexible trigger control

– Controller (software)

– Timers

– Analog Comparators

– PWM

– GPIO

■ Hardware averaging of up to 64 samples

■ Eight digital comparators

■ Converter uses signals VREFA+ and GNDA as the voltage reference

■ Power and ground for the analog circuitry is separate from the digital power and ground

■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)

– Dedicated channel for each sample sequencer

– ADC module uses burst requests for DMA

■ Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate
ADC clock

1.3.8.2 Analog Comparators (see page 1653)

An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result. The TM4C1294NCPDT microcontroller provides three
independent integrated analog comparators that can be configured to drive an output or generate
an interrupt or ADC event.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The TM4C1294NCPDT microcontroller provides three independent integrated analog comparators
with the following functions:

■ Compare external pin input to external pin input or to internal programmable voltage reference

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■ Compare a test voltage against any one of the following voltages:

– An individual external reference voltage

– A shared single external reference voltage

– A shared internal reference voltage

1.3.9 JTAG and ARM Serial Wire Debug (see page 207)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port
(SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one
module providing all the normal JTAG debug and test functionality plus real-time access to system
memory without halting the core or requiring any target resident code. The SWJ-DP interface has
the following features:

■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller

■ Four-bit Instruction Register (IR) chain for storing JTAG instructions

■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST

■ ARM additional instructions: APACC, DPACC and ABORT

■ Integrated ARM Serial Wire Debug (SWD)

– Serial Wire JTAG Debug Port (SWJ-DP)

– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

– Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling

– Instrumentation Trace Macrocell (ITM) for support of printf style debugging

– Embedded Trace Macrocell (ETM) for instruction trace capture

– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

1.3.10 Packaging and Temperature

■ 128-pin RoHS-compliant TQFP package

■ Industrial (-40°C to 85°C) ambient temperature range

■ Extended (-40°C to 105°C) ambient temperature range

1.4 TM4C1294NCPDT Microcontroller Hardware Details

Details on the pins and package can be found in the following sections:

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■ “Pin Diagram” on page 1771

■ “Signal Tables” on page 1772

■ “Electrical Characteristics” on page 1818

■ “Package Information” on page 1885

1.5 Kits
The Tiva™ C Series provides the hardware and software tools that engineers need to begin
development quickly.

■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files

■ Evaluation Kits provide a low-cost and effective means of evaluating TM4C1294NCPDT

microcontrollers before purchase

■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box

See the Tiva series website at http://www.ti.com/tiva-c for the latest tools available, or ask your
distributor.

1.6 Support Information

For support on Tiva™ C Series products, contact the TI Worldwide Product Information Center
nearest you.

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2 The Cortex-M4F Processor

The ARM® Cortex™-M4F processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
®
■ 32-bit ARM Cortex™-M4F architecture optimized for small-footprint embedded applications

■ 120-MHz operation; 150 DMIPS performance

■ Outstanding processing performance combined with fast interrupt handling

■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications

– Single-cycle multiply instruction and hardware divide

– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control

– Unaligned data access, enabling data to be efficiently packed into memory

■ IEEE754-compliant single-precision Floating-Point Unit (FPU)

■ 16-bit SIMD vector processing unit

■ Fast code execution permits slower processor clock or increases sleep mode time

■ Harvard architecture characterized by separate buses for instruction and data

■ Efficient processor core, system and memories

■ Hardware division and fast digital-signal-processing orientated multiply accumulate

■ Saturating arithmetic for signal processing

■ Deterministic, high-performance interrupt handling for time-critical applications

■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality

■ Enhanced system debug with extensive breakpoint and trace capabilities

■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing

■ Migration from the ARM7™ processor family for better performance and power efficiency

■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal
Memory” on page 600 for more information.

■ Ultra-low power consumption with integrated sleep modes

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The Tiva™ C Series microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-conscious applications requiring significant control processing and connectivity capabilities
such as:

■ Low power, hand-held smart devices

■ Gaming equipment
■ Network appliances and switches
■ Home and commercial site monitoring and control
■ Electronic point-of-sale (POS) machines
■ Motion control
■ Medical instrumentation
■ Remote connectivity and monitoring
■ Test and measurement equipment
■ Factory automation
■ Fire and security
■ Smart Energy/Smart Grid solutions
■ Intelligent lighting control
■ Transportation

This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4F
processor, including the programming model, the memory model, the exception model, fault handling,
and power management.
For technical details on the instruction set, see the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A).

2.1 Block Diagram

The Cortex-M4F processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including IEEE754-compliant single-precision floating-point
computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate
capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4F processor implements tightly
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M4F processor implements a version of the
Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced
program memory requirements. The Cortex-M4F instruction set provides the exceptional performance
expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
The Cortex-M4F processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The TM4C1294NCPDT NVIC includes a non-maskable
interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core
and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt
latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.

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Figure 2-1. CPU Block Diagram

FPU ARM
Nested Interrupts
Vectored Cortex-M4F Serial
Sleep CM4 Core Wire
Interrupt
Controller Debug Output
Instructions Data Embedded Trace
Trace Trace Port
Memory
Macrocell Port (SWO)
Protection
Unit Interface
Unit

Data Instrumentation
Flash Watchpoint Trace Macrocell
Patch and and Trace
Breakpoint
ROM
Table

Private Peripheral
Bus Adv. Peripheral
(internal) Bus
I-code bus
Bus
Matrix D-code bus
Serial Wire JTAG Debug System bus
Debug Port Access Port

2.2 Overview
2.2.1 System-Level Interface
The Cortex-M4F processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M4F processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.

2.2.2 Integrated Configurable Debug

The Cortex-M4F processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Tiva™
C Series implementation replaces the ARM SW-DP and JTAG-DP with the ARM
CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface
combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5
Architecture Specification for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.

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The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area smaller
than traditional trace units, enabling full instruction trace. For more details on the ARM ETM, see
the ARM® Embedded Trace Macrocell Architecture Specification.
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions for up to eight
words of program code in the code memory region. This FPB enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M4F debug capabilities, see theARM® Debug Interface V5
Architecture Specification.

2.2.3 Trace Port Interface Unit (TPIU)

The TPIU acts as a bridge between the Cortex-M4F trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 83.

Figure 2-2. TPIU Block Diagram

Debug ARM® Trace

Trace Out Serial Wire
ATB Bus (ATB) Asynchronous FIFO
(serializer) Trace Port
Slave Interface (SWO)
Port

Advance
APB
Peripheral
Slave
Bus (APB)
Port
Interface

2.2.4 Cortex-M4F System Component Details

The Cortex-M4F includes the following system components:

■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 135).

■ Nested Vectored Interrupt Controller (NVIC)

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An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 136).

■ System Control Block (SCB)

The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions
(see “System Control Block (SCB)” on page 137).

■ Memory Protection Unit (MPU)

Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
“Memory Protection Unit (MPU)” on page 137).

■ Floating-Point Unit (FPU)

Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square-root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions (see “Floating-Point Unit (FPU)” on page 142).

2.3 Programming Model

This section describes the Cortex-M4F programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.

2.3.1 Processor Mode and Privilege Levels for Software Execution

The Cortex-M4F has two modes of operation:

■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.

■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.

In addition, the Cortex-M4F has two privilege levels:

■ Unprivileged
In this mode, software has the following restrictions:

– Limited access to the MSR and MRS instructions and no use of the CPS instruction

– No access to the system timer, NVIC, or system control block

– Possibly restricted access to memory or peripherals

■ Privileged
In this mode, software can use all the instructions and has access to all resources.

In Thread mode, the CONTROL register (see page 99) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.

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Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.

2.3.2 Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the memory. When the processor pushes a new item onto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks:
the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 89).
In Thread mode, the CONTROL register (see page 99) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 85.

Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode Use Privilege Level Stack Used
a a
Thread Applications Privileged or unprivileged Main stack or process stack
Handler Exception handlers Always privileged Main stack
a. See CONTROL (page 99).

2.3.3 Register Map

Figure 2-3 on page 86 shows the Cortex-M4F register set. Table 2-2 on page 86 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.

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Figure 2-3. Cortex-M4F Register Set

R0
R1
R2
R3
Low registers
R4
R5
R6 General-purpose registers
R7
R8
R9
High registers R10
R11
R12
Stack Pointer SP (R13) PSP‡ MSP‡ ‡
Banked version of SP
Link Register LR (R14)
Program Counter PC (R15)

PSR Program status register

PRIMASK
FAULTMASK Exception mask registers Special registers
BASEPRI
CONTROL CONTROL register

Table 2-2. Processor Register Map

See
Offset Name Type Reset Description
page

- R0 RW - Cortex General-Purpose Register 0 88

- R1 RW - Cortex General-Purpose Register 1 88

- R2 RW - Cortex General-Purpose Register 2 88

- R3 RW - Cortex General-Purpose Register 3 88

- R4 RW - Cortex General-Purpose Register 4 88

- R5 RW - Cortex General-Purpose Register 5 88

- R6 RW - Cortex General-Purpose Register 6 88

- R7 RW - Cortex General-Purpose Register 7 88

- R8 RW - Cortex General-Purpose Register 8 88

- R9 RW - Cortex General-Purpose Register 9 88

- R10 RW - Cortex General-Purpose Register 10 88

- R11 RW - Cortex General-Purpose Register 11 88

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Table 2-2. Processor Register Map (continued)

See
Offset Name Type Reset Description
page

- R12 RW - Cortex General-Purpose Register 12 88

- SP RW - Stack Pointer 89

- LR RW 0xFFFF.FFFF Link Register 90

- PC RW - Program Counter 91

- PSR RW 0x0100.0000 Program Status Register 92

- PRIMASK RW 0x0000.0000 Priority Mask Register 96

- FAULTMASK RW 0x0000.0000 Fault Mask Register 97

- BASEPRI RW 0x0000.0000 Base Priority Mask Register 98

- CONTROL RW 0x0000.0000 Control Register 99

- FPSC RW - Floating-Point Status Control 101

2.3.4 Register Descriptions

This section lists and describes the Cortex-M4F registers, in the order shown in Figure
2-3 on page 86. The core registers are not memory mapped and are accessed by register name
rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.

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Register 1: Cortex General-Purpose Register 0 (R0)

Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.

Cortex General-Purpose Register 0 (R0)

Type RW, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 DATA RW - Register data.

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Register 14: Stack Pointer (SP)

The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.

Stack Pointer (SP)

Type RW, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SP

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SP

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 SP RW - This field is the address of the stack pointer.

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Register 15: Link Register (LR)

The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged
mode.
EXC_RETURN is loaded into the LR on exception entry. See Table 2-10 on page 123 for the values
and description.

Link Register (LR)

Type RW, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LINK

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LINK

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 LINK RW 0xFFFF.FFFF This field is the return address.

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Register 16: Program Counter (PC)

The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.

Program Counter (PC)

Type RW, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PC

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PC

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 PC RW - This field is the current program address.

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Register 17: Program Status Register (PSR)

Note: This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:

■ Application Program Status Register (APSR), bits 31:27, bits 19:16

■ Execution Program Status Register (EPSR), bits 26:24, 15:10

■ Interrupt Program Status Register (IPSR), bits 7:0

The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 120).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 92 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information
about how to access the program status registers.

Table 2-3. PSR Register Combinations

Register Type Combination
a, b
PSR RW APSR, EPSR, and IPSR
IEPSR RO EPSR and IPSR
a
IAPSR RW APSR and IPSR
b
EAPSR RW APSR and EPSR
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.

Program Status Register (PSR)

Type RW, reset 0x0100.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

N Z C V Q ICI / IT THUMB reserved GE

Type RW RW RW RW RW RO RO RO RO RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ICI / IT reserved ISRNUM

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit/Field Name Type Reset Description

31 N RW 0 APSR Negative or Less Flag

Value Description
1 The previous operation result was negative or less than.
0 The previous operation result was positive, zero, greater than,
or equal.

The value of this bit is only meaningful when accessing PSR or APSR.

30 Z RW 0 APSR Zero Flag

Value Description
1 The previous operation result was zero.
0 The previous operation result was non-zero.

The value of this bit is only meaningful when accessing PSR or APSR.

29 C RW 0 APSR Carry or Borrow Flag

Value Description
1 The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
0 The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.

The value of this bit is only meaningful when accessing PSR or APSR.

28 V RW 0 APSR Overflow Flag

Value Description
1 The previous operation resulted in an overflow.
0 The previous operation did not result in an overflow.

The value of this bit is only meaningful when accessing PSR or APSR.

27 Q RW 0 APSR DSP Overflow and Saturation Flag

Value Description
1 DSP Overflow or saturation has occurred when using a SIMD
instruction.
0 DSP overflow or saturation has not occurred since reset or since
the bit was last cleared.

The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.

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Bit/Field Name Type Reset Description

26:25 ICI / IT RO 0x0 EPSR ICI / IT status

These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following an IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A) for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
Note that these EPSR bits cannot be accessed using MRS and MSR
instructions but the definitions are provided to allow the stacked (E)PSR
value to be decoded within an exception handler.

24 THUMB RO 1 EPSR Thumb State

This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:

■ The BLX, BX and POP{PC} instructions

■ Restoration from the stacked xPSR value on an exception return

■ Bit 0 of the vector value on an exception entry or reset

Attempting to execute instructions when this bit is clear results in a fault

or lockup. See “Lockup” on page 125 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.

23:20 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19:16 GE RW 0x0 Greater Than or Equal Flags

See the description of the SEL instruction in the Cortex™-M4 instruction
set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A) for more information.
The value of this field is only meaningful when accessing PSR or APSR.

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Bit/Field Name Type Reset Description

15:10 ICI / IT RO 0x0 EPSR ICI / IT status

These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor stops the
load multiple or store multiple instruction operation temporarily and
stores the next register operand in the multiple operation to bits 15:12.
After servicing the interrupt, the processor returns to the register pointed
to by bits 15:12 and resumes execution of the multiple load or store
instruction. When EPSR holds the ICI execution state, bits 11:10 are
zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A) for more information.
The value of this field is only meaningful when accessing PSR or EPSR.

9:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 ISRNUM RO 0x00 IPSR ISR Number

This field contains the exception type number of the current Interrupt
Service Routine (ISR).

Value Description
0x00 Thread mode
0x01 Reserved
0x02 NMI
0x03 Hard fault
0x04 Memory management fault
0x05 Bus fault
0x06 Usage fault
0x07-0x0A Reserved
0x0B SVCall
0x0C Reserved for Debug
0x0D Reserved
0x0E PendSV
0x0F SysTick
0x10 Interrupt Vector 0
0x11 Interrupt Vector 1
... ...
0x81 Interrupt Vector 113

See “Exception Types” on page 114 for more information.

The value of this field is only meaningful when accessing PSR or IPSR.

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Register 18: Priority Mask Register (PRIMASK)

The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M4
instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number
ARM DUI 0553A) for more information on these instructions. For more information on exception
priority levels, see “Exception Types” on page 114.

Priority Mask Register (PRIMASK)

Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PRIMASK

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 PRIMASK RW 0 Priority Mask

Value Description
1 Prevents the activation of all exceptions with configurable
priority.
0 No effect.

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Register 19: Fault Mask Register (FAULTMASK)

The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic
User Guide (literature number ARM DUI 0553A) for more information on these instructions. For
more information on exception priority levels, see “Exception Types” on page 114.

Fault Mask Register (FAULTMASK)

Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FAULTMASK

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 FAULTMASK RW 0 Fault Mask

Value Description
1 Prevents the activation of all exceptions except for NMI.
0 No effect.

The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.

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Register 20: Base Priority Mask Register (BASEPRI)

The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 114.

Base Priority Mask Register (BASEPRI)

Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved BASEPRI reserved

Type RO RO RO RO RO RO RO RO RW RW RW RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 BASEPRI RW 0x0 Base Priority

Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.

Value Description
0x0 All exceptions are unmasked.
0x1 All exceptions with priority level 1-7 are masked.
0x2 All exceptions with priority level 2-7 are masked.
0x3 All exceptions with priority level 3-7 are masked.
0x4 All exceptions with priority level 4-7 are masked.
0x5 All exceptions with priority level 5-7 are masked.
0x6 All exceptions with priority level 6-7 are masked.
0x7 All exceptions with priority level 7 are masked.

4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 21: Control Register (CONTROL)

The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode, and indicates whether the FPU state is active. This register is only
accessible in privileged mode.
Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 123).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses the MSP. To
switch the stack pointer used in Thread mode to the PSP, either use the MSR instruction to set the
ASP bit, as detailed in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number ARM DUI 0553A), or perform an exception return to Thread
mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 123.
Note: When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number ARM DUI 0553A).

Control Register (CONTROL)

Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FPCA ASP TMPL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 FPCA RW 0 Floating-Point Context Active

Value Description
1 Floating-point context active
0 No floating-point context active

The Cortex-M4F uses this bit to determine whether to preserve

floating-point state when processing an exception.

Important: Two bits control when FPCA can be enabled: the ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the DISFPCA bit in the Auxiliary Control
(ACTLR) register.

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Bit/Field Name Type Reset Description

1 ASP RW 0 Active Stack Pointer

Value Description
1 The PSP is the current stack pointer.
0 The MSP is the current stack pointer

In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M4F updates this bit automatically on exception return.

0 TMPL RW 0 Thread Mode Privilege Level

Value Description
1 Unprivileged software can be executed in Thread mode.
0 Only privileged software can be executed in Thread mode.

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Register 22: Floating-Point Status Control (FPSC)

The FPSC register provides all necessary user-level control of the floating-point system.

Floating-Point Status Control (FPSC)

Type RW, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

N Z C V reserved AHP DN FZ RMODE reserved

Type RW RW RW RW RO RW RW RW RW RW RO RO RO RO RO RO
Reset - - - - 0 - - - - - 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IDC reserved IXC UFC OFC DZC IOC

Type RO RO RO RO RO RO RO RO RW RO RO RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 - 0 0 - - - - -

Bit/Field Name Type Reset Description

31 N RW - Negative Condition Code Flag

Floating-point comparison operations update this condition code flag.

30 Z RW - Zero Condition Code Flag

Floating-point comparison operations update this condition code flag.

29 C RW - Carry Condition Code Flag

Floating-point comparison operations update this condition code flag.

28 V RW - Overflow Condition Code Flag

Floating-point comparison operations update this condition code flag.

27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26 AHP RW - Alternative Half-Precision

When set, alternative half-precision format is selected. When clear,
IEEE half-precision format is selected.
The AHP bit in the FPDSC register holds the default value for this bit.

25 DN RW - Default NaN Mode

When set, any operation involving one or more NaNs returns the Default
NaN. When clear, NaN operands propagate through to the output of a
floating-point operation.
The DN bit in the FPDSC register holds the default value for this bit.

24 FZ RW - Flush-to-Zero Mode
When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero
mode is disabled and the behavior of the floating-point system is fully
compliant with the IEEE 754 standard.
The FZ bit in the FPDSC register holds the default value for this bit.

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Bit/Field Name Type Reset Description

23:22 RMODE RW - Rounding Mode

The specified rounding mode is used by almost all floating-point
instructions.
The RMODE bit in the FPDSC register holds the default value for this bit.

Value Description
0x0 Round to Nearest (RN) mode
0x1 Round towards Plus Infinity (RP) mode
0x2 Round towards Minus Infinity (RM) mode
0x3 Round towards Zero (RZ) mode

21:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 IDC RW - Input Denormal Cumulative Exception

When set, indicates this exception has occurred since 0 was last written
to this bit.

6:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 IXC RW - Inexact Cumulative Exception

When set, indicates this exception has occurred since 0 was last written
to this bit.

3 UFC RW - Underflow Cumulative Exception

When set, indicates this exception has occurred since 0 was last written
to this bit.

2 OFC RW - Overflow Cumulative Exception

When set, indicates this exception has occurred since 0 was last written
to this bit.

1 DZC RW - Division by Zero Cumulative Exception

When set, indicates this exception has occurred since 0 was last written
to this bit.

0 IOC RW - Invalid Operation Cumulative Exception

When set, indicates this exception has occurred since 0 was last written
to this bit.

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2.3.5 Exceptions and Interrupts

The Cortex-M4F processor supports interrupts and system exceptions. The processor and the
Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception
changes the normal flow of software control. The processor uses Handler mode to handle all
exceptions except for reset. See “Exception Entry and Return” on page 120 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 136 for more information.

2.3.6 Data Types

The Cortex-M4F supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 106 for more information.

2.4 Memory Model

This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the TM4C1294NCPDT controller is provided in Table 2-4 on page 103. In this
manual, register addresses are given as a hexadecimal increment, relative to the module's base
address as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 109).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M4 Peripherals” on page 134).
Note: Within the memory map, attempts to read or write addresses in reserved spaces result in
a bus fault. In addition, attempts to write addresses in the flash range also result in a bus
fault.

Table 2-4. Memory Map

Start End Description For details,
see page ...
Memory
0x0000.0000 0x000F.FFFF On-chip Flash 621
0x0010.0000 0x01FF.FFFF Reserved -
0x0200.0000 0x02FF.FFFF On-chip ROM (16 MB) 602
0x0300.0000 0x1FFF.FFFF Reserved -
0x2000.0000 0x2006.FFFF Bit-banded on-chip SRAM 602
0x2007.0000 0x21FF.FFFF Reserved -
0x2200.0000 0x2234.FFFF Bit-band alias of bit-banded on-chip SRAM starting at 602
0x2000.0000
0x2235.0000 0x3FFF.FFFF Reserved -
Peripherals
0x4000.0000 0x4000.0FFF Watchdog timer 0 1030
0x4000.1000 0x4000.1FFF Watchdog timer 1 1030
0x4000.2000 0x4000.3FFF Reserved -

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Table 2-4. Memory Map (continued)

Start End Description For details,
see page ...
0x4000.4000 0x4000.4FFF GPIO Port A 755
0x4000.5000 0x4000.5FFF GPIO Port B 755
0x4000.6000 0x4000.6FFF GPIO Port C 755
0x4000.7000 0x4000.7FFF GPIO Port D 755
0x4000.8000 0x4000.8FFF SSI0 1243
0x4000.9000 0x4000.9FFF SSI1 1243
0x4000.A000 0x4000.AFFF SSI2 1243
0x4000.B000 0x4000.BFFF SSI3 1243
0x4000.C000 0x4000.CFFF UART0 1173
0x4000.D000 0x4000.DFFF UART1 1173
0x4000.E000 0x4000.EFFF UART2 1173
0x4000.F000 0x4000.FFFF UART3 1173
0x4001.0000 0x4001.0FFF UART4 1173
0x4001.1000 0x4001.1FFF UART5 1173
0x4001.2000 0x4001.2FFF UART6 1173
0x4001.3000 0x4001.3FFF UART7 1173
0x4001.4000 0x4001.FFFF Reserved -
Peripherals
0x4002.0000 0x4002.0FFF I2C 0 1299
0x4002.1000 0x4002.1FFF I2C 1 1299
0x4002.2000 0x4002.2FFF I2C 2 1299
0x4002.3000 0x4002.3FFF I2C 3 1299
0x4002.4000 0x4002.4FFF GPIO Port E 755
0x4002.5000 0x4002.5FFF GPIO Port F 755
0x4002.6000 0x4002.6FFF GPIO Port G 755
0x4002.7000 0x4002.7FFF GPIO Port H 755
0x4002.8000 0x4002.8FFF PWM 0 1679
0x4002.9000 0x4002.BFFF Reserved -
0x4002.C000 0x4002.CFFF QEI0 1753
0x4002.D000 0x4002.FFFF Reserved -
0x4003.0000 0x4003.0FFF 16/32-bit Timer 0 974
0x4003.1000 0x4003.1FFF 16/32-bit Timer 1 974
0x4003.2000 0x4003.2FFF 16/32-bit Timer 2 974
0x4003.3000 0x4003.3FFF 16/32-bit Timer 3 974
0x4003.4000 0x4003.4FFF 16/32-bit Timer 4 974
0x4003.5000 0x4003.5FFF 16/32-bit Timer 5 974
0x4003.6000 0x4003.7FFF Reserved -
0x4003.8000 0x4003.8FFF ADC0 1073
0x4003.9000 0x4003.9FFF ADC1 1073
0x4003.A000 0x4003.BFFF Reserved -
0x4003.C000 0x4003.CFFF Analog Comparators 1659

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Table 2-4. Memory Map (continued)

Start End Description For details,
see page ...
0x4003.D000 0x4003.DFFF GPIO Port J 755
0x4003.E000 0x4003.FFFF Reserved -
0x4004.0000 0x4004.0FFF CAN0 Controller 1375
0x4004.1000 0x4004.1FFF CAN1 Controller 1375
0x4004.2000 0x4004.FFFF Reserved -
0x4005.0000 0x4005.0FFF USB 1646
0x4005.1000 0x4005.7FFF Reserved -
0x4005.8000 0x4005.8FFF GPIO Port A (AHB aperture) 755
0x4005.9000 0x4005.9FFF GPIO Port B (AHB aperture) 755
0x4005.A000 0x4005.AFFF GPIO Port C (AHB aperture) 755
0x4005.B000 0x4005.BFFF GPIO Port D (AHB aperture) 755
0x4005.C000 0x4005.CFFF GPIO Port E (AHB aperture) 755
0x4005.D000 0x4005.DFFF GPIO Port F (AHB aperture) 755
0x4005.E000 0x4005.EFFF GPIO Port G (AHB aperture) 755
0x4005.F000 0x4005.FFFF GPIO Port H (AHB aperture) 755
0x4006.0000 0x4006.0FFF GPIO Port J (AHB aperture) 755
0x4006.1000 0x4006.1FFF GPIO Port K (AHB aperture) 755
0x4006.2000 0x4006.2FFF GPIO Port L (AHB aperture) 755
0x4006.3000 0x4006.3FFF GPIO Port M (AHB aperture) 755
0x4006.4000 0x4006.4FFF GPIO Port N (AHB aperture) 755
0x4006.5000 0x4006.5FFF GPIO Port P (AHB aperture) 755
0x4006.6000 0x4006.6FFF GPIO Port Q (AHB aperture) 755
0x4006.7000 0x400A.EFFF Reserved -
0x400A.F000 0x400A.FFFF EEPROM and Key Locker 621
0x400B.0000 0x400B.7FFF Reserved -
0x400B.8000 0x400B.8FFF I2C 8 1299
0x400B.9000 0x400B.9FFF I2C 9 1299
0x400B.A000 0x400B.FFFF Reserved -
0x400C.0000 0x400C.0FFF I2C 4 1299
0x400C.1000 0x400C.1FFF I2C 5 1299
0x400C.2000 0x400C.2FFF I2C 6 1299
0x400C.3000 0x400C.3FFF I2C 7 1299
0x400C.4000 0x400C.FFFF Reserved -
0x400D.0000 0x400D.0FFF EPI 0 856
0x400D.1000 0x400D.FFFF Reserved -
0x400E.0000 0x400E.0FFF 16/32-bit Timer 6 974
0x400E.1000 0x400E.1FFF 16/32-bit Timer 7 974
0x400E.2000 0x400E.BFFF Reserved -
0x400E.C000 0x400E.CFFF Ethernet Controller 1467
0x400E.D000 0x400F.8FFF Reserved -
0x400F.9000 0x400F.9FFF System Exception Module 523

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Table 2-4. Memory Map (continued)

Start End Description For details,
see page ...
0x400F.A000 0x400F.BFFF Reserved -
0x400F.C000 0x400F.CFFF Hibernation Module 551
0x400F.D000 0x400F.DFFF Flash memory control 621
0x400F.E000 0x400F.EFFF System control 247
0x400F.F000 0x400F.FFFF µDMA 701
0x4010.0000 0x41FF.FFFF Reserved -
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF -
0x4400.0000 0x4402.FFFF Reserved -
0x4403.0000 0x4403.0FFF CRC Module -
0x4403.1000 0x4403.1FFF Reserved [4 kB] -
0x4403.2000 0x4403.3FFF Reserved [8 kB] -
0x4403.4000 0x4403.EFFF Reserved -
0x4403.F000 0x4403.FFFF Reserved [4 kB] -
0x4404.0000 0x4404.FFFF Reserved [64 kB] -
0x4405.0000 0x4405.3FFF Reserved -
0x4405.4000 0x4405.4FFF EPHY 0 1467
0x4405.5000 0x5FFF.FFFF Reserved -
0x6000.0000 0xDFFF.FFFF EPI0 mapped peripheral and RAM -
Private Peripheral Bus
0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 82
0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 82
0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 82
0xE000.3000 0xE000.DFFF Reserved -
0xE000.E000 0xE000.EFFF Cortex-M4F Peripherals (SysTick, NVIC, MPU, FPU and SCB) 146
0xE000.F000 0xE003.FFFF Reserved -
0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 83
0xE004.1000 0xE004.1FFF Embedded Trace Macrocell (ETM) 82
0xE004.2000 0xFFFF.FFFF Reserved -

2.4.1 Memory Regions, Types and Attributes

The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:

■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.

■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.

■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.

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The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.

2.4.2 Memory System Ordering of Memory Accesses

For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 108).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.

2.4.3 Behavior of Memory Accesses

Table 2-5 on page 107 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 106 for more information on memory types and
the XN attribute. Tiva™ C Series devices may have reserved memory areas within the address
ranges shown below (refer to Table 2-4 on page 103 for more information).

Table 2-5. Memory Access Behavior

Address Range Memory Region Memory Type Execute Description
Never
(XN)
0x0000.0000 - 0x1FFF.FFFF Code Normal - This executable region is for program code.
Data can also be stored here.
0x2000.0000 - 0x3FFF.FFFF SRAM Normal - This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 109).
0x4000.0000 - 0x5FFF.FFFF Peripheral Device XN This region includes bit band and bit band
alias areas (see Table 2-7 on page 109).
0x6000.0000 - 0x9FFF.FFFF External RAM Normal - This executable region is for data.
0xA000.0000 - 0xDFFF.FFFF External device Device XN This region is for external device memory.
0xE000.0000- 0xE00F.FFFF Private peripheral Strongly XN This region includes the NVIC, system
bus Ordered timer, and system control block.
0xE010.0000- 0xFFFF.FFFF Reserved - - -

The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M4F has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 137.
The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from
branch target addresses.

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2.4.4 Software Ordering of Memory Accesses

The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:

■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.

■ The processor has multiple bus interfaces.

■ Memory or devices in the memory map have different wait states.

■ Some memory accesses are buffered or speculative.

“Memory System Ordering of Memory Accesses” on page 107 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M4F
has the following memory barrier instructions:

■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.

■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.

■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.

Memory barrier instructions can be used in the following situations:

■ MPU programming

– If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.

– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.

■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.

■ Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.

■ Memory map switching

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If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.

■ Dynamic exception priority change

When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.

Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M4 instruction set chapter
in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A).

2.4.5 Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 109. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 109. For the specific address range of the bit-band regions,
see Table 2-4 on page 103.
Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.

Table 2-6. SRAM Memory Bit-Banding Regions

Address Range
Memory Region Instruction and Data Accesses
Start End
0x2000.0000 0x2006.FFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
0x2200.0000 0x2234.FFFF SRAM bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not remapped.

Table 2-7. Peripheral Memory Bit-Banding Regions

Address Range
Memory Region Instruction and Data Accesses
Start End
0x4000.0000 0x400F.FFFF Peripheral bit-band Direct accesses to this memory range behave as
region peripheral memory accesses, but this region is also bit
addressable through bit-band alias.
0x4200.0000 0x43FF.FFFF Peripheral bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not permitted.

The following formula shows how the alias region maps onto the bit-band region:

bit_word_offset = (byte_offset x 32) + (bit_number x 4)

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bit_word_addr = bit_band_base + bit_word_offset

where:

bit_word_offset
The position of the target bit in the bit-band memory region.

bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.

bit_band_base
The starting address of the alias region.

byte_offset
The number of the byte in the bit-band region that contains the targeted bit.

bit_number
The bit position, 0-7, of the targeted bit.

Figure 2-4 on page 111 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:

■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:

0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)

■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:

0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)

■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:

0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)

■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:

0x2200.001C = 0x2200.0000+ (0*32) + (7*4)

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Figure 2-4. Bit-Band Mapping

32-MB Alias Region

0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0

0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0004 0x2200.0000

1-MB SRAM Bit-Band Region

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0x200F.FFFF 0x200F.FFFE 0x200F.FFFD 0x200F.FFFC

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0x2000.0003 0x2000.0002 0x2000.0001 0x2000.0000

2.4.5.1 Directly Accessing an Alias Region

Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.

2.4.5.2 Directly Accessing a Bit-Band Region

“Behavior of Memory Accesses” on page 107 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.

2.4.6 Data Storage

The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 112 illustrates how data is stored.

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Figure 2-5. Data Storage

Memory Register
7 0

31 24 23 16 15 8 7 0
Address A B0 lsbyte B3 B2 B1 B0

A+1 B1

A+2 B2

A+3 B3 msbyte

2.4.7 Synchronization Primitives

The Cortex-M4F instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
Note: The available pairs of synchronization primitives are only available for single processor use
and should not be used with multi-processor systems.
A pair of synchronization primitives consists of:

■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.

■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.

The pairs of Load-Exclusive and Store-Exclusive instructions are:

■ The word instructions LDREX and STREX

■ The halfword instructions LDREXH and STREXH

■ The byte instructions LDREXB and STREXB

Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, software must:

1. Use a Load-Exclusive instruction to read the value of the location.

2. Modify the value, as required.

3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.

4. Test the returned status bit.

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If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no
write was performed, which indicates that the value returned at step 1 might be out of date. The
software must retry the entire read-modify-write sequence.

Software can use the synchronization primitives to implement a semaphore as follows:

1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.

2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.

3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.

The Cortex-M4F includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:

■ It executes a CLREX instruction.

■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.

■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.

For more information about the synchronization primitive instructions, see the Cortex™-M4 instruction
set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A).

2.5 Exception Model

The ARM Cortex-M4F processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 115 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 106 interrupts (listed in Table 2-9 on page 116).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 136.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.

Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source deassert. Thus if the interrupt clear is done as the last
action in an interrupt handler, it is possible for the interrupt handler to complete while

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the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).

See “Nested Vectored Interrupt Controller (NVIC)” on page 136 for more information on exceptions
and interrupts.

2.5.1 Exception States

Each exception is in one of the following states:

■ Inactive. The exception is not active and not pending.

■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.

■ Active. An exception that is being serviced by the processor but has not completed.
Note: An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.

■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.

2.5.2 Exception Types

The exception types are:

■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.

■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.

■ Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.

■ Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.

■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.

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■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:

– An undefined instruction

– An illegal unaligned access

– Invalid state on instruction execution

– An error on exception return

An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.

■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.

■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.

■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS

environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.

■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.

■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by

a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 116 lists the interrupts on the TM4C1294NCPDT controller.

For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 115 shows as having
configurable priority (see the SYSHNDCTRL register on page 180 and the DIS0 register on page 155).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 123.

Table 2-8. Exception Types

a
Exception Type Vector Priority Vector Address or Activation
b
Number Offset
- 0 - 0x0000.0000 Stack top is loaded from the first
entry of the vector table on reset.
Reset 1 -3 (highest) 0x0000.0004 Asynchronous
Non-Maskable Interrupt 2 -2 0x0000.0008 Asynchronous
(NMI)
Hard Fault 3 -1 0x0000.000C -
c
Memory Management 4 programmable 0x0000.0010 Synchronous

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Table 2-8. Exception Types (continued)

a
Exception Type Vector Priority Vector Address or Activation
b
Number Offset
c
Bus Fault 5 programmable 0x0000.0014 Synchronous when precise and
asynchronous when imprecise
c
Usage Fault 6 programmable 0x0000.0018 Synchronous
- 7-10 - - Reserved
c
SVCall 11 programmable 0x0000.002C Synchronous
c
Debug Monitor 12 programmable 0x0000.0030 Synchronous
- 13 - - Reserved
c
PendSV 14 programmable 0x0000.0038 Asynchronous
c
SysTick 15 programmable 0x0000.003C Asynchronous
d
Interrupts 16 and above programmable 0x0000.0040 and above Asynchronous
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 119.
c. See SYSPRI1 on page 177.
d. See PRIn registers on page 159.

Table 2-9. Interrupts

Vector Number Interrupt Number (Bit Vector Address or Description
in Interrupt Registers) Offset
0-15 - 0x0000.0000 - Processor exceptions
0x0000.003C
16 0 0x0000.0040 GPIO Port A
17 1 0x0000.0044 GPIO Port B
18 2 0x0000.0048 GPIO Port C
19 3 0x0000.004C GPIO Port D
20 4 0x0000.0050 GPIO Port E
21 5 0x0000.0054 UART0
22 6 0x0000.0058 UART1
23 7 0x0000.005C SSI0
24 8 0x0000.0060 I2C0
25 9 0x0000.0064 PWM Fault
26 10 0x0000.0068 PWM Generator 0
27 11 0x0000.006C PWM Generator 1
28 12 0x0000.0070 PWM Generator 2
29 13 0x0000.0074 QEI0
30 14 0x0000.0078 ADC0 Sequence 0
31 15 0x0000.007C ADC0 Sequence 1
32 16 0x0000.0080 ADC0 Sequence 2
33 17 0x0000.0084 ADC0 Sequence 3
34 18 0x0000.0088 Watchdog Timers 0 and 1
35 19 0x0000.008C 16/32-Bit Timer 0A
36 20 0x0000.0090 16/32-Bit Timer 0B
37 21 0x0000.0094 16/32-Bit Timer 1A

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Table 2-9. Interrupts (continued)

Vector Number Interrupt Number (Bit Vector Address or Description
in Interrupt Registers) Offset
38 22 0x0000.0098 16/32-Bit Timer 1B
39 23 0x0000.009C 16/32-Bit Timer 2A
40 24 0x0000.00A0 16/32-Bit Timer 2B
41 25 0x0000.00A4 Analog Comparator 0
42 26 0x0000.00A8 Analog Comparator 1
43 27 0x0000.00AC Analog Comparator 2
44 28 0x0000.00B0 System Control
45 29 0x0000.00B4 Flash Memory Control
46 30 0x0000.00B8 GPIO Port F
47 31 0x0000.00BC GPIO Port G
48 32 0x0000.00C0 GPIO Port H
49 33 0x0000.00C4 UART2
50 34 0x0000.00C8 SSI1
51 35 0x0000.00CC 16/32-Bit Timer 3A
52 36 0x0000.00D0 16/32-Bit Timer 3B
53 37 0x0000.00D4 I2C1
54 38 0x0000.00D8 CAN 0
55 39 0x0000.00DC CAN1
56 40 0x0000.00E0 Ethernet MAC
57 41 0x0000.00E4 HIB
58 42 0x0000.00E8 USB MAC
59 43 0x0000.00EC PWM Generator 3
60 44 0x0000.00F0 uDMA 0 Software
61 45 0x0000.00F4 uDMA 0 Error
62 46 0x0000.00F8 ADC1 Sequence 0
63 47 0x0000.00FC ADC1 Sequence 1
64 48 0x0000.0100 ADC1 Sequence 2
65 49 0x0000.0104 ADC1 Sequence 3
66 50 0x0000.0108 EPI 0
67 51 0x0000.010C GPIO Port J
68 52 0x0000.0110 GPIO Port K
69 53 0x0000.0114 GPIO Port L
70 54 0x0000.0118 SSI 2
71 55 0x0000.011C SSI 3
72 56 0x0000.0120 UART 3
73 57 0x0000.0124 UART 4
74 58 0x0000.0128 UART 5
75 59 0x0000.012C UART 6
76 60 0x0000.0130 UART 7
77 61 0x0000.0134 I2C 2
78 62 0x0000.0138 I2C 3

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Table 2-9. Interrupts (continued)

Vector Number Interrupt Number (Bit Vector Address or Description
in Interrupt Registers) Offset
79 63 0x0000.013C Timer 4A
80 64 0x0000.0140 Timer 4B
81 65 0x0000.0144 Timer 5A
82 66 0x0000.0148 Timer 5B
83 67 0x0000.014C Floating-Point Exception (imprecise)
84-85 68-69 - Reserved
86 70 0x0000.0158 I2C 4
87 71 0x0000.015C I2C 5
88 72 0x0000.0160 GPIO Port M
89 73 0x0000.0164 GPIO Port N
90 74 - Reserved
91 75 0x0000.016C Tamper
92 76 0x0000.017 GPIO Port P (Summary or P0)
93 77 0x0000.0174 GPIO Port P1
94 78 0x0000.0178 GPIO Port P2
95 79 0x0000.017C GPIO Port P3
96 80 0x0000.0180 GPIO Port P4
97 81 0x0000.0184 GPIO Port P5
98 82 0x0000.0188 GPIO Port P6
99 83 0x0000.018C GPIO Port P7
100 84 0x0000.0190 GPIO Port Q (Summary or Q0)
101 85 0x0000.0194 GPIO Port Q1
102 86 0x0000.0198 GPIO Port Q2
103 87 0x0000.019C GPIO Port Q3
104 88 0x0000.01A0 GPIO Port Q4
105 89 0x0000.01A4 GPIO Port Q5
106 90 0x0000.01A8 GPIO Port Q6
107 91 0x0000.01AC GPIO Port Q7
108-113 92-97 - Reserved
114 98 0x0000.01C8 16/32-Bit Timer 6A
115 99 0x0000.01CC 16/32-Bit Timer 6B
116 100 0x0000.01D0 16/32-Bit Timer 7A
117 101 0x0000.01D4 16/32-Bit Timer 7B
118 102 0x0000.01D8 I2C 6
119 103 0x0000.01DC I2C 7
120-124 104-108 - Reserved
125 109 0x0000.01F4 I2C 8
126 110 0x0000.01F8 I2C 9
127-129 111-113 - Reserved

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2.5.3 Exception Handlers

The processor handles exceptions using:

■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.

■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.

■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.

2.5.4 Vector Table

The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 115. Figure 2-6 on page 119 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code

Figure 2-6. Vector Table

Exception number IRQ number Offset Vector
0x040
(N+16) (N) + 0x(N*4) IRQ N
.
. . .
. . .
. 0x004C .

18 2 0x0048 IRQ2
17 1 0x0044 IRQ1
16 0 0x0040 IRQ0
15 -1 0x003C Systick
14 -2 0x0038 PendSV
13 Reserved
12 Reserved for Debug
11 -5 0x002C SVCall
10
9
Reserved
8
7
6 -10 0x0018 Usage fault

5 -11 0x0014 Bus fault

4 -12 0x0010 Memory management fault

3 -13 0x000C Hard fault

2 -14 0x0008 NMI

1 0x0004 Reset

0 0x0000 Initial SP value

On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different

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memory location, in the range 0x0000.0400 to 0x3FFF.FC00 (see “Vector Table” on page 119). Note
that when configuring the VTABLE register, the offset must be aligned on a 1024-byte boundary.

2.5.5 Exception Priorities

As Table 2-8 on page 115 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 177 and
page 159.
Note: Configurable priority values for the Tiva™ C Series implementation are in the range 0-7.
This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority
values, always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.

2.5.6 Interrupt Priority Grouping

To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:

■ An upper field that defines the group priority

■ A lower field that defines a subpriority within the group

Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 171.

2.5.7 Exception Entry and Return

Descriptions of exception handling use the following terms:

■ Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 120 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 121 more information.

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■ Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 122 for
more information.

■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception

handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.

■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs

during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.

2.5.7.1 Exception Entry

Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 96, FAULTMASK on page 97, and BASEPRI on page 98). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
When using floating-point routines, the Cortex-M4F processor automatically stacks the architected
floating-point state on exception entry. Figure 2-7 on page 122 shows the Cortex-M4F stack frame
layout when floating-point state is preserved on the stack as the result of an interrupt or an exception.
Note: Where stack space for floating-point state is not allocated, the stack frame is the same as
that of ARMv7-M implementations without an FPU. Figure 2-7 on page 122 shows this stack
frame also.

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Figure 2-7. Exception Stack Frame

...
Pre-IRQ top of stack
{aligner}

FPSCR
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1 ...
Pre-IRQ top of stack
S0 {aligner}
xPSR Decreasing xPSR
PC memory PC
address
LR LR
R12 R12
R3 R3
R2 R2
R1 R1
R0 IRQ top of stack R0 IRQ top of stack

Exception frame with Exception frame without

floating-point storage floating-point storage

Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel with the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.

2.5.7.2 Exception Return

Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:

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■ An LDM or POP instruction that loads the PC

■ A BX instruction using any register

■ An LDR instruction with the PC as the destination

EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest five
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 123
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:5 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.

Table 2-10. Exception Return Behavior

EXC_RETURN[31:0] Description
0xFFFF.FFE0 Reserved
0xFFFF.FFE1 Return to Handler mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFE2 - 0xFFFF.FFE8 Reserved
0xFFFF.FFE9 Return to Thread mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFEA - 0xFFFF.FFEC Reserved
0xFFFF.FFED Return to Thread mode.
Exception return uses floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFEE - 0xFFFF.FFF0 Reserved
0xFFFF.FFF1 Return to Handler mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFF2 - 0xFFFF.FFF8 Reserved
0xFFFF.FFF9 Return to Thread mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFFA - 0xFFFF.FFFC Reserved
0xFFFF.FFFD Return to Thread mode.
Exception return uses non-floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFFE - 0xFFFF.FFFF Reserved

2.6 Fault Handling

Faults are a subset of the exceptions (see “Exception Model” on page 113). The following conditions
generate a fault:

■ A bus error on an instruction fetch or vector table load or a data access.

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■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.

■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).

■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.

2.6.1 Fault Types

Table 2-11 on page 124 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 184 for more
information about the fault status registers.

Table 2-11. Faults

Fault Handler Fault Status Register Bit Name
Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT
Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) FORCED
a
MPU or default memory mismatch on Memory management Memory Management Fault Status IERR
instruction access fault (MFAULTSTAT)
MPU or default memory mismatch on Memory management Memory Management Fault Status DERR
data access fault (MFAULTSTAT)
MPU or default memory mismatch on Memory management Memory Management Fault Status MSTKE
exception stacking fault (MFAULTSTAT)
MPU or default memory mismatch on Memory management Memory Management Fault Status MUSTKE
exception unstacking fault (MFAULTSTAT)
MPU or default memory mismatch Memory management Memory Management Fault Status MLSPERR
during lazy floating-point state fault (MFAULTSTAT)
preservation
Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE
Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE
Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS
Bus error during lazy floating-point state Bus fault Bus Fault Status (BFAULTSTAT) BLSPE
preservation
Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE
Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE
Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP
Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF
Attempt to enter an invalid instruction Usage fault Usage Fault Status (UFAULTSTAT) INVSTAT
b
set state
Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC
Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN
Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiply instruction
with ICI continuation.

2.6.2 Fault Escalation and Hard Faults

All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 177). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 180).

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Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 113.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:

■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.

■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.

■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.

■ A fault occurs and the handler for that fault is not enabled.

If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.

2.6.3 Fault Status Registers and Fault Address Registers

The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 125.

Table 2-12. Fault Status and Fault Address Registers

Handler Status Register Name Address Register Name Register Description
Hard fault Hard Fault Status (HFAULTSTAT) - page 190
Memory management Memory Management Fault Status Memory Management Fault page 184
fault (MFAULTSTAT) Address (MMADDR) page 191
Bus fault Bus Fault Status (BFAULTSTAT) Bus Fault Address page 184
(FAULTADDR) page 192
Usage fault Usage Fault Status (UFAULTSTAT) - page 184

2.6.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.

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2.7 Power Management

The Cortex-M4F processor sleep modes reduce power consumption:

■ Sleep mode stops the processor clock.

■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.

The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 173). For more information about the behavior of the sleep modes, see “System
Control” on page 239.
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.

2.7.1 Entering Sleep Modes

This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.

2.7.1.1 Wait for Interrupt

The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 127). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature
number ARM DUI 0553A) for more information.

2.7.1.2 Wait for Event

The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A) for more information.

2.7.1.3 Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.

2.7.2 Wake Up from Sleep Mode

The conditions for the processor to wake up depend on the mechanism that caused it to enter sleep
mode.

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2.7.2.1 Wake Up from WFI or Sleep-on-Exit

Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 96 and page 97.

2.7.2.2 Wake Up from WFE

The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 173.

2.8 Instruction Set Summary

The processor implements a version of the Thumb instruction set. Table 2-13 on page 127 lists the
supported instructions.
Note: In Table 2-13 on page 127:

■ Angle brackets, <>, enclose alternative forms of the operand

■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■ Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix

For more information on the instructions and operands, see the instruction descriptions in
the ARM® Cortex™-M4 Technical Reference Manual.

Table 2-13. Cortex-M4F Instruction Summary

Mnemonic Operands Brief Description Flags
ADC, ADCS {Rd,} Rn, Op2 Add with carry N,Z,C,V
ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V
ADD, ADDW {Rd,} Rn , #imm12 Add -
ADR Rd, label Load PC-relative address -
AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic shift right N,Z,C
B label Branch -
BFC Rd, #lsb, #width Bit field clear -
BFI Rd, Rn, #lsb, #width Bit field insert -
BIC, BICS {Rd,} Rn, Op2 Bit clear N,Z,C
BKPT #imm Breakpoint -
BL label Branch with link -
BLX Rm Branch indirect with link -
BX Rm Branch indirect -
CBNZ Rn, label Compare and branch if non-zero -

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Table 2-13. Cortex-M4F Instruction Summary (continued)

Mnemonic Operands Brief Description Flags
CBZ Rn, label Compare and branch if zero -
CLREX - Clear exclusive -
CLZ Rd, Rm Count leading zeros -
CMN Rn, Op2 Compare negative N,Z,C,V
CMP Rn, Op2 Compare N,Z,C,V
CPSID i Change processor state, disable -
interrupts
CPSIE i Change processor state, enable -
interrupts
DMB - Data memory barrier -
DSB - Data synchronization barrier -
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C
ISB - Instruction synchronization barrier -
IT - If-Then condition block -
LDM Rn{!}, reglist Load multiple registers, increment after -
LDMDB, LDMEA Rn{!}, reglist Load multiple registers, decrement -
before
LDMFD, LDMIA Rn{!}, reglist Load multiple registers, increment after -
LDR Rt, [Rn, #offset] Load register with word -
LDRB, LDRBT Rt, [Rn, #offset] Load register with byte -
LDRD Rt, Rt2, [Rn, #offset] Load register with two bytes -
LDREX Rt, [Rn, #offset] Load register exclusive -
LDREXB Rt, [Rn] Load register exclusive with byte -
LDREXH Rt, [Rn] Load register exclusive with halfword -
LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword -
LDRSB, LDRSBT Rt, [Rn, #offset] Load register with signed byte -
LDRSH, LDRSHT Rt, [Rn, #offset] Load register with signed halfword -
LDRT Rt, [Rn, #offset] Load register with word -
LSL, LSLS Rd, Rm, <Rs|#n> Logical shift left N,Z,C
LSR, LSRS Rd, Rm, <Rs|#n> Logical shift right N,Z,C
MLA Rd, Rn, Rm, Ra Multiply with accumulate, 32-bit result -
MLS Rd, Rn, Rm, Ra Multiply and subtract, 32-bit result -
MOV, MOVS Rd, Op2 Move N,Z,C
MOV, MOVW Rd, #imm16 Move 16-bit constant N,Z,C
MOVT Rd, #imm16 Move top -
MRS Rd, spec_reg Move from special register to general -
register
MSR spec_reg, Rm Move from general register to special N,Z,C,V
register
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z
MVN, MVNS Rd, Op2 Move NOT N,Z,C
NOP - No operation -
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C

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Table 2-13. Cortex-M4F Instruction Summary (continued)

Mnemonic Operands Brief Description Flags
ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C
PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack halfword -
POP reglist Pop registers from stack -
PUSH reglist Push registers onto stack -
QADD {Rd,} Rn, Rm Saturating add Q
QADD16 {Rd,} Rn, Rm Saturating add 16 -
QADD8 {Rd,} Rn, Rm Saturating add 8 -
QASX {Rd,} Rn, Rm Saturating add and subtract with -
exchange
QDADD {Rd,} Rn, Rm Saturating double and add Q
QDSUB {Rd,} Rn, Rm Saturating double and subtract Q
QSAX {Rd,} Rn, Rm Saturating subtract and add with -
exchange
QSUB {Rd,} Rn, Rm Saturating subtract Q
QSUB16 {Rd,} Rn, Rm Saturating subtract 16 -
QSUB8 {Rd,} Rn, Rm Saturating subtract 8 -
RBIT Rd, Rn Reverse bits -
REV Rd, Rn Reverse byte order in a word -
REV16 Rd, Rn Reverse byte order in each halfword -
REVSH Rd, Rn Reverse byte order in bottom halfword -
and sign extend
ROR, RORS Rd, Rm, <Rs|#n> Rotate right N,Z,C
RRX, RRXS Rd, Rm Rotate right with extend N,Z,C
RSB, RSBS {Rd,} Rn, Op2 Reverse subtract N,Z,C,V
SADD16 {Rd,} Rn, Rm Signed add 16 GE
SADD8 {Rd,} Rn, Rm Signed add 8 GE
SASX {Rd,} Rn, Rm Signed add and subtract with exchange GE
SBC, SBCS {Rd,} Rn, Op2 Subtract with carry N,Z,C,V
SBFX Rd, Rn, #lsb, #width Signed bit field extract -
SDIV {Rd,} Rn, Rm Signed divide -
SEL {Rd,} Rn, Rm Select bytes -
SEV - Send event -
SHADD16 {Rd,} Rn, Rm Signed halving add 16 -
SHADD8 {Rd,} Rn, Rm Signed halving add 8 -
SHASX {Rd,} Rn, Rm Signed halving add and subtract with -
exchange
SHSAX {Rd,} Rn, Rm Signed halving add and subtract with -
exchange
SHSUB16 {Rd,} Rn, Rm Signed halving subtract 16 -
SHSUB8 {Rd,} Rn, Rm Signed halving subtract 8 -

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Table 2-13. Cortex-M4F Instruction Summary (continued)

Mnemonic Operands Brief Description Flags
SMLABB, Rd, Rn, Rm, Ra Signed multiply accumulate long Q
SMLABT, (halfwords)

SMLATB,
SMLATT
SMLAD, Rd, Rn, Rm, Ra Signed multiply accumulate dual Q
SMLADX
SMLAL RdLo, RdHi, Rn, Rm Signed multiply with accumulate -
(32x32+64), 64-bit result
SMLALBB, RdLo, RdHi, Rn, Rm Signed multiply accumulate long -
SMLALBT, (halfwords)

SMLALTB,
SMLALTT
SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed multiply accumulate long dual -
SMLAWB,SMLAWT Rd, Rn, Rm, Ra Signed multiply accumulate, word by Q
halfword
SMLSD Rd, Rn, Rm, Ra Signed multiply subtract dual Q
SMLSDX
SMLSLD RdLo, RdHi, Rn, Rm Signed multiply subtract long dual
SMLSLDX
SMMLA Rd, Rn, Rm, Ra Signed most significant word multiply -
accumulate
SMMLS, Rd, Rn, Rm, Ra Signed most significant word multiply -
SMMLR subtract

SMMUL, {Rd,} Rn, Rm Signed most significant word multiply -

SMMULR
SMUAD {Rd,} Rn, Rm Signed dual multiply add Q
SMUADX
SMULBB, {Rd,} Rn, Rm Signed multiply halfwords -
SMULBT,
SMULTB,
SMULTT
SMULL RdLo, RdHi, Rn, Rm Signed multiply (32x32), 64-bit result -
SMULWB, {Rd,} Rn, Rm Signed multiply by halfword -
SMULWT
SMUSD, {Rd,} Rn, Rm Signed dual multiply subtract -
SMUSDX
SSAT Rd, #n, Rm {,shift #s} Signed saturate Q
SSAT16 Rd, #n, Rm Signed saturate 16 Q
SSAX {Rd,} Rn, Rm Saturating subtract and add with GE
exchange
SSUB16 {Rd,} Rn, Rm Signed subtract 16 -
SSUB8 {Rd,} Rn, Rm Signed subtract 8 -
STM Rn{!}, reglist Store multiple registers, increment after -

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Table 2-13. Cortex-M4F Instruction Summary (continued)

Mnemonic Operands Brief Description Flags
STMDB, STMEA Rn{!}, reglist Store multiple registers, decrement -
before
STMFD, STMIA Rn{!}, reglist Store multiple registers, increment after -
STR Rt, [Rn {, #offset}] Store register word -
STRB, STRBT Rt, [Rn {, #offset}] Store register byte -
STRD Rt, Rt2, [Rn {, #offset}] Store register two words -
STREX Rt, Rt, [Rn {, #offset}] Store register exclusive -
STREXB Rd, Rt, [Rn] Store register exclusive byte -
STREXH Rd, Rt, [Rn] Store register exclusive halfword -
STRH, STRHT Rt, [Rn {, #offset}] Store register halfword -
STRSB, STRSBT Rt, [Rn {, #offset}] Store register signed byte -
STRSH, STRSHT Rt, [Rn {, #offset}] Store register signed halfword -
STRT Rt, [Rn {, #offset}] Store register word -
SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V
SUB, SUBW {Rd,} Rn, #imm12 Subtract 12-bit constant N,Z,C,V
SVC #imm Supervisor call -
SXTAB {Rd,} Rn, Rm, {,ROR #} Extend 8 bits to 32 and add -
SXTAB16 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add -
SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add -
SXTB16 {Rd,} Rm {,ROR #n} Signed extend byte 16 -
SXTB {Rd,} Rm {,ROR #n} Sign extend a byte -
SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword -
TBB [Rn, Rm] Table branch byte -
TBH [Rn, Rm, LSL #1] Table branch halfword -
TEQ Rn, Op2 Test equivalence N,Z,C
TST Rn, Op2 Test N,Z,C
UADD16 {Rd,} Rn, Rm Unsigned add 16 GE
UADD8 {Rd,} Rn, Rm Unsigned add 8 GE
UASX {Rd,} Rn, Rm Unsigned add and subtract with GE
exchange
UHADD16 {Rd,} Rn, Rm Unsigned halving add 16 -
UHADD8 {Rd,} Rn, Rm Unsigned halving add 8 -
UHASX {Rd,} Rn, Rm Unsigned halving add and subtract with -
exchange
UHSAX {Rd,} Rn, Rm Unsigned halving subtract and add with -
exchange
UHSUB16 {Rd,} Rn, Rm Unsigned halving subtract 16 -
UHSUB8 {Rd,} Rn, Rm Unsigned halving subtract 8 -
UBFX Rd, Rn, #lsb, #width Unsigned bit field extract -
UDIV {Rd,} Rn, Rm Unsigned divide -
UMAAL RdLo, RdHi, Rn, Rm Unsigned multiply accumulate -
accumulate long (32x32+64), 64-bit
result

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Table 2-13. Cortex-M4F Instruction Summary (continued)

Mnemonic Operands Brief Description Flags
UMLAL RdLo, RdHi, Rn, Rm Unsigned multiply with accumulate -
(32x32+32+32), 64-bit result
UMULL RdLo, RdHi, Rn, Rm Unsigned multiply (32x 2), 64-bit result -
UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16 -
UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8 -
UQASX {Rd,} Rn, Rm Unsigned Saturating Add and Subtract -
with Exchange
UQSAX {Rd,} Rn, Rm Unsigned Saturating Subtract and Add -
with Exchange
UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16 -
UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8 -
USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences -
USADA8 {Rd,} Rn, Rm, Ra Unsigned Sum of Absolute Differences -
and Accumulate
USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q
USAT16 Rd, #n, Rm Unsigned Saturate 16 Q
USAX {Rd,} Rn, Rm Unsigned Subtract and add with GE
Exchange
USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE
USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE
UXTAB {Rd,} Rn, Rm, {,ROR #} Rotate, extend 8 bits to 32 and Add -
UXTAB16 {Rd,} Rn, Rm, {,ROR #} Rotate, dual extend 8 bits to 16 and Add -
UXTAH {Rd,} Rn, Rm, {,ROR #} Rotate, unsigned extend and Add -
Halfword
UXTB {Rd,} Rm, {,ROR #n} Zero extend a Byte -
UXTB16 {Rd,} Rm, {,ROR #n} Unsigned Extend Byte 16 -
UXTH {Rd,} Rm, {,ROR #n} Zero extend a Halfword -
VABS.F32 Sd, Sm Floating-point Absolute -
VADD.F32 {Sd,} Sn, Sm Floating-point Add -
VCMP.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or FPSCR
one floating-point register and zero
VCMPE.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or FPSCR
one floating-point register and zero with
Invalid Operation check
VCVT.S32.F32 Sd, Sm Convert between floating-point and -
integer
VCVT.S16.F32 Sd, Sd, #fbits Convert between floating-point and fixed -
point
VCVTR.S32.F32 Sd, Sm Convert between floating-point and -
integer with rounding
VCVT<B|H>.F32.F16 Sd, Sm Converts half-precision value to -
single-precision
VCVTT<B|T>.F32.F16 Sd, Sm Converts single-precision register to -
half-precision
VDIV.F32 {Sd,} Sn, Sm Floating-point Divide -
VFMA.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate -

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Table 2-13. Cortex-M4F Instruction Summary (continued)

Mnemonic Operands Brief Description Flags
VFNMA.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply -
Accumulate
VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract -
VFNMS.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply -
Subtract
VLDM.F<32|64> Rn{!}, list Load Multiple extension registers -
VLDR.F<32|64> <Dd|Sd>, [Rn] Load an extension register from memory -
VLMA.F32 {Sd,} Sn, Sm Floating-point Multiply Accumulate -
VLMS.F32 {Sd,} Sn, Sm Floating-point Multiply Subtract -
VMOV.F32 Sd, #imm Floating-point Move immediate -
VMOV Sd, Sm Floating-point Move register -
VMOV Sn, Rt Copy ARM core register to single -
precision
VMOV Sm, Sm1, Rt, Rt2 Copy 2 ARM core registers to 2 single -
precision
VMOV Dd[x], Rt Copy ARM core register to scalar -
VMOV Rt, Dn[x] Copy scalar to ARM core register -
VMRS Rt, FPSCR Move FPSCR to ARM core register or N,Z,C,V
APSR
VMSR FPSCR, Rt Move to FPSCR from ARM Core register FPSCR
VMUL.F32 {Sd,} Sn, Sm Floating-point Multiply -
VNEG.F32 Sd, Sm Floating-point Negate -
VNMLA.F32 {Sd,} Sn, Sm Floating-point Multiply and Add -
VNMLS.F32 {Sd,} Sn, Sm Floating-point Multiply and Subtract -
VNMUL {Sd,} Sn, Sm Floating-point Multiply -
VPOP list Pop extension registers -
VPUSH list Push extension registers -
VSQRT.F32 Sd, Sm Calculates floating-point Square Root -
VSTM Rn{!}, list Floating-point register Store Multiple -
VSTR.F3<32|64> Sd, [Rn] Stores an extension register to memory -
VSUB.F<32|64> {Sd,} Sn, Sm Floating-point Subtract -
WFE - Wait for event -
WFI - Wait for interrupt -

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3 Cortex-M4 Peripherals
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals, including:

■ SysTick (see page 135)

Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.

■ Nested Vectored Interrupt Controller (NVIC) (see page 136)

– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers

■ System Control Block (SCB) (see page 137)

Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.

■ Memory Protection Unit (MPU) (see page 137)

Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.

■ Floating-Point Unit (FPU) (see page 142)

Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.

Table 3-1 on page 134 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.

Table 3-1. Core Peripheral Register Regions

Address Core Peripheral Description (see page ...)
0xE000.E010-0xE000.E01F System Timer 135
0xE000.E100-0xE000.E4EF Nested Vectored Interrupt Controller 136
0xE000.EF00-0xE000.EF03
0xE000.E008-0xE000.E00F System Control Block 137
0xE000.ED00-0xE000.ED3F
0xE000.ED90-0xE000.EDB8 Memory Protection Unit 137
0xE000.EF30-0xE000.EF44 Floating Point Unit 142

3.1 Functional Description

This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals: SysTick, NVIC, SCB, MPU, FPU.

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3.1.1 System Timer (SysTick)

Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:

■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.

■ A high-speed alarm timer using the system clock.

■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.

■ A simple counter used to measure time to completion and time used.

■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.

The timer consists of three registers:

■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.

■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.

■ SysTick Current Value (STCURRENT): The current value of the counter.

When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode,
the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick
registers.
The SysTick counter reload and current value are undefined at reset; the correct initialization
sequence for the SysTick counter is:

1. Program the value in the STRELOAD register.

2. Clear the STCURRENT register by writing to it with any value.

3. Configure the STCTRL register for the required operation.

Note: When the processor is halted for debugging, the counter does not decrement.

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3.1.2 Nested Vectored Interrupt Controller (NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:

■ 106 interrupts.

■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.

■ Low-latency exception and interrupt handling.

■ Level and pulse detection of interrupt signals.

■ Dynamic reprioritization of interrupts.

■ Grouping of priority values into group priority and subpriority fields.

■ Interrupt tail-chaining.

■ An external Non-maskable interrupt (NMI).

The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.

3.1.2.1 Level-Sensitive and Pulse Interrupts

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 136 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.

3.1.2.2 Hardware and Software Control of Interrupts

The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:

■ The NVIC detects that the interrupt signal is High and the interrupt is not active.

■ The NVIC detects a rising edge on the interrupt signal.

■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 156 or SWTRIG on page 163.

A pending interrupt remains pending until one of the following:

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■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:

– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.

– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.

■ Software writes to the corresponding interrupt clear-pending register bit

– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.

– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.

3.1.3 System Control Block (SCB)

The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.

3.1.4 Memory Protection Unit (MPU)

This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 106 for more information).

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Table 3-2 on page 138 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Tiva™ C Series Microcontroller” on page 142 for guidelines for programming a
microcontroller implementation.

Table 3-2. Memory Attributes Summary

Memory Type Description
Strongly Ordered All accesses to Strongly Ordered memory occur in program order.
Device Memory-mapped peripherals
Normal Normal memory

To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:

■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.

■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.

The processor does not support unaligned accesses to MPU registers.

When setting up the MPU, and if the MPU has previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.

3.1.4.1 Updating an MPU Region

To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.

Updating an MPU Region Using Separate Words

This example simple code configures one region:

; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute

Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:

; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register

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STR R1, [R0, #0x0] ; Region Number

BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable

Software must use memory barrier instructions:

■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.

■ After MPU setup, if it includes memory transfers that must use the new MPU settings.

However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.

Updating an MPU Region Using Multi-Word Writes

The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:

; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable

An STM instruction can be used to optimize this:

; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region number, address, attribute, size and enable

This operation can be done in two words for prepacked information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 197) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:

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; R1 = address and region number in one

; R2 = size and attributes in one
LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable

Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 199) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.

Example of SRD Use

Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 140 shows.

Figure 3-1. SRD Use Example

Region 2, with Offset from
subregions base address
512KB
448KB
384KB
320KB
256KB
Region 1 192KB
128KB
Disabled subregion
64KB
Disabled subregion
Base address of both regions 0

3.1.4.2 MPU Access Permission Attributes

The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 140 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M4 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Tiva™ C Series Microcontroller” on page 142 for information on programming the MPU for
TM4C1294NCPDT implementations.

Table 3-3. TEX, S, C, and B Bit Field Encoding

TEX S C B Memory Type Shareability Other Attributes
a
000b x 0 0 Strongly Ordered Shareable -
a
000 x 0 1 Device Shareable -

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Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)

TEX S C B Memory Type Shareability Other Attributes
000 0 1 0 Normal Not shareable
000 1 1 0 Normal Shareable Outer and inner
write-through. No write
000 0 1 1 Normal Not shareable allocate.
000 1 1 1 Normal Shareable
001 0 0 0 Normal Not shareable Outer and inner
001 1 0 0 Normal Shareable non-cacheable.
a
001 x 0 1 Reserved encoding - -
a
001 x 1 0 Reserved encoding - -
001 0 1 1 Normal Not shareable Outer and inner
write-back. Write and
001 1 1 1 Normal Shareable
read allocate.
a
010 x 0 0 Device Not shareable Nonshared Device.
a
010 x 0 1 Reserved encoding - -
a a
010 x 1 x Reserved encoding - -
1BB 0 A A Normal Not shareable Cached memory (BB =
outer policy, AA = inner
1BB 1 A A Normal Shareable
policy).
See Table 3-4 for the
encoding of the AA and
BB bits.
a. The MPU ignores the value of this bit.

Table 3-4 on page 141 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.

Table 3-4. Cache Policy for Memory Attribute Encoding

Encoding, AA or BB Corresponding Cache Policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate

Table 3-5 on page 141 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.

Table 3-5. AP Bit Field Encoding

AP Bit Field Privileged Unprivileged Description
Permissions Permissions
000 No access No access All accesses generate a permission fault.
001 RW No access Access from privileged software only.
010 RW RO Writes by unprivileged software generate a
permission fault.
011 RW RW Full access.
100 Unpredictable Unpredictable Reserved.
101 RO No access Reads by privileged software only.

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Table 3-5. AP Bit Field Encoding (continued)

AP Bit Field Privileged Unprivileged Description
Permissions Permissions
110 RO RO Read-only, by privileged or unprivileged software.
111 RO RO Read-only, by privileged or unprivileged software.

MPU Configuration for a Tiva™ C Series Microcontroller

Tiva™ C Series microcontrollers have only a single processor and no caches. As a result, the MPU
should be programmed as shown in Table 3-6 on page 142.

Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers

Memory Region TEX S C B Memory Type and Attributes
Flash memory 000b 0 1 0 Normal memory, non-shareable, write-through
Internal SRAM 000b 1 1 0 Normal memory, shareable, write-through
External SRAM 000b 1 1 1 Normal memory, shareable, write-back,
write-allocate
Peripherals 000b 1 0 1 Device memory, shareable

In current Tiva™ C Series microcontroller implementations, the shareability and cache policy
attributes do not affect the system behavior. However, using these settings for the MPU regions
can make the application code more portable. The values given are for typical situations.

3.1.4.3 MPU Mismatch

When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 103 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 184 for more information.

3.1.5 Floating-Point Unit (FPU)

This section describes the Floating-Point Unit (FPU) and the registers it uses. The FPU provides:

■ 32-bit instructions for single-precision (C float) data-processing operations

■ Combined multiply and accumulate instructions for increased precision (Fused MAC)

■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root

■ Hardware support for denormals and all IEEE rounding modes

■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers

■ Decoupled three stage pipeline

The Cortex-M4F FPU fully supports single-precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between fixed-point and
floating-point data formats, and floating-point constant instructions. The FPU provides floating-point
computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for
Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU's single-precision
extension registers can also be accessed as 16 doubleword registers for load, store, and move
operations.

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3.1.5.1 FPU Views of the Register Bank

The FPU provides an extension register file containing 32 single-precision registers. These can be
viewed as:

■ Sixteen 64-bit doubleword registers, D0-D15

■ Thirty-two 32-bit single-word registers, S0-S31

■ A combination of registers from the above views

Figure 3-2. FPU Register Bank

S0
D0
S1
S2
D1
S3
S4
D2
S5
S6
D3
S7

... ...

S28
D14
S29
S30
D15
S31

The mapping between the registers is as follows:

■ S<2n> maps to the least significant half of D<n>

■ S<2n+1> maps to the most significant half of D<n>

For example, you can access the least significant half of the value in D6 by accessing S12, and the
most significant half of the elements by accessing S13.

3.1.5.2 Modes of Operation

The FPU provides three modes of operation to accommodate a variety of applications.
Full-Compliance mode. In Full-Compliance mode, the FPU processes all operations according to
the IEEE 754 standard in hardware.
Flush-to-Zero mode. Setting the FZ bit of the Floating-Point Status and Control (FPSC) register
enables Flush-to-Zero mode. In this mode, the FPU treats all subnormal input operands of arithmetic
CDP operations as zeros in the operation. Exceptions that result from a zero operand are signalled
appropriately. VABS, VNEG, and VMOV are not considered arithmetic CDP operations and are not
affected by Flush-to-Zero mode. A result that is tiny, as described in the IEEE 754 standard, where
the destination precision is smaller in magnitude than the minimum normal value before rounding,
is replaced with a zero. The IDC bit in FPSC indicates when an input flush occurs. The UFC bit in
FPSC indicates when a result flush occurs.
Default NaN mode. Setting the DN bit in the FPSC register enables default NaN mode. In this mode,
the result of any arithmetic data processing operation that involves an input NaN, or that generates
a NaN result, returns the default NaN. Propagation of the fraction bits is maintained only by VABS,

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VNEG, and VMOV operations. All other CDP operations ignore any information in the fraction bits
of an input NaN.

3.1.5.3 Compliance with the IEEE 754 standard

When Default NaN (DN) and Flush-to-Zero (FZ) modes are disabled, FPv4 functionality is compliant
with the IEEE 754 standard in hardware. No support code is required to achieve this compliance.

3.1.5.4 Complete Implementation of the IEEE 754 standard

The Cortex-M4F floating point instruction set does not support all operations defined in the IEEE
754-2008 standard. Unsupported operations include, but are not limited to the following:

■ Remainder

■ Round floating-point number to integer-valued floating-point number

■ Binary-to-decimal conversions

■ Decimal-to-binary conversions

■ Direct comparison of single-precision and double-precision values

The Cortex-M4 FPU supports fused MAC operations as described in the IEEE standard. For complete
implementation of the IEEE 754-2008 standard, floating-point functionality must be augmented with
library functions.

3.1.5.5 IEEE 754 standard implementation choices

NaN handling
All single-precision values with the maximum exponent field value and a nonzero fraction field are
valid NaNs. A most-significant fraction bit of zero indicates a Signaling NaN (SNaN). A one indicates
a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. The
below table shows the default NaN values.

Sign Fraction Fraction

0 0xFF bit [22] = 1, bits [21:0] are all zeros

Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows:

■ In full-compliance mode, NaNs are handled as described in the ARM Architecture Reference
Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For data
transfer operations, NaNs are transferred without raising the Invalid Operation exception. For
the non-arithmetic CDP instructions, VABS, VNEG, and VMOV, NaNs are copied, with a change
of sign if specified in the instructions, without causing the Invalid Operation exception.

■ In default NaN mode, arithmetic CDP instructions involving NaN operands return the default
NaN regardless of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation
set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions
is the same as in full-compliance mode.

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Table 3-7. QNaN and SNaN Handling

Instruction Type Default NaN With QNaN Operand With SNaN Operand
Mode
a
Off The QNaN or one of the QNaN operands, IOC set. The SNaN is quieted and the
if there is more than one, is returned result NaN is determined by the rules
Arithmetic CDP according to the rules given in the ARM given in the ARM Architecture Reference
Architecture Reference Manual. Manual.
a
On Default NaN returns. IOC set. Default NaN returns.
Non-arithmetic CDP Off/On NaN passes to destination with sign changed as appropriate.
FCMP(Z) - Unordered compare. IOC set. Unordered compare.
FCMPE(Z) - IOC set. Unordered compare. IOC set. Unordered compare.
Load/store Off/On All NaNs transferred.
a. IOC is the Invalid Operation exception flag, FPSCR[0].

Comparisons
Comparison results modify the flags in the FPSCR. You can use the MVRS APSR_nzcv instruction
(formerly FMSTAT) to transfer the current flags from the FPSCR to the APSR. See the ARM
Architecture Reference Manual for mapping of IEEE 754-2008 standard predicates to ARM conditions.
The flags used are chosen so that subsequent conditional execution of ARM instructions can test
the predicates defined in the IEEE standard.

Underflow
The Cortex-M4F FPU uses the before rounding form of tininess and the inexact result form of loss
of accuracy as described in the IEEE 754-2008 standard to generate Underflow exceptions.
In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE standard, are
flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual
for information on flush-to-zero mode.
When the FPU is not in flush-to-zero mode, operations are performed on subnormal operands. If
the operation does not produce a tiny result, it returns the computed result, and the UFC flag,
FPSCR[3], is not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation
produces a tiny result, the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set
if the result was also inexact.

3.1.5.6 Exceptions
The FPU sets the cumulative exception status flag in the FPSCR register as required for each
instruction, in accordance with the FPv4 architecture. The FPU does not support user-mode traps.
The exception enable bits in the FPSCR read-as-zero, and writes are ignored. The processor also
has six output pins, FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect the
status of one of the cumulative exception flags. For a description of these outputs, see the ARM
Cortex-M4 Integration and Implementation Manual (ARM DII 0239, available from ARM).
The processor can reduce the exception latency by using lazy stacking. See Auxiliary Control
Register, ACTLR on page 4-5. This means that the processor reserves space on the stack for the
FP state, but does not save that state information to the stack. See the ARMv7-M Architecture
Reference Manual (available from ARM) for more information.

3.1.5.7 Enabling the FPU

The FPU is disabled from reset. You must enable it before you can use any floating-point instructions.
The processor must be in privileged mode to read from and write to the Coprocessor Access

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Control (CPAC) register. The below example code sequence enables the FPU in both privileged
and user modes.

; CPACR is located at address 0xE000ED88

LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
STR R1, [R0]; wait for store to complete
DSB
;reset pipeline now the FPU is enabled
ISB

3.2 Register Map

Table 3-8 on page 146 lists the Cortex-M4 Peripheral SysTick, NVIC, MPU, FPU and SCB registers.
The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.

Table 3-8. Peripherals Register Map

See
Offset Name Type Reset Description
page

System Timer (SysTick) Registers

0x010 STCTRL RW 0x0000.0000 SysTick Control and Status Register 150

0x014 STRELOAD RW - SysTick Reload Value Register 152

0x018 STCURRENT RWC - SysTick Current Value Register 153

Nested Vectored Interrupt Controller (NVIC) Registers

0x100 EN0 RW 0x0000.0000 Interrupt 0-31 Set Enable 154

0x104 EN1 RW 0x0000.0000 Interrupt 32-63 Set Enable 154

0x108 EN2 RW 0x0000.0000 Interrupt 64-95 Set Enable 154

0x10C EN3 RW 0x0000.0000 Interrupt 96-113 Set Enable 154

0x180 DIS0 RW 0x0000.0000 Interrupt 0-31 Clear Enable 155

0x184 DIS1 RW 0x0000.0000 Interrupt 32-63 Clear Enable 155

0x188 DIS2 RW 0x0000.0000 Interrupt 64-95 Clear Enable 155

0x18C DIS3 RW 0x0000.0000 Interrupt 96-113 Clear Enable 155

0x200 PEND0 RW 0x0000.0000 Interrupt 0-31 Set Pending 156

0x204 PEND1 RW 0x0000.0000 Interrupt 32-63 Set Pending 156

0x208 PEND2 RW 0x0000.0000 Interrupt 64-95 Set Pending 156

0x20C PEND3 RW 0x0000.0000 Interrupt 96-113 Set Pending 156

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Table 3-8. Peripherals Register Map (continued)

See
Offset Name Type Reset Description
page

0x280 UNPEND0 RW 0x0000.0000 Interrupt 0-31 Clear Pending 157

0x284 UNPEND1 RW 0x0000.0000 Interrupt 32-63 Clear Pending 157

0x288 UNPEND2 RW 0x0000.0000 Interrupt 64-95 Clear Pending 157

0x28C UNPEND3 RW 0x0000.0000 Interrupt 96-113 Clear Pending 157

0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0-31 Active Bit 158

0x304 ACTIVE1 RO 0x0000.0000 Interrupt 32-63 Active Bit 158

0x308 ACTIVE2 RO 0x0000.0000 Interrupt 64-95 Active Bit 158

0x30C ACTIVE3 RO 0x0000.0000 Interrupt 96-127 Active Bit 158

0x400 PRI0 RW 0x0000.0000 Interrupt 0-3 Priority 159

0x404 PRI1 RW 0x0000.0000 Interrupt 4-7 Priority 159

0x408 PRI2 RW 0x0000.0000 Interrupt 8-11 Priority 159

0x40C PRI3 RW 0x0000.0000 Interrupt 12-15 Priority 159

0x410 PRI4 RW 0x0000.0000 Interrupt 16-19 Priority 159

0x414 PRI5 RW 0x0000.0000 Interrupt 20-23 Priority 159

0x418 PRI6 RW 0x0000.0000 Interrupt 24-27 Priority 159

0x41C PRI7 RW 0x0000.0000 Interrupt 28-31 Priority 159

0x420 PRI8 RW 0x0000.0000 Interrupt 32-35 Priority 159

0x424 PRI9 RW 0x0000.0000 Interrupt 36-39 Priority 159

0x428 PRI10 RW 0x0000.0000 Interrupt 40-43 Priority 159

0x42C PRI11 RW 0x0000.0000 Interrupt 44-47 Priority 159

0x430 PRI12 RW 0x0000.0000 Interrupt 48-51 Priority 159

0x434 PRI13 RW 0x0000.0000 Interrupt 52-55 Priority 159

0x438 PRI14 RW 0x0000.0000 Interrupt 56-59 Priority 159

0x43C PRI15 RW 0x0000.0000 Interrupt 60-63 Priority 159

0x440 PRI16 RW 0x0000.0000 Interrupt 64-67 Priority 161

0x444 PRI17 RW 0x0000.0000 Interrupt 68-71 Priority 161

0x448 PRI18 RW 0x0000.0000 Interrupt 72-75 Priority 161

0x44C PRI19 RW 0x0000.0000 Interrupt 76-79 Priority 161

0x450 PRI20 RW 0x0000.0000 Interrupt 80-83 Priority 161

0x454 PRI21 RW 0x0000.0000 Interrupt 84-87 Priority 161

0x458 PRI22 RW 0x0000.0000 Interrupt 88-91 Priority 161

0x45C PRI23 RW 0x0000.0000 Interrupt 92-95 Priority 161

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Table 3-8. Peripherals Register Map (continued)

See
Offset Name Type Reset Description
page

0x460 PRI24 RW 0x0000.0000 Interrupt 96-99 Priority 161

0x464 PRI25 RW 0x0000.0000 Interrupt 100-103 Priority 161

0x468 PRI26 RW 0x0000.0000 Interrupt 104-107 Priority 161

0x46C PRI27 RW 0x0000.0000 Interrupt 108-111 Priority 161

0x470 PRI28 RW 0x0000.0000 Interrupt 112-113 Priority 161

0xF00 SWTRIG WO 0x0000.0000 Software Trigger Interrupt 163

System Control Block (SCB) Registers

0x008 ACTLR RW 0x0000.0000 Auxiliary Control 164

0xD00 CPUID RO 0x410F.C241 CPU ID Base 166

0xD04 INTCTRL RW 0x0000.0000 Interrupt Control and State 167

0xD08 VTABLE RW 0x0000.0000 Vector Table Offset 170

0xD0C APINT RW 0xFA05.0000 Application Interrupt and Reset Control 171

0xD10 SYSCTRL RW 0x0000.0000 System Control 173

0xD14 CFGCTRL RW 0x0000.0200 Configuration and Control 175

0xD18 SYSPRI1 RW 0x0000.0000 System Handler Priority 1 177

0xD1C SYSPRI2 RW 0x0000.0000 System Handler Priority 2 178

0xD20 SYSPRI3 RW 0x0000.0000 System Handler Priority 3 179

0xD24 SYSHNDCTRL RW 0x0000.0000 System Handler Control and State 180

0xD28 FAULTSTAT RW1C 0x0000.0000 Configurable Fault Status 184

0xD2C HFAULTSTAT RW1C 0x0000.0000 Hard Fault Status 190

0xD34 MMADDR RW - Memory Management Fault Address 191

0xD38 FAULTADDR RW - Bus Fault Address 192

Memory Protection Unit (MPU) Registers

0xD90 MPUTYPE RO 0x0000.0800 MPU Type 193

0xD94 MPUCTRL RW 0x0000.0000 MPU Control 194

0xD98 MPUNUMBER RW 0x0000.0000 MPU Region Number 196

0xD9C MPUBASE RW 0x0000.0000 MPU Region Base Address 197

0xDA0 MPUATTR RW 0x0000.0000 MPU Region Attribute and Size 199

0xDA4 MPUBASE1 RW 0x0000.0000 MPU Region Base Address Alias 1 197

0xDA8 MPUATTR1 RW 0x0000.0000 MPU Region Attribute and Size Alias 1 199

0xDAC MPUBASE2 RW 0x0000.0000 MPU Region Base Address Alias 2 197

0xDB0 MPUATTR2 RW 0x0000.0000 MPU Region Attribute and Size Alias 2 199

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Table 3-8. Peripherals Register Map (continued)

See
Offset Name Type Reset Description
page

0xDB4 MPUBASE3 RW 0x0000.0000 MPU Region Base Address Alias 3 197

0xDB8 MPUATTR3 RW 0x0000.0000 MPU Region Attribute and Size Alias 3 199

Floating-Point Unit (FPU) Registers

0xD88 CPAC RW 0x0000.0000 Coprocessor Access Control 202

0xF34 FPCC RW 0xC000.0000 Floating-Point Context Control 203

0xF38 FPCA RW - Floating-Point Context Address 205

0xF3C FPDSC RW 0x0000.0000 Floating-Point Default Status Control 206

3.3 System Timer (SysTick) Register Descriptions

This section lists and describes the System Timer registers, in numerical order by address offset.

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Register 1: SysTick Control and Status Register (STCTRL), offset 0x010

Note: This register can only be accessed from privileged mode.
The SysTick STCTRL register enables the SysTick features.

SysTick Control and Status Register (STCTRL)

Base 0xE000.E000
Offset 0x010
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved COUNT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CLK_SRC INTEN ENABLE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 COUNT RO 0 Count Flag

Value Description
0 The SysTick timer has not counted to 0 since the last time
this bit was read.
1 The SysTick timer has counted to 0 since the last time
this bit was read.

This bit is cleared by a read of the register or if the STCURRENT register

is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise,
the COUNT bit is not changed by the debugger read. See the ARM®
Debug Interface V5 Architecture Specification for more information on
MasterType.

15:3 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 CLK_SRC RW 0 Clock Source

Value Description
0 Precision internal oscillator (PIOSC) divided by 4
1 System clock

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Bit/Field Name Type Reset Description

1 INTEN RW 0 Interrupt Enable

Value Description
0 Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached 0.
1 An interrupt is generated to the NVIC when SysTick counts
to 0.

0 ENABLE RW 0 Enable

Value Description
0 The counter is disabled.
1 Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down.
On reaching 0, the COUNT bit is set and an interrupt is
generated if enabled by INTEN. The counter then loads the
RELOAD value again and begins counting.

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Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014

Note: This register can only be accessed from privileged mode.
The STRELOAD register specifies the start value to load into the SysTick Current Value
(STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and
0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the
COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
Note that in order to access this register correctly, the system clock must be faster than 8 MHz.

SysTick Reload Value Register (STRELOAD)

Base 0xE000.E000
Offset 0x014
Type RW, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved RELOAD

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RELOAD

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:0 RELOAD RW 0x00.0000 Reload Value

Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.

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Register 3: SysTick Current Value Register (STCURRENT), offset 0x018

Note: This register can only be accessed from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.

SysTick Current Value Register (STCURRENT)

Base 0xE000.E000
Offset 0x018
Type RWC, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved CURRENT

Type RO RO RO RO RO RO RO RO RWC RWC RWC RWC RWC RWC RWC RWC

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CURRENT

Type RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:0 CURRENT RWC 0x00.0000 Current Value

This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.

3.4 NVIC Register Descriptions

This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 170.

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Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100

Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104
Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108
Register 7: Interrupt 96-113 Set Enable (EN3), offset 0x10C
Note: This register can only be accessed from privileged mode.
The ENn registers enable interrupts and show which interrupts are enabled. Bit 0 of EN0 corresponds
to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31
corresponds to Interrupt 63. Bit 0 of EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt
95. Bit 0 of EN3 corresponds to Interrupt 96; bit 17 corresponds to Interrupt 113.
See Table 2-9 on page 116 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.

Interrupt 0-31 Set Enable (EN0)

Base 0xE000.E000
Offset 0x100
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT RW 0x0000.0000 Interrupt Enable

Value Description
0 On a read, indicates the interrupt is disabled.
On a write, no effect.
1 On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.

A bit can only be cleared by setting the corresponding INT[n] bit in

the DISn register.

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Register 8: Interrupt 0-31 Clear Enable (DIS0), offset 0x180

Register 9: Interrupt 32-63 Clear Enable (DIS1), offset 0x184
Register 10: Interrupt 64-95 Clear Enable (DIS2), offset 0x188
Register 11: Interrupt 96-113 Clear Enable (DIS3), offset 0x18C
Note: This register can only be accessed from privileged mode.
The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds
to Interrupt 31. Bit 0 of DIS1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of
DIS2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of DIS3 corresponds to
Interrupt 96; .
See Table 2-9 on page 116 for interrupt assignments.

Interrupt 0-31 Clear Enable (DIS0)

Base 0xE000.E000
Offset 0x180
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT RW 0x0000.0000 Interrupt Disable

Value Description
0 On a read, indicates the interrupt is disabled.
On a write, no effect.
1 On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].

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Register 12: Interrupt 0-31 Set Pending (PEND0), offset 0x200

Register 13: Interrupt 32-63 Set Pending (PEND1), offset 0x204
Register 14: Interrupt 64-95 Set Pending (PEND2), offset 0x208
Register 15: Interrupt 96-113 Set Pending (PEND3), offset 0x20C
Note: This register can only be accessed from privileged mode.
The PENDn registers force interrupts into the pending state and show which interrupts are pending.
Bit 0 of PEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of PEND1
corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of PEND2 corresponds to
Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of PEND3 corresponds to Interrupt 96; bit 17
corresponds to interrupt 113.
See Table 2-9 on page 116 for interrupt assignments.

Interrupt 0-31 Set Pending (PEND0)

Base 0xE000.E000
Offset 0x200
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT RW 0x0000.0000 Interrupt Set Pending

Value Description
0 On a read, indicates that the interrupt is not pending.
On a write, no effect.
1 On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.

If the corresponding interrupt is already pending, setting a bit has no

effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.

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Register 16: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280

Register 17: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284
Register 18: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288
Register 19: Interrupt 96-113 Clear Pending (UNPEND3), offset 0x28C
Note: This register can only be accessed from privileged mode.
The UNPENDn registers show which interrupts are pending and remove the pending state from
interrupts. Bit 0 of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of
UNPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2
corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to
Interrupt 96; bit 31 corresponds to Interrupt 113.
See Table 2-9 on page 116 for interrupt assignments.

Interrupt 0-31 Clear Pending (UNPEND0)

Base 0xE000.E000
Offset 0x280
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT RW 0x0000.0000 Interrupt Clear Pending

Value Description
0 On a read, indicates that the interrupt is not pending.
On a write, no effect.
1 On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.

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Register 20: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300

Register 21: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304
Register 22: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308
Register 23: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C
Note: This register can only be accessed from privileged mode.
The UNPENDn registers indicate which interrupts are active. Bit 0 of ACTIVE0 corresponds to
Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of ACTIVE1 corresponds to Interrupt 32; bit 31
corresponds to Interrupt 63. Bit 0 of ACTIVE2 corresponds to Interrupt 64; bit 31 corresponds to
Interrupt 95. Bit 0 of ACTIVE3 corresponds to Interrupt 96; bit 17 corresponds to Interrupt 113.
See Table 2-9 on page 116 for interrupt assignments.

Caution – Do not manually set or clear the bits in this register.

Interrupt 0-31 Active Bit (ACTIVE0)

Base 0xE000.E000
Offset 0x300
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT RO 0x0000.0000 Interrupt Active

Value Description
0 The corresponding interrupt is not active.
1 The corresponding interrupt is active, or active and pending.

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Register 24: Interrupt 0-3 Priority (PRI0), offset 0x400

Register 25: Interrupt 4-7 Priority (PRI1), offset 0x404
Register 26: Interrupt 8-11 Priority (PRI2), offset 0x408
Register 27: Interrupt 12-15 Priority (PRI3), offset 0x40C
Register 28: Interrupt 16-19 Priority (PRI4), offset 0x410
Register 29: Interrupt 20-23 Priority (PRI5), offset 0x414
Register 30: Interrupt 24-27 Priority (PRI6), offset 0x418
Register 31: Interrupt 28-31 Priority (PRI7), offset 0x41C
Register 32: Interrupt 32-35 Priority (PRI8), offset 0x420
Register 33: Interrupt 36-39 Priority (PRI9), offset 0x424
Register 34: Interrupt 40-43 Priority (PRI10), offset 0x428
Register 35: Interrupt 44-47 Priority (PRI11), offset 0x42C
Register 36: Interrupt 48-51 Priority (PRI12), offset 0x430
Register 37: Interrupt 52-55 Priority (PRI13), offset 0x434
Register 38: Interrupt 56-59 Priority (PRI14), offset 0x438
Register 39: Interrupt 60-63 Priority (PRI15), offset 0x43C
Note: This register can only be accessed from privileged mode.
The PRIn registers (see also page 161) provide 3-bit priority fields for each interrupt. These registers
are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows:

PRIn Register Bit Field Interrupt

Bits 31:29 Interrupt [4n+3]
Bits 23:21 Interrupt [4n+2]
Bits 15:13 Interrupt [4n+1]
Bits 7:5 Interrupt [4n]

See Table 2-9 on page 116 for interrupt assignments.

Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 171) indicates the
position of the binary point that splits the priority and subpriority fields.
These registers can only be accessed from privileged mode.

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Interrupt 0-3 Priority (PRI0)

Base 0xE000.E000
Offset 0x400
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INTD reserved INTC reserved

Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTB reserved INTA reserved

Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:29 INTD RW 0x0 Interrupt Priority for Interrupt [4n+3]

This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:21 INTC RW 0x0 Interrupt Priority for Interrupt [4n+2]

This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:13 INTB RW 0x0 Interrupt Priority for Interrupt [4n+1]

This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 INTA RW 0x0 Interrupt Priority for Interrupt [4n]

This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 40: Interrupt 64-67 Priority (PRI16), offset 0x440

Register 41: Interrupt 68-71 Priority (PRI17), offset 0x444
Register 42: Interrupt 72-75 Priority (PRI18), offset 0x448
Register 43: Interrupt 76-79 Priority (PRI19), offset 0x44C
Register 44: Interrupt 80-83 Priority (PRI20), offset 0x450
Register 45: Interrupt 84-87 Priority (PRI21), offset 0x454
Register 46: Interrupt 88-91 Priority (PRI22), offset 0x458
Register 47: Interrupt 92-95 Priority (PRI23), offset 0x45C
Register 48: Interrupt 96-99 Priority (PRI24), offset 0x460
Register 49: Interrupt 100-103 Priority (PRI25), offset 0x464
Register 50: Interrupt 104-107 Priority (PRI26), offset 0x468
Register 51: Interrupt 108-111 Priority (PRI27), offset 0x46C
Register 52: Interrupt 112-113 Priority (PRI28), offset 0x470
Note: This register can only be accessed from privileged mode.
The PRIn registers (see also page 159) provide 3-bit priority fields for each interrupt. These registers
are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows:

PRIn Register Bit Field Interrupt

Bits 31:29 Interrupt [4n+3]
Bits 23:21 Interrupt [4n+2]
Bits 15:13 Interrupt [4n+1]
Bits 7:5 Interrupt [4n]

See Table 2-9 on page 116 for interrupt assignments.

Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 171) indicates the
position of the binary point that splits the priority and subpriority fields .
These registers can only be accessed from privileged mode.
Note: Because the last interrupt vector is number 113, bits [31:16] of the PRI28 register are
reserved.

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Interrupt 64-67 Priority (PRI16)

Base 0xE000.E000
Offset 0x440
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INTD reserved INTC reserved

Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTB reserved INTA reserved

Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:29 INTD RW 0x0 Interrupt Priority for Interrupt [4n+3]

This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:21 INTC RW 0x0 Interrupt Priority for Interrupt [4n+2]

This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:13 INTB RW 0x0 Interrupt Priority for Interrupt [4n+1]

This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 INTA RW 0x0 Interrupt Priority for Interrupt [4n]

This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 53: Software Trigger Interrupt (SWTRIG), offset 0xF00

Note: Only privileged software can enable unprivileged access to the SWTRIG register.
Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI).
See Table 2-9 on page 116 for interrupt assignments.
When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 175) is
set, unprivileged software can access the SWTRIG register.

Software Trigger Interrupt (SWTRIG)

Base 0xE000.E000
Offset 0xF00
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved INTID

Type RO RO RO RO RO RO RO RO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 INTID WO 0x00 Interrupt ID

This field holds the interrupt ID of the required SGI. For example, a value
of 0x3 generates an interrupt on IRQ3.

3.5 System Control Block (SCB) Register Descriptions

This section lists and describes the System Control Block (SCB) registers, in numerical order by
address offset. The SCB registers can only be accessed from privileged mode.
All registers must be accessed with aligned word accesses except for the FAULTSTAT and
SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to system control block registers.

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Register 54: Auxiliary Control (ACTLR), offset 0x008

Note: This register can only be accessed from privileged mode.
The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default
memory map, and interruption of multi-cycle instructions. By default, this register is set to provide
optimum performance from the Cortex-M4 processor and does not normally require modification.

Auxiliary Control (ACTLR)

Base 0xE000.E000
Offset 0x008
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DISOOFP DISFPCA reserved DISFOLD DISWBUF DISMCYC

Type RO RO RO RO RO RO RW RW RO RO RO RO RO RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 DISOOFP RW 0 Disable Out-Of-Order Floating Point

Disables floating-point instructions completing out of order with respect
to integer instructions.

8 DISFPCA RW 0 Disable CONTROL.FPCA

Disable automatic update of the FPCA bit in the CONTROL register.

Important: Two bits control when FPCA can be enabled: the ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the DISFPCA bit in the Auxiliary Control
(ACTLR) register.

7:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 DISFOLD RW 0 Disable IT Folding

Value Description
0 No effect.
1 Disables IT folding.

In some situations, the processor can start executing the first instruction
in an IT block while it is still executing the IT instruction. This behavior
is called IT folding, and improves performance, However, IT folding can
cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit
before executing the task, to disable IT folding.

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Bit/Field Name Type Reset Description

1 DISWBUF RW 0 Disable Write Buffer

Value Description
0 No effect.
1 Disables write buffer use during default memory map accesses.
In this situation, all bus faults are precise bus faults but
performance is decreased because any store to memory must
complete before the processor can execute the next instruction.

Note: This bit only affects write buffers implemented in the

Cortex-M4 processor.

0 DISMCYC RW 0 Disable Interrupts of Multiple Cycle Instructions

Value Description
0 No effect.
1 Disables interruption of load multiple and store multiple
instructions. In this situation, the interrupt latency of the
processor is increased because any LDM or STM must complete
before the processor can stack the current state and enter the
interrupt handler.

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Register 55: CPU ID Base (CPUID), offset 0xD00

Note: This register can only be accessed from privileged mode.
The CPUID register contains the ARM® Cortex™-M4 processor part number, version, and
implementation information.

CPU ID Base (CPUID)

Base 0xE000.E000
Offset 0xD00
Type RO, reset 0x410F.C241
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IMP VAR CON

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PARTNO REV

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:24 IMP RO 0x41 Implementer Code

Value Description
0x41 ARM

23:20 VAR RO 0x0 Variant Number

Value Description
0x0 The rn value in the rnpn product revision identifier, for example,
the 0 in r0p0.

19:16 CON RO 0xF Constant

Value Description
0xF Always reads as 0xF.

15:4 PARTNO RO 0xC24 Part Number

Value Description
0xC24 Cortex-M4 processor.

3:0 REV RO 0x1 Revision Number

Value Description
0x1 The pn value in the rnpn product revision identifier, for example,
the 1 in r0p1.

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Register 56: Interrupt Control and State (INTCTRL), offset 0xD04

Note: This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.

Interrupt Control and State (INTCTRL)

Base 0xE000.E000
Offset 0xD04
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NMISET reserved PENDSV UNPENDSV PENDSTSET PENDSTCLR reserved ISRPRE ISRPEND reserved VECPEND

Type RW RO RO RW WO RW WO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VECPEND RETBASE reserved VECACT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 NMISET RW 0 NMI Set Pending

Value Description
0 On a read, indicates an NMI exception is not pending.
On a write, no effect.
1 On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.

Because NMI is the highest-priority exception, normally the processor

enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.

30:29 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

28 PENDSV RW 0 PendSV Set Pending

Value Description
0 On a read, indicates a PendSV exception is not pending.
On a write, no effect.
1 On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.

Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.

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Bit/Field Name Type Reset Description

27 UNPENDSV WO 0 PendSV Clear Pending

Value Description
0 On a write, no effect.
1 On a write, removes the pending state from the PendSV
exception.

This bit is write only; on a register read, its value is unknown.

26 PENDSTSET RW 0 SysTick Set Pending

Value Description
0 On a read, indicates a SysTick exception is not pending.
On a write, no effect.
1 On a read, indicates a SysTick exception is pending.
On a write, changes the SysTick exception state to pending.

This bit is cleared by writing a 1 to the PENDSTCLR bit.

25 PENDSTCLR WO 0 SysTick Clear Pending

Value Description
0 On a write, no effect.
1 On a write, removes the pending state from the SysTick
exception.

This bit is write only; on a register read, its value is unknown.

24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23 ISRPRE RO 0 Debug Interrupt Handling

Value Description
0 The release from halt does not take an interrupt.
1 The release from halt takes an interrupt.

This bit is only meaningful in Debug mode and reads as zero when the
processor is not in Debug mode.

22 ISRPEND RO 0 Interrupt Pending

Value Description
0 No interrupt is pending.
1 An interrupt is pending.

This bit provides status for all interrupts excluding NMI and Faults.

21:20 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

19:12 VECPEND RO 0x00 Interrupt Pending Vector Number

This field contains the exception number of the highest priority pending
enabled exception. The value indicated by this field includes the effect
of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.

Value Description
0x00 No exceptions are pending
0x01 Reserved
0x02 NMI
0x03 Hard fault
0x04 Memory management fault
0x05 Bus fault
0x06 Usage fault
0x07-0x0A Reserved
0x0B SVCall
0x0C Reserved for Debug
0x0D Reserved
0x0E PendSV
0x0F SysTick
0x10 Interrupt Vector 0
0x11 Interrupt Vector 1
... ...
0xD9 Interrupt Vector 199

11 RETBASE RO 0 Return to Base

Value Description
0 There are preempted active exceptions to execute.
1 There are no active exceptions, or the currently executing
exception is the only active exception.

This bit provides status for all interrupts excluding NMI and Faults. This
bit only has meaning if the processor is currently executing an ISR (the
Interrupt Program Status (IPSR) register is non-zero).

10:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 VECACT RO 0x00 Interrupt Pending Vector Number

This field contains the active exception number. The exception numbers
can be found in the description for the VECPEND field. If this field is clear,
the processor is in Thread mode. This field contains the same value as
the ISRNUM field in the IPSR register.
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn),
Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn),
and Interrupt Priority (PRIn) registers (see page 92).

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Register 57: Vector Table Offset (VTABLE), offset 0xD08

Note: This register can only be accessed from privileged mode.
The VTABLE register indicates the offset of the vector table base address from memory address
0x0000.0000.

Vector Table Offset (VTABLE)

Base 0xE000.E000
Offset 0xD08
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OFFSET

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OFFSET reserved

Type RW RW RW RW RW RW RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 OFFSET RW 0x000.00 Vector Table Offset

When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 112
interrupts, the offset must be aligned on a 1024-byte boundary.

9:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 58: Application Interrupt and Reset Control (APINT), offset 0xD0C
Note: This register can only be accessed from privileged mode.
The APINT register provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. To write to this register, 0x05FA must be written to
the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the
Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table
3-9 on page 171 shows how the PRIGROUP value controls this split. The bit numbers in the Group
Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the
INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note: Determining preemption of an exception uses only the group priority field.

Table 3-9. Interrupt Priority Levels

a
PRIGROUP Bit Field Binary Point Group Priority Field Subpriority Field Group Subpriorities
Priorities
0x0 - 0x4 bxxx. [7:5] None 8 1
0x5 bxx.y [7:6] [5] 4 2
0x6 bx.yy [7] [6:5] 2 4
0x7 b.yyy None [7:5] 1 8
a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.

Application Interrupt and Reset Control (APINT)

Base 0xE000.E000
Offset 0xD0C
Type RW, reset 0xFA05.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VECTKEY

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ENDIANESS reserved PRIGROUP reserved SYSRESREQ VECTCLRACT VECTRESET

Type RO RO RO RO RO RW RW RW RO RO RO RO RO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 VECTKEY RW 0xFA05 Register Key

This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this
register. On a read, 0xFA05 is returned.

15 ENDIANESS RO 0 Data Endianess

The Tiva™ C Series implementation uses only little-endian mode so
this is cleared to 0.

14:11 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

10:8 PRIGROUP RW 0x0 Interrupt Priority Grouping

This field determines the split of group priority from subpriority (see
Table 3-9 on page 171 for more information).

7:3 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 SYSRESREQ WO 0 System Reset Request

Value Description
0 No effect.
1 Resets the core and all on-chip peripherals except the Debug
interface.

This bit is automatically cleared during the reset of the core and reads
as 0.

1 VECTCLRACT WO 0 Clear Active NMI / Fault

This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.

0 VECTRESET WO 0 System Reset

This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.

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Register 59: System Control (SYSCTRL), offset 0xD10

Note: This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.

System Control (SYSCTRL)

Base 0xE000.E000
Offset 0xD10
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SEVONPEND reserved SLEEPDEEP SLEEPEXIT reserved

Type RO RO RO RO RO RO RO RO RO RO RO RW RO RW RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:5 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 SEVONPEND RW 0 Wake Up on Pending

Value Description
0 Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
1 Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.

When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 SLEEPDEEP RW 0 Deep Sleep Enable

Value Description
0 Use Sleep mode as the low power mode.
1 Use Deep-sleep mode as the low power mode.

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Bit/Field Name Type Reset Description

1 SLEEPEXIT RW 0 Sleep on ISR Exit

Value Description
0 When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode.
1 When returning from Handler mode to Thread mode, enter sleep
or deep sleep on return from an ISR.

Setting this bit enables an interrupt-driven application to avoid returning

to an empty main application.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 60: Configuration and Control (CFGCTRL), offset 0xD14

Note: This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 163).

Configuration and Control (CFGCTRL)

Base 0xE000.E000
Offset 0xD14
Type RW, reset 0x0000.0200
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved STKALIGN BFHFNMIGN reserved DIV0 UNALIGNED reserved MAINPEND BASETHR

Type RO RO RO RO RO RO RW RW RO RO RO RW RW RO RW RW
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 STKALIGN RW 1 Stack Alignment on Exception Entry

Value Description
0 The stack is 4-byte aligned.
1 The stack is 8-byte aligned.

On exception entry, the processor uses bit 9 of the stacked PSR to

indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.

8 BFHFNMIGN RW 0 Ignore Bus Fault in NMI and Fault

This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.

Value Description
0 Data bus faults caused by load and store instructions cause a
lock-up.
1 Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.

Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.

7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

4 DIV0 RW 0 Trap on Divide by 0

This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.

Value Description
0 Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
1 Trap on divide by 0.

3 UNALIGNED RW 0 Trap on Unaligned Access

Value Description
0 Do not trap on unaligned halfword and word accesses.
1 Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.

Unaligned LDM, STM, LDRD, and STRD instructions always fault

regardless of whether UNALIGNED is set.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 MAINPEND RW 0 Allow Main Interrupt Trigger

Value Description
0 Disables unprivileged software access to the SWTRIG register.
1 Enables unprivileged software access to the SWTRIG register
(see page 163).

0 BASETHR RW 0 Thread State Control

Value Description
0 The processor can enter Thread mode only when no exception
is active.
1 The processor can enter Thread mode from any level under the
control of an EXC_RETURN value (see “Exception
Return” on page 122 for more information).

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Register 61: System Handler Priority 1 (SYSPRI1), offset 0xD18

Note: This register can only be accessed from privileged mode.
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory
management fault exception handlers. This register is byte-accessible.

System Handler Priority 1 (SYSPRI1)

Base 0xE000.E000
Offset 0xD18
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved USAGE reserved

Type RO RO RO RO RO RO RO RO RW RW RW RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUS reserved MEM reserved

Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:21 USAGE RW 0x0 Usage Fault Priority

This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.

20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:13 BUS RW 0x0 Bus Fault Priority

This field configures the priority level of the bus fault. Configurable priority
values are in the range 0-7, with lower values having higher priority.

12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 MEM RW 0x0 Memory Management Fault Priority

This field configures the priority level of the memory management fault.
Configurable priority values are in the range 0-7, with lower values
having higher priority.

4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 62: System Handler Priority 2 (SYSPRI2), offset 0xD1C

Note: This register can only be accessed from privileged mode.
The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is
byte-accessible.

System Handler Priority 2 (SYSPRI2)

Base 0xE000.E000
Offset 0xD1C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SVC reserved

Type RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:29 SVC RW 0x0 SVCall Priority

This field configures the priority level of SVCall. Configurable priority
values are in the range 0-7, with lower values having higher priority.

28:0 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 63: System Handler Priority 3 (SYSPRI3), offset 0xD20

Note: This register can only be accessed from privileged mode.
The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV
handlers. This register is byte-accessible.

System Handler Priority 3 (SYSPRI3)

Base 0xE000.E000
Offset 0xD20
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TICK reserved PENDSV reserved

Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DEBUG reserved

Type RO RO RO RO RO RO RO RO RW RW RW RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:29 TICK RW 0x0 SysTick Exception Priority

This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values
having higher priority.

28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:21 PENDSV RW 0x0 PendSV Priority

This field configures the priority level of PendSV. Configurable priority
values are in the range 0-7, with lower values having higher priority.

20:8 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 DEBUG RW 0x0 Debug Priority

This field configures the priority level of Debug. Configurable priority
values are in the range 0-7, with lower values having higher priority.

4:0 reserved RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 64: System Handler Control and State (SYSHNDCTRL), offset 0xD24
Note: This register can only be accessed from privileged mode.
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the
usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status
of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as
a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS
kernel can write to the active bits to perform a context switch that changes the current exception
type.

Caution – Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure software that writes
to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modified after enabling the system handlers, a
read-modify-write procedure must be used to ensure that only the required bit is modified.

System Handler Control and State (SYSHNDCTRL)

Base 0xE000.E000
Offset 0xD24
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved USAGE BUS MEM

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SVC BUSP MEMP USAGEP TICK PNDSV reserved MON SVCA reserved USGA reserved BUSA MEMA

Type RW RW RW RW RW RW RO RW RW RO RO RO RW RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:19 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

18 USAGE RW 0 Usage Fault Enable

Value Description
0 Disables the usage fault exception.
1 Enables the usage fault exception.

17 BUS RW 0 Bus Fault Enable

Value Description
0 Disables the bus fault exception.
1 Enables the bus fault exception.

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Bit/Field Name Type Reset Description

16 MEM RW 0 Memory Management Fault Enable

Value Description
0 Disables the memory management fault exception.
1 Enables the memory management fault exception.

15 SVC RW 0 SVC Call Pending

Value Description
0 An SVC call exception is not pending.
1 An SVC call exception is pending.

This bit can be modified to change the pending status of the SVC call
exception.

14 BUSP RW 0 Bus Fault Pending

Value Description
0 A bus fault exception is not pending.
1 A bus fault exception is pending.

This bit can be modified to change the pending status of the bus fault
exception.

13 MEMP RW 0 Memory Management Fault Pending

Value Description
0 A memory management fault exception is not pending.
1 A memory management fault exception is pending.

This bit can be modified to change the pending status of the memory
management fault exception.

12 USAGEP RW 0 Usage Fault Pending

Value Description
0 A usage fault exception is not pending.
1 A usage fault exception is pending.

This bit can be modified to change the pending status of the usage fault
exception.

11 TICK RW 0 SysTick Exception Active

Value Description
0 A SysTick exception is not active.
1 A SysTick exception is active.

This bit can be modified to change the active status of the SysTick
exception, however, see the Caution above before setting this bit.

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Bit/Field Name Type Reset Description

10 PNDSV RW 0 PendSV Exception Active

Value Description
0 A PendSV exception is not active.
1 A PendSV exception is active.

This bit can be modified to change the active status of the PendSV
exception, however, see the Caution above before setting this bit.

9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

8 MON RW 0 Debug Monitor Active

Value Description
0 The Debug monitor is not active.
1 The Debug monitor is active.

7 SVCA RW 0 SVC Call Active

Value Description
0 SVC call is not active.
1 SVC call is active.

This bit can be modified to change the active status of the SVC call
exception, however, see the Caution above before setting this bit.

6:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 USGA RW 0 Usage Fault Active

Value Description
0 Usage fault is not active.
1 Usage fault is active.

This bit can be modified to change the active status of the usage fault
exception, however, see the Caution above before setting this bit.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 BUSA RW 0 Bus Fault Active

Value Description
0 Bus fault is not active.
1 Bus fault is active.

This bit can be modified to change the active status of the bus fault
exception, however, see the Caution above before setting this bit.

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Bit/Field Name Type Reset Description

0 MEMA RW 0 Memory Management Fault Active

Value Description
0 Memory management fault is not active.
1 Memory management fault is active.

This bit can be modified to change the active status of the memory
management fault exception, however, see the Caution above before
setting this bit.

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Register 65: Configurable Fault Status (FAULTSTAT), offset 0xD28

Note: This register can only be accessed from privileged mode.
The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage
fault. Each of these functions is assigned to a subregister as follows:

■ Usage Fault Status (UFAULTSTAT), bits 31:16

■ Bus Fault Status (BFAULTSTAT), bits 15:8
■ Memory Management Fault Status (MFAULTSTAT), bits 7:0

FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:

■ The complete FAULTSTAT register, with a word access to offset 0xD28

■ The MFAULTSTAT, with a byte access to offset 0xD28
■ The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
■ The BFAULTSTAT, with a byte access to offset 0xD29
■ The UFAULTSTAT, with a halfword access to offset 0xD2A

Bits are cleared by writing a 1 to them.

In a fault handler, the true faulting address can be determined by:

1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.

2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.

Software must follow this sequence because another higher priority exception might change the
MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMADDR or FAULTADDR value.

Configurable Fault Status (FAULTSTAT)

Base 0xE000.E000
Offset 0xD28
Type RW1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved DIV0 UNALIGN reserved NOCP INVPC INVSTAT UNDEF

Type RO RO RO RO RO RO RW1C RW1C RO RO RO RO RW1C RW1C RW1C RW1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BFARV reserved BLSPERR BSTKE BUSTKE IMPRE PRECISE IBUS MMARV reserved MLSPERR MSTKE MUSTKE reserved DERR IERR

Type RW1C RO RW1C RW1C RW1C RW1C RW1C RW1C RW1C RO RW1C RW1C RW1C RO RW1C RW1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:26 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

25 DIV0 RW1C 0 Divide-by-Zero Usage Fault

Value Description
0 No divide-by-zero fault has occurred, or divide-by-zero trapping
is not enabled.
1 The processor has executed an SDIV or UDIV instruction with
a divisor of 0.

When this bit is set, the PC value stacked for the exception return points
to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register (see page 175).
This bit is cleared by writing a 1 to it.

24 UNALIGN RW1C 0 Unaligned Access Usage Fault

Value Description
0 No unaligned access fault has occurred, or unaligned access
trapping is not enabled.
1 The processor has made an unaligned memory access.

Unaligned LDM, STM, LDRD, and STRD instructions always fault

regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting the UNALIGNED bit
in the CFGCTRL register (see page 175).
This bit is cleared by writing a 1 to it.

23:20 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19 NOCP RW1C 0 No Coprocessor Usage Fault

Value Description
0 A usage fault has not been caused by attempting to access a
coprocessor.
1 The processor has attempted to access a coprocessor.

This bit is cleared by writing a 1 to it.

18 INVPC RW1C 0 Invalid PC Load Usage Fault

Value Description
0 A usage fault has not been caused by attempting to load an
invalid PC value.
1 The processor has attempted an illegal load of EXC_RETURN
to the PC as a result of an invalid context or an invalid
EXC_RETURN value.

When this bit is set, the PC value stacked for the exception return points
to the instruction that tried to perform the illegal load of the PC.
This bit is cleared by writing a 1 to it.

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Bit/Field Name Type Reset Description

17 INVSTAT RW1C 0 Invalid State Usage Fault

Value Description
0 A usage fault has not been caused by an invalid state.
1 The processor has attempted to execute an instruction that
makes illegal use of the EPSR register.

When this bit is set, the PC value stacked for the exception return points
to the instruction that attempted the illegal use of the Execution
Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
This bit is cleared by writing a 1 to it.

16 UNDEF RW1C 0 Undefined Instruction Usage Fault

Value Description
0 A usage fault has not been caused by an undefined instruction.
1 The processor has attempted to execute an undefined
instruction.

When this bit is set, the PC value stacked for the exception return points
to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
This bit is cleared by writing a 1 to it.

15 BFARV RW1C 0 Bus Fault Address Register Valid

Value Description
0 The value in the Bus Fault Address (FAULTADDR) register
is not a valid fault address.
1 The FAULTADDR register is holding a valid fault address.

This bit is set after a bus fault, where the address is known. Other faults
can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority,
the hard fault handler must clear this bit. This action prevents problems
if returning to a stacked active bus fault handler whose FAULTADDR
register value has been overwritten.
This bit is cleared by writing a 1 to it.

14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

13 BLSPERR RW1C 0 Bus Fault on Floating-Point Lazy State Preservation

Value Description
0 No bus fault has occurred during floating-point lazy state
preservation.
1 A bus fault has occurred during floating-point lazy state
preservation.

This bit is cleared by writing a 1 to it.

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Bit/Field Name Type Reset Description

12 BSTKE RW1C 0 Stack Bus Fault

Value Description
0 No bus fault has occurred on stacking for exception entry.
1 Stacking for an exception entry has caused one or more bus
faults.

When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the FAULTADDR register.
This bit is cleared by writing a 1 to it.

11 BUSTKE RW1C 0 Unstack Bus Fault

Value Description
0 No bus fault has occurred on unstacking for a return from
exception.
1 Unstacking for a return from exception has caused one or more
bus faults.

This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
FAULTADDR register.
This bit is cleared by writing a 1 to it.

10 IMPRE RW1C 0 Imprecise Data Bus Error

Value Description
0 An imprecise data bus error has not occurred.
1 A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.

When this bit is set, a fault address is not written to the FAULTADDR
register.
This fault is asynchronous. Therefore, if the fault is detected when the
priority of the current process is higher than the bus fault priority, the
bus fault becomes pending and becomes active only when the processor
returns from all higher-priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects that both the IMPRE bit is set and one of the precise fault status
bits is set.
This bit is cleared by writing a 1 to it.

9 PRECISE RW1C 0 Precise Data Bus Error

Value Description
0 A precise data bus error has not occurred.
1 A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the
fault.

When this bit is set, the fault address is written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.

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Bit/Field Name Type Reset Description

8 IBUS RW1C 0 Instruction Bus Error

Value Description
0 An instruction bus error has not occurred.
1 An instruction bus error has occurred.

The processor detects the instruction bus error on prefetching an

instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.

7 MMARV RW1C 0 Memory Management Fault Address Register Valid

Value Description
0 The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
1 The MMADDR register is holding a valid fault address.

If a memory management fault occurs and is escalated to a hard fault

because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.

6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 MLSPERR RW1C 0 Memory Management Fault on Floating-Point Lazy State Preservation

Value Description
0 No memory management fault has occurred during floating-point
lazy state preservation.
1 No memory management fault has occurred during floating-point
lazy state preservation.

This bit is cleared by writing a 1 to it.

4 MSTKE RW1C 0 Stack Access Violation

Value Description
0 No memory management fault has occurred on stacking for
exception entry.
1 Stacking for an exception entry has caused one or more access
violations.

When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
This bit is cleared by writing a 1 to it.

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Bit/Field Name Type Reset Description

3 MUSTKE RW1C 0 Unstack Access Violation

Value Description
0 No memory management fault has occurred on unstacking for
a return from exception.
1 Unstacking for a return from exception has caused one or more
access violations.

This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
MMADDR register.
This bit is cleared by writing a 1 to it.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 DERR RW1C 0 Data Access Violation

Value Description
0 A data access violation has not occurred.
1 The processor attempted a load or store at a location that does
not permit the operation.

When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
written to the MMADDR register.
This bit is cleared by writing a 1 to it.

0 IERR RW1C 0 Instruction Access Violation

Value Description
0 An instruction access violation has not occurred.
1 The processor attempted an instruction fetch from a location
that does not permit execution.

This fault occurs on any access to an XN region, even when the MPU
is disabled or not present.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
not written to the MMADDR register.
This bit is cleared by writing a 1 to it.

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Register 66: Hard Fault Status (HFAULTSTAT), offset 0xD2C

Note: This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.

Hard Fault Status (HFAULTSTAT)

Base 0xE000.E000
Offset 0xD2C
Type RW1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBG FORCED reserved

Type RW1C RW1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VECT reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 DBG RW1C 0 Debug Event

This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.

30 FORCED RW1C 0 Forced Hard Fault

Value Description
0 No forced hard fault has occurred.
1 A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.

When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
This bit is cleared by writing a 1 to it.

29:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 VECT RW1C 0 Vector Table Read Fault

Value Description
0 No bus fault has occurred on a vector table read.
1 A bus fault occurred on a vector table read.

This error is always handled by the hard fault handler.

When this bit is set, the PC value stacked for the exception return points
to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 67: Memory Management Fault Address (MMADDR), offset 0xD34

Note: This register can only be accessed from privileged mode.
The MMADDR register contains the address of the location that generated a memory management
fault. When an unaligned access faults, the address in the MMADDR register is the actual address
that faulted. Because a single read or write instruction can be split into multiple aligned accesses,
the fault address can be any address in the range of the requested access size. Bits in the Memory
Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether
the value in the MMADDR register is valid (see page 184).

Memory Management Fault Address (MMADDR)

Base 0xE000.E000
Offset 0xD34
Type RW, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 ADDR RW - Fault Address

When the MMARV bit of MFAULTSTAT is set, this field holds the address
of the location that generated the memory management fault.

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Register 68: Bus Fault Address (FAULTADDR), offset 0xD38

Note: This register can only be accessed from privileged mode.
The FAULTADDR register contains the address of the location that generated a bus fault. When
an unaligned access faults, the address in the FAULTADDR register is the one requested by the
instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid
(see page 184).

Bus Fault Address (FAULTADDR)

Base 0xE000.E000
Offset 0xD38
Type RW, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 ADDR RW - Fault Address

When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the
address of the location that generated the bus fault.

3.6 Memory Protection Unit (MPU) Register Descriptions

This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by
address offset.
The MPU registers can only be accessed from privileged mode.

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Register 69: MPU Type (MPUTYPE), offset 0xD90

Note: This register can only be accessed from privileged mode.
The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it
supports.

MPU Type (MPUTYPE)

Base 0xE000.E000
Offset 0xD90
Type RO, reset 0x0000.0800
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved IREGION

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DREGION reserved SEPARATE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:16 IREGION RO 0x00 Number of I Regions

This field indicates the number of supported MPU instruction regions.
This field always contains 0x00. The MPU memory map is unified and
is described by the DREGION field.

15:8 DREGION RO 0x08 Number of D Regions

Value Description
0x08 Indicates there are eight supported MPU data regions.

7:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 SEPARATE RO 0 Separate or Unified MPU

Value Description
0 Indicates the MPU is unified.

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Register 70: MPU Control (MPUCTRL), offset 0xD94

Note: This register can only be accessed from privileged mode.
The MPUCTRL register enables the MPU, enables the default memory map background region,
and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask
Register (FAULTMASK) escalated handlers.
When the ENABLE and PRIVDEFEN bits are both set:

■ For privileged accesses, the default memory map is as described in “Memory Model” on page 103.
Any access by privileged software that does not address an enabled memory region behaves
as defined by the default memory map.

■ Any access by unprivileged software that does not address an enabled memory region causes
a memory management fault.

Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless
of the value of the ENABLE bit.
When the ENABLE bit is set, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled,
then only privileged software can operate.
When the ENABLE bit is clear, the system uses the default memory map, which has the same
memory attributes as if the MPU is not implemented (see Table 2-5 on page 107 for more information).
The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always
permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set.
Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for
an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or
NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when
operating with these two priorities.

MPU Control (MPUCTRL)

Base 0xE000.E000
Offset 0xD94
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PRIVDEFEN HFNMIENA ENABLE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

2 PRIVDEFEN RW 0 MPU Default Region

This bit enables privileged software access to the default memory map.

Value Description
0 If the MPU is enabled, this bit disables use of the default memory
map. Any memory access to a location not covered by any
enabled region causes a fault.
1 If the MPU is enabled, this bit enables use of the default memory
map as a background region for privileged software accesses.

When this bit is set, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this default
map.
If the MPU is disabled, the processor ignores this bit.

1 HFNMIENA RW 0 MPU Enabled During Faults

This bit controls the operation of the MPU during hard fault, NMI, and
FAULTMASK handlers.

Value Description
0 The MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit.
1 The MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.

When the MPU is disabled and this bit is set, the resulting behavior is
unpredictable.

0 ENABLE RW 0 MPU Enable

Value Description
0 The MPU is disabled.
1 The MPU is enabled.

When the MPU is disabled and the HFNMIENA bit is set, the resulting
behavior is unpredictable.

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Register 71: MPU Region Number (MPUNUMBER), offset 0xD98

Note: This register can only be accessed from privileged mode.
The MPUNUMBER register selects which memory region is referenced by the MPU Region Base
Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the
required region number should be written to this register before accessing the MPUBASE or the
MPUATTR register. However, the region number can be changed by writing to the MPUBASE
register with the VALID bit set (see page 197). This write updates the value of the REGION field.

MPU Region Number (MPUNUMBER)

Base 0xE000.E000
Offset 0xD98
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved NUMBER

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2:0 NUMBER RW 0x0 MPU Region to Access

This field indicates the MPU region referenced by the MPUBASE and
MPUATTR registers. The MPU supports eight memory regions.

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Register 72: MPU Region Base Address (MPUBASE), offset 0xD9C

Register 73: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4
Register 74: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC
Register 75: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4
Note: This register can only be accessed from privileged mode.
The MPUBASE register defines the base address of the MPU region selected by the MPU Region
Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To
change the current region number and update the MPUNUMBER register, write the MPUBASE
register with the VALID bit set.
The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size,
as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines
the value of N where:
N = Log2(Region size in bytes)
If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In
this case, the region occupies the complete memory map, and the base address is 0x0000.0000.
The base address is aligned to the size of the region. For example, a 64-KB region must be aligned
on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000.

MPU Region Base Address (MPUBASE)

Base 0xE000.E000
Offset 0xD9C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR VALID reserved REGION

Type RW RW RW RW RW RW RW RW RW RW RW WO RO RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:5 ADDR RW 0x0000.000 Base Address Mask

Bits 31:N in this field contain the region base address. The value of N
depends on the region size, as shown above. The remaining bits (N-1):5
are reserved.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

4 VALID WO 0 Region Number Valid

Value Description
0 The MPUNUMBER register is not changed and the processor
updates the base address for the region specified in the
MPUNUMBER register and ignores the value of the REGION
field.
1 The MPUNUMBER register is updated with the value of the
REGION field and the base address is updated for the region
specified in the REGION field.

This bit is always read as 0.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2:0 REGION RW 0x0 Region Number

On a write, contains the value to be written to the MPUNUMBER register.
On a read, returns the current region number in the MPUNUMBER
register.

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Register 76: MPU Region Attribute and Size (MPUATTR), offset 0xDA0
Register 77: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
Register 78: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
Register 79: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
Note: This register can only be accessed from privileged mode.
The MPUATTR register defines the region size and memory attributes of the MPU region specified
by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant
halfword holding the region attributes and the least-significant halfword holds the region size and
the region and subregion enable bits.
The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register
as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table
3-10 on page 199 gives example SIZE values with the corresponding region size and value of N in
the MPU Region Base Address (MPUBASE) register.

Table 3-10. Example SIZE Field Values

a
SIZE Encoding Region Size Value of N Note
00100b (0x4) 32 B 5 Minimum permitted size
01001b (0x9) 1 KB 10 -
10011b (0x13) 1 MB 20 -
11101b (0x1D) 1 GB 30 -
11111b (0x1F) 4 GB No valid ADDR field in MPUBASE; the Maximum possible size
region occupies the complete
memory map.
a. Refers to the N parameter in the MPUBASE register (see page 197).

MPU Region Attribute and Size (MPUATTR)

Base 0xE000.E000
Offset 0xDA0
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved XN reserved AP reserved TEX S C B

Type RO RO RO RW RO RW RW RW RO RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SRD reserved SIZE ENABLE

Type RW RW RW RW RW RW RW RW RO RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit/Field Name Type Reset Description

31:29 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

28 XN RW 0 Instruction Access Disable

Value Description
0 Instruction fetches are enabled.
1 Instruction fetches are disabled.

27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26:24 AP RW 0 Access Privilege

For information on using this bit field, see Table 3-5 on page 141.

23:22 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

21:19 TEX RW 0x0 Type Extension Mask

For information on using this bit field, see Table 3-3 on page 140.

18 S RW 0 Shareable
For information on using this bit, see Table 3-3 on page 140.

17 C RW 0 Cacheable
For information on using this bit, see Table 3-3 on page 140.

16 B RW 0 Bufferable
For information on using this bit, see Table 3-3 on page 140.

15:8 SRD RW 0x00 Subregion Disable Bits

Value Description
0 The corresponding subregion is enabled.
1 The corresponding subregion is disabled.

Region sizes of 128 bytes and less do not support subregions. When
writing the attributes for such a region, configure the SRD field as 0x00.
See the section called “Subregions” on page 140 for more information.

7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:1 SIZE RW 0x0 Region Size Mask

The SIZE field defines the size of the MPU memory region specified by
the MPUNUMBER register. Refer to Table 3-10 on page 199 for more
information.

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Bit/Field Name Type Reset Description

0 ENABLE RW 0 Region Enable

Value Description
0 The region is disabled.
1 The region is enabled.

3.7 Floating-Point Unit (FPU) Register Descriptions

This section lists and describes the Floating-Point Unit (FPU) registers, in numerical order by address
offset.

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Register 80: Coprocessor Access Control (CPAC), offset 0xD88

The CPAC register specifies the access privileges for coprocessors.

Coprocessor Access Control (CPAC)

Base 0xE000.E000
Offset 0xD88
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved CP11 CP10 reserved

Type RO RO RO RO RO RO RO RO RW RW RW RW RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:22 CP11 RW 0x00 CP11 Coprocessor Access Privilege

Value Description
0x0 Access Denied
Any attempted access generates a NOCP Usage Fault.
0x1 Privileged Access Only
An unprivileged access generates a NOCP fault.
0x2 Reserved
The result of any access is unpredictable.
0x3 Full Access

21:20 CP10 RW 0x00 CP10 Coprocessor Access Privilege

Value Description
0x0 Access Denied
Any attempted access generates a NOCP Usage Fault.
0x1 Privileged Access Only
An unprivileged access generates a NOCP fault.
0x2 Reserved
The result of any access is unpredictable.
0x3 Full Access

19:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 81: Floating-Point Context Control (FPCC), offset 0xF34

The FPCC register sets or returns FPU control data.

Floating-Point Context Control (FPCC)

Base 0xE000.E000
Offset 0xF34
Type RW, reset 0xC000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ASPEN LSPEN reserved

Type RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MONRDY reserved BFRDY MMRDY HFRDY THREAD reserved USER LSPACT

Type RO RO RO RO RO RO RO RW RO RW RW RW RW RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 ASPEN RW 1 Automatic State Preservation Enable

When set, enables the use of the FRACTV bit in the CONTROL register
on execution of a floating-point instruction. This results in automatic
hardware state preservation and restoration, for floating-point context,
on exception entry and exit.

Important: Two bits control when FPCA can be enabled: the ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the DISFPCA bit in the Auxiliary Control
(ACTLR) register.

30 LSPEN RW 1 Lazy State Preservation Enable

When set, enables automatic lazy state preservation for floating-point
context.

29:9 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

8 MONRDY RW 0 Monitor Ready

When set, DebugMonitor is enabled and priority permits setting
MON_PEND when the floating-point stack frame was allocated.

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 BFRDY RW 0 Bus Fault Ready

When set, BusFault is enabled and priority permitted setting the BusFault
handler to the pending state when the floating-point stack frame was
allocated.

5 MMRDY RW 0 Memory Management Fault Ready

When set, MemManage is enabled and priority permitted setting the
MemManage handler to the pending state when the floating-point stack
frame was allocated.

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Bit/Field Name Type Reset Description

4 HFRDY RW 0 Hard Fault Ready

When set, priority permitted setting the HardFault handler to the pending
state when the floating-point stack frame was allocated.

3 THREAD RW 0 Thread Mode

When set, mode was Thread Mode when the floating-point stack frame
was allocated.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 USER RW 0 User Privilege Level

When set, privilege level was user when the floating-point stack frame
was allocated.

0 LSPACT RW 0 Lazy State Preservation Active

When set, Lazy State preservation is active. Floating-point stack frame
has been allocated but saving state to it has been deferred.

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Register 82: Floating-Point Context Address (FPCA), offset 0xF38

The FPCA register holds the location of the unpopulated floating-point register space allocated on
an exception stack frame.

Floating-Point Context Address (FPCA)

Base 0xE000.E000
Offset 0xF38
Type RW, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDRESS

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRESS reserved

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RO RO RO
Reset - - - - - - - - - - - - - 0 0 0

Bit/Field Name Type Reset Description

31:3 ADDRESS RW - Address

The location of the unpopulated floating-point register space allocated
on an exception stack frame.

2:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 83: Floating-Point Default Status Control (FPDSC), offset 0xF3C

The FPDSC register holds the default values for the Floating-Point Status Control (FPSC) register.

Floating-Point Default Status Control (FPDSC)

Base 0xE000.E000
Offset 0xF3C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved AHP DN FZ RMODE reserved

Type RO RO RO RO RO RW RW RW RW RW RO RO RO RO RO RO
Reset 0 0 0 0 0 - - - - - 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:27 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26 AHP RW - AHP Bit Default

This bit holds the default value for the AHP bit in the FPSC register.

25 DN RW - DN Bit Default
This bit holds the default value for the DN bit in the FPSC register.

24 FZ RW - FZ Bit Default
This bit holds the default value for the FZ bit in the FPSC register.

23:22 RMODE RW - RMODE Bit Default

This bit holds the default value for the RMODE bit field in the FPSC
register.

Value Description
0x0 Round to Nearest (RN) mode
0x1 Round towards Plus Infinity (RP) mode
0x2 Round towards Minus Infinity (RM) mode
0x3 Round towards Zero (RZ) mode

21:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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4 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into
the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The TM4C1294NCPDT JTAG controller works with the ARM JTAG controller built into the Cortex-M4F
core by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the
ARM TDO output while JTAG instructions select the TDO output. The multiplexer is controlled by the
JTAG controller, which has comprehensive programming for the ARM, Tiva™ C Series
microcontroller, and unimplemented JTAG instructions.
The TM4C1294NCPDT JTAG module has the following features:

■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller

■ Four-bit Instruction Register (IR) chain for storing JTAG instructions

■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST

■ ARM additional instructions: APACC, DPACC and ABORT

■ Integrated ARM Serial Wire Debug (SWD)

– Serial Wire JTAG Debug Port (SWJ-DP)

– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

– Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling

– Instrumentation Trace Macrocell (ITM) for support of printf style debugging

– Embedded Trace Macrocell (ETM) for instruction trace capture

– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM
JTAG controller.

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4.1 Block Diagram

Figure 4-1. JTAG Module Block Diagram

TCK TAP Controller

TMS

TDI Instruction Register (IR)

BYPASS Data Register

TDO

Boundary Scan Data Register

IDCODE Data Register

ABORT Data Register

DPACC Data Register

APACC Data Register

Cortex-M4F
Debug
Port

4.2 Signal Description

The following table lists the external signals of the JTAG/SWD controller and describes the function
of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however
note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals
are under commit protection and require a special process to be configured as GPIOs, see “Commit
Control” on page 752. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO
pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 770) is set to choose the JTAG/SWD function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 787) to assign the JTAG/SWD controller signals to the specified GPIO
port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 742.

Table 4-1. JTAG_SWD_SWO Signals (128TQFP)

Pin Name Pin Number Pin Mux / Pin Pin Type Buffer Type Description
Assignment
SWCLK 100 PC0 (1) I TTL JTAG/SWD CLK.
SWDIO 99 PC1 (1) I/O TTL JTAG TMS and SWDIO.
SWO 97 PC3 (1) O TTL JTAG TDO and SWO.
TCK 100 PC0 (1) I TTL JTAG/SWD CLK.
TDI 98 PC2 (1) I TTL JTAG TDI.
TDO 97 PC3 (1) O TTL JTAG TDO and SWO.
TMS 99 PC1 (1) I TTL JTAG TMS and SWDIO.

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4.3 Functional Description

A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 208. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
The current state of the TAP controller depends on the sequence of values captured on TMS at the
rising edge of TCK. The TAP controller determines when the serial shift chains capture new data,
shift data from TDI towards TDO, and update the parallel load registers. The current state of the
TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register
(DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST, operate on data currently in a DR chain and do not capture, shift,
or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction
to ensure that the serial path between TDI and TDO is always connected (see Table 4-3 on page 216
for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 1824 for JTAG timing diagrams.
Depending on the reset source, the effect on the JTAG module varies. The following reset sources
reset the entire JTAG Module:

■ Externally generated Power-On Reset

The following reset sources reset only the JTAG pin configuration:

■ RST pin Power-On Reset

■ Brown-Out Power-On Reset

■ Watchdog Power-On Reset

■ HIB Module Power-On Reset

■ RST pin System Reset

■ Brown-Out System Reset

■ Software System Reset Request (using the SYSRESREQ bit in the APINT register)

■ Software Peripheral Reset

■ Watchdog System Reset

■ HIB Module System Reset

4.3.1 JTAG Interface Pins

The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their
associated state after a power-on reset or reset caused by the RST input are given in Table 4-2.
Detailed information on each pin follows.

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Note: The following pins are configured as JTAG port pins out of reset. Refer to “General-Purpose
Input/Outputs (GPIOs)” on page 742 for information on how to reprogram the configuration
of these pins.

Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion
Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value
TCK Input Enabled Disabled N/A N/A
TMS Input Enabled Disabled N/A N/A
TDI Input Enabled Disabled N/A N/A
TDO Output Enabled Disabled 2-mA driver High-Z

4.3.1.1 Test Clock Input (TCK)

The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks and to ensure that multiple JTAG TAP controllers that
are daisy-chained together can synchronously communicate serial test data between components.
During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When
necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0
or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data
Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset, assuring that no clocking
occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors
can be turned off to save internal power as long as the TCK pin is constantly being driven by an
external source (see page 776 and page 778).

4.3.1.2 Test Mode Select (TMS)

The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be
entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1
expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
module and associated registers are reset to their default values. This procedure should be performed
to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety
in Figure 4-2 on page 212.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost (see page 776).

4.3.1.3 Test Data Input (TDI)

The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, may present this data to the proper shift register chain. Because the TDI pin is sampled
on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the
falling edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost (see page 776).

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4.3.1.4 Test Data Output (TDO)

The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset, assuring that the pin
remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states (see page 776 and page 778).
Note: If the device fails initialization during reset, the hardware toggles the TDO output as an
indication of failure. Thus, during board layout, designers should not designate the TDO pin
as a GPIO in sensitive applications where the possibility of toggling could affect the design.

4.3.2 JTAG TAP Controller

The JTAG TAP controller state machine is shown in Figure 4-2. The TAP controller state machine
is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset
the JTAG module after the microcontroller has been powered on, the TMS input must be held HIGH
for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting
the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in
data, or idle during extended testing sequences. For detailed information on the function of the TAP
controller and the operations that occur in each state, please refer to IEEE Standard 1149.1.

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Figure 4-2. Test Access Port State Machine

Test Logic Reset

1 0

Run Test Idle Select DR Scan Select IR Scan

1 1 1
0 0 0

Capture DR Capture IR
1 1
0 0

Shift DR Shift IR
1 0 1 0

Exit 1 DR Exit 1 IR
1 1
0 0

Pause DR Pause IR

1 0 1 0

Exit 2 DR Exit 2 IR
0 0
1 1

Update DR Update IR
1 0 1 0

4.3.3 Shift Registers

The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller's CAPTURE states and allows
this information to be shifted out on TDO during the TAP controller's SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller's UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 215.

4.3.4 Operational Considerations

Certain operational parameters must be considered when using the JTAG module. Because the
JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these
pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes is described below.

4.3.4.1 GPIO Functionality

When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0]
set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0]
set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors
(PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the

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alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select
(GPIOAFSEL) register) on the JTAG/SWD pins. See page 770, page 776, page 778, and page 781.
It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in
the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.

Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the TM4C1294NCPDT microcontroller. If the program code loaded into flash immediately changes
the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and
halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked
out of the part. This issue can be avoided with a software routine that restores JTAG functionality
based on an external or software trigger. In the case that the software routine is not implemented and
the device is locked out of the part, this issue can be solved by using the TM4C1294NCPDT Flash
Programmer "Unlock" feature. Please refer to LMFLASHPROGRAMMER on the TI web for more
information.

The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four
JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 1772 for pin numbers). Writes to
protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 770), GPIO
Pull Up Select (GPIOPUR) register (see page 776), GPIO Pull-Down Select (GPIOPDR) register
(see page 778), and GPIO Digital Enable (GPIODEN) register (see page 781) are not committed to
storage unless the GPIO Lock (GPIOLOCK) register (see page 783) has been unlocked and the
appropriate bits of the GPIO Commit (GPIOCR) register (see page 784) have been set.

4.3.4.2 Communication with JTAG/SWD

Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.

4.3.4.3 Recovering a "Locked" Microcontroller

Note: Performing the sequence below restores the non-volatile registers discussed in “Non-Volatile
Register Programming-- Flash Memory Resident Registers” on page 613 to their factory
default values. The mass erase of the Flash memory caused by the sequence below occurs
prior to the non-volatile registers being restored.
In addition, the EEPROM is erased and its wear-leveling counters are returned to factory
default values when performing the sequence below.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug port unlock sequence that can be used to recover the
microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while
holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence
is:

1. Assert and hold the RST signal.

2. Apply power to the device.

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3. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD
Switching” on page 214.

4. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG
Switching” on page 215.

5. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.

6. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.

7. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.

8. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.

9. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.

10. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.

11. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.

12. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.

13. Release the RST signal.

14. Wait 400 ms.

15. Power-cycle the microcontroller.

4.3.4.4 ARM Serial Wire Debug (SWD)

In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M4F core without having to perform, or have any
knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued
before the SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequence of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Debug Interface V5 Architecture Specification.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This instance is the only one
where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to
the low probability of this sequence occurring during normal operation of the TAP controller, it should
not affect normal performance of the JTAG interface.

JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the microcontroller. The 16-bit
TMS/SWDIO command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted
LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The

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complete switch sequence should consist of the following transactions on the TCK/SWCLK and
TMS/SWDIO signals:

1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.

2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS/SWDIO.

3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in SWD mode before sending the switch sequence, the SWD goes into the line reset state.

To verify that the Debug Access Port (DAP) has switched to the Serial Wire Debug (SWD) operating
mode, perform a SWD READID operation. The ID value can be compared against the device's
known ID to verify the switch.

SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch command to the microcontroller. The 16-bit TMS/SWDIO
command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first.
This command can also be represented as 0xE73C when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:

1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.

2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS/SWDIO.

3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in JTAG mode before sending the switch sequence, the JTAG goes into the Test Logic Reset
state.

To verify that the Debug Access Port (DAP) has switched to the JTAG operating mode, set the
JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The
DR value can be compared against the device's known IDCODE to verify the switch.

4.4 Initialization and Configuration

After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. To return the pins to their JTAG functions,
enable the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register.
In addition to enabling the alternate functions, any other changes to the GPIO pad configurations
on the four JTAG pins (PC[3:0]) should be returned to their default settings.

4.5 Register Descriptions

The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are
not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within
the JTAG controller are all accessed serially through the TAP Controller. These registers include
the Instruction Register and the six Data Registers.

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4.5.1 Instruction Register (IR)

The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated,
they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-3. A
detailed explanation of each instruction, along with its associated Data Register, follows.

Table 4-3. JTAG Instruction Register Commands

IR[3:0] Instruction Description
0x0 EXTEST Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
0x2 SAMPLE / PRELOAD Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
0x8 ABORT Shifts data into the ARM Debug Port Abort Register.
0xA DPACC Shifts data into and out of the ARM DP Access Register.
0xB APACC Shifts data into and out of the ARM AC Access Register.
0xE IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1 into
the IDCODE chain and shifts it out.
0xF BYPASS Connects TDI to TDO through a single Shift Register chain.
All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.

4.5.1.1 EXTEST Instruction

The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. With tests
that drive known values out of the controller, this instruction can be used to verify connectivity. While
the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can
be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.

4.5.1.2 SAMPLE/PRELOAD Instruction

The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST instruction
to drive data into or out of the controller. See “Boundary Scan Data Register” on page 218 for more
information.

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4.5.1.3 ABORT Instruction

The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. See the “ABORT Data Register” on page 219 for more information.

4.5.1.4 DPACC Instruction

The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. See “DPACC Data
Register” on page 219 for more information.

4.5.1.5 APACC Instruction

The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
See “APACC Data Register” on page 218 for more information.

4.5.1.6 IDCODE Instruction

The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure input and output data streams. IDCODE is the default instruction loaded into the JTAG
Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is
entered. See “IDCODE Data Register” on page 217 for more information.

4.5.1.7 BYPASS Instruction

The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 218 for more
information.

4.5.2 Data Registers

The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE,
BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections.

4.5.2.1 IDCODE Data Register

The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-3. The standard requires that every JTAG-compliant microcontroller implement either the
IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.

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The major uses of the JTAG port are for manufacturer testing of component assembly and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically
configure themselves to work correctly with the Cortex-M4F during debug.

Figure 4-3. IDCODE Register Format

31 28 27 12 11 1 0
TDI TDO
Version Part Number Manufacturer ID 1

4.5.2.2 BYPASS Data Register

The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-4. The standard requires that every JTAG-compliant microcontroller implement either the
BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.

Figure 4-4. BYPASS Register Format

0
TDI 0 TDO

4.5.2.3 Boundary Scan Data Register

The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting
with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each
GPIO pin has three associated digital signals that are included in the chain. These signals are input,
output, and output enable, and are arranged in that order as shown in the figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST instruction. The EXTEST instruction forces data out of the controller.

Figure 4-5. Boundary Scan Register Format

O O O O
TDI I O I O I O I O TDO
U ... U U ... U
N E N E N E N E
T T T T

1st GPIO mth GPIO (m+1)th GPIO GPIO nth

4.5.2.4 APACC Data Register

The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.

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4.5.2.5 DPACC Data Register

The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.

4.5.2.6 ABORT Data Register

The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.

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5 System Control
System control configures the overall operation of the device and provides information about the
device. Configurable features include reset control, NMI operation, power control, clock control, and
low-power modes.

5.1 Signal Description

The following table lists the external signals of the System Control module and describes the function
of each. The NMI signal is the alternate function for two GPIO signals, which default to GPIO after
reset. The NMI pins are under commit protection and require a special process to be configured as
any alternate function or to subsequently return to the GPIO function. See “Commit
Control” on page 752 for more information. The column in the table below titled "Pin Mux/Pin
Assignment" lists the GPIO pin placement for the NMI signal. The number in parentheses next to
the pin placement listed is the encoding that must be programmed into the PMCn field in the GPIO
Port Control (GPIOPCTL) register (page 787) to assign the NMI signal to the specified GPIO port
pin. In addition, the AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register
(page 770) should be set to choose the NMI function. For more information on configuring GPIOs,
see “General-Purpose Input/Outputs (GPIOs)” on page 742. The remaining signals listed in the table
(with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment and
function.

Table 5-1. System Control & Clocks Signals (128TQFP)

Pin Name Pin Number Pin Mux / Pin Pin Type Buffer Type Description
Assignment
DIVSCLK 102 PQ4 (7) O TTL An optionally divided reference clock output based
on a selected clock source. Note that this signal is
not synchronized to the System Clock.
NMI 128 PD7 (8) I TTL Non-maskable interrupt.
OSC0 88 fixed I Analog Main oscillator crystal input or an external clock
reference input.
OSC1 89 fixed O Analog Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST 70 fixed I TTL System reset input.

5.2 Functional Description

The System Control module provides the following capabilities:

■ Device identification, see “Device Identification” on page 220

■ Configurable control of reset, power, and clock sources.

■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 239

5.2.1 Device Identification

Read-only registers in the system control module provide information about the microcontroller,
such as version, part number, pin count, operating temperature range and available peripherals on
the device. The Device Identification 0 (DID0) (page 255) and Device Identification 1 (DID1)
(page 257) registers provide details about the device's version, package, temperature range, and so
on. The Peripheral Present registers starting at system control offset 0x300, such as the Watchdog

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Timer Peripheral Present (PPWD) register, provide information on how many of each type of
module are included on the device. Finally, information about the capabilities of the on-chip
peripherals are provided at offset 0xFC0 in each peripheral's register space in the Peripheral
Properties registers, such as the GPTM Peripheral Properties (GPTMPP). In addition, there are
four unique identifier registers, Unique Identifier n (UNIQUEIDn), that provide a 128-bit unique
identifier for each device that cannot be modified.

5.2.2 Reset Control

This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.

5.2.2.1 Reset Sources

The TM4C1294NCPDT microcontroller has the following reset sources:

1. Power-on reset (POR) (see page 222).

2. External reset input pin (RST) assertion (see page 223).

3. A brown-out detection of VDDA (analog voltage source) or VDD (external voltage source) dropping
below its acceptable operating range. (see page 224).

4. Software-initiated reset (with the software reset registers) (see page 226).

5. A watchdog timer reset condition violation (see page 226).

6. Hibernation module event

7. A software restart initiated through a Hardware System Service Request (HSSR)

8. MOSC failure (see page 228).

Table 5-2 provides a summary of results of the various reset operations. Note that the external RST
pin, the Brown-out detection unit, the HIB module and watchdog timer can all be programmed to
generate either a Power-On Reset (POR) or system reset depending on how the Reset Behavior
Control (RESBEHAVCTL) register at offset 0x1D8 is programmed.

Table 5-2. Reset Sources

Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset?
Externally Generated Yes Yes Yes
Power-On Reset
RST pin Power-On Reset Yes Pin Configuration Only Yes
RST pin System Reset Yes Pin Configuration Only Yes
Brown-Out Power-On Reset Yes Pin Configuration Only Yes
Brown-Out System Reset Yes Pin Configuration Only Yes
Software System Reset Yes Pin Configuration Only Yes
Request using the
SYSRESREQ bit in the APINT
register.
Software System Reset Yes No No
Request using the
VECTRESET bit in the APINT
register.

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Table 5-2. Reset Sources (continued)

Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset?
a
Software Peripheral Reset No Pin Configuration Only Yes
Watchdog Power-On Reset Yes Pin Configuration Only Yes
Watchdog System Reset Yes Pin Configuration Only Yes
HIB Module Power-On Reset Yes Pin Configuration Only Yes
HIB Module System Reset Yes Pin Configuration Only Yes
HSSR Reset Yes Pin Configuration Only Yes
MOSC Failure Reset Yes Pin Configuration Only Yes
a. Programmable on a module-by-module basis by using the individual peripheral Software Reset Registers starting at
System Control offset 0x500

After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences. A bit in the RESC register can
be cleared by writing a 0.

5.2.2.2 Boot Configuration

After Power-On-Reset (POR) and device initialization occurs, the hardware loads the stack pointer
from either flash or ROM based on the presence of an application in flash and the state of the EN
bit in the BOOTCFG register. If the flash address 0x0000.0004 contains an erased word (value
0xFFFF.FFFF) or the EN bit is of the BOOTCFG register is clear, the stack pointer and reset vector
pointer are loaded from ROM at address 0x0100.0000 and 0x0100.0004, respectively. The boot
loader executes and configures the available boot slave interfaces and waits for an external memory
to load its software.
If the check of the Flash at address 0x0000.0004 contains a valid reset vector value and the
BOOTCFG register does not indicate the boot loader, the boot sequence causes the stack
pointer/reset vector fetch from Flash. This application stack pointer and reset vector is loaded and
the processor executes the application directly.
Note: If the device fails the initialization phase, it toggles the TDO output pin as an indication the
device is not executing. This feature is provided for debug purposes.

5.2.2.3 Externally Generated Power-On Reset (POR)

Note: The JTAG controller can be reset by a power-on reset or by holding the TMS pin to high
for 5 clock cycles.
During an externally generated POR, the internal Power-On Reset (POR) circuit monitors the power
supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when
the power supply ramp reaches a threshold value (VPOR). Reset does not complete if specific voltage
parameters are not met as defined in the Electrical Characteristics chapter. For applications that
require the use of an external reset signal to hold the microcontroller in reset longer than the internal
POR, the RST input may be used as discussed in “External RST Pin” on page 223. Holding this pin
active can keep the initialization process from starting even though power-on reset has occurred.
This is useful in in-circuit testing and other situations where it is desirable to delay the operation of
the device until an external supervisor has released.
The Power-On Reset sequence is as follows:

1. The microcontroller waits for internal POR to go inactive.

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2. The internal reset is released and the core executes a full initialization of the device. Upon
completion, the core loads from memory the initial stack pointer, the initial program counter,
and the first instruction designated by the program counter, and then begins execution.

The internal POR is only active on the initial power-up of the microcontroller, when the microcontroller
wakes from hibernation, and when the VDD supply drops below the its defined operating limit. Please
refer to the Electrical Characteristics chapter for information on exact values. The Power-On Reset
timing is shown in “Power and Brown-Out” on page 1826.

5.2.2.4 External RST Pin

When the external RST pin is asserted it initiates a system reset or Power-On Reset depending on
what has been configured in the Reset Behavior Control (RESBEHAVCTL) Register. If the EXTRES
bit field in RESBEHAVCTL is set to 0x3 then a simulated full initialization will begin upon RST
assertion. If these bits are programmed to 0x2 then a system reset is issued. When EXTRES is set
to a 0x0 or 0x1, then the external RST pin performs its default operation upon assertion, which is
issuing a full simulated POR.
An external reset pin (RST) that is configured to generate a Power-On Reset resets the microcontroller
including the core and all the on-chip peripherals. The external reset sequence is as follows:

1. The external reset pin (RST) is asserted for the duration specified by TMIN and then deasserted
(see “Reset” on page 1831). This generates an internal POR signal.

2. The microcontroller waits for internal POR to go inactive.

3. The internal reset is released and the core executes a full initialization of the device. Upon
completion, the core loads from memory the initial stack pointer, the initial program counter,
and the first instruction designated by the program counter, and then begins execution. Refer
to “Reset” on page 1831 for internal reset deassertion timing.

An external reset pin (RST) that is configured to generate a system reset will reset the microcontroller
including the core and all the on-chip peripherals. The external reset sequence is as follows:

1. The external reset pin (RST) is asserted for the duration specified by TMIN and then deasserted
(see “Reset” on page 1831).

2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.

Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 224.
The RST input has filtering which requires a minimum pulse width in order for the reset pulse to be
recognized, see Table 27-14 on page 1831.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 224. If the application requires the use of an external
reset switch, Figure 5-3 on page 224 shows the proper circuitry to use. In the figures, the RPU and
C1 components define the power-on delay. The external reset timing is shown in Figure
27-11 on page 1832.

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Figure 5-1. Basic RST Configuration

VDD
Tiva™
Microcontroller
RPU
RST

Note: RPU = 0 to 100 kΩ

Figure 5-2. External Circuitry to Extend Power-On Reset

VDD
Tiva™
Microcontroller
RPU
RST

C1

Note: RPU = 1 kΩ to 100 kΩ

C1 = 1 nF to 10 µF

Figure 5-3. Reset Circuit Controlled by Switch

VDD
Tiva™
Microcontroller
RPU
RST
RS
C1

Note: Typical RPU = 10 kΩ

Typical RS = 470 Ω

C1 = 10 nF

5.2.2.5 Brown-Out Reset (BOR)

The microcontroller provides a brown-out detection circuit that triggers if the VDD (external) or VDDA
(analog) power supply drops below its corresponding brown-out threshold voltage. If a brown-out
condition is detected, the system may generate an interrupt, a system reset or a Power-On Reset.
The default value at reset is to generate an interrupt.

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The application can identify the type of BOR event that occurred by reading the Power-Temperature
Cause (PWRTC) register. The BOR detection circuits can be programmed to generate a reset,
System Control interrupt, or NMI in the Power-Temp Brown Out Control (PTBOCTL) register.
The default settings at reset are as follows:

■ VDDA under BOR detection default setting is for no action to occur.

■ VDD under BOR detection default setting is to execute a full POR.

If the user has programmed a field in the PTBOCTL to generate a reset, then the BOR bit of the
Reset Behavior Control (RESBEHAVCTL) register can be programmed to further define what
type of reset is generated. If the BOR field is programmed to 0x3, a full POR is initiated; if is set to
0x2, then a system reset is issued. When the BOR field is set to a 0x0 or 0x1, then the Brown-Out
detection circuit will perform its default operation upon assertion, which is issuing an interrupt.
Note: VDDA BOR and VDD BOR events are a combined BOR to the system logic, such that if either
BOR event occurs, the following bits are affected:

■ BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050.
See page 261.

■ BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System Control
offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control (IMC)
register has been set. See page 263 and page 265.

■ BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit is
set only if either of the BOR events have been configured to initiate a reset. See page 267.

In addition, the following bits control both BOR events:

■ BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054.

■ VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC) register.

Please refer to “System Control” on page 220 for more information on how to configure these
registers.
The brown-out POR reset sequence is as follows:

1. When one of the BOR event triggers occurs, an internal Brown-Out Reset condition is set.

2. If the BOR event has been programmed to generate a reset in the PTBOCTL register and the
BOR bit of the RESBEHAVCTL has been set to 0x3, an internal POR reset is asserted.

3. The internal reset is released and the core executes a full initialization of the device. Upon
completion, the core loads from memory the initial stack pointer, the initial program counter,
and the first instruction designated by the program counter, and then begins execution. The
application starts after deassertion of internal POR. Refer to “Reset” on page 1831 for BOR internal
reset deassertion timing.

The brown-out system reset sequence is as follows:

1. When one of the BOR event triggers occurs, an internal Brown-Out Reset condition is set.

2. If the BOR event has been programmed to generate a reset in the PTBOCTL register and the
BOR bit of the RESBEHAVCTL has been set to 0x2, an internal reset is asserted.

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3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer,
the initial program counter, the first instruction designated by the program counter, and begins
execution.

The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and
the reset is held active until the proper voltage level is restored. The RESC register can be examined
in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus
allowing software to determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in “Power and Brown-Out” on page 1826.

5.2.2.6 Software Reset

Software can reset a specific peripheral or generate a reset to the entire microcontroller.
Peripherals can be individually reset by software via peripheral-specific reset registers available
beginning at System Control offset 0x500 (for example the Watchdog Timer Software Reset
(SRWD) register page 354). If the bit position corresponding to a peripheral is set and subsequently
cleared, the peripheral is reset.
The entire microcontroller, including the core, can be reset by software by setting the SYSRESREQ
bit in the Application Interrupt and Reset Control (APINT) register in the core peripheral memory
map space. The software-initiated system reset sequence is as follows:

1. A software microcontroller reset is initiated by setting the SYSRESREQ bit.

2. An internal reset is asserted.

3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.

The core only can be reset by software by setting the VECTRESET bit in the APINT register. The
software-initiated core reset sequence is as follows:

1. A core reset is initiated by setting the VECTRESET bit.

2. An internal reset is asserted.

3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.

The software-initiated system reset timing is shown in Figure 27-12 on page 1832.

5.2.2.7 Watchdog Timer Reset

The Watchdog Timer module's function is to prevent system hangs. The TM4C1294NCPDT
microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One
watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC).
The watchdog timer can be configured to generate an interrupt or a non-maskable interrupt to the
microcontroller on its first time-out and to generate a system reset or power-on reset on its second
time-out.
After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of
the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If
the timer counts down to zero again before the first time-out interrupt is cleared, and watchdog reset

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generation has been enabled through the RESEN bit in the Watchdog Control Register (WDTCTL),
the watchdog timer asserts its reset signal to the microcontroller. The reset generated can be a full
Power-On Reset or a system reset depending on the value programmed in WDOGn bit field of the
Reset Behavior Control Register (RESBEHAVCTL). If the RESEN bit of the WDTCTL register is
set to 1 and the WDOGn bit field of the RESBEHAVCTL register is programmed to 0x3 a full POR is
initiated; if WDOGn set to 0x2, then a system reset is issued. When WDOGn is set to a 0x0 or 0x1,
then the watchdog time performs its default operation upon assertion, which is issuing a full POR.
The watchdog timer Power-On Reset sequence is as follows:

1. The watchdog timer times out for the second time without being serviced.

2. An internal POR reset is asserted.

3. The internal reset is released and the core executes a full initialization of the device. Upon
completion, the core loads from memory the initial stack pointer, the initial program counter,
and the first instruction designated by the program counter, and then begins execution. Refer
to “Reset” on page 1831 for watchdog timeout internal reset deassertion timing.

The watch dog timer system reset sequence is as follows:

1. The watchdog timer times out for the second time without being serviced.

2. An internal reset is asserted.

3. The internal reset is released and the microcontroller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.

For more information on the Watchdog Timer module, see “Watchdog Timers” on page 1028.
The watchdog reset timing is shown in Figure 27-13 on page 1832.

5.2.2.8 Hibernation Module Reset

When the Hibernation module has been configured and powered by an initial "cold" POR and is
subsequently put into hibernation mode, a wake event (not including an external reset pin wake)
causes the module to generate a system reset. This reset signal resets all circuitry on the device
with the exception of the Hibernation module. All Hibernation module registers retain their values
after this reset.
When the Hibernation module receives a wake event and VDD is enabled, a system reset sequence
occurs as follows:

1. The POR or EXT bit in the RESC register is set.

2. An internal reset is asserted.

3. The internal reset is released and the microcontroller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.

4. The HIBRIS register in the Hibernation module can be read to determine the cause of the reset.

5. The POR or EXT bit in the RESC register is cleared by writing a 0.

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5.2.2.9 HSSR Reset

The Hardware System Service Request (HSSR) register can be used to restore the device back
to factory settings. A successful write to the Hardware System Service Request (HSSR) register
initiates a system reset. The reset initialization process executes before examining the HSSR register
and processing the command. This register can only be accessed in privileged mode.
Before the return-to-factory settings routine has completed, a system reset sequence executes and
the HSSR bit in the RESC register is set. After the HSSR function has been processed, the CDOFF
field in the HSSR register is written with the outcome of the function processing and another HSSR
system reset is executed. The HSSR bit can be cleared in the RESC register by writing a 0.
For more information regarding use of the HSSR register, refer to “Hardware System Service
Request” on page 245.

5.2.3 Non-Maskable Interrupt

The microcontroller has multiple sources of non-maskable interrupt (NMI):

■ The assertion of the NMI signal.

■ A main oscillator verification error.

■ The NMISET bit in the Interrupt Control and State (INTCTRL) register in the Cortex™-M4F (see
page 167).

■ The Watchdog module time-out interrupt when the INTTYPE bit in the Watchdog Control
(WDTCTL) register is set (see page 1034).

■ Tamper event (see “Hibernation Module” on page 531 for more information).

■ Any of the following BOR trigger events:

– VDDA under BOR setting

– VDD under BOR setting

Software must check the cause of the interrupt in the NMI Cause (NMIC) register in order to
distinguish among the sources.

5.2.3.1 NMI Pin

The NMI signal is an alternate function for the GPIO port pin(s) specified in Table 26-3 on page 1785.
The alternate function must be enabled in the GPIO for the signal to be used as an interrupt, as
described in “General-Purpose Input/Outputs (GPIOs)” on page 742. Note that enabling the NMI
alternate function requires the use of the GPIO lock and commit function, similar to the requirements
of the GPIO port pins associated with JTAG/SWD functionality, see page 784. The active sense of
the NMI signal is High; asserting the enabled NMI signal above VIH initiates the NMI interrupt
sequence.

5.2.3.2 Main Oscillator Verification Failure

The TM4C1294NCPDT microcontroller provides a main oscillator verification circuit that generates
an error condition if the oscillator is running too fast or too slow. If the main oscillator verification
circuit is enabled and a failure occurs, either a power-on reset is generated and control is transferred
to the NMI handler, or an interrupt is generated. The MOSCIM bit in the MOSCCTL register determines

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which action occurs. In either case, the system clock source is automatically switched to the PIOSC.
If a MOSC failure reset occurs, the NMI handler is used to address the main oscillator verification
failure because the necessary code can be removed from the general reset handler, speeding up
reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator
Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator
fail status (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit
action is described in more detail in the section called “Main Oscillator Verification Circuit” on page 236.

5.2.4 Power Control

The TM4C1294NCPDT microcontroller provides an integrated LDO regulator that is used to provide
power to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture.
The voltage output has a maximum voltage of 1.2 V. Refer to “Dynamic Power
Management” on page 242 for more information on the LDO operation.
An external LDO may not be used.
Note: VDDA must be supplied with 3.3 V, or the microcontroller does not function properly. VDDA
is the supply for all of the analog circuitry on the device, including the clock circuitry.

Figure 5-4. Power Architecture

VDDC GND
Internal
Logic and PLL
VDDC GND

LDO Voltage
Regulator

+3.3V

VDD GND

I/O Buffers
VDD GND

+3.3V

VDDA GNDA
Analog Circuits
VDDA GNDA

Note: The VDDA voltage source is typically connected to a filtered voltage source or regulator.

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5.2.5 Clock Control

The system control module determines the control of clocks in this part.

5.2.5.1 Fundamental Clock Sources

There are multiple clock sources for use in the microcontroller. The Run and Sleep Mode
Configuration Register (RSCLKCFG) can be used to configure the required clock source for the
device after Power-On Reset, as well as the system clock divisor encodings. The available clock
sources are as follows:

■ Precision Internal Oscillator (PIOSC). The precision internal oscillator is an on-chip clock
source that the microcontroller uses during and following POR. It is the clock source in effect at
the start of reset vector fetch and the start of code application execution. It does not require the
use of any external components and provides a clock that is 16 MHz ±FPIOSC across temperature
(see Table 27-19 on page 1837). The PIOSC allows for a reduced system cost in applications that
require an accurate enough clock source. If the main oscillator is required, software must enable
the main oscillator following reset and allow the main oscillator to stabilize before changing the
clock reference. If the Hibernation Module clock source is a 32.768-kHz oscillator, the precision
internal oscillator can be trimmed by software based on a reference clock for increased accuracy.
Regardless of whether or not the PIOSC is the source for the system clock, the PIOSC can be
configured to be an alternate clock source for some of the peripherals. See the section called
“Peripheral Clock Sources” on page 234 for more information on peripherals that can use the
PIOSC as an alternate clock.

■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value can be any frequency between 5 MHz to 25 MHz (inclusive). Refer to
Table 5-7 on page 238 for recommended crystal values and PLL register programming. If the PLL
is not being used, the crystal may be any one of the supported frequencies between 4 MHz to
25 MHz. The single-ended clock source range is from DC through the specified speed of the
microcontroller.

■ Low-Frequency Internal Oscillator (LFIOSC). The Low-Frequency Internal Oscillator (LFIOSC)

provides a nominal frequency of 33 kHz with percentage variance specified in the Electrical
Characteristics section. It is intended for use during Deep-Sleep power-saving modes. This
power-savings mode provides reduced internal switching and the ability to power down the
MOSC and/or PIOSC while in Deep-Sleep mode through configuration of the Deep Sleep Clock
Configuration Register (DSCLKCFG) register.

■ Hibernation Module RTC Oscillator (RTCOSC) Clock Source. The Hibernation Module provides
a muxed output of two clocks to the System Control Module, an external 32.768-kHz clock or a
low-frequency clock (HIB LFIOSC). The Hibernation module has the option of being clocked by
a 32.768-kHz oscillator connected to the XOSC0 pin. The 32.768-kHz oscillator can be used for
the system clock, thus eliminating the need for an additional crystal or oscillator. Alternatively,
the Hibernation module contains a low-frequency oscillator (HIB LFIOSC) which is intended to
provide the system with a real-time clock source and may also provide an accurate source of
Deep-Sleep or Hibernate mode power savings. Note that the HIB LFIOSC is a different clock
source than the LFIOSC. Refer to the Electrical Characteristic Chapter for more information on
frequency range.

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The internal system clock (SysClk), is derived from any of the above sources. An internal PLL can
also be used by the PIOSC or MOSC clock to generate the system clock and peripheral clocks.
Table 5-3 on page 231 shows how the various clock sources can be used in a system.

Table 5-3. Clock Source Options

Clock Source Drive PLL PLL Enabled, SysClk SysClk generation enabled,
Capability? RSCLKCFG Bit generation RSCLKCFG Bit Encodings
Encodings capability?
Precision Internal Oscillator Yes USEPLL = 1, PLLSRC = Yes USEPLL = 0, OSCSRC = 0x0
(PIOSC) 0x0
Main Oscillator (MOSC) Yes USEPLL = 1, PLLSRC = Yes USEPLL = 0, OSCSRC = 0x3
0x3
Low Frequency Internal Oscillator No - Yes USEPLL = 0, OSCSRC = 0x2
a
(LFIOSC)
Hibernation Module RTC Oscillator No - Yes USEPLL = 0, OSCSRC = 0x4
(RTCOSC). 32.768-kHz Oscillator
or HIB LFIOSC
a. LFIOSC frequency is characterized as 33 kHz nominal, 10 kHz minimum and 90 kHz maximum.

5.2.5.2 Clock Configuration

The Run and Sleep Mode Configuration Register (RSCLKCFG) provides control for the system
clock in run and sleep mode. The Deep Sleep Clock Configuration register (DSCLKCFG) specifies
the behavior of the clock system while in deep sleep mode. These registers control the following
clock functionality:

■ Source of system clock in run and sleep mode

■ Source of system clock in deep-sleep mode

■ Enabling/disabling of PLL-derived system clock

■ Clock divisors for PLL or oscillator, depending on what is enabled

■ Enabling of memory timing parameters for flash

Providing further configuration, the PLL Frequency n (PLLFREQn) registers allow the PLL VCO
frequency (fVCO) to multiplied or divided by programmable values depending on the system clock
speed required.
Table 5-4 on page 231 shows the state of the clock sources following a Power-On Reset.

Table 5-4. Clock Source State Following POR

Clock Source Power-On Reset State
PLL Disabled/Powered Off
MOSC Disabled/Powered Off
LFIOSC Enabled
PIOSC Enabled
HIB RTCOSC Disabled

Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled.

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Note: The clock sources in Figure 5-5 include a superset of peripherals available in the family.
Some peripheral clock sources may not be present on your specific device.

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Figure 5-5. Main Clock Tree

GPIO (PM4)
mosc
PHY Clock

EMAC & EPHY

÷N
CS

CLKDIV

PTP REF_CLK
MII/RMII CLK
OSC0
1 mosc
SYSCLK
MOSC 0

lpc
OSC1 CLKDIV
CS
NOXTAL
ADCCLK

ADC0
÷N
mosc

piosc

ADCCLK

ADC1
DIVSCLK
mosc
piosc
÷N DIVSCLK

RTCCLK

ULPIEN
&!CSD
USB0CLK
1
USBCLK
0

USB
DSOSCSRC ÷N USBCLK_PLL
OSCSRC ULPIEN &CSD

CLKDIV
RS DS
mode
MOSC
XOSC0 PIOSC
0 PWMCLK
RTCOSC RTCOSC

PWM0
÷2N 1
RTOSC LFIOSC
USEPWMDIV
Reg
XOSC1 PWMDIV
DSSYSDIV
Hibernation Module (HIB)
OSYSDIV

LCD
RS DS
LFIOSC mode
OSCCLK
÷N
mosc 0 SYSCLK
PERIPHERALS
CPU
PLL ÷N 1
piosc
PIOSC VCO
mode
RS DS
16 MHz PLLSRC PLLFREQ0 PSYSDIV 0
PIOSC16 PLLFREQ1 USEPLL
To peripherals requiring clock gates
16MHz PIOSC clock PLLSTAT

ALTCLKCFG

ALTCLK A
B
RTCOSC
To peripherals such as
LFIOSC RSCLKCFG.ACG
UART, SSI, Timers, ADC, WDT 0 1
A mode
B RSD
clock gate
RCGC

SCGC

DCGC

mode is either run/sleep (RS), or deep sleep (DS).

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Peripheral Clock Sources

In addition to the main clock tree described above, the ADC, USB, Ethernet, PWM, UART, and
QSSI all have a Clock Control register in their register map at offset 0xFC8 that can be used to
control the clock generation for the module.

ADC Clock Control

The ADC digital block is clocked by the system clock and the ADC analog block is clocked from a
separate conversion clock (ADC clock). The ADC clock frequency can be up to 32 MHz to generate
a conversion rate of 2 Msps. A 16 MHz ADC clock provides a 1 Msps sampling rate. There are three
sources for the ADC clock:

■ The PLL VCO (fVCO) can be used if the CS bit field is 0x0 in the ADC Clock Configuration
(ADCCC) register and the CLKDIV bit field is configured in the same register.

■ The PIOSC can be used directly to provide a conversion rate near 1 Ms/s. To use the PIOSC,
the CS field in the ADCCC register needs to be set to 0x1 and the ALTCLK field should be
programmed to 0x0 in the Alternate Clock Configuration (ALTCLKCFG) register.

■ The Main Oscillator (MOSC): The MOSC clock source must be 16 MHz for a 1 Msps conversion
rate and 32 MHz for a 2 Msps conversion rate.

Note: If the ADC module is not using the PIOSC as the clock source, the system clock must be
at least 16 MHz.

USB Clock Control

When the USB module uses the integrated USB PHY, the MOSC must be the clock source, either
with or without using the PLL, and the system clock must be at least 30 MHz. In addition, only integer
divisors should be used to achieve the 60 MHz USB clock source. Fractional divisors may increase
jitter and compromise USB function. The USB Clock Control Register (USBCC) register contains
a CLKDIV bit field which can be programmed to specify the divisor used to reduce the PLL VCO
output to the 60 MHz clock source required for the serialization/deserialization module of the USB
controller.
In ULPI mode, if the clock source to the USB is internal, then the USB0CLK pin is an output to the
external ULPI PHY. If the USB clock source is external then, the USB0CLK pin functions as an input
from the external ULPI PHY.

Ethernet Clock Control

The Ethernet Controller Module and Integrated PHY receive two clock inputs. A gated system clock
acts as the clock source to the Control and Status registers (CSR) of the Ethernet MAC and must
be 20 MHz or greater for correct operation. The SYSCLK frequency for Run, Sleep and Deep Sleep
mode is programmed in the System Control module. See “Ethernet Clock Control” on page 1409 for
more information.

PHY Interface Clocking

The Ethernet Controller Module and Integrated PHY receive two clock inputs (see “PHY
Interface” on page 1409 for more information):

■ A gated system clock acts as the clock source to the Control and Status registers (CSR) of the
Ethernet MAC. The SysClk frequency for Run, Sleep and Deep Sleep mode is programmed in
the System Control module.

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■ The PHY receives the main oscillator (MOSC) which must be 25 MHz ± 50 ppm for proper
operation. The MOSC source can be a single-ended source or a crystal.

PWM Clock Control

The PWMCC register can be used to select the System Clock as the PWM clock source or a divided
System Clock. For more information, see page 1747.

Other Peripheral Clock Control

In the UART and QSSI Clock Control Registers, users can choose between the system clock
(SysClk), which is the default source for the baud clock, and an alternate clock. Note that there may
be special considerations when configuring the baud clock.

Optional Clock Output Signal (DIVSCLK)

An optional clock output, DIVSCLK, is provided which can be used as a clock source to an external
device but bears no timing relationship to other signals. Note that this signal is not synchronized to
the System Clock. By programming the SRC field in the Divisor and Source Clock Configuration
(DIVSCLK) register, the following clock outputs may be selected for DIVSCLK:

■ System Clock

■ PIOSC

■ MOSC

The DIV field in the DIVSCLK register controls the divided output clock frequency. The DIVSCLK
signal is selected as an alternate function of a GPIO signal and has the same inherit electrical
characteristics of a GPIO as listed in “Electrical Characteristics” on page 1818.

System Clock Frequency

The system clock (SysClk) is the clock that is distributed to the processor and the integrated
peripherals after clock gating. The SysClk frequency is based on the frequency of the clock source
and the divisor factor. For example, if the PLL is not being used and the device is not in deep sleep
mode, then the OSYSDIV bit field in the RSCLKCFG register is the divisor used to determine the
system clock. If the PLL is being used, then PSYSDIV bit field in the RSCLKCFG register must be
programmed as well as the values in the PLLFREQ0 and PLLFREQ1 registers. If the device is in
deep sleep mode, then the Deep Sleep Clock Configuration Register (DSCLKCFG) can be
programmed with the divisor bit field DSSYSYDIV to modify the clock source frequency. Table
5-5 on page 235 shows the different system clock frequency calculations based on the operation
mode, clock source and PLL encoding.

Table 5-5. System Clock Frequency

Clock Mode USEPLL (RSCLKCFG) SYSCLK Value Divisor Factors Used
Run or Sleep 1 fVCO/(PSYSDIV + 1) PSYSDIV bit field in RSCLKCFG; MINT,
MDIV in PLLFREQ0; Q, N bits in PLLFREQ1
Run or Sleep 0 fOSCCLK/(OSYSDIV + 1) OSYSDIV bit field in RSCLKCFG
Deep Sleep PLL not enabled in Deep fOSCCLK/(DSSYSDIV + 1) DSSYSDIV bit field in DSCLKCFG
Sleep

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5.2.5.3 Precision Internal Oscillator Operation (PIOSC)

The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC
must remain enabled because it is used for internal functions. The PIOSC can only be disabled
during Deep-Sleep mode. It can be powered down by setting the PIOSCPD bit in the DSCLKCFG
register.
The PIOSC generates a 16-MHz clock with a ±FPIOSC accuracy (see Table 27-19 on page 1837). At
the factory, the PIOSC is set to 16 MHz at room temperature, however, the frequency can be trimmed
for other voltage or temperature conditions using software in the following ways:

■ Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator
Calibration (PIOSCCAL) register.

■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As
the UT value increases, the generated period increases. To commit a new UT value, first set the
UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within
a few clock periods and is glitch free.

■ Automatic calibration using the enable 32.768-kHz oscillator from the Hibernation module: Set
the CAL bit in the PIOSCCAL register; the results of the calibration are shown in the RESULT
field in the Precision Internal Oscillator Statistic (PIOSCSTAT) register. After calibration is
complete, the PIOSC is trimmed using the trimmed value returned in the CT field.

5.2.5.4 Main Oscillator (MOSC)

The main oscillator supports the use of crystals from 5 to 25 MHz. The system control's RSCLKCFG
register can be configured to specify the MOSC as the system clock or as the PLL input source.
The MOSC can be selected as the oscillator source by programming the OSCRC bit in the RSCLKCFG
register. The NOXTAL bit in the MOSCCTL register allows the user to turn off power to the MOSC
if no crystal is connected reducing power draw from the MOSC circuit.

Main Oscillator Verification Circuit

The clock control includes circuitry to ensure that the main oscillator is running at the appropriate
frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside
of the allowable band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, and if the MOSCIM bit in the MOSCCTL register
is clear, then the following sequence is performed by the hardware:

1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.

2. The system clock is switched from the main oscillator to the PIOSC.

3. An internal system reset is initiated.

4. Reset is deasserted and the processor is directed to the NMI handler during the reset sequence.

5.2.5.5 PLL
The PLL has two modes of operation: Normal and Power-Down

■ Normal: The PLL oscillates based on the values in the PLLFREQ0 and PLLFREQ1 registers
and drives the output.

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■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.

The modes are programmed using the PLLPWR bit in the PLLFREQ0 register (see page 292).

PLL Configuration
The PLL is disabled by default during power-on reset and is enabled later by software if required.
Software specifies the output divisor to set the system clock frequency and enables the PLL to drive
the output. The PLL is controlled using the PLLFREQ0, PLLFREQ1 and PLLSTAT registers.
Changes made to these registers do not become active until after the NEWFREQ bit in the RSCLKCFG
register is enabled.
The clock source for the main PLL is selected by configuring the PLLSRC field in the Run and Sleep
Clock Configuration (RSCLKCFG) register.
The PLL allows for the generation of system clock frequencies in excess of the reference clock
provided. The reference clocks for the PLL are the PIOSC and the MOSC. The PLL is controlled
by two registers, PLLFREQ0 and PLLFREQ1. The PLL VCO frequency (fVCO) is determined through
the following calculation:

fVCO = fIN * MDIV

where

fIN = fXTAL/(Q+1)(N+1) or fPIOSC/(Q+1)(N+1)

MDIV = MINT + (MFRAC / 1024)

The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC
should be programmed to 0x0.
When the PLL is active, the system clock frequency (SysClk) is calculated using the following
equation:

SysClk = fVCO/ (PSYSDIV + 1)

The PLL system divisor factor (PSYSDIV) determines the value of the system clock. Table
5-6 on page 237 shows how the system divisor encodings affect the system clock frequency when
the fVCO = 480 MHz.

Table 5-6. System Divisor Factors for fvco=480 MHz

fVCO (MHz)= 480 MHz
System Clock (SYSCLK) (MHz) a
System Divisors (PSYSDIV +1)
120 4
60 8
48 10
30 16
24 20
12 40
6 80
a. The use of non-integer divisors introduce additional jitter which may affect interface performance.

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If the main oscillator provides the clock reference to the PLL, the translation provided by hardware
and used to program the PLL is available for software in the PLL Frequency n (PLLFREQn) registers
(see page 292). The internal translation provides a translation within ± 1% of the targeted PLL VCO
frequency. Table 5-7 on page 238 shows the actual PLL frequency and error for a given crystal
choice.
Table 5-7 on page 238 provides examples of the programming expected for the PLLFREQ0 and
PLLFREQ1 registers. The first column specifies the input crystal frequency and the last column
displays the PLL frequency given the values of MINT and N, when Q=0.
a
Table 5-7. Actual PLL Frequency
Crystal MINT (Decimal MINT (Hexadecimal N Reference PLL Frequency
Frequency Value) Value) Frequency (MHz)
b
(MHz) (MHz)
5 64 0x40 0x0 5 320
6 160 0x35 0x2 2 320
8 40 0x28 0x0 8 320
10 32 0x20 0x0 10 320
12 80 0x50 0x2 4 320
16 20 0x14 0x0 16 320
18 160 0xA0 0x8 2 320
20 16 0x10 0x0 20 320
24 40 0x28 0x2 8 320
25 64 0x40 0x4 5 320
5 96 0x60 0x0 5 480
6 80 0x50 0x0 6 480
8 60 0x3C 0x0 8 480
10 48 0x30 0x0 10 480
12 40 0x28 0x0 12 480
16 30 0x1E 0x0 16 480
18 80 0x50 0x2 6 480
20 24 0x18 0x0 20 480
24 20 0x14 0x0 24 480
25 96 0x60 0x4 5 480
a. For all examples listed, Q=0
b. For a given crystal frequency, N should be chosen such that the reference frequency is within 4 to 30 MHz.

PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
27-16 on page 1835). During the relock time, the affected PLL is not usable as a clock reference.
Software can poll the LOCK bit in the PLL Status (PLLSTAT) register to determine when the PLL
has locked.
Modification of the PLL VCO frequency may not be performed while the PLL serves as a clock
source to the system. All changes to the PLL must be performed using a different clock source until
the PLL has locked frequency. Thus, changing the PLL VCO frequency must be done as a sequence
from PLL to PIOSC/MOSC and then PIOSC/MOSC to new PLL.

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Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition
is met after one of the two changes above. It is the user's responsibility to have a stable clock source
(like the main oscillator) before the RSCLKCFG register is re-programmed to enable the PLL.
Software can use many methods to ensure that the system is clocked from the PLL, including
periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register at offset 0x050, and
enabling the PLL Lock interrupt in the Interrupt Mask Control (IMC) register at offset 0x054.

5.2.6 System Control

There are four levels of operation for the microcontroller defined as:

■ Run mode

■ Sleep mode

■ Deep-Sleep mode

■ Hibernation mode

For power-savings purposes, the peripheral-specific RCGCx, SCGCx, and DCGCx registers (for
example, RCGCWD) control the clock-gating logic for that peripheral or block in the system while
the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. These registers are located
in the System Control register map starting at offsets 0x600, 0x700, and 0x800, respectively.
Note: A change in the RCGCx (or SCGCx/DCGCx/PCx/SRx) registers may not have an immediate
effect on the clock in all situations. It is recommended that software poll the peripheral's
Peripheral Ready (PRx) register to determine when a peripheral is ready to be accessed.
Note: If a peripheral is configured to be clock-gated during Run, Sleep- or Deep-Sleep mode, then
software should ensure that there are no pending transfers or register accesses before or
immediately after entering the clock-gated mode.
The following sections describe the different modes in detail.

5.2.6.1 Run Mode

In Run mode, the microcontroller actively executes code. Run mode provides normal operation of
the processor and all of the peripherals that are currently enabled by the peripheral-specific RCGC
registers. In run mode (and in sleep mode), the Run and Sleep Clock Configuration (RSCLKCFG)
register specifies the source of SysClk. The source is either from the VCO output of the PLL divided
down by a dedicated divisor (divisor value specified by the PSYSDIV field) or from the output of an
oscillator divided down by a dedicated divisor (divisor value specified by the OSYSDIV field). The
source is selected using the USEPLL bit in the RSCLKCFG register. The PLL has two sources of
reference clock as an input: the main oscillator (MOSC) or the precision internal oscillator (PIOSC).
The PLL input select is specified by PLLSRC. If the PLL VCO output is not selected as the source
of SysClk then the following reference clocks can be programmed as an input:

■ Main Oscillator (MOSC)

■ Precision Internal Oscillator (PIOSC)

■ Low-Frequency Internal Oscillator (LFIOSC)

■ Hibernation Module Real-Time Oscillator Source (RTCOSC): The source of this signal can be
either a 32.768-kHz oscillator source, an external 32.768-kHz clock source or the internal

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Hibernation Module Low-Frequency Oscillator (HIBLFIOSC). If this clock source is selected, it

has to be enabled in the Hibernation Module as well.

The selection of these alternate sources is through the OSCSRC field in the RSCLKCFG register.

5.2.6.2 Sleep Mode

In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and
the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered
by the Cortex-M4F core executing a WFI (Wait for Interrupt) instruction. Any properly configured
interrupt event in the system brings the processor back into Run mode. See “Power
Management” on page 126 for more details.
Peripherals are clocked that are enabled in the peripheral-specific SCGC registers when auto-clock
gating is enabled or the peripheral-specific RCGC registers when the auto-clock gating is disabled.
The system clock has the same source and frequency as that during Run mode.
The option to use the PLL VCO or an alternate oscillator source such as MOSC, PIOSC, Hibernation
Module real time clock, or the LFIOSC is the same as described in Run Mode. The RSCLKCFG
register programming applies to Sleep Mode.
Additional sleep modes are available that lower the power consumption of the SRAM and Flash
memory. However, the lower power consumption modes have slower sleep and wake-up times.

Caution – If the Cortex-M4F Debug Access Port (DAP) has been enabled, and the device wakes from
a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their Run mode configuration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.

5.2.6.3 Deep-Sleep Mode

In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Deep-Sleep mode clock configuration) in addition to the processor clock being stopped. An interrupt
returns the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered
on request from the code. Deep-Sleep mode is entered by first setting the SLEEPDEEP bit in the
System Control (SYSCTRL) register (see page 173) and then executing a WFI instruction. Any
properly configured interrupt event in the system brings the processor back into Run mode. See
“Power Management” on page 126 for more details.
Note: If the Debug Access Port is enabled in Run Mode and attempts to transition into Deep-Sleep
mode, the device is prevented from entering Deep-Sleep.
The Cortex-M4F processor core and the memory subsystem are not clocked in Deep-Sleep mode.
Peripherals are clocked that are enabled in the peripheral-specific DCGC registers when auto-clock
gating is enabled or the peripheral-specific RCGC registers when auto-clock gating is disabled. The
system clock source is specified in the DSCLKCFG register. When the DSCLKCFG register is used,
the internal oscillator source is powered up, if necessary, and other clocks are powered down. If
the PLL is running at the time of the WFI instruction, hardware shuts down the PLL for power savings.

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For further power savings the PIOSC can be disabled through the PIOSCPD bit in the DSCLKCFG
register. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the
source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had
been stopped during the Deep-Sleep duration. If the PIOSC is used as the PLL reference clock
source, it may continue to provide the clock during Deep-Sleep. See page 281.
Note: If the MOSC is chosen as the Deep-Sleep clock source in the DSCLKCFG register, the
MOSC must also be configured as the Run and Sleep clock source in the RSCLKCFG
register prior to entering Deep Sleep. If the PIOSC, LFIOSC, or Hibernation RTC Module
Oscillator (HIBLFIOSC or 32-kHz crystal) is configured as the Run and Sleep clock source
in the RSCLKFCFG register, and the MOSC is configured as the Deep-Sleep clock source
in the DSCLKCFG register, then two outcomes are possible:

■ If the PIOSC is still powered in Deep Sleep (using the PIOSCPD bit in the DSCLKCFG
register) then the PIOSC is utilized as the clock source when entering Deep Sleep and
the device enters and exits the Deep-Sleep state normally. The MOSC is not used as
the clock source in Deep Sleep.

■ If the PIOSC has been configured to be powered down in Deep Sleep, then the device
can enter the Deep-Sleep state, but cannot exit properly. This situation can be avoided
by programming the MOSC as the Run and Sleep clock source in the RSCLKCFG
register prior to entering Deep Sleep.

To provide the lowest possible Deep-Sleep power consumption as well the ability to wake the
processor from a peripheral without reconfiguring the peripheral for a change in clock, some of the
communications modules have a Clock Control register at offset 0xFC8 in the module register space.
The CS field in the Clock Control register allows the user to select the PIOSC or ALTCLK as the
clock source for the module's baud clock. When the microcontroller enters Deep-Sleep mode, the
PIOSC or ALTCLK becomes the source for the module clock as well, which allows the transmit and
receive FIFOs to continue operation while the part is in Deep-Sleep. Figure 5-6 on page 242 shows
how the clocks are selected.

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Figure 5-6. Module Clock Selection

Clock Control Register

PIOSC or
1
ALTCLK
Baud Clock

Deep Sleep

1
Module Clock

System Clock 0

Additional power management modes are available that lower the power consumption of the
peripheral memory, Flash, and SRAM memory. However, the lower power consumption modes
have slower deep-sleep and wake-up times.
Note: If one or more wait states are configured for Run Mode, then when the device enters
Deep-Sleep mode, it will achieve its lowest possible current. If there are no wait states
applied in Run mode, then lowest possible current is not achieved.

5.2.6.4 Dynamic Power Management

In addition to the Sleep and Deep-Sleep modes and the clock gating for the on-chip modules, there
are several additional power mode options that allow the LDO, Flash memory, and SRAM into
different levels of power savings while in Sleep or Deep-Sleep modes. In addition, software has the
ability to control the LDO settings to gain a power advantage when running at slower speeds. Note
that these features may not be available on all devices; the System Properties (SYSPROP) register
provides information on whether a mode is supported on a given MCU. The following registers
provide these capabilities:

■ Peripheral Power Control (PCx): Controls power to peripheral if that peripheral has the ability
to respond to a power request.

■ Peripheral Memory Power Control (xMPC): Provides power control to some the peripheral
memory arrays.

■ LDO Sleep Power Control (LDOSPCTL): Controls the LDO value in Sleep mode

■ LDO Deep-Sleep Power Control (LDODPCTL): Controls the LDO value in Deep-Sleep mode

■ LDO Sleep Power Calibration (LDOSPCAL): Provides factory recommendations for the LDO
value in Sleep mode

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■ LDO Deep-Sleep Power Calibration (LDODPCAL): Provides factory recommendations for the
LDO value in Deep-Sleep mode

■ Sleep Power Configuration (SLPPWRCFG): Controls the power saving modes for Flash memory
and SRAM in Sleep mode

■ Deep-Sleep Power Configuration (DSLPPWRCFG): Controls the power saving modes for
Flash memory and SRAM in Deep-Sleep mode

■ Deep-Sleep Clock Configuration (DSCLKCFG): Controls the clocking in Deep-Sleep mode

■ Sleep / Deep-Sleep Power Mode Status (SDPMST): Provides status information on the various
power saving events

Peripheral Power Control

The Peripheral Power Control (PCx) registers reside at offset 0x900 in the System Control module
register space. For modules that reside in a separate power domain, the user has the capability to
power down the module by setting the appropriate Pn bit to 0x0. This configuration provides the
lowest power consumption state of the module. Currently the following registers can be programmed
to disable power to the module:

■ PCCAN register

■ PCEMAC register

■ PCEPHY register

■ PCUSB register

■ PCCCM register

Modification to other PCx registers have no effect, since they are not on their own power domain.

Peripheral Memory Power Control

When Deep-Sleep is entered, users have the capability to reduce power further in peripheral modules
which have their own associated memory array. Many of these peripherals can be programmed to
enable a low-power retention mode or a power down of their associated peripheral SRAM array. If
retention is supported and the PWRCTL bit field of the module's xMPC register is programmed to
0x1, the associated peripheral SRAM memory array is put in retention mode in which no accesses
can be performed. When the PWRCTL bit is set to 0x0 in Deep-Sleep mode, the memory is powered
off, the contents are lost and the SRAM is not accessible. The peripheral's Power Domain Status
(xPDS) can be read to determine the status of the peripheral's memory array as well as the
peripheral's current power domain status. The table below lists the capabilities of peripherals with
SRAM arrays during low power modes.

Table 5-8. Peripheral Memory Power Control

Module Memory Retention Capability? Memory Array Power Down Capability?
USB Yes Yes
EMAC No Yes
(only when power domain is off, PCEMAC register = 0x0)
CAN No Yes

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LDO Power Control

Note: While the device is connected through JTAG, the LDO control settings for Sleep or
Deep-Sleep are not available and will not be applied.
Software can configure the LDOSPCTL register (see page 300) and/or the LDODPCTL register (see
page 303) to dynamically raise or lower the LDO voltage in Sleep and Deep-Sleep mode depending
on whether an increase in performance or reduction in power consumption is required. The VLDO
field in the LDOSPCTL register is set to 1.2 V as default. The LDODPCTL register is set to an LDO
voltage of 0.9 V as default. If an application requires performance over power consumption in
Deep-Sleep, the Deep-Sleep LDO voltage can be configured to a higher voltage than 0.9 V during
System Control initialization by setting the VADJEN bit and programming the VLDO field of the
LDODPCTL register.
Before the LDO level is lowered in Sleep or Deep-Sleep, the system clock must be configured to
an acceptable frequency in the RSCLKCFG register for Sleep mode and in DSLPCLKCFG for
Deep-Sleep mode. The following table shows the maximum System Clock and PIOSC frequency
with respect to the LDO voltage.

Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
Operating Voltage (LDO) Maximum System Clock Frequency PIOSC
1.2 120 MHz 16 MHz
0.9 30 MHz 16 MHz

The LDO Power Calibration registers, LDOSPCAL and LDODPCAL, provide suggested values for
the LDO in the various modes. If software requests an LDO value that is too low or too high, the
value is not accepted and an error is reported in the SDPMST register.
Note: When using the USB, Ethernet, EPI, and QSSI interfaces, the LDO must be configured to
1.2 V.

Flash Memory and SRAM Power Control

During Sleep or Deep-Sleep mode, Flash memory can be in either the default active mode or the
low power mode; SRAM can be in the default active mode, standby mode, or low power mode. The
active mode in each case provides the fastest times to sleep and wake up, but consumes more
power. Low power mode provides the lowest power consumption, but takes longer to sleep and
wake up.
The SRAM can be programmed to prohibit any power management by configuring the SRAMPM bit
in the Sleep Power Configuration (SLPPWRCFG) register. This configuration operates in the
®
same way that legacy Stellaris devices operate and provides the fastest sleep and wake-up times,
but consumes the most power while in Sleep and Deep-Sleep mode.
The following power saving options are available in Sleep and Deep-Sleep modes:

■ The clocks can be gated according to the settings in the peripheral-specific SCGC or DCGC
registers.

■ In Deep-Sleep mode, the clock source can be changed and the PIOSC can be powered off (if
no active peripheral requires it) using the DSCLKCFG register. These options are not available
for Sleep mode.

■ The LDO voltage can be changed using the LDOSPCTL or LDODPCTL register.

■ The Flash memory can be put into low power mode.

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■ The SRAM can be put into standby or low power mode.

For typical power consumption and sleep/wake-up times, refer to “Current Consumption ” on page 1880
and “Sleep Modes” on page 1843.
The SDPMST register provides results on the Dynamic Power Management command issued. It
also has some real time status that can be viewed by a debugger or the core if it is running. These
events do not trigger an interrupt and are meant to provide information to help tune software for
power management. The status register gets written at the beginning of every Dynamic Power
Management event request that provides error checking. There is no mechanism to clear the bits;
they are overwritten on the next event. The data is real time and there is no event to register that
information.

5.2.6.5 Hibernation Mode

In this mode, the power supplies are turned off to the main part of the microcontroller and only the
Hibernation module's circuitry is active. An external wake event or RTC event is required to bring
the microcontroller back to Run mode. The Cortex-M4F processor and peripherals outside of the
Hibernation module see a normal "power on" sequence and the processor starts running code. If
the HIB module has been put in hibernation mode and a reset occurs, the reset handler should
check the HIB Raw Interrupt Status (HIBRIS) register in the HIB module to determine the cause
of the reset.

5.2.6.6 Hardware System Service Request

The Hardware System Service Request (HSSR) register is used to issue a request that returns
a device to factory settings. An HSSR consists of writing the appropriate key and data structure
address offset to the HSSR register in the System Control Module. Any HSSR initiates a reset event
as the first event in the process. Then the HSSR register is evaluated.
To write to the HSSR register the KEY field must be set to 0xCA. The CDOFF field in the HSSR
register can have one of the following three values:

■ 0x00.0000 – No request and/or the previous request completed successfully

■ 0xFF.FFFF – No request and the previous request failed

■ Anything else – The offset into SRAM of a HSSR request structure

During the HSSR routine, if anything else is seen in the CDOFF field, then the offset is examined for
validity and the structure it points to is examined for validity. If either is invalid, the request has failed
and 0xFF.FFFF is written to the CDOFF field.
The offset is valid if all the following conditions are met:

■ The CDOFF value is word aligned (that is, the two LSBs are both zero)

■ The CDOFF value is at least 0x2000.4000

■ The CDOFF value is at most 0x2003.FFF0

Once a valid HSSR offset is determined, the following structure is examined in the SRAM that is
indicated by the CDOFF field in the HSSR register. In order to initiate a return-to-factory settings
function, the data structure must be as follows:

■ Request (32 bits) = 0xFEED.0001

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■ Data 1 (32 bits) = 0x0201.0100

■ Data 2 (32 bits) = 0x0D08.0503

■ Data 3 (32 bits) = 0x5937.2215

If the data bytes are correct, then the device is returned to factory condition. During the
return-to-factory settings function, the following events occur:

■ The RAM is erased in the Hibernation module

■ The system SRAM is erased

■ The FMPPEn registers are set to 0xFFFF.FFFF (to allow a Flash erase operation to occur)

■ The EEPROM pages are erased

■ A mass-erase of the flash array occurs

■ The BOOTCFG register is written with 0xFFFF.FFFE

Once the return-to-factory settings sequence is completed, the CDOFF field of the HSSR register is
written with 0x00.0000, indicating a successful completion and activating a system reset.

5.3 Initialization and Configuration

The PLL is configured using direct register writes to the PLLFREQn, MEMTIM0, and PLLSTAT
registers. The steps for initializing the system clock from POR to use the PLL from the main oscillator
is as follows:

1. Once POR has completed, the PIOSC is acting as the system clock.

2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register.

3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required,
clear the PWRDN bit and wait for the MOSCPUPRIS bit to be set in the Raw Interrupt Status
(RIS), indicating MOSC crystal mode is ready.

4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0.

5. If the application also requires the MOSC to be the deep-sleep clock source, then program the
DSOSCSRC field in the DSCLKCFG register to 0x3.

6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to
the configure the desired VCO frequency setting.

7. Write the MEMTIM0 register to correspond to the new system clock setting.

8. Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point
(or that a timeout period has passed and lock has failed, in which case an error condition exists
and this sequence is abandoned and error processing is initiated).

9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU
bit.

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If it is necessary to keep the MOSC powered on during automatic (deep-sleep) or accidental power
down, then the MOSCDPD bit should be set to 0x1. Otherwise, if the MOSCDPD bit is set to 0x0, the
MOSC is powered off when deep-sleep is entered or automatic power down occurs. The following
table describes the relationship between the PWRDN bit in the MOSCCTL register and the MOSCDPD
bit in the DSCLKCFG register:

Table 5-10. MOSC Configurations

PWRDN bit MOSCDPD field Result
0 0 MOSC is powered ON in run and sleep modes, but is disabled in accidental power down,
when the PWRDN bit is set in the MOSCCTL register, or in deep-sleep mode only if it is not
the deep-sleep clock source (DSOSCSRC !==0x3).
0 1 MOSC is powered and running in run, sleep and deep-sleep modes.
1 0 MOSC is powered off, and does not run in any mode. Please note, that in this configuration,
when the MOSC is disabled, the MOSC must not be chosen as a clock source or indeterminate
results occur.
1 1 MOSC runs and does not disable itself in run, sleep, and deep-sleep modes regardless of
the fact that the PWRDN bit is set.

Note: The MOSCDPD bit has an effect in all modes of operation

To change the system clock frequency by changing its corresponding PSYSDIV or OSYSDIV value,
a user must ensure timing parameters to memory are within range through the following steps:

1. If the change in system clock frequency changes the operational range of the timing parameters,
the MEMTIM0 register must be updated. If so, write the timing configuration register, MEMTIM0,
setting the value to correspond to the final SYSCLK frequency (fVCO/new SYSDIV or fOSC).
Otherwise the MEMTIM0 register should not be changed.

2. Write the RSCLKCFG register's PSYSDIV value and MEMTIMU bit if the MEMTIM0 register is
updated in the first step. The new SYSDIV is now in effect.

5.4 Register Map

Table 5-11 on page 247 lists the System Control registers, grouped by function. The offset listed is
a hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 600.

Table 5-11. System Control Register Map

See
Offset Name Type Reset Description
page

0x000 DID0 RO - Device Identification 0 255

0x004 DID1 RO 0x101F.C06E Device Identification 1 257

0x038 PTBOCTL RW 0x0000.0003 Power-Temp Brown Out Control 259

0x050 RIS RO 0x0000.0000 Raw Interrupt Status 261

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Table 5-11. System Control Register Map (continued)

See
Offset Name Type Reset Description
page

0x054 IMC RW 0x0000.0000 Interrupt Mask Control 263

0x058 MISC RW1C 0x0000.0000 Masked Interrupt Status and Clear 265

0x05C RESC RW 0x0000.0002 Reset Cause 267

0x060 PWRTC RW1C 0x0000.0000 Power-Temperature Cause 270

0x064 NMIC RW 0x0000.0000 NMI Cause Register 271

0x07C MOSCCTL RW 0x0000.000C Main Oscillator Control 273

0x0B0 RSCLKCFG RW 0x0000.0000 Run and Sleep Mode Configuration Register 275

Memory Timing Parameter Register 0 for Main Flash and

0x0C0 MEMTIM0 RW 0x0030.0030 277
EEPROM

0x138 ALTCLKCFG RW 0x0000.0000 Alternate Clock Configuration 280

0x144 DSCLKCFG RW 0x0000.0000 Deep Sleep Clock Configuration Register 281

0x148 DIVSCLK RW 0x0000.0000 Divisor and Source Clock Configuration 284

0x14C SYSPROP RO 0x0003.1F31 System Properties 286

0x150 PIOSCCAL RW 0x0000.0000 Precision Internal Oscillator Calibration 289

0x154 PIOSCSTAT RO 0x0040.0040 Precision Internal Oscillator Statistics 291

0x160 PLLFREQ0 RW 0x0000.0000 PLL Frequency 0 292

0x164 PLLFREQ1 RW 0x0000.0000 PLL Frequency 1 293

0x168 PLLSTAT RO 0x0000.0000 PLL Status 294

0x188 SLPPWRCFG RW 0x0000.0000 Sleep Power Configuration 295

0x18C DSLPPWRCFG RW 0x0000.0000 Deep-Sleep Power Configuration 297

0x1A0 NVMSTAT RO 0x0000.0001 Non-Volatile Memory Information 299

0x1B4 LDOSPCTL RW 0x0000.0018 LDO Sleep Power Control 300

0x1B8 LDOSPCAL RO 0x0000.1818 LDO Sleep Power Calibration 302

0x1BC LDODPCTL RW 0x0000.0012 LDO Deep-Sleep Power Control 303

0x1C0 LDODPCAL RO 0x0000.1212 LDO Deep-Sleep Power Calibration 305

0x1CC SDPMST RO 0x0000.0000 Sleep / Deep-Sleep Power Mode Status 306

0x1D8 RESBEHAVCTL RW 0xFFFF.FFFF Reset Behavior Control Register 309

0x1F4 HSSR RW 0x0000.0000 Hardware System Service Request 311

0x280 USBPDS RO 0x0000.003F USB Power Domain Status 312

0x284 USBMPC RW 0x0000.0003 USB Memory Power Control 313

0x288 EMACPDS RO 0x0000.003F Ethernet MAC Power Domain Status 314

0x28C EMACMPC RW 0x0000.0003 Ethernet MAC Memory Power Control 315

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Table 5-11. System Control Register Map (continued)

See
Offset Name Type Reset Description
page

0x298 CAN0PDS RO 0x0000.003F CAN 0 Power Domain Status 316

0x29C CAN0MPC RW 0x0000.0003 CAN 0 Memory Power Control 317

0x2A0 CAN1PDS RO 0x0000.003F CAN 1 Power Domain Status 318

0x2A4 CAN1MPC RW 0x0000.0003 CAN 1 Memory Power Control 319

0x300 PPWD RO 0x0000.0003 Watchdog Timer Peripheral Present 320

0x304 PPTIMER RO 0x0000.00FF 16/32-Bit General-Purpose Timer Peripheral Present 321

0x308 PPGPIO RO 0x0000.7FFF General-Purpose Input/Output Peripheral Present 323

0x30C PPDMA RO 0x0000.0001 Micro Direct Memory Access Peripheral Present 326

0x310 PPEPI RO 0x0000.0001 EPI Peripheral Present 327

0x314 PPHIB RO 0x0000.0001 Hibernation Peripheral Present 328

Universal Asynchronous Receiver/Transmitter Peripheral

0x318 PPUART RO 0x0000.00FF 329
Present

0x31C PPSSI RO 0x0000.000F Synchronous Serial Interface Peripheral Present 331

0x320 PPI2C RO 0x0000.03FF Inter-Integrated Circuit Peripheral Present 333

0x328 PPUSB RO 0x0000.0001 Universal Serial Bus Peripheral Present 335

0x330 PPEPHY RO 0x0000.0001 Ethernet PHY Peripheral Present 336

0x334 PPCAN RO 0x0000.0003 Controller Area Network Peripheral Present 337

0x338 PPADC RO 0x0000.0003 Analog-to-Digital Converter Peripheral Present 338

0x33C PPACMP RO 0x0000.0001 Analog Comparator Peripheral Present 339

0x340 PPPWM RO 0x0000.0001 Pulse Width Modulator Peripheral Present 340

0x344 PPQEI RO 0x0000.0001 Quadrature Encoder Interface Peripheral Present 341

0x348 PPLPC RO 0x0000.0000 Low Pin Count Interface Peripheral Present 342

Platform Environment Control Interface Peripheral

0x350 PPPECI RO 0x0000.0000 343
Present

0x354 PPFAN RO 0x0000.0000 Fan Control Peripheral Present 344

0x358 PPEEPROM RO 0x0000.0001 EEPROM Peripheral Present 345

32/64-Bit Wide General-Purpose Timer Peripheral

0x35C PPWTIMER RO 0x0000.0000 346
Present

0x370 PPRTS RO 0x0000.0000 Remote Temperature Sensor Peripheral Present 347

0x374 PPCCM RO 0x0000.0001 CRC Module Peripheral Present 348

0x390 PPLCD RO 0x0000.0000 LCD Peripheral Present 349

0x398 PPOWIRE RO 0x0000.0000 1-Wire Peripheral Present 350

0x39C PPEMAC RO 0x0000.0001 Ethernet MAC Peripheral Present 351

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Table 5-11. System Control Register Map (continued)

See
Offset Name Type Reset Description
page

0x3A0 PPPRB RO 0x0000.0000 Power Regulator Bus Peripheral Present 352

0x3A4 PPHIM RO 0x0000.0000 Human Interface Master Peripheral Present 353

0x500 SRWD RW 0x0000.0000 Watchdog Timer Software Reset 354

0x504 SRTIMER RW 0x0000.0000 16/32-Bit General-Purpose Timer Software Reset 355

0x508 SRGPIO RW 0x0000.0000 General-Purpose Input/Output Software Reset 357

0x50C SRDMA RW 0x0000.0000 Micro Direct Memory Access Software Reset 360

0x510 SREPI RW 0x0000.0000 EPI Software Reset 361

0x514 SRHIB RW 0x0000.0000 Hibernation Software Reset 362

Universal Asynchronous Receiver/Transmitter Software

0x518 SRUART RW 0x0000.0000 363
Reset

0x51C SRSSI RW 0x0000.0000 Synchronous Serial Interface Software Reset 365

0x520 SRI2C RW 0x0000.0000 Inter-Integrated Circuit Software Reset 367

0x528 SRUSB RW 0x0000.0000 Universal Serial Bus Software Reset 369

0x530 SREPHY RW 0x0000.0000 Ethernet PHY Software Reset 370

0x534 SRCAN RW 0x0000.0000 Controller Area Network Software Reset 371

0x538 SRADC RW 0x0000.0000 Analog-to-Digital Converter Software Reset 372

0x53C SRACMP RW 0x0000.0000 Analog Comparator Software Reset 373

0x540 SRPWM RW 0x0000.0000 Pulse Width Modulator Software Reset 374

0x544 SRQEI RW 0x0000.0000 Quadrature Encoder Interface Software Reset 375

0x558 SREEPROM RW 0x0000.0000 EEPROM Software Reset 376

0x574 SRCCM RW 0x0000.0000 CRC Module Software Reset 377

0x59C SREMAC RW 0x0000.0000 Ethernet MAC Software Reset 378

0x600 RCGCWD RW 0x0000.0000 Watchdog Timer Run Mode Clock Gating Control 379

16/32-Bit General-Purpose Timer Run Mode Clock Gating

0x604 RCGCTIMER RW 0x0000.0000 380
Control

General-Purpose Input/Output Run Mode Clock Gating

0x608 RCGCGPIO RW 0x0000.0000 382
Control

Micro Direct Memory Access Run Mode Clock Gating

0x60C RCGCDMA RW 0x0000.0000 385
Control

0x610 RCGCEPI RW 0x0000.0000 EPI Run Mode Clock Gating Control 386

0x614 RCGCHIB RW 0x0000.0001 Hibernation Run Mode Clock Gating Control 387

Universal Asynchronous Receiver/Transmitter Run Mode

0x618 RCGCUART RW 0x0000.0000 388
Clock Gating Control

Synchronous Serial Interface Run Mode Clock Gating

0x61C RCGCSSI RW 0x0000.0000 390
Control

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Table 5-11. System Control Register Map (continued)

See
Offset Name Type Reset Description
page

0x620 RCGCI2C RW 0x0000.0000 Inter-Integrated Circuit Run Mode Clock Gating Control 391

0x628 RCGCUSB RW 0x0000.0000 Universal Serial Bus Run Mode Clock Gating Control 393

0x630 RCGCEPHY RW 0x0000.0000 Ethernet PHY Run Mode Clock Gating Control 394

0x634 RCGCCAN RW 0x0000.0000 Controller Area Network Run Mode Clock Gating Control 395

Analog-to-Digital Converter Run Mode Clock Gating

0x638 RCGCADC RW 0x0000.0000 396
Control

0x63C RCGCACMP RW 0x0000.0000 Analog Comparator Run Mode Clock Gating Control 397

0x640 RCGCPWM RW 0x0000.0000 Pulse Width Modulator Run Mode Clock Gating Control 398

Quadrature Encoder Interface Run Mode Clock Gating

0x644 RCGCQEI RW 0x0000.0000 399
Control

0x658 RCGCEEPROM RW 0x0000.0000 EEPROM Run Mode Clock Gating Control 400

0x674 RCGCCCM RW 0x0000.0000 CRC Module Run Mode Clock Gating Control 401

0x69C RCGCEMAC RW 0x0000.0000 Ethernet MAC Run Mode Clock Gating Control 402

0x700 SCGCWD RW 0x0000.0000 Watchdog Timer Sleep Mode Clock Gating Control 403

16/32-Bit General-Purpose Timer Sleep Mode Clock

0x704 SCGCTIMER RW 0x0000.0000 404
Gating Control

General-Purpose Input/Output Sleep Mode Clock Gating

0x708 SCGCGPIO RW 0x0000.0000 406
Control

Micro Direct Memory Access Sleep Mode Clock Gating

0x70C SCGCDMA RW 0x0000.0000 409
Control

0x710 SCGCEPI RW 0x0000.0000 EPI Sleep Mode Clock Gating Control 410

0x714 SCGCHIB RW 0x0000.0001 Hibernation Sleep Mode Clock Gating Control 411

Universal Asynchronous Receiver/Transmitter Sleep

0x718 SCGCUART RW 0x0000.0000 412
Mode Clock Gating Control

Synchronous Serial Interface Sleep Mode Clock Gating

0x71C SCGCSSI RW 0x0000.0000 414
Control

0x720 SCGCI2C RW 0x0000.0000 Inter-Integrated Circuit Sleep Mode Clock Gating Control 415

0x728 SCGCUSB RW 0x0000.0000 Universal Serial Bus Sleep Mode Clock Gating Control 417

0x730 SCGCEPHY RW 0x0000.0000 Ethernet PHY Sleep Mode Clock Gating Control 418

Controller Area Network Sleep Mode Clock Gating

0x734 SCGCCAN RW 0x0000.0000 419
Control

Analog-to-Digital Converter Sleep Mode Clock Gating

0x738 SCGCADC RW 0x0000.0000 420
Control

0x73C SCGCACMP RW 0x0000.0000 Analog Comparator Sleep Mode Clock Gating Control 421

0x740 SCGCPWM RW 0x0000.0000 Pulse Width Modulator Sleep Mode Clock Gating Control 422

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Table 5-11. System Control Register Map (continued)

See
Offset Name Type Reset Description
page

Quadrature Encoder Interface Sleep Mode Clock Gating

0x744 SCGCQEI RW 0x0000.0000 423
Control

0x758 SCGCEEPROM RW 0x0000.0000 EEPROM Sleep Mode Clock Gating Control 424

0x774 SCGCCCM RW 0x0000.0000 CRC Module Sleep Mode Clock Gating Control 425

0x79C SCGCEMAC RW 0x0000.0000 Ethernet MAC Sleep Mode Clock Gating Control 426

0x800 DCGCWD RW 0x0000.0000 Watchdog Timer Deep-Sleep Mode Clock Gating Control 427

16/32-Bit General-Purpose Timer Deep-Sleep Mode

0x804 DCGCTIMER RW 0x0000.0000 428
Clock Gating Control

General-Purpose Input/Output Deep-Sleep Mode Clock

0x808 DCGCGPIO RW 0x0000.0000 430
Gating Control

Micro Direct Memory Access Deep-Sleep Mode Clock

0x80C DCGCDMA RW 0x0000.0000 433
Gating Control

0x810 DCGCEPI RW 0x0000.0000 EPI Deep-Sleep Mode Clock Gating Control 434

0x814 DCGCHIB RW 0x0000.0001 Hibernation Deep-Sleep Mode Clock Gating Control 435

Universal Asynchronous Receiver/Transmitter

0x818 DCGCUART RW 0x0000.0000 436
Deep-Sleep Mode Clock Gating Control

Synchronous Serial Interface Deep-Sleep Mode Clock

0x81C DCGCSSI RW 0x0000.0000 438
Gating Control

Inter-Integrated Circuit Deep-Sleep Mode Clock Gating

0x820 DCGCI2C RW 0x0000.0000 439
Control

Universal Serial Bus Deep-Sleep Mode Clock Gating

0x828 DCGCUSB RW 0x0000.0000 441
Control

0x830 DCGCEPHY RW 0x0000.0000 Ethernet PHY Deep-Sleep Mode Clock Gating Control 442

Controller Area Network Deep-Sleep Mode Clock Gating

0x834 DCGCCAN RW 0x0000.0000 443
Control

Analog-to-Digital Converter Deep-Sleep Mode Clock

0x838 DCGCADC RW 0x0000.0000 444
Gating Control

Analog Comparator Deep-Sleep Mode Clock Gating

0x83C DCGCACMP RW 0x0000.0000 445
Control

Pulse Width Modulator Deep-Sleep Mode Clock Gating

0x840 DCGCPWM RW 0x0000.0000 446
Control

Quadrature Encoder Interface Deep-Sleep Mode Clock

0x844 DCGCQEI RW 0x0000.0000 447
Gating Control

0x858 DCGCEEPROM RW 0x0000.0000 EEPROM Deep-Sleep Mode Clock Gating Control 448

0x874 DCGCCCM RW 0x0000.0000 CRC Module Deep-Sleep Mode Clock Gating Control 449

0x89C DCGCEMAC RW 0x0000.0000 Ethernet MAC Deep-Sleep Mode Clock Gating Control 450

0x900 PCWD RW 0x0000.0003 Watchdog Timer Power Control 451

0x904 PCTIMER RW 0x0000.00FF 16/32-Bit General-Purpose Timer Power Control 453

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Table 5-11. System Control Register Map (continued)

See
Offset Name Type Reset Description
page

0x908 PCGPIO RW 0x0000.7FFF General-Purpose Input/Output Power Control 456

0x90C PCDMA RW 0x0000.0001 Micro Direct Memory Access Power Control 461

0x910 PCEPI RW 0x0000.0001 External Peripheral Interface Power Control 463

0x914 PCHIB RW 0x0000.0001 Hibernation Power Control 465

Universal Asynchronous Receiver/Transmitter Power

0x918 PCUART RW 0x0000.00FF 467
Control

0x91C PCSSI RW 0x0000.000F Synchronous Serial Interface Power Control 470

0x920 PCI2C RW 0x0000.03FF Inter-Integrated Circuit Power Control 472

0x928 PCUSB RW 0x0000.0001 Universal Serial Bus Power Control 476

0x930 PCEPHY RW 0x0000.0000 Ethernet PHY Power Control 478

0x934 PCCAN RW 0x0000.0003 Controller Area Network Power Control 480

0x938 PCADC RW 0x0000.0003 Analog-to-Digital Converter Power Control 482

0x93C PCACMP RW 0x0000.0001 Analog Comparator Power Control 484

0x940 PCPWM RW 0x0000.0001 Pulse Width Modulator Power Control 486

0x944 PCQEI RW 0x0000.0001 Quadrature Encoder Interface Power Control 488

0x958 PCEEPROM RW 0x0000.0001 EEPROM Power Control 490

0x974 PCCCM RW 0x0000.0001 CRC Module Power Control 492

0x99C PCEMAC RW 0x0000.0001 Ethernet MAC Power Control 494

0xA00 PRWD RO 0x0000.0000 Watchdog Timer Peripheral Ready 496

0xA04 PRTIMER RO 0x0000.0000 16/32-Bit General-Purpose Timer Peripheral Ready 497

0xA08 PRGPIO RO 0x0000.0000 General-Purpose Input/Output Peripheral Ready 499

0xA0C PRDMA RO 0x0000.0000 Micro Direct Memory Access Peripheral Ready 502

0xA10 PREPI RO 0x0000.0000 EPI Peripheral Ready 503

0xA14 PRHIB RO 0x0000.0001 Hibernation Peripheral Ready 504

Universal Asynchronous Receiver/Transmitter Peripheral

0xA18 PRUART RO 0x0000.0000 505
Ready

0xA1C PRSSI RO 0x0000.0000 Synchronous Serial Interface Peripheral Ready 507

0xA20 PRI2C RO 0x0000.0000 Inter-Integrated Circuit Peripheral Ready 509

0xA28 PRUSB RO 0x0000.0000 Universal Serial Bus Peripheral Ready 512

0xA30 PREPHY RO 0x0000.0000 Ethernet PHY Peripheral Ready 513

0xA34 PRCAN RO 0x0000.0000 Controller Area Network Peripheral Ready 514

0xA38 PRADC RO 0x0000.0000 Analog-to-Digital Converter Peripheral Ready 515

0xA3C PRACMP RO 0x0000.0000 Analog Comparator Peripheral Ready 516

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Table 5-11. System Control Register Map (continued)

See
Offset Name Type Reset Description
page

0xA40 PRPWM RO 0x0000.0000 Pulse Width Modulator Peripheral Ready 517

0xA44 PRQEI RO 0x0000.0000 Quadrature Encoder Interface Peripheral Ready 518

0xA58 PREEPROM RO 0x0000.0000 EEPROM Peripheral Ready 519

0xA74 PRCCM RO 0x0000.0000 CRC Module Peripheral Ready 520

0xA9C PREMAC RO 0x0000.0000 Ethernet MAC Peripheral Ready 521

0xF20 UNIQUEID0 RO - Unique ID 0 522

0xF24 UNIQUEID1 RO - Unique ID 1 522

0xF28 UNIQUEID2 RO - Unique ID 2 522

0xF2C UNIQUEID3 RO - Unique ID 3 522

5.5 System Control Register Descriptions (System Control Offset)

All addresses given are relative to the System Control base address of 0x400F.E000.

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Register 1: Device Identification 0 (DID0), offset 0x000

This register identifies the version of the microcontroller. Each microcontroller is uniquely identified
by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1
register. The MAJOR and MINOR bit fields indicate the die revision number. Combined, the MAJOR
and MINOR bit fields indicate the part revision number.

MAJOR Bitfield Value MINOR Bitfield Value Die Revision Part Revision
0x0 0x0 A0 1
0x0 0x1 A1 2
0x0 0x2 A2 3

Device Identification 0 (DID0)

Base 0x400F.E000
Offset 0x000
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved VER reserved CLASS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAJOR MINOR

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

30:28 VER RO 0x1 DID0 Version

This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):

Value Description
0x1 Second version of the DID0 register format.

27:24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:16 CLASS RO 0x0A Device Class

The CLASS field value identifies the internal design from which all mask
sets are generated for all microcontrollers in a particular product line.
The CLASS field value is changed for new product lines, for changes in
fab process (for example, a remap or shrink), or any case where the
MAJOR or MINOR fields require differentiation from prior microcontrollers.
The value of the CLASS field is encoded as follows (all other encodings
are reserved):

Value Description
0x0A Tiva™ Snowflake-class microcontrollers

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Bit/Field Name Type Reset Description

15:8 MAJOR RO - Major Revision

This field specifies the major revision number of the microcontroller.
The major revision reflects changes to base layers of the design. The
major revision number is indicated in the part number as a letter (A for
first revision, B for second, and so on). This field is encoded as follows:

Value Description
0x0 Revision A (initial device)
0x1 Revision B (first base layer revision)
0x2 Revision C (second base layer revision)

and so on.

7:0 MINOR RO - Minor Revision

This field specifies the minor revision number of the microcontroller.
The minor revision reflects changes to the metal layers of the design.
The MINOR field value is reset when the MAJOR field is changed. This
field is numeric and is encoded as follows:

Value Description
0x0 Initial device, or a major revision update.
0x1 First metal layer change.
0x2 Second metal layer change.

and so on.

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Register 2: Device Identification 1 (DID1), offset 0x004

This register identifies the device family, part number, temperature range, pin count, and package
type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the
DID0 register and the PARTNO field in the DID1 register.

Device Identification 1 (DID1)

Base 0x400F.E000
Offset 0x004
Type RO, reset 0x101F.C06E
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VER FAM PARTNO

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PINCOUNT reserved TEMP PKG ROHS QUAL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0

Bit/Field Name Type Reset Description

31:28 VER RO 0x1 DID1 Version

This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):

Value Description
0x0 Initial DID1 register format definition, indicating a Stellaris
LM3Snnn device.
0x1 Second version of the DID1 register format.

27:24 FAM RO 0x0 Family

This field provides the family identification of the device within the Tiva™
product portfolio. The value is encoded as follows (all other encodings
are reserved):

Value Description
0x0 Tiva™ C Series microcontrollers and legacy Stellaris
microcontrollers, that is, all devices with external part numbers
starting with TM4Cor LM3S.

23:16 PARTNO RO 0x1F Part Number

This field provides the part number of the device within the family. This
value indicates the TM4C1294NCPDT microcontroller.

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Bit/Field Name Type Reset Description

15:13 PINCOUNT RO 0x6 Package Pin Count

This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):

Value Description
0x0 reserved
0x1 reserved
0x2 100-pin LQFP package
0x3 64-pin LQFP package
0x4 144-pin LQFP package
0x5 157-pin BGA package
0x6 128-pin TQFP package
0x7 212-pin BGA package

12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 TEMP RO 0x3 Temperature Range

This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):

Value Description
0x0 Commercial temperature range
0x1 Industrial temperature range
0x2 Extended temperature range

4:3 PKG RO 0x1 Package Type

This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):

Value Description
0x0 reserved
0x1 QFP package
0x2 BGA package

2 ROHS RO 0x1 RoHS-Compliance

This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.

1:0 QUAL RO 0x2 Qualification Status

This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):

Value Description
0x0 Engineering Sample (unqualified)
0x1 Pilot Production (unqualified)
0x2 Fully Qualified

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Register 3: Power-Temp Brown Out Control (PTBOCTL), offset 0x038

This register determines, based on an individual event level, the appropriate next level of action (for
example, NONE, System Control Interrupt, NMI, or reset) when an event occurs.
Power-temperature event actions are directed to the core as a System Control Interrupt or NMI.
When a reset occurs, its behavior is controlled by the Reset Behavior Control (RESBEHAVCTL)
register. If one of the events configured in the PTBOCTL register causes a reset, it is registered as
a BOR interrupt in the Reset Cause (RESC) register.
Note: VDDA is the supply voltage to the analog components of the device and VDD is the supply
voltage to the digital components of the device.

Power-Temp Brown Out Control (PTBOCTL)

Base 0x400F.E000
Offset 0x038
Type RW, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VDDA_UBOR reserved VDD_UBOR

Type RO RO RO RO RO RO RW RW RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9:8 VDDA_UBOR RW 0 VDDA under BOR Event Action

An event occurs when VDDA trips under the VDDA_BOR0 threshold found
in Table 27-13 on page 1826.
This field determines the action to take on the event.

Value Description
0x0 No Action
0x1 System control interrupt
0x2 NMI
0x3 Reset

7:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

1:0 VDD_UBOR RW 0x3 VDD under BOR Event Action

An event occurs when VDD trips under the VDD_BOR threshold found in
Table 27-13 on page 1826.
This field determines the action to take on the event.

Value Description
0x0 No Action
0x1 System control interrupt
0x2 NMI
0x3 Reset

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Register 4: Raw Interrupt Status (RIS), offset 0x050

This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt
controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1
to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt
status bit.

Raw Interrupt Status (RIS)

Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MOSCPUPRIS reserved PLLLRIS reserved MOFRIS reserved BORRIS reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:9 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

8 MOSCPUPRIS RO 0 MOSC Power Up Raw Interrupt Status

Value Description
0 Sufficient time has not passed for the MOSC to reach the
expected frequency.
1 Sufficient time has passed for the MOSC to reach the expected
frequency. The value for this power-up time is indicated by
TMOSC_START.

This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC

register.

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 PLLLRIS RO 0 PLL Lock Raw Interrupt Status

Value Description
0 The PLL timer has not reached TREADY.
1 The PLL timer has reached TREADY indicating that sufficient time
has passed for the PLL to lock.

This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register.

5:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

3 MOFRIS RO 0 Main Oscillator Failure Raw Interrupt Status

Value Description
0 The main oscillator has not failed.
1 The MOSCIM bit in the MOSCCTL register is set and the main
oscillator has failed.

This bit is cleared by writing a 1 to the MOFMIS bit in the MISC register.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 BORRIS RO 0 Brown-Out Reset Raw Interrupt Status

Value Description
0 A brown-out condition is not currently active.
1 A brown-out condition is currently active.

The appropriate BOR bit in the PTBOCTL register must be set to an

interrupt (0x1) encoding in order to generate an interrupt.
This bit is cleared by writing a 1 to the BORMIS bit in the MISC register.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 5: Interrupt Mask Control (IMC), offset 0x054

This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by
a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the
corresponding bit in this register is set.

Interrupt Mask Control (IMC)

Base 0x400F.E000
Offset 0x054
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MOSCPUPIM reserved PLLLIM reserved MOFIM reserved BORIM reserved

Type RO RO RO RO RO RO RO RW RO RW RO RO RW RO RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:9 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

8 MOSCPUPIM RW 0 MOSC Power Up Interrupt Mask

Value Description
0 The MOSCPUPRIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the
MOSCPUPRIS bit in the RIS register is set.

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 PLLLIM RW 0 PLL Lock Interrupt Mask

Value Description
0 The PLLLRIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the PLLLRIS
bit in the RIS register is set.

5:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

3 MOFIM RW 0 Main Oscillator Failure Interrupt Mask

Value Description
0 The MOFRIS interrupt is suppressed and not sent to the interrupt
controller.
1 An interrupt is sent to the interrupt controller when the MOFRIS
bit in the RIS register is set.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 BORIM RW 0 Brown-Out Reset Interrupt Mask

Value Description
0 The BORRIS interrupt is suppressed and not sent to the interrupt
controller.
1 An interrupt is sent to the interrupt controller when the BORRIS
bit in the RIS register is set.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058

On a read, this register gives the current masked status value of the corresponding interrupt in the
Raw Interrupt Status (RIS) register. All of the bits are RW1C, thus writing a 1 to a bit clears the
corresponding raw interrupt bit in the RIS register (see page 261).

Masked Interrupt Status and Clear (MISC)

Base 0x400F.E000
Offset 0x058
Type RW1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MOSCPUPMIS reserved PLLLMIS reserved MOFMIS reserved BORMIS reserved

Type RO RO RO RO RO RO RO RW1C RO RW1C RO RO RW1C RO RW1C RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:9 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

8 MOSCPUPMIS RW1C 0 MOSC Power Up Masked Interrupt Status

Value Description
0 When read, a 0 indicates that sufficient time has not passed for
the MOSC PLL to lock.
A write of 0 has no effect on the state of this bit.
1 When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the MOSC PLL
to lock.
Writing a 1 to this bit clears it and also the MOSCPUPRIS bit in
the RIS register.

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 PLLLMIS RW1C 0 PLL Lock Masked Interrupt Status

Value Description
0 When read, a 0 indicates that sufficient time has not passed for
the PLL to lock.
A write of 0 has no effect on the state of this bit.
1 When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the PLL to lock.
Writing a 1 to this bit clears it and also the PLLLRIS bit in the
RIS register.

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Bit/Field Name Type Reset Description

5:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 MOFMIS RW1C 0 Main Oscillator Failure Masked Interrupt Status

Value Description
0 When read, a 0 indicates that the main oscillator has not failed.
A write of 0 has no effect on the state of this bit.
1 When read, a 1 indicates that an unmasked interrupt was
signaled because the main oscillator failed.
Writing a 1 to this bit clears it and also the MOFRIS bit in the
RIS register.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 BORMIS RW1C 0 BOR Masked Interrupt Status

Value Description
0 When read, a 0 indicates that a brown-out condition has not
occurred.
A write of 0 has no effect on the state of this bit.
1 When read, a 1 indicates that an unmasked interrupt was
signaled because of a brown-out condition.
Writing a 1 to this bit clears it and also the BORRIS bit in the
RIS register.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 7: Reset Cause (RESC), offset 0x05C

This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences. If a full POK-POR is initiated, the POR bit in the RESC
register is set and all other bits are cleared. If the WDOGn, BOR or EXTRES configuration fields are
set to 0x3 in the RESBEHAVCTL register and a simulated POR is initiated, the cause of the reset
is reflected in the RESC register.
Note: After the Reset Cause (RESC) register is read, the Hibernate Raw Interrupt Status
(HIBRIS) register in the Hibernation module must be evaluated to determine the full cause
of the reset. Although an external reset assertion or POR resulting from a wake event is
registered in the RESC register, the specific external wake source, including a low battery
detect, is only registered in the HIBRIS register.

Reset Cause (RESC)

Base 0x400F.E000
Offset 0x05C
Type RW, reset 0x0000.0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved MOSCFAIL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved HSSR reserved WDT1 SW WDT0 BOR POR EXT

Type RO RO RO RW RO RO RO RO RO RO RW RW RW RW RW RW
Reset 0 0 0 - 0 0 0 0 0 0 0 0 0 0 1 0

Bit/Field Name Type Reset Description

31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 MOSCFAIL RW - MOSC Failure Reset

Writing a 0 to this bit clears it.

Value Description
0 When read, this bit indicates that a MOSC failure has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1 When read, this bit indicates that the MOSC circuit was enabled
for clock validation and failed while the MOSCIM bit in the
MOSCCTL register is clear, generating a reset event.

15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

12 HSSR RW - HSSR Reset

Value Description
0 When read, this bit indicates that a HSSR request has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1 When read, this bit indicates that a HSSR request has generated
a reset.

11:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 WDT1 RW 0 Watchdog Timer 1 Reset

Value Description
0 When read, this bit indicates that Watchdog Timer 1 has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1 When read, this bit indicates that Watchdog Timer 1 timed out
and generated a reset.

4 SW RW 0 Software Reset

Value Description
0 When read, this bit indicates that a software reset has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1 When read, this bit indicates that a software reset has caused
a reset event.

3 WDT0 RW 0 Watchdog Timer 0 Reset

Value Description
0 When read, this bit indicates that Watchdog Timer 0 has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1 When read, this bit indicates that Watchdog Timer 0 timed out
and generated a reset.

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Bit/Field Name Type Reset Description

2 BOR RW 0 Brown-Out Reset

Note that for this bit, the BOR event that causes the Brown-Out Reset
can be any of the following:

■ The VDD supply drops below its acceptable operating range.

■ The VDDA supply drops below its acceptable operating range.

Value Description
0 When read, this bit indicates that a brown-out reset has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1 When read, this bit indicates that a brown-out reset has caused
a reset event.

1 POR RW 1 Power-On Reset

Value Description
0 When read, this bit indicates that a power-on reset has not
generated a reset.
Writing a 0 to this bit clears it.
1 When read, this bit indicates that a power-on reset has caused
a reset event.

0 EXT RW 0 External Reset

Value Description
0 When read, this bit indicates that an external reset (RST
assertion) has not caused a reset event since the previous
power-on reset.
Writing a 0 to this bit clears it.
1 When read, this bit indicates that an external reset (RST
assertion) has caused a reset event.

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Register 8: Power-Temperature Cause (PWRTC), offset 0x060

This register provides detailed information on the power subsystem event that caused a reset or
interrupt. The event sets the condition in this register without regard to whether it is used to generate
a System control Interrupt, Reset, NMI, or no action. The PTBOCTL register contains the action to
be taken on the specific events. The combination of the PWRTC register outputs and the PTBOCTL
register causes the appropriate interrupt or reset condition to occur and the corresponding status
bits to be set.

Power-Temperature Cause (PWRTC)

Base 0x400F.E000
Offset 0x060
Type RW1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VDDA_UBOR reserved VDD_UBOR

Type RO RO RO RO RO RO RO RO RO RO RO RW1C RO RO RO RW1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 VDDA_UBOR RW1C 0 VDDAUnder BOR Status

Value Description
0 VDDA has not tripped under voltage BOR comparison.
1 VDDA has tripped under voltage BOR comparison.

3:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 VDD_UBOR RW1C 0 VDDUnder BOR Status

Value Description
0 VDD has not tripped under voltage BOR comparison.
1 VDD has tripped under voltage BOR comparison.

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Register 9: NMI Cause Register (NMIC), offset 0x064

This register provides the detailed information on the cause of an NMI interrupt. These bits are set
via hardware when the event occurs AND the higher level control indicates that it should be NMI
event.
Note: The NMIC register has to be cleared by the following sequence:

1. Read the NMIC register to identify the source of the NMI.

2. Clear the source of the NMI.

3. Read the NMIC register again to check the status.

4. Write a 0 into the NMIC register bit that corresponds with the NMI source.

5. Read the NMIC to check whether it is cleared. If not, repeat 3 on page 271 and
4 on page 271 again.

NMI Cause Register (NMIC)

Base 0x400F.E000
Offset 0x064
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved MOSCFAIL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TAMPER reserved WDT1 reserved WDT0 POWER reserved EXTERNAL

Type RO RO RO RO RO RO RW RO RO RO RW RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 MOSCFAIL RW 0 MOSC Failure NMI

Value Description
0 No MOSC failure has occurred.
1 An NMI has occurred due to a MOSC failure.

15:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

9 TAMPER RW 0 Tamper Event NMI

Value Description
0 No tamper event has occurred.
1 An NMI has occurred due to a tamper event

See the HIB module tamper registers for more details on the tamper
event.

8:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 WDT1 RW 0 Watch Dog Timer (WDT) 1 NMI

Value Description
0 No WDT 1 timeout has occurred.
1 An NMI has occurred due to a Watchdog Timer 1 timeout event.

4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 WDT0 RW 0 Watch Dog Timer (WDT) 0 NMI

Value Description
0 No WDT 0 timeout has occurred.
1 An NMI has occurred due to a Watchdog Timer 0 timeout event.

2 POWER RW 0 Power/Brown Out Event NMI

Value Description
0 No power event has occurred.
1 An NMI has occurred due to a power event.

See PWRTC register for exact cause of power/brown-out event.

1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 EXTERNAL RW 0 External Pin NMI

Value Description
0 No NMI pin event has occurred.
1 The NMI pin was asserted by external hardware.

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Register 10: Main Oscillator Control (MOSCCTL), offset 0x07C

This register provides control over the features of the main oscillator, including the ability to enable
the MOSC clock verification circuit, what action to take when the MOSC fails, and whether or not a
crystal is connected. When enabled, this circuit monitors the frequency of the MOSC to verify that
the oscillator is operating within specified limits. If the clock goes invalid after being enabled, the
microcontroller issues a power-on reset and reboots to the NMI handler or generates an interrupt.
Note: If the MOSC is chosen as the clock to the Ethernet PHY then software has to enable the
MOSC before enabling the Ethernet PHY by setting the P0 bit in the PCEPHY.

Main Oscillator Control (MOSCCTL)

Base 0x400F.E000
Offset 0x07C
Type RW, reset 0x0000.000C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OSCRNG PWRDN NOXTAL MOSCIM CVAL

Type RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

Bit/Field Name Type Reset Description

31:5 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 OSCRNG RW 0 Oscillator Range

Specifies the frequency range of operation of the oscillator.

Value Description
0 Low Frequency Range
1 High Frequency Range (equal to or greater than 10 MHz).

3 PWRDN RW 1 Power Down

Provides user control over powering down the main oscillator circuit.

Value Description
0 Power to main oscillator circuit is enabled.
1 Main Oscillator circuit is powered down.

Note: This bit should be cleared when using a crystal and set for
single-ended mode.

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Bit/Field Name Type Reset Description

2 NOXTAL RW 1 No MOSC/Crystal Connected

Provides the user control over the power drawn from the main oscillator
circuit. This bit should be set when either crystal or single-ended mode
is being used.
If the application needs MOSC, this bit should be cleared.

Value Description
0 This bit should be cleared when a crystal or oscillator is
connected to the OSC0 and OSC1 inputs, regardless of whether
or not the MOSC is used or powered down.

Note: For proper clock functionality when switching to

crystal mode, software must clear this bit and set the
PWRDN bit in a single write access.
1 This bit should be set when a crystal or external oscillator is not
connected to the OSC0 and OSC1 inputs to reduce power
consumption.

1 MOSCIM RW 0 MOSC Failure Action

Value Description
0 If the MOSC fails, a MOSC failure reset is generated and reboots
to the NMI handler.
1 If the MOSC fails, an interrupt is generated as indicated by the
MOSRIS bit in the RIS register.

Regardless of the action taken, if the MOSC fails, the oscillator source
is switched to the PIOSC automatically.

0 CVAL RW 0 Clock Validation for MOSC

Value Description
0 The MOSC monitor circuit is disabled.
1 The MOSC monitor circuit is enabled.

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Register 11: Run and Sleep Mode Configuration Register (RSCLKCFG), offset
0x0B0
Important: When transitioning the system clock configuration to use the MOSC as the fundamental
clock source, the PWRDN bit must be set in the MOSCCTL register prior to reselecting
the MOSC for proper operation.

Run and Sleep Mode Configuration Register (RSCLKCFG)

Base 0x400F.E000
Offset 0x0B0
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MEMTIMU NEWFREQ ACG USEPLL PLLSRC OSCSRC OSYSDIV

Type R0/W R0/W RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OSYSDIV PSYSDIV

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 MEMTIMU R0/W 0 Memory Timing Register Update

Setting this bit causes the MEMTIM0 register value to be applied, and
the memory timing to be updated. Execution and access is suspended
during the change.
This bit is automatically cleared by hardware.

30 NEWFREQ R0/W 0 New PLLFREQ Accept

This bit controls the activation of the values in the PLLFREQ0 and
PLLFREQ1 registers as applied to the PLL. Until NEWFREQ is written to
a 1, writes to the PLLFREQ0 and PLLFREQ1 are deferred. When written
with a 1, the values stored in PLLFREQ0 and PLLFREQ1 are applied
to the PLL.
This bit is automatically cleared by hardware. Software will not check
the value after being set.

29 ACG RW 0x0 Auto Clock Gating

This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the microcontroller enters a Sleep
or Deep-Sleep mode (respectively).

Value Description
0 The Run-Mode Clock Gating Control (RCGCn) registers are
used when the microcontroller enters a sleep mode.
1 If the microcontroller is in sleep mode, the SCGCn registers are
used to control the clocks distributed to the peripherals. If the
microcontroller is in deep-sleep mode, the DCGCn registers
are used to control the clocks distributed to the peripherals. The
SCGCn and DCGCn registers allow unused peripherals to
consume less power when the microcontroller is in a sleep
mode.

The RCGCn registers are always used to control the clocks in Run
mode.

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Bit/Field Name Type Reset Description

28 USEPLL RW 0 Use PLL

This bit controls whether the clock source is specified by the OSCSRC
field or the output of the PLL is provided to the system clock divider and
serves as the system clock source.

Value Description
0 Clock source specified by OSCSRC field.
1 Clock source specified by the PLL

27:24 PLLSRC RW 0 PLL Source

This field specifies the PLL input clock source

Value Description
0x0 PIOSC is the PLL input clock source
0x1-0x2 reserved
0x3 MOSC is the PLL input clock source
0x4-0xFF Reserved

23:20 OSCSRC RW 0 Oscillator Source

This field specifies the oscillator source that becomes the oscillator clock
(OSCCLK) source, which is used when the PLL is bypassed during run
or sleep modes.

Value Description
0x0 PIOSC is oscillator source
0x1 reserved
0x2 LFIOSC is oscillator source
0x3 MOSC is oscillator source
0x4 Hibernation Module RTC Oscillator (RTCOSC)
0x5-0xFF reserved

19:10 OSYSDIV RW 0 Oscillator System Clock Divisor

This field specifies the system clock divisor value for the oscillator path.
This field is used when the USEPLL bit is 0.
fsyclk=foscclk/(OSYSDIV+ 1)
The divisor value is the OSYSDIV field value + 1

9:0 PSYSDIV RW 0 PLL System Clock Divisor

This field specifies the system clock divisor value for the PLL. This field
is used when the USEPLL bit is 1.
fsyclk=fVCO/(PSYSDIV+ 1)

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Register 12: Memory Timing Parameter Register 0 for Main Flash and EEPROM
(MEMTIM0), offset 0x0C0
The MEMTIM0 register provides timing parameters for the main Flash and EEPROM memories.
The timing parameters apply to the memory while the system is in run or sleep mode; the clocking
for these modes is consistent and unchanged since the system clock frequency and source remains
unchanged during transitions between run-to-sleep and sleep-back-to-run. Writes to MEMTIM0 do
not have any effect on system state; the register contents are applied only when the MEMTIMU bit
in the RSCLKCFG register is set. Doing so allows the software to execute out of the same memory
system for which the timing parameters are being modified.
Depending on the CPU frequency, the application must program specific values into the fields of
the Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0). The following
table details the bit field values that are required for the given CPU frequency ranges.

Table 5-12. MEMTIM0 Register Configuration versus Frequency

CPU Frequency range (f) in Time Period Range (t) in ns FBCHT/EBCHT FBCE/EBCE FWS/EWS
MHz
16 62.5 0x0 1 0x0
16 < f ≤ 40 62.5 > t ≥ 25 0x2 0 0x1
40 < f ≤60 25 > t ≥ 16.67 0x3 0 0x2
60< f ≤80 16.67 > t ≥ 12.5 0x4 0 0x3
80 < f ≤100 12.5 > t ≥ 10 0x5 0 0x4
100< f ≤120 10 > t ≥ 8.33 0x6 0 0x5

Note: The associated Flash and EEPROM fields in the MEMTIM0 register must be programmed
to the same values. For example, the FWS field must be programmed to the same value as
the EWS field.
Refer to “Flash Memory” on page 604 and “EEPROM” on page 615 for more information about Flash
and EEPROM programming.

Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0)
Base 0x400F.E000
Offset 0x0C0
Type RW, reset 0x0030.0030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved EBCHT EBCE reserved EWS

Type RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FBCHT FBCE reserved FWS

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0

Bit/Field Name Type Reset Description

31:26 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

25:22 EBCHT RW 0x0 EEPROM Clock High Time

Specifies the length of the EEPROM bank clock high time

Value Description
0x0 1/2 system clock period
0x1 1 system clock period
0x2 1.5 system clock periods
0x3 2 system clock periods
0x4 2.5 system clock periods
0x5 3 system clock periods
0x6 3.5 system clock periods
0x7 4 system clock periods
0x8 4.5 system clock periods

21 EBCE RW 1 EEPROM Bank Clock Edge

Specifies the relationship of EEPROM clock to system clock

Value Description
0 EEPROM clock rising aligns with system clock rising
1 EEPROM clock rising aligns with system clock falling

20 reserved RW 1 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19:16 EWS RW 0 EEPROM Wait States

This field specifies the number of wait states inserted.

Value Description
0x0 0 wait states
0x1 1 wait state
0x2 2 wait states
0x3 3 wait states
0x4 4 wait states
0x5 5 wait states
0x6 6 wait states
0x7 7 wait states
0x8-0xF reserved

15:10 reserved RW 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

9:6 FBCHT RW 0x0 Flash Bank Clock High Time

Specifies the length of the flash bank clock high time

Value Description
0x0 1/2 system clock period
0x1 1 system clock period
0x2 1.5 system clock periods
0x3 2 system clock periods
0x4 2.5 system clock periods
0x5 3 system clock periods
0x6 3.5 system clock periods
0x7 4 system clock periods
0x8 4.5 system clock periods

5 FBCE RW 1 Flash Bank Clock Edge

Specifies the relationship of flash clock to system clock

Value Description
0 Flash clock rising aligns with system clock rising
1 Flash clock rising aligns with system clock falling

4 reserved RW 1 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3:0 FWS RW 0 Flash Wait State

This field specifies the number of wait states inserted.

Value Description
0x0 0 wait states
0x1 1 wait state
0x2 2 wait states
0x3 3 wait states
0x4 4 wait states
0x5 5 wait states
0x6 6 wait states
0x7 7 wait states
0x8-0xF reserved

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Register 13: Alternate Clock Configuration (ALTCLKCFG), offset 0x138

The ALTCLKCFG register specifies the alternate clock source used by many of the peripherals.

Alternate Clock Configuration (ALTCLKCFG)

Base 0x400F.E000
Offset 0x138
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved ALTCLK

Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3:0 ALTCLK RW 0x0 Alternate Clock Source

This provides a clock source of numerous frequencies to the
general-purpose timer, SSI, and UART modules. Note that if the
Hibernation Real-time Clock Output is selected, the clock source must
also be enabled in the Hibernation module.

Value Description
0x0 PIOSC
0x1-0x2 reserved
0x3 Hibernation Module Real-time clock output (RTCOSC)
0x4 Low-frequency internal oscillator (LFIOSC)
0x5-0x15 reserved

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Register 14: Deep Sleep Clock Configuration Register (DSCLKCFG), offset

0x144
The DSCLKCFG register specifies the behavior of the clock system while in deep sleep.
Note that the MOSCDPD bit not only affects deep-sleep mode, but all other modes as well depending
on the value of the bit. Please refer to the following table when programming this bit:

Table 5-13. MOSC Configurations

PWRDN bit MOSCDPD field Result
0 0 MOSC is powered ON in run and sleep modes, but is disabled in accidental power down,
when the PWRDN bit is set in the MOSCCTL register, or in deep-sleep mode only if it is not
the deep-sleep clock source (DSOSCSRC !==0x3).
0 1 MOSC is powered and running in run, sleep and deep-sleep modes.
1 0 MOSC is powered off, and does not run in any mode. Please note, that in this configuration,
when the MOSC is disabled, the MOSC must not be chosen as a clock source or indeterminate
results occur.
1 1 MOSC runs and does not disable itself in run, sleep, and deep-sleep modes regardless of
the fact that the PWRDN bit is set.

Note: The MOSCDPD bit has an effect in all modes of operation

Note: If the MOSC is chosen as the Deep-Sleep clock source in the DSCLKCFG register, the
MOSC must also be configured as the Run and Sleep clock source in the RSCLKCFG
register prior to entering Deep Sleep. If the PIOSC, LFIOSC, or Hibernation RTC Module
Oscillator (HIBLFIOSC or 32-kHz crystal) is configured as the Run and Sleep clock source
in the RSCLKFCFG register, and the MOSC is configured as the Deep-Sleep clock source
in the DSCLKCFG register, then two outcomes are possible:

■ If the PIOSC is still powered in Deep Sleep (using the PIOSCPD bit in the DSCLKCFG
register) then the PIOSC is utilized as the clock source when entering Deep Sleep and
the device enters and exits the Deep-Sleep state normally. The MOSC is not used as
the clock source in Deep Sleep.

■ If the PIOSC has been configured to be powered down in Deep Sleep, then the device
can enter the Deep-Sleep state, but cannot exit properly. This situation can be avoided
by programming the MOSC as the Run and Sleep clock source in the RSCLKCFG
register prior to entering Deep Sleep.

Deep Sleep Clock Configuration Register (DSCLKCFG)

Base 0x400F.E000
Offset 0x144
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PIOSCPD MOSCDPD reserved DSOSCSRC reserved

Type RW RW RO RO RO RO RO RO RW RW RW RW RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DSSYSDIV

Type RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit/Field Name Type Reset Description

31 PIOSCPD RW 0 PIOSC Power Down

Value Description
0 The PIOSC is active during deep sleep mode.
1 The PIOSC is disabled during sleep mode for additional power
savings.

30 MOSCDPD RW 0 MOSC Disable Power Down

This bit inhibits the MOSC from automatic or accidental power down.
This bit is defined to ensure the MOSC circuit cannot be interrupted in
uses where MOSC supplies a clock to the peripherals (for example,
Ethernet PHY).

Value Description
0 During deep-sleep (if DSOSCSRC is not MOSC), accidental power
down or when the PWRDWN bit is set in the MOSCCTL register,
the MOSC is powered down.
1 MOSC is not powered off during automatic or accidental power
down.

Note: MOSC is also not powered off if DSOSCRC is

programmed to be MOSC.

Note: This bit should only be set after software configures

the MOSCCTL register. Setting the MOSCDPD bit
masks writes to PWRDN bit in the MOSCCTL register.

29:24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:20 DSOSCSRC RW 0x0 Deep Sleep Oscillator Source

This field specifies the oscillator source that becomes the oscillator clock
(OSCCLK) source, which is used when the PLL is bypassed during deep
sleep mode.

Value Description
0x0 PIOSC
0x1 reserved
0x2 LFIOSC
0x3 MOSC
0x4 Hibernation Module RTCOSC
0x5-0xF reserved

19:10 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

9:0 DSSYSDIV RW 0x0 Deep Sleep Clock Divisor

This field specifies the system clock divisor value during deep sleep
mode. The clock source selected by DSOSCSRC is divided by DSSYSDIV
+ 1:
fSYSCLK=fOSCCLK/(DSSYSDIV + 1)

Note: Values 0x0 and 0x1 should not be used. If Deep-Sleep clock
divide by 1 or divide by 2 is desired, the OSYSDIV bit field of
the RSCLKCFG register must be configured for the desired
Deep-Sleep divider before entering Deep-Sleep. In this case,
the Q post-divider bit field in the PLLFREQ1 register may
need to be adjusted to keep the system clock frequency within
the maximum clock frequency before entering Deep-Sleep.

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Register 15: Divisor and Source Clock Configuration (DIVSCLK), offset 0x148
The DIVSCLK register specifies the source and divisor of the DIVSCLK reference clock output. This
signal can be used as a clock source to an external device but bears no timing relationship to other
signals.
Note: The DIVSCLK signal output is not synchronized to the System Clock.

Divisor and Source Clock Configuration (DIVSCLK)

Base 0x400F.E000
Offset 0x148
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EN reserved SRC

Type RW RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DIV

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 EN RW 0 DIVSCLK Enable
This bit enables the generation of the DIVSCLK clock output. It resets
to 0 to disable the output thereby reducing initial current/power
consumption.

Value Description
0 The clock output is disabled
1 Clock output is enabled.

30:18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

17:16 SRC RW 0 Clock Source

Selects the reference clock used to generate the output.

Value Description
0x0 System Clock
0x1 PIOSC
0x2 MOSC
0x3 reserved

15:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

7:0 DIV RW 0 Divisor Value

This field controls the ratio of the source clock to the output clock. The
output clock frequency is equal to the source clock frequency divided
by the DIV field value plus 1.

Value Description
0x0 Divided by 1
0x1 Divided by 2
.... ......
N Divided by N

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Register 16: System Properties (SYSPROP), offset 0x14C

This register provides information on whether certain System Control properties are present on the
microcontroller.

System Properties (SYSPROP)

Base 0x400F.E000
Offset 0x14C
Type RO, reset 0x0003.1F31
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved LDOSME TSPDE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PIOSCPDE SRAMSM SRAMLPM reserved FLASHLPM reserved LDOSEQ reserved FPU

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 1 1 0 1 0 0 1 0 0 0 0 1

Bit/Field Name Type Reset Description

31:18 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

17 LDOSME RO 0x1 LDO Sleep Mode Enable

Value Description
0 The LDOSM bit of the DSLPPWRCFG register is ignored.
1 The LDOSM bit of the DSLPPWRCFG register can be set to
place the LDO in a low-power mode when the deep sleep state
is entered.

16 TSPDE RO 0x1 Temp Sense Power Down Enable

This bit allows the internal temperature sensor in the ADC to be powered
off in Deep-Sleep mode.

Value Description
0 The TSPD bit of the DSLPPWRCFG register is ignored.
1 The TSPD bit of the DSLPPWRCFG register can be set to power
off the temperature sensor in deep sleep mode.

15:13 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

12 PIOSCPDE RO 0x1 PIOSC Power Down Present

This bit determines whether the PIOSCPD bit in the DSCLKCFG register
can be set to power down the PIOSC in Deep-Sleep mode.

Value Description
0 The status of the PIOSCPD bit is ignored.
1 The PIOSCPD bit can be set to power down the PIOSC in
Deep-Sleep mode.

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Bit/Field Name Type Reset Description

11 SRAMSM RO 0x1 SRAM Sleep/Deep-Sleep Standby Mode Present

This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into
Standby mode while in Sleep or Deep-Sleep mode.

Value Description
0 A value of 0x1 in the SRAMPM fields is ignored.
1 The SRAMPM fields can be configured to put the SRAM into
Standby mode while in Sleep or Deep-Sleep mode.

10 SRAMLPM RO 0x1 SRAM Sleep/Deep-Sleep Low Power Mode Present

This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into Low
Power mode while in Sleep or Deep-Sleep mode.
Refer to “Sleep Modes” on page 1843 for information regarding wake times
from Sleep and Deep-Sleep.

Value Description
0 A value of 0x3 in the SRAMPM fields is ignored.
1 The SRAMPM fields can be configured to put the SRAM into Low
Power mode while in Sleep or Deep-Sleep mode.

9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

8 FLASHLPM RO 0x1 Flash Memory Sleep/Deep-Sleep Low Power Mode Present

This bit determines whether the FLASHPM field in the SLPPWRCFG
and DSLPPWRCFG registers can be configured to put the Flash memory
into Low Power mode while in Sleep or Deep-Sleep mode.
Refer to “Sleep Modes” on page 1843 for information regarding wake times
from Sleep and Deep-Sleep.

Value Description
0 A value of 0x2 in the FLASHPM fields is ignored.
1 The FLASHPM fields can be configured to put the Flash memory
into Low Power mode while in Sleep or Deep-Sleep mode.

7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 LDOSEQ RO 0x1 Automatic LDO Sequence Control Present

This bit indicates that the ability to sequence the LDO output voltage is
available during Sleep and Deep-Sleep modes.

Value Description
0 Software cannot set the VADJEN bit in the LDOSPCTL and
LDODPCTL registers.
1 Software can set the VADJEN bit in the LDOSPCTL and
LDODPCTL registers.

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Bit/Field Name Type Reset Description

4:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 FPU RO 0x1 FPU Present

This bit indicates if the FPU is present in the Cortex-M4 core.

Value Description
0 FPU is not present.
1 FPU is present.

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Register 17: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150

This register provides the ability to update or recalibrate the precision internal oscillator. Note that
a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be
able to calibrate the PIOSC.

Precision Internal Oscillator Calibration (PIOSCCAL)

Base 0x400F.E000
Offset 0x150
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UTEN reserved

Type RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CAL UPDATE reserved UT

Type RO RO RO RO RO RO RW RW RO RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 UTEN RW 0 Use User Trim Value

Value Description
0 The factory calibration value is used for an update trim operation.
1 The trim value in bits[6:0] of this register are used for any update
trim operation.

30:10 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 CAL RW 0 Start Calibration

Value Description
0 No action.
1 Starts a new calibration of the PIOSC. Results are in the
PIOSCSTAT register. The resulting trim value from the operation
is active in the PIOSC after the calibration completes. The result
overrides any previous update trim operation whether the
calibration passes or fails.

This bit is auto-cleared after it is set.

8 UPDATE RW 0 Update Trim

Value Description
0 No action.
1 Updates the PIOSC trim value with the UT bit or the DT bit in
the PIOSCSTAT register. Used with UTEN.

This bit is auto-cleared after the update.

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

6:0 UT RW 0x0 User Trim Value

User trim value that can be loaded into the PIOSC.

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Register 18: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154

This register provides the user information on the PIOSC calibration. Note that a 32.768-kHz oscillator
must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC.

Precision Internal Oscillator Statistics (PIOSCSTAT)

Base 0x400F.E000
Offset 0x154
Type RO, reset 0x0040.0040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved DT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved RESULT reserved CT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

22:16 DT RO 0x40 Default Trim Value

This field contains the default trim value. This value is loaded into the
PIOSC after every full power-up.

15:10 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9:8 RESULT RO 0 Calibration Result

Value Description
0x0 Calibration has not been attempted.
0x1 The last calibration operation completed to meet 1% accuracy.
0x2 The last calibration operation failed to meet 1% accuracy.
0x3 Reserved

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6:0 CT RO 0x40 Calibration Trim Value

This field contains the trim value from the last calibration operation. After
factory calibration CT and DT are the same.

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Register 19: PLL Frequency 0 (PLLFREQ0), offset 0x160

This register always contains the variables used to configure the PLL. If the PLL is reprogrammed,
it must go through a relock sequence which is defined by the parameter TREADY in Table
27-16 on page 1835. When controlling this register directly, software must change this value while the
PLL is powered down. Writes to PLLFREQ0 are delayed from affecting the PLL until the RSCLKCFG
register NEWFREQ bit is written with a 1.
The PLL frequency can be calculated using the following equation:

fVCO = (fIN * MDIV)

where

fIN = fXTAL/(Q+1)(N+1) or fPIOSC/(Q+1)(N+1)

MDIV = MINT + (MFRAC / 1024)

The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC
should be programmed to 0x0.

PLL Frequency 0 (PLLFREQ0)

Base 0x400F.E000
Offset 0x160
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved PLLPWR reserved MFRAC

Type RO RO RO RO RO RO RO RO RW RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MFRAC MINT

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23 PLLPWR RW 0 PLL Power

This bit controls power to the PLL. If set, the PLL power is applied and
the PLL will oscillate based on the values in the PLLFREQ0 and
PLLFREQ1 registers.

22:20 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19:10 MFRAC RW 0 PLL M Fractional Value

9:0 MINT RW 0x00 PLL M Integer Value

This field contains the integer value of the PLL M value.

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Register 20: PLL Frequency 1 (PLLFREQ1), offset 0x164

This register always contains the current Q and N values presented to the system PLL. If the PLL
is reconfigured, it must go through a relock sequence which takes about 128 PIOSC clocks. When
controlling this register directly, software must change this value while the PLL is powered down.
Writes to PLLFREQ0 are delayed from affecting the PLL until the RSCLKCFG register NEWFREQ
bit is written with a 1.
The MINT and MFRAC fields are present in the PLLFREQ0 register.

PLL Frequency 1 (PLLFREQ1)

Base 0x400F.E000
Offset 0x164
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved Q reserved N

Type RO RO RO RW RW RW RW RW RO RO RO RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:13 reserved RO 0x0000.0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

12:8 Q RW 0x0 PLL Q Value

This field contains the PLL Q value.

7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4:0 N RW 0x0 PLL N Value

This field contains the PLL N value.

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Register 21: PLL Status (PLLSTAT), offset 0x168

This register shows the direct status of the PLL lock.

PLL Status (PLLSTAT)

Base 0x400F.E000
Offset 0x168
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved LOCK

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 LOCK RO 0x0 PLL Lock

Value Description
0 The PLL is unpowered or is not yet locked.
1 The PLL powered and locked.

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Register 22: Sleep Power Configuration (SLPPWRCFG), offset 0x188

This register provides configuration information for the power control of the SRAM and Flash memory
while in Sleep mode.

Sleep Power Configuration (SLPPWRCFG)

Base 0x400F.E000
Offset 0x188
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FLASHPM reserved SRAMPM

Type RO RO RO RO RO RO RO RO RO RO RW RW RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:4 FLASHPM RW 0x0 Flash Power Modes

Value Description
0x0 Active Mode
Flash memory is not placed in a lower power mode. This mode
provides the fastest time to sleep and wakeup but the highest
power consumption while the microcontroller is in Sleep mode.
0x1 Reserved
0x2 Low Power Mode
Flash memory is placed in low power mode. This mode provides
the lowers power consumption but requires more time to come
out of Sleep mode.
0x3 Reserved

3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

1:0 SRAMPM RW 0x0 SRAM Power Modes

This field controls the low power modes of the on-chip SRAM , including
the USB SRAM while the microcontroller is in Sleep mode.

Value Description
0x0 Active Mode
SRAM is not placed in a lower power mode. This mode provides
the fastest time to sleep and wakeup but the highest power
consumption while the microcontroller is in Sleep mode.
0x1 Standby Mode
SRAM is placed in standby mode while in Sleep mode.
0x2 Reserved
0x3 Low Power Mode
SRAM is placed in low power mode. This mode provides the
slowest time to sleep and wakeup but the lowest power
consumption while in Sleep mode.

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Register 23: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C

This register provides configuration information for the power control of the SRAM and Flashmemory
while in Deep-Sleep mode.

Deep-Sleep Power Configuration (DSLPPWRCFG)

Base 0x400F.E000
Offset 0x18C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved LDOSM TSPD reserved FLASHPM reserved SRAMPM

Type RO RO RO RO RO RO RW RW RO RO RW RW RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 LDOSM RW 0 LDO Sleep Mode

Value Description
0 LDO is disabled in sleep-mode.
1 LDO is placed in a low power mode when deep sleep mode is
entered.

8 TSPD RW 0 Temperature Sense Power Down

This bit controls low power mode for the internal temperature sensor in
the ADC.

Value Description
0 Temperature sensor in the ADC is disabled in sleep-mode.
1 The internal temperature sensor in the ADC is placed in a low
power mode when deep sleep mode is entered.

7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

5:4 FLASHPM RW 0x0 Flash Power Modes

This field enables the Flash to be placed in a Low Power Mode.
Refer to “Sleep Modes” on page 1843 for information regarding wake times
from Sleep and Deep-Sleep.
If using the LFIOSC as the Deep-Sleep clock source, FLASHPM = 0x2
must be used. If FLASHPM = 0x0 and the LFIOSC is used, current could
be higher and could vary.

Value Description
0x0 Active Mode
Flash memory is not placed in a lower power mode. This mode
provides the fastest time to sleep and wakeup but the highest
power consumption while the microcontroller is in Deep-Sleep
mode.
0x1 Reserved
0x2 Low Power Mode
Flash memory is placed in low power mode. This mode provides
the lowers power consumption but requires more time to come
out of Deep-Sleep mode.
0x3 Reserved

3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1:0 SRAMPM RW 0x0 SRAM Power Modes

This field controls the low power modes of the on-chip SRAM , including
the USB SRAM while the microcontroller is in Deep-Sleep mode.
Refer to “Sleep Modes” on page 1843 for information regarding wake times
from Sleep and Deep-Sleep.

Value Description
0x0 Active Mode
SRAM is not placed in a lower power mode. This mode provides
the fastest time to sleep and wakeup but the highest power
consumption while the microcontroller is in Deep-Sleep mode.
0x1 Standby Mode
SRAM is place in standby mode while in Deep-Sleep mode.
0x2 Reserved
0x3 Low Power Mode
SRAM is placed in low power mode. This mode provides the
slowest time to sleep and wakeup but the lowest power
consumption while in Deep-Sleep mode.

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Register 24: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0

This register is predefined by the part and can be used to verify features.

Non-Volatile Memory Information (NVMSTAT)

Base 0x400F.E000
Offset 0x1A0
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FWB

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 FWB RO 0x1 32 Word Flash Write Buffer Available

When set, indicates that the 32 word Flash memory write buffer feature
is available.

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Register 25: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4

This register specifies the LDO output voltage in Sleep mode. This register should be configured
while in Run Mode. If the VADJEN bit is set, writes can be made to the VLDO field within the provided
encodings. The following table shows the maximum clock frequencies with respect to LDO Voltage.

Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
Operating Voltage (LDO) Maximum System Clock Frequency PIOSC
1.2 120 MHz 16 MHz
0.9 30 MHz 16 MHz

LDO Sleep Power Control (LDOSPCTL)

Base 0x400F.E000
Offset 0x1B4
Type RW, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VADJEN reserved

Type RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VLDO

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

Bit/Field Name Type Reset Description

31 VADJEN RW 0 Voltage Adjust Enable

This bit enables the value of the VLDO field to be used to specify the
output voltage of the LDO in Sleep mode.

Value Description
0 The LDO output voltage is set to the factory default value in
Sleep mode. The value of the VLDO field does not affect the
LDO operation.
1 The LDO output value in Sleep mode is configured by the value
in the VLDO field.

30:8 reserved RO 0x000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

7:0 VLDO RW 0x18 LDO Output Voltage

This field provides program control of the LDO output voltage in Sleep
mode. The value of the field is only used for the LDO voltage when the
VADJEN bit is set.

Value Description
0x12 0.90 V
0x13 0.95 V
0x14 1.00 V
0x15 1.05 V
0x16 1.10 V
0x17 1.15 V
0x18 1.20 V
0x19 - 0xFF reserved

Note: When using the USB module, the LDO must be configured
to 1.2 V.

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Register 26: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8

This register provides factory determined values that are recommended for the VLDO field in the
LDOSPCTL register while in Sleep mode. The reset value of this register cannot be determined
until the product has been characterized.

LDO Sleep Power Calibration (LDOSPCAL)

Base 0x400F.E000
Offset 0x1B8
Type RO, reset 0x0000.1818
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WITHPLL NOPLL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:8 WITHPLL RO 0x18 Sleep with PLL

The value in this field is the suggested value for the VLDO field in the
LDOSPCTL register when using the PLL. This value provides the lowest
recommended LDO output voltage for use with the PLL at the maximum
specified value.

7:0 NOPLL RO 0x18 Sleep without PLL

The value in this field is the suggested value for the VLDO field in the
LDOSPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use without the PLL.

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Register 27: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC

This register specifies the LDO output voltage in Sleep mode. This register should be configured
while in Run Mode. If the VADJEN bit is set, writes can be made to the VLDO field within the provided
encodings. The following table shows the maximum clock frequencies with respect to LDO Voltage.

Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
Operating Voltage (LDO) Maximum System Clock Frequency PIOSC
1.2 120 MHz 16 MHz
0.9 30 MHz 16 MHz

LDO Deep-Sleep Power Control (LDODPCTL)

Base 0x400F.E000
Offset 0x1BC
Type RW, reset 0x0000.0012
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VADJEN reserved

Type RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VLDO

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0

Bit/Field Name Type Reset Description

31 VADJEN RW 0 Voltage Adjust Enable

This bit enables the value of the VLDO field to be used to specify the
output voltage of the LDO in Deep-Sleep mode.

Value Description
0 The LDO output voltage is set to the factory default value in
Deep-Sleep mode. The value of the VLDO field does not affect
the LDO operation.
1 The LDO output value in Deep-Sleep mode is configured by the
value in the VLDO field.

30:8 reserved RO 0x000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

7:0 VLDO RW 0x12 LDO Output Voltage

This field provides program control of the LDO output voltage in
Deep-Sleep mode. The value of the field is only used for the LDO voltage
when the VADJEN bit is set.

Value Description
0x12 0.90 V
0x13 0.95 V
0x14 1.00 V
0x15 1.05 V
0x16 1.10 V
0x17 1.15 V
0x18 1.20 V
0x19 - 0xFF reserved

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Register 28: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0

This register provides factory determined values that are recommended for the VLDO field in the
LDODPCTL register while in Deep-Sleep mode. The reset value of this register cannot be determined
until the product has been characterized.

LDO Deep-Sleep Power Calibration (LDODPCAL)

Base 0x400F.E000
Offset 0x1C0
Type RO, reset 0x0000.1212
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NOPLL 30KHZ

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:8 NOPLL RO 0x12 Deep-Sleep without PLL

The value in this field is the suggested value for the VLDO field in the
LDODPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use with the system clock.

7:0 30KHZ RO 0x12 Deep-Sleep with IOSC

The value in this field is the suggested value for the VLDO field in the
LDODPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use with the low-frequency
internal oscillator.

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Register 29: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC
This register provides status information on the Sleep and Deep-Sleep power modes as well as
some real time status that can be viewed by a debugger or the core if it is running. These events
do not trigger an interrupt and are meant to provide information that can help tune software for power
management. The status register gets written at the beginning of every Dynamic Power Management
event request with the results of any error checking. There is no mechanism to clear the bits; they
are overwritten on the next event. The LDOUA, FLASHLP, LOWPWR, PRACT bits provide real time
data and there are no events to register that information.

Sleep / Deep-Sleep Power Mode Status (SDPMST)

Base 0x400F.E000
Offset 0x1CC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved LDOUA FLASHLP LOWPWR PRACT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PPDW LMAXERR reserved LSMINERR LDMINERR PPDERR FPDERR SPDERR

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:20 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19 LDOUA RO 0 LDO Update Active

Value Description
0 The LDO voltage level is not changing.
1 The LDO voltage level is changing.

18 FLASHLP RO 0 Flash Memory in Low Power State

Value Description
0 The Flash memory is currently in the active state.
1 The Flash memory is currently in the low power state as
programmed in the SLPPWRCFG or DSLPPWRCFG register.

17 LOWPWR RO 0 Sleep or Deep-Sleep Mode

Value Description
0 The microcontroller is currently in Run mode.
1 The microcontroller is currently in Sleep or Deep-Sleep mode
and is waiting for an interrupt or is in the process of powering
up. The status of this bit is not affected by the power state of
the Flash memory or SRAM.

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Bit/Field Name Type Reset Description

16 PRACT RO 0 Sleep or Deep-Sleep Power Request Active

Value Description
0 A power request is not active.
1 The microcontroller is currently in Deep-Sleep mode or is in
Sleep mode and a request to put the SRAM and/or Flash
memory into a lower power mode is currently active as
configured by the SLPPWRCFG register.

15:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 PPDW RO 0 PIOSC Power Down Request Warning

Value Description
0 No error.
1 This bit indicates that the PIOSC was not powered off even
though the PIOSCPD bit was set in the DSLCLKCFG register
because the PIOSC was in use by a peripheral.

6 LMAXERR RO 0 VLDO Value Above Maximum Error

Value Description
0 No error.
1 An error has occurred because software has requested that the
LDO voltage be above the maximum value allowed using the
VLDO bit in the LDOSPCTL, or LDODPCTL register.
In this situation, the LDO is set to the factory default value.

5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 LSMINERR RO 0 VLDO Value Below Minimum Error in Sleep Mode

Value Description
0 No error.
1 An error has occurred because software has requested that the
LDO voltage be below the minimum value allowed using the
VLDO bit in the LDOSPCTL register.
In this situation, the LDO voltage is not changed when entering
Sleep mode.

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Bit/Field Name Type Reset Description

3 LDMINERR RO 0 VLDO Value Below Minimum Error in Deep-Sleep Mode

Value Description
0 No error.
1 An error has occurred because software has requested that the
LDO voltage be below the minimum value allowed using the
VLDO bit in the LDODPCTL register.
In this situation, the LDO voltage is not changed when entering
Deep-Sleep mode.

2 PPDERR RO 0 PIOSC Power Down Request Error

Value Description
0 No error.
1 An error has occurred because software has requested that the
PIOSC be powered down during Deep-Sleep and it is not
possible to power down the PIOSC.
In this situation, the PIOSC is not powered down when entering
Deep-Sleep mode.

1 FPDERR RO 0 Flash Memory Power Down Request Error

Value Description
0 No error.
1 An error has occurred because software has requested a Flash
memory power down mode that is not available using the
FLASHPM field in the SLPPWRCFG or the DSLPPWRCFG
register.

0 SPDERR RO 0 SRAM Power Down Request Error

Value Description
0 No error.
1 An error has occurred because software has requested an
SRAM power down mode that is not available using the SRAMPM
field in the SLPPWRCFG or the DSLPPWRCFG register.

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Register 30: Reset Behavior Control Register (RESBEHAVCTL), offset 0x1D8

The Reset Behavior Control Register contains system management controls.
The RESBEHAVCTL register effect occurs immediately when the register is changed. The next
power-on reset sequence returns the reset value.
If any bit field below is set to 0x3 when a reset occurs, a simulated POR will be generated and the
appropriate reset cause will be set in the Reset Cause (RESC) register. During a simulated POR,
registers are reloaded and the bootloader is executed. If a full POR is initiated the POR bit in the
RESC register will be set and all other bits will be cleared.

Reset Behavior Control Register (RESBEHAVCTL)

Base 0x400F.E000
Offset 0x1D8
Type RW, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved WDOG1 WDOG0 BOR EXTRES

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0xFFFF.FF Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:6 WDOG1 RW 0x3 Watchdog 1 Reset Operation

Value Description
0x0 - 0x1 Reserved. Default operation is performed.
0x2 Watchdog 1 issues a system reset.
0x3 Watchdog 1 issues a simulated POR sequence (default).

5:4 WDOG0 RW 0x3 Watchdog 0 Reset Operation

Value Description
0x0 - 0x1 Reserved. Default operation is performed.
0x2 Watchdog 0 issues a system reset.
0x3 Watchdog 0 issues a simulated POR sequence (default).

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Bit/Field Name Type Reset Description

3:2 BOR RW 0x3 BOR Reset operation

This field defines operation of BOR when the USER has defined the
BOR operation to be a reset.

Note: If the BOR operation is defined as an interrupt, this setting

has no effect.

Value Description
0x0 - 0x1 Reserved. Default operation is performed.
0x2 Brown Out Reset issues system reset.
0x3 Brown Out Reset issues a simulated POR sequence
(default).

1:0 EXTRES RW 0x3 External RST Pin Operation

Value Description
0x0 - 0x1 Reserved. Default operation is performed.
0x2 External RST assertion issues a system reset.
0x3 External RST assertion issues a simulated POR sequence
(default).

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Register 31: Hardware System Service Request (HSSR), offset 0x1F4

The HSSR register is used to control system configuration functions, such as Return-to-Factory
settings. A write to the HSSR register stores a command descriptor pointer (CDOFF) value if the
KEY field is correct (0xCA). A successful write to this register also initiates a system reset. The
initialization process executes before examining the HSSR register and processing the command.
This register can only be accessed in privilege mode. Refer to “Hardware System Service
Request” on page 245 for more information on how to use the HSSR register.

Hardware System Service Request (HSSR)

Base 0x400F.E000
Offset 0x1F4
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

KEY CDOFF

Type R0/W R0/W R0/W R0/W R0/W R0/W R0/W R0/W RW RW RW RW RW RW RW RW

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CDOFF

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 KEY R0/W 0 Write Key

When read, this field returns zero.
When written, this field must contain the value of 0xCA in order to register
the CDOFF field and initiate a HSSR request. Writes with KEY values
other than 0xCA are ignored.

23:0 CDOFF RW 0 Command Descriptor Pointer

This field contains either the status result from the previous HSSR
request, or it contains a (word-aligned) memory address where the
command descriptor is located.
If CDOFF = 0x00.0000, it indicates there is no request and no prcoessing
is performed.
If CDOFF = 0xFF.FFFF, it indicates that the previous request through
HSSR did not complete due to an error.
Otherwise, CDOFF contains the offset for a data structure in SRAM.

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Register 32: USB Power Domain Status (USBPDS), offset 0x280

This register provides the status of power to the USB SRAM memory array.
Note: If the USBMPC register's PWRCTL field is set to 0x3 and the power domain to the USB is
turned off by writing a 0 to the P0 bit of the PCUSB register, then the SRAM memory goes
into retention and the MEMSTAT field of the USBPDS register reads as 0x1 (retention).

USB Power Domain Status (USBPDS)

Base 0x400F.E000
Offset 0x280
Type RO, reset 0x0000.003F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved reserved MEMSTAT PWRSTAT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:4 reserved RO 0x3 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3:2 MEMSTAT RO 0x3 Memory Array Power Status

Displays status of USB SRAM memory

Value Description
0x0 Array OFF
0x1 SRAM Retention
0x2 Reserved
0x3 Array On

1:0 PWRSTAT RO 0x3 Power Domain Status

Value Description
0x0 OFF
0x1-0x2 Reserved
0x3 ON

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Register 33: USB Memory Power Control (USBMPC), offset 0x284

This register provides power control to the peripheral memory array.
Note: If the USBMPC register's PWRCTL field is set to 0x3 and the power domain to the USB is
turned off by writing a 0 to the P0 bit of the PCUSB register, then the SRAM memory goes
into retention and the MEMSTAT field of the USBPDS register reads as 0x1 (retention).

USB Memory Power Control (USBMPC)

Base 0x400F.E000
Offset 0x284
Type RW, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PWRCTL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1:0 PWRCTL RW 0x3 Memory Array Power Control

Allows multiple levels of power control in peripheral's SRAM memory
space

Value Description
0x0 Array OFF
0x1 SRAM Retention
0x2 Reserved
0x3 Array On

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Register 34: Ethernet MAC Power Domain Status (EMACPDS), offset 0x288
This register provides the status of power to the EMAC SRAM memory array.
Note: The EMAC memory array does not support retention and can only be turned ON and OFF.
Memory array OFF is supported only when the power domain is off. If the memory array is
currently turned on (PWRCTL = 0x3) and the power control to the EMAC is subsequently
removed by clearing the P0 bit of the PCEMAC register, the event causes the memory array
to turn off and the MEMSTAT bit in the EMACPDS register to be 0x0 (array OFF).

Ethernet MAC Power Domain Status (EMACPDS)

Base 0x400F.E000
Offset 0x288
Type RO, reset 0x0000.003F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved reserved MEMSTAT PWRSTAT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:4 reserved RO 0x3 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3:2 MEMSTAT RO 0x3 Memory Array Power Status

Displays status of EMAC SRAM memory

Value Description
0x0 Array OFF
0x1-0x2 Reserved
0x3 Array On

1:0 PWRSTAT RO 0x3 Power Domain Status

Value Description
0x0 OFF
0x1-0x2 Reserved
0x3 ON

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Register 35: Ethernet MAC Memory Power Control (EMACMPC), offset 0x28C
This register provides power control to the peripheral memory array.
Note: The EMAC memory array does not support retention and can only be turned ON and OFF.
Memory array OFF is supported only when the power domain is off. If the memory array is
turned on (PWRCTL = 0x3) and the power control to the EMAC is removed by clearing the
P0 bit of the PCEMAC register, the memory array is turned off and the MEMSTAT bit in the
EMACPDS register is 0x0.

Ethernet MAC Memory Power Control (EMACMPC)

Base 0x400F.E000
Offset 0x28C
Type RW, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PWRCTL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1:0 PWRCTL RW 0x3 Memory Array Power Control

Value Description
0x0 Array OFF

Note: Array OFF Mode is only supported when the P0 bit

of the PCEMAC register at offset 0x99C is set to
0.
0x1-0x2 Reserved
0x3 Array On

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Register 36: CAN 0 Power Domain Status (CAN0PDS), offset 0x298

This register provides the status of power to the CAN0 SRAM memory array.
Note: The CAN0 memory array does not support retention and can only be turned ON and OFF.
If the memory array is currently turned on (PWRCTL = 0x3) and the power control to the
CAN0 is subsequently removed by clearing the P0 bit of the PCCAN register, the event
causes the memory array to turn off and the MEMSTAT bit in the CAN0PDS register to be
0x0 (array OFF).

CAN 0 Power Domain Status (CAN0PDS)

Base 0x400F.E000
Offset 0x298
Type RO, reset 0x0000.003F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved reserved MEMSTAT PWRSTAT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:4 reserved RO 0x3 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3:2 MEMSTAT RO 0x3 Memory Array Power Status

Displays status of the CAN0 SRAM memory

Value Description
0x0 Array OFF
0x1-0x2 Reserved
0x3 Array On

1:0 PWRSTAT RO 0x3 Power Domain Status

Value Description
0x0 OFF
0x1-0x2 Reserved
0x3 ON

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Register 37: CAN 0 Memory Power Control (CAN0MPC), offset 0x29C

This register provides power control to the peripheral memory array.
Note: The CAN0 memory array does not support retention and can only be turned ON and OFF.
If the memory array is currently turned ON (PWRCTL = 0x3) and the power control to the
CAN0 is subsequently removed by clearing the P0 bit of the PCCAN register, the event
causes the memory array to turn off and the MEMSTAT bit in the CAN0PDS register to be
0x0 (array OFF).

CAN 0 Memory Power Control (CAN0MPC)

Base 0x400F.E000
Offset 0x29C
Type RW, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PWRCTL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1:0 PWRCTL RW 0x3 Memory Array Power Control

Allows multiple levels of power control in peripheral's SRAM memory
space

Value Description
0x0 Array OFF
0x1-0x2 Reserved
0x3 Array On

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Register 38: CAN 1 Power Domain Status (CAN1PDS), offset 0x2A0

This register provides the status of power to the CAN 1 SRAM memory array.
Note: The CAN1 memory array does not support retention and can only be turned ON and OFF.
If the memory array is currently turned on (PWRCTL = 0x3) and the power control to CAN1
is subsequently removed by clearing the P1 bit of the PCCAN register, the event causes
the memory array to turn off and the MEMSTAT bit in the CAN1PDS register to be 0x0 (array
OFF).

CAN 1 Power Domain Status (CAN1PDS)

Base 0x400F.E000
Offset 0x2A0
Type RO, reset 0x0000.003F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved reserved MEMSTAT PWRSTAT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:4 reserved RO 0x3 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3:2 MEMSTAT RO 0x3 Memory Array Power Status

Displays status of CAN1 SRAM memory

Value Description
0x0 Array OFF
0x1-0x2 Reserved
0x3 Array On

1:0 PWRSTAT RO 0x3 Power Domain Status

Value Description
0x0 OFF
0x1-0x2 Reserved
0x3 ON

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Register 39: CAN 1 Memory Power Control (CAN1MPC), offset 0x2A4

This register provides power control to the peripheral memory array.
Note: The CAN1 memory array does not support retention and can only be turned ON and OFF.
If the memory array is currently turned on (PWRCTL = 0x3) and the power control to CAN1
is subsequently removed by clearing the P1 bit of the PCCAN register, the event causes
the memory array to turn off and the MEMSTAT bit in the CAN1PDS register to be 0x0 (array
OFF).

CAN 1 Memory Power Control (CAN1MPC)

Base 0x400F.E000
Offset 0x2A4
Type RW, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PWRCTL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:2 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1:0 PWRCTL RW 0x3 Memory Array Power Control

Allows multiple levels of power control in peripheral's SRAM memory
space

Value Description
0x0 Array OFF
0x1-0x2 Reserved
0x3 Array On

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Register 40: Watchdog Timer Peripheral Present (PPWD), offset 0x300

The PPWD register provides software information regarding the watchdog modules.

Important: This register should be used to determine which watchdog timers are implemented on
this microcontroller.

Watchdog Timer Peripheral Present (PPWD)

Base 0x400F.E000
Offset 0x300
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 P1 RO 0x1 Watchdog Timer 1 Present

Value Description
0 Watchdog module 1 is not present.
1 Watchdog module 1 is present.

0 P0 RO 0x1 Watchdog Timer 0 Present

Value Description
0 Watchdog module 0 is not present.
1 Watchdog module 0 is present.

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Register 41: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER),

offset 0x304
The PPTIMER register provides software information regarding the 16/32-bit general-purpose timer
modules.

Important: This register should be used to determine which timers are implemented on this
microcontroller.

16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER)

Base 0x400F.E000
Offset 0x304
Type RO, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P7 P6 P5 P4 P3 P2 P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 P7 RO 0x1 16/32-Bit General-Purpose Timer 7 Present

Value Description
0 16/32-bit general-purpose timer module 7 is not present.
1 16/32-bit general-purpose timer module 7 is present.

6 P6 RO 0x1 16/32-Bit General-Purpose Timer 6 Present

Value Description
0 16/32-bit general-purpose timer module 6 is not present.
1 16/32-bit general-purpose timer module 6 is present.

5 P5 RO 0x1 16/32-Bit General-Purpose Timer 5 Present

Value Description
0 16/32-bit general-purpose timer module 5 is not present.
1 16/32-bit general-purpose timer module 5 is present.

4 P4 RO 0x1 16/32-Bit General-Purpose Timer 4 Present

Value Description
0 16/32-bit general-purpose timer module 4 is not present.
1 16/32-bit general-purpose timer module 4 is present.

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Bit/Field Name Type Reset Description

3 P3 RO 0x1 16/32-Bit General-Purpose Timer 3 Present

Value Description
0 16/32-bit general-purpose timer module 3 is not present.
1 16/32-bit general-purpose timer module 3 is present.

2 P2 RO 0x1 16/32-Bit General-Purpose Timer 2 Present

Value Description
0 16/32-bit general-purpose timer module 2 is not present.
1 16/32-bit general-purpose timer module 2 is present.

1 P1 RO 0x1 16/32-Bit General-Purpose Timer 1 Present

Value Description
0 16/32-bit general-purpose timer module 1 is not present.
1 16/32-bit general-purpose timer module 1 is present.

0 P0 RO 0x1 16/32-Bit General-Purpose Timer 0 Present

Value Description
0 16/32-bit general-purpose timer module 0 is not present.
1 16/32-bit general-purpose timer module 0 is present.

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Register 42: General-Purpose Input/Output Peripheral Present (PPGPIO),

offset 0x308
The PPGPIO register provides software information regarding the general-purpose input/output
modules.

Important: This register should be used to determine which GPIO ports are implemented on this
microcontroller.

General-Purpose Input/Output Peripheral Present (PPGPIO)

Base 0x400F.E000
Offset 0x308
Type RO, reset 0x0000.7FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 P14 RO 0x1 GPIO Port Q Present

Value Description
0 GPIO Port Q is not present.
1 GPIO Port Q is present.

13 P13 RO 0x1 GPIO Port P Present

Value Description
0 GPIO Port P is not present.
1 GPIO Port P is present.

12 P12 RO 0x1 GPIO Port N Present

Value Description
0 GPIO Port N is not present.
1 GPIO Port N is present.

11 P11 RO 0x1 GPIO Port M Present

Value Description
0 GPIO Port M is not present.
1 GPIO Port M is present.

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Bit/Field Name Type Reset Description

10 P10 RO 0x1 GPIO Port L Present

Value Description
0 GPIO Port L is not present.
1 GPIO Port L is present.

9 P9 RO 0x1 GPIO Port K Present

Value Description
0 GPIO Port K is not present.
1 GPIO Port K is present.

8 P8 RO 0x1 GPIO Port J Present

Value Description
0 GPIO Port J is not present.
1 GPIO Port J is present.

7 P7 RO 0x1 GPIO Port H Present

Value Description
0 GPIO Port H is not present.
1 GPIO Port H is present.

6 P6 RO 0x1 GPIO Port G Present

Value Description
0 GPIO Port G is not present.
1 GPIO Port G is present.

5 P5 RO 0x1 GPIO Port F Present

Value Description
0 GPIO Port F is not present.
1 GPIO Port F is present.

4 P4 RO 0x1 GPIO Port E Present

Value Description
0 GPIO Port E is not present.
1 GPIO Port E is present.

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Bit/Field Name Type Reset Description

3 P3 RO 0x1 GPIO Port D Present

Value Description
0 GPIO Port D is not present.
1 GPIO Port D is present.

2 P2 RO 0x1 GPIO Port C Present

Value Description
0 GPIO Port C is not present.
1 GPIO Port C is present.

1 P1 RO 0x1 GPIO Port B Present

Value Description
0 GPIO Port B is not present.
1 GPIO Port B is present.

0 P0 RO 0x1 GPIO Port A Present

Value Description
0 GPIO Port A is not present.
1 GPIO Port A is present.

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Register 43: Micro Direct Memory Access Peripheral Present (PPDMA), offset
0x30C
The PPDMA register provides software information regarding the μDMA module.

Important: This register should be used to determine if the μDMA module is implemented on this
microcontroller.

Micro Direct Memory Access Peripheral Present (PPDMA)

Base 0x400F.E000
Offset 0x30C
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 μDMA Module Present

Value Description
0 μDMA module is not present.
1 μDMA module is present.

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Register 44: EPI Peripheral Present (PPEPI), offset 0x310

The PPEPI register provides software information regarding the EPI module.

Important: This register should be used to determine if the EPI module is implemented on this
microcontroller.

EPI Peripheral Present (PPEPI)

Base 0x400F.E000
Offset 0x310
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 EPI Module Present

Value Description
0 EPI module is not present.
1 EPI module is present.

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Register 45: Hibernation Peripheral Present (PPHIB), offset 0x314

The PPHIB register provides software information regarding the Hibernation module.

Important: This register should be used to determine if the Hibernation module is implemented on
this microcontroller.

Hibernation Peripheral Present (PPHIB)

Base 0x400F.E000
Offset 0x314
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 Hibernation Module Present

Value Description
0 Hibernation module is not present.
1 Hibernation module is present.

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Register 46: Universal Asynchronous Receiver/Transmitter Peripheral Present

(PPUART), offset 0x318
The PPUART register provides software information regarding the UART modules.

Important: This register should be used to determine which UART modules are implemented on
this microcontroller.

Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART)

Base 0x400F.E000
Offset 0x318
Type RO, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P7 P6 P5 P4 P3 P2 P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 P7 RO 0x1 UART Module 7 Present

Value Description
0 UART module 7 is not present.
1 UART module 7 is present.

6 P6 RO 0x1 UART Module 6 Present

Value Description
0 UART module 6 is not present.
1 UART module 6 is present.

5 P5 RO 0x1 UART Module 5 Present

Value Description
0 UART module 5 is not present.
1 UART module 5 is present.

4 P4 RO 0x1 UART Module 4 Present

Value Description
0 UART module 4 is not present.
1 UART module 4 is present.

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Bit/Field Name Type Reset Description

3 P3 RO 0x1 UART Module 3 Present

Value Description
0 UART module 3 is not present.
1 UART module 3 is present.

2 P2 RO 0x1 UART Module 2 Present

Value Description
0 UART module 2 is not present.
1 UART module 2 is present.

1 P1 RO 0x1 UART Module 1 Present

Value Description
0 UART module 1 is not present.
1 UART module 1 is present.

0 P0 RO 0x1 UART Module 0 Present

Value Description
0 UART module 0 is not present.
1 UART module 0 is present.

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Register 47: Synchronous Serial Interface Peripheral Present (PPSSI), offset

0x31C
The PPSSI register provides software information regarding the SSI modules.

Important: This register should be used to determine which SSI modules are implemented on this
microcontroller. However, to support legacy software, the DC2 register is available. A
read of the DC2 register correctly identifies if a legacy SSI module is present. Software
must use this register to determine if a module that is not supported by the DC2 register
is present.

Synchronous Serial Interface Peripheral Present (PPSSI)

Base 0x400F.E000
Offset 0x31C
Type RO, reset 0x0000.000F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P3 P2 P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 P3 RO 0x1 SSI Module 3 Present

Value Description
0 SSI module 3 is not present.
1 SSI module 3 is present.

2 P2 RO 0x1 SSI Module 2 Present

Value Description
0 SSI module 2 is not present.
1 SSI module 2 is present.

1 P1 RO 0x1 SSI Module 1 Present

Value Description
0 SSI module 1 is not present.
1 SSI module 1 is present.

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Bit/Field Name Type Reset Description

0 P0 RO 0x1 SSI Module 0 Present

Value Description
0 SSI module 0 is not present.
1 SSI module 0 is present.

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Register 48: Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320

The PPI2C register provides software information regarding the I2C modules.

Important: This register should be used to determine which I2C modules are implemented on this
microcontroller.

Inter-Integrated Circuit Peripheral Present (PPI2C)

Base 0x400F.E000
Offset 0x320
Type RO, reset 0x0000.03FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 P9 RO 0x1 I2C Module 9 Present

Value Description
0 I2C module 9 is not present.
1 I2C module 9 is present.

8 P8 RO 0x1 I2C Module 8 Present

Value Description
0 I2C module 8 is not present.
1 I2C module 8 is present.

7 P7 RO 0x1 I2C Module 7 Present

Value Description
0 I2C module 7 is not present.
1 I2C module 7 is present.

6 P6 RO 0x1 I2C Module 6 Present

Value Description
0 I2C module 6 is not present.
1 I2C module 6 is present.

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Bit/Field Name Type Reset Description

5 P5 RO 0x1 I2C Module 5 Present

Value Description
0 I2C module 5 is not present.
1 I2C module 5 is present.

4 P4 RO 0x1 I2C Module 4 Present

Value Description
0 I2C module 4 is not present.
1 I2C module 4 is present.

3 P3 RO 0x1 I2C Module 3 Present

Value Description
0 I2C module 3 is not present.
1 I2C module 3 is present.

2 P2 RO 0x1 I2C Module 2 Present

Value Description
0 I2C module 2 is not present.
1 I2C module 2 is present.

1 P1 RO 0x1 I2C Module 1 Present

Value Description
0 I2C module 1 is not present.
1 I2C module 1 is present.

0 P0 RO 0x1 I2C Module 0 Present

Value Description
0 I2C module 0 is not present.
1 I2C module 0 is present.

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Register 49: Universal Serial Bus Peripheral Present (PPUSB), offset 0x328
The PPUSB register provides software information regarding the USB module.

Important: This register should be used to determine if the USB module is implemented on this
microcontroller.

Universal Serial Bus Peripheral Present (PPUSB)

Base 0x400F.E000
Offset 0x328
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 USB Module Present

Value Description
0 USB module is not present.
1 USB module is present.

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Register 50: Ethernet PHY Peripheral Present (PPEPHY), offset 0x330

The PPEPHY register provides software information regarding the Ethernet PHY module.

Important: This register should be used to determine if the Ethernet PHY module is implemented
on this microcontroller.

Ethernet PHY Peripheral Present (PPEPHY)

Base 0x400F.E000
Offset 0x330
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 Ethernet PHY Module Present

Value Description
0 Ethernet PHY module is not present.
1 Ethernet PHY module is present.

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Register 51: Controller Area Network Peripheral Present (PPCAN), offset 0x334
The PPCAN register provides software information regarding the CAN modules.

Important: This register should be used to determine which CAN modules are implemented on
this microcontroller.

Controller Area Network Peripheral Present (PPCAN)

Base 0x400F.E000
Offset 0x334
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 P1 RO 0x1 CAN Module 1 Present

Value Description
0 CAN module 1 is not present.
1 CAN module 1 is present.

0 P0 RO 0x1 CAN Module 0 Present

Value Description
0 CAN module 0 is not present.
1 CAN module 0 is present.

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Register 52: Analog-to-Digital Converter Peripheral Present (PPADC), offset

0x338
The PPADC register provides software information regarding the ADC modules.

Important: This register should be used to determine which ADC modules are implemented on
this microcontroller.

Analog-to-Digital Converter Peripheral Present (PPADC)

Base 0x400F.E000
Offset 0x338
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 P1 RO 0x1 ADC Module 1 Present

Value Description
0 ADC module 1 is not present.
1 ADC module 1 is present.

0 P0 RO 0x1 ADC Module 0 Present

Value Description
0 ADC module 0 is not present.
1 ADC module 0 is present.

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Register 53: Analog Comparator Peripheral Present (PPACMP), offset 0x33C

The PPACMP register provides software information regarding the analog comparator module.

Important: This register should be used to determine if the analog comparator module is
implemented on this microcontroller.
Note that the Analog Comparator Peripheral Properties (ACMPPP) register indicates
how many analog comparator blocks are included in the module.

Analog Comparator Peripheral Present (PPACMP)

Base 0x400F.E000
Offset 0x33C
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 Analog Comparator Module Present

Value Description
0 Analog comparator module is not present.
1 Analog comparator module is present.

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Register 54: Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340
The PPPWM register provides software information regarding the PWM modules.

Important: This register should be used to determine which PWM modules are implemented on
this microcontroller.

Pulse Width Modulator Peripheral Present (PPPWM)

Base 0x400F.E000
Offset 0x340
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 PWM Module 0 Present

Value Description
0 PWM module 0 is not present.
1 PWM module 0 is present.

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Register 55: Quadrature Encoder Interface Peripheral Present (PPQEI), offset

0x344
The PPQEI register provides software information regarding the QEI modules.

Important: This register should be used to determine which QEI modules are implemented on this
microcontroller.

Quadrature Encoder Interface Peripheral Present (PPQEI)

Base 0x400F.E000
Offset 0x344
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 QEI Module 0 Present

Value Description
0 QEI module 0 is not present.
1 QEI module 0 is present.

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Register 56: Low Pin Count Interface Peripheral Present (PPLPC), offset 0x348
The PPLPC register provides software information regarding the LPC module.

Low Pin Count Interface Peripheral Present (PPLPC)

Base 0x400F.E000
Offset 0x348
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x0 LPC Module Present

Value Description
0 LPC module is not present.
1 LPC module is present.

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Register 57: Platform Environment Control Interface Peripheral Present

(PPPECI), offset 0x350
The PPPECI register provides software information regarding the PECI module.

Platform Environment Control Interface Peripheral Present (PPPECI)

Base 0x400F.E000
Offset 0x350
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x0 PECI Module Present

Value Description
0 PECI module is not present.
1 PECI module is present.

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Register 58: Fan Control Peripheral Present (PPFAN), offset 0x354

The PPFAN register provides software information regarding the FAN module.

Fan Control Peripheral Present (PPFAN)

Base 0x400F.E000
Offset 0x354
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x0 FAN Module 0 Present

Value Description
0 FAN module is not present.
1 FAN module is present.

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Register 59: EEPROM Peripheral Present (PPEEPROM), offset 0x358

The PPEEPROM register provides software information regarding the EEPROM module.

EEPROM Peripheral Present (PPEEPROM)

Base 0x400F.E000
Offset 0x358
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 EEPROM 0 Module Present

Value Description
0 EEPROM module is not present.
1 EEPROM module is present.

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Register 60: 32/64-Bit Wide General-Purpose Timer Peripheral Present

(PPWTIMER), offset 0x35C
The PPWTIMER register provides software information regarding the 32/64-bit wide general-purpose
timer modules.

32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER)

Base 0x400F.E000
Offset 0x35C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x0 32/64-Bit Wide General-Purpose Timer 0 Present

Value Description
0 32/64-bit wide general-purpose timer module 0 is not present.
1 32/64-bit wide general-purpose timer module 0 is present.

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Register 61: Remote Temperature Sensor Peripheral Present (PPRTS), offset

0x370
The PPRTS register provides software information regarding the Remote Temperature Sensor
(RTS) module.

Important: This register should be used to determine which RTS modules are implemented on this
microcontroller.

Remote Temperature Sensor Peripheral Present (PPRTS)

Base 0x400F.E000
Offset 0x370
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x0 RTS Module Present

Value Description
0 RTS module is not present.
1 RTS module is present.

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Register 62: CRC Module Peripheral Present (PPCCM), offset 0x374

The PPCCM register provides software information regarding the CRC.

Important: This register should be used to determine if the CRC is implemented on this
microcontroller.

CRC Module Peripheral Present (PPCCM)

Base 0x400F.E000
Offset 0x374
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 CRC Modules Present

Value Description
0 The CRC module is not present.
1 The CRC module is present.

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Register 63: LCD Peripheral Present (PPLCD), offset 0x390

The PPLCD register provides software information regarding the LCD module.

Important: This register should be used to determine if an LCD controller is implemented on this
microcontroller.

LCD Peripheral Present (PPLCD)

Base 0x400F.E000
Offset 0x390
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x0 LCD Module Present

Value Description
0 LCD module is not present.
1 LCD module is present.

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Register 64: 1-Wire Peripheral Present (PPOWIRE), offset 0x398

The PPOWIRE register provides software information regarding the 1-Wire module.

Important: This register should be used to determine which 1-Wire modules are implemented on
this microcontroller.

1-Wire Peripheral Present (PPOWIRE)

Base 0x400F.E000
Offset 0x398
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x0 1-Wire Module Present

Value Description
0 1-Wire module is not present.
1 1-Wire module is present.

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Register 65: Ethernet MAC Peripheral Present (PPEMAC), offset 0x39C

The PPEMAC register provides software information regarding the Ethernet controller module.

Important: This register should be used to determine which Ethernet controller modules are
implemented on this microcontroller.

Ethernet MAC Peripheral Present (PPEMAC)

Base 0x400F.E000
Offset 0x39C
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x1 Ethernet Controller Module Present

Value Description
0 Ethernet Controller MAC module is not present.
1 Ethernet Controller MAC module is present.

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Register 66: Power Regulator Bus Peripheral Present (PPPRB), offset 0x3A0
The PPPRB register provides software information regarding the Power Regulator Bus module.

Important: This register should be used to determine which Power Regulator Bus modules are
implemented on this microcontroller.

Power Regulator Bus Peripheral Present (PPPRB)

Base 0x400F.E000
Offset 0x3A0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x0 PRB Module Present

Value Description
0 PRB module is not present.
1 PRB module is present.

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Register 67: Human Interface Master Peripheral Present (PPHIM), offset 0x3A4
The PPHIM register provides software information regarding the Human Interface Master (HIM)
module.

Important: This register should be used to determine which HIM modules are implemented on this
microcontroller.

Human Interface Master Peripheral Present (PPHIM)

Base 0x400F.E000
Offset 0x3A4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RO 0x0 HIM Module Present

Value Description
0 HIM module is not present.
1 HIM module is present.

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Register 68: Watchdog Timer Software Reset (SRWD), offset 0x500

The SRWD register provides software the capability to reset the available watchdog modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRWD register. While the SRWD bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SRWD bit.

There may be latency from the clearing of the SRWD bit to when the peripheral is ready for use.
Software should check the corresponding PRWD bit to verify that the Watchdog Timer Module
registers are ready to be accessed.

Important: This register should be used to reset the watchdog modules.

Watchdog Timer Software Reset (SRWD)

Base 0x400F.E000
Offset 0x500
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 R1 RW 0 Watchdog Timer 1 Software Reset

Value Description
0 Watchdog module 1 is not reset.
1 Watchdog module 1 is reset.

0 R0 RW 0 Watchdog Timer 0 Software Reset

Value Description
0 Watchdog module 0 is not reset.
1 Watchdog module 0 is reset.

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Register 69: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER),

offset 0x504
The SRTIMER register provides software the capability to reset the available 16/32-bit timer modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRTIMER register. While the SRTIMER bit is 1, the peripheral
is held in reset.

2. Software completes the reset process by clearing the SRTIMER bit.

There may be latency from the clearing of the SRTIMER bit to when the peripheral is ready for use.
Software should check the corresponding PRTIMER bit to verify that the Timer Module registers
are ready to be accessed.

Important: This register should be used to reset the timer modules.

16/32-Bit General-Purpose Timer Software Reset (SRTIMER)

Base 0x400F.E000
Offset 0x504
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 R7 RW 0 16/32-Bit General-Purpose Timer 7 Software Reset

Value Description
0 16/32-bit general-purpose timer module 7 is not reset.
1 16/32-bit general-purpose timer module 7 is reset.

6 R6 RW 0 16/32-Bit General-Purpose Timer 6 Software Reset

Value Description
0 16/32-bit general-purpose timer module 6 is not reset.
1 16/32-bit general-purpose timer module 6 is reset.

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Bit/Field Name Type Reset Description

5 R5 RW 0 16/32-Bit General-Purpose Timer 5 Software Reset

Value Description
0 16/32-bit general-purpose timer module 5 is not reset.
1 16/32-bit general-purpose timer module 5 is reset.

4 R4 RW 0 16/32-Bit General-Purpose Timer 4 Software Reset

Value Description
0 16/32-bit general-purpose timer module 4 is not reset.
1 16/32-bit general-purpose timer module 4 is reset.

3 R3 RW 0 16/32-Bit General-Purpose Timer 3 Software Reset

Value Description
0 16/32-bit general-purpose timer module 3 is not reset.
1 16/32-bit general-purpose timer module 3 is reset.

2 R2 RW 0 16/32-Bit General-Purpose Timer 2 Software Reset

Value Description
0 16/32-bit general-purpose timer module 2 is not reset.
1 16/32-bit general-purpose timer module 2 is reset.

1 R1 RW 0 16/32-Bit General-Purpose Timer 1 Software Reset

Value Description
0 16/32-bit general-purpose timer module 1 is not reset.
1 16/32-bit general-purpose timer module 1 is reset.

0 R0 RW 0 16/32-Bit General-Purpose Timer 0 Software Reset

Value Description
0 16/32-bit general-purpose timer module 0 is not reset.
1 16/32-bit general-purpose timer module 0 is reset.

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Register 70: General-Purpose Input/Output Software Reset (SRGPIO), offset

0x508
The SRGPIO register provides software the capability to reset the available GPIO modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRGPIO register. While the SRGPIO bit is 1, the peripheral
is held in reset.

2. Software completes the reset process by clearing the SRGPIO bit.

There may be latency from the clearing of the SRGPIO bit to when the peripheral is ready for use.
Software should check the corresponding PRGPIO bit to verify that the GPIO Module registers are
ready to be accessed.

Important: This register should be used to reset the GPIO modules.

General-Purpose Input/Output Software Reset (SRGPIO)

Base 0x400F.E000
Offset 0x508
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

Type RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 R14 RW 0 GPIO Port Q Software Reset

Value Description
0 GPIO Port Q is not reset.
1 GPIO Port Q is reset.

13 R13 RW 0 GPIO Port P Software Reset

Value Description
0 GPIO Port P is not reset.
1 GPIO Port P is reset.

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Bit/Field Name Type Reset Description

12 R12 RW 0 GPIO Port N Software Reset

Value Description
0 GPIO Port N is not reset.
1 GPIO Port N is reset.

11 R11 RW 0 GPIO Port M Software Reset

Value Description
0 GPIO Port M is not reset.
1 GPIO Port M is reset.

10 R10 RW 0 GPIO Port L Software Reset

Value Description
0 GPIO Port L is not reset.
1 GPIO Port L is reset.

9 R9 RW 0 GPIO Port K Software Reset

Value Description
0 GPIO Port K is not reset.
1 GPIO Port K is reset.

8 R8 RW 0 GPIO Port J Software Reset

Value Description
0 GPIO Port J is not reset.
1 GPIO Port J is reset.

7 R7 RW 0 GPIO Port H Software Reset

Value Description
0 GPIO Port H is not reset.
1 GPIO Port H is reset.

6 R6 RW 0 GPIO Port G Software Reset

Value Description
0 GPIO Port G is not reset.
1 GPIO Port G is reset.

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Bit/Field Name Type Reset Description

5 R5 RW 0 GPIO Port F Software Reset

Value Description
0 GPIO Port F is not reset.
1 GPIO Port F is reset.

4 R4 RW 0 GPIO Port E Software Reset

Value Description
0 GPIO Port E is not reset.
1 GPIO Port E is reset.

3 R3 RW 0 GPIO Port D Software Reset

Value Description
0 GPIO Port D is not reset.
1 GPIO Port D is reset.

2 R2 RW 0 GPIO Port C Software Reset

Value Description
0 GPIO Port C is not reset.
1 GPIO Port C is reset.

1 R1 RW 0 GPIO Port B Software Reset

Value Description
0 GPIO Port B is not reset.
1 GPIO Port B is reset.

0 R0 RW 0 GPIO Port A Software Reset

Value Description
0 GPIO Port A is not reset.
1 GPIO Port A is reset.

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Register 71: Micro Direct Memory Access Software Reset (SRDMA), offset
0x50C
The SRDMA register provides software the capability to reset the available μDMA module.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRDMA register. While the SRDMA bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SRDMA bit.

There may be latency from the clearing of the SRDMA bit to when the peripheral is ready for use.
Software should check the corresponding PRDMA bit to verify that the µDMA Module registers are
ready to be accessed.

Important: This register should be used to reset the μDMA module.

Micro Direct Memory Access Software Reset (SRDMA)

Base 0x400F.E000
Offset 0x50C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 μDMA Module Software Reset

Value Description
0 μDMA module is not reset.
1 μDMA module is reset.

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Register 72: EPI Software Reset (SREPI), offset 0x510

The SREPI register provides software the capability to reset the available EPI module.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SREPI register. While the SREPI bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SREPI bit.

There may be latency from the clearing of the SREPI bit to when the peripheral is ready for use.
Software should check the corresponding PREPI bit to verify that the EPI Module registers are ready
to be accessed.

Important: This register should be used to reset the EPI module.

EPI Software Reset (SREPI)

Base 0x400F.E000
Offset 0x510
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 EPI Module Software Reset

Value Description
0 EPI module is not reset.
1 EPI module is reset.

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Register 73: Hibernation Software Reset (SRHIB), offset 0x514

The SRHIB register provides software the capability to reset the available Hibernation module.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRHIB register. While the SRHIB bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SRHIB bit.

There may be latency from the clearing of the SRHIB bit to when the peripheral is ready for use.
Software should check the corresponding PRHIB bit to verify that the Hibernation Module registers
are ready to be accessed.

Important: This register should be used to reset the Hibernation module.

Hibernation Software Reset (SRHIB)

Base 0x400F.E000
Offset 0x514
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 Hibernation Module Software Reset

Value Description
0 Hibernation module is not reset.
1 Hibernation module is reset.

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Register 74: Universal Asynchronous Receiver/Transmitter Software Reset

(SRUART), offset 0x518
The SRUART register provides software the capability to reset the available UART modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRUART register. While the SRUART bit is 1, the peripheral
is held in reset.

2. Software completes the reset process by clearing the SRUART bit.

There may be latency from the clearing of the SRUART bit to when the peripheral is ready for use.
Software should check the corresponding PRUART bit to verify that the UART Module registers are
ready to be accessed.

Important: This register should be used to reset the UART modules.

Universal Asynchronous Receiver/Transmitter Software Reset (SRUART)

Base 0x400F.E000
Offset 0x518
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 R7 RW 0 UART Module 7 Software Reset

Value Description
0 UART module 7 is not reset.
1 UART module 7 is reset.

6 R6 RW 0 UART Module 6 Software Reset

Value Description
0 UART module 6 is not reset.
1 UART module 6 is reset.

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Bit/Field Name Type Reset Description

5 R5 RW 0 UART Module 5 Software Reset

Value Description
0 UART module 5 is not reset.
1 UART module 5 is reset.

4 R4 RW 0 UART Module 4 Software Reset

Value Description
0 UART module 4 is not reset.
1 UART module 4 is reset.

3 R3 RW 0 UART Module 3 Software Reset

Value Description
0 UART module 3 is not reset.
1 UART module 3 is reset.

2 R2 RW 0 UART Module 2 Software Reset

Value Description
0 UART module 2 is not reset.
1 UART module 2 is reset.

1 R1 RW 0 UART Module 1 Software Reset

Value Description
0 UART module 1 is not reset.
1 UART module 1 is reset.

0 R0 RW 0 UART Module 0 Software Reset

Value Description
0 UART module 0 is not reset.
1 UART module 0 is reset.

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Register 75: Synchronous Serial Interface Software Reset (SRSSI), offset

0x51C
The SRSSI register provides software the capability to reset the available SSI modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRSSI register. While the SRSSI bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SRSSI bit.

There may be latency from the clearing of the SRSSI bit to when the peripheral is ready for use.
Software should check the corresponding PRSSI bit to verify that the SSI Module registers are ready
to be accessed.

Important: This register should be used to reset the SSI modules.

Synchronous Serial Interface Software Reset (SRSSI)

Base 0x400F.E000
Offset 0x51C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 R3 RW 0 SSI Module 3 Software Reset

Value Description
0 SSI module 3 is not reset.
1 SSI module 3 is reset.

2 R2 RW 0 SSI Module 2 Software Reset

Value Description
0 SSI module 2 is not reset.
1 SSI module 2 is reset.

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Bit/Field Name Type Reset Description

1 R1 RW 0 SSI Module 1 Software Reset

Value Description
0 SSI module 1 is not reset.
1 SSI module 1 is reset.

0 R0 RW 0 SSI Module 0 Software Reset

Value Description
0 SSI module 0 is not reset.
1 SSI module 0 is reset.

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Register 76: Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520

The SRI2C register provides software the capability to reset the available I2C modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRI2C register. While the SRI2C bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SRI2C bit.

There may be latency from the clearing of the SRI2C bit to when the peripheral is ready for use.
Software should check the corresponding PRI2C bit to verify that the I2C Module registers are ready
to be accessed.

Important: This register should be used to reset the I2C modules.

Inter-Integrated Circuit Software Reset (SRI2C)

Base 0x400F.E000
Offset 0x520
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 R9 RW 0 I2C Module 9 Software Reset

Value Description
0 I2C module 9 is not reset.
1 I2C module 9 is reset.

8 R8 RW 0 I2C Module 8 Software Reset

Value Description
0 I2C module 8 is not reset.
1 I2C module 8 is reset.

7 R7 RW 0 I2C Module 7 Software Reset

Value Description
0 I2C module 7 is not reset.
1 I2C module 7 is reset.

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Bit/Field Name Type Reset Description

6 R6 RW 0 I2C Module 6 Software Reset

Value Description
0 I2C module 6 is not reset.
1 I2C module 6 is reset.

5 R5 RW 0 I2C Module 5 Software Reset

Value Description
0 I2C module 5 is not reset.
1 I2C module 5 is reset.

4 R4 RW 0 I2C Module 4 Software Reset

Value Description
0 I2C module 4 is not reset.
1 I2C module 4 is reset.

3 R3 RW 0 I2C Module 3 Software Reset

Value Description
0 I2C module 3 is not reset.
1 I2C module 3 is reset.

2 R2 RW 0 I2C Module 2 Software Reset

Value Description
0 I2C module 2 is not reset.
1 I2C module 2 is reset.

1 R1 RW 0 I2C Module 1 Software Reset

Value Description
0 I2C module 1 is not reset.
1 I2C module 1 is reset.

0 R0 RW 0 I2C Module 0 Software Reset

Value Description
0 I2C module 0 is not reset.
1 I2C module 0 is reset.

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Register 77: Universal Serial Bus Software Reset (SRUSB), offset 0x528
The SRUSB register provides software the capability to reset the available USB module.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRUSB register. While the SRUSB bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SRUSB bit.

There may be latency from the clearing of the SRUSB bit to when the peripheral is ready for use.
Software should check the corresponding PRUSB bit to verify that the USB Module registers are
ready to be accessed.

Important: This register should be used to reset the USB module.

Universal Serial Bus Software Reset (SRUSB)

Base 0x400F.E000
Offset 0x528
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 USB Module Software Reset

Value Description
0 USB module is not reset.
1 USB module is reset.

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Register 78: Ethernet PHY Software Reset (SREPHY), offset 0x530

The SREPHY register provides software the capability to reset the available PHY module.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SREPHY register. While the SREPHY bit is 1, the peripheral
is held in reset.

2. Software completes the reset process by clearing the SREPHY bit.

There may be latency from the clearing of the SREPHY bit to when the peripheral is ready for use.
Software should check the corresponding PREPHY bit to verify that the EPHY Module registers are
ready to be accessed.

Important: This register should be used to reset the Ethernet PHY module.

Ethernet PHY Software Reset (SREPHY)

Base 0x400F.E000
Offset 0x530
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 Ethernet PHY Module Software Reset

Value Description
0 Ethernet PHY module is not reset.
1 Ethernet PHY module is reset.

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Register 79: Controller Area Network Software Reset (SRCAN), offset 0x534
The SRCAN register provides software the capability to reset the available CAN modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRCAN register. While the SRCAN bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SRCAN bit.

There may be latency from the clearing of the SRCAN bit to when the peripheral is ready for use.
Software should check the corresponding PRCAN bit to verify that the CAN Module registers are
ready to be accessed.

Important: This register should be used to reset the CAN modules.

Controller Area Network Software Reset (SRCAN)

Base 0x400F.E000
Offset 0x534
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 R1 RW 0 CAN Module 1 Software Reset

Value Description
0 CAN module 1 is not reset.
1 CAN module 1 is reset.

0 R0 RW 0 CAN Module 0 Software Reset

Value Description
0 CAN module 0 is not reset.
1 CAN module 0 is reset.

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Register 80: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538

The SRADC register provides software the capability to reset the available ADC modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRADC register. While the SRADC bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SRADC bit.

There may be latency from the clearing of the SRADC bit to when the peripheral is ready for use.
Software should check the corresponding PRADC bit to verify that the ADC Module registers are
ready to be accessed.

Important: This register should be used to reset the ADC modules.

Analog-to-Digital Converter Software Reset (SRADC)

Base 0x400F.E000
Offset 0x538
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 R1 RW 0 ADC Module 1 Software Reset

Value Description
0 ADC module 1 is not reset.
1 ADC module 1 is reset.

0 R0 RW 0 ADC Module 0 Software Reset

Value Description
0 ADC module 0 is not reset.
1 ADC module 0 is reset.

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Register 81: Analog Comparator Software Reset (SRACMP), offset 0x53C

The SRACMP register provides software the capability to reset the available analog comparator
module.
A block is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRACMP register. While the SRACMP bit is 1, the module
is held in reset.

2. Software completes the reset process by clearing the SRACMP bit.

There may be latency from the clearing of the SRACMP bit to when the module is ready for use.
Software should check the corresponding PRACMP bit to verify that the Analog Comparator Module
registers are ready to be accessed.

Important: This register should be used to reset the analog comparator module.

Analog Comparator Software Reset (SRACMP)

Base 0x400F.E000
Offset 0x53C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 Analog Comparator Module 0 Software Reset

Value Description
0 Analog comparator module is not reset.
1 Analog comparator module is reset.

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Register 82: Pulse Width Modulator Software Reset (SRPWM), offset 0x540
The SRPWM register provides software the capability to reset the available PWM modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRPWM register. While the SRPWM bit is 1, the peripheral
is held in reset.

2. Software completes the reset process by clearing the SRPWM bit.

There may be latency from the clearing of the SRPWM bit to when the peripheral is ready for use.
Software should check the corresponding PRPWM bit to verify that the PWM Module registers are
ready to be accessed.

Important: This register should be used to reset the PWM modules.

Pulse Width Modulator Software Reset (SRPWM)

Base 0x400F.E000
Offset 0x540
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 PWM Module 0 Software Reset

Value Description
0 PWM module 0 is not reset.
1 PWM module 0 is reset.

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Register 83: Quadrature Encoder Interface Software Reset (SRQEI), offset

0x544
The SRQEI register provides software the capability to reset the available QEI modules.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SRQEI register. While the SRQEI bit is 1, the peripheral is
held in reset.

2. Software completes the reset process by clearing the SRQEI bit.

There may be latency from the clearing of the SRQEI bit to when the peripheral is ready for use.
Software should check the corresponding PRQEI bit to verify that the QEI Module registers are
ready to be accessed.

Important: This register should be used to reset the QEI modules.

Quadrature Encoder Interface Software Reset (SRQEI)

Base 0x400F.E000
Offset 0x544
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 QEI Module 0 Software Reset

Value Description
0 QEI module 0 is not reset.
1 QEI module 0 is reset.

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Register 84: EEPROM Software Reset (SREEPROM), offset 0x558

The SREEPROM register provides software the capability to reset the available EEPROM module.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SREEPROM register. While the SREEPROM bit is 1, the
peripheral is held in reset.

2. Software completes the reset process by clearing the SREEPROM bit.

There may be latency from the clearing of the SREEPROM bit to when the peripheral is ready for
use. Software should check the corresponding PREEPROM bit to verify that the EEPROM Module
registers are ready to be accessed.

EEPROM Software Reset (SREEPROM)

Base 0x400F.E000
Offset 0x558
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 EEPROM Module 0 Software Reset

Value Description
0 EEPROM module is not reset.
1 EEPROM module is reset.

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Register 85: CRC Module Software Reset (SRCCM), offset 0x574

The SRCCM register provides software the capability to reset the CRC .
A module is reset by software using a simple two-step process:

1. Software sets the bit in the SRCCM register. While the SRCCM bit is 1, the peripheral is held
in reset.

2. Software completes the reset process by clearing the SRCCM bit.

There may be latency from the clearing of the SRCCM bit to when the peripheral is ready for use.
Software should check the corresponding PRCCM bit to verify that the CRC registers are ready to
be accessed.

Important: This register should be used to reset the CRC module.

CRC Module Software Reset (SRCCM)

Base 0x400F.E000
Offset 0x574
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 CRC Software Reset

Value Description
0 The CRC module is not reset.
1 The CRC module is reset.

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Register 86: Ethernet MAC Software Reset (SREMAC), offset 0x59C

The SREMAC register provides software the capability to reset the available Ethernet MAC module.
A peripheral is reset by software using a simple two-step process:

1. Software sets a bit (or bits) in the SREMAC register. While the SREMAC bit is 1, the peripheral
is held in reset.

2. Software completes the reset process by clearing the SREMAC bit.

There may be latency from the clearing of the SREMAC bit to when the peripheral is ready for use.
Software should check the corresponding PREMAC bit to verify that the Ethernet MAC Module
registers are ready to be accessed.

Important: This register should be used to reset the Ethernet controller MAC module.

Ethernet MAC Software Reset (SREMAC)

Base 0x400F.E000
Offset 0x59C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 Ethernet Controller MAC Module 0 Software Reset

Value Description
0 Ethernet Controller MAC module 0 is not reset.
1 Ethernet Controller MAC module 0 is reset.

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Register 87: Watchdog Timer Run Mode Clock Gating Control (RCGCWD),
offset 0x600
The RCGCWD register provides software the capability to enable and disable watchdog modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the watchdog modules

Watchdog Timer Run Mode Clock Gating Control (RCGCWD)

Base 0x400F.E000
Offset 0x600
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 R1 RW 0 Watchdog Timer 1 Run Mode Clock Gating Control

Value Description
0 Watchdog module 1 is disabled.
1 Enable and provide a clock to Watchdog module 1 in Run mode.

0 R0 RW 0 Watchdog Timer 0 Run Mode Clock Gating Control

Value Description
0 Watchdog module 0 is disabled.
1 Enable and provide a clock to Watchdog module 0 in Run mode.

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Register 88: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control
(RCGCTIMER), offset 0x604
The RCGCGPT32 register provides software the capability to enable and disable 16/32-bit timer
modules in Run mode. When enabled, a module is provided a clock and accesses to module registers
are allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the timer modules.

16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER)

Base 0x400F.E000
Offset 0x604
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 R7 RW 0 16/32-Bit General-Purpose Timer 7 Run Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 7 is disabled.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 7 in Run mode.

6 R6 RW 0 16/32-Bit General-Purpose Timer 6 Run Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 6 is disabled.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 6 in Run mode.

5 R5 RW 0 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 5 is disabled.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 5 in Run mode.

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Bit/Field Name Type Reset Description

4 R4 RW 0 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 4 is disabled.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 4 in Run mode.

3 R3 RW 0 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 3 is disabled.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 3 in Run mode.

2 R2 RW 0 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 2 is disabled.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 2 in Run mode.

1 R1 RW 0 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 1 is disabled.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 1 in Run mode.

0 R0 RW 0 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 0 is disabled.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 0 in Run mode.

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Register 89: General-Purpose Input/Output Run Mode Clock Gating Control

(RCGCGPIO), offset 0x608
The RCGCGPIO register provides software the capability to enable and disable GPIO modules in
Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the GPIO modules.

General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO)

Base 0x400F.E000
Offset 0x608
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

Type RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 R14 RW 0 GPIO Port Q Run Mode Clock Gating Control

Value Description
0 GPIO Port Q is disabled.
1 Enable and provide a clock to GPIO Port Q in Run mode.

13 R13 RW 0 GPIO Port P Run Mode Clock Gating Control

Value Description
0 GPIO Port P is disabled.
1 Enable and provide a clock to GPIO Port P in Run mode.

12 R12 RW 0 GPIO Port N Run Mode Clock Gating Control

Value Description
0 GPIO Port N is disabled.
1 Enable and provide a clock to GPIO Port N in Run mode.

11 R11 RW 0 GPIO Port M Run Mode Clock Gating Control

Value Description
0 GPIO Port M is disabled.
1 Enable and provide a clock to GPIO Port M in Run mode.

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Bit/Field Name Type Reset Description

10 R10 RW 0 GPIO Port L Run Mode Clock Gating Control

Value Description
0 GPIO Port L is disabled.
1 Enable and provide a clock to GPIO Port L in Run mode.

9 R9 RW 0 GPIO Port K Run Mode Clock Gating Control

Value Description
0 GPIO Port K is disabled.
1 Enable and provide a clock to GPIO Port K in Run mode.

8 R8 RW 0 GPIO Port J Run Mode Clock Gating Control

Value Description
0 GPIO Port J is disabled.
1 Enable and provide a clock to GPIO Port J in Run mode.

7 R7 RW 0 GPIO Port H Run Mode Clock Gating Control

Value Description
0 GPIO Port H is disabled.
1 Enable and provide a clock to GPIO Port H in Run mode.

6 R6 RW 0 GPIO Port G Run Mode Clock Gating Control

Value Description
0 GPIO Port G is disabled.
1 Enable and provide a clock to GPIO Port G in Run mode.

5 R5 RW 0 GPIO Port F Run Mode Clock Gating Control

Value Description
0 GPIO Port F is disabled.
1 Enable and provide a clock to GPIO Port F in Run mode.

4 R4 RW 0 GPIO Port E Run Mode Clock Gating Control

Value Description
0 GPIO Port E is disabled.
1 Enable and provide a clock to GPIO Port E in Run mode.

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Bit/Field Name Type Reset Description

3 R3 RW 0 GPIO Port D Run Mode Clock Gating Control

Value Description
0 GPIO Port D is disabled.
1 Enable and provide a clock to GPIO Port D in Run mode.

2 R2 RW 0 GPIO Port C Run Mode Clock Gating Control

Value Description
0 GPIO Port C is disabled.
1 Enable and provide a clock to GPIO Port C in Run mode.

1 R1 RW 0 GPIO Port B Run Mode Clock Gating Control

Value Description
0 GPIO Port B is disabled.
1 Enable and provide a clock to GPIO Port B in Run mode.

0 R0 RW 0 GPIO Port A Run Mode Clock Gating Control

Value Description
0 GPIO Port A is disabled.
1 Enable and provide a clock to GPIO Port A in Run mode.

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Register 90: Micro Direct Memory Access Run Mode Clock Gating Control
(RCGCDMA), offset 0x60C
The RCGCDMA register provides software the capability to enable and disable the μDMA module
in Run mode. When enabled, the module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the μDMA module.

Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA)
Base 0x400F.E000
Offset 0x60C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 μDMA Module Run Mode Clock Gating Control

Value Description
0 μDMA module is disabled.
1 Enable and provide a clock to the μDMA module in Run mode.

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Register 91: EPI Run Mode Clock Gating Control (RCGCEPI), offset 0x610
The RCGCEPI register provides software the capability to enable and disable the EPI module in
Run mode. When enabled, the module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the EPI module.

EPI Run Mode Clock Gating Control (RCGCEPI)

Base 0x400F.E000
Offset 0x610
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 EPI Module Run Mode Clock Gating Control

Value Description
0 EPI module is disabled.
1 Enable and provide a clock to the EPI module in Run mode.

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Register 92: Hibernation Run Mode Clock Gating Control (RCGCHIB), offset
0x614
The RCGCHIB register provides software the capability to enable and disable the Hibernation
module in Run mode. When enabled, the module is provided a clock and accesses to module
registers are allowed. When disabled, the clock is disabled to save power and accesses to module
registers generate a bus fault.

Important: This register should be used to control the clocking for the Hibernation module.

Hibernation Run Mode Clock Gating Control (RCGCHIB)

Base 0x400F.E000
Offset 0x614
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 1 Hibernation Module Run Mode Clock Gating Control

Value Description
0 Hibernation module is disabled.
1 Enable and provide a clock to the Hibernation module in Run
mode.

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Register 93: Universal Asynchronous Receiver/Transmitter Run Mode Clock

Gating Control (RCGCUART), offset 0x618
The RCGCUART register provides software the capability to enable and disable the UART modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the UART modules.

Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART)

Base 0x400F.E000
Offset 0x618
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 R7 RW 0 UART Module 7 Run Mode Clock Gating Control

Value Description
0 UART module 7 is disabled.
1 Enable and provide a clock to UART module 7 in Run mode.

6 R6 RW 0 UART Module 6 Run Mode Clock Gating Control

Value Description
0 UART module 6 is disabled.
1 Enable and provide a clock to UART module 6 in Run mode.

5 R5 RW 0 UART Module 5 Run Mode Clock Gating Control

Value Description
0 UART module 5 is disabled.
1 Enable and provide a clock to UART module 5 in Run mode.

4 R4 RW 0 UART Module 4 Run Mode Clock Gating Control

Value Description
0 UART module 4 is disabled.
1 Enable and provide a clock to UART module 4 in Run mode.

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Bit/Field Name Type Reset Description

3 R3 RW 0 UART Module 3 Run Mode Clock Gating Control

Value Description
0 UART module 3 is disabled.
1 Enable and provide a clock to UART module 3 in Run mode.

2 R2 RW 0 UART Module 2 Run Mode Clock Gating Control

Value Description
0 UART module 2 is disabled.
1 Enable and provide a clock to UART module 2 in Run mode.

1 R1 RW 0 UART Module 1 Run Mode Clock Gating Control

Value Description
0 UART module 1 is disabled.
1 Enable and provide a clock to UART module 1 in Run mode.

0 R0 RW 0 UART Module 0 Run Mode Clock Gating Control

Value Description
0 UART module 0 is disabled.
1 Enable and provide a clock to UART module 0 in Run mode.

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Register 94: Synchronous Serial Interface Run Mode Clock Gating Control
(RCGCSSI), offset 0x61C
The RCGCSSI register provides software the capability to enable and disable the SSI modules in
Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the SSI modules.

Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI)

Base 0x400F.E000
Offset 0x61C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 R3 RW 0 SSI Module 3 Run Mode Clock Gating Control

Value Description
0 SSI module 3 is disabled.
1 Enable and provide a clock to SSI module 3 in Run mode.

2 R2 RW 0 SSI Module 2 Run Mode Clock Gating Control

Value Description
0 SSI module 2 is disabled.
1 Enable and provide a clock to SSI module 2 in Run mode.

1 R1 RW 0 SSI Module 1 Run Mode Clock Gating Control

Value Description
0 SSI module 1 is disabled.
1 Enable and provide a clock to SSI module 1 in Run mode.

0 R0 RW 0 SSI Module 0 Run Mode Clock Gating Control

Value Description
0 SSI module 0 is disabled.
1 Enable and provide a clock to SSI module 0 in Run mode.

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Register 95: Inter-Integrated Circuit Run Mode Clock Gating Control

(RCGCI2C), offset 0x620
The RCGCI2C register provides software the capability to enable and disable the I2C modules in
Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the I2C modules.

Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C)

Base 0x400F.E000
Offset 0x620
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 R9 RW 0 I2C Module 9 Run Mode Clock Gating Control

Value Description
0 I2C module 9 is disabled.
1 Enable and provide a clock to I2C module 9 in Run mode.

8 R8 RW 0 I2C Module 8 Run Mode Clock Gating Control

Value Description
0 I2C module 8 is disabled.
1 Enable and provide a clock to I2C module 8 in Run mode.

7 R7 RW 0 I2C Module 7 Run Mode Clock Gating Control

Value Description
0 I2C module 7 is disabled.
1 Enable and provide a clock to I2C module 7 in Run mode.

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Bit/Field Name Type Reset Description

6 R6 RW 0 I2C Module 6 Run Mode Clock Gating Control

Value Description
0 I2C module 6 is disabled.
1 Enable and provide a clock to I2C module 6 in Run mode.

5 R5 RW 0 I2C Module 5 Run Mode Clock Gating Control

Value Description
0 I2C module 5 is disabled.
1 Enable and provide a clock to I2C module 5 in Run mode.

4 R4 RW 0 I2C Module 4 Run Mode Clock Gating Control

Value Description
0 I2C module 4 is disabled.
1 Enable and provide a clock to I2C module 4 in Run mode.

3 R3 RW 0 I2C Module 3 Run Mode Clock Gating Control

Value Description
0 I2C module 3 is disabled.
1 Enable and provide a clock to I2C module 3 in Run mode.

2 R2 RW 0 I2C Module 2 Run Mode Clock Gating Control

Value Description
0 I2C module 2 is disabled.
1 Enable and provide a clock to I2C module 2 in Run mode.

1 R1 RW 0 I2C Module 1 Run Mode Clock Gating Control

Value Description
0 I2C module 1 is disabled.
1 Enable and provide a clock to I2C module 1 in Run mode.

0 R0 RW 0 I2C Module 0 Run Mode Clock Gating Control

Value Description
0 I2C module 0 is disabled.
1 Enable and provide a clock to I2C module 0 in Run mode.

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Register 96: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB),
offset 0x628
The RCGCUSB register provides software the capability to enable and disable the USB module in
Run mode. When enabled, the module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the USB module.

Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB)

Base 0x400F.E000
Offset 0x628
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 USB Module Run Mode Clock Gating Control

Value Description
0 USB module is disabled.
1 Enable and provide a clock to the USB module in Run mode.

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Register 97: Ethernet PHY Run Mode Clock Gating Control (RCGCEPHY),
offset 0x630
The RCGCEPHY register provides software the capability to enable and disable the PHY module
in Run mode. When enabled, the module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the PHY module.

Ethernet PHY Run Mode Clock Gating Control (RCGCEPHY)

Base 0x400F.E000
Offset 0x630
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 Ethernet PHY Module Run Mode Clock Gating Control

Value Description
0 PHY module is disabled.
1 Enable and provide a clock to the PHY module in Run mode.

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Register 98: Controller Area Network Run Mode Clock Gating Control
(RCGCCAN), offset 0x634
The RCGCCAN register provides software the capability to enable and disable the CAN modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the CAN modules.

Controller Area Network Run Mode Clock Gating Control (RCGCCAN)

Base 0x400F.E000
Offset 0x634
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 R1 RW 0 CAN Module 1 Run Mode Clock Gating Control

Value Description
0 CAN module 1 is disabled.
1 Enable and provide a clock to CAN module 1 in Run mode.

0 R0 RW 0 CAN Module 0 Run Mode Clock Gating Control

Value Description
0 CAN module 0 is disabled.
1 Enable and provide a clock to CAN module 0 in Run mode.

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Register 99: Analog-to-Digital Converter Run Mode Clock Gating Control

(RCGCADC), offset 0x638
The RCGCADC register provides software the capability to enable and disable the ADC modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the ADC modules.

Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC)

Base 0x400F.E000
Offset 0x638
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 R1 RW 0 ADC Module 1 Run Mode Clock Gating Control

Value Description
0 ADC module 1 is disabled.
1 Enable and provide a clock to ADC module 1 in Run mode.

0 R0 RW 0 ADC Module 0 Run Mode Clock Gating Control

Value Description
0 ADC module 0 is disabled.
1 Enable and provide a clock to ADC module 0 in Run mode.

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Register 100: Analog Comparator Run Mode Clock Gating Control

(RCGCACMP), offset 0x63C
The RCGCACMP register provides software the capability to enable and disable the analog
comparator module in Run mode. When enabled, the module is provided a clock and accesses to
module registers are allowed. When disabled, the clock is disabled to save power and accesses to
module registers generate a bus fault.

Important: This register should be used to control the clocking for the analog comparator module.

Analog Comparator Run Mode Clock Gating Control (RCGCACMP)

Base 0x400F.E000
Offset 0x63C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 Analog Comparator Module 0 Run Mode Clock Gating Control

Value Description
0 Analog comparator module is disabled.
1 Enable and provide a clock to the analog comparator module
in Run mode.

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Register 101: Pulse Width Modulator Run Mode Clock Gating Control
(RCGCPWM), offset 0x640
The RCGCPWM register provides software the capability to enable and disable the PWM modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the PWM modules.

Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM)

Base 0x400F.E000
Offset 0x640
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 PWM Module 0 Run Mode Clock Gating Control

Value Description
0 PWM module 0 is disabled.
1 Enable and provide a clock to PWM module 0 in Run mode.

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Register 102: Quadrature Encoder Interface Run Mode Clock Gating Control
(RCGCQEI), offset 0x644
The RCGCQEI register provides software the capability to enable and disable the QEI modules in
Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the QEI modules.

Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI)

Base 0x400F.E000
Offset 0x644
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 QEI Module 0 Run Mode Clock Gating Control

Value Description
0 QEI module 0 is disabled.
1 Enable and provide a clock to QEI module 0 in Run mode.

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Register 103: EEPROM Run Mode Clock Gating Control (RCGCEEPROM),

offset 0x658
The RCGCEEPROM register provides software the capability to enable and disable the EEPROM
module in Run mode. When enabled, the module is provided a clock and accesses to module
registers are allowed. When disabled, the clock is disabled to save power and accesses to module
registers generate a bus fault.

EEPROM Run Mode Clock Gating Control (RCGCEEPROM)

Base 0x400F.E000
Offset 0x658
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 EEPROM Module 0 Run Mode Clock Gating Control

Value Description
0 EEPROM module is disabled.
1 Enable and provide a clock to the EEPROM module in Run
mode.

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Register 104: CRC Module Run Mode Clock Gating Control (RCGCCCM), offset
0x674
The RCGCCCM register provides software the capability to enable and disable the CRC in Run
mode. When enabled, the module is provided a clock and accesses to module registers are allowed.
When disabled, the clock is disabled to save power and accesses to module registers generate a
bus fault.

Important: This register should be used to control the clocking for the CRC module.

CRC Module Run Mode Clock Gating Control (RCGCCCM)

Base 0x400F.E000
Offset 0x674
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 CRC Run Mode Clock Gating Control

Value Description
0 The CRC5 module is disabled.
1 Enable and provide a clock to the CRC module in Run mode.

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Register 105: Ethernet MAC Run Mode Clock Gating Control (RCGCEMAC),
offset 0x69C
The RCGCEMAC register provides software the capability to enable and disable the Ethernet MAC
module in Run mode. When enabled, a module is provided a clock and accesses to module registers
are allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault.

Important: This register should be used to control the clocking for the Ethernet Controller module.

Ethernet MAC Run Mode Clock Gating Control (RCGCEMAC)

Base 0x400F.E000
Offset 0x69C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RW 0 Ethernet MAC Module 0 Run Mode Clock Gating Control

Value Description
0 Ethernet MAC module 0 is disabled.
1 Enable and provide a clock to Ethernet MAC module 0 in Run
mode.

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Register 106: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD),
offset 0x700
The SCGCWD register provides software the capability to enable and disable watchdog modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the watchdog modules.

Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD)

Base 0x400F.E000
Offset 0x700
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S1 S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 S1 RW 0 Watchdog Timer 1 Sleep Mode Clock Gating Control

Value Description
0 Watchdog module 1 is disabled in sleep mode.
1 Enable and provide a clock to Watchdog module 1 in sleep
mode.

0 S0 RW 0 Watchdog Timer 0 Sleep Mode Clock Gating Control

Value Description
0 Watchdog module 0 is disabled in sleep mode.
1 Enable and provide a clock to Watchdog module 0 in sleep
mode.

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Register 107: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating

Control (SCGCTIMER), offset 0x704
The SCGCGPT32 register provides software the capability to enable and disable 16/32-bit timer
modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the timer modules.

16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER)

Base 0x400F.E000
Offset 0x704
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S7 S6 S5 S4 S3 S2 S1 S0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 S7 RW 0 16/32-Bit General-Purpose Timer 7 Sleep Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 7 is disabled in sleep
mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 7 in sleep mode.

6 S6 RW 0 16/32-Bit General-Purpose Timer 6 Sleep Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 6 is disabled in sleep
mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 6 in sleep mode.

5 S5 RW 0 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 5 is disabled in sleep
mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 5 in sleep mode.

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Bit/Field Name Type Reset Description

4 S4 RW 0 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 4 is disabled in sleep
mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 4 in sleep mode.

3 S3 RW 0 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 3 is disabled in sleep
mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 3 in sleep mode.

2 S2 RW 0 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 2 is disabled in sleep
mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 2 in sleep mode.

1 S1 RW 0 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 1 is disabled in sleep
mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 1 in sleep mode.

0 S0 RW 0 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control

Value Description
0 16/32-bit general-purpose timer module 0 is disabled in sleep
mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 0 in sleep mode.

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Register 108: General-Purpose Input/Output Sleep Mode Clock Gating Control

(SCGCGPIO), offset 0x708
The SCGCGPIO register provides software the capability to enable and disable GPIO modules in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power.

Important: This register should be used to control the clocking for the GPIO modules.

General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO)

Base 0x400F.E000
Offset 0x708
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Type RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 S14 RW 0 GPIO Port Q Sleep Mode Clock Gating Control

Value Description
0 GPIO Port Q is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port Q in sleep mode.

13 S13 RW 0 GPIO Port P Sleep Mode Clock Gating Control

Value Description
0 GPIO Port P is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port P in sleep mode.

12 S12 RW 0 GPIO Port N Sleep Mode Clock Gating Control

Value Description
0 GPIO Port N is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port N in sleep mode.

11 S11 RW 0 GPIO Port M Sleep Mode Clock Gating Control

Value Description
0 GPIO Port M is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port M in sleep mode.

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Bit/Field Name Type Reset Description

10 S10 RW 0 GPIO Port L Sleep Mode Clock Gating Control

Value Description
0 GPIO Port L is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port L in sleep mode.

9 S9 RW 0 GPIO Port K Sleep Mode Clock Gating Control

Value Description
0 GPIO Port K is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port K in sleep mode.

8 S8 RW 0 GPIO Port J Sleep Mode Clock Gating Control

Value Description
0 GPIO Port J is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port J in sleep mode.

7 S7 RW 0 GPIO Port H Sleep Mode Clock Gating Control

Value Description
0 GPIO Port H is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port H in sleep mode.

6 S6 RW 0 GPIO Port G Sleep Mode Clock Gating Control

Value Description
0 GPIO Port G is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port G in sleep mode.

5 S5 RW 0 GPIO Port F Sleep Mode Clock Gating Control

Value Description
0 GPIO Port F is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port F in sleep mode.

4 S4 RW 0 GPIO Port E Sleep Mode Clock Gating Control

Value Description
0 GPIO Port E is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port E in sleep mode.

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Bit/Field Name Type Reset Description

3 S3 RW 0 GPIO Port D Sleep Mode Clock Gating Control

Value Description
0 GPIO Port D is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port D in sleep mode.

2 S2 RW 0 GPIO Port C Sleep Mode Clock Gating Control

Value Description
0 GPIO Port C is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port C in sleep mode.

1 S1 RW 0 GPIO Port B Sleep Mode Clock Gating Control

Value Description
0 GPIO Port B is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port B in sleep mode.

0 S0 RW 0 GPIO Port A Sleep Mode Clock Gating Control

Value Description
0 GPIO Port A is disabled in sleep mode.
1 Enable and provide a clock to GPIO Port A in sleep mode.

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Register 109: Micro Direct Memory Access Sleep Mode Clock Gating Control
(SCGCDMA), offset 0x70C
The SCGCDMA register provides software the capability to enable and disable the μDMA module
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the μDMA module.

Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA)
Base 0x400F.E000
Offset 0x70C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 μDMA Module Sleep Mode Clock Gating Control

Value Description
0 μDMA module is disabled in sleep mode.
1 Enable and provide a clock to the μDMA module in sleep mode.

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Register 110: EPI Sleep Mode Clock Gating Control (SCGCEPI), offset 0x710
The SCGCEPI register provides software the capability to enable and disable the EPI module in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power.

Important: This register should be used to control the clocking for the EPI module.

EPI Sleep Mode Clock Gating Control (SCGCEPI)

Base 0x400F.E000
Offset 0x710
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 EPI Module Sleep Mode Clock Gating Control

Value Description
0 EPI module is disabled in sleep mode.
1 Enable and provide a clock to the EPI module in sleep mode.

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Register 111: Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset
0x714
The SCGCHIB register provides software the capability to enable and disable the Hibernation module
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the Hibernation module.

Hibernation Sleep Mode Clock Gating Control (SCGCHIB)

Base 0x400F.E000
Offset 0x714
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 1 Hibernation Module Sleep Mode Clock Gating Control

Value Description
0 Hibernation module is disabled in sleep mode.
1 Enable and provide a clock to the Hibernation module in sleep
mode.

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Register 112: Universal Asynchronous Receiver/Transmitter Sleep Mode

Clock Gating Control (SCGCUART), offset 0x718
The SCGCUART register provides software the capability to enable and disable the UART modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the UART modules.

Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART)

Base 0x400F.E000
Offset 0x718
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S7 S6 S5 S4 S3 S2 S1 S0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 S7 RW 0 UART Module 7 Sleep Mode Clock Gating Control

Value Description
0 UART module 7 is disabled in sleep mode.
1 Enable and provide a clock to UART module 7 in sleep mode.

6 S6 RW 0 UART Module 6 Sleep Mode Clock Gating Control

Value Description
0 UART module 6 is disabled in sleep mode.
1 Enable and provide a clock to UART module 6 in sleep mode.

5 S5 RW 0 UART Module 5 Sleep Mode Clock Gating Control

Value Description
0 UART module 5 is disabled in sleep mode.
1 Enable and provide a clock to UART module 5 in sleep mode.

4 S4 RW 0 UART Module 4 Sleep Mode Clock Gating Control

Value Description
0 UART module 4 is disabled.
1 Enable and provide a clock to UART module 4 in sleep mode.

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Bit/Field Name Type Reset Description

3 S3 RW 0 UART Module 3 Sleep Mode Clock Gating Control

Value Description
0 UART module 3 is disabled in sleep mode.
1 Enable and provide a clock to UART module 3 in sleep mode.

2 S2 RW 0 UART Module 2 Sleep Mode Clock Gating Control

Value Description
0 UART module 2 is disabled in sleep mode.
1 Enable and provide a clock to UART module 2 in sleep mode.

1 S1 RW 0 UART Module 1 Sleep Mode Clock Gating Control

Value Description
0 UART module 1 is disabled in sleep mode.
1 Enable and provide a clock to UART module 1 in sleep mode.

0 S0 RW 0 UART Module 0 Sleep Mode Clock Gating Control

Value Description
0 UART module 0 is disabled.
1 Enable and provide a clock to UART module 0 in sleep mode.

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Register 113: Synchronous Serial Interface Sleep Mode Clock Gating Control
(SCGCSSI), offset 0x71C
The SCGCSSI register provides software the capability to enable and disable the SSI modules in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power.

Important: This register should be used to control the clocking for the SSI modules.

Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI)

Base 0x400F.E000
Offset 0x71C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S3 S2 S1 S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 S3 RW 0 SSI Module 3 Sleep Mode Clock Gating Control

Value Description
0 SSI module 3 is disabled in sleep mode.
1 Enable and provide a clock to SSI module 3 in sleep mode.

2 S2 RW 0 SSI Module 2 Sleep Mode Clock Gating Control

Value Description
0 SSI module 2 is disabled in sleep mode.
1 Enable and provide a clock to SSI module 2 in sleep mode.

1 S1 RW 0 SSI Module 1 Sleep Mode Clock Gating Control

Value Description
0 SSI module 1 is disabled in sleep mode.
1 Enable and provide a clock to SSI module 1 in sleep mode.

0 S0 RW 0 SSI Module 0 Sleep Mode Clock Gating Control

Value Description
0 SSI module 0 is disabled in sleep mode.
1 Enable and provide a clock to SSI module 0 in sleep mode.

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Register 114: Inter-Integrated Circuit Sleep Mode Clock Gating Control

(SCGCI2C), offset 0x720
The SCGCI2C register provides software the capability to enable and disable the I2C modules in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power.

Important: This register should be used to control the clocking for the I2C modules.

Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C)

Base 0x400F.E000
Offset 0x720
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Type RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 S9 RW 0 I2C Module 9 Sleep Mode Clock Gating Control

Value Description
0 I2C module 9 is disabled in sleep mode.
1 Enable and provide a clock to I2C module 9 in sleep mode.

8 S8 RW 0 I2C Module 8 Sleep Mode Clock Gating Control

Value Description
0 I2C module 8 is disabled in sleep mode.
1 Enable and provide a clock to I2C module 8 in sleep mode.

7 S7 RW 0 I2C Module 7 Sleep Mode Clock Gating Control

Value Description
0 I2C module 7 is disabled in sleep mode.
1 Enable and provide a clock to I2C module 7 in sleep mode.

6 S6 RW 0 I2C Module 6 Sleep Mode Clock Gating Control

Value Description
0 I2C module 6 is disabled in sleep mode.
1 Enable and provide a clock to I2C module 6 in sleep mode.

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Bit/Field Name Type Reset Description

5 S5 RW 0 I2C Module 5 Sleep Mode Clock Gating Control

Value Description
0 I2C module 5 is disabled in sleep mode.
1 Enable and provide a clock to I2C module 5 in sleep mode.

4 S4 RW 0 I2C Module 4 Sleep Mode Clock Gating Control

Value Description
0 I2C module 4 is disabled in sleep mode.
1 Enable and provide a clock to I2C module 4 in sleep mode.

3 S3 RW 0 I2C Module 3 Sleep Mode Clock Gating Control

Value Description
0 I2C module 3 is disabled in sleep mode.
1 Enable and provide a clock to I2C module 3 in sleep mode.

2 S2 RW 0 I2C Module 2 Sleep Mode Clock Gating Control

Value Description
0 I2C module 2 is disabled in sleep mode.
1 Enable and provide a clock to I2C module 2 in sleep mode.

1 S1 RW 0 I2C Module 1 Sleep Mode Clock Gating Control

Value Description
0 I2C module 1 is disabled in sleep mode.
1 Enable and provide a clock to I2C module 1 in sleep mode.

0 S0 RW 0 I2C Module 0 Sleep Mode Clock Gating Control

Value Description
0 I2C module 0 is disabled.
1 Enable and provide a clock to I2C module 0 in sleep mode.

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Register 115: Universal Serial Bus Sleep Mode Clock Gating Control
(SCGCUSB), offset 0x728
The SCGCUSB register provides software the capability to enable and disable the USB module in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power.

Important: This register should be used to control the clocking for the USB module.

Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB)

Base 0x400F.E000
Offset 0x728
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 USB Module Sleep Mode Clock Gating Control

Value Description
0 USB module is disabled in sleep mode.
1 Enable and provide a clock to the USB module in sleep mode.

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Register 116: Ethernet PHY Sleep Mode Clock Gating Control (SCGCEPHY),
offset 0x730
The SCGCEPHY register provides software the capability to enable and disable the PHY module
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the PHY module.

Ethernet PHY Sleep Mode Clock Gating Control (SCGCEPHY)

Base 0x400F.E000
Offset 0x730
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 PHY Module Sleep Mode Clock Gating Control

Value Description
0 PHY module is disabled in sleep mode.
1 Enable and provide a clock to the PHY module in sleep mode.

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Register 117: Controller Area Network Sleep Mode Clock Gating Control
(SCGCCAN), offset 0x734
The SCGCCAN register provides software the capability to enable and disable the CAN modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the CAN modules.

Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN)

Base 0x400F.E000
Offset 0x734
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S1 S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 S1 RW 0 CAN Module 1 Sleep Mode Clock Gating Control

Value Description
0 CAN module 1 is disabled in sleep mode.
1 Enable and provide a clock to CAN module 1 in sleep mode.

0 S0 RW 0 CAN Module 0 Sleep Mode Clock Gating Control

Value Description
0 CAN module 0 is disabled.
1 Enable and provide a clock to CAN module 0 in sleep mode.

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Register 118: Analog-to-Digital Converter Sleep Mode Clock Gating Control

(SCGCADC), offset 0x738
The SCGCADC register provides software the capability to enable and disable the ADC modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the ADC modules.

Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC)

Base 0x400F.E000
Offset 0x738
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S1 S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 S1 RW 0 ADC Module 1 Sleep Mode Clock Gating Control

Value Description
0 ADC module 1 is disabled in sleep mode.
1 Enable and provide a clock to ADC module 1 in sleep mode.

0 S0 RW 0 ADC Module 0 Sleep Mode Clock Gating Control

Value Description
0 ADC module 0 is disabled in sleep mode.
1 Enable and provide a clock to ADC module 0 in sleep mode.

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Register 119: Analog Comparator Sleep Mode Clock Gating Control

(SCGCACMP), offset 0x73C
The SCGCACMP register provides software the capability to enable and disable the analog
comparator module in sleep mode. When enabled, a module is provided a clock. When disabled,
the clock is disabled to save power.

Important: This register should be used to control the clocking for the analog comparator module.

Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP)

Base 0x400F.E000
Offset 0x73C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 Analog Comparator Module 0 Sleep Mode Clock Gating Control

Value Description
0 Analog comparator module is disabled in sleep mode.
1 Enable and provide a clock to the analog comparator module
in sleep mode.

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Register 120: Pulse Width Modulator Sleep Mode Clock Gating Control
(SCGCPWM), offset 0x740
The SCGCPWM register provides software the capability to enable and disable the PWM modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the PWM modules.

Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM)

Base 0x400F.E000
Offset 0x740
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 PWM Module 0 Sleep Mode Clock Gating Control

Value Description
0 PWM module 0 is disabled in sleep mode.
1 Enable and provide a clock to PWM module 0 in sleep mode.

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Register 121: Quadrature Encoder Interface Sleep Mode Clock Gating Control
(SCGCQEI), offset 0x744
The SCGCQEI register provides software the capability to enable and disable the QEI modules in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power.

Important: This register should be used to control the clocking for the QEI modules.

Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI)

Base 0x400F.E000
Offset 0x744
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 QEI Module 0 Sleep Mode Clock Gating Control

Value Description
0 QEI module 0 is disabled in sleep mode.
1 Enable and provide a clock to QEI module 0 in sleep mode.

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Register 122: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM),

offset 0x758
The SCGCEEPROM register provides software the capability to enable and disable the EEPROM
module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM)

Base 0x400F.E000
Offset 0x758
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 EEPROM Module 0 Sleep Mode Clock Gating Control

Value Description
0 EEPROM module is disabled.
1 Enable and provide a clock to the EEPROM module in sleep
mode.

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Register 123: CRC Module Sleep Mode Clock Gating Control (SCGCCCM),
offset 0x774
The SCGCCCM register provides software the capability to enable and disable the CRC module in
sleep mode. When enabled, the module is provided a clock . When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the CRC module.

CRC Module Sleep Mode Clock Gating Control (SCGCCCM)

Base 0x400F.E000
Offset 0x774
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 CRC Module Sleep Mode Clock Gating Control

Value Description
0 The CRC module is disabled in sleep mode.
1 Enable and provide a clock to the CRC module in sleep mode.

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Register 124: Ethernet MAC Sleep Mode Clock Gating Control (SCGCEMAC),
offset 0x79C
The SCGCEMAC register provides software the capability to enable and disable the Ethernet MAC
module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the Ethernet MAC module.

Ethernet MAC Sleep Mode Clock Gating Control (SCGCEMAC)

Base 0x400F.E000
Offset 0x79C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved S0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 S0 RW 0 Ethernet MAC Module 0 Sleep Mode Clock Gating Control

Value Description
0 Ethernet MAC module 0 is disabled in sleep mode.
1 Enable and provide a clock to Ethernet MAC module 0 in sleep
mode.

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Register 125: Watchdog Timer Deep-Sleep Mode Clock Gating Control

(DCGCWD), offset 0x800
The DCGCWD register provides software the capability to enable and disable watchdog modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the watchdog modules.

Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD)

Base 0x400F.E000
Offset 0x800
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D1 D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 D1 RW 0 Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control

Value Description
0 Watchdog module 1 is disabled in deep-sleep mode.
1 Enable and provide a clock to Watchdog module 1 in deep-sleep
mode.

0 D0 RW 0 Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 Watchdog module 0 is disabled in deep-sleep mode.
1 Enable and provide a clock to Watchdog module 0 in deep-sleep
mode.

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Register 126: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating

Control (DCGCTIMER), offset 0x804
The DCGCGPT32 register provides software the capability to enable and disable 16/32-bit timer
modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the
clock is disabled to save power.

Important: This register should be used to control the clocking for the timer modules.

16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER)

Base 0x400F.E000
Offset 0x804
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D7 D6 D5 D4 D3 D2 D1 D0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 D7 RW 0 16/32-Bit General-Purpose Timer 7 Deep-Sleep Mode Clock Gating

Control

Value Description
0 16/32-bit general-purpose timer module 7 is disabled in
deep-sleep mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 7 in deep-sleep mode.

6 D6 RW 0 16/32-Bit General-Purpose Timer 6 Deep-Sleep Mode Clock Gating

Control

Value Description
0 16/32-bit general-purpose timer module 6 is disabled in
deep-sleep mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 6 in deep-sleep mode.

5 D5 RW 0 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating

Control

Value Description
0 16/32-bit general-purpose timer module 5 is disabled in
deep-sleep mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 5 in deep-sleep mode.

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Bit/Field Name Type Reset Description

4 D4 RW 0 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating

Control

Value Description
0 16/32-bit general-purpose timer module 4 is disabled in
deep-sleep mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 4 in deep-sleep mode.

3 D3 RW 0 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating

Control

Value Description
0 16/32-bit general-purpose timer module 3 is disabled in
deep-sleep mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 3 in deep-sleep mode.

2 D2 RW 0 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating

Control

Value Description
0 16/32-bit general-purpose timer module 2 is disabled in
deep-sleep mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 2 in deep-sleep mode.

1 D1 RW 0 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating

Control

Value Description
0 16/32-bit general-purpose timer module 1 is disabled in
deep-sleep mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 1 in deep-sleep mode.

0 D0 RW 0 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating

Control

Value Description
0 16/32-bit general-purpose timer module 0 is disabled in
deep-sleep mode.
1 Enable and provide a clock to 16/32-bit general-purpose timer
module 0 in deep-sleep mode.

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Register 127: General-Purpose Input/Output Deep-Sleep Mode Clock Gating

Control (DCGCGPIO), offset 0x808
The DCGCGPIO register provides software the capability to enable and disable GPIO modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the GPIO modules.

General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO)

Base 0x400F.E000
Offset 0x808
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Type RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 D14 RW 0 GPIO Port Q Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port Q is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port Q in deep-sleep mode.

13 D13 RW 0 GPIO Port P Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port P is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port P in deep-sleep mode.

12 D12 RW 0 GPIO Port N Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port N is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port N in deep-sleep mode.

11 D11 RW 0 GPIO Port M Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port M is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port M in deep-sleep mode.

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Bit/Field Name Type Reset Description

10 D10 RW 0 GPIO Port L Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port L is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port L in deep-sleep mode.

9 D9 RW 0 GPIO Port K Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port K is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port K in deep-sleep mode.

8 D8 RW 0 GPIO Port J Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port J is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port J in deep-sleep mode.

7 D7 RW 0 GPIO Port H Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port H is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port H in deep-sleep mode.

6 D6 RW 0 GPIO Port G Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port G is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port G in deep-sleep mode.

5 D5 RW 0 GPIO Port F Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port F is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port F in deep-sleep mode.

4 D4 RW 0 GPIO Port E Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port E is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port E in deep-sleep mode.

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Bit/Field Name Type Reset Description

3 D3 RW 0 GPIO Port D Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port D is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port D in deep-sleep mode.

2 D2 RW 0 GPIO Port C Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port C is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port C in deep-sleep mode.

1 D1 RW 0 GPIO Port B Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port B is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port B in deep-sleep mode.

0 D0 RW 0 GPIO Port A Deep-Sleep Mode Clock Gating Control

Value Description
0 GPIO Port A is disabled in deep-sleep mode.
1 Enable and provide a clock to GPIO Port A in deep-sleep mode.

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Register 128: Micro Direct Memory Access Deep-Sleep Mode Clock Gating
Control (DCGCDMA), offset 0x80C
The DCGCDMA register provides software the capability to enable and disable the μDMA module
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the μDMA module.

Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA)
Base 0x400F.E000
Offset 0x80C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 μDMA Module Deep-Sleep Mode Clock Gating Control

Value Description
0 μDMA module is disabled in deep-sleep mode.
1 Enable and provide a clock to the μDMA module in deep-sleep
mode.

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Register 129: EPI Deep-Sleep Mode Clock Gating Control (DCGCEPI), offset
0x810
The DCGCEPI register provides software the capability to enable and disable the EPI module in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the EPI module.

EPI Deep-Sleep Mode Clock Gating Control (DCGCEPI)

Base 0x400F.E000
Offset 0x810
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 EPI Module Deep-Sleep Mode Clock Gating Control

Value Description
0 EPI module is disabled in deep-sleep mode.
1 Enable and provide a clock to the EPI module in deep-sleep
mode.

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Register 130: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB),

offset 0x814
The DCGCHIB register provides software the capability to enable and disable the Hibernation
module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock
is disabled to save power.

Important: This register should be used to control the clocking for the Hibernation module.

Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB)

Base 0x400F.E000
Offset 0x814
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 1 Hibernation Module Deep-Sleep Mode Clock Gating Control

Value Description
0 Hibernation module is disabled in deep-sleep mode.
1 Enable and provide a clock to the Hibernation module in
deep-sleep mode.

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Register 131: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode

Clock Gating Control (DCGCUART), offset 0x818
The DCGCUART register provides software the capability to enable and disable the UART modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the UART modules.

Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART)

Base 0x400F.E000
Offset 0x818
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D7 D6 D5 D4 D3 D2 D1 D0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 D7 RW 0 UART Module 7 Deep-Sleep Mode Clock Gating Control

Value Description
0 UART module 7 is disabled in deep-sleep mode.
1 Enable and provide a clock to UART module 7 in deep-sleep
mode.

6 D6 RW 0 UART Module 6 Deep-Sleep Mode Clock Gating Control

Value Description
0 UART module 6 is disabled in deep-sleep mode.
1 Enable and provide a clock to UART module 6 in deep-sleep
mode.

5 D5 RW 0 UART Module 5 Deep-Sleep Mode Clock Gating Control

Value Description
0 UART module 5 is disabled in deep-sleep mode.
1 Enable and provide a clock to UART module 5 in deep-sleep
mode.

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Bit/Field Name Type Reset Description

4 D4 RW 0 UART Module 4 Deep-Sleep Mode Clock Gating Control

Value Description
0 UART module 4 is disabled in deep-sleep mode.
1 Enable and provide a clock to UART module 4 in deep-sleep
mode.

3 D3 RW 0 UART Module 3 Deep-Sleep Mode Clock Gating Control

Value Description
0 UART module 3 is disabled in deep-sleep mode.
1 Enable and provide a clock to UART module 3 in deep-sleep
mode.

2 D2 RW 0 UART Module 2 Deep-Sleep Mode Clock Gating Control

Value Description
0 UART module 2 is disabled in deep-sleep mode.
1 Enable and provide a clock to UART module 2 in deep-sleep
mode.

1 D1 RW 0 UART Module 1 Deep-Sleep Mode Clock Gating Control

Value Description
0 UART module 1 is disabled in deep-sleep mode.
1 Enable and provide a clock to UART module 1 in deep-sleep
mode.

0 D0 RW 0 UART Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 UART module 0 is disabled in deep-sleep mode.
1 Enable and provide a clock to UART module 0 in deep-sleep
mode.

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Register 132: Synchronous Serial Interface Deep-Sleep Mode Clock Gating

Control (DCGCSSI), offset 0x81C
The DCGCSSI register provides software the capability to enable and disable the SSI modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the SSI modules.

Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI)

Base 0x400F.E000
Offset 0x81C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D3 D2 D1 D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 D3 RW 0 SSI Module 3 Deep-Sleep Mode Clock Gating Control

Value Description
0 SSI module 3 is disabled in deep-sleep mode.
1 Enable and provide a clock to SSI module 3 in deep-sleep mode.

2 D2 RW 0 SSI Module 2 Deep-Sleep Mode Clock Gating Control

Value Description
0 SSI module 2 is disabled in deep-sleep mode.
1 Enable and provide a clock to SSI module 2 in deep-sleep mode.

1 D1 RW 0 SSI Module 1 Deep-Sleep Mode Clock Gating Control

Value Description
0 SSI module 1 is disabled in deep-sleep mode.
1 Enable and provide a clock to SSI module 1 in deep-sleep mode.

0 D0 RW 0 SSI Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 SSI module 0 is disabled in deep-sleep mode.
1 Enable and provide a clock to SSI module 0 in deep-sleep mode.

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Register 133: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control

(DCGCI2C), offset 0x820
The DCGCI2C register provides software the capability to enable and disable the I2C modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the I2C modules.

Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C)

Base 0x400F.E000
Offset 0x820
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Type RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 D9 RW 0 I2C Module 9 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 9 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 9 in deep-sleep mode.

8 D8 RW 0 I2C Module 8 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 8 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 8 in deep-sleep mode.

7 D7 RW 0 I2C Module 7 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 7 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 7 in deep-sleep mode.

6 D6 RW 0 I2C Module 6 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 6 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 6 in deep-sleep mode.

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Bit/Field Name Type Reset Description

5 D5 RW 0 I2C Module 5 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 5 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 5 in deep-sleep mode.

4 D4 RW 0 I2C Module 4 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 4 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 4 in deep-sleep mode.

3 D3 RW 0 I2C Module 3 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 3 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 3 in deep-sleep mode.

2 D2 RW 0 I2C Module 2 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 2 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 2 in deep-sleep mode.

1 D1 RW 0 I2C Module 1 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 1 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 1 in deep-sleep mode.

0 D0 RW 0 I2C Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 I2C module 0 is disabled in deep-sleep mode.
1 Enable and provide a clock to I2C module 0 in deep-sleep mode.

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Register 134: Universal Serial Bus Deep-Sleep Mode Clock Gating Control
(DCGCUSB), offset 0x828
The DCGCUSB register provides software the capability to enable and disable the USB module in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the USB module.

Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB)

Base 0x400F.E000
Offset 0x828
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 USB Module Deep-Sleep Mode Clock Gating Control

Value Description
0 USB module is disabled in deep-sleep mode.
1 Enable and provide a clock to the USB module in deep-sleep
mode.

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Register 135: Ethernet PHY Deep-Sleep Mode Clock Gating Control

(DCGCEPHY), offset 0x830
The DCGCEPHY register provides software the capability to enable and disable the PHY module
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the PHY module.

Ethernet PHY Deep-Sleep Mode Clock Gating Control (DCGCEPHY)

Base 0x400F.E000
Offset 0x830
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 PHY Module Deep-Sleep Mode Clock Gating Control

Value Description
0 PHY module is disabled in deep-sleep mode.
1 Enable and provide a clock to the PHY module in deep-sleep
mode.

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Register 136: Controller Area Network Deep-Sleep Mode Clock Gating Control
(DCGCCAN), offset 0x834
The DCGCCAN register provides software the capability to enable and disable the CAN modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the CAN modules.

Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN)

Base 0x400F.E000
Offset 0x834
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D1 D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 D1 RW 0 CAN Module 1 Deep-Sleep Mode Clock Gating Control

Value Description
0 CAN module 1 is disabled in deep-sleep mode.
1 Enable and provide a clock to CAN module 1 in deep-sleep
mode.

0 D0 RW 0 CAN Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 CAN module 0 is disabled in deep-sleep mode.
1 Enable and provide a clock to CAN module 0 in deep-sleep
mode.

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Register 137: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating

Control (DCGCADC), offset 0x838
The DCGCADC register provides software the capability to enable and disable the ADC modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the ADC modules.

Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC)

Base 0x400F.E000
Offset 0x838
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D1 D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 D1 RW 0 ADC Module 1 Deep-Sleep Mode Clock Gating Control

Value Description
0 ADC module 1 is disabled in deep-sleep mode.
1 Enable and provide a clock to ADC module 1 in deep-sleep
mode.

0 D0 RW 0 ADC Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 ADC module 0 is disabled in deep-sleep mode.
1 Enable and provide a clock to ADC module 0 in deep-sleep
mode.

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Register 138: Analog Comparator Deep-Sleep Mode Clock Gating Control

(DCGCACMP), offset 0x83C
The DCGCACMP register provides software the capability to enable and disable the analog
comparator module in deep-sleep mode. When enabled, a module is provided a clock. When
disabled, the clock is disabled to save power.

Important: This register should be used to control the clocking for the analog comparator module.

Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP)

Base 0x400F.E000
Offset 0x83C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 Analog comparator module is disabled in deep-sleep mode.
1 Enable and provide a clock to the analog comparator module
in deep-sleep mode.

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Register 139: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control
(DCGCPWM), offset 0x840
The DCGCPWM register provides software the capability to enable and disable the PWM modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the PWM modules.

Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM)

Base 0x400F.E000
Offset 0x840
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 PWM Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 PWM module 0 is disabled in deep-sleep mode.
1 Enable and provide a clock to PWM module 0 in deep-sleep
mode.

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Register 140: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating

Control (DCGCQEI), offset 0x844
The DCGCQEI register provides software the capability to enable and disable the QEI modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.

Important: This register should be used to control the clocking for the QEI modules.

Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI)

Base 0x400F.E000
Offset 0x844
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 QEI Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 QEI module 0 is disabled in deep-sleep mode.
1 Enable and provide a clock to QEI module 0 in deep-sleep
mode.

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Register 141: EEPROM Deep-Sleep Mode Clock Gating Control

(DCGCEEPROM), offset 0x858
The DCGCEEPROM register provides software the capability to enable and disable the EEPROM
module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock
is disabled to save power.

EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM)

Base 0x400F.E000
Offset 0x858
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 EEPROM Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 EEPROM module is disabled in deep-sleep mode.
1 Enable and provide a clock to the EEPROM module in
deep-sleep mode.

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Register 142: CRC Module Deep-Sleep Mode Clock Gating Control

(DCGCCCM), offset 0x874
The DCGCCCM register provides software the capability to enable and disable the CRC module in
deep-sleep mode. When enabled, the module is provided a clock. When disabled, the clock is
disabled to save power.

Important: This register should be used to control the clocking for the CRC module.

CRC Module Deep-Sleep Mode Clock Gating Control (DCGCCCM)

Base 0x400F.E000
Offset 0x874
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 CRC Module Deep-Sleep Mode Clock Gating Control

Value Description
0 The CRC module is disabled in deep-sleep mode.
1 Enable and provide a clock to the CRC module in deep-sleep
mode.

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Register 143: Ethernet MAC Deep-Sleep Mode Clock Gating Control

(DCGCEMAC), offset 0x89C
The DCGCEMAC register provides software the capability to enable and disable the Ethernet MAC
module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock
is disabled to save power.

Important: This register should be used to control the clocking for the Ethernet MAC module.

Ethernet MAC Deep-Sleep Mode Clock Gating Control (DCGCEMAC)

Base 0x400F.E000
Offset 0x89C
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved D0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 D0 RW 0 Ethernet MAC Module 0 Deep-Sleep Mode Clock Gating Control

Value Description
0 Ethernet MAC module 0 is disabled in deep-sleep mode.
1 Enable and provide a clock to Ethernet MAC module 0 in
deep-sleep mode.

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Register 144: Watchdog Timer Power Control (PCWD), offset 0x900

Important: The Watchdog Timer modules do not currently provide the ability to respond to the
power down request. Setting a bit in this register has no effect on power consumption.
This register is defined for future software compatibility.

The PCWD register controls the power applied to the Watchdog Module module. The function of
this bit depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of
the corresponding bits in the RCGCWD, SCGCWD and DCGCWD registers. If the Rn, Sn, or Dn
bit of the respective RCGCWD, SCGCWD and DCGCWD registers is 1 and the device is in that
mode, the module is powered and receives a clock irrespective of what the corresponding Pn bit in
the PCWD register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCWD, SCGCWD and DCGCWD registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCWD register. In this case, when the Pn bit is clear the module is
not powered and does not receive a clock. If the Pn bit is set, the module is powered but does not
receive a clock. The table below details the differences.

Table 5-16. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Watchdog Timer Power Control (PCWD)

Base 0x400F.E000
Offset 0x900
Type RW, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

1 P1 RW 1 Watchdog Timer 1 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCWD, SCGCWD or DCGCWD register is clear.

Value Description
0 Watchdog Timer 1 module is not powered and does not receive
a clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Watchdog Timer 1 module is powered, but does not receive a
clock. In this case, the module is inactive.

0 P0 RW 1 Watchdog Timer 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCWD, SCGCWD or DCGCWD register is clear.

Value Description
0 Watchdog Timer 0 module is not powered and does not receive
a clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Watchdog Timer 0 module is powered, but does not receive a
clock. In this case, the module is inactive.

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Register 145: 16/32-Bit General-Purpose Timer Power Control (PCTIMER),

offset 0x904
Important: The Timer module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCTIMER register controls the power applied to the Timer module. The function of this bit
depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the
corresponding bits in the RCGCTIMER, SCGCTIMER and DCGCTIMER registers. If the Rn, Sn, or
Dn bit of the respective RCGCTIMER, SCGCTIMER and DCGCTIMER registers is 1 and the device
is in that mode, the module is powered and receives a clock irrespective of what the corresponding
Pn bit in the PCTIMER register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCTIMER, SCGCTIMER and DCGCTIMER
registers is 0 and the device is in that mode, then the module behaves differently depending on the
value of the corresponding Pn bit in the PCTIMER register. In this case, when the Pn bit is clear the
module is not powered and does not receive a clock. If the Pn bit is set, the module is powered but
does not receive a clock. The table below details the differences.

Table 5-17. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

16/32-Bit General-Purpose Timer Power Control (PCTIMER)

Base 0x400F.E000
Offset 0x904
Type RW, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P7 P6 P5 P4 P3 P2 P1 P0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

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Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 P7 RW 1 General-Purpose Timer 7 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear.

Value Description
0 Timer 7 module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Timer 7 module is powered, but does not receive a clock. In this
case, the module is inactive.

6 P6 RW 1 General-Purpose Timer 6 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear.

Value Description
0 Timer 6 module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Timer 6 module is powered, but does not receive a clock. In this
case, the module is inactive.

5 P5 RW 1 General-Purpose Timer 5 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear.

Value Description
0 Timer 5 module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Timer 5 module is powered, but does not receive a clock. In this
case, the module is inactive.

4 P4 RW 1 General-Purpose Timer 4 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear.

Value Description
0 Timer 4 module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Timer 4 module is powered, but does not receive a clock. In this
case, the module is inactive.

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Bit/Field Name Type Reset Description

3 P3 RW 1 General-Purpose Timer 3 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear.

Value Description
0 Timer 3 module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Timer 3 module is powered, but does not receive a clock. In this
case, the module is inactive.

2 P2 RW 1 General-Purpose Timer 2 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear.

Value Description
0 Timer 2 module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Timer 2 module is powered, but does not receive a clock. In this
case, the module is inactive.

1 P1 RW 1 General-Purpose Timer 1 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear.

Value Description
0 Timer 1 module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Timer 1 module is powered, but does not receive a clock. In this
case, the module is inactive.

0 P0 RW 1 General-Purpose Timer 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear.

Value Description
0 Timer 0 module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Timer 0 module is powered, but does not receive a clock. In this
case, the module is inactive.

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Register 146: General-Purpose Input/Output Power Control (PCGPIO), offset

0x908
Important: The GPIO modules do not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCGPIO register controls the power applied to the GPIO module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCGPIO, SCGCGPIO and DCGCGPIO registers. If the Rn, Sn, or Dn bit of the
respective RCGCGPIO, SCGCGPIO and DCGCGPIO registers is 1 and the device is in that mode,
the module is powered and receives a clock irrespective of what the corresponding Pn bit in the
PCGPIO register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCGPIO, SCGCGPIO and DCGCGPIO
registers is 0 and the device is in that mode, then the module behaves differently depending on the
value of the corresponding Pn bit in the PCGPIO register. In this case, when the Pn bit is clear the
module is not powered and does not receive a clock. If the Pn bit is set, the module is powered but
does not receive a clock. The table below details the differences.

Table 5-18. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

General-Purpose Input/Output Power Control (PCGPIO)

Base 0x400F.E000
Offset 0x908
Type RW, reset 0x0000.7FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

Type RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Bit/Field Name Type Reset Description

31:15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 P14 RW 1 GPIO Port Q Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port Q is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port Q is powered, but does not receive a clock. In this
case, the module is inactive.

13 P13 RW 1 GPIO Port P Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port P is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port P is powered, but does not receive a clock. In this
case, the module is inactive.

12 P12 RW 1 GPIO Port N Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port N is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port N is powered, but does not receive a clock. In this
case, the module is inactive.

11 P11 RW 1 GPIO Port M Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port M is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port M is powered, but does not receive a clock. In this
case, the module is inactive.

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Bit/Field Name Type Reset Description

10 P10 RW 1 GPIO Port L Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port L is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port L is powered, but does not receive a clock. In this
case, the module is inactive.

9 P9 RW 1 GPIO Port K Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port K is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port K is powered, but does not receive a clock. In this
case, the module is inactive.

8 P8 RW 1 GPIO Port J Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port J is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port J is powered, but does not receive a clock. In this
case, the module is inactive.

7 P7 RW 1 GPIO Port H Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port H is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port H is powered, but does not receive a clock. In this
case, the module is inactive.

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Bit/Field Name Type Reset Description

6 P6 RW 1 GPIO Port G Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port G is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port G is powered, but does not receive a clock. In this
case, the module is inactive.

5 P5 RW 1 GPIO Port F Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port F is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port F is powered, but does not receive a clock. In this
case, the module is inactive.

4 P4 RW 1 GPIO Port E Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port E is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port E is powered, but does not receive a clock. In this
case, the module is inactive.

3 P3 RW 1 GPIO Port D Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port D is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port D is powered, but does not receive a clock. In this
case, the module is inactive.

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Bit/Field Name Type Reset Description

2 P2 RW 1 GPIO Port C Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port C is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port C is powered, but does not receive a clock. In this
case, the module is inactive.

1 P1 RW 1 GPIO Port B Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port B is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port B is powered, but does not receive a clock. In this
case, the module is inactive.

0 P0 RW 1 GPIO Port A Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.

Value Description
0 GPIO Port A is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 GPIO Port A is powered, but does not receive a clock. In this
case, the module is inactive.

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Register 147: Micro Direct Memory Access Power Control (PCDMA), offset
0x90C
Important: The µDMA module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCDMA register controls the power applied to the DMA module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCDMA, SCGCDMA and DCGCDMA registers. If the Rn, Sn, or Dn bit of the respective
RCGCDMA, SCGCDMA and DCGCDMA registers is 1 and the device is in that mode, the module
is powered and receives a clock irrespective of what the corresponding Pn bit in the PCDMA register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCDMA, SCGCDMA and DCGCDMA registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCDMA register. In this case, when the Pn bit is clear the module
is not powered and does not receive a clock. If the Pn bit is set, the module is powered but does
not receive a clock. The table below details the differences.

Table 5-19. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Micro Direct Memory Access Power Control (PCDMA)

Base 0x400F.E000
Offset 0x90C
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

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Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RW 1 μDMA Module Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCDMA, SCGCDMA or DCGCDMA register is clear.

Value Description
0 The µDMA module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The µDMA module is powered, but does not receive a clock. In
this case, the module is inactive.

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Register 148: External Peripheral Interface Power Control (PCEPI), offset

0x910
Important: The EPI module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCEPI register controls the power applied to the EPI module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCEPI, SCGCEPI and DCGCEPI registers. If the Rn, Sn, or Dn bit of the respective
RCGCEPI, SCGCEPI and DCGCEPI registers is 1 and the device is in that mode, the module is
powered and receives a clock irrespective of what the corresponding Pn bit in the PCEPI register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCEPI, SCGCEPI and DCGCEPI registers is
0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCEPI register. In this case, when the Pn bit is clear the module is
not powered and does not receive a clock. If the Pn bit is set, the module is powered but does not
receive a clock. The table below details the differences.

Table 5-20. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

External Peripheral Interface Power Control (PCEPI)

Base 0x400F.E000
Offset 0x910
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

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Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RW 1 EPI Module Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCEPI, SCGCEPI or DCGCEPI register is clear.

Value Description
0 The EPI module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The EPI module is powered, but does not receive a clock. In
this case, the module is inactive.

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Register 149: Hibernation Power Control (PCHIB), offset 0x914

Important: The Hibernation module does not currently provide the ability to respond to the power
down request. Setting a bit in this register has no effect on power consumption. This
register is defined for future software compatibility.

The PCHIB register controls the power applied to the HIB module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCHIB, SCGCHIB and DCGCHIB registers. If the Rn, Sn, or Dn bit of the respective
RCGCHIB, SCGCHIB and DCGCHIB registers is 1 and the device is in that mode, the module is
powered and receives a clock irrespective of what the corresponding Pn bit in the PCHIB register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCHIB, SCGCHIB and DCGCHIB registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCHIB register. In this case, when the Pn bit is clear the module is
not powered and does not receive a clock. If the Pn bit is set, the module is powered but does not
receive a clock. The table below details the differences.

Table 5-21. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Hibernation Power Control (PCHIB)

Base 0x400F.E000
Offset 0x914
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

0 P0 RW 1 Hibernation Module Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCHIB, SCGCHIB or DCGCHIB register is clear.

Value Description
0 The HIB module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The HIB module is powered, but does not receive a clock. In
this case, the module is inactive.

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Register 150: Universal Asynchronous Receiver/Transmitter Power Control

(PCUART), offset 0x918
Important: The UART module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCUART register controls the power applied to the UART module. The function of this bit
depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the
corresponding bits in the RCGCUART, SCGCUART and DCGCUART registers. If the Rn, Sn, or
Dn bit of the respective RCGCUART, SCGCUART and DCGCUART registers is 1 and the device
is in that mode, the module is powered and receives a clock irrespective of what the corresponding
Pn bit in the PCUART register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCUART, SCGCUART and DCGCUART
registers is 0 and the device is in that mode, then the module behaves differently depending on the
value of the corresponding Pn bit in the PCUART register. In this case, when the Pn bit is clear the
module is not powered and does not receive a clock. If the Pn bit is set, the module is powered but
does not receive a clock. The table below details the differences.

Table 5-22. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Universal Asynchronous Receiver/Transmitter Power Control (PCUART)

Base 0x400F.E000
Offset 0x918
Type RW, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P7 P6 P5 P4 P3 P2 P1 P0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

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Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 P7 RW 1 UART Module 7 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCUART, SCGCUART or DCGCUART register is clear.

Value Description
0 The UART module 7 is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The UART module 7 is powered, but does not receive a clock.
In this case, the module is inactive.

6 P6 RW 1 UART Module 6 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCUART, SCGCUART or DCGCUART register is clear.

Value Description
0 The UART module 6 is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The UART module 6 is powered, but does not receive a clock.
In this case, the module is inactive.

5 P5 RW 1 UART Module 5 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCUART, SCGCUART or DCGCUART register is clear.

Value Description
0 The UART module 5 is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The UART module 5 is powered, but does not receive a clock.
In this case, the module is inactive.

4 P4 RW 1 UART Module 4 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCUART, SCGCUART or DCGCUART register is clear.

Value Description
0 The UART module 4 is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The UART module 4 is powered, but does not receive a clock.
In this case, the module is inactive.

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Bit/Field Name Type Reset Description

3 P3 RW 1 UART Module 3 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCUART, SCGCUART or DCGCUART register is clear.

Value Description
0 The UART module 3 is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The UART module 3 is powered, but does not receive a clock.
In this case, the module is inactive.

2 P2 RW 1 UART Module 2 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCUART, SCGCUART or DCGCUART register is clear.

Value Description
0 The UART module 2 is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The UART module 2 is powered, but does not receive a clock.
In this case, the module is inactive.

1 P1 RW 1 UART Module 1 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCUART, SCGCUART or DCGCUART register is clear.

Value Description
0 The UART module 1 is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The UART module 1 is powered, but does not receive a clock.
In this case, the module is inactive.

0 P0 RW 1 UART Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCUART, SCGCUART or DCGCUART register is clear.

Value Description
0 The UART module 0 is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The UART module 0 is powered, but does not receive a clock.
In this case, the module is inactive.

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Register 151: Synchronous Serial Interface Power Control (PCSSI), offset

0x91C
Important: The SSI module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCSSI register controls the power applied to the SSI module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCSSI, SCGCSSI and DCGCSSI registers. If the Rn, Sn, or Dn bit of the respective
RCGCSSI, SCGCSSI and DCGCSSI registers is 1 and the device is in that mode, the module is
powered and receives a clock irrespective of what the corresponding Pn bit in the PCSSI register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCSSI, SCGCSSI and DCGCSSI registers is
0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCSSI register. In this case, when the Pn bit is clear the module is
not powered and does not receive a clock. If the Pn bit is set, the module is powered but does not
receive a clock. The table below details the differences.

Table 5-23. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Synchronous Serial Interface Power Control (PCSSI)

Base 0x400F.E000
Offset 0x91C
Type RW, reset 0x0000.000F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P3 P2 P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

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Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 P3 RW 1 SSI Module 3 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCSSI, SCGCSSI or DCGCSSI register is clear.

Value Description
0 The SSI module 3 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The SSI module 3 is powered, but does not receive a clock. In
this case, the module is inactive.

2 P2 RW 1 SSI Module 2 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCSSI, SCGCSSI or DCGCSSI register is clear.

Value Description
0 The SSI module 2 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The SSI module 2 is powered, but does not receive a clock. In
this case, the module is inactive.

1 P1 RW 1 SSI Module 1 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCSSI, SCGCSSI or DCGCSSI register is clear.

Value Description
0 The SSI module 1 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The SSI module 1 is powered, but does not receive a clock. In
this case, the module is inactive.

0 P0 RW 1 SSI Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCSSI, SCGCSSI or DCGCSSI register is clear.

Value Description
0 The SSI module 0 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The SSI module 0 is powered, but does not receive a clock. In
this case, the module is inactive.

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Register 152: Inter-Integrated Circuit Power Control (PCI2C), offset 0x920

Important: The I2C module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCI2C register controls the power applied to the I2C module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCI2C, SCGCI2C and DCGCI2C registers. If the Rn, Sn, or Dn bit of the respective
RCGCI2C, SCGCI2C and DCGCI2C registers is 1 and the device is in that mode, the module is
powered and receives a clock irrespective of what the corresponding Pn bit in the PCI2C register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCI2C, SCGCI2C and DCGCI2C registers is
0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCI2C register. In this case, when the Pn bit is clear the module is
not powered and does not receive a clock. If the Pn bit is set, the module is powered but does not
receive a clock. The table below details the differences.

Table 5-24. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Inter-Integrated Circuit Power Control (PCI2C)

Base 0x400F.E000
Offset 0x920
Type RW, reset 0x0000.03FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

Type RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

9 P9 RW 1 I2C Module 9 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 9 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 9 is powered, but does not receive a clock. In
this case, the module is inactive.

8 P8 RW 1 I2C Module 8 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 8 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 8 is powered, but does not receive a clock. In
this case, the module is inactive.

7 P7 RW 1 I2C Module 7 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 7 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 7 is powered, but does not receive a clock. In
this case, the module is inactive.

6 P6 RW 1 I2C Module 6 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 6 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 6 is powered, but does not receive a clock. In
this case, the module is inactive.

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Bit/Field Name Type Reset Description

5 P5 RW 1 I2C Module 5 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 5 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 5 is powered, but does not receive a clock. In
this case, the module is inactive.

4 P4 RW 1 I2C Module 4 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 4 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 4 is powered, but does not receive a clock. In
this case, the module is inactive.

3 P3 RW 1 I2C Module 3 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 3 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 3 is powered, but does not receive a clock. In
this case, the module is inactive.

2 P2 RW 1 I2C Module 2 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 2 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 2 is powered, but does not receive a clock. In
this case, the module is inactive.

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Bit/Field Name Type Reset Description

1 P1 RW 1 I2C Module 1 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 1 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 1 is powered, but does not receive a clock. In
this case, the module is inactive.

0 P0 RW 1 I2C Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCI2C, SCGCI2C or DCGCI2C register is clear.

Value Description
0 The I2C module 0 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The I2C module 0 is powered, but does not receive a clock. In
this case, the module is inactive.

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 System Control

Register 153: Universal Serial Bus Power Control (PCUSB), offset 0x928
The PCUSB register controls the power applied to the USB module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCUSB, SCGCUSB and DCGCUSB registers. If the Rn, Sn, or Dn bit of the respective
RCGCUSB, SCGCUSB and DCGCUSB registers is 1 and the device is in that mode, the module
is powered and receives a clock irrespective of what the corresponding Pn bit in the PCUSB register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCUSB, SCGCUSB and DCGCUSB registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCUSB register. In this case, when the Pn bit is clear the module
is not powered and does not receive a clock. If the Pn bit is set, the module is powered but does
not receive a clock. The table below details the differences.

Table 5-25. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Universal Serial Bus Power Control (PCUSB)

Base 0x400F.E000
Offset 0x928
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

0 P0 RW 1 USB Module Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCUSB, SCGCUSB or DCGCUSB register is clear.

Value Description
0 The USB module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The USB module is powered, but does not receive a clock. In
this case, the module is inactive.

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 System Control

Register 154: Ethernet PHY Power Control (PCEPHY), offset 0x930

The PCEPHY register controls the power applied to the EEPROM module. The function of this bit
depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the
corresponding bits in the RCGCEPHY, SCGCEPHY and DCGCEPHY registers. If the Rn, Sn, or
Dn bit of the respective RCGCEPHY, SCGCEPHY and DCGCEPHY registers is 1 and the device
is in that mode, the module is powered and receives a clock irrespective of what the corresponding
Pn bit in the PCEPHY register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCEPHY, SCGCEPHY and DCGCEPHY
registers is 0 and the device is in that mode, then the module behaves differently depending on the
value of the corresponding Pn bit in the PCEPHY register. In this case, when the Pn bit is clear the
module is not powered and does not receive a clock. If the Pn bit is set, the module is powered but
does not receive a clock. The table below details the differences.

Table 5-26. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Note: The Ethernet PHY module is not powered up at reset to prevent an automatic negotiation
on power-up. To properly initialize the PHY, first inhibit the PHY from running on power up
by setting the PHYHOLD bit in the Ethernet Peripheral Configuration (EMACPC) register
and then set the P0 bit in the PCEPHY register. Once it is determined that the PHY is ready
(by polling the R0 bit in the Peripheral Ready (PREPHY) register), the PHY can be
programmed with its appropriate values.
Note: If the MOSC is chosen as the clock to the Ethernet PHY then software has to enable the
MOSC before enabling the Ethernet PHY by setting the P0 bit in the PCEPHY.

Ethernet PHY Power Control (PCEPHY)

Base 0x400F.E000
Offset 0x930
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RW 0 Ethernet PHY Module Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCEPHY, SCGCEPHY or DCGCEPHY register is clear.

Value Description
0 The EPHY module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The EPHY module is powered, but does not receive a clock. In
this case, the module is inactive.

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 System Control

Register 155: Controller Area Network Power Control (PCCAN), offset 0x934
The PCCAN register controls the power applied to the CAN module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCCAN, SCGCCAN and DCGCCAN registers. If the Rn, Sn, or Dn bit of the respective
RCGCCAN, SCGCCAN and DCGCCAN registers is 1 and the device is in that mode, the module
is powered and receives a clock irrespective of what the corresponding Pn bit in the PCCAN register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCCAN, SCGCCAN and DCGCCAN registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCCAN register. In this case, when the Pn bit is clear the module
is not powered and does not receive a clock. If the Pn bit is set, the module is powered but does
not receive a clock. The table below details the differences.

Table 5-27. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Controller Area Network Power Control (PCCAN)

Base 0x400F.E000
Offset 0x934
Type RW, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

1 P1 RW 1 CAN Module 1 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCCAN, SCGCCAN or DCGCCAN register is clear.

Value Description
0 The CAN module 1 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The CAN module 1 is powered, but does not receive a clock.
In this case, the module is inactive.

0 P0 RW 1 CAN Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCCAN, SCGCCAN or DCGCCAN register is clear.

Value Description
0 The CAN module 0 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The CAN module 0 is powered, but does not receive a clock.
In this case, the module is inactive.

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 System Control

Register 156: Analog-to-Digital Converter Power Control (PCADC), offset

0x938
Important: The ADC module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCADC register controls the power applied to the ADC module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCADC, SCGCADC and DCGCADC registers. If the Rn, Sn, or Dn bit of the respective
RCGCADC, SCGCADC and DCGCADC registers is 1 and the device is in that mode, the module
is powered and receives a clock irrespective of what the corresponding Pn bit in the PCADC register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCADC, SCGCADC and DCGCADC registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCADC register. In this case, when the Pn bit is clear the module
is not powered and does not receive a clock. If the Pn bit is set, the module is powered but does
not receive a clock. The table below details the differences.

Table 5-28. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Analog-to-Digital Converter Power Control (PCADC)

Base 0x400F.E000
Offset 0x938
Type RW, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P1 P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

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Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 P1 RW 1 ADC Module 1 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCADC, SCGCADC or DCGCADC register is clear.

Value Description
0 The ADC module 1 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The ADC module 1 is powered, but does not receive a clock.
In this case, the module is inactive.

0 P0 RW 1 ADC Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCADC, SCGCADC or DCGCADC register is clear.

Value Description
0 The ADC module 0 is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The ADC module 0 is powered, but does not receive a clock.
In this case, the module is inactive.

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 System Control

Register 157: Analog Comparator Power Control (PCACMP), offset 0x93C

Important: The ACMP module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCACMP register controls the power applied to the ACMP module. The function of this bit
depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the
corresponding bits in the RCGCACMP, SCGCACMP and DCGCACMP registers. If the Rn, Sn, or
Dn bit of the respective RCGCACMP, SCGCACMP and DCGCACMP registers is 1 and the device
is in that mode, the module is powered and receives a clock irrespective of what the corresponding
Pn bit in the PCACMP register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCACMP, SCGCACMP and DCGCACMP
registers is 0 and the device is in that mode, then the module behaves differently depending on the
value of the corresponding Pn bit in the PCACMP register. In this case, when the Pn bit is clear the
module is not powered and does not receive a clock. If the Pn bit is set, the module is powered but
does not receive a clock. The table below details the differences.

Table 5-29. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Analog Comparator Power Control (PCACMP)

Base 0x400F.E000
Offset 0x93C
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

0 P0 RW 1 Analog Comparator Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCACMP, SCGCACMP or DCGCACMP register is clear.

Value Description
0 The Analog Comparator module is not powered and does not
receive a clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The Analog Comparator module is powered, but does not
receive a clock. In this case, the module is inactive.

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 System Control

Register 158: Pulse Width Modulator Power Control (PCPWM), offset 0x940
Important: The PWM module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCPWM register controls the power applied to the PWM module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCPWM, SCGCPWM and DCGCPWM registers. If the Rn, Sn, or Dn bit of the
respective RCGCPWM, SCGCPWM and DCGCPWM registers is 1 and the device is in that mode,
the module is powered and receives a clock irrespective of what the corresponding Pn bit in the
PCPWM register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCPWM, SCGCPWM and DCGCPWM registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCPWM register. In this case, when the Pn bit is clear the module
is not powered and does not receive a clock. If the Pn bit is set, the module is powered but does
not receive a clock. The table below details the differences.

Table 5-30. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Pulse Width Modulator Power Control (PCPWM)

Base 0x400F.E000
Offset 0x940
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

0 P0 RW 1 PWM Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCPWM, SCGCPWM or DCGCPWM register is clear.

Value Description
0 The PWM module 0 is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The PWM module 0 is powered, but does not receive a clock.
In this case, the module is inactive.

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 System Control

Register 159: Quadrature Encoder Interface Power Control (PCQEI), offset

0x944
Important: The QEI module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.

The PCQEI register controls the power applied to the QEI module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCQEI, SCGCQEI and DCGCQEI registers. If the Rn, Sn, or Dn bit of the respective
RCGCQEI, SCGCQEI and DCGCQEI registers is 1 and the device is in that mode, the module is
powered and receives a clock irrespective of what the corresponding Pn bit in the PCQEI register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCQEI, SCGCQEI and DCGCQEI registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCQEI register. In this case, when the Pn bit is clear the module is
not powered and does not receive a clock. If the Pn bit is set, the module is powered but does not
receive a clock. The table below details the differences.

Table 5-31. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Quadrature Encoder Interface Power Control (PCQEI)

Base 0x400F.E000
Offset 0x944
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

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Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 P0 RW 1 QEI Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCQEI, SCGCQEI or DCGCQEI register is clear.

Value Description
0 QEI module 0 is not powered and does not receive a clock. In
this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 QEI module 0 is powered, but does not receive a clock. In this
case, the module is inactive.

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 System Control

Register 160: EEPROM Power Control (PCEEPROM), offset 0x958

Important: The EEPROM module does not currently provide the ability to respond to the power
down request. Setting a bit in this register has no effect on power consumption. This
register is defined for future software compatibility.

The PCEEPROM register controls the power applied to the EEPROM module. The function of this
bit depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the
corresponding bits in the RCGCEEPROM, SCGCEEPROM and DCGCEEPROM registers. If the
Rn, Sn, or Dn bit of the respective RCGCEEPROM, SCGCEEPROM and DCGCEEPROM registers
is 1 and the device is in that mode, the module is powered and receives a clock irrespective of what
the corresponding Pn bit in the PCEEPROM register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCEEPROM, SCGCEEPROM and
DCGCEEPROM registers is 0 and the device is in that mode, then the module behaves differently
depending on the value of the corresponding Pn bit in the PCEEPROM register. In this case, when
the Pn bit is clear the module is not powered and does not receive a clock. If the Pn bit is set, the
module is powered but does not receive a clock. The table below details the differences.

Table 5-32. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

EEPROM Power Control (PCEEPROM)

Base 0x400F.E000
Offset 0x958
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

0 P0 RW 1 EEPROM Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCEEPROM, SCGCEEPROM or DCGCEEPROM register is clear.

Value Description
0 The EEPROM module is not powered and does not receive a
clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The EEPROM module is powered, but does not receive a clock.
In this case, the module is inactive.

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Register 161: CRC Module Power Control (PCCCM), offset 0x974

The PCCCM register controls the power applied to the CRC module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCCCM, SCGCCCM and DCGCCCM registers. If the Rn, Sn, or Dn bit of the respective
RCGCCCM, SCGCCCM and DCGCCCM registers is 1 and the device is in that mode, the module
is powered and receives a clock irrespective of what the corresponding Pn bit in the PCCCM register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCCCM, SCGCCCM and DCGCCCM registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCCCM register. In this case, when the Pn bit is clear the module
is not powered and does not receive a clock. If the Pn bit is set, the module is powered but does
not receive a clock. The table below details the differences.

Table 5-33. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

CRC Module Power Control (PCCCM)

Base 0x400F.E000
Offset 0x974
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

0 P0 RW 1 CRC Module Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCCCM, SCGCCCM or DCGCCCM register is clear.

Value Description
0 The CRC module is not powered and does not receive a clock.
In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 The CRC module is powered, but does not receive a clock. In
this case, the module is inactive.

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Register 162: Ethernet MAC Power Control (PCEMAC), offset 0x99C

The PCEMAC register controls the power applied to the EMAC module. The function of this bit
depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the
corresponding bits in the RCGCEMAC, SCGCEMAC and DCGCEMAC registers. If the Rn, Sn, or
Dn bit of the respective RCGCEMAC, SCGCEMAC and DCGCEMAC registers is 1 and the device
is in that mode, the module is powered and receives a clock irrespective of what the corresponding
Pn bit in the PCEMAC register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCEMAC, SCGCEMAC and DCGCEMAC
registers is 0 and the device is in that mode, then the module behaves differently depending on the
value of the corresponding Pn bit in the PCEMAC register. In this case, when the Pn bit is clear the
module is not powered and does not receive a clock. If the Pn bit is set, the module is powered but
does not receive a clock. The table below details the differences.

Table 5-34. Module Power Control

Rn, Sn or Dn Value in Pn Description
Respective RCGCx,
SCGCx, or DCGCx
Register
0 0 Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
0 1 Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
1 X Module is powered and receives a clock.

Ethernet MAC Power Control (PCEMAC)

Base 0x400F.E000
Offset 0x99C
Type RW, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved P0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

0 P0 RW 1 Ethernet MAC Module 0 Power Control

The Pn bit encodings are not applicable if the corresponding bit in the
RCGCEMAC, SCGCEMAC or DCGCEMAC register is clear.

Value Description
0 Ethernet MAC Module 0 is not powered and does not receive
a clock. In this case, the module's state is not retained.
This configuration provides the lowest power consumption state.
1 Ethernet MAC module 0 is powered, but does not receive a
clock. In this case, the module is inactive.

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Register 163: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00

The PRWD register indicates whether the watchdog modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCWD bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCWD bit is changed. A reset change is initiated if the corresponding SRWD bit
is changed from 0 to 1.
The PRWD bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Watchdog Timer Peripheral Ready (PRWD)

Base 0x400F.E000
Offset 0xA00
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 R1 RO 0 Watchdog Timer 1 Peripheral Ready

Value Description
0 Watchdog module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 Watchdog module 1 is ready for access.

0 R0 RO 0 Watchdog Timer 0 Peripheral Ready

Value Description
0 Watchdog module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 Watchdog module 0 is ready for access.

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Register 164: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER),

offset 0xA04
The PRGPT32 register indicates whether the timer modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCGPT32 bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCGPT32 bit is changed. A reset change is initiated if the corresponding
SRGPT32 bit is changed from 0 to 1.
The PRGPT32 bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER)

Base 0x400F.E000
Offset 0xA04
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 R7 RO 0 16/32-Bit General-Purpose Timer 7 Peripheral Ready

Value Description
0 16/32-bit timer module 7 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 16/32-bit timer module 7 is ready for access.

6 R6 RO 0 16/32-Bit General-Purpose Timer 6 Peripheral Ready

Value Description
0 16/32-bit timer module 6 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 16/32-bit timer module 6 is ready for access.

5 R5 RO 0 16/32-Bit General-Purpose Timer 5 Peripheral Ready

Value Description
0 16/32-bit timer module 5 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 16/32-bit timer module 5 is ready for access.

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Bit/Field Name Type Reset Description

4 R4 RO 0 16/32-Bit General-Purpose Timer 4 Peripheral Ready

Value Description
0 16/32-bit timer module 4 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 16/32-bit timer module 4 is ready for access.

3 R3 RO 0 16/32-Bit General-Purpose Timer 3 Peripheral Ready

Value Description
0 16/32-bit timer module 3 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 16/32-bit timer module 3 is ready for access.

2 R2 RO 0 16/32-Bit General-Purpose Timer 2 Peripheral Ready

Value Description
0 16/32-bit timer module 2 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 16/32-bit timer module 2 is ready for access.

1 R1 RO 0 16/32-Bit General-Purpose Timer 1 Peripheral Ready

Value Description
0 16/32-bit timer module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 16/32-bit timer module 1 is ready for access.

0 R0 RO 0 16/32-Bit General-Purpose Timer 0 Peripheral Ready

Value Description
0 16/32-bit timer module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 16/32-bit timer module 0 is ready for access.

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Register 165: General-Purpose Input/Output Peripheral Ready (PRGPIO),

offset 0xA08
The PRGPIO register indicates whether the GPIO modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCGPIO bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCGPIO bit is changed. A reset change is initiated if the corresponding
SRGPIO bit is changed from 0 to 1.
The PRGPIO bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

General-Purpose Input/Output Peripheral Ready (PRGPIO)

Base 0x400F.E000
Offset 0xA08
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 R14 RO 0 GPIO Port Q Peripheral Ready

Value Description
0 GPIO Port Q is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port Q is ready for access.

13 R13 RO 0 GPIO Port P Peripheral Ready

Value Description
0 GPIO Port P is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port P is ready for access.

12 R12 RO 0 GPIO Port N Peripheral Ready

Value Description
0 GPIO Port N is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port N is ready for access.

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Bit/Field Name Type Reset Description

11 R11 RO 0 GPIO Port M Peripheral Ready

Value Description
0 GPIO Port M is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port M is ready for access.

10 R10 RO 0 GPIO Port L Peripheral Ready

Value Description
0 GPIO Port L is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port L is ready for access.

9 R9 RO 0 GPIO Port K Peripheral Ready

Value Description
0 GPIO Port K is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port K is ready for access.

8 R8 RO 0 GPIO Port J Peripheral Ready

Value Description
0 GPIO Port J is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port J is ready for access.

7 R7 RO 0 GPIO Port H Peripheral Ready

Value Description
0 GPIO Port H is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port H is ready for access.

6 R6 RO 0 GPIO Port G Peripheral Ready

Value Description
0 GPIO Port G is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port G is ready for access.

5 R5 RO 0 GPIO Port F Peripheral Ready

Value Description
0 GPIO Port F is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port F is ready for access.

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Bit/Field Name Type Reset Description

4 R4 RO 0 GPIO Port E Peripheral Ready

Value Description
0 GPIO Port E is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port E is ready for access.

3 R3 RO 0 GPIO Port D Peripheral Ready

Value Description
0 GPIO Port D is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port D is ready for access.

2 R2 RO 0 GPIO Port C Peripheral Ready

Value Description
0 GPIO Port C is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port C is ready for access.

1 R1 RO 0 GPIO Port B Peripheral Ready

Value Description
0 GPIO Port B is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port B is ready for access.

0 R0 RO 0 GPIO Port A Peripheral Ready

Value Description
0 GPIO Port A is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 GPIO Port A is ready for access.

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Register 166: Micro Direct Memory Access Peripheral Ready (PRDMA), offset
0xA0C
The PRDMA register indicates whether the μDMA module is ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCDMA bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCDMA bit is changed. A reset change is initiated if the corresponding SRDMA
bit is changed from 0 to 1.
The PRDMA bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Micro Direct Memory Access Peripheral Ready (PRDMA)

Base 0x400F.E000
Offset 0xA0C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 μDMA Module Peripheral Ready

Value Description
0 The μDMA module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 The μDMA module is ready for access.

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Register 167: EPI Peripheral Ready (PREPI), offset 0xA10

The PREPI register indicates whether the EPI module is ready to be accessed by software following
a change in status of power, Run mode clocking, or reset. A power change is initiated if the
corresponding PCEPI bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCEPI bit is changed. A reset change is initiated if the corresponding SREPI bit
is changed from 0 to 1.
The PREPI bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

EPI Peripheral Ready (PREPI)

Base 0x400F.E000
Offset 0xA10
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 EPI Module Peripheral Ready

Value Description
0 The EPI module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 The EPI module is ready for access.

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Register 168: Hibernation Peripheral Ready (PRHIB), offset 0xA14

The PRHIB register indicates whether the Hibernation module is ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCHIB bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCHIB bit is changed. A reset change is initiated if the corresponding SRHIB bit
is changed from 0 to 1.
The PRHIB bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Hibernation Peripheral Ready (PRHIB)

Base 0x400F.E000
Offset 0xA14
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 1 Hibernation Module Peripheral Ready

Value Description
0 The Hibernation module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 The Hibernation module is ready for access.

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Register 169: Universal Asynchronous Receiver/Transmitter Peripheral Ready

(PRUART), offset 0xA18
The PRUART register indicates whether the UART modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCUART bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCUART bit is changed. A reset change is initiated if the corresponding
SRUART bit is changed from 0 to 1.
The PRUART bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART)

Base 0x400F.E000
Offset 0xA18
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 R7 RO 0 UART Module 7 Peripheral Ready

Value Description
0 UART module 7 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 UART module 7 is ready for access.

6 R6 RO 0 UART Module 6 Peripheral Ready

Value Description
0 UART module 6 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 UART module 6 is ready for access.

5 R5 RO 0 UART Module 5 Peripheral Ready

Value Description
0 UART module 5 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 UART module 5 is ready for access.

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Bit/Field Name Type Reset Description

4 R4 RO 0 UART Module 4 Peripheral Ready

Value Description
0 UART module 4 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 UART module 4 is ready for access.

3 R3 RO 0 UART Module 3 Peripheral Ready

Value Description
0 UART module 3 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 UART module 3 is ready for access.

2 R2 RO 0 UART Module 2 Peripheral Ready

Value Description
0 UART module 2 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 UART module 2 is ready for access.

1 R1 RO 0 UART Module 1 Peripheral Ready

Value Description
0 UART module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 UART module 1 is ready for access.

0 R0 RO 0 UART Module 0 Peripheral Ready

Value Description
0 UART module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 UART module 0 is ready for access.

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Register 170: Synchronous Serial Interface Peripheral Ready (PRSSI), offset

0xA1C
The PRSSI register indicates whether the SSI modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCSSI bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCSSI bit is changed. A reset change is initiated if the corresponding SRSSI bit
is changed from 0 to 1.
The PRSSI bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Synchronous Serial Interface Peripheral Ready (PRSSI)

Base 0x400F.E000
Offset 0xA1C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 R3 RO 0 SSI Module 3 Peripheral Ready

Value Description
0 SSI module 3 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 SSI module 3 is ready for access.

2 R2 RO 0 SSI Module 2 Peripheral Ready

Value Description
0 SSI module 2 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 SSI module 2 is ready for access.

1 R1 RO 0 SSI Module 1 Peripheral Ready

Value Description
0 SSI module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 SSI module 1 is ready for access.

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Bit/Field Name Type Reset Description

0 R0 RO 0 SSI Module 0 Peripheral Ready

Value Description
0 SSI module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 SSI module 0 is ready for access.

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Register 171: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20

The PRI2C register indicates whether the I2C modules are ready to be accessed by software following
a change in status of power, Run mode clocking, or reset. A power change is initiated if the
corresponding PCI2C bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCI2C bit is changed. A reset change is initiated if the corresponding SRI2C bit
is changed from 0 to 1.
The PRI2C bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Inter-Integrated Circuit Peripheral Ready (PRI2C)

Base 0x400F.E000
Offset 0xA20
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 R9 RO 0 I2C Module 9 Peripheral Ready

Value Description
0 I2C module 9 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 9 is ready for access.

8 R8 RO 0 I2C Module 8 Peripheral Ready

Value Description
0 I2C module 8 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 8 is ready for access.

7 R7 RO 0 I2C Module 7 Peripheral Ready

Value Description
0 I2C module 7 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 7 is ready for access.

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Bit/Field Name Type Reset Description

6 R6 RO 0 I2C Module 6 Peripheral Ready

Value Description
0 I2C module 6 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 6 is ready for access.

5 R5 RO 0 I2C Module 5 Peripheral Ready

Value Description
0 I2C module 5 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 5 is ready for access.

4 R4 RO 0 I2C Module 4 Peripheral Ready

Value Description
0 I2C module 4 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 4 is ready for access.

3 R3 RO 0 I2C Module 3 Peripheral Ready

Value Description
0 I2C module 3 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 3 is ready for access.

2 R2 RO 0 I2C Module 2 Peripheral Ready

Value Description
0 I2C module 2 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 2 is ready for access.

1 R1 RO 0 I2C Module 1 Peripheral Ready

Value Description
0 I2C module 1 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 1 is ready for access.

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Bit/Field Name Type Reset Description

0 R0 RO 0 I2C Module 0 Peripheral Ready

Value Description
0 I2C module 0 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1 I2C module 0 is ready for access.

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Register 172: Universal Serial Bus Peripheral Ready (PRUSB), offset 0xA28
The PRUSB register indicates whether the USB module is ready to be accessed by software following
a change in status of power, Run mode clocking, or reset. A power change is initiated if the
corresponding PCUSB bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCUSB bit is changed. A reset change is initiated if the corresponding SRUSB
bit is changed from 0 to 1.
The PRUSB bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Universal Serial Bus Peripheral Ready (PRUSB)

Base 0x400F.E000
Offset 0xA28
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 USB Module Peripheral Ready

Value Description
0 The USB module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 The USB module is ready for access.

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Register 173: Ethernet PHY Peripheral Ready (PREPHY), offset 0xA30

The PREPHY register indicates whether the Ethernet PHY module is ready to be accessed by
software following a change in status of power, Run mode clocking, or reset. A power change is
initiated if the corresponding PCEPHY bit is changed from 0 to 1. A Run mode clocking change is
initiated if the corresponding RCGCEPHY bit is changed. A reset change is initiated if the
corresponding SREPHY bit is changed from 0 to 1.
The PREPHY bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Ethernet PHY Peripheral Ready (PREPHY)

Base 0x400F.E000
Offset 0xA30
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 Ethernet PHY Module Peripheral Ready

Value Description
0 The Ethernet PHY module is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
1 The Ethernet PHY module is ready for access.

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Register 174: Controller Area Network Peripheral Ready (PRCAN), offset

0xA34
The PRCAN register indicates whether the CAN modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCCAN bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCCAN bit is changed. A reset change is initiated if the corresponding SRCAN
bit is changed from 0 to 1.
The PRCAN bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Controller Area Network Peripheral Ready (PRCAN)

Base 0x400F.E000
Offset 0xA34
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 R1 RO 0 CAN Module 1 Peripheral Ready

Value Description
0 CAN module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 CAN module 1 is ready for access.

0 R0 RO 0 CAN Module 0 Peripheral Ready

Value Description
0 CAN module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 CAN module 0 is ready for access.

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Register 175: Analog-to-Digital Converter Peripheral Ready (PRADC), offset

0xA38
The PRADC register indicates whether the ADC modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCADC bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCADC bit is changed. A reset change is initiated if the corresponding SRADC
bit is changed from 0 to 1.
The PRADC bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Analog-to-Digital Converter Peripheral Ready (PRADC)

Base 0x400F.E000
Offset 0xA38
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R1 R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 R1 RO 0 ADC Module 1 Peripheral Ready

Value Description
0 ADC module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 ADC module 1 is ready for access.

0 R0 RO 0 ADC Module 0 Peripheral Ready

Value Description
0 ADC module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 ADC module 0 is ready for access.

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Register 176: Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C

The PRACMP register indicates whether the analog comparator module is ready to be accessed
by software following a change in status of power, Run mode clocking, or reset. A power change is
initiated if the corresponding PCACMP bit is changed from 0 to 1. A Run mode clocking change is
initiated if the corresponding RCGCACMP bit is changed. A reset change is initiated if the
corresponding SRACMP bit is changed from 0 to 1.
The PRACMP bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Analog Comparator Peripheral Ready (PRACMP)

Base 0x400F.E000
Offset 0xA3C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 Analog Comparator Module 0 Peripheral Ready

Value Description
0 The analog comparator module is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
1 The analog comparator module is ready for access.

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Register 177: Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40
The PRPWM register indicates whether the PWM modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCPWM bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCPWM bit is changed. A reset change is initiated if the corresponding
SRPWM bit is changed from 0 to 1.
The PRPWM bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Pulse Width Modulator Peripheral Ready (PRPWM)

Base 0x400F.E000
Offset 0xA40
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 PWM Module 0 Peripheral Ready

Value Description
0 PWM module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 PWM module 0 is ready for access.

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Register 178: Quadrature Encoder Interface Peripheral Ready (PRQEI), offset

0xA44
The PRQEI register indicates whether the QEI modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCQEI bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCQEI bit is changed. A reset change is initiated if the corresponding SRQEI bit
is changed from 0 to 1.
The PRQEI bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Quadrature Encoder Interface Peripheral Ready (PRQEI)

Base 0x400F.E000
Offset 0xA44
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 QEI Module 0 Peripheral Ready

Value Description
0 QEI module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 QEI module 0 is ready for access.

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Register 179: EEPROM Peripheral Ready (PREEPROM), offset 0xA58

The PREEPROM register indicates whether the EEPROM module is ready to be accessed by
software following a change in status of power, Run mode clocking, or reset. A power change is
initiated if the corresponding PCEEPROM bit is changed from 0 to 1. A Run mode clocking change
is initiated if the corresponding RCGCEEPROM bit is changed. A reset change is initiated if the
corresponding SREEPROM bit is changed from 0 to 1.
The PREEPROM bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

EEPROM Peripheral Ready (PREEPROM)

Base 0x400F.E000
Offset 0xA58
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 EEPROM Module 0 Peripheral Ready

Value Description
0 The EEPROM module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 The EEPROM module is ready for access.

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Register 180: CRC Module Peripheral Ready (PRCCM), offset 0xA74

The PRCCM register indicates whether the CRC is ready to be accessed by software following a
change in status of power, Run mode clocking, or reset. A power change is initiated if the
corresponding PCCCM bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCCCM bit is changed. A reset change is initiated if the corresponding SRCCM
bit is changed from 0 to 1.
The PRCCM bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

CRC Module Peripheral Ready (PRCCM)

Base 0x400F.E000
Offset 0xA74
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 CRC Peripheral Ready

Value Description
0 The CRC module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 The CRC module is ready for access.

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Register 181: Ethernet MAC Peripheral Ready (PREMAC), offset 0xA9C

The PREMAC register indicates whether the Ethernet module is ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCEMAC bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCEMAC bit is changed. A reset change is initiated if the corresponding
SREMAC bit is changed from 0 to 1.
The PREMAC bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.

Ethernet MAC Peripheral Ready (PREMAC)

Base 0x400F.E000
Offset 0xA9C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved R0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 R0 RO 0 Ethernet MAC Module 0 Peripheral Ready

Value Description
0 Ethernet MAC module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 Ethernet MAC module 0 is ready for access.

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Register 182: Unique ID 0 (UNIQUEID0), offset 0xF20

Register 183: Unique ID 1 (UNIQUEID1), offset 0xF24
Register 184: Unique ID 2 (UNIQUEID2), offset 0xF28
Register 185: Unique ID 3 (UNIQUEID3), offset 0xF2C
These registers contain a unique 128-bit identifier that cannot be modified by the user. This value
is unique to each individual die but is not a random value. This unique device identifier can be used
to initiate secure boot processes or as a serial number for USB or other end applications.

Unique ID n (UNIQUEIDn)
Base 0x400F.E000
Offset 0xF20
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ID

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 ID RO - Unique ID
The result of registers 0-3 concatenated defines the unique 128-bit
device identifier.

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6 Processor Support and Exception Module

This module is an AHB peripheral that handles system-level Cortex-M4 FPU exceptions. For functions
with registers mapped into this aperture, if the function is not available on a device, then all writes
to the associated registers are ignored and reads return zeros.

6.1 Functional Description

The System Exception module provides control and status of the system-level interrupts. All the
interrupt events are ORed together before being sent to the interrupt controller, so the System
Exception module can only generate a single interrupt request to the controller at any given time.
Software can service multiple interrupt events in a single interrupt service routine by reading the
System Exception Masked Interrupt Status (SYSEXCMIS) register. The interrupt events that can
trigger a controller-level interrupt are defined in the System Exception Interrupt Mask (SYSEXCIM)
register by setting the corresponding interrupt mask bits. If interrupts are not used, the raw interrupt
status is always visible via the System Exception Raw Interrupt Status (SYSEXCRIS) register.
Interrupts are always cleared (for both the SYSEXCMIS and SYSEXCRIS registers) by writing a 1
to the corresponding bit in the System Exception Interrupt Clear (SYSEXCIC) register.

6.2 Register Map

Table 6-1 on page 523 lists the System Exception module registers. The offset listed is a hexadecimal
increment to the register's address, relative to the System Exception base address of 0x400F.9000.
Note: Spaces in the System Exception register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.

Table 6-1. System Exception Register Map

See
Offset Name Type Reset Description
page

0x000 SYSEXCRIS RO 0x0000.0000 System Exception Raw Interrupt Status 524

0x004 SYSEXCIM RW 0x0000.0000 System Exception Interrupt Mask 526

0x008 SYSEXCMIS RO 0x0000.0000 System Exception Masked Interrupt Status 528

0x00C SYSEXCIC W1C 0x0000.0000 System Exception Interrupt Clear 530

6.3 Register Descriptions

All addresses given are relative to the System Exception base address of 0x400F.9000.

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Register 1: System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000

The SYSEXCRIS register is the raw interrupt status register. On a read, this register gives the
current raw status value of the corresponding interrupt. A write has no effect.

System Exception Raw Interrupt Status (SYSEXCRIS)

Base 0x400F.9000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FPIXCRIS FPOFCRIS FPUFCRIS FPIOCRIS FPDZCRIS FPIDCRIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 FPIXCRIS RO 0 Floating-Point Inexact Exception Raw Interrupt Status

Value Description
0 No interrupt
1 A floating-point inexact exception has occurred.

This bit is cleared by writing a 1 to the IXCIC bit in the SYSEXCIC

register.

4 FPOFCRIS RO 0 Floating-Point Overflow Exception Raw Interrupt Status

Value Description
0 No interrupt
1 A floating-point overflow exception has occurred.

This bit is cleared by writing a 1 to the OFCIC bit in the SYSEXCIC

register.

3 FPUFCRIS RO 0 Floating-Point Underflow Exception Raw Interrupt Status

Value Description
0 No interrupt
1 A floating-point underflow exception has occurred.

This bit is cleared by writing a 1 to the UFCIC bit in the SYSEXCIC

register.

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Bit/Field Name Type Reset Description

2 FPIOCRIS RO 0 Floating-Point Invalid Operation Raw Interrupt Status

Value Description
0 No interrupt
1 A floating-point invalid operation exception has occurred.

This bit is cleared by writing a 1 to the IOCIC bit in the SYSEXCIC

register.

1 FPDZCRIS RO 0 Floating-Point Divide By 0 Exception Raw Interrupt Status

Value Description
0 No interrupt
1 A floating-point divide by 0 exception has occurred.

This bit is cleared by writing a 1 to the DZCIC bit in the SYSEXCIC

register.

0 FPIDCRIS RO 0 Floating-Point Input Denormal Exception Raw Interrupt Status

Value Description
0 No interrupt
1 A floating-point input denormal exception has occurred.

This bit is cleared by writing a 1 to the IDCIC bit in the SYSEXCIC

register.

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Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004

The SYSEXCIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.

System Exception Interrupt Mask (SYSEXCIM)

Base 0x400F.9000
Offset 0x004
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FPIXCIM FPOFCIM FPUFCIM FPIOCIM FPDZCIM FPIDCIM

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RW 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 FPIXCIM RW 0 Floating-Point Inexact Exception Interrupt Mask

Value Description
0 The FPIXCRIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the
FPISCRIS bit in the SYSEXCRIS register is set.

4 FPOFCIM RW 0 Floating-Point Overflow Exception Interrupt Mask

Value Description
0 The FPOFCIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the
FPOFCRIS bit in the SYSEXCRIS register is set.

3 FPUFCIM RW 0 Floating-Point Underflow Exception Interrupt Mask

Value Description
0 The FPUFCRIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the
FPUFCRIS bit in the SYSEXCRIS register is set.

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Bit/Field Name Type Reset Description

2 FPIOCIM RW 0 Floating-Point Invalid Operation Interrupt Mask

Value Description
0 The FPIOCRIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the
FPIOCRIS bit in the SYSEXCRIS register is set.

1 FPDZCIM RW 0 Floating-Point Divide By 0 Exception Interrupt Mask

Value Description
0 The FPDZCRIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the
FPDZCRIS bit in the SYSEXCRIS register is set.

0 FPIDCIM RW 0 Floating-Point Input Denormal Exception Interrupt Mask

Value Description
0 The FPIDCRIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the
FPIDCRIS bit in the SYSEXCRIS register is set.

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Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset

0x008
The SYSEXCMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.

System Exception Masked Interrupt Status (SYSEXCMIS)

Base 0x400F.9000
Offset 0x008
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FPIXCMIS FPOFCMIS FPUFCMIS FPIOCMIS FPDZCMIS FPIDCMIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 FPIXCMIS RO 0 Floating-Point Inexact Exception Masked Interrupt Status

Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an inexact
exception.

This bit is cleared by writing a 1 to the FPIXCIC bit in the SYSEXCIC

register.

4 FPOFCMIS RO 0 Floating-Point Overflow Exception Masked Interrupt Status

Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an overflow
exception.

This bit is cleared by writing a 1 to the FPOFCIC bit in the SYSEXCIC

register.

3 FPUFCMIS RO 0 Floating-Point Underflow Exception Masked Interrupt Status

Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an underflow
exception.

This bit is cleared by writing a 1 to the FPUFCIC bit in the SYSEXCIC

register.

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Bit/Field Name Type Reset Description

2 FPIOCMIS RO 0 Floating-Point Invalid Operation Masked Interrupt Status

Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an invalid operation.

This bit is cleared by writing a 1 to the FPIOCIC bit in the SYSEXCIC

register.

1 FPDZCMIS RO 0 Floating-Point Divide By 0 Exception Masked Interrupt Status

Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a divide by 0
exception.

This bit is cleared by writing a 1 to the FPDZCIC bit in the SYSEXCIC

register.

0 FPIDCMIS RO 0 Floating-Point Input Denormal Exception Masked Interrupt Status

Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an input denormal
exception.

This bit is cleared by writing a 1 to the FPIDCIC bit in the SYSEXCIC

register.

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Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C

The SYSEXCIC register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.

System Exception Interrupt Clear (SYSEXCIC)

Base 0x400F.9000
Offset 0x00C
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FPIXCIC FPOFCIC FPUFCIC FPIOCIC FPDZCIC FPIDCIC

Type W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved W1C 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 FPIXCIC W1C 0 Floating-Point Inexact Exception Interrupt Clear

Writing a 1 to this bit clears the FPIXCRIS bit in the SYSEXCRIS register
and the FPIXCMIS bit in the SYSEXCMIS register.

4 FPOFCIC W1C 0 Floating-Point Overflow Exception Interrupt Clear

Writing a 1 to this bit clears the FPOFCRIS bit in the SYSEXCRIS register
and the FPOFCMIS bit in the SYSEXCMIS register.

3 FPUFCIC W1C 0 Floating-Point Underflow Exception Interrupt Clear

Writing a 1 to this bit clears the FPUFCRIS bit in the SYSEXCRIS register
and the FPUFCMIS bit in the SYSEXCMIS register.

2 FPIOCIC W1C 0 Floating-Point Invalid Operation Interrupt Clear

Writing a 1 to this bit clears the FPIOCRIS bit in the SYSEXCRIS register
and the FPIOCMIS bit in the SYSEXCMIS register.

1 FPDZCIC W1C 0 Floating-Point Divide By 0 Exception Interrupt Clear

Writing a 1 to this bit clears the FPDZCRIS bit in the SYSEXCRIS register
and the FPDZCMIS bit in the SYSEXCMIS register.

0 FPIDCIC W1C 0 Floating-Point Input Denormal Exception Interrupt Clear

Writing a 1 to this bit clears the FPIDCRIS bit in the SYSEXCRIS register
and the FPIDCMIS bit in the SYSEXCMIS register.

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7 Hibernation Module
The Hibernation Module manages removal and restoration of power to provide a means for reducing
system power consumption. When the processor and peripherals are idle, power can be completely
removed with only the Hibernation module remaining powered. Power can be restored based on
an external signal or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation
module can be independently supplied from an external battery or an auxiliary power supply.
The Hibernation also integrates a tamper module which provides mechanisms to detect, respond
to, and log system tampering events. The Tamper module is designed to be low power and operate
from either a battery or the MCU I/O voltage supply.
The Hibernation module has the following features:

■ 32-bit real-time seconds counter (RTC) with 1/32,768 second resolution and a 15-bit sub-seconds
counter

– 32-bit RTC seconds match register and a 15-bit sub seconds match for timed wake-up and
interrupt generation with 1/32,768 second resolution

– RTC predivider trim for making fine adjustments to the clock rate

■ Hardware Calendar Function

– Year, Month, Day, Day of Week, Hours, Minutes, Seconds

– Four-year leap compensation

– 24-hour or AM/PM configuration

■ Two mechanisms for power control

– System power control using discrete external regulator

– On-chip power control using internal switches under register control

■ VDD supplies power when valid, even if VBAT > VDD

■ Dedicated pin for waking using an external signal

■ Capability to configure external reset (RST) pin and/or up to four GPIO port pins as wake source,
with programmable wake level

■ Tamper Functionality

– Support for four tamper inputs

– Configurable level, weak pull-up, and glitch filter

– Configurable tamper event response

– Logging of up to four tamper events

– Optional BBRAM erase on tamper detection

– Tamper wake from hibernate capability

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– Hibernation clock input failure detect with a switch to the internal oscillator on detection

■ RTC operational and hibernation memory valid as long as VDD or VBAT is valid

■ Low-battery detection, signaling, and interrupt generation, with optional wake on low battery

■ GPIO pin state can be retained during hibernation

■ Clock source from an internal low frequency oscillator (HIB LFIOSC) or a 32.768-kHz external
crystal or oscillator

■ Sixteen 32-bit words of battery-backed memory to save state during hibernation

■ Programmable interrupts for:

– RTC match

– External wake

– Low battery

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7.1 Block Diagram

Figure 7-1. Hibernation Module Block Diagram

Alternate Clock Clock Source for

for LPC System Clock To GPIO Module

HIBCTL.CLK32EN
& HIBCTL.OSCSEL

HIBCC. HIBCC. I/O Config.

Low
ALTCLK1EN SYSCLKEN HIBIO
Frequency
Oscillator

XOSC0 32.786 kHz

Oscillator
XOSC1 Pre-Divider Interrupts
HIBRTCT HIBIM
HIBRIS Interrupts
HIBMIS to CPU
HIBCTL.CLK32EN &
HIBCTL.OSCSEL HIBIC
RTC
Battery-Backed HIBRTCC
HIBRTCLD MATCH
Memory
16 words HIBRTCM0
HIBRTCSS RTCCLK
HIBDATA

HIBCTL.RTCEN
WAKE
LOWBAT

Low Battery Power

VBAT Sequence HIB
Detect
Logic

HIBCTL.VBATSEL HIBCTL.RTCWEN
HIBCTL.BATCHK HIBCTL.PINWEN
HIBCTL.VABORT
HIBCTL.HIBREQ
HIBCTL.BATWKEN

Note: References to alternate clock to LPC only apply to devices which have LPC.

7.2 Signal Description

The following table lists the external signals of the Hibernation module and describes the function
of each.
The RTCCLK and TMPR[3:0] signals are alternate functions for a GPIO signal and defaults to be
a GPIO signal at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO
pin placement for the RTCCLK and TMPR[3:0] signals. The number in parentheses is the encoding
that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register
(page 787) to assign each signal to its specified GPIO port pin. In addition, the AFSEL bit in the GPIO
Alternate Function Select (GPIOAFSEL) register (page 770) should be set to choose the proper
HIB function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 742.
The remaining signals have a fixed pin assignment and function.

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Note: In addition to the Hibernation signals that are part of the Hibernation Module, GPIO pins
K[7:4] can be configured as external wake sources. Refer to “Waking from
Hibernate” on page 546 for more information.
Note: Port pins PM[7:4] operate as Fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive
capability. 10- and 12-mA drive are not supported. All standard GPIO register controls,
except for the GPIODR12R register, apply to these port pins. Refer to “General-Purpose
Input/Outputs (GPIOs)” on page 742 and “Recommended GPIO Operating
Characteristics” on page 1820 for more information.

Table 7-1. Hibernate Signals (128TQFP)

Pin Name Pin Number Pin Mux / Pin Pin Type Buffer Type Description
Assignment
HIB 65 fixed O TTL An output that indicates the processor is in
Hibernate mode.
RTCCLK 24 PC5 (7) O TTL Buffered version of the Hibernation module's
60 PK7 (5) 32.768-kHz clock. This signal is not output when
104 PP3 (7) the part is in Hibernate mode and before being
configured after power-on reset.
TMPR0 71 PM7 I/O TTL Tamper signal 0.
TMPR1 72 PM6 I/O TTL Tamper signal 1.
TMPR2 73 PM5 I/O TTL Tamper signal 2.
TMPR3 74 PM4 I/O TTL Tamper signal 3.
VBAT 68 fixed - Power Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
WAKE 64 fixed I TTL An external input that brings the processor out of
Hibernate mode when asserted.
XOSC0 66 fixed I Analog Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a crystal or a 32.768-kHz oscillator for the
Hibernation module RTC.
XOSC1 67 fixed O Analog Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.

7.3 Functional Description

The Hibernation module provides two mechanisms for power control:

■ The first mechanism uses internal switches to control power to the Cortex-M4F as well as to
most analog and digital functions while retaining I/O pin power (VDD3ON mode).

■ The second mechanism controls the power to the microcontroller with a control signal (HIB) that
signals an external voltage regulator to turn on or off.

The Hibernation module power source is supplied by VDD as long as it is within a valid range, even
if VBAT>VDD. The Hibernation module also has an independent clock source to maintain a real-time
clock (RTC) when the system clock is powered down. Hibernate mode can be entered through one
of two ways:

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■ The user initiates hibernation by setting the HIBREQ bit in the Hibernation Control (HIBCTL)
register

■ Power is arbitrarily removed from VDD while a valid VBAT is applied

Once in hibernation, the module signals an external voltage regulator to turn the power back on
when an external pin (WAKE, RST or a wake-enabled GPIO pin) is asserted or when the internal
RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is
low and optionally prevent hibernation or wake from hibernation when the battery voltage falls below
a certain threshold. Note that multiple wake sources can be configured at the same time to generate
a wake signal such that any of them can wake the module.
When waking from hibernation, the HIB signal is deasserted. The return of VDD causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TPOR).

7.3.1 Register Access Timing

Because the Hibernation module has an independent clocking domain, hibernation registers must
be written only with a timing gap between accesses. The delay time is tHIB_REG_ACCESS, therefore
software must guarantee that this delay is inserted between back-to-back writes to Hibernation
registers or between a write followed by a read. The WC interrupt in the HIBMIS register can be used
to notify the application when the Hibernation modules registers can be accessed. Alternatively,
software may make use of the WRC bit in the Hibernation Control (HIBCTL) register to ensure that
the required timing gap has elapsed. This bit is cleared on a write operation and set once the write
completes, indicating to software that another write or read may be started safely. Software should
poll HIBCTL for WRC=1 prior to accessing any hibernation register.
Back-to-back reads from Hibernation module registers have no timing restrictions. Reads are
performed at the full peripheral clock rate.

7.3.2 Hibernation Clock Source

The HIB module can be clocked by one of three different clock sources:

■ A 32.768-kHz oscillator

■ An external 32.768-kHz clock source

■ An internal low frequency oscillator (HIB LFIOSC)

Table 7-2 on page 535 summarizes the encodings for the bits in the HIBCTL register that are required
for each clock source to be enabled. Note that CLK32EN must be set for any Hibernation clock
source to be valid. The Hibernation module is not enabled until the CLK32EN bit is set. The HIB
clock source is the source of the RTC Oscillator (RTCOSC), which can be selected as the system
clock source by programming a 0x4 in the OSCSRC field of the Run and Sleep Mode Configuration
(RSCLKCFG) register in the System Control Module. Please refer to “System Control” on page 220
for more information.

Table 7-2. HIB Clock Source Configurations

HIB Clock Source CLK32EN OSCSEL OSCBYP
32.768 kHz Oscillator 1 0 0
External 32.768-kHz Clock Source 1 0 1

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Table 7-2. HIB Clock Source Configurations (continued)

HIB Clock Source CLK32EN OSCSEL OSCBYP
a
Low-frequency internal oscillator (HIB LFIOSC) 1 1 0
a. The frequency can have wide variations; refer to “Hibernation Clock Source Specifications” on page 1837 for more details.

To use an external crystal, a 32.768-kHz crystal is connected to the XOSC0 and XOSC1 pins.
Alternatively, a 32.768-kHz oscillator can be connected to the XOSC0 pin, leaving XOSC1 unconnected.
Care must be taken that the voltage amplitude of the 32.768-kHz oscillator is less than VBAT,
otherwise, the Hibernation module may draw power from the oscillator and not VBAT during
hibernation. See Figure 7-2 on page 537 and Figure 7-3 on page 537.
Alternatively, a low frequency oscillator source (HIB LFIOSC) present in the Hibernation module
can be a clock source. (The frequency can have wide variations; refer to “Hibernation Clock Source
Specifications” on page 1837 for more details.) The intent of this source is to provide an internal low
power clock source to enable the use of the asynchronous pin wakes and memory storage without
the requirement of an external crystal. To enable the HIB LFIOSC to be the clock source for the
Hibernation module, both the OSCSEL bit and the CLK32EN bit in the Hibernation Control (HIBCTL)
register must be set.
Note: The HIB low-frequency oscillator (HIB LFIOSC) has a wide frequency variation, therefore
the RTC is not accurate when using this clock source. It is not recommended to use the
HIB LFIOSC as an RTC clock source.
The Hibernation module is enabled by setting the CLK32EN bit of the HIBCTL register. The CLK32EN
bit must be set before accessing any other Hibernation module register. The type of clock source
used for the HIB module is selected by setting the OSCSEL and OSCBYP bit of the HIBCTL register.
If the internal low frequency precision oscillator is used as the clock source, the OSCSEL bit should
be set to a 1 at the same time the CLK32EN bit is set. If a crystal is used for the clock source, the
software must leave a delay of tHIBOSC_START after writing to the CLK32EN bit and before any other
accesses to the Hibernation module registers. The delay allows the crystal to power up and stabilize.
If an external oscillator is used for the clock source, no delay is needed. When using an external
clock source, the OSCBYP bit in the HIBCTL register should be set. When using a crystal clock
source, the GNDX pin should be connected to digital ground along with the crystal load capacitors,
as shown in Figure 7-2 on page 537. When using an external clock source, the GNDX pin should be
connected to digital ground.
Note: In the figures below the parameters RBAT and CBAT have recommended values of 51Ω ±5%
and 0.1µF ±5%, respectively. See “Hibernation Module” on page 1845 for more information.

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Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source
Regulator Tiva™ Microcontroller
or Switch
Input
IN OUT VDD
Voltage
EN

XOSC0

X1
XOSC1

C1 C2
GNDX

HIB RBAT
WAKE VBAT
Open drain 3V
GND CBAT
external wake Battery
up circuit RPU

Note: Some devices may not supply the GNDX signal. If GNDX is absent, the crystal load capacitors can
be tied to GND externally. See “Signal Tables” on page 1772 for pins specific to your device.

X1 = Crystal frequency is fXOSC_XTAL.

C1,2 = Capacitor value derived from crystal vendor load capacitance specifications.

RPU = Pull-up resistor is 200 kΩ

RBAT = 51Ω ±5%

CBAT = 0.1µF ±20%

See “Hibernation Clock Source Specifications” on page 1837 for specific parameter values.

Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode

Tiva™ Microcontroller
Regulator
Input
IN OUT VDD
Voltage
Clock
Source XOSC0
(fEXT_OSC)

N.C. XOSC1

GNDX

HIB RBAT
WAKE VBAT

Open drain 3V
GND CBAT
Battery
external wake
RPU
up circuit

Note: Some devices may not supply a GNDX signal. See “Signal Tables” on page 1772 for pins specific to
your device.

RPU = Pull-up resistor is 1 MΩ

RBAT = 51Ω ±5%

CBAT = 0.1µF ±20%

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7.3.2.1 Hibernate Clock Output RTCOSC

The clock source that is configured as the HIB clock has the option of becoming an internal output,
RTCOSC, and being selected as the clock source for the system clock. To enable RTCOSC as a
system clock source, the SYSCLKEN bit must be set in the Hibernate Clock Control (HIBCC)
register.

7.3.3 System Implementation

Several different system configurations are possible when using the Hibernation module:

■ Using a single battery source, where the battery provides both VDD and VBAT, as shown in Figure
7-2 on page 537.

■ Using the VDD3ON mode, where VDD continues to be powered in hibernation, allowing the GPIO
pins to retain their states, as shown in Figure 7-3 on page 537. In this mode, VDDC is powered off
internally. In VDD3ON mode, the RETCLR bit in the HIBCTL register must be set so that after
power is reapplied, GPIO retention is held until software clears the bit. GPIO retention is released
when software writes a 0 to the RETCLR bit.

■ Using separate sources for VDD and VBAT. In this mode, additional circuitry is required for system
start-up without a battery or with a depleted battery.

■ Using a regulator to provide both VDD and VBAT with a switch enabled by HIB to remove VDD
during hibernation as shown in Figure 7-4 on page 538.

Figure 7-4. Using a Regulator for Both VDD and VBAT

Tiva™ Microcontroller
Regulator Switch
Input
IN OUT IN OUT VDD
Voltage
EN

XOSC0

X1
XOSC1

C1 C2
GNDX

HIB

WAKE VBAT
Open drain
GND
external wake
up circuit RPU

Note: Some devices may not supply a GNDX signal. See “Signal Tables” on page 1772 for pins specific to
your device.

Adding external capacitance to the VBAT supply reduces the accuracy of the low-battery measurement
and should be avoided if possible. The diagrams referenced in this section only show the connection
to the Hibernation pins and not to the full system.
If the application does not require the use of the Hibernation module, refer to “Connections for
Unused Signals” on page 1816. In this situation, the HIB bit in the Hibernation Run Mode Clock
Gating Control (RCGCHIB) register must be cleared, disabling the system clock to the Hibernation
module and Hibernation module registers are not accessible.

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7.3.4 Battery Management

Important: System-level factors may affect the accuracy of the low-battery detect circuit. The
designer should consider battery type, discharge characteristics, and a test load during
battery voltage measurements.

The Hibernation module can be independently powered by a battery or an auxiliary power source
using the VBAT pin. The module can monitor the voltage level of the battery and detect when the
voltage drops below VLOWBAT. The voltage threshold can be between 1.9 V and 2.5 V and is
configured using the VBATSEL field in the HIBCTL register. The module can also be configured so
that it does not go into Hibernate mode if the battery voltage drops below this threshold. In addition,
battery voltage is monitored while in hibernation, and the microcontroller can be configured to wake
from hibernation if the battery voltage goes below the threshold using the BATWKEN bit in the HIBCTL
register.
The Hibernation module is designed to detect a low-battery condition and set the LOWBAT bit of the
Hibernation Raw Interrupt Status (HIBRIS) register when this occurs. If the VABORT bit in the
HIBCTL register is also set, then the module is prevented from entering Hibernate mode when a
low-battery is detected. The module can also be configured to generate an interrupt for the low-battery
condition (see “Interrupts and Status” on page 548).

7.3.5 Real-Time Clock

The RTC module is designed to keep wall time. The RTC can operate in seconds counter mode or
calendar mode. A 32.768 kHz clock source along with a 15-bit predivider reduces the clock to 1 Hz.
The 1 Hz clock is used to increment the 32-bit counter and keep track of seconds. In calendar mode,
registers are provided which support the tracking of date, month, year and day-of-week. A match
register can be configured to interrupt or wake the system from hibernate. In addition, a software
trim register is implemented to allow the user to compensate for oscillator inaccuracies using software.

7.3.5.1 RTC Counter - Seconds/Subseconds Mode

The clock signal to the RTC is provided by either of the 32.768-kHz clock sources available to the
Hibernation module. The Hibernation RTC Counter (HIBRTCC) register displays the seconds
value. The Hibernation RTC Sub Seconds register (HIBRTCSS) is provided for additional time
resolution of an application requiring less than one-second divisions.
The RTC is enabled by setting the RTCEN bit of the HIBCTL register. The RTCEN bit is also used
along with the CALEN bit in the Hibernation Calendar Control (HIBCALCTL) register to enable
the calender. Thus, if the calendar is enabled, the RTC registers, HIBRTCC, HIBRTCSS, HIBRTCM0
and HIBRTCLD, cannot be used. The RTC counter and sub-seconds counters begin counting
immediately once RTCEN is set. Both counters count up. The RTC continues counting as long as
the RTC is enabled and a valid VBAT is present, regardless of whether VDD is present or if the device
is in hibernation.
The HIBRTCC register is set by writing the Hibernation RTC Load (HIBRTCLD) register. A write
to the HIBRTCLD register clears the 15-bit sub-seconds counter field, RTCSSC, in the HIBRTCSS
register. To ensure a valid read of the RTC value, the HIBRTCC register should be read first, followed
by a read of the RTCSSC field in the HIBRTCSS register and then a re-read of the HIBRTCC register.
If the two values for the HIBRTCC are equal, the read is valid. By following this procedure, errors
in the application caused by the HIBRTCC register rolling over by a count of 1 during a read of the
RTCSSC field are prevented. The RTC can be configured to generate an alarm by setting the RTCAL0
bit in the HIBIM register. When an RTC match occurs, an interrupt is generated and displayed in
the HIBRIS register. Refer to “RTC Match - Seconds/Subseconds Mode” on page 540 for more
information.

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If the RTC is enabled, only a cold POR, where both VBAT and VDD are removed, resets the RTC
registers. If any other reset occurs while the RTC is enabled, such as an external RST assertion or
BOR reset, the RTC is not reset. The RTC registers can be reset under any type of system reset
as long as the RTC, external wake pins and tamper pins are not enabled.
A buffered version of the 32.768-kHz signal Hibernate clock source is available on the RTCCLK
signal output, which is muxed with a GPIO pin. The RTCCLK signal can be the external 32.786-kHz
clock source or the HIB LFIOSC depending on the value of the OSCSEL bit in the HIBCTL register.
See “Signal Description” on page 533 or pin mux information and “General-Purpose Input/Outputs
(GPIOs)” on page 742 for additional details on initialization and configuration of this signal. The pin
does not output RTCCLK when Hibernate mode is active or before the RTCCLK GPIO digital function
has been selected through the GPIO Digital Enable (GPIODEN) register in the GPIO module. This
includes selecting the RTCCLK signal as an output source in the GPIO Port Control (GPIOPCTL)
register and setting the SYSCLKEN bit within the Hibernate Clock Control (HIBCC) register.
Note: The HIB low-frequency oscillator (HIB LFIOSC) has a wide frequency variation, therefore
the RTC is not accurate when using this clock source. In addition, the RTCCLK signal may
not meet the specification shown in Table 27-30 on page 1845.

7.3.5.2 RTC Match - Seconds/Subseconds Mode

The Hibernation module includes a 32-bit match register, HIBRTCM0, which is compared to the
value of the RTC 32-bit counter, HIBRTCC. The match functionality also extends to the sub-seconds
counter. The 15-bit field (RTCSSM) in the HIBRTCSS register is compared to the value of the 15-bit
sub-seconds counter. When a match occurs, the RTCALT0 bit is set in the HIBRIS register. For
applications using Hibernate mode, the processor can be programmed to wake from Hibernate
mode by setting the RTCWEN bit in the HIBCTL register. The processor can also be programmed to
generate an interrupt to the interrupt controller by setting the RTCALT0 bit in the HIBIM register.
The match interrupt generation takes priority over an interrupt clear. Therefore, writes to the RTCALT0
bit in the Hibernation Interrupt Clear (HIBIC) register do not clear the RTCALT0 bit if the HIBRTCC
value and the HIBRTCM0 value are equal. There are several methodologies to avoid this occurrence,
such as writing a new value to the HIBRTCLD register prior to writing the HIBIC to clear the RTCALT0.
Another example, would be to disable the RTC and re-enable the RTC by clearing and setting the
RTCEN bit in the HIBCTL register.
Note: A Hibernate request made while a match event is valid causes the module to immediately
wake up. This occurs when the RTCWEN bit is set and the RTCALT0 bit in the HIBRIS register
is set at the same time the HIBREQ bit in the HIBCTL register is written to a 1. This can be
avoided by clearing the RTCAL0 bit in the HIBRIS register by writing a 1 to the corresponding
bit in the HIBIC register before setting the HIBREQ bit. Another example would be to disable
the RTC and re-enable the RTC by clearing and setting the RTCEN bit in the HIBCTL register.

7.3.5.3 RTC Calendar

The RTC Calendar function is selected by setting the CALEN bit in the HIB Calendar Control
(HIBCALCTL) register. In this mode, six 32-bit registers provide the read (HIBCAL0/1), match
(HIBCALM0/1), and load (HIBCALLD0/1) interface. The standard RTC registers: HIBRTCC,
HIBRTCLD, HIBRTCSS, and HIBRTCM0 are disabled when the calendar function is enabled and
read back as all 0s in this mode. In addition, writes have no effect on these registers when the
calendar function is enabled.
The Hibernation Calendar n (HIBCALn), Hibernation Calendar Match (HIBCALMn) and
Hibernation Calendar Load (HIBCALLDn) register fields are written or stored in hexadecimal.

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When reading the Hibernation Calendar n (HIBCALn) registers, the status of the VALID bit in the
HIBCAL0/1 register must be checked to ensure the registers are in sync before reading.
The calendar function will keep track of the following:

■ Seconds (0-59 seconds)

■ Minutes (0-59 minutes)

■ Hours (0-23 or 0-11 hours with an AM/PM option)

■ Day of the week (0-6)

■ Day of the month (1-31 days)

■ Month (1-12 months)

■ Year (00-99 years)

The hours may be reported with AM/PM or 24-hour based on the CAL24 bit in the HIBCALCTL
register. The leap year compensation is handled within the calendar function. The number of days
in February are adjusted to 29 whenever the year is divisible by four.

RTC Calendar Match

The HIB Calendar Match function can be used to generate an interrupt on a match of seconds,
minutes, hours, and day of month. The day of the week, year and month are not included in the
match function. To ignore a match function for the hours, minutes, or seconds, set each of the upper
two bits to 1 in the respective fields of the HIBCALMn register. To ignore the day of the month, set
the DOM field to all zeros in the HIBCALM1 register. If a match occurs in any field, the RTCALT0 bit
is set in the HIBRIS register.

7.3.5.4 RTC Trim

The RTC counting rate can be adjusted to compensate for inaccuracies in the clock source by using
the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and is used for
one second out of every 64 seconds in RTC counter mode, when bits [5:0] in the HIBRTCC register
change from 0x00 to 0x01, to divide the input clock. Trim is applied every 60 seconds in calendar
mode. This configuration allows the software to make fine corrections to the clock rate by adjusting
the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from
0x7FFF in order to slow down the RTC rate and down from 0x7FFF in order to speed up the RTC
rate.
Care must be taken when using trim values that are near to the sub seconds match value in the
HIBRTCSS register. It is possible when using trim values above 0x7FFF to receive two match
interrupts for the same counter value. In addition, it is possible when using trim values below 0x7FFF
to miss a match interrupt.
In the case of a trim value above 0x7FFF, when the RTCSSC value in the HIBRTCSS register reaches
0x7FFF, the RTCC value increments from 0x0 to 0x1 while the RTCSSC value is decreased by the
trim amount. The RTCSSC value is counted up again to 0x7FFF before rolling over to 0x0 to begin
counting up again. If the match value is within this range, the match interrupt is triggered twice. For
example, as shown in Figure 7-5 on page 542, if the match interrupt was configured with RTCM0=0x1
and RTCSSM=0x7FFD, two interrupts would be triggered.

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Figure 7-5. Counter Behavior with a TRIM Value of 0x8002

RTCCLK

RTCC[6:0] 0x00 0x01 0x02

RTCSSC 0x7FFD 0x7FFE 0x7FFF 0x7FFD 0x7FFE 0x7FFF 0x0 0x7FFE 0x7FFF 0x0 0x1

In the case of a trim value below 0x7FFF, the RTCSSC value is advanced from 0x7FFF to the trim
value while the RTCC value is incremented from 0x0 to 0x1. If the match value is within that range,
the match interrupt is not triggered. For example, as shown in Figure 7-6 on page 542, if the match
interrupt was configured with RTCM0=0x1 and RTCSSM=0x2,an interrupt would never be triggered.

Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC

RTCCLK

RTCC[6:0] 0x00 0x01

RTCSSC 0x7FFD 0x7FFE 0x7FFF 0x7FFD 0x7FFE 0x7FFF

7.3.6 Tamper
The Tamper module provides a user with mechanisms to detect, respond to, and log system
tampering events. The Tamper module is designed to be low power and operate either from a battery
or the MCU I/O voltage supply. This module is a sub-module of the Hibernate module.

7.3.6.1 Tamper Block Diagram

Figure 7-7 on page 542 shows the Tamper block diagram.

Figure 7-7. Tamper Block Diagram

Tamper Detect Control Tamper Event NMI

and Filter
TMPR[3:0] HIBTPCTL BBRAM Clear
HIBTPIO HIBTPSTAT HIB Wake
HIBTPCTL.TPEN

XOSC Fail Tamper Log

XOSC0
Detector
HIBTPLOG
HIBTPCTL.TPEN

RTC

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7.3.6.2 Functional Description

The Tamper module provides mechanisms to detect, respond, and log system tamper events. A
tamper event is detected by state transitions on up to four GPIOs. The module may respond to a
tamper event by clearing all or part of the hibernate module memory, generating a tamper event
signal to the System Control module. The event will also be logged with a RTC time stamp to allow
for tamper investigation.

Tamper Detection
Qualified tamper events are detected through an XOSCn pin failure or through tamper I/O level
matches which pass through a glitch filter. Tamper I/O pad events are detected by comparing the
level on a tamper I/O pad with an expected value. The tamper I/O is sampled using the hibernate
clock source and when the glitch filtering is enabled, must be stable for about 100 ms. This provides
debounce filtering of a breakaway switch as a results of a drop impact. The tamper module contains
one long glitch filter and one short glitch filter which uses an OR of the inputs as shown in Figure
7-8 on page 543. This implies if two Tamper inputs are asserted and one deasserts, the glitch filter
runs to timeout or until the second Tamper input is deasserted. The glitch filter or tamper logging
logic does not re-trigger if the tamper event match continues. The glitch filter resets on the deassertion
of the tamper conditions or when a qualified tamper event is logged.
If the XOSCn pins are enabled for use with the Hibernation module and subsequently fail, a tamper
event is detected and is indicated by the STATE field in the HIB Tamper Status (HIBTPSTAT)
register. In addition, the XOSCST and XOSCFAIL bits can be read for further details on the external
oscillator source state.

Figure 7-8. Tamper Pad with Glitch Filtering

XOSC0

XOSC Fail Detect Logic

TMPR0
Tamper
Input Detect LONG TAMPER
FILTER EVENT

TMPR1
Tamper
SHORT
Input Detect
FILTER

TMPR2
Tamper
Input Detect

TMPR3
Tamper
Input Detect

Tamper Event Responses

There are many responses to a tamper event including clearing some or all of Hibernate memory
and generating a tamper signal to the System Control Module. The descriptions of the possible
event responses follows.

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■ Tamper Register Status

The tamper status is indicated by the STATE bit field of the HIB Tamper Status (HIBTPSTAT)
register. The register bits are reset to 0x0 on cold POR. When the tamper I/O is
enabled/configured, the STATE field shows 0x1. The STATE field is set to 0x2 when a tamper
event is detected. The software may reset the trigger source and the STATE field by writing to
the TPCLR bit in the HIBTPCTL register.

■ System Event Response

When a tamper event is detected, an NMI is generated. The NMI handler is responsible for
performing any other system responses, including a simulate POR. If the tamper event was an
XOSC fail condition, the part switches to the HIB LFIOSC. Once XOSC is stable, the XOSC may
be enabled as the clock source once again.

■ Hibernate Memory Clearing

On a tamper event, software has the option to clear all, the upper half, lower half, or none of the
Hibernate memory. The feature is controlled through the MEMCLR field of the HIBTPCTL register.

■ Wake from Hibernate

A tamper event will assert a wake event to the MCU if the WAKE bit in the HIBTPCTL register is
set.

Tamper Event Logging

Up to four tamper events are stored in HIB Tamper Log n (HIBTPLOGn) registers within the
Hibernate module. When a tamper event occurs the following status is logged:

■ The RTC seconds or calendar values of year, minutes, day of month, hours and seconds in the
HIBTPLOG0/2/4/6 registers
Note: 24-hour mode must be used if RTC calendar mode is enabled. This mode is selected
by setting the CAL24 bit in HIB Calendar Control (HIBCALCTL) register.

■ The tamper status of the TMPRn pins and the XOSCn pins in the HIBTPLOG1/3/5 registers. The
HIBTPLOG7 register captures the OR of all events occurring after the 3rd event is logged in the
HIBTPLOG5 register.

On the assertion of a qualified tamper event (rising edge) on any of the TMPRn pins or an XOSC
failure signal, the current status of all tamper inputs are logged in the HIBTPLOGn register.

Clearing a Tamper Event

After a tamper event, the HIB Tamper Log (HIBTPLOGn) registers and the NMI to the processor
may be cleared by writing a 1 to the TPCLR bit in the HIBTPCTL register. This clear status is reflected
by the STATE bit in the HIBSTPSTAT register changing from 0x2 back to a 0x1. If the source of the
tamper event comes from an XOSC failure, the clearing of a tamper event is delayed while the clock
is switched to LFIOSC. The NMI interrupt handler may access the module immediately, but should
read the HIBTPLOGn registers before issuing a tamper clear in the HIBTPCTL register.
Note: The HIBTPLOG7 register is sticky and is only cleared by a Hibernate module reset.

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Tamper I/O Control

Up to four tamper I/Os are available. These signals are individually enabled and the detection level
can be configured per pin. Enabling the tamper IO will override all settings made in the GPIO module.
Each tamper IO has a weak pull-up.

Tamper Clocking
The Hibernate clock is the clock source for the Tamper module. When an external oscillator is used
and tamper is enabled, the external oscillator is monitored by the Tamper module. If the external
oscillator stops for any reason, the XOSCFAIL bit is set in the HIBTPSTAT register and the Hibernate
clock source is switched to the HIB LFIOSC immediately. When the XOSCST bit in the HIBTPSTAT
register is 0, indicating the external oscillator is active, a 1 can be written to the XOSCFAIL bit to
clear it and re-enable the external 32.768-kHz oscillator.
Note: Because the HIB LFIOSC has a wide frequency variation, it should not be configured as
the HIB clock source when accurate monitoring of the tamper logs are important.

Tamper Resets
The Tamper module uses the resets from the Hibernate module.

Important: The Hibernation module registers are reset under two conditions:

1. Any type of system reset (if the RTCEN and the PINWEN bits in the HIBCTL register
are clear and the TPEN bit in the HIBTPCTL register is clear).

2. A cold POR occurs when both the VDD and VBAT supplies are removed.

Any other reset condition is ignored by the Hibernation module.

7.3.7 Battery-Backed Memory

The Hibernation module contains 16 32-bit words of memory that are powered from the battery or
an auxiliary power supply and therefore retained during hibernation. The processor software can
save state information in this memory prior to hibernation and recover the state upon waking. To
access the upper eight words of memory, the processor must be in privilege mode. Refer to
“Processor Mode and Privilege Levels for Software Execution” on page 84 for more information
about processor privilege mode. The battery-backed memory can be accessed through the HIBDATA
registers. If both VDD and VBAT are removed, the contents of the HIBDATA registers are not retained.

7.3.8 Power Control Using HIB

Important: The Hibernation Module requires special system implementation considerations when
using HIB to control power, as it is intended to power-down all other sections of the
microcontroller. All system signals and power supplies that connect to the chip must
be driven to 0 V or powered down with the same regulator controlled by HIB.

The Hibernation module controls power to the microcontroller through the use of the HIB pin which
is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V to the
microcontroller and other circuits. When the HIB signal is asserted by the Hibernation module, the
external regulator is turned off and no longer powers the microcontroller and any parts of the system
that are powered by the regulator. The Hibernation module remains powered from the VBAT supply
until a Wake event. Power to the microcontroller is restored by deasserting the HIB signal, which
causes the external regulator to turn power back on to the chip.

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7.3.9 Power Control Using VDD3ON Mode

The Hibernation module may also be configured to cut power to all internal modules during Hibernate
mode. While in this state, if VDD3ON is set in the HIBCTL register, all pins are held in the state they
were in prior to entering hibernation. For example, inputs remain inputs; outputs driven high remain
driven high, and so on. There are important procedural and functional items to note when in VDD3ON
mode:

■ JTAG Ports C[0] - C[3] do not retain their state in Hibernate VDD3ON mode.

■ If GPIO pins K[7:4] are not used as a wake source, they should not be left floating. An internal
pull-up resistor may be configured by the application before entering Hibernate mode by
programming the GPIO Pull-Up Select (GPIOPUR) register in the GPIO module.

■ In the VDD3ON mode, the regulator should maintain 3.3 V power to the microcontroller during
Hibernate. GPIO retention is disabled when the RETCLR bit is cleared in the HIBCTL register.

■ When entering hibernation in VDD3ON mode, the supply rails to the Ethernet resistors R1, R2,
R3, R4 found in Figure 20-13 on page 1464 must be switched off.

7.3.10 Initiating Hibernate

Hibernate mode is initiated when the HIBREQ bit of the HIBCTL register is set. If a wake-up condition
has not been configured using the PINWEN or RTCWEN bits in the HIBCTL register, the hibernation
request is ignored. In addition, if the battery voltage is below the threshold voltage defined by the
VBATSEL field in the HIBCTL register, the hibernation request is ignored.

7.3.11 Waking from Hibernate

The Hibernation module can be configured to wake from Hibernate mode if any of the following are
enabled:

■ External WAKE

■ External RST

■ GPIO K[7:4]

■ Tamper TMPR[3:0]

■ Tamper XOSC failure

The Hibernation module can also be configured to wake from hibernate when the following events
occur:

■ RTC match wake event

■ Low Battery wake event

The external WAKE pin is enabled by setting the PINWEN bit in the HIBCTL register. The external
WAKE pin can generate an interrupt by programming the EXTWEN bit in the Hibernation Interrupt
Mask (HIBIM) register.
Note: If an external WAKE signal is asserted, the application is responsible for clearing the signal
source once the EXTWEN bit has been registered in the Hibernation Raw Interrupt Status
(HIBRIS) register.

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To use the RST pin as a wake source, the WURSTEN bit must be set in the Hibernate I/O
Configuration (HIBIO) register and the WUUNLK bit must be set in the same register.
To enable any of the assigned GPIO pins as a wake source, the WUUNLK bit must be set in the
HIBIO register and the wake configuration must be programmed through the GPIOWAKEPEN and
GPIOWAKELVL registers in the GPIO module. Please refer to “General-Purpose Input/Outputs
(GPIOs)” on page 742 for more information on programming the GPIOs.
Note: The RST pin and GPIO wake sources are cleared by a write to either or both the RSTWK
and PADIOWK bits. This clears the source of interrupts for RSTWK, PADIOWK and the
GPIOWAKESTAT register.
TMPR[3:0] are enabled by setting the appropriate ENn bits the Tamper IO Control and Status
(HIBTPIO) register. The HIBTPIO register overrides the GPIO port configuration registers. By setting
the WAKE bit in the Tamper Control (HIBTPCTL) register, a tamper event can cause a wake from
Hibernate. If a tamper event occurs, the time of the event and the status of the tamper pins are
logged in the Tamper Log (HIBTPLOG) register.
By setting the RTCWEN bit in the HIBCTL register a wake from hibernate can occur when the value
of the HIBRTCC register matches the value of the HIBRTCM0 register and the value of the RTCSSC
field matches the RTCSSM field in the HIBRTCSS register.
To allow a wake from Hibernate on a low battery event, the BATWKEN bit in the HIBCTL register
must be set. In this configuration, the battery voltage is checked every 512 seconds while in
hibernation. If the voltage is below the level specified by the VBATSEL field, the LOWBAT interrupt
is set in the HIBRIS register.
Upon external wake-up, external reset, tamper event, or RTC match, the Hibernation module delays
coming out of hibernation until VDD is above the minimum specified voltage, see Table
27-6 on page 1820.
When the Hibernation module wakes, the microcontroller performs a normal power-on reset. The
normal power-on reset does not reset the Hibernation module or Tamper module, but does reset
the rest of the microcontroller. Software can detect that the power-on was due to a wake from
hibernation by examining the raw interrupt status register (see “Interrupts and Status” on page 548)
and by looking for state data in the battery-backed memory (see “Battery-Backed
Memory” on page 545).

7.3.12 Arbitrary Power Removal

The microcontroller goes into hibernation if VDD is arbitrarily removed when the CLK32EN bit is set
and any of the following bits are set:

■ TPEN bit in the HIBTPCTL register

■ PINWEN bit in the HIBCTL register

■ RTCEN bit in the HIBCTL register

The microcontroller wakes from hibernation when power is reapplied.

If the CLK32EN bit is set but the TPEN, PINWEN, and RTCEN bits are all clear, the microcontroller
still goes into hibernation if power is removed; however, when VDD is reapplied, the MCU executes
a cold POR and the Hibernation module is reset. If the CLK32EN bit is not set and VDD is arbitrarily
removed, the part is simply powered off and executes a cold POR when power is reapplied.

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If VDD is arbitrarily removed while a Flash memory or HIBDATA register write operation is in progress,
the write operation must be retried after VDD is reapplied.

7.3.13 Interrupts and Status

The Hibernation module can generate interrupts when the following conditions occur:

■ Assertion of WAKE pin

■ RTC match

■ Low battery detected

■ Write complete/capable

■ Assertion of an external RESET pin

■ Assertion of an external wake-enabled GPIO pin (port K[7:4]])

All of the interrupts except for the tamper signals are ORed together before being sent to the interrupt
controller, so the Hibernate module can only generate a single interrupt request to the controller at
any given time. The software interrupt handler can service multiple interrupt events by reading the
Hibernation Masked Interrupt Status (HIBMIS) register. Software can also read the status of the
Hibernation module at any time by reading the HIBRIS register which shows all of the pending
events. This register can be used after waking from hibernation to see if a wake condition was
caused by one of the events above or by a power loss.
The WAKE pin can generate interrupts in Run, Sleep and Deep Sleep Mode. The events that can
trigger an interrupt are configured by setting the appropriate bits in the Hibernation Interrupt Mask
(HIBIM) register. Pending interrupts can be cleared by writing the corresponding bit in the Hibernation
Interrupt Clear (HIBIC) register.

7.4 Initialization and Configuration

The Hibernation module has several different configurations. The following sections show the
recommended programming sequence for various scenarios. Because the Hibernation module runs
at a low frequency and is asynchronous to the rest of the microcontroller, which is run off the system
clock, software must allow a delay of tHIB_REG_ACCESS after writes to registers (see “Register Access
Timing” on page 535). The WC interrupt in the HIBMIS register can be used to notify the application
when the Hibernation modules registers can be accessed.

7.4.1 Initialization
The Hibernation module comes out of reset with the system clock enabled to the module, but if the
system clock to the module has been disabled, then it must be re-enabled, even if the RTC feature
is not used. See page 387.
If a 32.768-kHz crystal is used as the Hibernation module clock source, perform the following steps:

1. Write 0x0000.0010 to the HIBIM register to enable the WC interrupt.

2. Write 0x40 to the HIBCTL register at offset 0x10 to enable the oscillator input.

3. Wait until the WC interrupt in the HIBMIS register has been triggered before performing any other
operations with the Hibernation module.

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If a 32.768-kHz single-ended oscillator is used as the Hibernation module clock source, then perform
the following steps:

1. Write 0x0000.0010 to the HIBIM register to enable the WC interrupt.

2. Write 0x0001.0040 to the HIBCTL register at offset 0x10 to enable the oscillator input and
bypass the on-chip oscillator.

3. Wait until the WC interrupt in the HIBMIS register has been triggered before performing any other
operations with the Hibernation module.

If the internal low frequency oscillator is used as the Hibernation module clock source, then perform
the following steps:

1. Write 0x0000.0010 to the HIBIM register to enable the WC interrupt.

2. Write 0x0008.0040 to the HIBCTL register at offset 0x10 to enable the internal low frequency
oscillator.

3. Wait until the WC interrupt in the HIBMIS register has been triggered before performing any other
operations with the Hibernation module.

The above steps are only necessary when the entire system is initialized for the first time. If the
microcontroller has been in hibernation, then the Hibernation module has already been powered
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.

7.4.2 RTC Match Functionality (No Hibernation)

Use the following steps to implement the RTC match functionality of the Hibernation module:

1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.

2. Write the required RTC match value to the HIBRTCM0 register at offset 0x004 and the RTCSSM
field in the HIBRTCSS register at offset 0x028.

3. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.

4. Set the required RTC match interrupt mask in the RTCALT0 in the HIBIM register at offset 0x014.

5. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.

7.4.3 RTC Match/Wake-Up from Hibernation

Use the following steps to implement the RTC match and wake-up functionality of the Hibernation
module:

1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.

2. Write the required RTC match value to the HIBRTCM0 register at offset 0x004 and the RTCSSM
field in the HIBRTCSS register at offset 0x028.

3. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. This write causes
the 15-bit sub seconds counter to be cleared.

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4. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.

5. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004B to the
HIBCTL register at offset 0x010.

7.4.4 External Wake-Up from Hibernation

Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:

1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.

2. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.

3. Enable the external wake and start the hibernation sequence by writing 0x0000.0052 to the
HIBCTL register at offset 0x010.

Use the following steps to program the external RESET pin as the wake source for the microcontroller:

1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.

2. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.

3. Enable the external RESET pin as a wake source by writing a 0x0000.0011 to the HIBIO register
at offset 0x02C.

4. When the IOWRC bit in the HIBIO register is read as 1, clear the WUUNLK bit in the HIBIO register
to lock the current pad configuration so that any other writes to the WURSTEN bit in the HIBIO
register will be ignored.

5. The hibernation sequence may be initiated by writing 0x4000.0152 to the HIBCTL register. Note
that when using RESET, the user must enable VDD3ON mode and set the RETCLR bit in the
HIBCTL register.

Use the following steps to program GPIO port K pins K[7:4] as the wake source for the microcontroller:

1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.

2. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.

3. Configure the GPIOWAKEPEN and GPIOWAKELVL registers at offsets 0x540 and 0x544 in
the GPIO module. Enable the I/O wake pad configuration by writing 0x0000.0001 to the HIBIO
register at offset 0x010.

4. When the IOWRC bit in the HIBIO register is read as 1, write 0x0000.0000 to the HIBIO register
to lock the current pad configuration so that any other writes to the GPIOWAKEPEN and
GPIOWAKELVL register will be ignored.

5. Clear any pending interrupts by writing a 1 to the PADIOWK bit in the HIBIC register.

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6. The hibernation sequence may be initiated by writing 0x4000.0152 to the HIBCTL register. Note
for Port M external wake, the user must enable VDD3ON mode and set the RETCLR bit in the
HIBCTL register.

7.4.5 RTC or External Wake-Up from Hibernation

1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.

2. Write the required RTC match value to the HIBRTCM0 register at offset 0x004 and the RTCSSM
field in the HIBRTCSS register at offset 0x028.

3. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. This write causes
the 15-bit sub seconds counter to be cleared.

4. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.

5. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005B
to the HIBCTL register at offset 0x010.

7.4.6 Tamper Initialization

Use the following steps to configure the Tamper module to interrupt the processor when a TMPR
signal has triggered:
Note: Unlike other functions, the Tamper pins do not need to be configured for the GPIO in the
GPIOAFSEL register. The Tamper IO Control and Status (HIBTPIO) register overrides
configurations made to the GPIO module.

1. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the 32.768-kHz Hibernate
oscillator and enable the RTC.

2. Enable the four Tamper I/O to trigger on the a high state on any of the pins by writing
0x0F0F.0F0F to the HIBTPIO register at offset 0x410.

3. Write 0x0000.0001 to the HIBTPCTL register to enable the tamper.

Note: Once tamper is enabled, the following HIBCTL register bits are locked and cannot be
modified:

■ OSCSEL
■ OSCDRV
■ OSCBYP
■ VDD3ON
■ CLK32EN
■ RTCEN

7.5 Register Map

Table 7-3 on page 552 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000. Note that the system clock to the Hibernation module must
be enabled before the registers can be programmed (see page 387). There must be a delay of 3
system clocks after the Hibernation module clock is enabled before any Hibernation module registers

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are accessed. In addition, the CLK32EN bit in the HIBCTL register must be set before accessing
any other Hibernation module register.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.

Important: The Hibernation module registers are reset under two conditions:

1. Any type of system reset (if the RTCEN and the PINWEN bits in the HIBCTL register
are clear and the TPEN bit in the HIBTPCTL register is clear).

2. A cold POR occurs when both the VDD and VBAT supplies are removed.

Any other reset condition is ignored by the Hibernation module.

Note that the following registers are only accessed through privileged mode (see “System
Control” on page 220 for more details):

■ HIBTPCTL

■ HIBPTSTAT

■ HIBTPIO

■ HIBTPLOG

■ Upper eight words of memory (HIBDATA register 0x50 to 0x6F)

Table 7-3. Hibernation Module Register Map

See
Offset Name Type Reset Description
page

0x000 HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 554

0x004 HIBRTCM0 RW 0xFFFF.FFFF Hibernation RTC Match 0 555

0x00C HIBRTCLD WO 0x0000.0000 Hibernation RTC Load 556

0x010 HIBCTL RW 0x8000.2000 Hibernation Control 557

0x014 HIBIM RW 0x0000.0000 Hibernation Interrupt Mask 562

0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 564

0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 566

0x020 HIBIC RW1C 0x0000.0000 Hibernation Interrupt Clear 568

0x024 HIBRTCT RW 0x0000.7FFF Hibernation RTC Trim 570

0x028 HIBRTCSS RW 0x0000.0000 Hibernation RTC Sub Seconds 571

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Table 7-3. Hibernation Module Register Map (continued)

See
Offset Name Type Reset Description
page

0x02C HIBIO RW 0x8000.0000 Hibernation IO Configuration 572

0x030-
HIBDATA RW - Hibernation Data 574
0x06F

0x300 HIBCALCTL RW 0x0000.0000 Hibernation Calendar Control 575

0x310 HIBCAL0 RO 0x0000.0000 Hibernation Calendar 0 576

0x314 HIBCAL1 RO 0x0000.0000 Hibernation Calendar 1 578

0x320 HIBCALLD0 WO 0x0000.0000 Hibernation Calendar Load 0 580

0x324 HIBCALLD1 WO 0x0000.0000 Hibernation Calendar Load 582

0x330 HIBCALM0 RW 0x0000.0000 Hibernation Calendar Match 0 583

0x334 HIBCALM1 RW 0x0000.0000 Hibernation Calendar Match 1 585

0x360 HIBLOCK RW 0x0000.0000 Hibernation Lock 586

0x400 HIBTPCTL RW 0x0000.0000 HIB Tamper Control 587

0x404 HIBTPSTAT RW1C 0x0000.0000 HIB Tamper Status 589

0x410 HIBTPIO RW 0x0000.0000 HIB Tamper I/O Control 591

0x4E0 HIBTPLOG0 RO 0x0000.0000 HIB Tamper Log 0 595

0x4E4 HIBTPLOG1 RO 0x0000.0000 HIB Tamper Log 1 596

0x4E8 HIBTPLOG2 RO 0x0000.0000 HIB Tamper Log 2 595

0x4EC HIBTPLOG3 RO 0x0000.0000 HIB Tamper Log 3 596

0x4F0 HIBTPLOG4 RO 0x0000.0000 HIB Tamper Log 4 595

0x4F4 HIBTPLOG5 RO 0x0000.0000 HIB Tamper Log 5 596

0x4F8 HIBTPLOG6 RO 0x0000.0000 HIB Tamper Log 6 595

0x4FC HIBTPLOG7 RO 0x0000.0000 HIB Tamper Log 7 596

0xFC0 HIBPP RO 0x0000.0002 Hibernation Peripheral Properties 598

0xFC8 HIBCC RW 0x0000.0000 Hibernation Clock Control 599

7.6 Register Descriptions

The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.

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Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000

This register is the current 32-bit value of the RTC counter.
The RTC counter consists of a 32-bit seconds counter and a 15-bit sub seconds counter. The RTC
counters are reset by the Hibernation module reset. The RTC 32-bit seconds counter can be set by
the user using the HIBRTCLD register. When the 32-bit seconds counter is set, the 15-bit sub
second counter is cleared.
The RTC value can be read by first reading the HIBRTCC register, reading the RTCSSC field in the
HIBRTCSS register, and then rereading the HIBRTCC register. If the two values for HIBRTCC are
equal, the read is valid.
Note: There is a minimum system clock rate of three times the HIB clock rate to properly read the
HIBRTCC register.

Hibernation RTC Counter (HIBRTCC)

Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTCC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTCC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 RTCC RO 0x0000.0000 RTC Counter

A read returns the 32-bit counter value, which represents the seconds
elapsed since the RTC was enabled. This register is read-only. To
change the value, use the HIBRTCLD register.

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Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004

This register is the 32-bit seconds match register for the RTC counter. The 15-bit sub second match
value is stored in the reading the RTCSSC field in the HIBRTCSS register and can be used in
conjunction with this register for a more precise time match.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.

Hibernation RTC Match 0 (HIBRTCM0)

Base 0x400F.C000
Offset 0x004
Type RW, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTCM0

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTCM0

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 RTCM0 RW 0xFFFF.FFFF RTC Match 0

A write loads the value into the RTC match register.
A read returns the current match value.

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Register 3: Hibernation RTC Load (HIBRTCLD), offset 0x00C

This register is used to load a 32-bit value loaded into the RTC counter. The load occurs immediately
upon this register being written. When this register is written, the 15-bit sub seconds counter is also
cleared.
Note: This register is protected from errant code by using the HIBLOCK register. This register is
write-only; any reads to this register read back as zeros.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.

Hibernation RTC Load (HIBRTCLD)

Base 0x400F.C000
Offset 0x00C
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTCLD

Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTCLD

Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 RTCLD WO 0x0000.0000 RTC Load

A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.

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Register 4: Hibernation Control (HIBCTL), offset 0x010

This register is the control register for the Hibernation module. This register must be written last
before a hibernate event is issued. Writes to other registers after the HIBREQ bit is set are not
guaranteed to complete before hibernation is entered.
Note: Writes to this register have special timing requirements. Software should make use of the
WRC bit in the HIBCTL register to ensure that the required synchronization has elapsed.
While the WRC bit is clear, any attempts to write this register are ignored. Reads may occur
at any time.
Note that once tamper is enabled, the following HIBCTL clock configuration bits and bus write stall
bit are locked and cannot be modified:

■ OSCSEL
■ OSCDRV
■ OSCBYP
■ VDD3ON
■ CLK32EN
■ RTCEN

Hibernation Control (HIBCTL)

Base 0x400F.C000
Offset 0x010
Type RW, reset 0x8000.2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WRC RETCLR reserved OSCSEL reserved OSCDRV OSCBYP

Type RO RW RO RO RO RO RO RO RO RO RO RO RW RO RW RW
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VBATSEL reserved BATCHK BATWKEN VDD3ON VABORT CLK32EN reserved PINWEN RTCWEN reserved HIBREQ RTCEN

Type RO RW RW RO RO RW RW RW RW RW RO RW RW RO RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 WRC RO 1 Write Complete/Capable

Value Description
0 The interface is processing a prior write and is busy. Any write
operation that is attempted while WRC is 0 results in
undetermined behavior.
1 The interface is ready to accept a write.

Software must poll this bit between write requests and defer writes until
WRC=1 to ensure proper operation. An interrupt can be configured to
indicate the WRC has completed.
The bit name WRC means "Write Complete," which is the normal use of
the bit (between write accesses). However, because the bit is set
out-of-reset, the name can also mean "Write Capable" which simply
indicates that the interface may be written to by software. This difference
may be exploited by software at reset time to detect which method of
programming is appropriate: 0 = software delay loops required; 1 = WRC
paced available.

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Bit/Field Name Type Reset Description

30 RETCLR RW 0 GPIO Retention/Clear

This bit is used when the VDD3ON bit is set.This bit is must be set when
entering the hibernate state when the VDD3ON bit is set. This does not
affect behavior when VDD3ON is clear.

Note: This bit must be set when enabling VDD3ON mode.

Value Description
0 GPIO retention is released when power is reapplied. The GPIOs
are initialized to default values.
1 GPIO retention set until software clears this bit.

29:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19 OSCSEL RW 0 Oscillator Select

This bit is used to select between the use of an external 32.768-kHz
source or the HIB internal low frequency oscillator (HIB LFIOSC).

Note: To enable the HIB LFIOSC, CLK32EN must be programmed

to 1 at the same time the OSCSEL bit is set. Thus the HIBCTL
register should be written with 0x0008.0040

Value Description
0 External 32.786-kHZ clock source is enabled.
1 HIB Low frequency oscillator (HIB LFIOSC) is enabled.

Note: The HIB low-frequency oscillator has a wide frequency

variation, therefore the RTC is not accurate when using this
clock source.

18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

17 OSCDRV RW 0 Oscillator Drive Capability

This bit is used to compensate for larger or smaller filtering capacitors.

Note: This bit is not meant to be changed once the Hibernation

oscillator has started. Oscillator stability is not guaranteed if
the user changes this value after the oscillator is running.

Value Description
0 Low drive strength is enabled, 12 pF.
1 High drive strength is enabled, 24 pF.

16 OSCBYP RW 0 Oscillator Bypass

Value Description
0 The internal 32.768-kHz Hibernation oscillator is enabled. This
bit should be cleared when using an external 32.768-kHz crystal.
1 The internal 32.768-kHz Hibernation oscillator is disabled and
powered down. This bit should be set when using a single-ended
oscillator attached to XOSC0.

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Bit/Field Name Type Reset Description

15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14:13 VBATSEL RW 0x1 Select for Low-Battery Comparator

This field selects the battery level that is used when checking the battery
status. If the battery voltage is below the specified level, the LOWBAT
interrupt bit in the HIBRIS register is set.

Value Description
0x0 1.9 Volts
0x1 2.1 Volts (default)
0x2 2.3 Volts
0x3 2.5 Volts

12:11 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 BATCHK RW 0 Check Battery Status

Value Description
0 When read, indicates that the low-battery comparator cycle is
not active.
Writing a 0 has no effect.
1 When read, indicates the low-battery comparator cycle has not
completed.
Setting this bit initiates a low-battery comparator cycle. If the
battery voltage is below the level specified by VBATSEL field,
the LOWBAT interrupt bit in the HIBRIS register is set. A
hibernation request is held off if a battery check is in progress.

9 BATWKEN RW 0 Wake on Low Battery

Value Description
0 The battery voltage level is not automatically checked. Low
battery voltage does not cause the microcontroller to wake from
hibernation.
1 In RTC mode, when this bit is set, the battery voltage level is
checked every 512 seconds while in hibernation.
In calendar mode, the battery voltage is checked on minutes
divisible by 8 while in hibernation.
If the voltage is below the level specified by VBATSEL field, the
microcontroller wakes from hibernation and the LOWBAT interrupt
bit in the HIBRIS register is set.

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Bit/Field Name Type Reset Description

8 VDD3ON RW 0 VDD Powered

Value Description
0 The internal switches are not used. The HIB signal should be
used to control an external switch or regulator.
1 The internal switches control the power to the on-chip modules
(VDD3ON mode).

Regardless of the status of the VDD3ON bit, the HIB signal is asserted
during Hibernate mode. Thus, when VDD3ON is set, the HIB signal
should not be connected to the 3.3V regulator, and the 3.3V power
source should remain connected. When this bit is set while in hibernation,
all pins are held in the state they were in prior to entering hibernation.
For example, inputs remain inputs; outputs driven high remain driven
high, and so on.
Ports retain their state in VDD3ON mode until the RETCLR bit is cleared.
The RETCLR bit must be set when the VDD3ON bit is set.

7 VABORT RW 0 Power Cut Abort Enable

Value Description
0 The microcontroller goes into hibernation regardless of the
voltage level of the battery.
1 When this bit is set, the battery voltage level is checked
before entering hibernation. If VBAT is less than the voltage
specified by VBATSEL, the microcontroller does not go into
hibernation.

6 CLK32EN RW 0 Clocking Enable

This bit must be enabled to use the Hibernation module.

Value Description
0 The Hibernation module clock source is disabled.
1 The Hibernation module clock source is enabled.

5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 PINWEN RW 0 External Wake and Interrupt Pin Enable

Value Description
0 The status of the WAKE or an external I/O wake pad source
pin has no effect on hibernation.
1 An assertion of the WAKE pin or an external I/O wake pad
source takes the microcontroller out of hibernation. An
external I/O wake pad interrupt may be generated in active
mode.

Note: The external I/O wake pad interrupt is set if the WAKE pin is
asserted in Run, Sleep, or Deep Sleep mode regardless of
whether the PINWEN bit is 0x0 or 0x1. The interrupt may be
forwarded to the processor by setting the EXTW bit in the
HIBIM register.

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Bit/Field Name Type Reset Description

3 RTCWEN RW 0 RTC Wake-up Enable

Value Description
0 An RTC match event has no effect on hibernation.
1 An RTC match event (the value the HIBRTCC register
matches the value of the HIBRTCM0 register and the value
of the RTCSSC field matches the RTCSSM field in the
HIBRTCSS register) takes the microcontroller out of
hibernation.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 HIBREQ RW 0 Hibernation Request

Value Description
0 No hibernation request.
1 Set this bit to initiate hibernation.

After a wake-up event, this bit is automatically cleared by hardware.

A hibernation request is ignored if both the PINWEN and RTCWEN bits
are clear.

0 RTCEN RW 0 RTC Timer/Calendar Enable

This is bit must be set to enable RTC or calendar mode. For calendar
mode enable, the CALEN bit in the HIBCALCTL register must also be
set.

Value Description
0 The Hibernation module RTC and calendar mode are
disabled.
1 The Hibernation module RTC and calendar mode are
enabled.

Note: The low-frequency oscillator has a wide frequency variation,

therefore the RTC is not accurate when using this clock
source.

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Register 5: Hibernation Interrupt Mask (HIBIM), offset 0x014

This register is the interrupt mask register for the Hibernation module interrupt sources. Each bit in
this register masks the corresponding bit in the Hibernation Raw Interrupt Status (HIBRIS) register.
If a bit is unmasked, the interrupt is sent to the interrupt controller. If the bit is masked, the interrupt
is not sent to the interrupt controller. The WC bit of the HIBIM register may be set before the CLK32EN
bit of the HIBCTL register is set. This allows software to use the WC interrupt trigger to detect when
the RTCOSC clock is stable, which may be in excess of one second. If the WC bit is set before the
CLK32EN has been set, the mask value is not preserved over a hibernate cycle unless the bit is
written a second time.
Note: The WC bit of this register is in the system clock domain such that a write to this bit is
immediate and may be done before the CLK32EN bit is set in the HIBCTL register.

Hibernation Interrupt Mask (HIBIM)

Base 0x400F.C000
Offset 0x014
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VDDFAIL RSTWK PADIOWK WC EXTW LOWBAT reserved RTCALT0

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 VDDFAIL RW 0 VDD Fail Interrupt Mask

Value Description
0 The VDDFAIL interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the VDDFAIL
bit in the HIBRIS register is set.

6 RSTWK RW 0 Reset Pad I/O Wake-Up Interrupt Mask

Value Description
0 The RSTWK interrupt is suppressed and not sent to the interrupt
controller.
1 An interrupt is sent to the interrupt controller when the RSTWK
bit in the HIBRIS register is set.

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Bit/Field Name Type Reset Description

5 PADIOWK RW 0 Pad I/O Wake-Up Interrupt Mask

Value Description
0 The PADIOWK interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the PADIOWK
bit in the HIBRIS register is set.

4 WC RW 0 External Write Complete/Capable Interrupt Mask

Value Description
0 The WC interrupt is suppressed and not sent to the interrupt
controller.
1 An interrupt is sent to the interrupt controller when the WC bit in
the HIBRIS register is set.

3 EXTW RW 0 External Wake-Up Interrupt Mask

Value Description
0 The EXTW interrupt is suppressed and not sent to the interrupt
controller.
1 An interrupt is sent to the interrupt controller when the EXTW bit
in the HIBRIS register is set.

2 LOWBAT RW 0 Low Battery Voltage Interrupt Mask

Value Description
0 The LOWBAT interrupt is suppressed and not sent to the interrupt
controller.
1 An interrupt is sent to the interrupt controller when the LOWBAT
bit in the HIBRIS register is set.

1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 RTCALT0 RW 0 RTC Alert 0 Interrupt Mask

Value Description
0 The RTCALT0 interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the RTCALT0
bit in the HIBRIS register is set.

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Register 6: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018

This register is the raw interrupt status for the Hibernation module interrupt sources. Each bit can
be masked by clearing the corresponding bit in the HIBIM register. When a bit is masked, the
interrupt is not sent to the interrupt controller. Bits in this register are cleared by writing a 1 to the
corresponding bit in the Hibernation Interrupt Clear (HIBIC) register or by entering hibernation.

Hibernation Raw Interrupt Status (HIBRIS)

Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VDDFAIL RSTWK PADIOWK WC EXTW LOWBAT reserved RTCALT0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 VDDFAIL RO 0 VDD Fail Raw Interrupt Status

Value Description
0 No VDDFAIL interrupt condition exists.
1 An interrupt is sent to the interrupt controller because of arbitrary
power removal or because one or more of the supplies (VDD,
VDDA or VDDC) has dropped below the defined operating range.

6 RSTWK RO 0 Reset Pad I/O Wake-Up Raw Interrupt Status

Value Description
0 The RESET pin has not been asserted or has not been enabled
to wake the device from hibernation.
1 An interrupt is sent to the interrupt controller because the RESET
pin has been programmed to wake the device from hibernation.

5 PADIOWK RO 0 Pad I/O Wake-Up Raw Interrupt Status

Value Description
0 One of the wake-enabled GPIO pins or the external RESET pin
has not been asserted or has not been enabled to wake the
device from hibernation.
1 An interrupt is sent to the interrupt controller because one of
the wake-enabled GPIO pins or the external RESET pin has
been asserted.

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Bit/Field Name Type Reset Description

4 WC RO 0 Write Complete/Capable Raw Interrupt Status

Value Description
0 The WRC bit in the HIBCTL has not been set.
1 The WRC bit in the HIBCTL has been set.

This bit is cleared by writing a 1 to the WC bit in the HIBIC register.

3 EXTW RO 0 External Wake-Up Raw Interrupt Status

Note that a wake signal source must be cleared by the application after
the interrupt has been registered.

Value Description
0 The WAKE pin has not been asserted.
1 The WAKE pin has been asserted.

This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.

Note: The EXTW bit is set if the WAKE pin is asserted in any mode
of operation (Run, Sleep, Deep Sleep) regardless of whether
the PINWEN bit is set in the HIBCTL register.

2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status

Value Description
0 The battery voltage has not dropped below VLOWBAT.
1 The battery voltage dropped below VLOWBAT.

This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.

1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 RTCALT0 RO 0 RTC Alert 0 Raw Interrupt Status

Value Description
0 No match
1 If the RTC is enabled, t he value of the HIBRTCC register
matches the value in the HIBRTCM0 register and the value of
the RTCSSC field matches the RTCSSM field in the HIBRTCSS
register.
If the Calendar function is enabled, this interrupt status indicates
that one or more of the allowed fields in the HIBCAL0/1 register
matches in the HIBCALM0/1 register..

This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register.

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Register 7: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C

This register is the masked interrupt status for the Hibernation module interrupt sources. Bits in this
register are the AND of the corresponding bits in the HIBRIS and HIBIM registers. When both
corresponding bits are set, the bit in this register is set, and the interrupt is sent to the interrupt
controller.

Hibernation Masked Interrupt Status (HIBMIS)

Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VDDFAIL RSTWK PADIOWK WC EXTW LOWBAT reserved RTCALT0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 VDDFAIL RO 0 VDD Fail Interrupt Mask

Value Description
0 An VDDFAIL interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a an arbitrary loss
of power or because on or more of the voltage supplies (VDD,
VDDA or VDDC) has dropped below the defined operating
range.

6 RSTWK RO 0 Reset Pad I/O Wake-Up Interrupt Mask

Value Description
0 An external reset interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a RESET pin
assertion.

5 PADIOWK RO 0 Pad I/O Wake-Up Interrupt Mask

Value Description
0 An external GPIO or reset interrupt has not occurred or is
masked.
1 An unmasked interrupt was signaled due to a wake-enabled
GPIO or RESET pin assertion.

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Bit/Field Name Type Reset Description

4 WC RO 0 Write Complete/Capable Masked Interrupt Status

Value Description
0 The WRC bit has not been set or the interrupt is masked.
1 An unmasked interrupt was signaled due to the WRC bit being
set.

This bit is cleared by writing a 1 to the WC bit in the HIBIC register.

3 EXTW RO 0 External Wake-Up Masked Interrupt Status

Value Description
0 An external wake-up interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a WAKE pin
assertion.

This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.

2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status

Value Description
0 A low-battery voltage interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a low-battery voltage
condition.

This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.

1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 RTCALT0 RO 0 RTC Alert 0 Masked Interrupt Status

Note: The MIS may apply to either the RTC or calendar block
depending on which is enabled.

Value Description
0 An RTC or calendar match interrupt has not occurred or is
masked.
1 An unmasked interrupt was signaled due to an RTC or calendar
match.

This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register.

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 Hibernation Module

Register 8: Hibernation Interrupt Clear (HIBIC), offset 0x020

This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Writing a 1 to a bit clears the corresponding interrupt in the HIBRIS register.
Note: Writes to the RSTWK, PADIOWK and WC bits of this register are immediate and the status
may be read from the HIBRIS and HIBMIS registers without monitoring the WRC bit of the
HIBCTL register.
Note: All I/O wake sources are cleared by a write to either or both the RSTWK and PADIOWK bits.
This clears the source of interrupts for RSTWK, PADIOWK and the GPIOWAKESTAT register.

Hibernation Interrupt Clear (HIBIC)

Base 0x400F.C000
Offset 0x020
Type RW1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VDDFAIL RSTWK PADIOWK WC EXTW LOWBAT reserved RTCALT0

Type RO RO RO RO RO RO RO RO RW1C RW1C RW1C RW1C RW1C RW1C RO RW1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 VDDFAIL RW1C 0 VDD Fail Interrupt Clear

Writing a 1 to this bit clears the VDDFAIL bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.

6 RSTWK RW1C 0 Reset Pad I/O Wake-Up Interrupt Clear

Writing a 1 to this bit clears the RSTWK bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.

5 PADIOWK RW1C 0 Pad I/O Wake-Up Interrupt Clear

Writing a 1 to this bit clears the PADIOWK bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.

4 WC RW1C 0 Write Complete/Capable Interrupt Clear

Writing a 1 to this bit clears the WC bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.

3 EXTW RW1C 0 External Wake-Up Interrupt Clear

Writing a 1 to this bit clears the EXTW bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.

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Bit/Field Name Type Reset Description

2 LOWBAT RW1C 0 Low Battery Voltage Interrupt Clear

Writing a 1 to this bit clears the LOWBAT bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.

1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 RTCALT0 RW1C 0 RTC Alert0 Masked Interrupt Clear

Writing a 1 to this bit clears the RTCALT0 bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.

Note: The timer interrupt source cannot be cleared if the RTC value
and the HIBRTCM0 register / RTCMSS field values are equal.
The match interrupt takes priority over the interrupt clear.

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Register 9: Hibernation RTC Trim (HIBRTCT), offset 0x024

This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles, where N is the number of clock cycles to add or subtract every 64 seconds in RTC mode or
60 seconds in calendar mode.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.

Hibernation RTC Trim (HIBRTCT)

Base 0x400F.C000
Offset 0x024
Type RW, reset 0x0000.7FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TRIM

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 TRIM RW 0x7FFF RTC Trim Value

This value is loaded into the RTC predivider every 64 seconds in RTC
counter mode.
In calendar mode, the value is loaded every 60 seconds.
It is used to adjust the RTC rate to account for drift and inaccuracy in
the clock source. Compensation can be adjusted by software by moving
the default value of 0x7FFF up or down. Moving the value up slows
down the RTC and moving the value down speeds up the RTC.

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Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028

This register contains the RTC sub seconds counter and match values. The RTC value can be read
by first reading the HIBRTCC register, reading the RTCSSC field in the HIBRTCSS register, and
then rereading the HIBRTCC register. If the two values for HIBRTCC are equal, the read is valid.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Note: There is a minimum system clock rate of three times the HIB clock rate to properly read the
HIBRTCSS register.

Hibernation RTC Sub Seconds (HIBRTCSS)

Base 0x400F.C000
Offset 0x028
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved RTCSSM

Type RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved RTCSSC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

30:16 RTCSSM RW 0x0000 RTC Sub Seconds Match

The match value is contained in this field in one RTCOSC clock
increments. A read returns the current seconds match value.

15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14:0 RTCSSC RO 0x0000 RTC Sub Seconds Count

This field contains the sub second RTC count and is read as RTCOSC
clock units. For the 32.768-kHz clock source, this would be in units of
1/32,768 seconds.

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Register 11: Hibernation IO Configuration (HIBIO), offset 0x02C

This register is used to lock and unlock the external wake pin levels and enable the external RST
pin and/or GPIO pins, Port K[7:4], as valid external WAKE sources.
Note: This register is in the system clock domain and does not require monitoring the WRC bit of
the HIBCTL register before issuing a read or write of this register. Writes to this register are
immediate.
Note: This register is in the core voltage domain and will not retain values over a hibernate cycle

Hibernation IO Configuration (HIBIO)

Base 0x400F.C000
Offset 0x02C
Type RW, reset 0x8000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IOWRC reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved WURSTEN reserved WUUNLK

Type RO RO RO RO RO RO RO RO RO RO RO RW RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 IOWRC RO 0x1 I/O Write Complete

Indicates whether or not the configuration that was programmed by the
WURSTEN bit or GPIOWAKEPEN and GPIOWAKELVL registers have
propagated through the pad ring.

Value Description
0 The changes programmed in the external pad I/O wake source
registers have not propagated through the pad I/O.
1 The changes programmed in the external pad I/O wake source
registers have propagated through the pad I/O.

30:5 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 WURSTEN RW 0 Reset Wake Source Enable

This register bit programming takes affect after WUUNLK has been set.

Value Description
0 The RST signal is not enabled as a wake source.
1 The RST signal is enabled as a wake source.

3:1 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

0 WUUNLK RW 0 I/O Wake Pad Configuration Enable

Value Description
0 The I/O WAKE configuration set by the WURSTEN bit or in the
GPIO module registers GPIOWAKEPEN and GPIOWAKELVL
is ignored.
1 Implement the I/O WAKE configuration, level and enables for
the external RST pin and/or GPIO wake-enabled pins.

Note: This bit must be cleared before issuing a hibernate

request by setting the HIBREQ bit in the HIBCTL
register.

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Register 12: Hibernation Data (HIBDATA), offset 0x030-0x06F

This address space is implemented as a 16x32-bit memory (64 bytes). It can be loaded by the
system processor in order to store state information and retains its state during a power cut operation
as long as a battery is present. HIBDATA registers 0x050 to 0x064 (upper eight words) may only
be accessed using the processor privileged mode (default).
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Note: If VDD is arbitrarily removed while a HIBDATA register write operation is in progress, the
write operation must be retried after VDD is reapplied.

Hibernation Data (HIBDATA)

Base 0x400F.C000
Offset 0x030-0x06F
Type RW, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTD

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTD

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 RTD RW - Hibernation Module NV Data

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Register 13: Hibernation Calendar Control (HIBCALCTL), offset 0x300

The Hibernate calendar is enabled by setting the CALEN bit in the HIBCALCTL register. If the BCD
bit is set, the fields are reported in BCD format.

Hibernation Calendar Control (HIBCALCTL)

Base 0x400F.C000
Offset 0x300
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CAL24 reserved CALEN

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 CAL24 RW 0 Calendar Mode

Value Description
0 12 hour, AM/PM Mode
1 24 hour mode

1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 CALEN RW 0 RTC Calendar/Counter Mode Select

Note that the RTC must be enabled by setting the RTCEN bit in the
HIBCTL register to use this mode select.

Value Description
0 RTC Counter mode enabled.
1 Calendar mode enabled

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Register 14: Hibernation Calendar 0 (HIBCAL0), offset 0x310

The Hibernation Calendar 0 (HIBCAL0) register is used when the CALEN bit is set in the
HIBCALCTL register.

Hibernation Calendar 0 (HIBCAL0)

Base 0x400F.C000
Offset 0x310
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VALID reserved AMPM reserved HR

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MIN reserved SEC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 VALID RO 0 Valid Calendar Load

The calendar may take several cycles to update as the values roll over.
This bit indicates whether the HIBCAL0 register contents are valid.

Value Description
0 Register currently updating or initializing
1 HIBCAL0 register valid and ready.

30:23 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

22 AMPM RO 0 AM/PM Designation

This bit is used when CAL24=0 in the HIBCALCTL register.

Value Description
0 AM
1 PM

21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

20:16 HR RO 0 Hours
This field holds the hour information in hexadecimal.
For military time, bits 20:16 range from 0x0 to 0x17 (0 to 23 hours).
For standard time (AM/PM mode) bits 20:16 range from 0x0 to 0x11,
with 0x0 representing 12AM or 12 PM.

15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

13:8 MIN RO 0 Minutes

This field holds the minute information in hexadecimal. Bits 13:8
correspond to hex values from 0x0 to 0x3b (0 to 59 minutes).

7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:0 SEC RO 0 Seconds

This field holds the seconds value in hexadecimal. Bits 5:0 correspond
to hex values from 0x0 to 0x3b (0 to 59 seconds).

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Register 15: Hibernation Calendar 1 (HIBCAL1), offset 0x314

The Hibernation Calendar 1 (HIBCAL1) register is used when the CALEN bit is set in the
HIBCALCTL register.

Hibernation Calendar 1 (HIBCAL1)

Base 0x400F.C000
Offset 0x314
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VALID reserved DOW reserved YEAR

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MON reserved DOM

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 VALID RO 0 Valid Calendar Load

The calendar may take several cycles to update as the values roll over.
This bit indicates whether the HIBCAL1 register contents are valid.

Value Description
0 Register currently updating or initializing
1 HIBCAL1 register valid and ready.

30:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26:24 DOW RO 0 Day of Week

This field displays the day of the week in the encodings 0x0 to 0x6. The
application defines which days are assigned to each encoding.

23 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

22:16 YEAR RO 0 Year Value

The last two digits of the year are stored in hexadecimal in this field.
Bits 22:16 correspond to hex values from 0x0 to 0x63 (0 to 99 years).

15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:8 MON RO 0 Month

This field holds the month value in hexadecimal.
Bits 11:8 correspond to hex values from 0x1 to 0xC (1 to 12 months).

7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

4:0 DOM RO 0 Day of Month

This field holds the day of the month value in hexadecimal.
Bits 4:0 correspond to hex values from 0x1 to 1F (1 to 31 days). The
value 0 is used to show an ignore match.

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Register 16: Hibernation Calendar Load 0 (HIBCALLD0), offset 0x320

The Hibernation Calendar Load (HIBCALLD0) register is used when the CALEN bit is set in the
HIBCALCTL register.
Note: This register is write-only; any reads to this register read back as zeros. Errant writes to the
HIBCALLD0/1 registers are protected by the Hibernate HIBLOCK register.

Hibernation Calendar Load 0 (HIBCALLD0)

Base 0x400F.C000
Offset 0x320
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved AMPM reserved HR

Type RO RO RO RO RO RO RO RO RO WO RO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MIN reserved SEC

Type RO RO WO WO WO WO WO WO RO RO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:23 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

22 AMPM WO 0 AM/PM Designation

This bit is used when CAL24=0 in the HIBCALCTL register.

Value Description
0 AM
1 PM

21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

20:16 HR WO 0 Hours
This field holds the hour information in hexadecimal.
Bits 20:16 correspond to hex values from 0x0 to 0x17 (0 to 23 hours).

15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

13:8 MIN WO 0 Minutes

This field holds the minute information in hexadecimal.
Bits 13:8 correspond to hex values from 0x0 to 0x3B (0 to 59 minutes).

7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

5:0 SEC WO 0 Seconds

This field holds the seconds value in hexadecimal.
Bits 5:0 correspond to hex values from 0x0 to 0x3B (0 to 59 seconds).

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Register 17: Hibernation Calendar Load (HIBCALLD1), offset 0x324

The Hibernation Calendar Load 1 (HIBCALLD1) register is used when the CALEN bit is set in the
HIBCALCTL register.
Note: This register is write-only; any reads to this register read back as zeros. Errant writes to the
HIBCALLD0/1 registers are protected by the Hibernate HIBLOCK register.

Hibernation Calendar Load (HIBCALLD1)

Base 0x400F.C000
Offset 0x324
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved DOW reserved YEAR

Type RO RO RO RO RO WO WO WO RO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MON reserved DOM

Type RO RO RO RO WO WO WO WO RO RO RO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26:24 DOW WO 0 Day of Week

This field is written with the day of the week in the encodings 0x0 to 0x6.
The application defines which days are assigned to each encoding.

23 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

22:16 YEAR WO 0 Year Value

The last two digits of the year are written in this field in hexadecimal.
For example, "12" would be programmed into this field for 2012.
Bits 22:16 correspond to hex values from 0x0 to 0x63 (0 to 99 years).

15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:8 MON WO 0 Month

The month value is written in this field in hexadecimal.
Bits 11:8 correspond to hex values from 0x1 to 0xC (1 to 12 months).

7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4:0 DOM WO 0 Day of Month

The day of the month value is written in this field in hexadecimal.
Bits 4:0 correspond to hex values from 0x1 to 1F (1 to 31 days). The
encoding 0x0 is reserved for the ignore match function.

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Register 18: Hibernation Calendar Match 0 (HIBCALM0), offset 0x330

The Hibernation Calendar Match 0 (HIBCALM0) register is used when the CALEN bit is set in the
HIBCALCTL register. This register is loaded with desired match values for calendar mode. Once
the HIBCAL0/1 register values equal the HIBCALM0/1 register values, the RTCALT0 bit is set in
the HIBRIS register.
Note: The day of week, month and year are not included in the match functionality.

Hibernation Calendar Match 0 (HIBCALM0)

Base 0x400F.C000
Offset 0x330
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved AMPM reserved HR

Type RO RO RO RO RO RO RO RO RO RW RO RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MIN reserved SEC

Type RO RO RW RW RW RW RW RW RO RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:23 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

22 AMPM RW 0 AM/PM Designation

This bit is used when CAL24=0 in the HIBCALCTL register.

Value Description
0 AM
1 PM

21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

20:16 HR RW 0 Hours
This field match value for the hours in hexadecimal units.
Bits 20:16 correspond to hex values from 0x0 to 0x17 (0 to 23 hours).
To ignore the hours match, write this field to all 1s.

15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

13:8 MIN RW 0 Minutes

This field holds the match value for minutes in hexadecimal units.
Bits 13:8 correspond to hex values from 0x0 to 0x3B (0 to 59 minutes).
To ignore the hours match, write this field to all 1s.

7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

5:0 SEC RW 0 Seconds

This field holds the match value for seconds. The value is represented
in hexadecimal.
Bits 5:0 correspond to hex values from 0x0 to 0x3b (0 to 59 seconds).
To ignore the hours match, write this field to all 1s.

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Register 19: Hibernation Calendar Match 1 (HIBCALM1), offset 0x334

The Hibernation Calendar Match 1 (HIBCALM1) register is used when the CALEN bit is set in the
HIBCALCTL register. This register is loaded with desired match values for calendar mode. Once
the HIBCAL0/1 register values equal the HIBCALM0/1 register values, the RTCALT0 bit is set in
the HIBRIS register.
Note: The day of week, month and year are not included in the match functionality.

Hibernation Calendar Match 1 (HIBCALM1)

Base 0x400F.C000
Offset 0x334
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DOM

Type RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4:0 DOM RW 0 Day of Month

This field holds the match value for the day of the month in hexadecimal.
Bits 4:0 correspond to hex values from 0x1 to 1F (1 to 31 days). To
disable match for the day of the month, the value 0x0 is used.

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Register 20: Hibernation Lock (HIBLOCK), offset 0x360

Writing 0xA335.9554 to the HIBLOCK register enables write access to the HIBRTCLD, HIBCALLD0,
HIBCALLD1 and Tamper registers. Writing any other value to the HIBLOCK register re-enables
the locked state for register writes to all the other registers. Reading the HIBLOCK register returns
the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled,
reading the HIBLOCK register returns 0x0000.0001 when locked; otherwise, the returned value is
0x0000.0000 (unlocked).

Hibernation Lock (HIBLOCK)

Base 0x400F.C000
Offset 0x360
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

HIBLOCK

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HIBLOCK

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 HIBLOCK RW 0x0000 HIbernate Lock

A write of 0xA335.9554 unlocks the HIBRCTL and Tamper registers.

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Register 21: HIB Tamper Control (HIBTPCTL), offset 0x400

The Tamper Control (HIBTPCTL) register provides control of the module.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Note: Errant writes to the Tamper registers are protected by the Hibernate HIBLOCK register.

HIB Tamper Control (HIBTPCTL)

Base 0x400F.C000
Offset 0x400
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved WAKE reserved MEMCLR reserved TPCLR reserved TPEN

Type RO RO RO RO RW RO RW RW RO RO RO W1C RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11 WAKE RW 0 Wake from Hibernate on a Tamper Event

Value Description
0 Do not wake from hibernate on a tamper event.
1 Wake from hibernate on a tamper event.

10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9:8 MEMCLR RW 0 HIB Memory Clear on Tamper Event

Value Description
0x0 Do not Clear HIB memory on tamper event.
0x1 Clear Lower 32 Bytes of HIB memory on tamper event
0x2 Clear upper 32 Bytes of HIB memory on tamper event
0x3 Clear all HIB memory on tamper event

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Bit/Field Name Type Reset Description

7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 TPCLR W1C 0 Tamper Event Clear

Writing a 1 to this bit clears the tamper event. The status of the clear is
reflected in the STATE bit field.

3:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 TPEN RW 0 Tamper Module Enable

This bit enables the Tamper module.

Value Description
0 Tamper module disabled.
1 Tamper module Enabled.

Note: Once tamper is enabled, the following HIBCTL register bits

are locked and cannot be modified:

■ OSCSEL

■ OSCDRV

■ OSCBYP

■ VDD3ON

■ CLK32EN

■ RTCEN

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Register 22: HIB Tamper Status (HIBTPSTAT), offset 0x404

The HIB Tamper Status (HIBTPCTL) register provides status of the module.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Note: Errant writes to the Tamper registers are protected by the Hibernate HIBLOCK register.

HIB Tamper Status (HIBTPSTAT)

Base 0x400F.C000
Offset 0x404
Type RW1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved STATE XOSCST XOSCFAIL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3:2 STATE RO 0 Tamper Module Status

Tamper is defined as being configured when the tamper I/Os have been
enabled (setting the ENx bits in the HIBTPIO register).

Value Description
0x0 Tamper disabled.
0x1 Tamper configured.
0x2 Tamper pin event occurred.

1 XOSCST RO 0 External Oscillator Status

Value Description
0 Active
1 Stopped

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Bit/Field Name Type Reset Description

0 XOSCFAIL RW1C 0 External Oscillator Failure

Write a 1 to this bit to clear it.

Value Description
0 External oscillator is valid.
1 External oscillator has failed

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Register 23: HIB Tamper I/O Control (HIBTPIO), offset 0x410

The HIB Tamper I/O Control (HIBTPIO) register provides control of the Tamper I/O.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Note: Errant writes to the Tamper registers are protected by the Hibernate HIBLOCK register.

HIB Tamper I/O Control (HIBTPIO)

Base 0x400F.C000
Offset 0x410
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved GFLTR3 PUEN3 LEV3 EN3 reserved GFLTR2 PUEN2 LEV2 EN2

Type RO RO RO RO RW RW RW RW RO RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved GFLTR1 PUEN1 LEV1 EN1 reserved GFLTR0 PUEN0 LEV0 EN0

Type RO RO RO RO RW RW RW RW RO RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:28 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

27 GFLTR3 RW 0 TMPR3 Glitch Filtering

Value Description
0 A trigger match level is ignored until the TMPR3 signal is stable
for two hibernate clocks.
1 A trigger match level is ignored until the TMPR3 signal is stable
for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).

26 PUEN3 RW 0 TMPR3 Internal Weak Pull-up Enable

Value Description
0 Pull-up disabled
1 Pull-up enabled

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Bit/Field Name Type Reset Description

25 LEV3 RW 0 TMPR3 Trigger Level

Value Description
0 Trigger on level low
1 Trigger on level high

24 EN3 RW 0 TMPR3 Enable

Value Description
0 Detect disabled
1 Detect enabled

23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19 GFLTR2 RW 0 TMPR2 Glitch Filtering

Value Description
0 A trigger match level is ignored until the TMPR2 signal is stable
for two hibernate clocks.
1 A trigger match level is ignored until the TMPR2 signal is stable
for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).

18 PUEN2 RW 0 TMPR2 Internal Weak Pull-up Enable

Value Description
0 Pull-up disabled
1 Pull-up enabled

17 LEV2 RW 0 TMPR2 Trigger Level

Value Description
0 Trigger on level low
1 Trigger on level high

16 EN2 RW 0 TMPR2 Enable

Value Description
0 Detect disabled
1 Detect enabled

15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

11 GFLTR1 RW 0 TMPR1 Glitch Filtering

Value Description
0 A trigger match level is ignored until the TMPR1 signal is stable
for two hibernate clocks.
1 A trigger match level is ignored until the TMPR1 signal is stable
for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).

10 PUEN1 RW 0 TMPR1 Internal Weak Pull-up Enable

Value Description
0 Pull-up disabled
1 Pull-up enabled

9 LEV1 RW 0 TMPR1 Trigger Level

Value Description
0 Trigger on level low
1 Trigger on level high

8 EN1 RW 0 TMPR1Enable

Value Description
0 Detect disabled
1 Detect enabled

7:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 GFLTR0 RW 0 TMPR0 Glitch Filtering

Value Description
0 A trigger match level is ignored until the TMPR0 signal is stable
for two hibernate clocks.
1 A trigger match level is ignored until the TMPR0 signal is stable
for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).

2 PUEN0 RW 0 TMPR0 Internal Weak Pull-up Enable

Value Description
0 Pull-up disabled
1 Pull-up enabled

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Bit/Field Name Type Reset Description

1 LEV0 RW 0 TMPR0 Trigger Level

Value Description
0 Trigger on level low
1 Trigger on level high

0 EN0 RW 0 TMPR0 Enable

Value Description
0 Detect disabled
1 Detect enabled

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Register 24: HIB Tamper Log 0 (HIBTPLOG0), offset 0x4E0

Register 25: HIB Tamper Log 2 (HIBTPLOG2), offset 0x4E8
Register 26: HIB Tamper Log 4 (HIBTPLOG4), offset 0x4F0
Register 27: HIB Tamper Log 6 (HIBTPLOG6), offset 0x4F8
The HIB Tamper Log (HIBTPLOG) even registers capture the time information during a tamper
event. Up to four tamper logs can be stored. The HIBTPLOG registers are cleared when the TPCLR
bit is written in the HIBTPCTL register.
Note: It is recommended that an external oscillator is used if accurate time stamps on the tamper
log are critical.

HIB Tamper Log 0 (HIBTPLOG0)

Base 0x400F.C000
Offset 0x4E0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TIME

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIME

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 TIME RO 0x0 Tamper Log Calendar Information.

When the hibernate module is configured for RTC count mode, the time
from the RTCCC register is captured on a tamper event.
If the calendar function is enabled, the captured time is configured as
the hex values for year, month, day, hour, minute and seconds. 24 hour
mode should be used by setting the CAL24 bit in HIBCALCTL register.
The format of the calendar information is as follows:

■ TIME[31:26]: Year (0-64)

■ TIME[25:22]: Month

■ TIME[21:17]: Day of month

■ TIME[16:12]: Hours

■ TIME[11:6]: Minutes

■ TIME[5:0]: Seconds

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Register 28: HIB Tamper Log 1 (HIBTPLOG1), offset 0x4E4

Register 29: HIB Tamper Log 3 (HIBTPLOG3), offset 0x4EC
Register 30: HIB Tamper Log 5 (HIBTPLOG5), offset 0x4F4
Register 31: HIB Tamper Log 7 (HIBTPLOG7), offset 0x4FC
The HIB Tamper Log (HIBTPLOGn) odd registers capture the trigger information during a tamper
event. Up to four tamper logs can be stored. The HIBTPLOG registers are cleared when the TPCLR
bit is set to 1 in the HIBTPCTL register. The HIBTPLOG7 register contains to OR of all events after
the 3rd event is logged in HIBTPLOG5. The HIBTPLOG7 register is cleared on a Hibernation module
reset.

HIB Tamper Log 1 (HIBTPLOG1)

Base 0x400F.C000
Offset 0x4E4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved XOSC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TRIG3 TRIG2 TRIG1 TRIG0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 XOSC RO 0 Status of external 32.768-kHz oscillator

Value Description
0 Default
1 32.768-kHz oscillator has failed

15:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 TRIG3 RO 0 Status of TMPR[3] Trigger

Value Description
0 Default
1 A tamper event has been detected on TMPR[3]

2 TRIG2 RO 0 Status of TMPR[2] Trigger

Value Description
0 Default
1 A tamper event has been detected on TMPR[2]

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Bit/Field Name Type Reset Description

1 TRIG1 RO 0 Status of TMPR[1] Trigger

Value Description
0 Default
1 A tamper event has been detected on TMPR[1]

0 TRIG0 RO 0 Status of TMPR[0] Trigger

Value Description
0 Default
1 A tamper event has been detected on TMPR[0]

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Register 32: Hibernation Peripheral Properties (HIBPP) , offset 0xFC0

This register describes the features available within the Hibernation Module.

Hibernation Peripheral Properties (HIBPP)

Base 0x400F.C000
Offset 0xFC0
Type RO, reset 0x0000.0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TAMPER WAKENC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 TAMPER RO 0x1 Tamper Pin Presence

Value Description
0 Tamper module is not present.
1 Tamper module is present.

0 WAKENC RO 0x0 Wake Pin Presence

Value Description
0 WAKE pin is present.
1 WAKE pin is not part of the package pinout.

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Register 33: Hibernation Clock Control (HIBCC), offset 0xFC8

This register enables alternate clock sources.
Note: This register is in the system clock domain. Writes to this register do not require waiting for
the WRC bit of the HIBCTL register to be set.

Hibernation Clock Control (HIBCC)

Base 0x400F.C000
Offset 0xFC8
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SYSCLKEN

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 SYSCLKEN RW 0x0 RTCOSC to System Clock Enable

This bit RTCOSC clock to be sent to the system control for selection as
a possible system clock source. Default mode is disabled to support
low power modes.

Value Description
0 RTCOSC is not available as a system clock source.
1 RTCOSC is available for use as a system clock source.

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8 Internal Memory
The TM4C1294NCPDT microcontroller comes with 256 KB of bit-banded SRAM, internal ROM,
1024 KB of Flash memory, and 6KB of EEPROM.
The TM4C1294NCPDT microcontroller provides 1024 KB of on-chip Flash memory. The Flash
memory is configured as four banks of 16K x 128 bits (4 * 256 KB total) which are two-way
interleaved. Memory blocks can be marked as read-only or execute-only, providing different levels
of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of
those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can
only be read by the controller instruction fetch mechanism, protecting the contents of those blocks
from being read by either the controller or by a debugger.
The TM4C1294NCPDT microcontroller provides enhanced performance and power savings by
implementation of two sets of instruction prefetch buffers. Each prefetch buffer is 2 x 256 bits and
can be combined as a 4 x 256-bit prefetch buffer.
The EEPROM module provides a well-defined register interface to support accesses to the EEPROM
with both a random access style of read and write as well as a rolling or sequential access scheme.
A password model allows the application to lock one or more EEPROM blocks to control access on
16-word boundaries.

8.1 Block Diagram

Figure 8-1 on page 601 illustrates the internal memory and control structure . The dashed box in the
figure indicate registers residing in the System Control module.

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Figure 8-1. Internal Memory Block Diagram

EEPROM Control
EESIZE
EEBLOCK
EEOFFSET
EERDWR
EEPROM Array
EEDWRINC
EEDONE
EESUPP
EEUNLOCK
EEPROT
EEPASSn
EEINT
EEHIDE
EEDBGME
EEPROMPP

SPB

ROMSWMAP

Flash Control
FMA
FMD
FMC
FCRIS ROM
ICODE FCIM
CORTEX M4 FCMISC
DCODE FSIZE
FLASHPP
FLASHCONF
FLPEKEY
2x256-bit Prefetch
Buffer 0
DMA Control
FLASHDMASZ 2x256-bit Prefetch
FLASHDMAST Buffer 1
SPB
Flash Write 8-KB Sectors 8-KB Sectors
Bus Matrix Buffer Control
FMC2
DMA FWBVAL

SRAM Control
SSIZE

Flash Protection

FMPPEn

FWBn 8-KB Sectors 8-KB Sectors

FMPREn
(32 word write
buffers)
User Registers
BOOTCFG
SRAM USER_REGn
(four-way interleaved Flash Array
banks) USRPWRUP
(2-Way Interleaved)
Boot Registers
SCV
RVP

To Peripherals

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8.2 Functional Description

This section describes the functionality of the SRAM, ROM, Flash, and EEPROM memories.
Note: The μDMA has read-only access to flash (in Run Mode only).

8.2.1 SRAM
The internal system SRAM of the Tiva™ C Series devices is located at address 0x2000.0000 of the
device memory map. To reduce the number of time consuming read-modify-write (RMW) operations,
ARM provides bit-banding technology in the processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation. The bit-band base is located at address 0x2200.0000.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see “Bit-Banding” on page 109.
Note: The SRAM is implemented using four-way 32-bit wide interleaved SRAM banks (separate
SRAM arrays) which allow for increased speed between memory accesses. When using
interleaving, a write to one bank followed by a read of another bank can occur in successive
clock cycles without incurring any delay. However, a write access that is followed immediately
by a read access to the same bank incurs a stall of a single clock cycle.
The SRAM memory layout allows for multiple masters to access different SRAM banks
simultaneously. If two masters attempt to access the same SRAM bank, the master with
the higher priority gains access to the memory bus and the master with the lower priority is
stalled by one wait state. If four masters attempt to access the same SRAM bank, access
by the master with the lowest priority is delayed by three wait states. The CPU core always
has the highest priority for SRAM memory accesses.

8.2.2 ROM
The internal ROM of the Tiva™ C Series device is located at address 0x0100.0000 of the device
memory map. Detailed information on the ROM contents can be found in the Tiva™ C Series
TM4C129x ROM User’s Guide (literature number SPMU363).
The ROM contains the following components:

■ TivaWare™ Boot Loader and vector table

■ TivaWare Peripheral Driver Library (DriverLib) release for product-specific peripherals and
interfaces

■ Advanced Encryption Standard (AES) cryptography tables

■ Cyclic Redundancy Check (CRC) error detection functionality

The boot loader is used as an initial program loader (when the Flash location 0x0000.0004, the
reset vector location is all 1s (that is, erased state of Flash)) as well as an application-initiated

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firmware upgrade mechanism (by calling back to the boot loader). The Peripheral Driver Library
APIs in ROM can be called by applications, reducing Flash memory requirements and freeing the
Flash memory to be used for other purposes (such as additional features in the application). Advanced
Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government.
Cyclic Redundancy Check (CRC) is a technique to validate whether a block of data has the same
contents as when previously checked.
Note: CRC software program are available in TivaWare for backward-compatibility. A device that
has enhanced CRC integrated module should utilize this hardware for best performance.
Please refer to “Cyclical Redundancy Check (CRC)” on page 946 for more information.

8.2.2.1 Boot Configuration

After Power-On-Reset (POR) and device initialization occurs, the hardware loads the stack pointer
from either flash or ROM based on the presence of an application in flash and the state of the EN
bit in the BOOTCFG register. If the flash address 0x0000.0004 contains an erased word (value
0xFFFF.FFFF) or the EN bit is of the BOOTCFG register is clear, the stack pointer and reset vector
pointer are loaded from ROM at address 0x0100.0000 and 0x0100.0004, respectively. The boot
loader executes and configures the available boot slave interfaces and waits for an external memory
to load its software. The boot loader uses a simple packet interface to provide synchronous
communication with the device. The speed of the boot loader is determined by the internal oscillator
(PIOSC) frequency. The following serial interfaces can be used:

■ UART0
■ SSI0
■ I2C0
■ USB

If the check of the Flash at address 0x0000.0004 contains a valid reset vector value and the EN bit
in the BOOTCFG register is set, the stack pointer and