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Full Adder Simulation Code

This document contains the code for a Verilog simulation module (fulladder01sim) that is testing a full adder module (fulladder01). The simulation module instantiates the full adder module and applies different input combinations over time to test the output sums and carry outputs. It sets the inputs a, b, and c through an initial block and uses delays to step through the different test cases.

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Satyam Sharma
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143 views3 pages

Full Adder Simulation Code

This document contains the code for a Verilog simulation module (fulladder01sim) that is testing a full adder module (fulladder01). The simulation module instantiates the full adder module and applies different input combinations over time to test the output sums and carry outputs. It sets the inputs a, b, and c through an initial block and uses delays to step through the different test cases.

Uploaded by

Satyam Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/06/2018 [Link] PM
// Design Name:
// Module Name: fulladder01sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module fulladder01sim( );
reg a,b,c;
fulladder01 inst(a,b,c,s,c1);
initial
begin
a=0;
b=0;
c=0;
#20;
c=1;
#20;
b=1;
c=0;
#20;
c=1;
#20;
a=1;
b=0;
c=0;
#20;
c=1;
#20;
b=1;
c=0;
#20;
c=1;
end

`timescale 1ns / 1ps


//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/06/2018 [Link] PM
// Design Name:
// Module Name: fulladder01sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module fulladder01sim();
reg a,b,c;
fulladder01 inst(a,b,c,s,c1);
initial
begin
a=0;
b=0;
c=0;
#20;
c=1;
#20;
b=1;
c=0;
#20;
c=1;
#20;
a=1;
b=0;
c=0;
#20;
c=1;
#20;
b=1;
c=0;
#20;
c=1;
end
endmodule

endmodule

`timescale 1ns / 1ps


//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/06/2018 [Link] PM
// Design Name:
// Module Name: fulladder01
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module fulladder01(
input a,
input b,
input c,
output s,
output c1
);

assign s=a^b^c;
assign c1=(a&c)|(b&c);
endmodule

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