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VHDL Code for 4-Bit Shift
Register
May 1, 2014 by Admin
Contents [hide]
1 Shift Register
2 Parallel In – Parallel Out Shift Registers
3 VHDL code for Parallel In Parallel Out Shift Register
4 Serial In – Parallel Out Shift Registers
5 VHDL Code for Serial In Parallel Out Shift Register
6 Related
Shift Register Let's Chat? - Online
VHDL Code for shift register can be categorised in serial
in serial out shift register, serial in parallel out shift
register, parallel in parallel out shift register and parallel
in serial out shift register.
Parallel In – Parallel Out Shift Registers
For parallel in – parallel out shift registers, all data bits
appear on the parallel outputs immediately following the
simultaneous entry of the data bits. The following circuit
is a four-bit parallel in – parallel out shift register
constructed by D ip- ops.
The D’s are the parallel inputs and the Q’s are the parallel
outputs. Once the register is clocked, all the data at the D
inputs appear at the corresponding Q outputs
simultaneously.
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VHDL code for Parallel In Parallel Out Shift
Register
1 library ieee;
2 use ieee.std_logic_1164.all;
3
4 entity pipo is
5 port(
6 clk : in std_logic;
7 D: in std_logic_vector(3 downto 0)
8 Q: out std_logic_vector(3 downto 0
9 );
10 end pipo;
11
12 architecture arch of pipo is
13
14 begin
15
16 process (clk)
17 begin
18 if (CLK'event and CLK='1') then
19 Q <= D;
20 end if;
21 end process;
22
23 end arch;
Serial In – Parallel Out Shift Registers
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For Serial in – parallel out shift registers, all data bits
appear on the parallel outputs following the data bits
enters sequentially through each ip op. The following
circuit is a four-bit Serial in – parallel out shift register
constructed by D ip- ops.
VHDL Code for Serial In Parallel Out Shift
Register
1 library ieee;
2 use ieee.std_logic_1164.all;
3
4 entity sipo is
5 port(
6 clk, clear : in std_logic;
7 Input_Data: in std_logic;
8 Q: out std_logic_vector(3 downto 0
9 end sipo;
10
11 architecture arch of sipo is
12
13 begin Let's Chat? - Online
14
15 process (clk)
16 begin
17 if clear = '1' then
18 Q <= "0000";
19 elsif (CLK'event and CLK='1') then
20 Q(3 downto 1) <= Q(2 downto 0);
21 Q(0) <= Input_Data;
22 end if;
23 end process;
24 end arch;
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6 thoughts on “VHDL Code for 4-Bit Shift
Register”
hemanth
February 6, 2018 at 4:17 pm | Reply
q is a output, u made it as input it leads an error
rite?
Akbar
November 30, 2017 at 6:31 pm | Reply
What does it do exactly?
‘ Q(3 downto 1) <= Q(2 downto 0);'
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Admin
December 7, 2017 at 12:08 am | Reply
it shift content of the q by 1 bit.
Ms San San Naing
November 27, 2017 at 1:29 am | Reply
Very useful for beginners.
I really apreciate you.
Ms San San Naing
November 27, 2017 at 1:28 am | Reply
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Thank you so much. Its very useful for vhdl
beginners.
I really apreciate you.
Adam
November 3, 2017 at 5:41 pm | Reply
the example given for PIPO shift register is not
actually a shift register, its a storing element,
you’re just feeding the input to the output, no
bits have been shifted, please revise that!
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