ECE3002-VLSI SYSTEM DESIGN
SLOT:L53+54
TASK 1
Aishwarya Sriyapu Reddy -15BEC0717
V – I Characteristics of a NMOS transistor
Aim:
To plot and verify the V–I (Drain) characteristics of a NMOS transistor and
determine β.
CIRCUIT DIAGRAM:
Components details:
Components Library Cell Name View Name Instance
Name
NMOS gpdk090 nmos1V symbol NM0
Transistor
Vgs AnalogLib vdc symbol vgs
(D.C source)
Vds AnalogLib vdc symbol vds
(D.C source)
Ground AnalogLib gnd symbol gnd
Procedure:
1. Circuit/Schematic was designed
2. Vds was set with 1.2 V
3. Variable name “VGS” was assigned vgs
4. Check and saved without / after rectify any warnings and errors
5. ADE L was invoked for device simulation
6. DC analysis was chosen
7. “vds” was chosen as component, “dc” was selected as parameter for “x-axis” and appropriate
value assigned to minimum and maximum
8. Drain current (“Id”) was chosen as output
9. Proper value was assigned to variable “VGS”
10. VGS was selected in parametric analysis with suitable start value, stop value and step size.
11. Linear region were calculated from the V – I plot.
12. Channel length modulation parameter ( λ ) was determined then Saturation region β was
found.
WAVEFORM
Parametric analysis with Vgs=1.117V, 0.917V and 0.717V respectively
Current at Vds=1.2V and 1.1V
CALCULATIONS:
Case 1: Vgs=0.717 V
Case 2: Vgs=0.917 V
Case 3: Vgs= 1.117 V
Vt= 0.13V
Vds(sat) = Vgs-Vt
= 1.117-(0.13) =0.987
For Vds > 0.987, it is in saturation
Take Vds as 1.1 and 1.2
So, Vds = 1.1 , Vgs = 1.117 , Id1 = 95.771uA
Vds = 1.2 , Vgs =1.117 , Id2 = 98.061uA
(Id1)/(Id2)=(1+ λVds1)/(1+ λVds2)
(95.771)/(98.061) = (1+(1) λ)/(1+(1.2) λ)
0.9766+1.1719 λ = 1+ λ
0.1372 λ = 0.0523
so, λ = 0.3811 (1/V)
Saturation region:
At Vds= 1.1 and Vgs = 1.117 , Id = 95.771uA
Id (Vgs Vtn ) 2 (1 Vds )
2
Now, β = (95.771*2)/(0.9741*1.45732) * 10−6
,β = 138.92* 10−6 A/V2
K1 = β*L/W = 138.92*10−6 * (100/120)
K1 = 115.76 *10−6 A/V2
At, Vds= 1.1 and Vgs = 0.917 , Id = 73.9075uA (practical)
Id (Vgs Vtn ) 2 (1 Vds )
2
Id = (138.92 * 10−6 /2)*(0.917-0.13)^2 *(1+(0.3811*1.1))
Id = 76.189uA
Therefore, Theoritical value, Id = 76.189uuA
Practical value, Id = 73.9075uA
At, Vds= 1.1 and Vgs = 0.717 , Id = 50.848uA (practical)
Id (Vgs Vtn ) 2 (1 Vds )
2
Id = (138.92 * 10−6 /2)*(0.717-0.13)^2 *(1+(0.3811*1.1))
Id = 48.554uA
Therefore, Theoritical value, Id = 48.554uA
Practical value, Id = 50.848uA
INFERENCE: We observe that the theoretical and practical values are almost the same and
V – I Drain Characteristics of a nmos was verified and β was determined.
Transfer Characteristics of a NMOS transistor
Aim:
To plot and verify the Transfer characteristics of a NMOS transistor.
CIRCUIT DIAGRAM:
Components details:
Components Library Cell Name View Name Instance
Name
NMOS gpdk090 nmos1V symbol NM0
Transistor
Vgs AnalogLib vdc symbol vgs
(D.C source)
Vds AnalogLib vdc symbol vds
(D.C source)
Ground AnalogLib gnd symbol gnd
Procedure:
1. Circuit/Schematic was designed
2. Vgs was set with 1.2 V
3. Variable name “VDS” was assigned vds
4. Check and saved without / after rectify any warnings and errors
5. ADE L was invoked for device simulation
6. DC analysis was chosen
7. “vgs” was chosen as component, “dc” was selected as parameter for “x-axis” and appropriate
value assigned to minimum and maximum
8. Drain current (“Id”) was chosen as output
9. Proper value was assigned to variable “VDS”
10. VDS was selected in parametric analysis with suitable start value, stop value and step size.
11. Linear region were calculated from the V – I plot.
12. Vtn was assumed as 0.13V
14. Drain current was calculated theoretically and verified with simulation.
Waveform:
Vgs versus Ids for Vds=0.717V,0.917V and 1.117V respectively
Infernce:
Transfer characteristics of a nmos was verified.
V – I Characteristics of a PMOS transistor
Aim:
To plot and verify the V–I (Drain) characteristics of a PMOS transistor and determine β.
CIRCUIT DIAGRAM:
Components details:
Components Library Cell Name View Name Instance
Name
NMOS gpdk090 nmos1V symbol NM0
Transistor
Vgs AnalogLib vdc symbol Vgs
(D.C source)
Vds AnalogLib vdc symbol Vds
(D.C source)
Ground AnalogLib gnd symbol Gnd
Procedure:
1. Circuit/Schematic was designed
2. Vds was set with 1.2 V
3. Variable name “VGS” was assigned vgs
4. Check and saved without / after rectify any warnings and errors
5. ADE L was invoked for device simulation
6. DC analysis was chosen
7. “vds” was chosen as component, “dc” was selected as parameter for “x-axis” and appropriate
value assigned to minimum and maximum
8. Drain current (“Id”) was chosen as output
9. Proper value was assigned to variable “VGS”
10. VGS was selected in parametric analysis with suitable start value, stop value and step size.
11. Linear region were calculated from the V – I plot.
12. Channel length modulation parameter ( λ ) was determined then Saturation region β was
found.
Waveform
Vgs versus Ids for Vds=-0.717V,-0.917V,-1.117V respectively
Calculation
a) Case 1: Vgs=-0.717V
Case 2: Vgs=-0.917 V
Case 3: Vgs=-1.117 V
Vgs = -0.717, -0.917, -1.117
Vt= -0.13V
Vds(sat) = Vgs-Vt
= -1.117-(-0.13) = -0.987
For Vds < -0.987, it is in saturation
Take Vds as -1.0 and -1.1
So, Vds = -1.0 , Vgs = -1.117 , Id1 = -40.84uA
Vds = -1.1 , Vgs = -1.117 , Id2 = -41.945uA
(Id1)/(Id2)=(1+ λVds1)/(1+ λVds2)
(-40.84)/(-41.945) = (1+(-1) λ)/(1+(-1.2) λ)
0.9736-1.16832 λ = 1- λ
-0.168 λ = 0.0264
so, λ = -0.35967 (1/V)
Saturation region:
At Vds= -1.1 and Vgs = -1.117 , Id = -41.945uA
Id (Vgs Vtn ) 2 (1 Vds )
2
Now, β = (-41.945*2)/(0.9741*1.395637) * 10−6
β = -60.6544 * 10−6 A/V2
K1 = β*L/W =-60.6544*10−6 * (100/120)
K1 = -50.545 *10−6 A/V2
At, Vds= -1.1 and Vgs = -0.917 , Id = -30.206uA (practical)
Id (Vgs Vtn ) 2 (1 Vds )
2
Id = (-60.6544 * 10−6 /2)*(-0.917+0.13)^2 *(1+(-0.35967*-1.1))
Id = -27.54uA
Therefore, Theoritical value, Id = -27.54uA
Practical value, Id = -30.206uA
At, Vds= -1.1 and Vgs = -0.717 , Id = -15.864uA (practical)
Id = (-60.6544 * 10−6 /2)*(-0.717+0.13)^2 *(1+(-0.35967*-1.1))
Id = -14.3824uA
Therefore, Theoritical value, Id = -13.987uA
Practical value, Id = -15.864u
INFERENCE: It is observed that from the above the theoretical results and the results obtained
using simulation are nearly the same.
Transfer Characteristics of a PMOS transistor
Aim:
To plot and verify the Transfer characteristics of a PMOS transistor.
CIRCUIT DIAGRAM:
Components details:
Components Library Cell Name View Name Instance
Name
NMOS gpdk090 nmos1V symbol NM0
Transistor
Vgs AnalogLib vdc symbol Vgs
(D.C source)
Vds AnalogLib vdc symbol Vds
(D.C source)
Ground AnalogLib gnd symbol Gnd
Procedure:
1. Circuit/Schematic was designed
2. Vgs was set with 1.2 V
3. Variable name “VDS” was assigned vds
4. Check and saved without / after rectify any warnings and errors
5. ADE L was invoked for device simulation
6. DC analysis was chosen
7. “vgs” was chosen as component, “dc” was selected as parameter for “x-axis” and appropriate
value assigned to minimum and maximum
8. Drain current (“Id”) was chosen as output
9. Proper value was assigned to variable “VDS”
10. VDS was selected in parametric analysis with suitable start value, stop value and step size.
11. Linear region were calculated from the V – I plot.
12. Vtn was assumed as 0.13V
14. Drain current was calculated theoretically and verified with simulation.
Waveforms:
Inference:
Transfer characteristics of a pmos was verified.
