EE371 Spring 1999
Static Random Access Memories
(SRAM)
Birdy Amrutur
[email protected]
EE371 Spring 1999
Key features of SRAMs
Holds data statically:
As long as power is supplied to the chip, the data
remains.
Data randomly accessible:
ReadData = Memory[ Address ]
Memory[ Address ] = WriteData
EE371 Spring 1999
SRAMs Used as:
Embedded memory, e.g.:
First and second level caches in processors
Data buffers in various DSP chips
Standalone SRAMs:
Caches in computer systems
Main memory in low power applications
Typical sizes:
Embedded: upto 1Mbit
Standalone: upto 16Mbit
EE371 Spring 1999
The system level view of SRAMs
Asynchronous interface tAC
tAA
Ai Aj address
address
data in
M [ 0 .. 2n ] data out r/w
r/w
M [ Ai ] data out
Used for stand alone SRAM chips
data in
Synchronous interface tsu tcyc
clk
address Ai Aj address
data in
M [ 0 .. 2n ] data out r/w
r/w
clk
M [ Ai ] data out
Used for embedded and standalone SRAMs data in
EE371 Spring 1999
SRAM Architecture
2m
Row decoder
word line
bitline
2n
Address input n
Column Mux
Column decoder
Sense en
Sense amplifier
Read enable Write en
Read-write control
Write driver
Data in Data out
EE371 Spring 1999
CMOS SRAM cell
Vdd
b b
wp wp
wa wa
wn wn
wordline
a) Static cell
b) 6T CMOS cell
c) 4T poly-R cell d) 6T poly-PMOS cell
EE371 Spring 1999
Reading a cell
b
b
0 wl
1
a b,b
a
Cb v
Icell a
wl Icell *
v =
Cb
Sense Amplifier
EE371 Spring 1999
Writing a cell
b
b
wl
0 1 b
a
a b
Cb a
Icell
a
wl
D=0 D=1
write
EE371 Spring 1999
Bitline precharge and load
Pre Pre Pre
Important to
equalize bitline
voltage before
reads
cell cell cell
wl wl wl
b b
b,b b,b b,b vdd
vdd -vtn
Pre
Pre v
Pre v wl
wl wl
Precharged to Vdd . Bitline voltage clamped during reads. Precharge to an Nmos threshold
Precharge shut off during reads below supply
and writes Useful with current mirror
Use with latch style sense amps Use with current sense amps sense amps
(Cant operate with low supply)
EE371 Spring 1999
Sense amplifiers
Need to amplify input bitline swing of ~100mV to full digital levels.
b b
b b
Sense clock
Sense enable
Current mirror amplifier Latch type amplifier
EE371 Spring 1999
Decoders
1 16 Logically an n-input AND function.
16 1 word driver
Enables the Random Access portion
CL of RAMs.
Row decoder in the critical path of the
SRAM access.
Could contribute upto 40% of the delay
and power
256
Large decoders implemented
hierarchically.
A0A1A2A3
4 to 16 predecoder
A0 A1 A3
An 8 to 256 decoder
EE371 Spring 1999
Sram Partitioning
Divided word line Architecture
block
select bitlines
global local
word line
word line
address
local senseamp
IO lines
global sense
amp
dout din
Use higher level metal for global word lines
EE371 Spring 1999
Bitline partitioning
256
Wordline drivers
Wordline drivers
512
256
sense amps Global
Bitlines
Single Level Mux Two Level Mux
Use higher level metal for global bitlines
EE371 Spring 1999
Partioning summary
Partioning involves a trade off between area, power and speed
For high speed designs, use short blocks(e.g 64 rows x 128 columns )
Keep local bitline heights small
For low power designs use tall narrow blocks (e.g 256 rows x 64 columns)
Keep the number of columns same as the access width to minimize wasted power
EE371 Spring 1999
CMOS SRAM cell design-1
Vdd
b b Problem: Find wa, wd, wp such that
wp wp
1) minimize cell area
wa wa 2) obtain good read and write cell margins
a a 3) good soft error immunity
4) good cell read current
wd wd
in that order
wl
Conflicting goals!
Vdd a
Vdd
wp Static Noise Margin
wa
a
a
wd
Vdd
a
EE371 Spring 1999
CMOS SRAM cell design-2
Read Stability
Vdd
b Usually Cbit is very big compared to internal
b node capacitances
wp wp
wa Cell will flip if the 0 node bounces high
wa enough to cause the 1 node to discharge
a (=0) (1=) a
Simulate for worst case scenario with threshold
Cbit and size mismatches in the cell which aids in
wd wd
flipping
To obtain good stability :
wl
= wd * ( Vdd - Vtn ) 2 = wd > 2.5
wa * ( Vdd - Vtn ) 2 wa
Vdd
Vdd Vdd
wp wp
wl
wa*1.1 wa
b,b
a a
+ a
- wd + - wd*1.1
Vt Vt a
Vdd
Dynamic read noise margin
EE371 Spring 1999
CMOS SRAM cell design-3
Vdd
Write Stability
Vdd Cell is written by discharging the 1
node low. This causes the 0 node to
wp wp charge up.
wa wa*0.9
Need to ensure that
a ( = 0) (1=) a
wa * n*(Vdd-Vtn)2 > wp*p*(Vdd-Vtp)2
-
wd*1.1 + wd +
-
Vt Vt Hence use minimum sized pMOS
Gnd load devices.
Vdd
wl
b
b
a
a
Dynamic write noise margin
EE371 Spring 1999
CMOS SRAM cell design-4
Soft Error Immunity
Vdd
particle can create electron-hole pairs in
b the channel of a off transistor.
b
This causes the off transistor to leak away
a a some of the stored charge.
(=0) (1=) Two solutions to the problem:
Cbit
Increase stored charge ( > 20fC ) - use larger
transistors (more capacitance), bigger voltages
Use system level solution like redundancy
bits for error detection and correction
- particle (He2+)
a b b a Cell Layout
Simple layout in MOSIS design rule. Cell area
wp metal 2 is 66.5 m2 (10642) in 0.5m CMOS
metal 1
Advanced processes with tighter rules + clever
poly non-manhattan (non-right angle) layouts
wn reduce cell area significantly
diffusion
(typically ~6502)
contact
wl
Poly-R and poly-PMOS cells have 2-3 times
smaller area as the load devices can be laid
wa out on top of the nMOS transistors
