Write a verilog code to swap contents of two registers with and without a temporary register?
With temp reg ;
always @ (posedge clock)
begin
temp=b;
b=a;
a=temp;
end
Without temp reg;
always @ (posedge clock)
begin
a <= b;
b <= a;
end
Difference between blocking and non-blocking?(Verilog interview questions that is most commonly
asked)
The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking.
The two are distinguished by the = and <= assignment operators. The blocking assignment statement (=
operator) acts much like in traditional programming languages. The whole statement is done before
control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand
sides for the current time unit and assigns the left-hand sides at the end of the time unit. For example,
the following Verilog program
// testing blocking and non-blocking assignment
module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;
$display("Blocking: A= %b B= %b", A, B ); A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule
produces the following output:
Blocking: A= 00000100 B= 00000101
Non-blocking: A= 00000100 B= 00000100
The effect is for all the non-blocking assignments to use the old values of the variables at the beginning
of the current time unit and to assign the registers new values at the end of the current time unit. This
reflects how register transfers occur in some hardware systems.
blocking procedural assignment is used for combinational logic and non-blocking procedural assignment
for sequential
Tell me about verilog file I/O?
OPEN A FILE
integer file;
file = $fopenr("filename");
file = $fopenw("filename");
file = $fopena("filename");
The function $fopenr opens an existing file for reading. $fopenw opens a new file for writing, and
$fopena opens a new file for writing where any data will be appended to the end of the file. The file
name can be either a quoted string or a reg holding the file name. If the file was successfully opened, it
returns an integer containing the file number (1..MAX_FILES) or NULL (0) if there was an error. Note that
these functions are not the same as the built-in system function $fopen which opens a file for writing by
$fdisplay. The files are opened in C with 'rb', 'wb', and 'ab' which allows reading and writing binary data
on the PC. The 'b' is ignored on Unix.
CLOSE A FILE
integer file, r;
r = $fcloser(file);
r = $fclosew(file);
The function $fcloser closes a file for input. $fclosew closes a file for output. It returns EOF if there was
an error, otherwise 0. Note that these are not the same as $fclose which closes files for writing.
3) Difference between task and function?
Function:
A function is unable to enable a task however functions can enable other functions.
A function will carry out its required duty in zero simulation time. ( The program time will not be
incremented during the function routine)
Within a function, no event, delay or timing control statements are permitted
In the invocation of a function their must be at least one argument to be passed.
Functions will only return a single value and can not use either output or inout statements.
Tasks:
Tasks are capable of enabling a function as well as enabling other versions of a Task
Tasks also run with a zero simulation however they can if required be executed in a non zero simulation
time.
Tasks are allowed to contain any of these statements.
A task is allowed to use zero or more arguments which are of type output, input or inout.
A Task is unable to return a value but has the facility to pass multiple values via the output and inout
statements .
4) Difference between inter statement and intra statement delay?
//define register variables
reg a, b, c;
//intra assignment delays
initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end
//Equivalent method with temporary variables and regular delay control
initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end
5) What is delta simulation time?
6) Difference between $monitor,$display & $strobe?
These commands have the same syntax, and display text on the screen during simulation. They are
much less convenient than waveform display tools like cwaves?. $display and $strobe display once every
time they are executed, whereas $monitor displays every time one of its parameters changes.
The difference between $display and $strobe is that $strobe displays the parameters at the very end of
the current simulation time unit rather than exactly where it is executed. The format string is like that in
C/C++, and may contain format characters. Format characters include %d (decimal), %h (hexadecimal),
%b (binary), %c (character), %s (string) and %t (time), %m (hierarchy level). %5d, %5b etc. would give
exactly 5 spaces for the number instead of the space needed. Append b, h, o to the task name to change
default format to binary, octal or hexadecimal.
Syntax:
$display (format_string, par_1, par_2, ... );
$strobe (format_string, par_1, par_2, ... );
$monitor (format_string, par_1, par_2, ... );
7) What is difference between Verilog full case and parallel case?
A "full" case statement is a case statement in which all possible case-expression binary patterns can be
matched to a case item or to a case default. If a case statement does not include a case default and if it
is possible to find a binary case expression that does not match any of the defined case items, the case
statement is not "full."
A "parallel" case statement is a case statement in which it is only possible to match a case expression to
one and only one case item. If it is possible to find a case expression that would match more than one
case item, the matching case items are called "overlapping" case items and the case statement is not
"parallel."
8) What is meant by inferring latches,how to avoid it?
Consider the following :
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
endcase
in a case statement if all the possible combinations are not compared and default is also not specified
like in example above a latch will be inferred ,a latch is inferred because to reproduce the previous value
when unknown branch is specified.
For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing a latch is
inferred.
The same may be observed in IF statement in case an ELSE IF is not specified.
To avoid inferring latches make sure that all the cases are mentioned if not default condition is
provided.
9) Tell me how blocking and non blocking statements get executed?
Execution of blocking assignments can be viewed as a one-step process:
1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the
blocking assignment without interruption from any other Verilog statement. A blocking assignment
"blocks" trailing assignments in the same always block from occurring until after the current assignment
has been completed
Execution of nonblocking assignments can be viewed as a two-step process:
1. Evaluate the RHS of nonblocking statements at the beginning of the time step. 2. Update the LHS of
nonblocking statements at the end of the time step.
10) Variable and signal which will be Updated first?
Signals
11) What is sensitivity list?
The sensitivity list indicates that when a change occurs to any one of elements in the list change,
beginend statement inside that always block will get executed.
12) In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes,
why?
Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it
will result in pre and post synthesis mismatch.
13) Tell me structure of Verilog code you follow?
A good template for your Verilog file is shown below.
// timescale directive tells the simulator the base units and precision of the simulation
`timescale 1 ns / 10 ps
module name (input and outputs);
// parameter declarations
parameter parameter_name = parameter value;
// Input output declarations
input in1;
input in2; // single bit inputs
output [msb:lsb] out; // a bus output
// internal signal register type declaration - register types (only assigned within always statements). reg
register variable 1;
reg [msb:lsb] register variable 2;
// internal signal. net type declaration - (only assigned outside always statements) wire net variable 1;
// hierarchy - instantiating another module
reference name instance name (
.pin1 (net1),
.pin2 (net2),
.
.pinn (netn)
);
// synchronous procedures
always @ (posedge clock)
begin
.
end
// combinatinal procedures
always @ (signal1 or signal2 or signal3)
begin
.
end
assign net variable = combinational logic;
endmodule
14) Difference between Verilog and vhdl?
Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be
separately compiled if so desired. However, it is good design practice to keep each design unit in it's own
system file in which case separate compilation should not be an issue.
Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of
speeding up simulation, but has not changed the original nature of the language. As a result care must
be taken with both the compilation order of code written in a single file and the compilation order of
multiple files. Simulation results can change by simply changing the order of compilation.
Data types
VHDL. A multitude of language or user defined data types can be used. This may mean dedicated
conversion functions are needed to convert objects from one type to another. The choice of which data
types to use should be considered wisely, especially enumerated (abstract) data types. This will make
models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the
code. VHDL may be preferred because it allows a multitude of language or user defined data types to be
used.
Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared
towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data
types used in a Verilog model are defined by the Verilog language and not by the user. There are net
data types, for example wire, and a register data type called reg. A model with a signal whose type is
one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects,
that is signals, of type reg hold their value over simulation delta cycles and should not be confused with
the modeling of a hardware register. Verilog may be preferred because of it's simplicity.
Design reusability
VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-
unit that wishes to use them.
Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must
be defined in the module. To make functions and procedures generally accessible from different module
statements the functions and procedures must be placed in a separate system file and included using
the `include compiler directive.
15) What are different styles of Verilog coding I mean gate-level,continuous level and others explain
in detail?
16) Can you tell me some of system tasks and their purpose?
$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.
The most useful of these is $display.This can be used for displaying strings, expression or values of
variables.
Here are some examples of usage.
$display("Hello oni");
--- output: Hello oni
$display($time) // current simulation time.
--- output: 460
counter = 4'b10;
$display(" The count is %b", counter);
--- output: The count is 0010
$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode
where the
user can enter commands; $finish exits the simulator back to the operating system
17) Can you list out some of enhancements in Verilog 2001?
In earlier version of Verilog ,we use 'or' to specify more than one element in sensitivity list . In Verilog
2001, we can use comma as shown in the example below.
// Verilog 2k example for usage of comma
always @ (i1,i2,i3,i4)
Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo
logics . This removes typo mistakes and thus avoids simulation and synthesis mismatches,
Verilog 2001 allows port direction and data type in the port list of modules as shown in the example
below
module memory (
input r,
input wr,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);
18)Write a Verilog code for synchronous and asynchronous reset?
Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk
eg:
always @ (posedge clk )
begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in sensitivity list.
Eg
Always @(posedge clock or posedge reset)
begin
if (reset)
. . . end
19) What is pli?why is it used?
Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog programs with
programs written in C language. It also provides mechanism to access internal databases of the
simulator from the C program.
PLI is used for implementing system calls which would have been hard to do otherwise (or impossible)
using Verilog syntax. Or, in other words, you can take advantage of both the paradigms - parallel and
hardware related features of Verilog and sequential flow of C - using PLI.
20) There is a triangle and on it there are 3 ants one on each corner and are free to move along sides
of triangle what is probability that they will collide?
Ants can move only along edges of triangle in either of direction, lets say one is represented by 1 and
another by 0, since there are 3 sides eight combinations are possible, when all ants are going in same
direction they wont collide that is 111 or 000 so probability of not collision is 2/8=1/4 or collision
probability is 6/8=3/4
Verilog interview Questions
How to write FSM is verilog?
there r mainly 4 ways 2 write fsm code
1) using 1 process where all input decoder, present state, and output decoder r combine in one process.
2) using 2 process where all comb ckt and sequential ckt separated in different process
3) using 2 process where input decoder and persent state r combine and output decoder seperated in
other process
4) using 3 process where all three, input decoder, present state and output decoder r separated in 3
process.
Verilog interview Questions
21)What is difference between freeze deposit and force?
$deposit(variable, value);
This system task sets a Verilog register or net to the specified value. variable is the
register or net to be changed; value is the new value for the register or net. The value
remains until there is a subsequent driver transaction or another $deposit task for the
same register or net. This system task operates identically to the ModelSim
force -deposit command.
The force command has -freeze, -drive, and -deposit options. When none of these is
specified, then -freeze is assumed for unresolved signals and -drive is assumed for resolved
signals. This is designed to provide compatibility with force files. But if you prefer -freeze
as the default for both resolved and unresolved signals.
Verilog interview Questions
22)Will case infer priority register if yes how give an example?
yes case can infer priority register depending on coding style
reg r;
// Priority encoded mux,
always @ (a or b or c or select2)
begin
r = c;
case (select2)
2'b00: r = a;
2'b01: r = b;
endcase
end
Verilog interview Questions
23)Casex,z difference,which is preferable,why?
CASEZ :
Special version of the case statement which uses a Z logic value to represent don't-care bits. CASEX :
Special version of the case statement which uses Z or X logic values to represent don't-care bits.
CASEZ should be used for case statements with wildcard dont cares, otherwise use of CASE is required;
CASEX should never be used.
This is because:
Dont cares are not allowed in the "case" statement. Therefore casex or casez are required. Casex will
automatically match any x or z with anything in the case statement. Casez will only match zs -- xs
require an absolute match.
Verilog interview Questions
24)Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
This is a tricky one! Verilog scheduling semantics basically imply a
four-level deep queue for the current simulation time:
1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).
Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue. Only events in the active queue are
completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at
the value of a in the next sim cycle, it would show 1.
25) What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;
#5 a = b; Wait five time units before doing the action for "a = b;".
a = #5 b; The value of b is calculated and stored in an internal temp register,After five time units, assign
this stored value to a.
26)What is the difference between:
c = foo ? a : b;
and
if (foo) c = a;
else c = b;
The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get
c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.
27)What are Intertial and Transport Delays ??
28)What does `timescale 1 ns/ 1 ps signify in a verilog code?
'timescale directive is a compiler directive.It is used to measure simulation time or delay time. Usage :
`timescale / reference_time_unit : Specifies the unit of measurement for times and delays.
time_precision: specifies the precision to which the delays are rounded off.
29) What is the difference between === and == ?
output of "==" can be 1, 0 or X.
output of "===" can only be 0 or 1.
When you are comparing 2 nos using "==" and if one/both the numbers have one or more bits as "x"
then the output would be "X" . But if use "===" outpout would be 0 or 1.
e.g A = 3'b1x0
B = 3'b10x
A == B will give X as output.
A === B will give 0 as output.
"==" is used for comparison of only 1's and 0's .It can't compare Xs. If any bit of the input is X output will
be X
"===" is used for comparison of X also.
30)How to generate sine wav using verilog coding style?
A: The easiest and efficient way to generate sine wave is using CORDIC Algorithm.
31) What is the difference between wire and reg?
Net types: (wire,tri)Physical connection between structural elements. Value assigned by a continuous
assignment or a gate output. Register type: (reg, integer, time, real, real time) represents abstract data
storage element. Assigned values only within an always statement or an initial statement. The main
difference between wire and reg is wire cannot hold (store) the value when there no connection
between a and b like a->b, if there is no connection in a and b, wire loose value. But reg can hold the
value even if there in no connection. Default values:wire is Z,reg is x.
32 )How do you implement the bi-directional ports in Verilog HDL?
module bidirec (oe, clk, inp, outp, bidir);
// Port Declaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;
// Always Construct
always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end
endmodule
34)what is verilog case (1) ?
wire [3:0] x;
always @(...) begin
case (1'b1)
x[0]: SOMETHING1;
x[1]: SOMETHING2;
x[2]: SOMETHING3;
x[3]: SOMETHING4;
endcase
end
The case statement walks down the list of cases and executes the first one that matches. So here, if the
lowest 1-bit of x is bit 2, then something3 is the statement that will get executed (or selected by the
logic).
35) Why is it that "if (2'b01 & 2'b10)..." doesn't run the true case?
This is a popular coding error. You used the bit wise AND operator (&) where you meant to use the
logical AND operator (&&).
36)What are Different types of Verilog Simulators ?
There are mainly two types of simulators available.
Event Driven
Cycle Based
Event-based Simulator:
This Digital Logic Simulation method sacrifices performance for rich functionality: every active signal is
calculated for every device it propagates through during a clock cycle. Full Event-based simulators
support 4-28 states; simulation of Behavioral HDL, RTL HDL, gate, and transistor representations; full
timing calculations for all devices; and the full HDL standard. Event-based simulators are like a Swiss
Army knife with many different features but none are particularly fast.
Cycle Based Simulator:
This is a Digital Logic Simulation method that eliminates unnecessary calculations to achieve huge
performance gains in verifying Boolean logic:
1.) Results are only examined at the end of every clock cycle; and
2.) The digital logic is the only part of the design simulated (no timing calculations). By limiting the
calculations, Cycle based Simulators can provide huge increases in performance over conventional
Event-based simulators.
Cycle based simulators are more like a high speed electric carving knife in comparison because they
focus on a subset of the biggest problem: logic verification.
Cycle based simulators are almost invariably used along with Static Timing verifier to compensate for the
lost timing information coverage.
37)What is Constrained-Random Verification ?
Introduction
As ASIC and system-on-chip (SoC) designs continue to increase in size and complexity, there is an equal
or greater increase in the size of the verification effort required to achieve functional coverage goals.
This has created a trend in RTL verification techniques to employ constrained-random verification, which
shifts the emphasis from hand-authored tests to utilization of compute resources. With the
corresponding emergence of faster, more complex bus standards to handle the massive volume of data
traffic there has also been a renewed significance for verification IP to speed the time taken to develop
advanced testbench environments that include randomization of bus traffic.
Directed-Test Methodology
Building a directed verification environment with a comprehensive set of directed tests is extremely
time-consuming and difficult. Since directed tests only cover conditions that have been anticipated by
the verification team, they do a poor job of covering corner cases. This can lead to costly re-spins or,
worse still, missed market windows.
Traditionally verification IP works in a directed-test environment by acting on specific testbench
commands such as read, write or burst to generate transactions for whichever protocol is being tested.
This directed traffic is used to verify that an interface behaves as expected in response to valid
transactions and error conditions. The drawback is that, in this directed methodology, the task of writing
the command code and checking the responses across the full breadth of a protocol is an overwhelming
task. The verification team frequently runs out of time before a mandated tape-out date, leading to
poorly tested interfaces. However, the bigger issue is that directed tests only test for predicted behavior
and it is typically the unforeseen that trips up design teams and leads to extremely costly bugs found in
silicon.
Constrained-Random Verification Methodology
The advent of constrained-random verification gives verification engineers an effective method to
achieve coverage goals faster and also help find corner-case problems. It shifts the emphasis from
writing an enormous number of directed tests to writing a smaller set of constrained-random scenarios
that let the compute resources do the work. Coverage goals are achieved not by the sheer weight of
manual labor required to hand-write directed tests but by the number of processors that can be utilized
to run random seeds. This significantly reduces the time required to achieve the coverage goals.
Scoreboards are used to verify that data has successfully reached its destination, while monitors snoop
the interfaces to provide coverage information. New or revised constraints focus verification on the
uncovered parts of the design under test. As verification progresses, the simulation tool identifies the
best seeds, which are then retained as regression tests to create a set of scenarios, constraints, and
seeds that provide high coverage of the design.
1. How are blocking and non-blocking statements executed?
Answer
In a blocking statement, the RHS will be evaluated and the LHS will be then updated, without
interruption from any other Verilog statement. A blocking statement "blocks" trailing statements.
In a non-blocking statement, RHS will be evaluated at the beginning of the time step. Then the
LHS will be updated at the end of the time step.
2. How do you model a synchronous and asynchronous reset in Verilog?
Answer
Synchronous reset:
always @(posedge clk)
begin
--
if(reset)
--
end
Asynchronous reset:
always @(posedge clk or posedge reset)
begin
--
if(reset)
--
end
The logic is very simple: In asynchronous reset, the always block will invoked at positive edge
of the reset signal, irrespective of clock's value.
3. What happens if there is connecting wires width mismatch?
Answer
For example there are two signals rhs[7:0], and lhs[15:0]. If we do rhs = lhs. Then it is equivalent
to rhs = lhs[7:0]. Assignment starts from LSBs of the signals, and ends at the MSB of smaller
width signal.
4. What are different options that can be used with $display statement in Verilog?
Answer
%b or %B - Binary.
%c or %C - ASCII character.
%d or %D - Decimal.
%h or %H - Hexadecimal.
%m or %M - Hierarchical name.
%o or %O - Octal.
%s or %S - String.
%t or %T - Time.
%v or %V - Net signal strength.
6. Should we include all the inputs of a combinational circuit in the sensitivity list? Give reason.
Answer
Yes, in a combinational circuit all the inputs should be included in the sensitivity list other wise
it will result in a synthesis error.
7. Give 10 commonly used Verilog keywords.
Answer
always, and, assign, begin, case, default, else, end, module, endmodule, reg, net, etc.
Click here for the complete list.
8. Is it possible to optimize a Verilog code such that we can achieve low power design?
Answer
9. How does the following code work?
wire [3:0] a;
always @(*)
begin
case (1'b1)
a[0]: $display("Its a[0]");
a[1]: $display("Its a[1]");
a[2]: $display("Its a[2]");
a[3]: $display("Its a[3]");
default: $display("Its default")
endcase
end
Answer
The case checks a[0] to a[3], if any one of the is 1'b1, then the first appearing 1'b1 will be
executed. suppose a[0] = 0, a[1] = 1, a[2] = 1, and a[3] = 0,then Its a[1] will be displayed. If all
are zeros then Its default, will be displayed.
10. Which is updated first: signal or variable?
Answer
Signal.
5. Give the precedence order of the operators in Verilog.
Answer
Operator precedence
