Design Vision

User Guide
Version U-2003.03, March 2003

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Design Vision User Guide, vU-2003.03

ii
Contents

What’s New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii

About This User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi

1. Introduction to Design Vision

Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Supported Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Design Vision and Other Synopsys Products . . . . . . . . . . . . . . . . . 1-7

2. Before You Start

The Design Vision Documentation Set . . . . . . . . . . . . . . . . . . . . . . 2-2
Design Compiler Tutorial Using Design Vision. . . . . . . . . . . . . . 2-2

iii
 Design Vision User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Design Vision Online Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Setup Files for Design Vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Starting and Exiting the Graphical User Interface . . . . . . . . . . . . . . 2-7
Exploring the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . 2-9
Changing the Appearance of Schematics . . . . . . . . . . . . . . . . . . . . 2-13
Using Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

3. Performing Basic Tasks

Specifying Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Reading In Your Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Setting the Current Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Defining the Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Setting Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Setting Design Rule Constraints . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Setting Optimization Constraints . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Saving the Design Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Working With Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Generating Reports for Selected Objects . . . . . . . . . . . . . . . . . 3-10
Printing Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

iv
4. Solving Timing Problems
Before You Analyze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Creating a Timing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Choosing a Strategy for Timing Closure . . . . . . . . . . . . . . . . . . . . . 4-4
Assessing the Relative Size of Your Timing Violations . . . . . . . 4-4
When Timing Violations Are Small. . . . . . . . . . . . . . . . . . . . . . . 4-5
Working Globally to Fix Small Violations . . . . . . . . . . . . . . . 4-6
Working Locally to Fix Small Violations . . . . . . . . . . . . . . . . 4-6
When Timing Violations Are Medium Size. . . . . . . . . . . . . . . . . 4-8
When Timing Violations Are Large . . . . . . . . . . . . . . . . . . . . . . 4-11

Index

v
vi
Figures

Figure 2-1 The Design Vision Window . . . . . . . . . . . . . . . . . . . . . . . 2-9

Figure 4-1 Endpoint Slack Histogram. . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-2 Design With Small Timing Violations . . . . . . . . . . . . . . . 4-5
Figure 4-3 Design With Medium Timing Violations . . . . . . . . . . . . . 4-9
Figure 4-4 Design With Large Timing Violations . . . . . . . . . . . . . . . 4-12

vii
viii
Tables

Table 1-1 Supported File Formats . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Table 1-2 Design Vision Supported Platforms . . . . . . . . . . . . . . . . 1-6
Table 2-1 Commands for Scripting . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

ix
x
Preface FIX ME!

This preface includes the following sections:

• What’s New in This Release

• About This User Guide
• Customer Support

xi
What’s New in This Release
Information about new features, enhancements, and changes;
known problems and limitations; and resolved Synopsys Technical
Action Requests (STARs) is available in the Design Vision Release
Notes in SolvNet.

To see the Design Vision Release Notes,

1. Go to the Synopsys Web page at http://www.synopsys.com and

click SolvNet.
2. If prompted, enter your user name and password. (If you do not
have a Synopsys user name and password, follow the
instructions to register with SolvNet.)
3. Click Release Notes in the Main Navigation section, find the
U-2003.03 Release Notes, then open the Design Vision Release
Notes.

About This User Guide

This section contains information about the target audience of this
document, where to find other pertinent publications, and
documentation conventions used in this manual.

Preface
xii
Audience
This user guide is for logic design engineers who have some
experience using Design Compiler and who want to use the
visualization features of Design Vision for synthesis and analysis. To
use this user guide, you should be familiar with

• Synthesis using Design Compiler

• VHDL or Verilog HDL
• The UNIX operating system

Related Publications
For additional information about Design Vision, see

• Synopsys Online Documentation (SOLD), which is included with

the software for CD users or is available to download through the
Synopsys Electronic Software Transfer (EST) system
• Documentation on the Web, which is available through SolvNet
at http://solvnet.synopsys.com
• The Synopsys MediaDocs Shop, from which you can order
printed copies of Synopsys documents, at
http://mediadocs.synopsys.com
You might also want to refer to the documentation for the following
related Synopsys products:

• Design Compiler
• DFT Compiler
• BSD Compiler

About This User Guide

xiii
 • Power Compiler

Preface
xiv
Conventions
The following conventions are used in Synopsys documentation.

Convention Description

Courier Indicates command syntax.

Courier italic Indicates a user-defined value in Synopsys

syntax, such as object_name. (A user-defined
value that is not Synopsys syntax, such as a
user-defined value in a Verilog or VHDL
statement, is indicated by regular text font
italic.)

Courier bold Indicates user input—text you type verbatim—

in Synopsys syntax and examples. (User input
that is not Synopsys syntax, such as a user
name or password you enter in a GUI, is
indicated by regular text font bold.)

[] Denotes optional parameters, such as

pin1 [pin2 ... pinN]

| Indicates a choice among alternatives, such as

low | medium | high
(This example indicates that you can enter one
of three possible values for an option:
low, medium, or high.)

_ Connects terms that are read as a single term

by the system, such as
set_annotated_delay

Control-c Indicates a keyboard combination, such as

holding down the Control key and pressing c.

\ Indicates a continuation of a command line.

/ Indicates levels of directory structure.

Edit > Copy Indicates a path to a menu command, such as

opening the Edit menu and choosing Copy.

About This User Guide

xv
Customer Support
Customer support is available through SolvNet online customer
support and through contacting the Synopsys Technical Support
Center.

Accessing SolvNet
SolvNet includes an electronic knowledge base of technical articles
and answers to frequently asked questions about Synopsys tools.
SolvNet also gives you access to a wide range of Synopsys online
services including software downloads, documentation on the Web,
and “Enter a Call to the Support Center.”

To access SolvNet,

1. Go to the SolvNet Web page at http://solvnet.synopsys.com.

2. If prompted, enter your user name and password. (If you do not
have a Synopsys user name and password, follow the
instructions to register with SolvNet.)
If you need help using SolvNet, click SolvNet Help in the Support
Resources section.

Preface
xvi
Contacting the Synopsys Technical Support Center
If you have problems, questions, or suggestions, you can contact the
Synopsys Technical Support Center in the following ways:

• Open a call to your local support center from the Web by going to
http://solvnet.synopsys.com (Synopsys user name and
password required), then clicking “Enter a Call to the Support
Center.”
• Send an e-mail message to support_center@synopsys.com.
• Telephone your local support center.
- Call (800) 245-8005 from within the continental United States.
- Call (650) 584-4200 from Canada.
- Find other local support center telephone numbers at
http://www.synopsys.com/support/support_ctr.

Customer Support
xvii
Preface
xviii
1
Introduction to Design Vision 1
Design Vision is a graphical user interface (GUI) to the Synopsys
synthesis environment and an analysis tool for viewing and
analyzing your design at the generic technology (GTECH) level and
the gate level.

This chapter contains the following sections:

• Features and Benefits

• User Interfaces
• Methodology
• Supported Formats
• Licensing
• Supported Platforms
• Design Vision and Other Synopsys Products

1-1
Features and Benefits
Design Vision has these features:

• Window- and menu-driven interface to Synopsys synthesis

(Design Compiler)
• Analysis visualization capabilities that include
- A logic hierarchy view for easy visualization and navigation of
your design hierarchy (including viewing area attributes)
- Design schematic generation for examining high-level and
low-level design connectivity
- Histograms for visualizing trends in various metrics, for
example slack and capacitance
- Path schematic generation for visual examination of any paths
or selected logic you choose
• Command-line interface integrated in the GUI
• Scripting support for all Design Compiler shell (dcsh) commands
and Design Compiler tool command language (dctcl) commands
Using the features of Design Vision, you can

• Invoke Design Compiler synthesis and reporting

• Explore design structure
• Perform timing analysis for blocks you are synthesizing
• Visualize overall timing with Design Vision graphical analysis
• Perform detailed visual analysis of timing paths

Chapter 1: Introduction to Design Vision

1-2
 • Insert scan cells and logic into a design, with or without test
points

User Interfaces
Design Vision offers menus and dialog boxes for important Design
Compiler functions. Menus also offer visual analysis features and
other design viewing features that are not Design Compiler
functions.

Design Vision includes a command-line interface that provides

access to all the capabilities of Synopsys synthesis tools.

The Design Vision GUI and command-line interface operate in both

Tcl (dctcl) mode, the default, and dc_shell (dcsh) mode.

Methodology
Design Vision allows you to use the same design methodology and
scripts you currently use and to extend your methodology with
Design Vision visual analysis.

Many of the Design Compiler functions are available through Design

Vision menus. All Design Compiler functions are available through
the Design Vision command-line interface.

User Interfaces
1-3
Supported Formats
With Design Vision you can access all the files supported by Design
Compiler. Table 1-1 shows the supported design file formats.

Table 1-1 Supported File Formats

Data Formats

Netlist EDIF

LSI Logic Corporation netlist format (LSI)

Mentor Intermediate Format (MIF)

Programmable logic array (PLA)

Synopsys equation

Synopsys state table

Synopsys database format (.db)

Tegas Design Language (TDL)

Verilog

VHDL

Xilinx Netlist Format (XNF)

Timing Standard Delay Format (SDF)

Command dcsh, Tcl

Script

Cell Clustering Physical Design Exchange Format (PDEF)

Library Synopsys internal library format (.lib)

Synopsys database format (.db)

Parasitics dc_shell command scripts

Chapter 1: Introduction to Design Vision

1-4
Licensing
To use Design Vision, you need the Design-Vision license.

Synopsys licensing software and the documentation describing it are

now separate from the tools that use it. You install, configure, and
use a single copy of Synopsys Common Licensing (SCL) for all
Synopsys tools. Because it provides a single, common licensing
base for all Synopsys tools, SCL reduces licensing administration
complexity, minimizing the effort you expend in installing,
maintaining, and managing licensing software for Synopsys tools.

For complete Synopsys licensing information, see the following

documents:

• Licensing Quick Start

This booklet provides instructions on how to obtain an electronic
copy of your license key file and how to install and configure SCL
on UNIX and Windows NT operating systems.

• Licensing Installation and Administration Guide

This guide provides detailed information on SCL installation and
configuration, including examples of license key files and
troubleshooting guidelines.

Licensing
1-5
Supported Platforms
Design Vision runs on the platforms listed in Table 1-2.

Table 1-2 Design Vision Supported Platforms

Platform Operating system Default window manager

HP9000 HP-UX 11.0, 11.11 (11i) CDE

IBM RS/6000 AIX 4.3.31 CDE

Sun SPARC Solaris 8 CDE

Intel IA-32 Red Hat Linux 7.22 GNOME

1. Not available on CD, but will be available for download by EST at a later date. For availability, check
with your Synopsys sales representative.
2. Runs only in 32-bit mode; limited to 4 GB memory space.

All UNIX platforms support the default window manager supplied by

the manufacturer as well as Motif Window Manager v1.2.1 through
v1.2.5, and eXceed versions 6.2 and 7.0 native window manager
multiple window mode. Design Vision does not support the
schematic interface (SGE) to Mentor Graphics tools.

Note:
OpenWindows is not a supported window manager for Design
Vision. Sun Microsystems no longer supports or maintains
OpenWindows and recommends that you move to the CDE
Windows environment.

Chapter 1: Introduction to Design Vision

1-6
 Your hardware and operating system vendor has required patches
available for your system. For more information about the supported
platforms and the operating system patches necessary to run
Synopsys software on supported platforms, go to

http://www.synopsys.com/products/sw_platform.html

From this Web page you can navigate to the Supported Platforms
Guide for your release.

Design Vision and Other Synopsys Products

As a visual analysis tool and GUI for Synopsys synthesis, Design
Vision works with Design Compiler to synthesize and analyze your
design.

The Design Vision and Synopsys PrimeTime tools have similar

timing visualization features; however, the tools have different timing
engines and differ in their application to analysis. Design Vision has
the same static timing engine as Design Compiler. Use Design
Vision to perform timing analysis and modification of blocks you are
synthesizing. Use PrimeTime for static timing sign-off or for
analyzing the timing of a chip or of large portions of a chip.

Design Vision and Other Synopsys Products

1-7
Chapter 1: Introduction to Design Vision
1-8
2
Before You Start 2
This chapter contains general and specific information you need to
know before you use Design Vision for the first time. In this chapter
you can find the following sections:

• The Design Vision Documentation Set

• Setup Files for Design Vision
• Starting and Exiting the Graphical User Interface
• Exploring the Graphical User Interface
• Changing the Appearance of Schematics
• Using Scripts

2-1
The Design Vision Documentation Set
You can find most of what you need to know to run Design Vision in
the Design Vision documentation set.

The Design Vision documentation set is divided into these parts:

• Design Compiler Tutorial Using Design Vision

• Design Vision User Guide
• Design Vision online Help
Other sources of information include man pages, the SolvNet
knowledge base, and the Customer Support Center. For information
about accessing these sources of information, see “Customer
Support” on page xvi.

Design Compiler Tutorial Using Design Vision

The Design Compiler Tutorial Using Design Vision is an introduction
to ASIC design using Synopsys Design Compiler and Design Vision.

The tutorial is a group of guided exercises in which you use Design

Compiler to synthesize and analyze a simple design. The tutorial
introduces Design Vision as the GUI for synthesis and provides
some post-synthesis analysis that takes advantage of the Design
Vision visual representation of analysis results.

Use the Design Compiler Tutorial Using Design Vision if you are new
to Design Compiler. However, even if you are an experienced Design
Compiler user, the tutorial is a useful introduction to the features of
Design Vision.

Chapter 2: Before You Start

2-2
In the tutorial, you can read about and perform exercises for basic
synthesis and analysis. For example, you

• Read a design from disk into the tool’s workspace

• Define design constraints to direct synthesis results
• Compile the design to gates
• View analysis results
• Modify the design
• Resynthesize the design
• Reanalyze the design

Design Vision User Guide

The Design Vision User Guide assumes you are familiar with basic
Design Compiler concepts.

The user guide provides guidance in solving particular problems. For

example, it presents short procedures that use the analysis
visualization features of Design Vision to locate and solve timing
problems.

Sometimes steps in a procedure refer to actions without further

explanation: for example, “Create a histogram” or “Create a path
schematic.” Such steps refer to features of Design Vision that are
explained in the Design Vision online Help.

The Design Vision User Guide does not contain specific information
about individual menu items or dialog boxes. For such information,
see the Design Vision online Help.

The Design Vision Documentation Set

2-3
 In Chapter 3, “Performing Basic Tasks,” experienced Design
Compiler users can learn how to do certain familiar synthesis tasks
using Design Vision. However, the user guide explains such topics
only briefly.

Design Vision Online Help

The Design Vision online Help is integrated in the Design Vision GUI.
You access the Help system from the Help menu in the main Design
Vision window.

Design Vision online Help explains the details of features and

procedures. For example, if you need help performing a step in a
procedure presented in the user guide, you can find the information
you need in the online Help system.

Information in online Help is grouped in the following categories:

• Feature topics
Provide overviews of Design Vision window components and
tools.

• How to topics
Provide procedures for accomplishing general synthesis and
analysis tasks.

• Reference topics
Provide explanations for views, toolbar buttons, menu
commands, and dialog box options.

Chapter 2: Before You Start

2-4
 To access the Design Vision online Help system,

• Choose Help > Online Help.

Design Vision online Help is a browser-based HTML Help system.
For optimal viewing, you should use Netscape Navigator version
4.78. Design Vision Help is not supported in Netscape version 6 or
later.

The online Help system makes extensive use of Java, JavaScript,

and style sheets. To configure your browser for viewing online Help,
make sure the advanced preferences are set as follows:

• Enable Java, JavaScript, and style sheets

• Disable Java plug-ins
If you reset preferences while the Help system is open, click the
Reload button on the browser's navigation toolbar after you reset the
preferences.

Setup Files for Design Vision

When you start Design Vision, it executes the standard Synopsys
setup file, .synopsys_dc.setup, and the GUI setup file, .dv_setup.tcl.
Design Vision also executes the GUI setup file when you open or
reopen the GUI from the Design Vision shell. These setup files have
the same names in each of their three locations: the installation,
home, and design directories.

Setup Files for Design Vision

2-5
 The files contain commands that initialize parameters and variables,
declare design libraries, and so forth. Besides defining settings for
synthesis, these files can

• Change the default appearance of Design Vision schematics

• Define scripts that you can run by using the source command
(for dctcl scripts) or the include command (for dcsh scripts)
These topics are covered in detail in “Exploring the Graphical User
Interface” on page 2-9 and “Using Scripts” on page 2-14
respectively.

For more information about the locations of setup files and

initialization settings for synthesis, see the Design Compiler User
Guide.

Chapter 2: Before You Start

2-6
Starting and Exiting the Graphical User Interface
You can invoke the Design Vision GUI in either of the two dc_shell
modes:

• dctcl mode
This is the default.

• dcsh mode
You must start in this mode to use dcsh scripts.

To start Design Vision in dctcl mode,

• At the UNIX shell prompt, enter

% design_vision

To start Design Vision in dcsh mode,

• At the UNIX shell prompt, enter

% design_vision -dcsh_mode

You cannot switch from mode to mode in the same session. To

operate in either mode, Design Vision must start up and initialize in
that mode. For example, to change from the default dctcl mode to
dcsh mode, exit Design Vision and start Design Vision in dcsh mode.

When you start Design Vision, the Design Vision window appears by
default. In addition, the design_vision-t prompt (in dctcl mode) or the
design_vision prompt (in dcsh mode) appears in the shell where you
started Design Vision.

Starting and Exiting the Graphical User Interface

2-7
 You can close and reopen the Design Vision GUI without exiting the
Design Vision shell. In addition, you can start the Design Vision shell
without opening the GUI.

To close the GUI without exiting Design Vision,

• Choose File > Close.

Or you can enter gui_stop on the command line.

To open or reopen the GUI from the Design Vision shell,

• Enter the following on the design_vision-t (or design_vision)

command line.
design_vision-t> gui_start

To start Design Vision in dctcl mode without opening the GUI,

• At the UNIX shell prompt, enter

% design_vision -no_gui

To start Design Vision in dcsh mode without opening the GUI,

• At the UNIX shell prompt, enter

% design_vision -dcsh_mode -no_gui

To set Design Vision to start without the GUI by default,

• Set the following variable in your .synopsys_dc.setup file:

set gui_auto_start 0

To exit Design Vision,

• Choose File > Exit.

Chapter 2: Before You Start

2-8
Exploring the Graphical User Interface
Design Vision has the look and feel of the Microsoft Windows GUI.
Figure 2-1 shows the window you see when you start Design Vision,
read in a design, and a design schematic for the top-level design.

Figure 2-1 The Design Vision Window

Logic hierarchy view Menus Toolbars Schematic view

Status bar Tabs Command line Console

Exploring the Graphical User Interface

2-9
 The window consists of a title bar, a menu bar, and several toolbars
at the top of the window and a status bar at the bottom of the window.
You use the workspace between the toolbars and the status bar to
display view windows containing graphical and textual design
information. When you start a Design Vision session, the following
view windows appear in the workspace:

• Logic hierarchy View

The logic hierarchy view helps you navigate your design and
gather information. The view is divided into the following two
panes:

- Instance tree
- Objects list
The instance tree lets you quickly navigate the design hierarchy
and see the relationships among its levels. If you select the
instance name of a hierarchical cell (an instance that contains
subblocks), information about that instance appears in the object
table. You can Shift-click or Control-click instance names to
select combinations of instances.

By default, the object table displays information about

hierarchical cells belonging to the selected instance in the
instance tree. To display information about other types of objects,
select the object types in the list above the table. You can display
information about hierarchical cells, all cells, pins and ports, pins
of child cells, and nets.

If some of the text in a column is missing because the column is

too narrow, you can hold the pointer over it to display the
information in an InfoTip. You can also adjust the width of a
column by dragging its right edge left or right.

Chapter 2: Before You Start

2-10
• Console
The console provides a command-line interface and displays
information about the commands you use during the session in
the following three views:

- Log view
- History view
- Errors and warnings view
You can enter dc_shell commands on the command line at the
bottom of the console. Enter these commands just as you would
enter them at the dc_shell prompt in a standard UNIX or Linux
shell. Design Vision echoes the dc_shell command output
(including processing messages and any warnings or error
messages) in the console log view.

The log view provides the session transcript. The history view
provides a list of the commands that you have used during the
session. The errors and warnings view displays error and
warning messages.

To select a view, click the tab at the bottom of the console. The
log view is displayed by default when you start Design Vision. For
more details about the console, see the “Using dc_shell
Commands” topic in online Help.

In addition to the logic hierarchy view and the console, you can
display design information in the following views:

• Schematic views (design schematics, path schematics, and

symbol views)
• Histogram views (endpoint slack, path slack, net capacitance,
and user-defined)

Exploring the Graphical User Interface

2-11
 • Report view
• List views (cells, ports, pins, nets, and designs)
Design Vision displays a tab in the workspace for each undocked
view you open.

You can adjust the sizes of view windows for viewing purposes, and
you can move them to different locations within the Design Vision
window. When you click anywhere within a view window, Design
Vision highlights its title bar to indicate that it has the focus (that is, it
is the active view) and can receive keyboard and mouse input. For
more details, see the “Design Vision Window” topic in online Help.

To learn more about the functions of menu commands and toolbar

buttons, see the “Menu Bar” and “Toolbars” topics in online Help.

The status bar, at the bottom of the window, displays current

information about the session, such as the number and type of
selected objects. If you hold the pointer over a menu command, a
toolbar button, or a tab in the workspace, the status bar displays a
brief message about the action that the command, button, or tab
performs. To quickly display the list of selected objects in the
Selection List dialog box, you can click the button at the right end of
the status bar.

You can open additional Design Vision windows and use them to
compare views, or different design information within a view, side by
side. All open Design Vision windows share the same designs in
memory and the same current timing information. However, you can
configure the views independently for each window. To learn more,
see the “Opening New Design Vision Windows” topic in online Help.

Chapter 2: Before You Start

2-12
Changing the Appearance of Schematics
For display purposes only, when Design Vision generates a
schematic, it applies the same display characteristics (color, fill
pattern, line width, line style, text color, and font) to all the objects of
a given object type: cell, port, pin, net, bus, bus ripper, or hierarchy
crossing. This convention allows you to define how similar objects
are displayed in a schematic or whether they appear at all.

You can change schematic settings in either of the following ways:

• Choose View > Preferences to open the Application Preferences

dialog box, select the Schematic Settings category, set the
desired options, and click OK.
• Edit the .synopsys_dv_prefs.tcl file and run it as a Tcl script.

Changing the Appearance of Schematics

2-13
Using Scripts
Designers often use scripts to accomplish routine repetitive tasks
such as setting constraints or defining other design attributes.
Because Design Vision can run in either dctcl mode or dcsh mode,
you can use your existing scripts in Design Vision.

To run dctcl scripts, start Design Vision in dctcl mode. To run dcsh
scripts, start Design Vision in dcsh mode. For information about
starting Design Vision in either mode, see “Starting and Exiting the
Graphical User Interface” on page 2-7.

To run scripts in Design Vision,

• Choose File > Execute Scripts.

The Execute File dialog box opens. Use the dialog box to
navigate to the appropriate directory and run your script.

Alternatively, you can run scripts from the design_vision-t command

line by using the source command in dctcl mode or from the
design_vision command line by using the include command in
dcsh mode.

To learn more about adding scripts to the Tools menu, see the “Using
Scripts” topic in online Help.

Chapter 2: Before You Start

2-14
 Table 2-1 is a short list of some commands that are useful when you
are writing scripts for use with Design Vision.

Table 2-1 Commands for Scripting

Command Mode Description

get_selection dctcl Returns a collection that is

currently selected in the GUI

change_selection dctcl Changes the selection in the

GUI to the collection passed to it
as a parameter

For detailed descriptions of commands and options, see the man

page for each command.

Using Scripts
2-15
Chapter 2: Before You Start
2-16
3
Performing Basic Tasks 3
This chapter describes how to perform basic presynthesis and
synthesis tasks using Design Vision menus. This chapter is useful for
experienced users of Design Compiler who need to accomplish
familiar basic tasks in Design Compiler using Design Vision windows
and menus.

If you are new to Synopsys synthesis tools, see the Design Compiler
Tutorial Using Design Vision to learn about basic tasks by performing
them on a simple design.

This chapter contains the following sections:

• Specifying Libraries
• Reading In Your Design
• Setting the Current Design
• Defining the Design Environment

3-1
 • Setting Design Constraints
• Compiling the Design
• Saving the Design Database
• Working With Reports
• Printing Schematics

Chapter 3: Performing Basic Tasks

3-2
Specifying Libraries
Before you start work on a design, specify the location of your
libraries. You can define your library locations directly in the
.synopsys_dc.setup file or indirectly by entering the locations in the
Application Setup dialog box. Either method is acceptable—they
both accomplish the same thing.

The link and target libraries are technology libraries that define the
semiconductor vendor’s set of cells and related information, such as
cell names, cell pin names, delay arcs, pin loading, design rules, and
operating conditions.

The symbol library defines the symbols for schematic viewing of the
design.

You must specify any additional, specially licensed, DesignWare

libraries with the synthetic_library variable (you do not need to
specify the standard DesignWare library).

To define libraries in the .synopsys_dc.setup file, see the Design

Compiler User Guide.

To specify the library location in the Application Setup dialog box,

1. Select File > Setup.

The Application Setup dialog box opens.

2. Select the Defaults category if the Defaults page is not displayed.

3. Enter the library file names for link library, target library, and
symbol library.
4. Make sure you enter the appropriate path in the Search Path box.

Specifying Libraries
3-3
 5. Click OK.
For more information about the options on the Defaults page, see the
“Setting Library Locations” topic in the online Help. For information
about the options on the Variables page, see the “Setting Variables”
topic.

To understand more about the function of link libraries, target

libraries, and symbol libraries, see the Design Compiler User Guide.

Reading In Your Design

To begin working on your design, read the design from disk into the
tool’s active memory. This is where all changes in the design take
place before you save the design by writing it back to disk.

The File menu contains the commands for reading in a design:

• Analyze and Elaborate

Use Analyze and Elaborate to read HDL designs and convert
them to Synopsys database (.db) format.

• Read
Use Read (read_file is the command-line equivalent) to read
designs that are already in .db format.

The Analyze command checks the HDL designs for proper syntax
and synthesizable logic, translates the design files into an
intermediate format, and stores the intermediate files in the directory
you specify.

Chapter 3: Performing Basic Tasks

3-4
 The Elaborate command first checks the intermediate format files
before building a.db design. During this process, Elaborate
determines whether it has the necessary synthetic operators to
replace the HDL operators, and it also determines correct bus size.

If you use Read to read in HDL files, the Analyze and Elaborate read
functions are combined; however, Read does not do certain design
checks that Analyze and Elaborate do.

Setting the Current Design

When you start a Design Vision session and read a design, the
current design is automatically set to the top-level design. Some
commands require you to set the current design to a subdesign
before you issue them (the man pages provide such information).

To set the current design,

1. Click the drop-down list on the Design List toolbar to display the
design names.
2. Select a design name.
Alternatively, you can open a designs list view (by choosing List >
Designs View) and double-click a design name.

The command-line equivalent is set current_design.

Setting the Current Design

3-5
Defining the Design Environment
Design Compiler requires that you model the environment of the
design to be synthesized. This model comprises the external
operating conditions (manufacturing process, temperature, and
voltage), loads, drives, fanout, and wire load models. It directly
influences design synthesis and optimization results.

Defining the design environment can involve invoking a large number

of commands. Many designers find it convenient to define the design
environment by using the default target technology library settings
and by running scripts to define differences or additions.

To define the design environment by using Design Vision menus,

explore the Operating Environment submenu on the Attributes
menu. The online Help has more information about particular
commands and submenus in the Attributes menu.

Setting Design Constraints

Setting design constraints can involve invoking a large number of
commands. Most designers find it convenient to use scripts to set
design constraints.

Design Compiler uses design rule and optimization constraints to

control the synthesis of the design.

Chapter 3: Performing Basic Tasks

3-6
Setting Design Rule Constraints
Design rules are provided in the vendor technology library to ensure
that the product meets specifications and works as intended. Typical
design rules constrain transition times, fanout loads, and
capacitances. These rules specify technology requirements that you
cannot violate. (You can, however, specify stricter constraints.)

To set design rule constraints by using the GUI,

• Choose Attributes > Optimization Constraints >

Design Constraints, set options as needed, and click OK.

Setting Optimization Constraints

Optimization constraints define the design goals for timing (clocks,
clock skews, input delays, and output delays) and area (maximum
area). During optimization, Design Compiler attempts to meet these
goals; however, it does not violate your design rules. To optimize a
design correctly, you must set realistic optimization constraints.

To set optimization constraints by using the GUI,

• Click Attributes in the menu bar to open the Attributes menu.

Use Specify Clock to set clock constraints. Other optimization
constraints and settings are in the submenus under the Attributes
menu: Operating Environment, Optimization Constraints, and
Optimization Directives. Explore these submenus to find the
settings you need.

For more information about menu items in the Attributes menu, see
the “Attributes Menu” topic in the online Help.

Setting Design Constraints

3-7
Compiling the Design
Use Design Vision to invoke Design Compiler synthesis and
optimization, thus compiling your high-level design description to
your target technology.

Design Vision supports standard synthesis methodology: either a

top-down compile or a bottom-up compile. For more information
about compile methodologies, see the Design Compiler User Guide.

To compile the current design,

1. Choose Design > Compile Design.

The Compile Design dialog box opens.

2. Select or deselect options as you require.

Use the default settings for your first-pass compile. For most
designs, the default settings provide good initial results. For more
information about compile options, see the Design Compiler User
Guide and the Design Compiler Reference Manual: Optimization
and Timing Analysis.

3. Click OK to begin compiling.

After compiling the design, save the design as described in the next
section.

Chapter 3: Performing Basic Tasks

3-8
 The command log file records your Design Vision session. This log
file is a record of all commands invoked. It includes commands you
enter on the command line, commands initiated by your menu and
dialog box selections, and tool commands (such as initialization
commands and commands needed to execute user-entered
commands).

You can use the command.log file to create a script file. Copy the file
and use a text editor to add or remove commands as necessary.

Saving the Design Database

Design Vision does not automatically save designs before exiting.

To save the current design and each of its subdesigns in separate

Synopsys database (.db) format files named design_name.db,
where design_name is the name of the design,

• Choose File > Save.

To save the current design and all of its subdesigns in a single file
with a different file name or file format,

• Choose File > Save As, enter or select a file name, select a file
format, and click OK.

Working With Reports

Textual reports are available from the Design menu and the Timing
menu. Use commands in the Design menu to generate design
information and design object reports. Use commands in the Timing

Saving the Design Database

3-9
 menu to generate timing and constraint reports. If these menus do
not have the report you need, you can generate any Design Compiler
by issuing dc_shell report commands on the command line.

You can generate reports and display them in the report view (the
default), save them in text files, or both. When you display a report in
the report view, you can select object names in the report. You can
also save or print the report. For more information, see the “Viewing
Reports” topic in online Help.

Generating Reports for Selected Objects

You can generate reports for selected objects.

To generate a report for a particular design object or group of design

objects,

1. Select an object.
2. Choose a report command in the Design menu to open the
associated dialog box.
You can generate reports for cells, ports, and nets.

3. Click Selection in the report dialog box.

The names of the selected objects appear.

4. Set other options as needed.

5. Click OK.

Chapter 3: Performing Basic Tasks

3-10
Printing Schematics
You can print the path schematic, design schematic, or symbol view
displayed in the active schematic view. Be sure that a default printer
is set in your .cshrc file.

To print the active schematic view,

1. Generate a path schematic, design schematic, or symbol view.

2. Make sure the view you want to print is the active view.
Click the corresponding tab at the bottom of the workspace if you
need to make the view active.

3. Choose File > Print Schematic.

The Select Printer Settings dialog box opens.

4. Select the print options you require and click OK.

For details about the options in the Print dialog box, see the “Printing
a Schematic View” topic in online Help.

Printing Schematics
3-11
Chapter 3: Performing Basic Tasks
3-12
4
Solving Timing Problems 4
This chapter presents procedures and suggestions for solving timing
problems by using the features of Design Vision. The chapter does
not provide details about exercising particular features of Design
Vision, such as how to create a histogram or how to create a path
schematic. For detailed information about Design Vision features,
see the Design Vision online Help system.

This chapter contains the following sections:

• Before You Analyze

• Creating a Timing Overview
• Choosing a Strategy for Timing Closure

4-1
Before You Analyze
Before you analyze your design with Design Vision, follow your
normal compile methodology to create a constrained gate-level
design. A constrained gate-level design is a prerequisite to any
timing analysis.

For more information about using Design Vision to create a

gate-level design, see Chapter 3, “Performing Basic Tasks.”

Creating a Timing Overview

Creating an overview of the timing of your design is a valuable way
to start any analysis of your design’s timing problems. A timing
overview can help you decide what strategy to follow in gaining
timing closure.

For example, a timing overview can help answer such questions as

• Do I have many failing paths or just a few?

• Can I apply a local strategy for gaining timing closure?
• Do I need a global strategy for gaining timing closure?
To create a timing overview of your design,

1. Start with a constrained gate-level design.

2. Generate an endpoint slack histogram.
Figure 4-1 is a typical endpoint slack histogram for a design with a
4-ns clock cycle.

Chapter 4: Solving Timing Problems

4-2
Figure 4-1 Endpoint Slack Histogram

Endpoints of Selected bin (yellow)

failing paths (red)
Endpoint names for
selected bin

Using information such as that in Figure 4-1, you might decide on a

local strategy if just a few paths are failing by a small margin (failing
path endpoints are in one or more red bins to the left of 0 on the
horizontal axis). Conversely, if you find that many paths are failing, or
that the design is failing your timing goals by a large margin, you
might choose a higher-level, or global, strategy for problem solving.

Creating a Timing Overview

4-3
Choosing a Strategy for Timing Closure
There is no single strategy that ensures quick and easy timing
closure; however, a strategy based on the size and number of timing
violations can be useful.

Assessing the Relative Size of Your Timing Violations

This section suggests guidelines for describing the relative size of
timing violations in your design. After you create an endpoint slack
histogram, you can use these size guidelines to help you judge what
strategy to use for timing closure.

What you consider to be small or large violations depends on the

requirements of your design and your design process; however,
assessing violation size as a percentage of clock cycle can be useful.

• Small violations
Some designers consider small violations to be about 10 percent
of the clock cycle or less.

• Large violations
Some designers consider large violations to be about 20 percent
of the clock cycle or greater.

• Medium violations
Medium-size timing failures fall between the limits you set for
large and small failures in your design or design process.

Whether your design is failing timing goals by large or small margins,

the best strategy for timing closure is one that uses the least amount
of runtime or number of design iterations to achieve timing goals.

Chapter 4: Solving Timing Problems

4-4
 This principle underlies the methodology suggestions in this chapter.
For more information about creating a timing overview, see “Creating
a Timing Overview” on page 4-2.

When Timing Violations Are Small

Figure 4-2 is a histogram of a design that is failing timing goals by a
small margin. For example, no path is failing by more than 0.14 ns—
that is, less than 10 percent of the 4-ns clock cycle (ignoring input
and output delay). You can click any bin to see the endpoint names
for the paths in the bin.

Figure 4-2 Design With Small Timing Violations

Clock cycle: 4 ns

Endpoints of
failing paths (red)

Choosing a Strategy for Timing Closure

4-5
 Designs that fail by a small margin can have many failing paths or
just a few. The endpoint slack histogram helps you to recognize
quickly which case you have. Whether you have just a few failing
paths or many, you can follow a global or local strategy in fixing the
violations.

If suggestions for fixing small violations (either globally or locally)

don’t meet your timing goals, try applying the suggestions in “When
Timing Violations Are Medium Size” on page 4-8 or “When Timing
Violations Are Large” on page 4-11.

Working Globally to Fix Small Violations

To apply a global methodology for fixing small violations, consider
recompiling your design using the incremental option and a higher
map effort. The incremental option saves runtime by using the
current netlist as the startpoint for design improvements.

The incremental compile with higher map effort has the advantage
of simplicity—that is, it requires little or no time spent in analyzing the
source of timing problems. However, this method can change much
of the logic in the design.

Working Locally to Fix Small Violations

If you have a small number of paths with small violations, or if your
violations seem to come from a limited set of problems on a few
paths, a local strategy can be effective.

To use a local strategy for fixing small violations,

• Check hierarchy on failing paths

Chapter 4: Solving Timing Problems

4-6
 Design Compiler does not optimize across hierarchical
boundaries. Thus, snake paths limit Design Compiler’s ability to
solve timing problems on such paths.

• Look for excessive fanout on failing paths

Because higher fanout causes higher transition times, excessive
fanout can worsen negative slack on failing paths.

To check for hierarchy problems on failing paths (dctcl mode only),

1. Generate an endpoint slack histogram.

2. Click a bin that contains a failing path.
A list of endpoints for failing paths is displayed.

3. Select the endpoint for the path you are interested in.
4. Generate a path schematic to see which leaf cells are in which
levels of hierarchy.
If your critical path, for example, crosses multiple subblocks of a
level of hierarchy, consider ungrouping these subblocks. Design
Compiler does not optimize across hierarchy boundaries. Thus,
a subsequent compile has further opportunity to optimize the
critical path when you ungroup such blocks.

To look for excessive fanout on failing paths,

1. Generate an endpoint slack histogram.

2. Select the endpoints for failing paths.
Select the failing bin to see the endpoints.

Choosing a Strategy for Timing Closure

4-7
 3. Generate a timing report with the following options:
- net
- trans
Send the report output to the report view. For more information
on report generation, see “Working With Reports” on page 3-9
and the “Viewing Reports” topic in online Help.

4. Examine the report for pins with high transition times and nets
with high fanout.
Such paths are candidates for buffering or drive-cell resizing.

5. Create path schematics of any paths you would like to see.

A path schematic provides contextual information and details
about the path and its components. Such information is often a
prerequisite to understanding problems on the path.

6. View fanin and fanout for path schematics.

This step can provide useful information about the logic that
drives, or is driven by, the problem path. For example, after
viewing fanin or fanout, you might choose to resize cells in those
logic cones.

When Timing Violations Are Medium Size

Figure 4-3 is a histogram of a design that is failing timing goals by
margins that are between the large and small limits that are
appropriate to your design methodology (for example, between 10
and 20 percent of the clock cycle). You can click a bin to see the
endpoint names for paths the bin contains. A bin is yellow when
selected. In Figure 4-3, one of the four bins containing endpoints of
failing paths is selected.

Chapter 4: Solving Timing Problems

4-8
Figure 4-3 Design With Medium Timing Violations

Clock cycle: 4 ns

Endpoints of failing paths

When negative slack values are medium, you can use Design Vision
to investigate further and focus your recompile on a critical range of
negative slack values for path groups. Focusing your compile effort
on a critical range can improve worst negative slack and total
negative slack. For more information about calculating worst
negative slack and total negative slack, see the SolvNet article
Synthesis-238.html.

Defining a critical range for path groups offers the advantage of

concentrating compile effort and runtime on those areas that most
need it.

Choosing a Strategy for Timing Closure

4-9
 To investigate and focus a recompile by defining a critical negative
slack range for path groups,

1. Create a path slack histogram for each path group in your design.
Start with an arbitrary value of 1000 for the number of paths to
include in each histogram. Raise or lower this value depending
on the number of failing paths. The goal is to choose a value that
shows you all or nearly all of the failing paths.

2. Decide on a critical range for each path group (note the values for
use in step 3).
When deciding on a critical range, choose a range that allows Design
Compiler to focus on the worst endpoint violations without too large
an increase in runtime. For example, some designers apply one of
the following guidelines to decide on a critical range:

- Use a range that includes the worst 50 paths in a group.

- Use a range equal to one generic cell delay in your technology.
These are rough guidelines; for subsequent compiles you can
adjust your critical range as necessary.

3. Set a critical range for each path group.

Using the values you decided on in step 2, set the critical ranges
for each path group with the group_path command. For
example,

design_vision-t> group_path -name my_clock -critical_range 0.25

Chapter 4: Solving Timing Problems

4-10
4. Recompile the design.
With a critical range defined, the compile effort is now focused.
However, you can also choose to increase the compile effort over
your previous compile. In the Compile Design dialog box, select
medium or high effort. Select the “Incremental mapping” option
to direct Design Compiler to use the current netlist as a starting
point for design improvements. An incremental compile can save
runtime when your design does not require fundamental
changes.

For more information about defining critical ranges for synthesis, see
the SolvNet article Methodology-10.html.

If suggestions in this section don’t meet your timing goals, try

applying the suggestions in “When Timing Violations Are Large” on
page 4-11.

When Timing Violations Are Large

Figure 4-4 shows a design that is failing timing goals by a large
margin. You can click a bin to see the endpoint names for the paths
it contains.

Choosing a Strategy for Timing Closure

4-11
Figure 4-4 Design With Large Timing Violations

Clock cycle: 4 ns

Endpoints of failing paths

Fixing large violations can require a high-level strategy to improve

your design’s performance. To fix large timing problems, consider
any of the following changes:

• Modify your constraints.

For example, increase the clock cycle or adjust time budgeting for
the block or chip.

• Change the target technology.

For example, target a higher performance technology.

Chapter 4: Solving Timing Problems

4-12
• Modify the RTL.
For example, you can move late-arriving signals such that you
minimize their path length.

Choosing a Strategy for Timing Closure

4-13
Chapter 4: Solving Timing Problems
4-14
Index

A dcsh mode, starting 2-7

dcsh mode, starting without GUI 2-8
appearance, changing for schematics 2-13
dcsh scripts 2-14
Attributes menu 3-7
dctcl mode, starting 2-7
dctcl mode, starting without the GUI 2-8
C dctcl scripts 2-14
cell clustering data, supported formats 1-4 design
change_selection command 2-15 current, setting 3-5
writing to disk 3-9
closure, timing, strategy for 4-4
design constraints, setting 3-6
command.log 3-9
design files, supported formats 1-4
commands for scripting 2-15
compiling design schematics 2-11
focusing on timing range 4-10 Design Vision
starting, how to 3-8 documentation set 2-2
features of 1-2
conditions, operating 3-6
formats, input and output 1-4
Console, description 2-11
graphical window components 2-9
constraints, setting 3-6 introduction to 1-1
critical timing range licensing for 1-5
choosing for compile 4-10 supported platforms 1-6
current design, setting 3-5 Synopsys products, relationship to other 1-7
current instance, setting 3-5 user interfaces 1-3
design, reading in a 3-4
documentation, Design Vision 2-2
D drive strength, setting 3-6
.db file, saving 3-9

IN-1
E histograms
endpoint slack 4-2
environment, setting operating 3-6 script commands for 2-15
errors/warnings view 2-11 history view 2-11
excessive fanout, finding 4-7, 4-8

I
F initialization (see setup files)
fanout, excessive, finding 4-7, 4-8 instance tree 2-10
fanout, setting maximum 3-6 instance, setting current 3-5
features, Design Vision 1-2 interfaces, Design Vision 1-3
files
log files 3-9
setup files 2-5 L
finding reported objects in schematic 3-9 large timing violations
focusing compile 4-10 defined 4-4
formats global approach 4-12
cell clustering 1-4 layers, changing appearance 2-13
design data 1-4 libraries
input and output 1-4 specifying 3-3
library 1-4 supported formats 1-4
netlist 1-4 synthetic libraries 3-3
parasitics 1-4 licensing 1-5
script file 1-4 list views 2-12
timing data 1-4
loads, setting 3-6
log files
G naming 3-9
scripts, creating from 3-9
generating reports 3-9
log view 2-11
get_selection command 2-15
logic hierarchy view, description 2-10
global approach, timing closure
large violations 4-12
small violations 4-6 M
group_path command 4-10
manufacturing process, setting 3-6
GUI (see window, Design Vision)
medium-size timing violations
defining 4-4
H fixing 4-8
methodology
Help, online 2-4
choosing for timing closure 4-4
hierarchy, finding excessive 4-7 large violations, for 4-11
histogram views 2-11 medium-size violations, for 4-8

IN-2
 small violations, for 4-5, 4-6 SCL (Synopys Common Licensing) 1-5
scripts
command-line interface, running from 2-14
O commands 2-15
objects, locating reported 3-9 creating from log file 3-9
objects, reports for selected 3-10 histogram, generating 2-15
online Help, description of 2-4 menu access to 2-14
OpenWindows, support for 1-6 mode, Tcl and dsch 2-14
supported formats 1-4
operating conditions, setting 3-6
setup files 2-5
operating systems
patches for 1-7 slack types, SolvNet article about 4-9
supported platforms 1-6 small timing violations
optimization defining 4-4
constraints, setting 3-6 global approach to solving 4-6
initiating 3-8 local approach to solving 4-6
overview, creating for timing 4-2 snake paths, finding 4-7
SolvNet articles
slack types, calculating 4-9
P specifying libraries 3-3
parasitics, supported formats 1-4 status bar 2-9, 2-12
patches, operating system 1-7 supported
path schematics 2-11 operating systems 1-6
window managers 1-6
preferences, schematic appearance 2-13
printing Synopsys Common Licensing 1-5
schematics 3-11 synthesis, initiating 3-8
synthetic libraries 3-3

R
reading a design 3-4
T
reports Tcl mode, starting 2-7
for selected objects 3-10 timing closure, methodology
generating 3-9 for large violations 4-11
for medium-size violations 4-8
for small violations
S high-level approach 4-6
saving to disk 3-9 introduction 4-5
schematic views 2-11 low-level approach 4-6
schematics timing data, supported formats for 1-4
appearance, changing 2-13 timing problems, solving
printing 3-11 histogram, endpoint slack 4-2
judging violation size 4-4

IN-3
 strategy for closure, choosing 4-4
timing overview, creating 4-2
toolbar 2-9
tutorial, overview of 2-2

U
using scripts 2-14

V
violations, timing
fixing large 4-11
fixing medium size 4-8
fixing small 4-5
judging relative size of 4-4

W
window managers, supported 1-6
window, Design Vision
components of 2-9
modes of initialization 2-7
schematics, setting appearance 2-13
starting and exiting 2-7
wire load models, setting 3-6
workspace 2-9
writing to disk 3-9

IN-4