8751H/8753H Single-Chip 8-Bit Microcontroller with 4k/8K Bytes ‘of EPROM DISTINCTIVE CHARACTERISTICS 4K x8 EPROM (6751H); 8Kx8 EPROM (8753H) 420x8 RAM Four 8-bt ports, 92 1/0 tines; programmable ‘Two 16-bit Timer/Evont counters {84K adarossabie Program and Data Memory © Boolean processor ial port 18 Five interrupt sources/wo priory levels 4-cycle multiply and divide Program memory security feature Fast EPROM programming: 12 sec for 4K bytes ‘© ‘Supports siicon signature verifeaton © Pin compatbie with 8051 GENERAL DESCRIPTION ‘The 8751H and 8753H are members of @ family of advanced single-chip microcontrollers. Both the 8751H, which has 4K bytes of EPROM, and the 8753H, which hes {&K bytes of EPROM, are pin-compatile EPROM versions the G0S1AH and SOSSAH, respectively. Thus, the 8751H/8759H are ful-speed prototyping tools which pro- vide etfectve single-chip solutions for controller applica: tions that require code modification flexibity. fer to the block lagram of the 6051 family ‘The 8751H/8753H dovics feature: thirty-two 1/0 lines; Wo 16. timer/event counters; a Boolesn processor, a 5- ‘source, bilevel interrupt structure; aful-duplex serial chan- nel, and on-chip oscillator and clock cuit. Program and Data Memory are located in independent ‘addrosses, The AMO family of microcontrollers can access Upto 64K bytes of external Program Memory and up to 64K bytes of extemal Data Memory. The 8751H and the 6753H Contain the lower 4K and 8K bytes of Program Memory, respectively, on-chip. Both parts have 128 bytes of on-chip read/write data memory. ‘The AMD 8051 Microcontraliar Family is specifically suted for control applications. A variety of fast adsressing modes, Which aocoss the intemal RAM, facilitates byte processing ‘and numerical operations on small data structures. Includ- 0 in the instrtion set is a menu of B-bit arithmetic Instructions, including 4-cycle mutily and divide instruc- ‘ions, Extensive on-chip support enables direct bit manipulation ‘and testing of 1-it variables as separate datatypes. Thus, ‘the device's algo sulted for control and logle systems that raquire Boolean processing BLOCK DIAGRAM es | — fe f || bones mae gus ot 721CONNECTION DIAGRAMS Top View DIP TPP222I2 z SRSERRBS 588 zee Wns wre wine Br BErERUEEereuEeEsessS TERRIERS EE? . rrgriire 3 3 Note: Pin 1 is marked for orientation, With tii 7-22ORDERING INFORMATION Commadity Products AMD commodity products are availabe in soveral packages and operating ranges. The order number (Valid Combination) is smporature Range ©. Device Number 4. Speed Option . Optional Processing fr ‘gpTioNaL PRocEssiNG Siira= Stance Processing 16 SPEED OPTION Blane 12 Mee «6. DEVICE NUMBER/DESCRIPTION GTN Siglo Shp Sat Meroconroter wih ie Dye of EPROM Progam Maroy 17801 = Sirgletchp 8-8 Meroconlie wh {x Byte of EPROM Program Monon >. PACKAGE TYPE B48 Come OF covo%0) B= hn Garame Leadless Chip Carer (C.VD44) (Praiminan) ‘2 TEMPERATURE RANGE" Blanc = Gommereal (0 fo 470°C) Zhadueral (40 f6 65°C} (Protimnany Valid Combinations, Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combination, to check on newly released valid combinations, land to obtain additional data on AMD's standard mitary grade products, Valid Combinations ‘This device is also available in Miltary temporature range. ‘See MOS Microprocessors and Perigherals Miltary Handbook (Order #09275A/0) for electrical perlormance char- actoristics. 7-23PIN DESCRIPTION Port 0 (Bidirectional; Open Drain) Port 0is an open-drain /O pot. Por Opin that have t's witon to thar Nest, and in ha tae can e used as Nigh impedance inputs Por is also the multiplexed LOW order adcress and data bus duing aocesses to extra Program and Data Memory inthis applcaton it uses song ileal pups whan citing "1's. Port 0 also outputs the code bytes ding program veriication in the 8751H and €753H, Exteel pulps are requires during program vercation Port 1 (Blarectiona) Pod 1 is an i bidtectone! 1/0 por with internal pulups. The Port 1 output bufors can snk/souree four LS TTL Inputs. Port pine that have "1s writen to thom are pulled HIGH by the internal pulupe and — whit ints state — can be used as inputs. AS inputs, Port 1 pina that are fxtomaly bong pulled LOW wil source curent (hn the Gata shoot) because ofthe iniral pulps Pon also recioves the LOW-order adress bytes during program verficaion Port 2 (Bidirectional) Por 2 6 an Bit Bidroctonal 1/0 port wih internal pulps. ‘The Po 2 outut butlers can snk/soutce four LS TTL inputs Port 2 ps having "1's writen to them are puled HIGH by the itteral pulps and — while ints stato — can be used as inp. As inpus, Port 2 pine externally being pulod LOW wil source curont (ly) Because of intra pulps. Port 2 emits the HiGH.order adéress byte dung fetches from extemal Program Memory and during accesses 10 ‘external Data Momory that use TS:bR addresses (MOVX @DPTR). In ths application It uses strong intoral pulups ‘when emiting "1's, During accesses Yo extemal Data Morory thal use 8:bt adcrsses (MOVX @R, Port 2 emits the contents of the P2 Special Function register. Por 2 aso recieves the HIGH-order adress bts during the ‘rogramming ofthe EPROM and during rogram verfeation oF tho EPROM Port 3. (Bidirectional) Por 3 i an Bit Bidrectonal I/O port wth intaral pulups. Tho Pos 3 output buffs can sink/source four LS TTL inpus. Port 3 ins having "1's writen to thom ar pulod HIGH by the internal pulps and — while ints stato — can be used as inputs. As inputs, Port 3 pins externally being puled LOW wil souce curont () Because ofthe pulps. ort 3 also serves the functions of various special feats as istod botow Pon Pin ‘iternate Function Py] FD ore lap Font Pay [TaD (Bere Ovtput Por Pag | NTo Exoral rier) Pag INT; (Enea! rir 1), Pax [To Cer 0 era np Pas. Timer + Exorat put Pua [WR (Ener) Oats Wenory Wate Svabe) P57 [RB (exer! Data Momery Ress S1obe) RST/Vpp Reset (Input; Active HIGH) This pit is used to resat the device when neld HIGH fortwo. ‘machine cycios while the oscilator is runing, AST/Vep © held within the Vp spec, it wil supply standby power to the RAM in the event that Vcc drops Below its spec. When RST/Veo is LOW, the RAN's bias Is drawn from Voc. ALE/PROG Address Latch Enable/Program Pulse (Input/Output) ‘Address Latch Enable output puso for latching the LOW byte of the addross during accesses to extemal memory. ALE can drive eight LS TTL inputs. In normal operation ALE is omitted at a constant rate of 1/6 the oscilator frequency, allowing use for external-timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to extemal Data Memory. This pin also accepts the program pulse input (PROG) when Programming the EPROM, SEN _ Frogram Store Enable (Output; Active LOW) 'PSEN isthe red strobe to external Program Memory. PSER Can drive eight LS TTL inputs. When the device is executing code from an external program memory, PSEN is actvated twice each machine cycle — except that two PEN ‘activations are skipped during each access to external Data Momary. PSEN is not activated during fetches trom intemal Program Memory EXWpp External Kecese Enable (Input; Active LOW) EK must be extomally held LOW to enable the device to fetch code from extemal Program Memory locations 0O00H to OFFFH (0000H to TFFFH in the 6753H) i EK is held HIGH, the 8751H executes trom intemal Program Memory Unless the program counter contains an address greater than OFFFH (1FFFH in the 8753H), XTAL, Crystal (input) Ingut tothe inverting oscilator amplifier. When an external oscillator is used, XTAL; should be grounded. XTALg Crystal (Output) Cutout of the iwvering osciiator amplifier. XTAL2 is also the input for the oscilator signal whon using an extemal oteilatr. Yee Power Supply Ves Circult GroundPROGRAMMING Programming the EPROM To. program the EPROM, either the intomal or external cscilltor must be runcing at 4 to 6 MHz bocause the internal bus is used to transfer address and program data to the appropriate intemal registers. ‘The 8751H and 8753H devices support an adaptive EPROM programming algoritim in aditon to the conventional EPROM programming algorithm. Adaptive device program ring (sometimes called interactive oF inteligent program- ring) adapts to the actual charge storage efficiency of each byte, so that no wasted programming time occurs and minimum davice programming timo is realized. ‘The typical rasuling device programming tee is @ mere 7% of What Is required for a conventional programming algorthm, For example, to program a 4K byte EPROM using the ‘conventional programming algorithm wil require 4K x50 ms = 200 see. If adaptive programming Is used, the theoretical programming tie roquired will bo 4K x3 ms = 12 sec. The factual speed advantage of the adaptive programming i stil very significant even aliowing for the addtional software ‘overhead to implement the adaptive algorithm (2 to 8 sec depending on the brand of EPROM programmer), ‘To program the 8751H, pins Pz.4-P29 and PSEN should be hold LOW, and Po 7 and RST held HIGH as shown in Table 2. “The adress of the location to be programmed is apoed to Port 1 and P2.0~Pa.s while the code byte to be programmed is applied to Pon 0 (eee Figue 1), Vor should be at 21 V during device programming and the ALE/PROG pin shouid be pulsed LOW for t ms t0 program ‘the code byte into the addressed EPROM location. The Programmed byte is verified immedataly afer programming Figure 2 illustrates the flow of the adaptive programming algorithm. At each address, up 1015 program/veriy loops are attempted to very the programmabilty of the byte using 1 ms PROG pulses. After the programmabiity of @ byte 1s deter. ‘mined, an overprogramming pulse of 2 ms is applied to PROG to guarantee data retention. (This conforms with the AMD standard of 2 ms/byte overprogramming for all N-channel EPROMs) “The programing of 8753H is similar tothe above procedures fexcopt that pin Pa, is the additional address. pin (ra) for accessing the upper 4K bytes of the EPROM (so Figure 2) The 8751H and 8753H can also be programmed using the loss efficient conventional EPROM programming aor. n ths method, pis halt at 21 Vand PRIOR is pusod low or 50's to program each code bye Io the adcessod EPROM Ioeaton. Aer the memory is programmed, all edoresses would be sequenced and verted. a AA Note of Caution When Programming ‘Te maximum votage appied to tho ER/Vep pin must not exceed 21.5 Vat any time a specie for Vo. Evan a sight ‘ike can cause permanent damage tothe device. The Ver source should thus be wel-guated and git, When programming, @ 0.1% 10°F capactor is roquted cross Vp ad ground to suppress spurious transionts which may damage ne deve, ers 2 way us | ore al ven “rl snoress Figure 1. 8751H Programming Configuration 725re Kear us | pro Bl weeny ve 7 Lsooted Figure 2. 8753H Programming Configuration TABLE 1. EPROM PROGRAMMING MODES FOR THE 8751H Mode st | PSEN | ALE ca Par | Pa Pas | Pea Progam via T t vee: H t t U ro Vir Tex i t + t Veet Vie i H Vere ft t t t Seearty Set Wine c uy vee. H H t x Note: ee notes below Table 2 TABLE 2, EPROM PROGRAMMING MODES FOR THE 8753H Mode RST SEN ALE x Par Pag Pas Progam Vise v c Ver H v v Vesty Vist t H Veo L t t Secor St Mist c ro Ver x x c ogi HIGH or that pn Loge LOW or mat 0 mi care “ALE s puta LOW for 1 msc In tbe pegaming lop of the adepve programming algrtim and is pulsed LOW for 0 msec if corwantonal EPROM programming algorinm i uted ALE pba LOW for 60 moe 7-28Figure 3. Adaptive Programming Algorithm for 8751H and 8753H 727Program Verification ‘The Program Memory may be read out for verification pur- poses when the security bit has not been programmed. Reading the Program Memory may occur during of aftor programming of the EPROM. When the oscillator is running at 446 Mitz, the 8751H Program Memory adoress location to bo read is appiod to Port 1 and pins Pz.o- Pa. of Port 2. Pins Pea~Pae and PSEN aro held at TTL LOW (s00 Figure 4), ‘The 87594 utlizes Por 1 and pins Pz ~Pa.4 to address the EPROM, whilo P2s~Poe and PSEN aro held LOW (seo Figure 8). ‘The ALE/PROG and RST pins of both devices ara hela HIGH (RST requires only 25 V for HIGH) and the EA/Vpp pin voltage can have ary value trom 2.0 V to 21.5 V as shown in Tables 1 and 2, Por 0 wil then output the contents of the across location Extomal pull-ups are needed on Port 0 when verifying the 8751H and 6763H EPROM, Note: Since Vep can be eld at 21 V during program verification, the Vep pin can be connected to a static 21 V power supply for device programming and verification in the Adaptive device programming technique (see Figures 4 and 6) (Gee 1 tsoo1e2 Figure 4. 8751H Program Verification — rae rl Figure §. 8753H Program Verification 7-28Security of the EPROM ‘Tho 8751H and 8753H incorporates a security bt, which whan activated, prohibits all extemal readout of the on-chip EPROM contents. Figure 6 iusrates the socurty bit programming Configuration for both the 8751H and 8753H. To activate the ‘secuny bit, the same setup is used as wien programming the EPROM except that Pg is held HIGH. Port 0, Port 1 and pins P2q~Pag may assume any state. Vpp should be at 21 V and the ALE/BROG pin should be pulsed LOW for 50 msec. The logle stats of tho other pins are dotaled in Tables 1 and 2 ‘With the EPROM secuty BI programmed, retieval of intemal rogram Memory cannot be achieved. [A secured Program Memory looks tke @ blank array of all ‘ones, and this property can be used to verity that the EPROM Is secured. The programmed securty bit aso proniite further device programming and the execution of external Program Memory. Full unctionalty and programmabilty may be restored by ‘erasing the EPROM and thus clearing the security bit. i 8001973 ‘When programming, a 0.1 x 10°F capactor ie required across Vep and ground to suppress spurious tran- slonts which may damage the device. Figure 6, Programming the Security Bit 7-29‘Slilcon Signature Verification AMD will support siicon signature verifcation for the 8751H/ S753H. To engure that the dvice can be programmed ‘according o the adaptive EPROM programming algorithm, the manufacturer code and part code can be read from the device bofore any programming is done, To read the silicon signature, sot up the conditions as spocited in Figure 7, Noto that Pa. is now required 1o be a ‘TTL high level. Read the fist byte of the slicon signature by applying address 0000H to the device: the byte should bo a OTH, Indicating AMD as the manufacturer. Then road the second byte of the siicon signature by applying address ‘0001H to the device; the byte should be OOH, indicating the AMD 8751H/8753H product family. Erasure Characteristics Light and other forms of electromagnetic radiation can load to ‘erasure of the EPROM when exposed for extended periods of tine. ‘Wavelengths of light shorter than 4000 angstroms, euch as ‘sunlight or indoor fluorescent lighting, cen ultimately cause Inadvertent erasure and should, therefor, not be allowed to ‘0xpose the EPROM for lengthy durations (approximately one ‘nook in sunight oF three years in roomevel fluorescent lighting). It is suggested that the window be covered with an page ibe an aprleaton salt tet re doce to this type of radiation. itis recommended that ultraviolet ight (o! 57 angstroms) be used to a dose of atleast 15 W-sec/em? when erasing the EPROM. Anulvaviclet lamp rated at 12,000 uW/em? held one inch away for 20~30 minutos should be sufficient. EPROM erasure loaves the Program Memory in an "all ones state, ‘Address 0000H) ipso ‘= Manufacture Code tom Part Code = 00H Lsooteau Figure 7. 8751H/8753H Silicon Signature Verification Configuration 7-30ABSOLUTE MAXIMUM RATINGS Stocage Temperature 65 to +150°C Voltage on EA/Vpp Pin to Ves “05 to +215 V Voltage on Any Other Pin to Vs =05 10 +7V Power Dissipation 138W Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits isnot implied. Exposure to absolute ‘maximum ratings for extended periods may affect device rotabiny OPERATING RANGES Commercial (C) Devices “Temperature (Tp) 010 +70" ‘Supply Voltage (Vcc) 4450 455V Ground (Ves) ov Indust () Devices (Preliminary) Temperature (Ta). Supply Voltage (Voc) Ground (Vs. Operating ranges define those limits between whicn te ftnetonaty ofthe device 1 guaranteed DC CHARACTERISTICS over operating range unless otherwise specified Parameter Symbol Parameter Description Test conattione | win | _wax_| unite cn Tapa COW voepe cept EA =os [a8 v ‘ir Tp LOW Wotags 16 EX ° a7 v Vat Tapa HGH vowape capt TAL RST 20 [Wees0e |v Vea Top HGH Votape to BTALg, FST TR aves zs [vee =05 |v Ve put LOW Votage Pore 1 29) a 1 To. 15 mA oa [v vou ‘uit LOW votage (Por 9, ALE, PEER) erga ee Ty You | Sana WOH vakape Pore 13 Tons = 88 a 7 v x apt HV ‘one ‘ y font (Port 0 in External Bus Mode, ALE, PSEN) to -400 HA 2 . ei 0 rgd Goent ors 1.2 WarOaev = ie Tages 0 no Conant ER rm hz Legato np Comer Varo rm tu Top Celage Core (Por 8) 045 < Von Ver 7” we Lege + put Goren! EA 1” ti iopd Carer 6 RST 16 Acta Peat Vane Wests ry ‘ er vert ‘Opts Dacor me | me 5 Power Sip Cu Boe Ge Ti Canesinee Toe Freg= 1 Os nr 0 Power Down Gua Voo=0 V.vip=50 7D Toler + Capscive lasing on Pots 0 and? may cause spas rape plo o be supormposod onthe Vos ot ALE and Pots} and 3. The ole ‘Sus to etornl bus capactance aactrgng to to Por O and Pon's when thse prs ake 100 Wanatine unng bus apratons in th worst caans(capactove lose > 100 PF) he ase puso on he ALE ine ay ousoag 08 Vn such cass ay be Goose 1 ‘uaiy"ALE wi a Sohmt Trigger o use an aase lich mah SchratTegpur STROSE put “es Sen 6 Trowel Owecasix ora 731SWITCHING CHARACTERISTICS over operating range uniess otherwise speciiod (Load Capacitance for Port 0, ALE, and PSEN= 100 pF, Load Capacitance for All Other Outputs = 80 pF) a a 12 MHz Ove. Variable Oscillator ‘Symbol Description win. | Max | Min. Mex | Unite Troe Dsctaior Feuer 2 = Mr Tor ALE Puke Wath ca wa ry TavE ‘actos Sawp 10 ALE z 5 TOLL, os TAK ‘Aahons Hold Air ACE = Tete 35 Tv TALE to Vai ate 1a Teese | TRL TALE w PEN = Ta, ne Tae PEN Pune wiih 90 BTCA ne TPL EEN to Vand ire Tn To Haase] re TRAD inp si Hod Ar PEER z z rs Tex Input nai oat At PEN s Tec | re THAT Adress Vaid Aor PEER e Tae ne TAY ‘ess to Vaid rir ar OLE] re RAZ ‘Float Mer PEER 2 2 rH TRLRH "RD Pulee Wie co CLL 106 rs WLW WA Pulse wom 20, STOLL 100 re TRY FD to Vaid Oates me wre es | ne Troe ‘ate Hold Aer AD 3 3 2 TRHOZ ‘Dats Fost tor RO 7 wae |e Tubv TALE to Vat Oa si wrcucL-150_| ne TAVOY, ‘Achons to Vaid Daten 506 oreuc-165 | ne TW ALE 1 RO or WT Be_| 300 | are | arene o | TAH areas 0 FD or WF 208 “TOLL 100 re Tow Date Vala 10 WR Tranaion 3 TCLCL-79, rm Tower Data Seu Satore WH 2s TrLeL- 180 rH TwOx ‘ate Hota Ater OF = TOLL, ne TRLAZ ‘Adooas Fost Ahar FO @ = re Two FD or WF HGis w ALE HGH me _[ reese] recs | oe SWITCHING WAVEFORMS KEY TO SWITCHING WAVEFORMS, GODOT 7-82‘SWITCHING WAVEFORMS fen] ja i External Program Memory Read Cycle External Data Memory Read Cycle 7-33SWITCHING WAVEFORMS (Cont'd) pom fete fon wro0e7s7 External Data Memory Write Cycle Fs - = LPF Liisi iis ore ~ x XXX i SN 8 eS T 7 Shift Register Timing Waveforms 7-34EXTERNAL CLOCK DRIVE Ac pours oumna TESTING AA OREN A Yoc=05 Fon A LOG ‘ating wi FOR A LOGIE} AND Me MAL FOR A LOBE “D Input/Output Waveform _——_—__— rameter Parameter Symbol Description Mie. Max. nits ec DechatarFreqoonay 12 a Tare ToHEX 2 a TeLex 2 a TO.GH @ a Tot 2 os wro0e762 External Clock Drive Waveforms SERIAL PORT TIMING — SHIFT REGISTER MODE (Load Gapacitance = 80 pF) Variable Oscillator rameter Parameter ‘Symbol Description mio. [wax | Min. Max [Units To Sera For Gack Oye Te 70 Ter. z Tower ‘ups Date Soup to Cock Rang Cage 70. ToT. 138 oy “THO ‘oto Date Hold Aner Gk Fie E390 2 TOUGHT me “OK inp Oaa hoe Ata Gack ara £250 a c me “perv Glock Fig Gage 12 nput Dla Vai 7 wore | oe AC Testing Voo-04 Moan+01v, feat) =e ent aay. Muoa0-01 vousary ‘wroz0060 ‘wo20540 FOR TMING FURPOBES A PORT P16 NO LONGER FLOATING WHEN 4 [Sign Que rou Com votrase Secure avo Beans TO etane ouion #50 mn vores Float Waveform 7-35EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS a= #21 to +27°C, Voc = +5 V 10%, Vsg=0 Vp Parameter Parameter ‘syonet Dscoanen Min. Max. unite Ver Progremming Scop Volags Bs ae v top Programming Supply Curent 30 ma TAG ‘Osseo Frequency = © ure ave ‘Aaaoss Soup to PROT wareiee THA across Hold At PROS aso TDVGL ata Sot 19 PROG asrcucL THO Hos Aner PROT arcu TEHSH Fey (ERBLE) HGH 1 Vie aaTouc TSHGL Veo Sap to PROG. 70 see ToHSL Vee Hold ater FROG v0 ps2 TeLGe PROG wa 6 = msec TAVOY reece to Oaia Vaid aro TELOv TENABE 10 Date Vaid aaTGL Tenaz Dats Fost Ater ERABTE z aaTOSL EPROM PROGRAMMING AND VERIFICATION WAVEFORMS a weone719 For Programming condvons, see Figures 1, 2, and 3 For Vertication conditions, see Figures 4 and 5. For Secunty Bit Programming, see Figure 6,