2016 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC 2016).

Ixtapa, Mexico

IRIG-B decoder based on FPGA for

synchronization in PMUs by considering
different input formats
Jose R. Razo-Hernandez a, Martin Valtierra-Rodriguez a,*, Member, IEEE, David Granados Lieberman b,
Member, IEEE, Juan P. Amezquita-Sanchez a, Luis A. Morales-Hernandez a, and Aurelio Dominguez-Gonzalez a
a
Facultad de Ingeniera, Universidad Autnoma de Quertaro, Campus San Juan del Ro, Ro Moctezuma 249,
Col. San Cayetano, 76807, San Juan del Ro, Quertaro, Mxico.
b
ITESI Departamento de Ingeniera Electromecnica, Instituto Tecnolgico Superior de Irapuato, Carr.
Irapuato-Silao km 12.5, Colonia El Copal, Irapuato, Guanajuato, Mxico.

*Corresponding author: [Link]@[Link]

long distances in the electrical power transmission. Here, the

Abstract Time synchronization (TS) represents an important main idea is to be able of measuring the state of the network in
necessity for many industries in fields such as communications, different points at the same time, which is achieved by means
manufacturing, and power systems related to electrical networks, of a TS. It is generally referred to a global time provided by a
microgrids, and renewable energies, among others, because it can
ensure that cooperating processes or systems can interoperate
GPS [1]. One of the most advanced systems is the Phasor
correctly; further, the scheduling of specific tasks through a Measurement Unit (PMU) or Synchrophasor. In general, they
timestamp can be done. Among different synchronization provide the phasor measurement of voltage and current signals
protocols, the inter-range instrumentation group (IRIG)-B time at specific points of the network with a timestamp. Also, they
code has become one of the most employed in real-time provide very high synchronized measurements thanks to the
information transmission systems because of its accuracy, Global Positioning System (GPS), providing the most direct
robustness, and simplicity. In this paper, a field programmable
gate array (FPGA)-based IRIG-B decoder is presented. The
access to the state of the power system at any given instant.
FPGA used is a Cyclone IV EP4CE115F29; yet, the proposed The synchronization of these systems is key in monitoring,
hardware implementation has a vendor independency. On the protection, control, and state estimation in power systems [3-
other hand, the IRIG-B output is provided by a SEL-2401 4]. For this instance, in [5] a synchronized voltage phasor
Satellite-Synchronized Clock. Results show that the proposal can measurement in wide area protection and control schemes is
provide a reliable and accurate time source using the IRIG-B presented. Further, a Tracking network state using both
time code. Regarding the FPGA, a low resource usage of the chip
is obtained; besides, thanks to its high capabilities of integration
Supervisory Control and Data Acquisition (SCADA) and
and parallelism, a widely number of applications can be synchronized phasor measurement is approached by [6].
incorporated. Other applications in communications, manufacturing, and
militia are focused in preventing the appearance of anomalies
Index Terms FPGA, IRIG-B time code, satellite-synchronized- of faults or damages through the continuous monitoring. For
clock, time synchronization. example, a data acquisition system (DAS) based on Field
Programmable Gate Array (FPGA) with a time stamp
provided by a GPS is presented in [7]. It can also store data
I. INTRODUCTION from multiple channels with a resolution up to 20-

T IME SYNCHRONIZATION (TS) based normally on marks or

timestamps is very important because it provides an
accurate interoperation of monitoring and control systems.
microsecond, which is possible thanks to the parallelism and
high performance of such technology [8]. Regarding
monitoring area, in [9], the authors describe a monitoring
This ensures through a time reference the correct and suitable system based on LabVIEW, which is developed for the
sequence of events in a process. Nowadays, the exponential evaluation of Progressive Deterioration of a Squirrel-Cage
technological advancement has allowed the development of Rotor. Another contribution about monitoring is presented in
new equipment with a noticeable improvement in the accuracy [10], where a prototype to perform the monitoring
and stability of global sources of location and time, being the measurement and control of electrical loads in residential
most important the global positioning systems (GPS). applications in order to avoid an excessive consumption is
Among the synchronization applications, it can be presented. On other hand, the surveillance of the equipment
highlighted those related to the power systems because of the integrity based on TS to protect, connect and activate
This work is supported by PRODEP UAQ-PTC-331 under the FIN2016 peripherals is used in [11]; besides, it puts the microprocessor
project. in a power saving mode simultaneously and if is required it
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 2016 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC 2016). Ixtapa, Mexico

enters into a mode of work scheduled in the same manner. In Synchronized Clock SEL-2401 is used to provide the time
[12-13], military applications which include surveillance, information for the level shift protocol. Bearing in mind that
target tracking, counter-sniper systems or surveillance of the purpose of the other two digital structures is the same, the
battlefield information to soldiers and vehicles involved in the VHDL simulation is presented only. Regarding the FPGA, a
combat are discussed. Other application related to power Cyclone IV EP4CE115F29 into a DE2-115 is used for rapid
quality monitoring is presented in [14], where a prototyping; however, the developed digital structure has a
synchronization with the voltage/current signal is desired. vendor independency. Results show a low consumption of the
Finally in [15], a review of the current state of the art of wide FPGA resources, making the proposal a suitable system-on-a-
area control systems (WACS) incorporating flexible ac chip (SoC) solution, which can be integrated to many
transmission systems (FACTS) devices, specifically, the applications that require a TS such as PMUs.
different FACTS configurations, applications and control is
presented. II. DESCRIPTION OF IRIG-B CODE
For TS and timestamps, there are different standards and Among other things, the Range Commanders Council is the
protocols that regulate the data profile. In the IEEE 1588 responsible for the standard IRIG Time Codes, which have
standard [2], the requirements and features in experimental been used for many years in communications between
tests to explore a Precision Time Protocol (PTP) and instrumentation systems worldwide. The most commonly used
determine how new requirements can affect the performance format is the IRIG-B time code due to its suitability in terms
of the power distribution applications of next generations are of robustness, precision, and simplicity. An example of the
addressed. On the other hand, the Inter Range Instrumentation aforementioned is that the 1 kHz amplitude modulated version
Group (IRIG)-B code is one of the most widely used as a can be carried for several hundred meters over standard
standard interface to transmit a pulse per second (PPS), where coaxial cable without perturbations. Therefore, despite
the time information is continuously coordinated; besides, it existing more recent protocols and their corresponding
has the advantages of increasing the reliability, consistency, implementations, IRIG will certainly maintain a place in
and accuracy of the time information [16]. In general, the instrumentation systems for many years [4].
IRIG-B code has three common ways of transmission The characteristic that distinguishes different IRIG time
according to the used device, being level shift, amplitude code formats is primarily resolution, which directly relates to
modulation (AM), and Modified Manchester coding. data rate. On one end of the scale is IRIG D, with a time
Having in mind the number of applications that require TM, frame (how long it takes to transmit a complete set of
such as PMUs, communications, militia, and manufacturing information) of 1 hour, and at the other end is IRIG G, with a
processes, among others, and by considering that the IRIG-B time frame of 0.01 seconds. IRIG B has a "time frame" of 1
code is one of the most command formats for TS, it would be second, and that time frame is divided into a data rate of 100
desirable to have a device that can decode the three ways of Hz to provide the day time and the day of the year
transmission of IRIG-B, which can provide a TS for the information. The most commonly found forms of IRIG B are
aforementioned applications regardless the used device. In this level shift (pulse width), modified Manchester, and amplitude
article, a general digital structure based on FPGA technology modulated (AM).
to implement the three ways of decoding for IRIG-B code is In general, the IRIG-B code is a serial time code of one
presented. In order to achieve a general implementation, the frame per second, in which the velocity is 100Bits/m is the
VHSIC (Very High Speed Integrated Circuit)-hardware most common implementation. It has three kinds of code
description language (VHDL) code is preferred. The Satellite- elements which are F (position flag), H (high or 1), and L

Fig. 1. IRIG-B Coding Comparation.

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 2016 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC 2016). Ixtapa, Mexico

(low or 0) according to their pulse width, being 8ms, 5ms,

2ms respectively, as shown in Fig. 1. Other format for IRIG-B
transmission is the AM encoding, which has a sine wave
carrier to be amplitude modulated by a time code. A higher
amplitude indicates a high level of DC, a lower amplitude
indicates a low level of DC, as shown in Fig. 1. An F
reference value is given by eight ones and two zeros, a H
value (1) is given by two ones and eight zeros, finally, an L
value (0) is given by five ones and five zeros. Additionally,
the last way of IRIG-B transmission, the Manchester encoding
employs a square wave as the encoding (data) clock, with the
Fig. 3. General Digital IRIG Structure .
rising edge on-time with Coordinated Universal Time. The
encoding clock frequency must be ten times the index rate of methodology for the different types of signals, depending on
the time code generated (see Fig. 1). This modulation the type of device that generates the IRIG-B signal. It should
technique has several advantages: no dc component can be ac be noticed that the type of input signal (level shift, AM,
coupled, it has a better signal-to-noise ratio and a good Manchester) determines the digital structure to be used. At the
spectral power density; further, it can be easily decoded, and end of each digital structure, there are different output signals:
has better timing resolution. The Modified Manchester coding IRIG one (O), IRIG zero (Z), IRIG reference (F) and enable.
technique is designed to operate over fiber-optic or coaxial The former indicates when the data is valid and can be
lines for short distances [16]. In this format, the decoding is stored in order to be used by the next process, called Storage
performed in the same way that the AM one but with a square and Display (shown in detail in Fig. 4), which saves the ones,
signal. zeros, and reference values in order to be displayed (date and
The IRIG-B code contains time information about date time). Also, this module gives one pulse per second, in order
(days and years), hours, minutes, seconds and control to be used for synchronization purposes with other tasks, and
information. Time information is expressed using Binary- the estimated values of seconds, minutes, hours, days, months,
coded decimal (BCD) format. At the end of the time and years that are contained in the input signal.
information, 27 bits of control and 17 bits for straight binary The level shift implementation, depicted in Fig. 5a, uses a
seconds are given; however, they are barely used. In Fig. 2, it common signal acquired from a satellite-synchronized clock,
is seen that the beginning of data can be distinguished with a which is a train of pulses of different widths. It should be
start of the frame by seeing two bits of mark (P). After 8 bits, pointed out that the voltage levels of this signal might not be
the seconds can be codified depending on the position appropriate to be directly by the FPGA; hence, the signal must
occupied and if it is a one or a zero. It can be expressed be pre-processed in order to be properly acquired by the
directly in BCD or can be multiplied by their weights for implementation platform. Once it is acquired by the FPGA, a
further decoding, i.e. decimal format. Then, the next bit mark finite state machine (FSM) is used to detect changes in the
is set to indicate that the followings 8 bits expresses the input signal; when a rising edge is detected, a synchronization
minutes, where there are two bits that are not used. Next,
another mark bit is used for decoding the minutes, hours, and
days. Finally, the years are decoded into a range from 0 to
100.
III. SYSTEM ARCHITECTURE
In order to perform the implementation of the different
forms of IRIG-B decoding, a general digital structure based on Fig. 4. Storage and Display .
FPGA is developed using VHDL. Fig. 3 shows the general

Fig. 2. Codification Information.

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 2016 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC 2016). Ixtapa, Mexico

Fig. 5. Digital Structure of IRIG-B: a) Level Shift, b) Modulated Amplitude, and c) Modified Manchester.

signal is set, and a counter starts its operation. When the input they are a IRIG zero, IRIG one or IRIG reference. It is worth
signal has a falling edge, then the counter stops its operation, noting that an IRIG zero has eight zeros and two ones, an
and the value is decoded by a comparator. Within the IRIG one is composed by five ones and five zeros, and an
comparator, depending on the value of the counter, it is IRIG reference has eight ones and two zeros. Once the
decoded as: IRIG zero, IRIG one, or IRIG reference, samples are decoded into its IRIG equivalent, the information
respectively. The comparator output is passed to the storage is sent to the next process the storage and display block, which
and display block, where ones and zeros are stored in a right is the same for the three structures (see Fig. 4).
shift register: The data is valid depending on the enable signal For the Manchester-modified encoding, a similar AM
that comes from FSM. After the 100 bits per second (from 0 to process is employed with the difference that an ADC and a
99 in the counter), the data is loaded into a final register and comparator are not needed because the input signal is a digital
hence the multiplication of the weights shown in Fig. 2, the one. It is only necessary to determine if they are zeros or ones.
date and time are displayed on the liquid-crystal display These values are sent to a shift register and compared
(LCD). A second shift register is used for detecting the two according to the IRIG number definitions. This digital
mark bits, which is very important in order to ensure that the structure can be seen in Fig. 5c.
data will be completely saved; otherwise, the data would be in For validation and testing purposes, a clock synchronized
the middle of a process. The Counter 0-99 only gives the pulse satellite of Schweitzer brand Engineering Laboratories (SEL)
of synchronization when the data has received one hundred of 2401 is used hereafter. It is worth noting that its main
bits (zeros, ones, and mark bits).
Fig. 5b shows the digital structure for the AM encoding. In
this digital structure, the IRIG-B is also conditioned, since the
device provides is an analog signal. To this purpose, an
analog-to-digital converter (ADC) of 12 bits is used. Once this
signal is captured by the ADC, the samples are analyzed. In
this work, by considering that 12 bits allows a range from 0-
4095, one value in the range from 2700 to 4095 can be
considered as the large amplitude (a one) and the small
amplitude has a range of values from 1365 to 2700 (a zero).
These samples are processed by a finite state machine (FSM);
which also detects the positive edge of a 1 kHz reference
signal, used to start the process. As the sampling frequency
used is 10 kHz, 10 samples will be obtained, which will be
compared to decide whether they can be decoded as a one or
zero; then, this one or zero is stored in a register to verify if Fig. 6. SEL- 2401 Satellite-Synchronized Clock.

978-1-5090-3794-0/16/$31.00 2016 IEEE

 2016 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC 2016). Ixtapa, Mexico

is also observed. As can be seen, the digital structure gives the

enable data flag and specifies that this value is a one,
activating the corresponding flag, so that the next process,
storage and display, can begin to decode this signal. Fig. 8b
shows the digital structure for the modified Manchester. The
simulation shows the IRIG-one, IRIG-Zero, IRIG-Flag and the
enable, where after 100 bits of data, the process of storage and
displays is in charge to decode these signals and generate the
final information and the 1 pps (pulse per second).
In order to test the level shift encoding, the experimental
setup shown in Fig. 9a is carried out. First, a simple signal
conditioning stage is performed in order to provide proper
voltages from the SEL 2401 to the FPGA running at a
frequency of 50 MHz. Then, the digital structure presented in
Fig. 7. Real IRIG-B signal provided by the SEL-2401.
Fig. 3 for level shift is synthetized into an FPGA DE2-115
application is for PMUs, since it satisfies the requirements Terasic board. As previously mentioned, the obtained time
stated in [16]. The Satellite-Synchronized Clock is shown in information is shown in the LCD of the implementation board.
Fig. 6. As can be observed, the level shift signal is provided Regarding the synchronization pulse, it is placed on a
through a BNC connector. The signal coming directly from digital output to be monitored using an oscilloscope, as shown
the clock synchronizer is shown in Fig. 7. It depicts several in Fig. 9b. It is worth noting that each pulse appears each
pulse widths corresponding to the mark bit (8 ms), the one bit second and has to have duration of a clock cycle; however, if
(5 ms), and the zero bit (2ms). the time resolution of the oscilloscope is adjusted with the
Regarding the proposed digital structure for level shift, the intention of seeing two pulses, they will not be perceptible. In
main entity shown in Fig. 3, and by considering the module in this regard and for observation purposes, an arrangement using
Fig. 5a, consists of an input that receives the IRIG-B signal a flip-flop to make more evident the synchronization pulse is
and two outputs, one to provide the synchronization pulse and used. It consists of considering the changes of value from 0 to
the second one to present the time information. 1 or from 1 to 0 as the synchronization pulse.
Finally, Table I summarizes the hardware implementation
IV. RESULTS resources used by the proposed architecture. As can be
To demonstrate the operation of the different digital observed, the overall proposed methodology takes less than 1
percent of the overall total logic elements, which is measured
structures proposed in this paper, the simulations and FPGA
for both the dedicated logic registers and the total
synthesis level shift structure are presented. Fig. 8a shows the
TABLE I
simulation for the digital AM decoded structure. In this figure
RESOURCE USAGE OF THE FPGA FOR THE LEVEL SHIFT FORMAT
can be distinguished the signals, U, and Ze, which represents
the output signals, one (O) and Zero (Z), in the digital Resource Used Available Used percentage
structure shown in Fig. 5b. These signals are only active
utilization (%)
depending on the value of the input signal. To illustrate this,
the values 2600 and 2900 are shown. The structure is able to Total combinational 73 114 480 < 1%
detect when the value is 2600, which activates the Zero flag, functions
along with the enable data signal, in order to store and display
Logic Register 232 114 480 <1%
it. On the other hand, a value of 2900, which represents a one,

Fig. 8. AM and Manchester Simulations. a) AM digital structure. b) Complete Modified Manchester structure.

978-1-5090-3794-0/16/$31.00 2016 IEEE

 2016 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC 2016). Ixtapa, Mexico

a) b)
Fig. 9. Experimentation: a) Test bench and b) synchronization pulses.

combinational functions. These results demonstrate that the data mining, ACM Trans. Comput. Syst., vol. 21, no. 2, pp. 164-206,
May 2003.
proposal can be implemented in a low-cost FPGA with few
[2] J. Amelot, J. Fletcher, D. Anand, C Vasseur, Ya-Shian Li-Baboud, J.
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