NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

EXPERIMENT NO.1

Date:

Aim:- Determination of chlorine demand, break-point chlorination and free residual chlorine.
a) To determine the chlorine demand of the given water sample.
Apparatus:BOD bottles, conical flask, burette, pipette, measuring jar, funnel, beakers.
Reagents:0.01N Sodium thiosulphate, KI solution, Glacial acetic acid and Starch solution
Theory:Chlorine is used as a disinfectant in water. The chlorine demand of water is the difference
between the amount of chlorine applied and the amount of free chlorine left after the contact
period as residue. The optimum dose of chlorine for given water is therefore generally
determined experimentally by adding varying amounts of chlorine to the given sample and
observing the residual chlorine left after a contact period of about 20 minutes. The dose, which
leaves a residual of 0.2 mg/l, is then selected. This total dose minus the free residual will
automatically represent the chlorine demand of water.
Procedure:1. Take 6 clean BOD bottles and add 200m1 of homogenous water sample to each.
2. Add 0, 2, 4, 6, 8 ml of chlorinated water (known strength) to each bottle respectively.
3. Put stopper and Shake well. Allow it to remain so for about 20 minutes. Chlorine reacts with
the organic matter and oxidizes it and also kills the bacteria present in the sample
4. After contact period, add 1gm KI and 5ml glacial acetic acid to each of these bottles.
5. Titrate this solution with 0.025 N Sodium thiosulphate. The solution turns from deep yellow
to pale yellow.
6. Add 2 to 3 drops starch indicator. The appearance of blue color indicates the presence of
chlorine.
7. To estimate the amount of chlorine left in the sample as residue, it can be titrated against 0.01
N Na2S203 till the end point is reached, which is indicated by the disappearance of blue color.
8. The chlorine demand is given by the difference between the applied Chlorine and the residual
chlorine after the contact period.
Observations for Residual Chlorine:Trial No

Initial Reading

Final reading

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Difference

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Calculation:S.No.

BOD
ml of chlorine
bottle No added

mg of chlorine
added to 1000
ml

Residual
chlorine
[mg/l]

Chlorine
Demand [mg/l]

Result:-

b) To determine the residual chlorine present in the given sample of water by Iodometric
method.
Apparatus
Conical flask, burette, pipette, measuring jar, funnel, beakers.
Reagents
0.1N Sodium thiosulphate, Glacial Acetic acid, KI solution and Starch solution indicator.
Principle
Chlorine present in water reacts with KI and iodine is liberated, when starch is used as indicator,
the presence of blue color produced indicates the presence of Iodine.
Procedure
1.
Take 25m1 of water sample in a BOD bottle.
2.
Add 1gm of KI crystals and 5ml of glacial acetic acid, Mix thoroughly. Wait for 15-20
minutes (contact period)
3.
Titrate this solution with 0.025 N Sodium thiosulphate. The solution turns from deep
yellow to pale yellow.
4.
Add 2 drops of starch solution. The solution becomes blue in color.
5.
Continue the titration till the blue color turns colorless.

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Sample collection, preservation and storage

Chlorine in aqueous solution is not stable, and the chlorine content of samples or solutions,
particularly weak solutions, will decrease rapidly. Exposure to sunlight or other strong light or
agitation will accelerate the reduction of chlorine. Therefore, chlorine determination should be
done immediately after sampling, avoiding excessive light and agitation. The sample should not
be stored for analyses of residual chlorine.
Observation
Trial No

Initial Reading

Final reading

Difference

Calculation:Amount of residual chlorine = [V x N x 35.46 x 1000] / ml of sample =

mg/l.

Where
V = volume of sodium thiosulphate run down.
N = Normality of sodium thiosulphate.
Result:-

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

EXPERIMENT NO.2

Date:

AIM:- Estimation of Na and K in sewage sample, wastewater and natural water

a) To determine the concentration of Sodium in given water sample by Flame Photometer.
Apparatus:- Flame photometer
Reagents:- Stock sodium solution, Intermediate sodium solution, Standard sodium solution
Storage:Store samples containing low sodium concentrations or alkaline samples in polyethylene bottles
to eliminate the possibility of sample contamination due to leaching of the glass container.
Principle of Quantification:Trace amounts of sodium can be determined by flame emission photometry at the wavelength of
589 nm. The sample is sprayed into a gas flame and excitation is carried out under carefully
controlled and reproducible conditions. The calibration curve may be linear but has a tendency
to levels off at higher concentrations.
Procedure
1.
Follow instructions of flame photometer manufacturer for selecting proper photocell,
wavelength, slit width adjustments, fuel gas and air pressure, steps for warm up, correcting for
interference and flame background, rinsing of burner, sample ignition and emission intensity
measurements.
2.
Prepare a blank and sodium calibration standards, in any of the applicable ranges, 0-100,
0-10, or 0-1 mg Na/l. Set instrument zero with standard containing no sodium.
3.
Measure emission at 589 nm and prepare calibration curve.
4.
Determine sodium concentration of the sample, or diluted sample, from the curve.
Calculation
Dilution

mg Na/l =

mg Na/l [from the calibration curve] x Dilution

where,

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Observations
Sample Size
0
5
10
15
25
Unknown Sample

Absorbance

Result:-

b) To determine the concentration of Potassium in given water sample by Flame

Photometer.
Apparatus
Flame photometer
Reagents
Stock Potassium solution, Intermediate potassium solution, Standard potassium solution
Storage
Do not store samples in soft-glass bottles because of the possibility of contamination from
leaching of the glass. Use acid washed polyethylene or borosilicate glass bottles. Adjust sample
to pH <2 with nitric acid. This will dissolve potassium salts and reduce adsorption on vessel
walls.
Principle of Quantification
Trace amounts of potassium can be determined in either a direct-reading of internal standard
type of flame photometer at a wavelength of 766.5 nm. The sample is sprayed into a gas flame
and excitation is carried out under carefully controlled and reproducible conditions. The
calibration curve may be linear but has a tendency to levels off at higher concentrations.
Procedure
1. Follow instructions of flame photometer manufacturer for selecting proper photocell
wavelength, slit width adjustments, fuel gas and air pressure, steps for warm up, correcting
for interference and flame background, rinsing of burner, sample ignition and emission
intensity measurements.

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DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

2. Prepare a blank and potassium calibration standards, in any of the applicable ranges, 0-100,
0-10, or 0-1 mg/l. Calibrate instrument, set instrument to zero absorbance with blank solution
containing no potassium.
3. Measure emission at 766.5 nm and prepare calibration curve.
4. Determine potassium concentration of the sample, or diluted sample, from the curve.
Calculation
mg K/l =

mg K/l [from the calibration curve] x Dilution

Where,
Observations
Sample Size (ml)

Absorbance

0 [BLANK]

Unknown Sample

Result

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

EXPERIMENT NO.3

Date:

AIM:- Determination of Nitrate-nitrogen of nitrate nitrogen from the given wastewater samples
Apparatus:- Spectrophotometer or Colorimeter, Nessler tubes (capacity-100ml), Beakers
(capacity-100ml) and Water bath.
Reagents:1. Stock nitrate solution
2. Standard nitrate solution
3. Standard silver sulphate
4. Potassium Hydroxide [12N]
5. Phenol di- sulphonic acid (PDA)
6. Concentrated Ammonium hydroxide [NH4OH].
Principle:Nitrate reacts with Phenol di-sulphonic acid and produces a nitro-derivative which in alkaline
medium develops a yellow color. The color produced follows the Beer's law and is directly
proportional to the concentration of nitrate present in the sample.
Procedure:1. Take 50ml of filtered sample in an Erlenmeyer flask.
2. Add an equivalent amount of silver sulphate to remove chlorides (1
mg/l Cl = l ml Ag2SO4 solution)
3. Heat slightly and filter the precipitate of AgCl.
4. Evaporate the filtrate in a porcelain disc to dryness.
5. Cool and dissolve the residue in 2m1 phenol di-sulphonic acid and dilute to 50 ml.
6. Add 10 m1 of liquid ammonia to develop the yellow color.
7. Read the color developed at 410 nm with a light path of 1cm.
8. Calculate the concentration of nitrate nitrogen from the standard curve.
9. Prepare the standard curve using suitable aliquots of standard nitrate solution in the
range of 5-500 mg NO3-N following the above procedure.
Interferences:Chlorides and nitrite are the two main sources of interferences. Pretreatment of sample is
necessary when the interfering radicals are present.
Result:Environmental Significance:In surface waters, nitrate may cause objectionable eutrophication. Nitrates are poisonous to
infants, animals including humans. In humans it can cause 'methemoglobinemia'.
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DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

EXPERIMENT NO.4

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Date:

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

AIM:- Determination of iron from raw sewage, wastewater, natural surface water and compare
the results
Apparatus:- Nessler's tubes (100 ml), Conical flasks, Pipettes, Colorimeter.
Reagents:- Conc. HCl acid, Hydroxylamine hydrochloride solution, Ammonium acetate buffer
solution, 1, 10-Phenanthroline solution, Stock Fe soln. and Std Fe soln. (1ml = 1 mg Fe).
Principle:In the Phenanthroline method, the ferric form of iron is reduced to ferrous form by boiling with
hydrochloric acid and hydroxylamine hydrochloride. The reduced iron chelates with 1,10
H
phenanthroline at p 3.2 - 33 to form a complex of orange-red color. The intensity of color is
proportional to the concentration of iron and obeys Beer's law.
Procedure:1. Pipette 10, 20, 30 and 50m1 of standard iron solution into 100m1 conical flask
2. Add l ml of Hydroxyl amine hydrochloride solution and 1m1 of sodium acetate
solution to each flask.
3. Dilute each to about 75m1 with distilled water and Add 2ml of 1,10-phenanthroline
solution to each flask.
4. Make up the contents of each flask exactly to 100m1 by adding distilled water and allow
at least 10-15 minutes for maximum color development.
5. For visual comparison pour the solution in 1.00 m1 Nessler tubes and keep them in a stand.
Mix the sample thoroughly and measure 50ml into a conical flask
8. Add 2 ml of concentrated HCl and 1 ml of Folderol amine solution and a few glass
beads. Boil the contents to half of the volume for dissolution of all the iron
9. Cool the flask to room temperature and transfer the solution to a 100 m1 Nessler tube
10. Add 10m1 of Ammonium acetate buffer solution and 2m1 Phenanthroline solution and
dilute to 100m1 mark with distilled water. If the sample contains interference of heavy metals
add 10m1 of Phenanthroline instead of 2m1
11. Mix thoroughly and allow at least 10-15 minutes for maximum color development
12. For visual comparison, match the color of sample with that of the standards prepared in
steps 1-6 above
13. The matching color standard will give the concentration of iron in the sample
For photometric measurement, use light path at 510nm. Read standards against distilled water
set at zero absorbance and plot a calibration curve, including a blank. If samples are coloured or
turbid, carry a second set of samples through all steps of the procedure without adding
Phenanthroline.
Observations:Sample

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Conc.

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Environmental Significance
Long time consumption of drinking water with a high concentration of iron can lead to liver
diseases. Iron rich water exposed to the air becomes turbid and highly unacceptable from the
aesthetic view point.

EXPERIMENT NO.5

Date:

AIM:- MLSS and MLVSS. Sludge Volume Index (SVI) and development of sludge settling
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DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

characteristics curve and design of PST based on settling curve.

EXPERIMENT NO.6

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Date:

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

AIM:- Determination of the Biochemical Oxygen Demand (BOD) for a given sample of
Wastewater.
Apparatus:- BOD bottles, burette, pipette, conical flask, measuring jar.
Reagents:1. Magnesium sulphate solution
2. Alkali Iodide azide
3. Concentrated Sulphuric acid
4. Starch solution
5. 0.025 N Sodium thiosulphate (Na2S203)
6. Phosphate buffer
7. Calcium chloride
8. Ferric chloride
Theory:BOD is the amount of oxygen required to stabilize the organic matter present in wastewater. The
degree of magnitude of BOD depends on the amount of organic matter present in the wastewater
and temperature during the experiment. The rate of oxygen demand or the process of
stabilization on the organic matter is very high or rapid in the initial stage i.e. 1-7 days. This is
mainly due to the oxidation of carbonaceous matter present in sewage. The oxidation of the rest
is done due to nitrification. The time required for complete oxidation is infinite, but it is limited
to 20 days. For practical purpose the period of oxidation is taken as 5 days. Then 70%-80% of
oxidation will be completed within first 5 days itself.
Principle:The standard test temperature is 20C. This temperature is taken as the temperature of
natural water. There are 2 methods for determining the BOD.
1. Direct method: In this method BOD is directly calculated. This method is applicable only
for wastewater whose BOD value is < 7mg/l.
2. Dilution method: This test is made with various dilutions.
The following dilutions are suggested,
a. 0.1% to 7% - Strong trade waste
b. 1% to 5% - for raw or settled waste
c. 5% to 15% - for treated effluent
d. 25% to 100% - river water
Procedure:1. Place the desired volume of distilled water in a 5 litre flask (usually about 3 litres of
distilled water will be needed for each sample).
2. Add 1ml each of phosphate buffer, magnesium sulphate solution, calcium chloride
solution and ferric chloride solution for every litre of distilled water.
3. Seed the sample with 12 ml of settled domestic sewage.
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DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

4. Saturate the dilution water in the flask by aerating with a supply of clean compressed air
for at least 30 minutes.
H
5. Highly alkaline or acidic samples should be neutralized to p 7.
6. Destroy the chlorine residual in the sample by keeping the sample exposed to air for 1-2 hours
or by adding a few ml of sodium sulphite solution.
7. Take the sample in the requisite concentrations as per dilution method
8. Add the required quantity of sample (calculate for 650 ml dilution water the required
quantity of sample for a particular concentration) into a 1000 ml measuring cylinder. Add the
dilution water up to the 650mL mark.
9. Mix the contents in the measuring cylinder.
10. Add this solution into two B.O.D. bottles, one for incubation and the other for
determination of initial dissolved oxygen in the mixture.
11. Prepare in the same manner for other concentrations and for all the other samples.
12. Lastly fill the dilution water alone into two B.O.D. bottles. Keep one for incubation and
the other for determination of initial dissolved oxygen.
13. Place the set of bottles to be incubated in a B.O.D. incubator for 5 days at 20C. Care
should be taken to maintain the water seal over the bottles throughout the period of incubation.
14. Determine the initial dissolved oxygen contents in the other set of bottles and note down
the results.
15. Determine the dissolved oxygen content in the incubated bottles at the end of 5 days
and note down the results.
16. Calculate the B.O.D. of the given sample.
Overview of Procedure:1. Prepare the required dilution of the sewage sample.
(For 1% dilution 1/100 300= 3 ml of sewage is taken in the BOD bottle and diluted to 300
ml with aerated distilled water).
2. Determine the DO of this sample, which is the zeroth day DO or initial DO.
3. In another BOD bottle, prepare the sample of same dilution as before. Keep this sample
in a BOD incubator at 20C for determining the DO after 5 days to get D2 (final DO or
DO after 5 days.)
Calculations:BOD5= (D1-D2)/P mg/l
D1= Zero day or initial DO (before incubation)
D2 = DO after 5 days (final or DO after incubation)
P = % dilution (1% = 1/100 = 0.01)
Observations for D1:Trial No

Initial Reading

Final reading

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Difference

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Observations for D2:Trial No

Initial Reading

Final reading

Difference

Result:-

EXPERIMENT NO.7

Date:

AIM:- Determination of the Chemical Oxygen Demand (COD) for a given sample of
Wastewater.

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Apparatus:Reflux apparatus of capacity 500m1 with a condenser, Burner or hot plate, 250 or 500mL
Erlenmeyer flask with standard (24/40) tapered glass joints, Friedrichs reflux condenser (12
inch) with standard (24/40) tapered glass joints, Volumetric pipettes (10, 25, and 50ml capacity),
Burette, 50ml with 0.1ml accuracy, Burette stand and clamp, Analytical balance, accuracy
0.001gm, Spatula, Volumetric flasks (1000ml capacity), glass beads.
Reagents:0.25N Std Potassium-dichromate (0.04167 M), Conc. Sulphuric acid reagent, (0.25M) Std
Ferrous ammonium sulphate , Ferroin indicator, Mercuric sulphate crystals, analytical grade and
Standard Potassium hydrogen phthalate (KHP)
Principle:The organic matter gets oxidized completely by K2Cr2O7 in the presence of H2SO4 to produce
CO2 and H2O. The excess K2Cr2O7 remaining after the reaction is treated with Ferrous
Ammonium Sulphate .The dichromate consumed gives the oxygen required for oxidation of the
organic matter.
Procedure:Standardisation
Dilute 10 ml standard K2Cr2O7 to about 100 ml, add 30 ml conc.H2SO4, cool. Add 2 drops of
ferroin indicator and titrate with FAS.

Estimation
Place 0.4 gm. HgSO4 in a reflux flask. Add 20 m1 sample or an aliquot of sample diluted to
20m1 with distilled water. Mix well and add glass beads followed by 10 m1 Std K2Cr2O7. Add
slowly 30 m1 H2SO4 containing Ag2SO4, mixing thoroughly. Connect the flask to the condenser
and mix the contents before heating. Reflux for a minimum period of 2 hours, cool and wash
down the condenser with distilled water. Dilute to about 150 m1, cool and titrate excess
K2Cr2O7 with 0.1 N FAS using Ferroin indicator. Sharp color change from blue green to wine
red indicates the end point. Reflux the blank in the same manner using distilled water instead of
the sample.
Calculation:COD (mg/l) = [ ( a b) 8000 N ] / ml of sample.
Where a & b = ml of FAS for blank and sample respectively.
N = Normality of FAS (0.1 N)

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Observation:Trial No

Initial Reading

Final reading

Difference

Result:-

EXPERIMENT NO.8

Date:

AIM:- Determination of the Optimum Alum Dose for a given sample of water through Jar Test.
H

Apparatus:- Glass beakers, Jar test apparatus, Nephelometer, Pipette, p meter.

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Reagents:- Alum
Theory:The public water supplies consists of very fine particles of clay, silt etc. which are present in a
finely divided state and it is not possible to detain them in primary sedimentation tanks unless
they are designed for longer detention periods. The other way to remove them is to increase their
size so that they become settleable, by adding certain chemicals called coagulants, which react
with impurities in water and convert them into settleable size. Some common coagulants used
are Alum, Sodium aluminate, ferric chloride, copperas, chlorinated copperas, ferric sulphate etc.
Procedure:1. Prepare standard solution of coagulant say 1% solution, by dissolving 5gm of alum in
distilled water and making upto 500m1.
The strength of the solution = 1% (1m1 = 10mg)
2. Take 1-litre beakers and fill them with sample up to the mark.
3. Keep each beaker below each paddle and lower the paddles, such that each one is about
1cm above the bottom.
4. Find the pH of the sample and adjust it to 6 to 8.5.
5. Pipette 1, 2, 3, 4, 5, 6 ml of the alum solution into the test samples, i.e. the dosage is 10,
20, 30, 40, 50 and 60mg respectively.
6. Immediately run the paddles at 100 rpm for 1 minute.
7. Reduce the speed to 3040 rpm and run at this rate for 30 minutes.
8. Stop the machine, lift out the paddles and allow to settle for 30 minutes.
9. Find the residual turbidity of the supernatant using Nephelometer.
10. Plot a graph with alum dosage along x-axis and turbidity along y-axis.
11. The dosage of alum, which represents least turbidity, gives Optimum Coagulant
Dosage.
12. Repeat steps 110 with higher dose of alum, if necessary.
Note
Strength of solution: 1 gm. = 100m1

Observation:Jar
No

Description of
the sample

ml of
coagulant
added

II Semester Wastewater quality analysis

mg of
coagulant
added

Concentration
mg/l

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Conclusion:-

EXPERIMENT NO.9

Date:

AIM:- Estimation of fecal coliform (total coliform) from the swage and drinking water samples.
Apparatus:- Incubator, fermentation tubes, test tubes, EMB agar plate, Petri-dishes,
microscopes, Autoclave, Pipettes, Measuring jars, Inoculating equipment [platinum loop],
Media preparation utensils.
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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Reagents:1. Lauryl tryptose broth

2. Brilliant green lactose bile broth
3. Endo methylene blue agar.
4. Eosin methylene blue agar.
5. Lactose broth
Theory:Coliform group comprises of all the aerobic, facultative and anaerobic gram-negative non-spore
forming rod shaped bacteria that ferment lactose with gas formation within 48 hours at 35C.
The standard test for this group may be carried out either by multiple tube fermentation
technique or by membrane filter technique. Escherichia coli (E.coli) is used as an indicator
organism for the purpose of sanitary examination of water. The E.coli test by multiple tube
fermentation technique consists of 3 phases presumptive, confirmed and completed. The
results are expressed in terms of MPN (Most Probable Number), which is based on certain
probability formulae. The estimate may give a value greater than the actual number of coliform
present. The accuracy of any single test depends on the number of tubes fermented. This method
helps in describing the sanitary quality of water. The safety of the water is generally judged from
the knowledge of sanitary condition and mentioned by the number of samples yielding positive
or negative results. If more than 95% should yield negative results, the safety is usually assured.
Procedure:1. Collect the sample in sterilized bottles
2. Prepare the sterilized media necessary for the bacteriological test and keep them re0y in test
tubes containing Durham tubes / fermentation tubes.
3. Inoculate the sample in an exponential order le 10, 1 and 0.1 ml in 5 tubes each of lauryl
tryptose broth under aseptic conditions.
4. Incubate all the tubes at 35C.
5. After 24 hours examine the tubes for gas formation.
6. The tubes containing the gas are marked positive and are taken out of the incubator for
further analysis. Remaining tubes are further incubated at 35C for another 24 hours. This is the
presumptive test for coliform organisms.
7. One or two loop full of the liquid from the positive lauryl tryptose tubes are transferred into
the sterilized EC medium tubes and incubated for 24 hours at 44C.
8. The gas production after 24 hours confirms the presence of E-Coli or fecal Coliforms.
Observations:-

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Computation of MPN:The number of positive finding of coliform group organisms resulting from the multiple
portion decimal dilution planting should be computed as the combination of positives and
recorded in terms of the Most Probable Number (MPN). The MPN may be estimated by
Thomas simple formula:

Result : MPN/100 ml =

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DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

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DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

RESULT: Thus we have implemented basic gate in XILINX ISE 9.1.

VIVA QUESTIONS:Q1)What is VHDL?

Q2) How many truth table entries are required for four input circuit?

Q3)Name all universal gates and basic gates?

Q4) Define Entity?

..
Q5) How many architectures are present in VHDL?

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

EXPERIMENT NO.2

Date:

Aim :- Write a VHDL program for Universal gates using all types of style modeling.
Tools:- Xilinx ISE 9.1
Theory:- In digital system the basic operations can be performed by Universal gates. The
Universal gates are simple circuit that take one or more input signals and send output signal.
Several of these gates are define below.
1. NAND gate :- The NAND gate takes two or more inputs and performs logic NAND
on them. From truth table we notice that if both inputs are 1, the output will be 0.
Any other combination of inputs will gives a 1 output. The example shows two
inputs x and y. Multiple outputs are also possible for logic gates. In case of NAND
gate, if all inputs are 1, then output is 0. If any input is 0, the output is one.

2. NOR gate :- The NOR gate takes two or more inputs and performs logic NOR on
them. From truth table we notice that if one or more inputs are 1, the output will be
0. Any other combination of inputs will gives a 1 output. The example shows two

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DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

inputs x and y. Multiple outputs are also possible for logic gates. In case of NOR gate,
if any one input is 1, then output is 0. If both inputs are 0, the output is one.

--Program for NAND gate using if ----then statement

entity nand_beh is
port(a,b:in bit;
c:out bit);
end nand_beh;
architecture beh_nand of nand_beh is
begin
process(a,b)
begin
if(a <= '0' and b <= '0')then c <= '1';
elsif(a <= '0' and b <= '1')then c <= '1';
elsif(a <= '1' and b <= '0')then c <= '1';
elsif(a <= '1' and b <= '1')then c <= '0';
end if;
end process;
end beh_nand;

--Program for NOR gate using if---then statement

entity nor2 is
port(a,b: in bit;
c: out bit);
end nor2;
architecture beh of nor2 is
begin
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process(a,b)
begin
if (a = '0' and b = '0') then c <= '1';
elsif (a = '0' and b = '1') then c <= '0';
elsif(a = '1' and b = '0') then c <= '0';
elsif (a = '1' and b = '1') then c <= '0';
end if;
end process;
end beh;

RESULT: Thus we have implemented Universal gate in Xilinx ISE 9.1.

VIVA QUESTIONS:Q1) What is the full form of ASCII and IEEE?

Q2)What is a test bench?

Q3)What is difference between combinational and sequential circuits?

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Q4) What is a net list?

..
Q5)What are the steps in synthesis?

EXPERIMENT NO.3

Date: - _____________

Aim:- Write a VHDL code for HALF-ADDER and FULL-ADDER circuit.

Tools:- Xilinx ISE 9.1
Theory:A binary half adder is a switching circuit which will add together two binary digits (called
binary bits), producing two output bits, a sum bit, S, and a carry bit, C. It has the following truth
table:
Truth Table:A

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It is immediately obvious from the truth table that the two functions Sand C can be implemented
as S=A B, and C= AB as shown in Figure shows a logic symbol for a half adder. (Logic
symbols for devices more complex than the basic logic gates are usually just boxes with
appropriately labeled inputs and outputs).
Circuit Diagram:-

:- Full Adder is a circuit which perform the addition operation of three input bits. The addition
of 3 one-bit numbers entails eight possible combinations. Two bits are needed to represent the
result of the addition (i.e. Sum and Carry).
The Sum term is XORing of Input bits whereas the Carry generated by SOP equation of
input bits. As shown in the truth table.
Circuit Diagram:A

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Sum

Carry

Truth Table:A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

Carry
0
0
0
1
0
1
1
1

Sum
0
1
1
0
1
0
0
1

Equation:Sum = A + B + C
Carry = AB+BC+AC

Program:--half adder using structure style of modeling

library ieee;
use ieee.std_logic_1164.all;
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entity hfaddstr is
port (x,y:in std_logic;
s0,c0:out std_logic);
end hfaddstr;
architecture hfadd of hfaddstr is
component xor_2
port (e,d:in std_logic;
s:out std_logic);
end component;
component and_2
port (a,b:in std_logic;
c:out std_logic);
end component;
begin
X2: xor_2 port map (x,y,s0);
A2: and_2 port map (x,y,c0);
end hfadd;

Program:- (8)--FULL ADDER using data flow

library ieee;
use ieee.std_logic_1164.all;
entity fladd is
port (a,b,c :in bit;
s,z:out bit);
end fladd;
architecture fulladd of fladd is
begin
s<= a xor b xor c;
z<= (a and b) or (a and c) or (b and c);
end fulladd;

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Result:- Hence we studied HALF-ADDER and FULL-ADDER by using structural style of

modeling.
VIVA QUESTIONS:Q1)Who is the father of VHDL?

Q2)Is it possible to construct full adder using half adder?

Q3)How many inputs and outputs are there in full adder?

Q4) What is configuration declaration?

..

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EXPERIMENT NO.4

Date: - _____________

Aim:- Write a VHDL code for HALF-SUBTRACTOR and FULL-SUBTRACTOR circuit.

Tools:- Xilinx ISE 9.1
Theory:A binary half subtractor is a switching circuit which will subtract together two binary digits
(called binary bits), producing two output bits, a difference bit, D, and a borrow bit, B. It has
the following truth table:
Truth Table:A

It is immediately obvious from the truth table that the two functions D and B can be
implemented as D=A B, and B= A.notB as shown in Figure shows a logic symbol for a half
subtractor. (Logic symbols for devices more complex than the basic logic gates are usually just
boxes with appropriately labeled inputs and outputs).
Circuit Diagram:-

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:- Full Sbtractor is a circuit which perform the subtraction operation of three input bits. The
subtraction of 3 one-bit numbers entails eight possible combinations. Two bits are needed to
represent the result of the subtraction (i.e. Difference and Borrow).
The Difference term is XORing of Input bits whereas the Borrow generated by SOP
equation of input bits. As shown in the truth table.
Circuit Diagram:-

Truth Table:A
0
0
0
0
1

B
0
0
1
1
0

C
0
1
0
1
0

difference
0
1
1
0
1

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borrow
0
1
1
1
0
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1
1
1

0
1
1

1
0
1

0
0
1

0
0
1

Equation:difference =( A + B) + C
borrow = (A.notB)+{not(A + B).C}

Program:--half subtractor using structure style of modeling

library ieee;
use ieee.std_logic_1164.all;
entity hfsubr is
port (x,y:in std_logic;
s0,c0:out std_logic);
end hfsubr;
architecture hfsub of hfsubr is
component xor_2
port (e,d:in std_logic;
s:out std_logic);
end component;
component and_2
port (a,b:in std_logic;
c:out std_logic);
end component;
begin
X2: xor_2 port map (x,y,s0);
A2: and_2 port map (x,y,c0);
end hfsub;

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Program:- (8)--FULL SUBTRACTOR using data flow

library ieee;
use ieee.std_logic_1164.all;
entity flsub is
port (a,b,c :in bit;
s,z:out bit);
end flsub;
architecture fullsub of flsub is
begin
s<= a xor b xor c;
z<= (a and notb) or {not(a and c) or (c);
end fullsub;
Result:- Hence we studied HALF- SUBTRACTOR and FULL-SUBTRACTOR by using
structural style of modeling.

VIVA QUESTIONS:Q1)What is a library?

Q2)What are the operators in concurrent code?

Q3)What is a process?

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Q4) What is a port?

..
Q5)What is a design unit?

EXPERIMENT NO.5

Date: - _____________

Aim:- Write a VHDL program for 4:1 MUX using all types of style modeling.
Tool:- Xilinx ISE 9.1.
Theory: The multiplexer is a combination circuit that is one of the most widely used standard
circuits in digital design. The multiplexer is a logic circuit that gates one of the several input to a
output. The input selected is controlled by asset of select inputs. The block dig. of a multiplexer
with n input lines and one output line. For selected one out of n input for connection to the
output, a set of m select inputs is required where 2m = n

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Depending upon the digital code applied at the select inputs one out of n data source is
selected and transmitted to a single output channel.

Program:
library ieee;
use ieee.std_logic_1164.all;
entity mux4_1 is
port(a: in std_logic_vector ( 3 downto 0);
b: out std_logic);
end mux4_1;
architecture select1 of mux4_1 is

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signal s: std_logic_vector ( 1 downto 0);

begin
with s select
b <= a('0') when "00",
a('1') when "01",
a('2') when "10",
a('3') when "11",
"-" when others;
end select1;
--program with data flow
architecture behv1 of Mux4 is
begin
y<= (not (s(0)) and not(s(1)) and I(0)) or(s(0) and not(s(1)) and I(1)) or (not(s(0)) and
s(1) and I(2))or (s(0) and s(1) and I(3));
end behv1;
--architecture with 'when ....else'statement
architecture behv2 of Mux4 is
begin
y <=
I(0) when S="00" else
I(1) when S="01" else
I(2) when S="10" else
I(3) when S="11" else
'Z' ;
end behv2;
RESULT: Thus we have implemented Multiplexer in XILINX ISE 9.1.

VIVA QUESTIONS:Q1)What is the function of select line in Mux?

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Q2) Is dataflow is sequential or concurrent ?

Q3) Is behavioral is sequential or concurrent ?

Q4) Name different data types ?

..
Q5)What is difference between with/select and case select ?

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EXPERIMENT NO.6

Date: - _____________

Aim :- Write a VHDL code for 3:8 Decoder using all style of modeling.
Tool :- Xilinx ISE 9.1
Theory:- Decoder is a circuit which performs the reverse operation of encoder. In which the
number of output lines is n whereas the number of output lines m. i.e. n = 2m.

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Program:
--program with when ....else statement
library ieee;
use ieee.std_logic_1164.all;
entity encoder8 is port(A: in std_logic_vector(7 downto 0);
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y:out std_logic_vector(2 downto 0));

end encoder8;
--architecture for conditional signal
architecture select1 of encoder8 is
begin
with A select
y <= a(0) when s = "000" else
a(1) when s = "001" else
a(2) when s = "010" else
a(3) when s = "011" else
a(4) when s = "100" else
a(5) when s = "101" else
a(6) when s = "110" else
a(7) when s = "111" else
'Z' ;
end select1;
--3:8 decoder using behavioural statements
library ieee;
use ieee.std_logic_1164.all;
entity decoder2 is
port(A:in std_logic_vector(2 downto 0);
Q:out std_logic_vector(7 downto 0));
end decoder2;
--architecture
architecture beh of decoder3 is
begin
process(A)
begin
if A="000" then Q <="00000001";
elsif A="001" then Q <="00000010";
elsif A="010"then Q <="00000100";
elsif A="011" then Q <="00001000";
elsif A="100"then Q <="00010000";
elsif A="101" then Q <="00100000";
elsif A="110" then Q <="01000000";
elsif A="111" then Q <= "10000000";
end if;
end process;
end beh;
--3:8 decoder using select statements
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architecture beh of decoder1 is

begin
with A select
Q <="00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"--------" when others;
end beh;

--3:8 decoder using conditional statements

architecture beh of decoder2 is
begin
Q <="00000001" when (A="000") else
"00000010" when (A="001") else
"00000100" when (A="010") else
"00001000" when (A="011") else
"00010000" when (A="100") else
"00100000" when (A="101") else
"01000000" when (A="110") else
"10000000" when (A="111");
end beh;

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Waveform:-

RESULT: Thus we have implemented Encoder in XILINX ISE 9.1.

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VIVA QUESTIONS:Q1) Give examples of combinational logic circuit?

Q2) How many encoder are there in digital electronics?

Q3) What are applications of encoder and decoder?

Q4) How many select lines are present in 2:4 encoder?

..

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EXPERIMENT NO.7

Date: - _____________

Aim :- Write a VHDL program for 8:3 encoder using all types of style modeling.
Tool :- Xilinx ISE 9.1
Theory:- Encoder:- The digital circuits work in a binary manner, therefore the numerals,
alphabets and other special character are to be converted into binary format. There are various
possible ways of doing this and this process is known as Encoding.
Commonly used binary codes are:a) Binary Code
b) BCD Codes
c) Excess-3 Codes
d) Gray Codes
e) Hexadecimal Codes
f) Octal Codes

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Program:
--program with when ....else statement

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library ieee;
use ieee.std_logic_1164.all;
entity encoder8 is port(A: in std_logic_vector(7 downto 0);
y: out std_logic_vector (2 downto 0));
end encoder8;
--architecture for conditional signal
architecture select1 of encoder8 is
begin
with A select
y <= a(0) when s = "000" else
a(1) when s = "001" else
a(2) when s = "010" else
a(3) when s = "011" else
a(4) when s = "100" else
a(5) when s = "101" else
a(6) when s = "110" else
a(7) when s = "111" else
'Z' ;
end select1;

--program with select line style

architecture beh of encoder1 is
begin
with i select
q <= "000" when "00000001",
"001" when "00000010",
"010" when "00000100",
"011" when "00001000",
"100" when "00010000",
"101" when "00100000",
"110" when "01000000",
"111" when "10000000",
"---" when others;
end beh;

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WAVEFORM:-

RESULT: Thus we have implemented Encoder in XILINX ISE 9.1.

VIVA QUESTIONS:Q1) Which device converts BCD to seven segment?

Q2) What is a test bench in VHDL?

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Q3)How many inputs are there in 4:2 encoder?

EXPERIMENT NO.8

Date: - _____________

Aim :- Write a VHDL code for D FLIP-FLOP, S-R FLIP-FLOP, J-K FLIP-FLOP using style of
modeling.

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Tool :- Xilinx ISE 9.1

Theory:- The circuit for a gated D latch. It is based on the gated SR latch, but instead of using
the S and R inputs separately, it has just one data input, D. for convenience we have labeled the
points in the circuit that are equivalent to the S and R inputs. If D = 1, then S = 1 and R = 1,
which forced the latch into the state Q =1. If D = 0, then S = 0
And R = 1,which causes Q = 0. Of course, the change in state occurs only when CLK = 1
The transfer of data from input to output is delayed and hence the name delay(D). the D-type
FLIP-FLOP is either used as a delay device or as a latch to store 1-bit of binary information.
The S-R flip flop is set or reset the memory cell in synchronism with a train
pluses known as Clock.
In this circuit, if a clock pulse is present (Clk = 1), its operation is exactly the same as
that of fig. on other hand, when clock pulse is absent (Clk = 0), the gate are inhibited i.e. their
output are 1 irrespective of the values of S and R only when the clock is present.
Assuming that inputs do not change during the presence of the clock pulse, we can
express the operation of a Flip-Flop in the form of the truth table.
(1).
If S = R = 0, and clock pulse is applied, the output at the end of the clock pulse is same
as the output before the clock pulse Qn+1 = Qn.
(2).
If S = 1 and R = 0, the output at the end of clock pulse will be Qn+1 = 1.
(3).
If S = 0 and R = 1, the output at the end of clock pulse will be Qn+1 = 0.
(4)
If S = R = 1, is not allowed.

The J-K flip flop is a cascade of two S-R Flip-Flops with feedback from the output of the second
to the inputs of the first as shown in circuit dig.
Positive clock pulse are applied to the first Flip-Flop and the clock pulse are inverted before
these are applied to second Flip-Flop.
When Clk = 1, the first Flip-Flop is enabled and the output Q and Q respond to the
inputs J and K
(1). If J = K = 0, the output at the end of clock pulse will be Qn+1 = Qn.
(2). If J = 1 and K = 0, the output at the end of clock pulse will be Qn+1 = 1.
(3).
If J = 0 and K = 1, the output at the end of clock pulse will be Qn+1 = 0.
(4)
If J = K = 1, the output at the end of clock pulse will be Qn+1 = Qn.

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Circuit Diagram:S

Q
Clk
Q
R

Truth table:Clk
0
1
1

D
X
0
1

Q(t+1)
Q(t)
0
1

Timing Diagram:t1

t2

t3

t4

Clk
D
Q

Symbol:-

S
Clk
R

S-R
FLIP
FLOP

Q
Q

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Truth table:S
0
1
0
1

R
0
0
1
1

Qn+1
Qn
1
0
?

Circuit Diagram:S

Clk
Q

Symbol:J
Q

J-K
FLIP
FLOP

Clk

K
Truth table:J
0
1
0
1

K
0
0
1
1

Qn+1
Qn
1
0
Qn

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Circuit Diagram:Q

J
Clk
K

S-R
FLIP
FLOP
Q

Program:(5)--D Flipflop
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(d,clk: in std_logic;
q : out std_logic);
end dff;
architecture d_ff of dff is
begin
with clk select
q<=d when '1',
'Z'when others;
end d_ff;

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Program:-

(7)--SR flip flop using if then else

library ieee;
use ieee.std_logic_1164.all;
entity sr is
port(s,r,clk: in std_logic;
q,q1 : out std_logic);
end sr;
architecture sr_ff of sr is
begin
process (clk,s,r)
begin
if (clk='1')then
if (s='0' and r='0') then
q <='1';
q1<='0';
elsif (s='1' and r='0') then
q <='1';
q1<='0';
elsif (s='0' and r='1') then
q <='0';
q1<='1';
elsif (s='1' and r='1') then
q <='X';
q1<='X';
end if;
end if;
end process;
end sr_ff;
Program:- (6)--JK flip flop using if then else
library ieee;
use ieee.std_logic_1164.all;
entity jk is
port(j,k,clk: in std_logic;
q,q1 : out std_logic);
end jk;
architecture jk_ff of jk is
begin
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process (clk,j,k)
begin
if (clk='1')then
if (j='0' and k='0') then
q <='1';
q1<='0';
elsif (j='1' and k='0') then
q <='1';
q1<='0';
elsif (j='0' and k='1') then
q <='0';
q1<='1';
elsif (j='1' and k='1') then
q <='0';
q1<='1';
end if;
end if;
end process;
end jk_ff;

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Result:- Hence we studied the D Flip Flop, J-K FLIP-FLOP, S-R FLIP-FLOP circuit

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

VIVA QUESTIONS:Q1) What is a flip/flop?

Q2)What is the use of clock?

Q3) Name various flip flops?

Q4) What is a counter ?

..
Q5)What is advantage of JK f/f over RS f/f ?

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

EXPERIMENT NO.9

Date: - _____________

Aim :- Write a VHDL code for BCD to 7 Segment Decoder using all style of modeling.
Tool :- Xilinx ISE 9.1
Theory:- In a 3-to-8 binary decoder converts from binary number on the input to a one-hot
encoding at the output.
In the BCD to 7 segment decoder, which convert s one binary coded decimal (BCD)
digit into information suitable for driving a digital oriented display. In the seven segment display
each segment is a small light emitting diode(LED), which glows when driven by an electrical
signal. The segment label from a to g . the truth table for BCD to 7 segment decoder given in the
fig. each valuation of the inputs w3w0, the seven output are set to display the appropriate
BCD digit a circuit that implements s the truth table can be derived using the synthesis
techniques. This circuit that produce one hot encoded output.
A
BCD-7

CODE
CONVERTER

D
fig (b) 7 SEGMENT DISPLAY

fig (a) CODE CONVERTER

Truth Table:w3

w2

w1

w0

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G
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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

1
0
1
1
0
1
1
1
1
1

1
1
1
1
1
0
0
1
1
1

1
1
0
1
1
1
1
1
1
1

1
0
1
1
0
1
1
0
1
1

1
0
1
0
0
0
1
0
1
0

1
0
0
0
1
1
1
0
1
1

0
0
1
1
1
1
1
0
1
1

Program :(1) -- program for 7 seg. to bcd using case statement

library ieee;
use ieee.std_logic_1164.all;
entity bcd_case is
port (a: in std_logic_vector(3 downto 0);
y: out std_logic_vector(6 downto 0));
end bcd_case;
architecture bcd of bcd_case is
begin
process (a)
begin
case a is
when "0000" => y<="0000001" ;
when "0001" => y<="1001111" ;
when "0010" => y<="0010010" ;
when "0011" => y<="0000110" ;
when "0100" => y<="1001100" ;
when "0101" => y<="0100100" ;
when "0110" => y<="0100000" ;
when "0111" => y<="0001111" ;
when "1000" => y<="0000000" ;
when "1001" => y<="0000100" ;
when others => y<="-------" ;
end case;
end process;
end bcd;

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

(2)-- bcd to 7 segment using select signals

library ieee;
use ieee.std_logic_1164.all;
entity bcd1 is
port (a : in std_logic_vector(3 downto 0);
y: out std_logic_vector(6 downto 0));
end bcd1;
architecture bcd of bcd1 is
begin
with a select
y<= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

"XXXXXXX" when others;

end bcd;

(3)-- bcd to 7 segment using when else signals

library ieee;
use ieee.std_logic_1164.all;
entity bcd2 is
port (a: in std_logic_vector(3 downto 0);
y: out std_logic_vector(6 downto 0));
end bcd2;
architecture bcd of bcd2 is
begin
y<= "0000001" when (a="0000") else
"1001111" when (a="0001") else
"0010010" when (a="0010") else
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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

"0000110" when (a="0011") else

"1001100" when (a="0100") else
"0100100" when (a="0101") else
"0100000" when (a="0110") else
"0001111" when (a="0111") else
"0000000" when (a="1000") else
"0000100" when (a="1001");
end bcd;

(4)-- bcd to 7 segment using if then else signals

library ieee;
use ieee.std_logic_1164.all;
entity bcd3 is
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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

port (a: in std_logic_vector(3 downto 0);

y: out std_logic_vector(6 downto 0));
end bcd3;
architecture bcd of bcd3 is
begin
process (a)
begin
if (a="0000") then y<="0000001" ;
elsif (a="0001") then y<="1001111" ;
elsif (a="0010") then y<="0010010" ;
elsif (a="0011") then y<="0000110" ;
elsif (a="0100") then y<="1001100" ;
elsif (a="0101") then y<="0100100" ;
elsif (a="0110") then y<="0100000" ;
elsif (a="0111") then y<="0001111" ;
elsif (a="1000") then y<="0000000" ;
elsif (a="1001") then y<="0000100" ;
end if;
end process;
end bcd;

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Result:- Hence we study the BCD-to-7-Segment Display Decoder.

VIVA QUESTIONS:Q1) What is a register?

Q2)What is a sequential circuit?

Q3) Which device converts BCD to seven segment??

Q4) Who is father of VHDL?

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

..

EXPERIMENT NO.10

Date: - _____________

Aim:- Write the VHDL code for Two Bit Multiplier

Tools:- Xilinx ISE 9.1
Theory:This is a more complicated problem in which we compared again our solution with the
circuit generated by a human designer (see Figure 5). Once more, the solution generated by the
GA using binary representation was somewhat disappointing, because it uses one more gate than
the solution generated by a human (see Figure 6). Then, we decided to try a GA with an alphabet
of cardinality 8 (using the integers from 0 to 7). With only 7 gates, we generated a circuit
equivalent to the one produced by a human designer using 16 gates.
In this context, a fitness of 64 represents a functional circuit, and any increment above
that indicates the number of WIREs used. For the GA with binary representation, the maximum
fitness achieved was only 79, whereas for the GA with our alternative
representation, we could find a design with a fitness of 89, as can be seen in our results.
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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

Circuit Diagram:-

Program :--program for 2bit multiplier

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mulbit is
Port ( A,B : in std_logic_vector(1 downto 0);
C : OUT std_logic_vector(3 downto 0));
end mulbit;
architecture mul of mulbit is
begin
C <= A*B;
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DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

end mul;
Output:-

Result:- Hence we studied the VHDL code for Two Bit Multiplier

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NUVA COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF M.TECH ENVIRONMENTAL ENGINEERING (CIVIL)

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