ElectricalSystemsDesign(ELX304)

Part5VLSIimplementationplatforms

PART5

VLSIIMPLEMENTATION
PLATFORMS

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LESSON1

REGULARARRAYSTRUCTURES
INTRODUCTION
Thismoduleintroducestheconceptofregulararraystructuresthat
providethebasicmethodologyforoptimumuseofVLSIdesign.
Itproceedstolookatthemostcommonapplications,namely
memorydevices,andintroducesprogrammabledevicesfor
efficientlogicimplementation.

YOURAIMS
Attheendofthislesson,youshouldbeableto
understandthereasonsbehindtheuseofregulararray
structures
investigatebasicstructuresthatareimplementedinVLSI
technology.

STUDYADVICE
[Link],
thefollowingreferenceswillprovideadditionalsupportmaterial.

SUPPORTMATERIAL
Uyemura,J.P. (2001) IntroductiontoVLSICircuits&SystemsJ.
Wiley&Sons.(Chapters13)
Geiger,R.L.,Allen,P.E.&Strader,N.R. (1990) VLSI,Design
[Link].(Chapter
9)
Martin,K.(1999)[Link]
UniversityPress.(Chapter10)
Fabricus,E.D.(1990) [Link]
Hill.(Chapters9&10)

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1.1 REGULARARRAYSTRUCTURES
InVLSIdesignthecontinuousdrivetowardssmallertechnologies
isnotonlycompoundedbythemanufacturingcapabilitiesbutalso
thetechniquesutilisedtooptimiseanydesignslayoutfor
[Link]
oftheinterconnectionsbetweengatesandconsequentlytheuseof
structuredarchitecturesbecomesincreasinglymoreimportant.
Therepetitivestructuresthatresultallowthedesignertospend
considerablymoreeffort,thanwouldnormallybethecase,onthe
optimisationofthesmallersubcircuitsthattheoveralldesign
breaksdownto.
Aswewillinvestigatelater,andhasbeenpreviouslyidentified
underintegrationlevels(seetopic4lesson1),typicalexamples
thatfitwithinthisphilosophyarememorydevicesandgatearrays
butletusfirstofallinvestigatethesimplecaseofdatatransfer
[Link]
twobasicbuildingblocks:
i)
ii)

ShiftRegister(S/R)storageelements,and
CombinationalLogic(C/L)controlelements.

1.1.1

DATATRANSMISSION

Adatatransmissionpathcanbeconstructedusingthefollowing
cascadearrangement:

S/R

C/L

S/R

C/L

Inordertocontrolsuchdevicesandpreventdatasimplycascading
[Link]
operationwhichisrelativelysimplewithedgetriggeredbipolar
devicesasthefinitedurationoftheclocksedgeensuresthat
insufficienttimeexistsforthecombinationallogicblocksto
propagatethedatafromthepreviousregisterstageonthroughthe
[Link].
However,thisisnotthecasewithleveltriggeredCMOSdevices
asthelengthoftimethattheclockisheldattheappropriatelevel
canbegreaterthanthepropagationdelaythroughthelogicblocks
allowingdatatofreerundownthestructureuntiltheclock
[Link]
clockoperationwhichisdesignedtoensureonlyoneclocklevel
existsatanysinglepointintime,therefore:

f1 f 2 L f n = 0

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andthereforethedatapathbecomes
f1

f2

S/R

C/L

f1

S/R

C/L

S/R

AsolutionofthetypefirstencounteredwithmasterslaveJKflip
flopsinordertopreventcontinuousfeedbackaffectingoperation.

1.1.2

LOGICIMPLEMENTATION

Similarly,themultiphaseclockisrequiredfortheconstructionof
synchronousmachines(seepart1lesson1)forthesamereason:
f1

f2

S/R

C/L

S/R

Inordertokeepthestructuresregularthenthecombinational
logicblocksarethemselvesoftenrealisedinPLAorROM
structures.
WORKEDEXAMPLE1
Thefollowingsimplecircuitillustratesastructurewhichis
capableofperformingdatatransmissioninbothshiftrightand
shiftleftmodes:
SHL

DATA

SHR

TRR

TRL

SHL

DATA

Derivethenecessarycontrollogictoallow,inconjunctionwitha
twophaseclock,shiftrightoperationwhenasinglecontrolsignal
(CTRL)ishighandshiftleftoperation whenitislow.

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SOLUTION
ConsiderdatamovingbetweenAandBthenthefollowing
transistorsrequireswitching:
ShiftRight: SHR,TRR,SHR,TRR,etc..
ShiftLeft:
TRL,SHL,TRL,SHL,etc..
Thereforethefollowingtableillustratesonesolutiontothe
problemwhichusestheabovesequencesforsequential
applicationsofthetwophasedclock(i.e. f1, f2, f1, f2,etc..):

ShiftRight
ShiftLeft

Thus

CTRL
CTRL

f1

f2

SHR
TRL

TRR
SHL

SHR= f1 .CTRL
TRR= f2 .CTRL
TRL= f1 .CTRL
SHL= f2 .CTRL

f1
f2
CTRL

SHL

DATA

SHR

TRR

TRL

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1.2 MEMORYSTRUCTURES
Therepetitivearraystructureofmemorydevicesmakethemideal
[Link]
(RandomAccessMemory)andROM (ReadOnlyMemory)both
ofwhichwillbebrieflydiscussedbelow:

1.2.1

RANDOMACCESSMEMORY

Asthenamesuggeststhistypeofmemorycanbereadorwrite
accessedatanytimeandcomesinbothstaticanddynamicforms:
[Link]
STATICRAM(SRAM)
SRAMsarebaseduponflipflopswherethememorycontents
willremainoncesetuntileitherthememoryisdeliberatelyover
[Link]
[Link]
followingdiagramillustratingaCMOScell:

Vdd
Q3
BIT

Q4

Q5

Q6
Q1

WORD

BIT

Q2
WORD
Gnd

TowritetothememorycelltheBITandBIT lineshavetobeset
[Link]
deviceswilllatchthecellandtheWORDlinecannowbede
[Link]
latchiscompletedandalsocounteracttheaffectsofcharge
leakageviathepasstransistors.
ReadingisperformedbyprechargingtheBIT andBIT linesand
[Link]
viathecurrentlyactiveNMOSpulldowntransistortoleavethe
memorycontentsontheBITlines.
[Link]
useofatwometalprocessinordertoachieveaccesstothebit
[Link].

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VDD

GND

Bit

Word

Word

Metal

Poly

PMoat

NMoat

Bit

NWell

ACMOSSRAMCell

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[Link]
DYNAMICRAM(DRAM)
AsinSRAMacrosscoupledinverterstructureisusedbutthe
storageisperformedintheparasiticgate/sourcecapacitanceofthe
[Link]
controllingdevicesworkonanentirecolumnandhencethe
overalltransistorcountisreducedandlargermemoriescanbe
[Link]:
BIT

BIT

Sharedbyentirecolumn
Vdd
Q

v
x

Row
Line
Q3

Q4

Q1

Q2

Gnd

ToR/W
Amplifiers

ToR/W
Amplifiers

However,leakagecurrentscausethestoredvoltagetodecay
towardsgroundlevelsandDRAMsmustbecontinuously
refreshedtooperate [Link]
fashionbyselectingtheappropriaterowline(x)andpulsingthe
columnrefreshsignal(v)forapproximately1mSwhichconnects
thestoragedevicestoVddforrefreshasQ/Q1andQ/Q2actas
[Link]
repeatedevery2mStosecurestoragelevels.
FromtheDRAMstructureabove,thegate/sourcecapacitorwill
discharge,fromVdd,ataratedependinguponthesizeofthe
capacitanceandtheeffectiveleakageresistanceofthepulldown
[Link],thelogiclevelswillberesettosupplyrail
[Link],duringa
typicalrefreshcycle,thefollowingvoltagecharacteristicswillbe
seen:

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VS
Vdd
Vmin

time
0

tp tr

tp

Refresh

Hold

Therefore,duringtheholdtime,(0t tp - tr ):
-

VS =Vdde

t
CGSReff

and,refresh(t p -tr t tp ):
-

VS =Vdd - (Vdd - Vmin)e

t
CGSRon

Ideally,inpracticethetimeconstantsaresuchthat(notingthat
CGSistypicallyaround50fF):
11
th = CGSReff >> (tp - tr ) asReff isintheregionof10 W,and

tr = CGSRon << tr

asRon isintheregionof104W
(seePart4lesson6).

Ensuringthatthedecayisalmostlinearandtherefreshisalmost
instantaneousincomparison,guaranteeingreestablishmentof
Vdd.

INTEXTQUESTION
[Link]
thewideningofthepolysiliconlineimprovethings?

ANSWER
WideningthelinewillreducetheresistanceasRpoly =(L/W)[Link],thiswillalso
increasethecapacitanceassociatedwiththelineby Cpoly =(L*W)Cs andthereforetheoverall
propagationdelay, tpoly=CpolyRpoly willremainthesameatL2CsRs.

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WORKEDEXAMPLE2
ADRAMcellisconstructedusingapulldownFETof
gate/sourcecapacitance50fF.Ifavoltageof3.8Vistheminimum
thatcanberecognizedandaperiodof2mSandrefreshtimeof
1mSistobeused,whatwouldbetheminimumpermissible
leakageresistanceoftheFET?
SOLUTION
Actual:
Basedupontheaboverelationshipforthedecayof
thegate/sourcecapacitorthenrearrangingprovides:
Reff =

Linear:

(t - t )
p

V
- CGS loge min
Vdd

(2 10

- 1 10- 6)
= 1.46 1011W
-15
- 50 10 loge(3.8/5)
-3

Assumingthatalineardecayrateexiststhenthe
changeinchargeexperiencedbythecapacitoris

DQ = CGSDVS = 50 10-15(5- 3.8)= 60 10-15C

Hencetheeffectiveresistanceitexperiences,linearlyfromVdd is:
Reff =

V VDt 5(2 10-3 - 1 10-6)

Note:
Evaluatingtherelationshipsforthelinearapproachprovides
Reff =

Vdd(tp - tr)
CGS(Vdd - Vmin)

(t - t )
p

V - V
CGS dd min
Vdd

(t - t )
p

V
CGS1- min
Vdd

However,since loge (1+x) x as x0 thentheabove

Hencethetworelationshipsbecomeequivalentas Vmin Vdd .

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ForhighcapacityDRAMdevicesthenasingleNMOSdeviceis
[Link]
requiredasleakageproblemsstillexist:
BIT

Row
Line

CC

VC
CR

VR

y
ToR/W
Amplifiers

Themajorproblemwiththisstructureisthatthereadingoperation
destroysthecellsmemorycontentsasthechargeeachcell
containsdissipatesintotheread/writedatalinescapacitance,CR.
Aproblemthatisfurthercompoundedbythefactthatthereare
manycellsconnectedtotheBIT datalineandhenceCR >>CC ,
thusVR<<VC.
WORKEDEXAMPLE3
ForasingleMOSDRAMcellwhichstoresachargethatproduces
VC [Link]
amplifiersifthebitlinecapacitanceisCR? Assumingthattheread
lineisinitiallyuncharged.
SOLUTION
Priortoactivatingtherowlinesignal,X,andreadsignal,Y,all
thechargeisstoredinthecellitself (VR* =0),thus
QT =CCVC
However,afterthesignalshavebeenactivatedthischargeis
[Link]
arenowinparallelthechargeisredistributedsothatthefinal
voltageVR is:
QT =CCVR+CRVR =(CC+CR)VR
Thus,assumingnochargeislost,then

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CC
VC
V R =
CC + CR

[Link]
PHOTOSENSITIVERAM
CMOSCamerasareconstructedusingsingleMOSRAM
structuresbutwithareversebiasedphotodiode,formedby
extendingandexposingthesourceregionofastandardMOS,
whichisconnectedtothecellcontrollingMOSdevicestransistors
[Link]
proportionaltotheincidentlightandhencetheresultingstored
potentialformsagreyscaleimageoftheincidentlightatthat
[Link]
pixeloftheoverallimageandtheentirearraysurfacetheimage
[Link]
ownchargesenseamplifier.
Column
Line

Row
Line

ToR/W
Amplifiers

INTEXTQUESTION
Howcouldtheabovetechnologybeconvertedtoprovidecolourimages?

ANSWER
Acolourimageismadepossibleusingsuitablefilterstoisolatered,greenandbluelight
[Link]
everypixelintheimage.

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1.2.2

READONLYMEMORY

Asthenamesuggeststhistypeofmemorycanonlybereadandis
normallyusedincomputerstostoretheoperatingsystemsdueto
itslongtermstability (barringcircuitfailure).ROMdevicesare
programmedatmanufacturebythecreation/noncreationofMOS
devicesintheappropriatecelllocationsmakingtheminflexible
[Link]
programmabledevicesarealsoavailable(PROMs)andcomein
variousstructures,someofthemostcommonbeing:

[Link]
ERASABLEPROM(EPROM)
ThistechnologyusesadoublegateNMOStransistorstructure
oftencalledafloatinggateavalancheinjectionMOS(FAMOS)
gate:
Vdd

ToR/W
Amplifiers

Gate2

Drain

Word
Line

x
Source

Gate1
n+

n+
psubs
psub
BIT

Gate1isleftfloating(electricallyisolated)andisusedtocontrol
[Link]
largepositivevoltage,typically25V,isappliedbetweenGate2
andthedrainoftheFAMOSdeviceandtheresultinghigh
electricalfieldinthedepletionregionaboutthedraincauses
[Link],
whichareacceleratedbythelargeelectricalfield,topenetratethe
[Link]
chargedgatewillpreventformulationofachannelinthe
depletionregion andthecellsFAMOSdeviceisnowincapableof
[Link]
programmingonthecell.
Becauseoftheinsulatingpropertiesofthesilicondioxidethis
[Link],assilicondioxide
becomesmoreconductivewhenexposedtoUVlightthenthis
canbeusedtoresetthedevice,byallowingthestoredelectronsto
migratefromtheisolatedgate.

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[Link]

ELECTRICALLYERASABLEPROMS
(EEPROMS)
ThemajorproblemwithEPROMisthewindowcreatedinthe
package,thefactthatplasticpackagingisnegatedbytheneedto
exposeittoUVlightandthesubsequentexposuretimetakento
[Link]
EPROMexceptthattheGate1insulatinglayersareconsiderably
thinner,[Link]
electronstotheisolatedgateviaquantummechanicaltunneling
[Link]
voltagelevelsthenthememorycellscanbeerasedbyapplying
theprogrammingvoltageinreversewithoutdamagingthe
structure,amuchmoreefficientprocedurethanforEPROM.

1.2.3

CHARGECOUPLEDDEVICES
(CCDS)

BasicallyMOStransistorsdesignedwithalongchannelwith
thousandsoftinycloselyspacedgatesbetweenthesourceandthe
[Link]
thesubstratewhosechargecanbetransferredalongthestructure.
Thisisachievedbyapplyingapositivevoltage(withrespectto
thegroundedsubstrate)profiletoeachgateinturn,seebelow:
Therebycreatingdepletionregionsinthechannel,andunderthe
gateconcerned,andformingpotentialenergywellswithinwhich
mobileminoritycarriersfromthesubstratecanbeattracted.

f1
f2
f3
123456n

psubs

T1Period

T2Period

T3Period

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Inordertocontrolthepassageofthechargepacketsalongthe
structure,startingwithachargepacketinlocation1,thenthe
aboveillustratesthelocationsoftheelectronholdingenergywells
toallowthedataheldinposition 1tobepassedontolocation2.
Thereforethreephasesarerequiredtoallowforthenecessary
phaseoverlap,whilstavoidingfreerundownthestructure,
althoughitispossibletoconstructtwophasedevicesusing
[Link] thenthesedevicesmustbe
operatedathighfrequencies,upto30MHz,andtheirminimum
operatingfrequency,typically10kHz,isrestrictedbecause
thermallygeneratedcarriersbecometrappedinemptywellsandin
timecanleadtoachangeinlogicstatefromlowtohigh.
Theserialnatureofthesedevicesgenerallymakethemunsuitable
formemorystoragedevicesbuttheyarecommonlyusedfor
imageanddigitalsignalprocessingduetotheirveryhighdensity.

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SUMMARY
Theimportanceofregulararray structurestoachievetheVLSI
[Link]
mostefficientprocessesforthisarememorydevicesthenthis
lessonhasconcentrateduponthem.
Followingonwiththeregulararraystructurephilosophythengate
arraysprovidestructuresforprogrammablelogicarchitecture.
Eachofthearchitecturesoffervariouslevelsofimplementation
[Link]
categoriesinclude:
SimpleProgrammableLogicDevices(SPLDs),
ComplexProgrammableLogicDevices(CPLDs),and

FieldProgrammableGateArrays(FPGAs)

FieldProgrammableInterConnect(FPICs)

Thefollowinglessonwilllookattheselogicimplementation
structures.

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SELFASSESSMENTQUESTIONS
QUESTION1
Usingthesolutiontoworkedexample1,whatlogiccontrolisrequiredtoholdthedatainits
currentlocation?
QUESTION2
If theSRAMcellofsection 1.2.1.1hadbothBITlinesgroundedandtheWORDlinesseparated
forcontrolpurposeswhatlogicfunctionwouldresultattheinverteroutputs?
QUESTION3
A256kSRAMdevice,offeaturesize2mm,isconstructedusingminimumwidthdesignforthe
polysiliconwordselectlinesandassociatedtransistorchannels.Iftheselectlinesare4mmlong
onthechipsurfacethen,assumingasquarearchitecture,estimatetheirpropagationdelay(seethe
MOSISvaluesinPart4Lesson5).
QUESTION4
ADRAMcellisconstructedusingapulldownFETofgate/sourcecapacitance40fFandleakage
[Link]
canbereadis3.8Vfromasupplyof5V.
QUESTION5
ForthesingletransistorDRAMdeviceshowninsection [Link]:
(a) DevelopanalternativeexpressionfortheBITreadvoltageiftheBITlinehastheinitial
voltage,VR*,andnotzeroasassumedinworkedexample3.
(b)Rearrangetheaboveequationintermsofthechangeinreadvoltage.
(c) WhatwouldbethemaximumallowablecapacitanceoftheBITlineifthecellscapacitance
[Link]
assumethatthesmallestchangeincellvoltagethatwillallowasuccessfulreadisVdd/2
(whereVdd =5V).

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ANSWERSTOSELFASSESSMENTQUESTIONS
ANSWER1
[Link]
achievedintwoways:
CircleCW: SHR,SHL,SHR,SHL,etc.
CircleACW: TRL,TRR,TRL,TRR,etc.
Withthepreviouscontrolsignalsfortheaboveoperations,i.e.

ShiftRight
ShiftLeft

CTRL
CTRL

f1
SHR
TRL

f2
TRR
SHL

Thenthesolutionistotogglethestatusofthecontrolsignal,CTRL,witheachclockphase.

ANSWER2
Hence,thecircuitbecomes
Vdd

f2

f1

Gnd

Thus
A
0
0
1
1

B
0
1
0
1

f1
f2
NoChange
1
0
0
1
Race

AnRSFlipFlop(f1 =Q,f2 =Q,withA=Reset,B=Set).

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ANSWER3
Forasquare256kmemory (218 gates) thenitwillhave512*[Link]
drive512devicesandasminimumMOSISdimensionsare2lwideforthepolysiliconand2l*2l
areaforthegatesthen:
Totalselectlinearea=4mm*2l = 4mm*2(2mm) = 16000mm2
GateArea=512*(2l*2l)=512*2(2mm)*2(2mm)=8192mm2
Henceeffectivepolysiliconarea(nongate)is160008192=7808mm2
Nowfrom Table2inPart4Lesson5,thentheinputcapacitanceassociatedwiththeselectline
(l=2mm) is:
Cin =Cg +Cpoly =8192(0.8)+7808(0.06)=6553.6fF+468.48fF=7.022pF
FromTable1inPart4Lesson5,thentheresistanceofthepolysilicon(assuminganaverage
value)is22.5W/o,asthepolysiliconis4mmlongand(2(2mm))widethen
Rpoly =(4mm/(2(2mm))*22.5=1000*22.5=22.5kW
Thusthepropagationdelaytimeconstantis:
tselect =Rpoly*Cin =22.5e+3*7.022e12=158ns=0.158ms

ANSWER4
Assumingconstantleakagecurrentthen
IL =-

dQ d(CGSVS )
d(VS )
=
= -CGS
dt
dt
dt

Therefore,asallchangesareassumedlinear,then
IL =-

DQ
D (VS )
= -CGS
Dt
Dt

andtherefore
Dt = -CGS

Page24

D(VS )
(3.8- 5)
= -40 10-15
= 48ms
- 9
IL
1 10

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ANSWER5
(a) Thetotalchargeinthesystemmustbethesamebeforeandaftertheread,
hence
QT =CCVC+CRVR* =CCVR+CRVR
*

C V + CRVR
VR = C C
CC + CR

Therefore

(b)SubtractingVR* frombothsidesthen
*
C V + CRVR
CC
*
*
*

VR -VR = C C
- VR = VC - VR
CC + CR
CC + CR

(c) From (b)above,rearranging(intermsofCR)

2.5
CR = C R* - 1CC =
- 140fF = 1210fF
0
.
08
V
V

R R

(
(

)
)

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