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SDF to Verilog Mapping Guide

The annotator matches timing constructs in SDF files to corresponding constructs in Verilog specify blocks. IOPATH matches path delays or primitives, INTERCONNECT and PORT match input ports and create delayed versions, PATHPULSE and GLOBALPATHPULSE match path delays, and DEVICE matches primitives or path delays. SETUP, HOLD, SETUPHOLD match timing checks like $setup and $setuphold. RECOVERY, REMOVAL, RECREM match checks like $recovery and $removal. SKEW matches $skew, WIDTH matches $width, PERIOD matches $period, and NOCHANGE matches $nochange.

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Veeranjaneyulu Dhikonda
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204 views3 pages

SDF to Verilog Mapping Guide

The annotator matches timing constructs in SDF files to corresponding constructs in Verilog specify blocks. IOPATH matches path delays or primitives, INTERCONNECT and PORT match input ports and create delayed versions, PATHPULSE and GLOBALPATHPULSE match path delays, and DEVICE matches primitives or path delays. SETUP, HOLD, SETUPHOLD match timing checks like $setup and $setuphold. RECOVERY, REMOVAL, RECREM match checks like $recovery and $removal. SKEW matches $skew, WIDTH matches $width, PERIOD matches $period, and NOCHANGE matches $nochange.

Uploaded by

Veeranjaneyulu Dhikonda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

7/21/2016

SDFtoVerilogconstructmatching

SDFtoVerilogconstructmatching
[Link],the
[Link],the
annotatorlocatesthecellinstanceandupdateseachspecifypathdelayortimingcheckthatmatches.
AnSDFconstructcanhavemultiplematches,inwhichcaseeachmatchingspecifystatementis
[Link]:
IOPATHismatchedtospecifypathdelaysorprimitives:
SDF

Verilog

(IOPATH(posedgeclk)q(3)(4)) (posedgeclk=>q)=0
(IOPATHay(3)(4))

bufu1(y,a)

[Link],thenall
primitivesthatdrivethespecifiedoutputportareannotated.
INTERCONNECTandPORTarematchedtoinputports:
SDF

Verilog

(INTERCONNECTu1.yu2.a(5)) inputa
(PORTu2.a(5))

inouta

Bothoftheseconstructsidentifyamoduleinputorinoutportandcreateaninternalnetthatisa
[Link](MIPD).Allprimitives,
specifypathdelays,andspecifytimingchecksconnectedtotheoriginalportarereconnectedtothe
newMIPDnet.
PATHPULSEandGLOBALPATHPULSEarematchedtospecifypathdelays:
SDF
(PATHPULSEay(5)(10))

Verilog
(a=>y)=0

(GLOBALPATHPULSEay(30)(60)) (a=>y)=0

IftheinputandoutputportsareomittedintheSDF,thenallpathdelaysarematchedinthecell.
DEVICEismatchedtoprimitivesorspecifypathdelays:
[Link]

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7/21/2016

SDFtoVerilogconstructmatching

SDF

Verilog

(DEVICEy(5)) andu1(y,a,b)
(DEVICEy(5)) (a=>y)=0(b=>y)=0

IftheSDFcellinstanceisaprimitiveinstance,thenthatprimitive'[Link]
moduleinstance,thenallspecifypathdelaysareannotatedthatdrivetheoutputportspecifiedinthe
DEVICEconstruct(allpathdelaysareannotatediftheoutputportisomitted).Ifthemodule
containsnopathdelays,thenallprimitivesthatdrivethespecifiedoutputportareannotated(orall
primitivesthatdriveanyoutputportiftheoutputportisomitted).
SETUPismatchedto$setupand$setuphold:
SDF

Verilog

(SETUPd(posedgeclk)(5)) $setup(d,posedgeclk,0)
(SETUPd(posedgeclk)(5)) $setuphold(posedgeclk,d,0,0)
HOLDismatchedto$holdand$setuphold:
SDF

Verilog

(HOLDd(posedgeclk)(5)) $hold(posedgeclk,d,0)
(HOLDd(posedgeclk)(5)) $setuphold(posedgeclk,d,0,0)
SETUPHOLDismatchedto$setup,$hold,and$setuphold:
SDF

Verilog

(SETUPHOLDd(posedgeclk)(5)(5)) $setup(d,posedgeclk,0)
(SETUPHOLDd(posedgeclk)(5)(5)) $hold(posedgeclk,d,0)
(SETUPHOLDd(posedgeclk)(5)(5)) $setuphold(posedgeclk,d,0,0)
RECOVERYismatchedto$recovery:
SDF

Verilog

(RECOVERY(negedgereset)(posedgeclk)(5)) $recovery(negedgereset,posedgeclk,0)
REMOVALismatchedto$removal:
SDF

Verilog

(REMOVAL(negedgereset)(posedgeclk)(5)) $removal(negedgereset,posedgeclk,0)
RECREMismatchedto$recovery,$removal,and$recrem:
SDF

Verilog

(RECREM(negedgereset)(posedgeclk)(5)(5)) $recovery(negedgereset,posedgeclk,0)
[Link]

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SDFtoVerilogconstructmatching

(RECREM(negedgereset)(posedgeclk)(5)(5)) $removal(negedgereset,posedgeclk,0)
(RECREM(negedgereset)(posedgeclk)(5)(5)) $recrem(negedgereset,posedgeclk,0)
SKEWismatchedto$skew:
SDF

Verilog

(SKEW(posedgeclk1)(posedgeclk2)(5)) $skew(posedgeclk1,posedgeclk2,0)
WIDTHismatchedto$width:
SDF

Verilog

(WIDTH(posedgeclk)(5)) $width(posedgeclk,0)
PERIODismatchedto$period:
SDF

Verilog

(PERIOD(posedgeclk)(5)) $period(posedgeclk,0)
NOCHANGEismatchedto$nochange:
SDF

Verilog

(NOCHANGE(negedgewrite)addr(5)(5)) $nochange(negedgewrite,addr,0,0)

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Voice:(503)6411340
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[Link]
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[Link]

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