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Unit 5

This document contains 8 multiple choice questions about field effect transistors and MOSFETs. The questions cover topics like pinch-off voltage, self bias circuits, calculating output voltage given transistor parameters, common source amplifier voltage gain, advantages of CMOS circuits, and characteristics of common source amplifiers. The answers provided are: 5.1(a), 5.2(b), 5.3(d), 5.4(a), 5.5(b), 5.6(b), 5.7(d), 5.8(c).

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Raj Patel
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149 views5 pages

Unit 5

This document contains 8 multiple choice questions about field effect transistors and MOSFETs. The questions cover topics like pinch-off voltage, self bias circuits, calculating output voltage given transistor parameters, common source amplifier voltage gain, advantages of CMOS circuits, and characteristics of common source amplifiers. The answers provided are: 5.1(a), 5.2(b), 5.3(d), 5.4(a), 5.5(b), 5.6(b), 5.7(d), 5.8(c).

Uploaded by

Raj Patel
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Unit V

Field Effect Transistors and MOSFETS


5.1 In a JFET drain current is maximum when VGS is
(a) Zero
(b) Positive
(c) Negative
(d) Equal to pinch-off voltage
5.2 An n-channel JFET has pinch-off voltage Vp = -4 volts. Given VGS = -1V, the
minimum VDS for the device to operate in the pinch-off region will be
(a) + 1V
(b) + 3V
(c) + 4V
(d) + 5V
5.3 In the self bias circuit for n-JFET shown in figure, VGS is

VDD = 15V
RD

2k

+
VDS

RG

10k

RS

3k

(a) + 5V
(b) 5V
(c) +6V
(d) -6V
5.4 Pick up the correct value of RS that will give Vout = 5V. The parameters of
MOSFET in the circuit shown are : VT = 2V and device constant k = 500A/v2

VDD = +12V

Vout
RS

(a) 400
(b) 600
(c) 800
(d) 1200

IS

5.5 The DMOSFET in the circuit shown has VGS(OFF) = - 6V and IDSS = 10mA. VOUT
is,

VDD = + 24V
RD

680
VOUT

RG

(a) 21.6 V
(b) 17.2 V
(c) 19.6 V
(d) 15.2 V

10M

5.6 For the common-source amplifier circuit shown, how much is the voltage gain?
The transconductance of the transistor is 4000S. Capacitors may be taken as
short as signal frequency.

VDD = +18V

RD

10k

0.5k
RG

5M

RS

RL

10k

(a) 40
(b) 20
(c) 10
(d) 6.6
5.7 The power consumption is least in CMOS circuits as compared to NMOS and
PMOS circuits. This is because, in CMOS
(a) Both the transistors remain in off-state most of the time.
(b) Small voltages are required.
(c) High value resistors are used
(d) Both the transistors go to on-state simultaneously only for a very short time
during change of states.

5.8 Which of the following statements is not true for common source (CS) amplifier.
(a) It is most widely used as compared to common-drain or common-gate
amplifiers
(b) It has high voltage gain
(c) There is no phase inversion
(d) It has high input impedance.

Answers:
5.1 (a)

5.2 (b)

5.7 (d)

5.8 (c)

5.3 (d)

5.4 (a)

5.5 (b)

5.6 (b)

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