DIGITAL LOGIC CIRCUITS CS437A, Fall Semester 2008
Instructor: Mr. Mubarak Banisakher
Office Phone: (386) 481-2675
Office: Science Hall 202
Email:
[email protected]Webpage: www4.cookman.edu/faculty/Banisakher
Office Hours: M: 9:00- 11:30AM, , TR: 11:15- 12:00 PM
Pre-Requisite Courses: CS332, PH252
Course Description:
This course covers the introduction to digital electronics, digital circuits, logic circuits, analog to digital converters, digital to analog
converters, as well their applications. It includes the study of logic gates, logic families, logic function implementation, flip-flops,
control circuits, codes, registers, encoders & decoders, multiplexers, counters, memory and converters. Practical experimentation and
a project support the content theory.
Goals
Thiscourseisintendedtoprovideacomprehensive,balancedanduptodatecoverageofdigitalcircuits;itisintendedtoteachdesign
andsynthesisoftwolevel/multilevelcombinationallogicaswellasfinitestatemachinedesign,optimization,andsynthesis.Material
reinforcedwiththeuseofcontemporaryEDAtools.Introducestheuseofahardwaredescriptionlanguage(VHDL).
Additionalgoalsare:
1)DotwolevellogicminimizationusingBooleanalgebra,Karnaughmaps,theQuineMcCluskeymethod,andtheEspressosoftware;
2)DomultilevellogicsimplificationusingfactoringandtheMISsoftware;
3)Developanduseadvancedtechnologymappingalgorithms;
4)Developadvancedtwolevelminimizationheuristics;
5)Designusingavarietyofimplementationtechnologies,e.g.,PLAs,multiplexors,CMOStransistors,andfieldprogrammablegate
arrays;
5)Drawandinterprettimingdiagrams;
6)Identifyandaccelerateacircuit'scriticaltimingpath;
7)Designstaticanddynamichazardfreelogic;
8)DoefficientFSMstateminimization,assignment,andsplitting;
9)Designvariousarithmetic,logic,andmemorycomponents,e.g.,ALUs,shifters,decoders,multiplexers,RAMs,andROMs;
10)DesigncombinationalandsequentialcircuitsusingVHDL;
11)UsearesearchqualityEDAsoftwaretoperformtwolevelcombinationallogicminimization,multilevelcombinationalsynthesis,
stateminimization,andstateassignmentofsequentiallogic;and
12)UseindustrialEDAtoolsforschematiccapture,gatelevellogicsimulationaswellasHDLsimulationandsynthesis .
Textbook: "Introduction to Logic and Computer Design
ISBN-13 978007352949-3.
McGraw-Hill Book Co., New York, N.Y.
Laboratory Manual Thereisnotextforthiscourse,butforlabworkalabmanualwillbeprovidedtothestudents,thatcarrythe
detailoftheexperimentsandrelatedinstructionstoperformtheexperiments.
Course Requirements:
The following are minimal requirements to be met by each student:
I. Lecture 8:00 9:00 a.m. MWF , S102
1. Regular attendance - The policy on class attendance as stated in the current University Catalog will be strictly adhered to.
2. Read all assigned material.
3. Take all exams and complete all assignments. There will be no make-up examinations except in cases of extreme
circumstances such as accidents or death in the family. A student missing examinations will be given a grade of zero (0).
4. Promptness. Frequent tardiness is discouraged. The teacher has the authority to admit or refuse admission when a student is
more than 15 minutes late.
II.
Laboratory 9:10 - 10:10 p.m. WF S203B
1. Attendance and participation are required.
2. Each experiment is to be carried out per the instructions given and written in the fashion supplied by the instructor.
Evaluation:
Each students final grade will be computed as follows:
-Lecture exams - There will be approximately six lecture exams
- Chapters review questions and other assignments
-Midterm exam - There will be one exam
-Final Exam
There will be one exam
- Attendance and class participation
Lab Evaluation
There will be about 15 Lab experiment upon completion.
Tests
Midterm
Final Exam
30 %
25
15%
25%
5%
50%
10%
15%
25%
Grading Scale:
90 - 100 = A
80 - 89 = B
70 - 79 = C
60 - 69 = D
Less than 60 = F
Methods of Instruction: Amixtureoflecturesanddemonstrationscombinewithgroupwork,PowerPointpresentationslideswillbe
usedintheclassroomandpostedontheclasswebpage.We'llcoverthecourse'sprimarytopicsinthesesessions,withreadingand
homeworkassignmentsthatprovideopportunitiestogainadeeperunderstandingoftheunderlyingissuesandtechniquesofdigital
circuits,thisIncludeexamplesofoutofclassassignments,requiredreadingandwritingassignments,andmethodsforteaching
criticalthinkingskills.)
a.Lectures
b.Handouts
c.Homeworkassignmentsfromthetextbook
e.Computerbasedtrainingactivities
f.Labactivities,Practical/Experimentation
g.Discussion
Use of Technology:Students use the workstations in Room203B lab. Students learn to use industrial EDA tools from the instructor.
Use of the internet for student-instructor communication, completion of assignments is required. Navigating the Internet and Email is
part of this course. As a result, you must follow all turn-in instructions carefully and save your assignments as a soft copy. Overhead
projector will be used in the classroom to run the class presentation.
Impact on BCU Mission and Institutional Student Learning Outcomes (ISLOs):
Through the attainment of the course student learning objectives (CSLOs), students will acquire knowledge, skills and competencies
outlined in the Institutional Student Learning Outcomes, School Student Learning Outcomes (SSLOs) and Program Student Learning
Outcomes (PSLOs) . The Course Student Learning Objectives fully support the University Mission and Core Values as stated in the
Strategic Plan; as well as, the School Goals.
Program Student Learning Outcomes (PSLOs) addressed in Course Learning Objectives.
PSLO1.Anabilitytoapplyknowledgeofcomputingandmathematicsappropriatetothediscipline
PSLO2.Anabilitytoanalyzeaproblem,andidentifyanddefinethecomputingrequirementsappropriatetoitssolution
PSLO3.Anabilitytodesign,implements,andevaluateacomputerbasedsystem,process,component,orprogramtomeetdesired
needs
PSLO4.Anabilitytofunctioneffectivelyonteamstoaccomplishacommongoal
PSLO5.Anunderstandingofprofessional,ethical,legal,securityandsocialissuesandresponsibilities
PSLO6.Anabilitytocommunicateeffectivelywitharangeofaudiences
PSLO7.Anabilitytoanalyzethelocalandglobalimpactofcomputingonindividuals,organizations,andsociety
PSLO8.Recognitionoftheneedforandanabilitytoengageincontinuingprofessionaldevelopment
PSLO9.Anabilitytousecurrenttechniques,skills,andtoolsnecessaryforcomputingpractice.
PSLO10. An ability to apply mathematical foundations, algorithmic principles, and computer science theory in the modeling and
design of computer-based systems in a way that demonstrates comprehension of the tradeoffs involved in design choices.
PSLO11.An ability to apply design and development principles in the construction of software systems of varying complexity
Course Student Learning Objectives and Measurements:
1: IntroductiontoLogic Circuits: Students will demonstrate knowledge of the following: (PSLO, 2, 3, 4,11)
1. Understand the principles of Boolean algebra (especially DeMorgans theorem) and the
techniques for transforming and simplifying Boolean expressions, including standard forms for
Boolean expressions.
2. Be able to analyze a schematic of a combinational logic circuit and write its logic function.
3. Given a functional description of a combinational circuit, write its logic function and design a
corresponding combinational logic circuit
2. ImplementationTechnology : Students will demonstrate knowledge of the following : (PSLO 1, 2, 3, 4,10)
1. Understand the architecture of NMOS and CMOS logic gates, using switch models for the
transistors.
2. Understand the overall architecture of PLDs; specifically PLA, PAL, CPLD, and FPGA families.
3. Be able to calculate some electrical properties of NMOS and CMOS circuits, including noise
margins, allowable fan-in/out, and power dissipation.
4. Be able to map simple functions onto PLDs manually.
5. Given a fusemap and/or LUT contents, determine what logic function is being computed.
3. Optimized Implementation of Logic Functions : Students will demonstrate knowledge of the following
: (PSLO, 2, 3, 4,9)
1. Find minimal sum-of-products (SOP) and product-of-sums (POS) expressions using Karnaugh
maps, and create a corresponding circuit from AND, OR, NAND, and NOR gates.
2. Know how to minimize logic functions where some of the input combinations will never occur
(dont care inputs).
4. Number Representation and Arithmetic : Students will demonstrate knowledge of the following : (PSLO,
2, 3, 6)
1. Know how to represent and convert numbers between different positional number systems,
including decimal, binary (unsigned, signed-magnitude, and twos complement), hex, and octal.
2. Do negation and addition in the twos complement number system, and detect overflow.
3. Understand the architecture of adder circuits, and how to implement them in VHDL.
5. Combinational Circuit Building Blocks: Students will demonstrate knowledge of the following: (PSLO,
2, 3, 4,6)
1. Understand the functionality of common digital building blocks including multiplexers, decoders,
encoders, and comparators. Know how to use them to implement logic functions.
2. Be able to calculate the propagation delays through a circuit and draw a timing diagram.
6. Sequential Circuit Elements: Students will demonstrate knowledge of the following : (PSLO 1, 2, 3, 4,5,7,11)
1. Predict the behavior of latches (S-R and D) and edge-triggered flip-flops (D, J-K, and T) in
response to time-varying inputs.
2. Understand the overall architecture of counters and shift registers, draw timing diagrams, and be
able to connect these devices together to realize larger or customized functions. Examples
include: cascaded counters, non-binary counters, self-correcting counters.
3. Given a logic diagram of a circuit incorporating a counter (or a PLD program), determine the
counting sequence.
7. State Machines: Students will demonstrate knowledge of the following : (PSLO 1, 2, 3, 4,8)
1. Understand the overall architecture of clocked synchronous state machines, and the difference
between Moore and Mealy machines.
2. Given a logic diagram of a clocked synchronous state machine (using D, J-K or T flip-flops),
analyze it to determine state and timing diagrams.
3. Be able to take a functional description of a clocked synchronous state machine, and design it out
of D flip-flops (or your choice of another kind) and combinational logic.
8. VHDL, CAD Tools, and PLDs : Students will demonstrate knowledge of the following : (PSLO, 2, 3, 4,9,10)
1.Beabletoread,modify,andwritesimpleVHDLprogramstoimplement:(a)logicandarithmetic
functions,(b)flipflops,(c)registersandcounters,(d)otherstatemachines.
2.BeabletousetheAlteraQuartussoftwareapplicationtodrawschematicsandrunsimulations.
StudentLearningOutcomesMatrix(SLOM)
AlignmentofCourseAssessmentswithSSEMGoals,
ProgramStudentLearningOutcomes,
CourseLearningObjectives,
InstitutionalStudentLearningOutcomesandUniversityStrategicGoals
Course
Assessments
Introductionto
LogicCircuits
Exams,written
assignments
Implementatio
nTechnology
Exams,written
assignments,lab
Optimized
Implementatio
nofLogic
Functions
Exams,written
assignments,lab
reports
CS437
Course
Learning
Objectives
StudentLearningOutcomesMatrix
ProgramStudentLearning
School
Institutional
Outcomes
Student
Student
Learning
Learning
Outcomes
Outcomes
SSEM
Goals
University
Strategic
Goals
1,2,3,4,5
1,3
TheStudentwill:
1,2,3
1,2,3,4,5
1,2
1. Demonstrate the
principles knowledge of
Boolean algebra (especially
DeMorgans theorem) and
the
techniques for transforming
and simplifying Boolean
expressions, including
standard forms for
Boolean expressions.
2. Demonstrate how to be
able to analyze a schematic
of a combinational logic
circuit and write its logic
function.
TheStudentwill:
1,2,3
1. Demonstrate
knowledge of the
architecture of NMOS and
CMOS logic gates, using
switch models for the
transistors.
2. Demonstrate knowledge
overall architecture of
PLDs; specifically PLA,
PAL, CPLD, and FPGA
families
TheStudentwill:
1,2,3
2. Demonstrate
knowledge of how to find
minimal sum-of-products
(SOP) and product-of-sums
(POS) expressions using
Karnaugh maps, and create
a corresponding circuit from
AND, OR, NAND, and
NOR gates.
3. Demonstrate how to
minimize logic functions
where some of the input
combinations will never
occur
1,2,3
1,2,3,4
1,2,3,4,5
1,2,3,4
1,2,3,4,5
1,3,
1,2,3,4,5
1,2,3,4
1,2,3,4,5
1,3,
(dont care inputs).
Number
Representation
andArithmetic
Exams,written
assignments,lab
reports
TheStudentwill:
1,2,3
Combinational
Circuit
Building
Blocks
Exams,written
assignments,lab
reports
Sequential
Circuit
Elements
Exams,written
assignments,lab
reports
1,2
1,2,3
1,2,3,4,5
2. Demonstrate
knowledge of knowing how
to represent and convert
numbers between different
positional number systems,
including decimal, binary
(unsigned, signedmagnitude, and twos
complement), hex, and
octal.
4. Demonstrate knowledge
of do negation and addition
in the twos complement
number system, and detect
overflow.
1,2,3
1,2,3,4
1,2,3,4,5
1,3,
1. Demonstrate knowledge
of the functionality of
common digital building
blocks including
multiplexers, decoders,
encoders, and comparators.
Know how to use them to
implement logic functions.
2. Demonstrate knowledge
of being able to calculate
the propagation delays
through a circuit and draw a
timing diagram.
1,2,3
1,2,3,4
1,2,3,4,5
1,3,
1. Demonstrate knowledge
of predicting the behavior
of latches (S-R and D) and
edge-triggered flip-flops (D,
J-K, and T) in
response to time-varying
inputs.
2. Demonstrate knowledge
of understanding the overall
architecture of counters and
shift registers, draw timing
diagrams, and be
able to connect these
devices together to realize
larger or customized
functions. Examples
include: cascaded counters,
non-binary counters, selfcorrecting counters.
1,2,3
1,2,3,4
1,2,3,4,5
1,3,
StateMachines
Exams,written
assignments,lab
reports
VHDL,CAD
Tools,and
PLDs
Exams,written
assignments,lab
reports
1,2,3
1,2
1. Demonstrate knowledge
of the overall architecture of
clocked synchronous state
machines, and the difference
between Moore and Mealy
machines.
2. Demonstrate knowledge
of a logic diagram of a
clocked synchronous state
machine (using D, J-K or T
flip-flops), analyze it to
determine state and timing
diagrams.
3. Demonstrate. knowledge
of being able to take a
functional description of a
clocked synchronous state
machine, and design it out
of D flip-flops (or your
choice of another kind) and
combinational logic.
1,2,3
1,2,3,4
1,2,3,4,5
1,3,
1. Demonstrate. knowledge
of being able to read,
modify, and write simple
VHDL programs to
implement:
(a) logic and arithmetic
functions,
(b) flip-flops,
(c) registers and counters,
(d) other state machines.
1,2,3
1,2,3,4
1,2,3,4,5
1,3,
Topical Outline and Lecture Schedule
Week
1
1)Introduction
Topic
2) Combinational Systems
ReviewofNumbersystems.TheDesignProcessfor
CombinationalSystems.IntroductiontoDontCare
Conditions.
(
TheDevelopmentofTruthTables.SwitchingAlgebra.
ManipulationofAlgebraicFunctions.Implementation
ofFunctionswithGates.FromTruthTabletoAlgebraic
Expressions.IntroductiontoKarnaughMap.
Assignmentdu
HomeWork#1)Exercises(1,2,3,4,5
HomeWork#2,Exercises(1,2,3,4,5
LAB#1)
Exam1
(
3
3)TheKarnaughMap
4) Designing Combinational Systems
5)AnalysisofSequentialSystems
6) The Design of Sequential Systems
(HomeWork#3,Exercises(1,2,3,4,
ComplementandProductofSums.NAND,NOR,XOR LAB#2)
Gates.SimplificationofAlgebraicExpressions.NAND Exam2
GateImplementation.GeneralBooleanAlgebra.
(HomeWork#4,Exercises(1,2,3,4,
MinimumSumofProductExpressionsUsingKarnaugh LAB#3)
Map.MinimumCostGateImplementations.
FunctionMinimizationAlgorithms.
DelayinCombinationalLogicCircuits.Arithmetic
Circuits.Decoders.Encoders.Mulitplexers.
7
(HomeWork#5,Exercises(1,2,3,4,
LAB#4)
Exam3
(HomeWork#6,Exercises(1,2,3,4,
LAB#5)
MIDSEMESTEREXAM
7)SolvingLargerSequentialProblems
ThreeStateGates.GateArrays.LargerCombinational
Systems.
(HomeWork#7,Exercises(1,2,3,4,
LAB#6)
Exam4
8) Computer Organization
(HomeWork#8,Exercises(1,2,3,4,
LAB#7)
LatchesandFlipFlops.AnalysisofSequentialSystems.
10
9)ComputerDesignFundamentals
FlipFlopDesign.SynchronousCounters.Asynchronous
Counters.
(HomeWork#9,Exercises(1,2,3,4,
LAB#8)
Exam5
11
10) The Design of a Central Processing Unit
(HomeWork#10,Exercises(1,2,3,4
LAB#9)
ShiftRegisters.Counters.PLDs.
12
11)BeyondtheCentralProcessingUnit
(HomeWork#11,Exercises(1,2,3,4
LAB#10)
Exam6
13
SimplificationofSequentialCircuits.
(HomeWork#12,Exercises(1,2,3,4
LAB#11)
FINALEXAM
1415
HardwareDesignLanguages.Simplificationof
SequentialCircuits.
