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Lecture-3
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Design Styles
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Design Styles
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Design
Issues
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Performance
Area
Cost
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Design Styles
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Full Custom
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Standard Cell
Gate Array
EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
FPGA
Full Custom Design Style
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This style involves the design of every component from scratch.
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This method is followed if there are no libraries available.
All the mask layers are customized.
Very expensive in terms of effort and cost
High Performance and speed.
Time to market is very high.
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Example Back
EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
Standard Cell Design Style
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Allows the use of standard cells defined in the cell library .
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Each standard cell in the cell library is constructed using full custom
design style.
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This library contains hundreds of different logic cells like AND,OR, etc.
We can change the transistor size in a standard cell to optimize the cell
for speed and performance.
All Mask layers are customized.
Helps in reduced design times.
CAD tools are used to choose blocks and interconnect them.
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Example Back
EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
Gate Array Design Style
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1.
Transistors are pre defined on the silicon wafer. This predefined pattern
2.
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of transistors on a gate array is the base array.
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The designer chooses from the gate array library of pre designed logic
cells. These cells are called as Macros.
3.
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The transistor size cannot be changed to optimize the cell for speed and
area.
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There are 3 different types i) Channeled ii) channel less iii) Structured.
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Example Back
EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
FPGA Field Programmable Gate Array
1.
The core is the regular array of programmable basic logic cells that can
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implement combinational as well as sequential logic. These cells are
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called as CLB s.
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2.
A programmable interconnects surrounds these basic logic cells.
3.
Programmable I/O cells surround the core.
4.
None of the mask layers are customized.
5.
Design takes only few hours.
6.
Used Mainly for circuit prototyping.
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EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
Example Back
Example
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Back
EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
Example
N Well
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VDD
Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects
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Cell height is 12 pitch
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In
Out
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Cell boundary
GND
Rails ~10
Standard Cell - Inverter
EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
Example
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Back
EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
Gate Array, Semi-Custom, and Full-Custom ICs
VLSI Technology
Gate Array
Standard Cell
Chip Area Ratios:
3:2:1
Full Custom
EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
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Which is Better
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Comparison of design styles
Full
Custom
Standard
Cell
Gate array FPGA
Variable
Fixed
Fixed
Fixed
Variable
Variable
Fixed
Programmabl
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Cell Placement
Variable
Variable
Fixed
Fixed
Inter
Connections
Variable
Variable
Variable
Programmabl
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Packaging
Density
Best
Moderate
Poor
Very Poor
Unit Cost in
Large Quantities
Very Low
Moderate
High
Very High
Unit Cost in
Small Quantities
Very High
High
Moderate
Very Low
Cell size
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Cell Type
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EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
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Comparison of design styles contd
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Design and
Simulation
Total Area
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Full
Custom
Standard
Cell
Gate array
FPGA
Complex
Moderate
Moderate
Very Easy
Less
Moderate
Moderate
Very High
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Performance Best
and Speed
Better
Good
Average
Time to
Market
Very High
High
Moderate
Very Less
Modifying
the Design
Very
Difficult
Easy
Very Easy
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Difficult
EEE588 Digital IC Design -VLSI
DIVISION-2010 FALL
