UCS1903
3-Channel LED Driver / Controller
l
GENERAL DESCRIPTION
Unlimited cascading is possible in linear
transfer mode.
The UCS1903 is a 3-channel LED display
driver / controller with a built-in MCU digital
interface, data latches and LED high
voltage driving functions. It features superior
performances and reliable functions. Under
the control of the external MCU, it performs
independent grayscale control and cascading
control for driving large outdoor colour dotmatrix LED panels.
any two points. No additional circuitry is
necessary.
l At the refresh speed of 30 frames / s,
up to 512 cascaded dots are possible
at the low-speed mode, and up to 1024
cascaded dots are possible at the highspeed mode.
l
FEATURES
Over 10-meter transfer distance between
Data transfer rates of up to 400kbps or
800kbps.
12V-rated output port.
6V to 12V operating voltage.
PIN CONFIGURATION
l Grayscle adjustment function (256-level
adjustable grayscle).
SOP8
l Built-in dual RC oscillators for clock
synchronization with the signals on the
data line. After the first data is received,
the subsequent data will be shaped and
forwarded automatically.
OUTR
VDD
Built-in power-on reset function.
OUTG
SET
256-level adjustment is possible through
OUTB
DIN
the PWM control, with the scanning
GND
frequency up to 400Hz/s.
l Serial cascade interface, with the data
received and decoded on one wire.
PIN DESCRIPTION
Number
Symbol
Name
OUTR
LED drive output
Red PWM control output
OUTG
LED drive output
Green PWM control output
OUTB
LED drive output
Blue PWM control output
GND
Ground
V. 1.0
Function Description
Ground
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DOUT
UCS1903
V. 1.0
2 of 9
UCS1903
5
DOUT
Data output
Display data cascaded output
DIN
Data input
SET
Mode setting
VDD
Logic power supply
Display data input
Connected to VDD: Low speed mode;
Floating: High speed mode
ABSOLUTE MAXIMUM RATINGS (TA =25, VSS =0V, unless otherwise specified)
Parameter
Symbol
Value
Unit
Logic supply voltage
VDD
+6.0 to +7.0
Output port rated voltage
VOUT
12
VI
0.5 to VDD+0.5
Operating temperature
TOPT
25 to +85
Storage temperature
TSTG
55 to +150
Logic input voltage
RECOMMENDED OPERATNG RANGES (TA =20 to +70, VSS =0V, unless otherwise
specified)
Parameter
Symbol
Min.
Typ.
Max
Unit
Logic supply voltage
VDD
High level input voltage
VIH
0.7VDD
VDD
Low level input voltage
VIL
0.3VDD
ELECTRICAL CHARACTERISTICS (TA =20 to +70, VDD =4.5 to 5.5V, VSS =0V, unless
otherwise specified)
Parameter
Symbol
Min.
Typ.
Max
Unit
Test conditions
Low level output current
IOL1
17
mA
G, B
Low level output current
IOL2
18
mA
Low level output current
Idout
10
mA
VO =0.4V, DOUT
II
VI =VDD /VSS
High level input voltage
VIH
0.7VDD
DIN, SET
Low level input voltage
VIL
0.3VDD
DIN, SET
Voltage hysteresis
VH
0.35
DIN, SET
Input current
V. 1.0
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UCS1903
SWITCHING CHARACTERISTICS (TA =20 to +70, VDD =4.5 to 5.5V, VSS =0V, unless
otherwise specified)
Parameter
Symbol
Min.
Typ.
Max
Unit
Test conditions
FOSC1
400
kHz
FOSC2
800
kHz
Propagation delay time
tPLZ
300
ns
CL =15pF, DINDOUT,
RL =10k
Fall time
tTHZ
120
CL =300pF, OUTR/OUTG/
OUTB
Data transfer rate
FMAX
400
kbps
50% duty cycle
Input capacitance
CI
15
pF
Oscillation frequency
FUNCTIONAL DESCRIPTION
The UCS1903 sends signals in return to zero codes with a single-wire communication method.
When the power-on reset is completed, the UCS1903 receives the data from the DIN pin. When
all the 24 bits of data have been received, the DOUT port starts to forward the data to the next
chip as its input data. The DOUT pin is held LOW before the data forwarding, and the chip does
not receive new data. The three PWM output ports, OUTR, OUTG and OUTB, send signals
in a 4-ms period, with different duty cycles corresponding to the 24-bit data received. If the
input signal from the DIN pin is a RESET signal, the UCS1903 will send the received data for
display. When the signal is completed, the UCS1903 will receive new data. When all the initial
24 bits of data have been received, the UCS1903 will forward the data through the DOUT pin.
Before the RESET signal is received, the output at the OUTR, OUTG and OUTB pins will remain
unchanged. When a low level RESET code longer than 24s is received, the UCS1903 will
output the 24-bit PWM data just received to the OUTR, OUTG and OUTB pins.
The UCS1903 employs an automatic shaping-forwarding technique, so the number of the
cascaded chips is not limited by the signal transfer, and is only limited by the panel refresh
speed. For example, in a 1024-chip cascaded design with the panel refresh time of 1024X0.4X2
=0.8192ms (the data delay time of the UCS1903 is 0.4s), no flickering will appear.
V. 1.0
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UCS1903
TIMING WAVEFORMS
1 Input code
RESET
2 Low-speed mode time
Name
Description
Typ. value
Allowable error
T0H
code 0, high level time
0.5s
150ns
T1H
code 1, high level time
2.0s
150ns
T0L
code 0, low level time
2.0s
150ns
T1L
code 1, low level time
0.5s
150ns
Note: In the high-speed mode, only half of the above time is needed (the time for code RESET is
not changed).
3 Connection scheme
Chip 1
V. 1.0
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UCS1903
4 Data transfer format
24s
Data refresh
cycle 2
Data refresh
cycle 1
D1
1st 24 bits
D2
D3
2nd 24 bits
3rd 24 bits
RESET
CODE
2nd 24 bits
3rd 24 bits
RESET
CODE
3rd 24 bits
RESET
CODE
1st 24 bits
2nd 24 bits
3rd 24 bits
RESET
CODE
2nd 24
bits
3rd 24 bits
RESET
CODE
3rd 24 bits
RESET
CODE
D4
Note: D1 is the data sent from the MCU, D2, D3 and D4 are the data automatically shaped and
forwarded by the cascaded circuit.
5 24-bit data format
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Note: The data is sent in the sequence of RGB, and the MSB is sent first.
V. 1.0
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UCS1903
APPLICATION DIAGRAM
VC
C
612V
1
2
3
4
VC
C
612V
VDD
SET
DIN
DO
OUTR
OUTG
OUTB
GND
VDD
SET
DIN
DO
OUTR
OUTG
OUTB
GND
VDD
SET
DIN
DO
8
7
6
5
104
GND
MCUDATA
GND
1
2
3
4
VC
C
OUTR
OUTG
OUTB
GND
8
7
6
5
104
8
7
6
5
104
GND
612V
1
2
3
4
V. 1.0
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GND
DO
UCS1903
The power supply voltage for the UCS1903 may be selected from 6V to 12V. A 104 capacitor
between the power supply and the ground should be connected as close to the UCS1903
package as possible, and the PCB traces should be as short as possible. A resistor R should be
connected between the power supply and the VDD pin, with the resistance value determined in
reference to the supply voltage. The recommended resistance value is as follows:
Supply Voltage
Recommended power supply resistor value
6V
1k
9V
4k
12V
7k
In practical applications, the VDD voltage is constant at about 5V. When the SET pin is
connected to high level, it should be connected to VDD. It should not be connected to external
Power supply VCC, so as to prevent chip breakdown.
V. 1.0
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UCS1903
PACKAGE OUTLINE DRAWING AND DIMENSION
SOP 8
Symbol
A
A1
A2
b
c
D
E
E1
e
L
In mm
In inches
Min.
Max.
0.053
0.069
0.004
0.010
0.053
0.061
0.013
0.020
0.006
0.010
0.185
0.200
0.150
0.157
0.228
0.244
0.050 (BSC)
0.016
0.050
0
8
Min.
Max.
1.350
1.750
0.100
0.250
1.350
1.550
0.330
0.510
0.170
0.250
4.700
5.100
3.800
4.000
5.800
6.200
1.270 (BSC)
0.400
1.270
0
8
V. 1.0
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