AE2406 AVIONICS LAB

VII SEM
AERONAUTICAL ENGINEERING

PREPARED BYMr.M.MAGESH

AE2405 AVIONICS LAB

VII Semester Aero
Syllabus

CYCLE I - 8085 MICROPROCESSORS

1. Addition and Subtraction of 8-bit and 16-bit numbers.
2. Sorting of Data in Ascending & Descending order.
3. Sum of a given series with and without carry.
4. Greatest in a given series & Multi-byte addition in BCD mode.
5. Interface programming with 4 digit 7 segment Display & Switches &
LEDs.
6. 16 Channel Analog to Digital Converter & Generation of Ramp, Square,
Triangular wave by Digital to Analog Converter.
CYCLE II - DIGITAL ELECTRONICS
7. Addition/Subtraction of binary numbers.
8. Multiplexer/Demultiplexer Circuits.
9. Encoder/Decoder Circuits.
10. Timer Circuits, Shift Registers, Binary Comparator Circuits.
CYCLE III - AVIONICS DATA BUSES
11. Study of Different Avionics Data Buses.
12. MIL-Std 1553 Data Buses Configuration with Message transfer.
13. MIL-Std 1553 Remote Terminal Configuration.

1. INTRODUCTION TO 8085
INTEL 8085 is one of the most popular 8-bit microprocessor capable of
addressing 64 KB of memory and its architecture is simple. The device has 40 pins,
requires +5 V power supply and can operate with 3MHz single phase clock.
ALU (Arithmetic Logic Unit):
The 8085A has a simple 8-bit ALU and it works in coordination with the
accumulator, temporary registers, 5 flags and arithmetic and logic circuits. ALU has
the capability of performing several mathematical and logical operations. The
temporary registers are used to hold the data during an arithmetic and logic operation.
The result is stored in the accumulator and the flags are set or reset according to the
result of the operation. The flags are affected by the arithmetic and logic operation.
They are as follows:

Sign flag
After the execution of the arithmetic - logic operation if the bit D7
of the result is 1, the sign flag is set. This flag is used with signed
numbers. If it is 1, it is a negative number and if it is 0, it is a positive
number.

Zero flag
The zero flag is set if the ALU operation results in zero. This flag
is modified by the result in the accumulator as well as in other registers.

Auxillary carry flag

In an arithmetic operation when a carry is generated by digit D3
and passed on to D4, the auxillary flag is set.

Parity flag
After arithmetic logic operation, if the result has an even number
of 1s the flag is set. If it has odd number of 1s it is reset.

Carry flag
If an arithmetic operation results in a carry, the carry flag is set.
The carry flag also serves as a borrow flag for subtraction.

Timing and control unit

This unit synchronizes all the microprocessor operation with a clock and
generates

the

control

signals

necessary for

communication

between

the

microprocessor and peripherals. The control signals RD (read) and WR (write)

indicate the availability of data on the data bus.
Instruction register and decoder
The instruction register and decoder are part of the ALU. When an instruction is
fetched from memory it is loaded in the instruction register. The decoder decodes the
instruction and establishes the sequence of events to follow.
Register array
The 8085 has six general purpose registers to store 8-bit data during program
execution. These registers are identified as B, C, D, E, H and L. they can be combined
as BC, DE and HL to perform 16-bit operation.
Accumulator
Accumulator is an 8-bit register that is part of the ALU. This register is used to
store 8-bit data and to perform arithmetic and logic operation. The result of an
operation is stored in the accumulator.
Program counter
The program counter is a 16-bit register used to point to the memory address of
the next instruction to be executed.

Stack pointer
It is a 16-bit register which points to the memory location in R/W memory, called
the Stack.

Communication lines
8085 microprocessor performs data transfer operations using three communication
lines called buses. They are address bus, data bus and control bus.

Address bus it is a group of 16-bit lines generally identified as A 0 A15.

The address bus is unidirectional i.e., the bits flow in one direction from
microprocessor to the peripheral devices. It is capable of addressing 2 16
memory locations.

Data bus it is a group of 8 lines used for data flow and it is bidirectional.
The data ranges from 00 FF.

Control bus it consist of various single lines that carry synchronizing

signals. The microprocessor uses such signals for timing purpose.

2(A). 8 BIT DATA ADDITION

AIM:
To add two 8 bit numbers stored at consecutive memory locations.
ALGORITHM:
1.
2.
3.
4.

Initialize memory pointer to data location.

Get the first number from memory in accumulator.
Get the second number and add it to the accumulator.
Store the answer at another memory location.

RESULT:
Thus the 8 bit numbers stored at 4500 &4501 are added and the result stored at 4502 &
4503.

FLOW CHART:
START

[C]

00H

[HL]

4500H

[A]

[M]

[HL][HL]+1

[A][A]+[M]

NO
Is there a
Carry ?YES

[C][C]+1

[HL][HL]+1

[M]

[A]

[HL][HL]+1

[M]

[C]

STOP

PROGRAM:
ADDRESS OPCODE LABEL
4100
START
4101
4102
4103
4104
4105

MNEMONICS OPERAND
MVI
C, 00

COMMENT
Clear C reg.

LXI

H, 4500

Initialize HL reg. to
4500

MOV

A, M

4106

INX

4107

ADD

4108
4109
410A

JNC

L1

Transfer first data to

accumulator
Increment HL reg. to
point next memory
Location.
Add first number to
acc. Content.
Jump to location if
result does not yield
carry.

410B
410C

INR
INX

C
H

410D

MOV

M, A

410E

INX

410F
4110

MOV
HLT

M, C

L1

Increment C reg.
Increment HL reg. to
point next memory
Location.
Transfer the result from
acc. to memory.
Increment HL reg. to
point next memory
Location.
Move carry to memory
Stop the program

OBSERVATION:
INPUT
4500
4501

OUTPUT
4502
4503

2(B). 8 BIT DATA SUBTRACTION

AIM:
To Subtract two 8 bit numbers stored at consecutive memory locations.
ALGORITHM:
1.
2.
3.
4.

Initialize memory pointer to data location.

Get the first number from memory in accumulator.
Get the second number and subtract from the accumulator.
If the result yields a borrow, the content of the acc. is complemented and 01H is
added to it (2s complement). A register is cleared and the content of that reg. is
incremented in case there is a borrow. If there is no borrow the content of the acc.
is directly taken as the result.
5. Store the answer at next memory location.
RESULT:
Thus the 8 bit numbers stored at 4500 &4501 are subtracted and the result stored at 4502
& 4503.

FLOW CHART:
START

[C]

00H

[HL] 4500H

[A]

[M]

[HL][HL]+1

[A][A]-[M]

Is there a

NO

Borrow ?

YES
Complement [A]
Add 01H to [A]
[C][C]+1

[HL][HL]+1

[M]

[A]

[HL][HL]+1

[M]

[C]

STOP

10

PROGRAM:
ADDRESS OPCODE LABEL
4100
START
4102
4102
4103
4104
4105

MNEMONICS OPERAND
MVI
C, 00

COMMENT
Clear C reg.

LXI

H, 4500

Initialize HL reg. to
4500

MOV

A, M

4106

INX

4107

SUB

4108
4109
410A

JNC

L1

Transfer first data to

accumulator
Increment HL reg. to
point next mem.
Location.
Subtract first number
from acc. Content.
Jump to location if
result does not yield
borrow.

410B
410C

INR
CMA

410D
410E
410F

ADI

01H

INX

4110

MOV

M, A

4111

INX

4112
4113

MOV
HLT

M, C

L1

Increment C reg.
Complement the Acc.
content
Add 01H to content of
acc.
Increment HL reg. to
point next mem.
Location.
Transfer the result from
acc. to memory.
Increment HL reg. to
point next mem.
Location.
Move carry to mem.
Stop the program

OBSERVATION:
INPUT
4500
4501

OUTPUT
4502
4503

11

3(A). 8 BIT DATA MULTIPLICATION

AIM:
To multiply two 8 bit numbers stored at consecutive memory locations and store
the result in memory.
ALGORITHM:
LOGIC: Multiplication can be done by repeated addition.
1.
2.
3.
4.
5.
6.
7.
8.

Initialize memory pointer to data location.

Move multiplicand to a register.
Move the multiplier to another register.
Clear the accumulator.
Add multiplicand to accumulator
Decrement multiplier
Repeat step 5 till multiplier comes to zero.
The result, which is in the accumulator, is stored in a memory location.

RESULT:
Thus the 8-bit multiplication was done in 8085p using repeated addition method.

12

FLOW CHART:
START

[HL] 4500
B M
[HL] [HL]+1

A 00

C 00
[A] [A] +[M]

Is there
any
carry

NO

YES
C C+1
B B-1

NO

IS
B=0
YES
A

13

A
[HL][HL]+1

[M]

[A]

[HL][HL]+1

[M]

[C]

STOP

14

PROGRAM:
ADDRESS OPCODE LABEL
4100
START
4101
4102
4103

MNEMONICS
LXI

OPERAND
H, 4500

COMMENT
Initialize HL reg. to
4500

MOV

B, M

4104

INX

4105
4106
4107
4108

MVI

A, 00H

Transfer first data to

reg. B
Increment HL reg. to
point next mem.
Location.
Clear the acc.

MVI

C, 00H

Clear C reg for carry

ADD

410A

JNC

NEXT

410B
410C
410D
410E
410F
4110
4111
4112

Add multiplicand
multiplier times.
Jump to NEXT if there
is no carry

INR
DCR
JNZ

C
B
L1

Increment C reg
Decrement B reg
Jump to L1 if B is not
zero.

INX

4113

MOV

M, A

4114

INX

4115

MOV

M, C

4116

HLT

Increment HL reg. to
point next mem.
Location.
Transfer the result from
acc. to memory.
Increment HL reg. to
point next mem.
Location.
Transfer the result from
C reg. to memory.
Stop the program

4109

L1

NEXT

OBSERVATION:
INPUT
4500
4501

OUTPUT
4502
4503
15

3(B). 8 BIT DIVISION

AIM:
To divide two 8-bit numbers and store the result in memory.
ALGORITHM:
LOGIC: Division is done using the method Repeated subtraction.
1. Load Divisor and Dividend
2. Subtract divisor from dividend
3. Count the number of times of subtraction which equals the quotient
4. Stop subtraction when the dividend is less than the divisor .The dividend now
becomes the remainder. Otherwise go to step 2.
5. stop the program execution.
RESULT:
Thus an ALP was written for 8-bit division using repeated subtraction method and
executed using 8085 p kits

16

FLOWCHART:
START

B 00
[HL] 4500
A M
[HL] [HL]+1
M A-M

[B] [B] +1

IS A<0

NO

YES
A A+ M

B B-1

[HL][HL]+1

[M]

[A]

[HL][HL]+1

[M]

[B]

STOP

17

PROGRAM:
ADDRESS

OPCODE LABEL

MNEMO
NICS
MVI

OPERA
ND
B,00

LXI

H,4500

MOV
INX

A,M
H

SUB
INR
JNC

M
B
LOOP

ADD
DCR
INX

M
B
H

410F

MOV

M,A

4110

INX

4111

MOV

M,B

4112

HLT

4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E

LOOP

COMMENTS
Clear B reg for quotient
Initialize HL reg. to
4500H
Transfer dividend to acc.
Increment HL reg. to point
next mem. Location.
Subtract divisor from dividend
Increment B reg
Jump to LOOP if result does
not yield borrow
Add divisor to acc.
Decrement B reg
Increment HL reg. to point
next mem. Location.
Transfer the remainder from
acc. to memory.
Increment HL reg. to point
next mem. Location.
Transfer the quotient from B
reg. to memory.
Stop the program

OBSERVATION:
S.NO
1
2

ADDRESS
4500
4501
4500
4501

INPUT
DATA

ADDRESS
4502
4503
4502
4503

OUTPUT
DATA

18

4(A). 16 BIT DATA ADDITION

AIM:
To add two 16-bit numbers stored at consecutive memory locations.
ALGORITHM:
1.
2.
3.
4.

Initialize memory pointer to data location.

Get the first number from memory and store in Register pair.
Get the second number in memory and add it to the Register pair.
Store the sum & carry in separate memory locations.

RESULT:
Thus an ALP program for 16-bit addition was written and executed in 8085p
using special instructions.

19

FLOW CHART:
START

[L]
[H]

[4050 H]
[4051 H]

[DE]

[HL]

[L]
[H]

[4052H]
[4053H]

[A]00H

[HL][HL]+[DE]

Is there a
Carry?

NO

YES
[A][A]+1

[4054][ L]

[4055] [H]

[4056]

[A]

STOP

20

PROGRAM:
ADDRESS OPCODE LABEL
4000
START
4001
4002
4003
4004
4005
4006
4007
4008
4009

MNEMONICS OPERAND
LHLD
4050H

400A
400B
400C
400D
400E
400F
4010
4011
4012
4013
4014

LOOP

COMMENT
Load the augend in DE
pair through HL pair.

XCHG
LHLD

4052H

Load the addend in HL

pair.

MVI

A, 00H

DAD

JNC

LOOP

INR

SHLD

4054H

STA

4056H

Initialize reg. A for

carry
Add the contents of HL
Pair with that of DE
pair.
If there is no carry, go
to the instruction
labeled LOOP.
Otherwise increment
reg. A
Store the content of HL
Pair in 4054H(LSB of
sum)
Store the carry in
4056H through Acc.
(MSB of sum).
Stop the program.

HLT

OBSERVATION:

ADDRESS
4050H
4051H
4052H
4053H

INPUT
DATA

ADDRESS
4054H
4055H
4056H

OUTPUT
DATA

21

4(B). 16 BIT DATA SUBTRACTION

AIM:
To subtract two 16-bit numbers stored at consecutive memory locations.
ALGORITHM:
1.
2.
3.
4.
5.

Initialize memory pointer to data location.

Get the subtrahend from memory and transfer it to register pair.
Get the minuend from memory and store it in another register pair.
Subtract subtrahend from minuend.
Store the difference and borrow in different memory locations.

RESULT:
Thus an ALP program for subtracting two 16-bit numbers was written and
executed.

22

FLOW CHART:
START

[L]
[H]

[4050 H]
[4051 H]

[DE]

[HL]

[L]
[H]

[4052H]
[4053H]

[HL][HL]-[DE]

Is there a
borrow?

NO

YES
[C][C]+1

[4054][ L]

[4055] [H]

[4056]

[C]

STOP

23

PROGRAM:
ADDRESS OPCODE LABEL

MNEMO
NICS
MVI

OPER COMMENTS
AND
C, 00
Initialize C reg.

LHLD

4050H

Load the subtrahend in DE

reg. Pair through HL reg.
pair.

XCHG
LHLD

4052H

Load the minuend in HL reg.

Pair.

MOV

A, L

400A

SUB

400B

MOV

L, A

400C

MOV

A, H

400D

SBB

400E

MOV

H, A

400F
4010
4011
4012
4013
4014
4015
4016

SHLD

4054H

Move the content of reg. L to

Acc.
Subtract the content of reg.
E from that of acc.
Move the content of Acc. to
reg. L
Move the content of reg. H to
Acc.
Subtract content of reg. D
with that of Acc.
Transfer content of acc. to
reg. H
Store the content of HL pair
in memory location 8504H.

JNC

NEXT

If there is borrow, go to the

instruction labeled NEXT.

INR
MOV

C
A, C

STA

4056H

Increment reg. C
Transfer the content of reg. C
to Acc.
Store the content of acc. to
the memory location 4506H

4000
4001
4002
4003
4004
4005
4006
4007
4008
4009

START

NEXT

4017
4018
4019
401A

HLT

Stop the program execution.

OBSERVATION:
ADDRESS
4050H
4051H
4052H
4053H

INPUT
DATA

ADDRESS
4054H
4055H
4056H

OUTPUT
DATA

24

5(A). 16 BIT MULTIPLICATION

AIM:
To multiply two 16 bit numbers and store the result in memory.
ALGORITHM:
1.
2.
3.
4.

Get the multiplier and multiplicand.

Initialize a register to store partial product.
Add multiplicand, multiplier times.
Store the result in consecutive memory locations.

RESULT:
Thus the 16-bit multiplication was done in 8085p using repeated addition
method.

25

FLOWCHART:
START
L
H

[4050]
[4051]

SP HL

L
H

[4052]
[4053]

DE

HL

HL0000
BC0000

HLHL+SP

Is Carry
flag set?

BCBC+1

DEDE+1

Is Zero
flag set?

26

NO

YES

NO
YES
A

[4054]
[4055]

L
H

[4056]
[4057]

C
B

STOP

27

ADDRESS OPCODE LABEL MNEM

8000
4001
4002
4003
4004
4005
4006
4007
4008
4009
400A
400B
400C
400D
400E
400F
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
401A
401B
401C
401D
401E
401F
4020
4021
4022
4023
4024

START

OPERAN COMMENTS
O
D
N
I
C
S
LHLD
4050
Load the first No. in stack pointer
through HL reg. pair
SPHL
LHLD

4052

XCHG
LXI

H, 0000H

LXI

B, 0000H

DAD
JNC

SP
NEXT

Add SP with HL pair.

If there is no carry, go to the
instruction labeled NEXT

INX
DCX
MOV
ORA
JNZ

B
D
A,E
D
LOOP

Increment BC reg. pair

Decrement DE reg. pair.
Move the content of reg. E to Acc.
OR Acc. with D reg.
If there is no zero, go to instruction
labeled LOOP

SHLD

4054

MOV
STA

A, C
4056

Store the content of HL pair in

memory locations 4054 &
4055.
Move the content of reg. C to Acc.
Store the content of Acc. in
memory location 4056.

MOV
STA

A, B
4057

Load the second No. in HL reg.

pair
& Exchange with DE reg. pair.

Clear HL & DE reg. pairs.

LOOP

NEXT

HLT

Move the content of reg. B to Acc.

Store the content of Acc. in
memory location 4056.
Stop program execution

28

OBSERVATION:
ADDRESS

INPUT
DATA

OUTPUT
ADDRESS
DATA

4050
4051
4052

4054
4055
4056

4053

4057

5(B). 16- BIT DIVISION

AIM:
To divide two 16-bit numbers and store the result in memory using 8085
mnemonics.
ALGORITHM:
1.
2.
3.
4.
5.

Get the dividend and divisor.

Initialize the register for quotient.
Repeatedly subtract divisor from dividend till dividend becomes less than divisor.
Count the number of subtraction which equals the quotient.
Store the result in memory.

RESULT:
Thus the 16-bit Division was done in 8085p using repeated subtraction method.

29

FLOWCHART:
START
L
[4051]
H [4052]

HL

DE

L [4050]
H [4051]

BC 0000H

L; AA- E
LA

AH
AA- H- Borrow
HA

BCBC+ 1

NO

Is Carry
flag set ?

YES
A

30

BCBC- 1
HLHL+DE

L[4054]
H[4055]

AC

[4056] A

AB

[4057] A

STOP

31

PROGRAM:
ADDRESS OPCODE LABEL
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
400A
400B
400C
400D
400E
400F
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
401A
401B
401C
401D
401E
401F
4020
4021
OBSERVATION:
INPUT
ADDRESS DATA
4050
4051
4052
4053

START

MNEM
ONICS
LHLD

OPERA
ND
4052

COMMENTS

XCHG
LHLD

4050

Load the second No. in HL reg. pair

& Exchange with DE reg. pair.

LXI

B, 0000H

Load the first No. in stack pointer

through HL reg. pair

Clear BC reg. pair.

LOOP

MOV
SUB
MOV
MOV
SBB
MOV
INX
JNC

A, L
E
L, A
A, H
D
H, A
B
LOOP

Move the content of reg. L to Acc.

Subtract reg. E from that of Acc.
Move the content of Acc to L.
Move the content of reg. H Acc.
Subtract reg. D from that of Acc.
Move the content of Acc to H.
Increment reg. Pair BC
If there is no carry, go to the location
labeled LOOP.

DCX
DAD
SHLD

B
D
4054

Decrement BC reg. pair.

Add content of HL and DE reg. pairs.
Store the content of HL pair in 4054 &
4055.

MOV
STA

A, C
4056

Move the content of reg. C to Acc.

Store the content of Acc. in memory
4056

MOV
STA

A, B
4057

Move the content of reg. B to Acc.

Store the content of Acc. in memory
4057.

HLT

Stop the program execution.

OUTPUT
ADDRESS DATA
4054
4055
4056
4057
32

6(A). LARGEST ELEMENT IN AN ARRAY

AIM:
To find the largest element in an array.
ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next
element).
7. If the accumulator content is smaller, then move the memory content
(largest element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.
RESULT:
Thus the largest number in the given array is found out.

33

FLOW CHART:
START
[HL] [4100H]

[B] 04H
[A] [HL]
[HL [HL] + 1

NO

IS
[A] <
[HL]?

YES

[A] [HL]
[B] [B]-1

IS
[B] =
0?
YES

NO

[4105] [A]
STOP

34

PROGRAM:
ADDRE
SS
4001
4002
4003
4004
4005
4006
4007

OPCO
DE

4008
4009
400A
400B
400C
400D
400E
400F
4010
4011
4012
4013
4014

LABEL

LOOP1

LOOP

MNEM
ONICS
LXI

OPER
AND
H,4100

MVI

B,04

MOV
INX

A,M
H

CMP
JNC

M
LOOP

MOV
DCR
JNZ

A,M
B
LOOP1

STA

4105

HLT

COMMENTS
Initialize HL reg. to
4100H
Initialize B reg with no. of
comparisons(n-1)
Transfer first data to acc.
Increment HL reg. to point
next memory location
Compare M & A
If A is greater than M then go
to loop
Transfer data from M to A reg
Decrement B reg
If B is not Zero go to loop1
Store the result in a memory
location.
Stop the program

OBSERVATION:
INPUT
ADDRESS DATA
4100
4101
4102
4103
4104

OUTPUT
ADDRESS DATA
4105

35

6(B). SMALLEST ELEMENT IN AN ARRAY

AIM:
To find the smallest element in an array.
ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next
element).
7. If the accumulator content is smaller, then move the memory content
(largest element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.
RESULT:
Thus the smallest number in the given array is found out.

36

FLOW CHART:
START
[HL] [4100H]

[B] 04H
[A] [HL]
[HL [HL] + 1

YES

IS
[A] <
[HL]?

NO

[A] [HL]
[B] [B]-1

IS
[B] =
0?
YES

NO

[4105] [A]
STOP

37

PROGRAM:
ADDRE
SS
4001
4002
4003
4004
4005
4006
4007

OPCO
DE

4004
4009
400A
400B
400C
400D
400E
400F
4010
4011
4012
4013
4014

LABEL

LOOP1

LOOP

MNEM
ONICS
LXI

OPER
AND
H,4100

MVI

B,04

MOV
INX

A,M
H

CMP
JC

M
LOOP

MOV
DCR
JNZ

A,M
B
LOOP1

STA

4105

HLT

COMMENTS
Initialize HL reg. to
4100H
Initialize B reg with no. of
comparisons(n-1)
Transfer first data to acc.
Increment HL reg. to point
next memory location
Compare M & A
If A is lesser than M then go to
loop
Transfer data from M to A reg
Decrement B reg
If B is not Zero go to loop1
Store the result in a memory
location.
Stop the program

OBSERVATION:
INPUT
ADDRESS DATA
4100
4101
4102
4103
4104

OUTPUT
ADDRESS DATA
4105

38

7(A).ASCENDING ORDER
AIM:
To sort the given number in the ascending order using 8085 microprocessor.
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is larger than second then I
interchange the number.
3. If the first number is smaller, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
RESULT:
Thus the ascending order program is executed and thus the numbers are arranged
in ascending order.

39

FLOWCHART:

START
[B] 04H
[HL] [4100H]

[C] 04H
[A] [HL]
[HL [HL] + 1

YES

IS
[A] <
[HL]?
NO
[D] [HL]

[HL] [A]

[HL] [HL] - 1

[HL] [D]
[HL] [HL] + 1
[C] [C] 01 H

40

IS
[C] =
0?

NO
YES

[B] [B]-1

IS
[B] =
0?

NO
YES

STOP

PROGRAM:
41

ADDR
E
SS
4000
4001
4002
4003
4004
4005
4006
4007
4004

OPCO
DE

LABEL

LOOP 3

LOOP2

4009
400A
400B
400C
400D
400E
400F
4010
4011
4012
4013
4014
4015
4016
4017
4014
4019
401A

LOOP1

MNEM
ONICS

OPER
AND

MVI

B,04

LXI

H,4100

MVI

C,04

MOV
INX

A,M
H

CMP
JC

M
LOOP1

MOV
MOV
DCX
MOV
INX
DCR
JNZ

D,M
M,A
H
M,D
H
C
LOOP2

Transfer data from M to D reg

Transfer data from acc to M
Decrement HL pair
Transfer data from D to M
Increment HL pair
Decrement C reg
If C is not zero go to loop2

DCR
JNZ

B
LOOP3

Decrement B reg
If B is not Zero go to loop3

HLT

COMMENTS
Initialize B reg with number
of comparisons (n-1)
Initialize HL reg. to
4100H
Initialize C reg with no. of
comparisons(n-1)
Transfer first data to acc.
Increment HL reg. to point
next memory location
Compare M & A
If A is less than M then go to
loop1

Stop the program

OBSERVATION:
INPUT
MEMORY
LOCATION
4100
4101
4102
4103
4104

OUTPUT
DATA

MEMORY
LOCATION
4100
4101
4102
4103
4104

DATA

42

7(B). DESCENDING ORDER

AIM:
To sort the given number in the descending order using 8085 microprocessor.
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is smaller than second then I
interchange the number.
3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
RESULT:
Thus the descending order program is executed and thus the numbers are arranged
in descending order.

43

FLOWCHART:

START
[B] 04H
[HL] [4100H]

[C] 04H
[A] [HL]
[HL [HL] + 1

NO

IS
[A] <
[HL]?
YES
[D] [HL]

[HL] [A]

[HL] [HL] - 1

[HL] [D]
[HL] [HL] + 1
[C] [C] 01 H

44

IS
[C] =
0?

NO
YES

[B] [B]-1

IS
[B] =
0?

NO
YES

STOP

PROGRAM:
45

ADDRE
SS
4000
4001
4002
4003
4004
4005
4006
4007
4004

OPCO
DE

LABEL

MNEM
ONICS
MVI

OPER
AND
B,04

LXI

H,4100

MVI

C,04

MOV
INX

A,M
H

CMP
JNC

M
LOOP1

MOV
MOV
DCX
MOV
INX
DCR
JNZ

D,M
M,A
H
M,D
H
C
LOOP2

Transfer data from M to D reg

Transfer data from acc to M
Decrement HL pair
Transfer data from D to M
Increment HL pair
Decrement C reg
If C is not zero go to loop2

DCR
JNZ

B
LOOP3

Decrement B reg
If B is not Zero go to loop3

LOOP 3

LOOP2

4009
400A
400B
400C
400D
400E
400F
4010
4011
4012
4013
4014
4015
4016
4017
4014
4019
401A

LOOP1

HLT

COMMENTS
Initialize B reg with number
of comparisons (n-1)
Initialize HL reg. to
4100H
Initialize C reg with no. of
comparisons(n-1)
Transfer first data to acc.
Increment HL reg. to point
next memory location
Compare M & A
If A is greater than M then go
to loop1

Stop the program

OBSERVATION:
INPUT
MEMORY
LOCATION
4100
4101
4102
4103
4104

OUTPUT
DATA

MEMORY
LOCATION
4100
4101
4102
4103
4104

DATA

8(A) BCD ADDITION

AIM:
46

To add two 8 bit BCD numbers stored at consecutive memory locations.

ALGORITHM:
1.
2.
3.
4.
5.

Initialize memory pointer to data location.

Get the first number from memory in accumulator.
Get the second number and add it to the accumulator
Adjust the accumulator value to the proper BCD value using DAA instruction.
Store the answer at another memory location.

RESULT:
Thus the 8 bit BCD numbers stored at 4500 &4501 are added and the result stored at
4502 & 4503.

47

FLOW CHART:
START

[C]

00H

[HL]

4500H

[A]

[M]

[HL][HL]+1

[A][A]+[M]
Decimal Adjust Accumulator
NO
Is there aYES
Carry ?

[C][C]+1

[HL][HL]+1

[M]

[A]

[HL][HL]+1

[M]

[C]

STOP

48

PROGRAM:
ADDRESS OPCODE LABEL
4100
START
4103
4102
4103
4104
4105

MNEMONICS OPERAND
MVI
C, 00

COMMENT
Clear C reg.

LXI

H, 4500

Initialize HL reg. to
4500

MOV

A, M

4106

INX

4107

ADD

4108

DAA

4109
410A
410B

JNC

L1

Transfer first data to

accumulator
Increment HL reg. to
point next memory
Location.
Add first number to
acc. Content.
Decimal adjust
accumulator
Jump to location if
result does not yield
carry.

410C
410D

INR
INX

C
H

410E

MOV

M, A

410F

INX

4110
4111

MOV
HLT

M, C

L1

Increment C reg.
Increment HL reg. to
point next memory
Location.
Transfer the result from
acc. to memory.
Increment HL reg. to
point next memory
Location.
Move carry to memory
Stop the program

OBSERVATION:
INPUT
4500
4501

OUTPUT
4502
4503

8(B). BCD SUBTRACTION

49

AIM:
To Subtract two 8 bit BCD numbers stored at consecutive memory locations.
ALGORITHM:
1.
2.
3.
4.
5.

Load the minuend and subtrahend in two registers.

Initialize Borrow register to 0.
Take the 100s complement of the subtrahend.
Add the result with the minuend which yields the result.
Adjust the accumulator value to the proper BCD value using DAA instruction.
If there is a carry ignore it.
6. If there is no carry, increment the carry register by 1
7. Store the content of the accumulator
START (result)and borrow register in the
specified memory location
[D] 00H
HL
4500
M &4501 are subtracted and the result stored at
Thus the 8 bit BCD numbers storedBat 4500
4502 & 4503.

RESULT:

HL HL+ 1
C M
A 99
[A] [A] [C]
[A] [A]+1
[A][A]+[B]
DAA

Is there a
Carry ?

[D][D]+1

[HL][HL]+1

FLOW CHART:
[4502] A
[4503] D

50
STOP

YES

NO

PROGRAM:

51

ADDRESS OPCODE LABEL

4100
START
4101
4102
4103
4104
4105

MNEMONICS OPERAND COMMENT

MVI
D, 00
Clear D reg.
LXI

H, 4500

Initialize HL reg. to
4500

MOV

B, M

4106

INX

4107

MOV

C, M

4108
4109
410A

MVI

A, 99

SUB

410B
410C
410D

INR
ADD
DAA

A
B

410E

JC

LOOP

Transfer first data to

accumulator
Increment HL reg. to
point next mem.
Location.
Move second no. to B
reg.
Move 99 to the
Accumulator
Subtract [C] from acc.
Content.
Increment A register
Add [B] with [A]
Adjust Accumulator
value for Decimal digits
Jump on carry to loop

INR
INX

D
H

4113

MOV

M,A

4114

INX

4115

MOV

M, D

4116

HLT

410F
4110
4111
4112

LOOP

Increment D reg.
Increment HL register
pair
Move the Acc.content to
the memory location
Increment HL reg. to
point next mem.
Location.
Transfer D register
content to memory.
Stop the program

OBSERVATION:
INPUT
4500
4501

OUTPUT
4502
4503

9(A). To Find the Sum of Given Series of Number Without Carry

52

Aim:
To write an assembly language program to find the sum of series of data without
carry.
Apparatus Required:
Microprocessor 8085 kit, power supply.
Mnemonics:
XRA A
LXI H, A001
MOV C, M
INX H
MOV A, M
DCR C
INX H
ADD M
DCR C
JNZ 8008
STA C001
RST 1

Result:
Thus an assembly language for sum of given numbers without carry is written and
executed.

9(B). To Find the Sum of Given Series of Number With Carry

53

Date:

Aim:
To write an assembly language program to find the sum of series of data with
carry.
Apparatus Required:
Microprocessor 8085 kit, power supply.
Mnemonics:
MVI C, 00
XRA A
LXI H, A001
MOV B, M
INX H
MOV A, M
DCR B
INX H
ADD M
JNC 8010
INR C
DCR B
JNZ 800A
STA C001
MOV A, C
STA C002
RST 1

Result:
Thus an assembly language for sum of given numbers with carry is written and
executed.

54

55

56

57

58

59

CYCLE II
Ex. No. 10.

Study of Multiplexer IC 74151

Date:

Aim:
To study 4:1 multiplexer operation using IC 74151components.

Study:
MULTIPLEXERS
A multiplexer performs the function of selecting the input on any one of 'n' input
lines and feeding this input to one output line. Multiplexers are used as one method of
reducing the number of integrated circuit packages required by a particular circuit design.
This in turn reduces the cost of the system.
Assume that we have four lines, C0, C1, C2 and C3, which are to be multiplexed
on a single line, Output (f). The four input lines are also known as the Data Inputs. Since
there are four inputs, we will need two additional inputs to the multiplexer, known as the
Select Inputs, to select which of the C inputs is to appear at the output. Call these select
lines
A
and
B.
The gate implementation of a 4-line to 1-line multiplexer is shown below:

60

The circuit symbol for the above multiplexer is:

Result:
Thus the truth table for multiplexer IC 74151 is studied

61

Study of Demultiplexer IC 74154

Ex. No. 11.

Date:

Aim:
To study 1:8 Demultiplexer operation using IC 74154 components.

Study:
DEMULTIPLEXERS
A Demultiplexer (DMUX) is a device which essentially performs the opposite
operation to the MUX. That is, it functions as an electronic switch (/data distributor) to
route an incoming data signal to one of several outputs. Figure 2-15 shows the logic
symbol for the 1-line-to-4-line Demultiplexer circuit and Table 2-15 list the associated
Truth table. The corresponding logic circuit implementation is then shown in Figure 2-16.

Figure 2-15 Logic symbol for 1-line-to-4-line Demultiplexer

Address

Outputs

Data
S1

S0

Y0

Y1

Y2

Y3

62

Table 2 -15 Demultiplexer Function Tables

Figure 2-16 1-line-to-4-line Demultiplexer

Result:
Thus the truth table for Demultiplexer IC 74154 is studied

63

Study of Encoder

Ex. No. 13.

Date:
Aim:

To study the encoder function using IC 74147.

Study:
An encoder is a device used to change a signal (such as a bit stream) or data into
a code. The code may serve any of a number of purposes such as compressing
information for transmission or storage, encrypting or adding redundancies to the input
code, or translating from one code to another. This is usually done by means of a
programmed algorithm, especially if any part is digital, while most analog encoding is
done with analog circuitry.
Single bit 4 to 2 Encoder
A single bit 4 to 2 encoder takes in 4 bits and outputs 2 bits. It is assumed that there are
only 4 types of input signals these are : 0001, 0010, 0100, 1000.
I3 I2 I1 I0 O1 O0
0 0 0 1 0

0 0 1 0 0

0 1 0 0 1

1 0 0 0 1

4 to 2 encoder
Priority encoder
A priority encoder prioritizes more significant bits in the data stream, and once it finds a
high signal will ignore all other bits. An example of a single bit 4 to 2 encoder is shown.
I3 I2 I1 I0 O1 O0
0 0 0 d 0

0 0 1 d 0

0 1 d d 1

1 d d d 1

64

4 to 2 priority encoder
Ex. No. 14.

Study of Decoder

Date:
Aim:
To study the decoder function using IC 74147.
Study:
DECODER
A decoder is a device which does the reverse of an encoder, undoing the encoding
so that the original information can be retrieved. The same method used to encode is
usually just reversed in order to decode.
In digital electronics this would mean that a decoder is a multiple-input, multipleoutput logic circuit that converts coded inputs into coded outputs, where the input and
output codes are different. e.g. n-to-2n, BCD decoders.
Enable inputs must be on for the decoder to function, otherwise its outputs assume
a single "disabled" output code word. Decoding is necessary in applications such as data
multiplexing, 7 segment display and memory address decoding.
The simplest decoder circuit would be an AND gate because the output of an
AND gate is "High" (1) only when all its inputs are "High".
Example: A 2-to-4 Line Single Bit Decoder
A slightly more complex decoder would be the n-to-2 n type binary decoders. These
type of decoders are combinational circuits that convert binary information from 'n' coded
inputs to a maximum of 2n unique outputs. We say a maximum of 2n outputs because in
case the 'n' bit coded information has unused bit combinations, the decoder may have less
than 2n outputs. We can have 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder. We can
form a 3-to-8 decoder from two 2-to-4 decoders (with enable signals).
A 2-to-4 line decoder/demultiplexer is shown below.
As a decoder, this circuit takes an n-bit binary number and produces an output on
one of 2n output lines. It is therefore commonly defined by the number of addressing
input lines and the number of data output lines. Typical decoder/demultiplexer ICs
might contain two 2-to-4 line circuits, a 3-to-8 line circuit, or a 4-to-16 line circuit.
65

One exception to the binary nature of this circuit is the 4-to-10 line
decoder/demultiplexer, which is intended to convert a BCD (Binary Coded Decimal)
input to an output in the 0-9 range.

If you use this circuit as a demultiplexer, you may want to add data latches
at the outputs to retain each signal while the others are being transmitted.

Result:
Thus the Encoder is studied using IC 74147

66

CYCLE III

Study MIL STD 1553B data bus

Aim:
To study architecture, transfer modes and coupling methods of MIL STD 1553B
data bus.

67

68

69

70

71

72

73