CDA 3103
Fall 2015
Final Exam Practice
Problem 5 Refer to the following byte-addressable memory consisting of 2 modules, each of which
contains 4 locations.
1) (1 points) How many address lines are used by this memory
3
.
2) (2 points) Fill in each location its memory address assuming the memory is in low-order inter-leaving.
Module 0
Module 1
000
001
010
011
100
101
110
111
3) (2 points) Fill in each location its memory address assuming the memory is in high-order inter-leaving.
Module 0
Module 1
000
100
001
101
010
110
011
111
Problem 7 Execute the above MARINE program.
a) List the hexadecimal code for the above program (hand assemble it).
b) Draw the symbol table.
c) Fill in the blanks with correct values for registers PC and AC, and the contents in memory
locations X, and Y, after each instruction is executed starting from the first instruction.
Answer
a)
CDA 3103
b)
Fall 2015
Symbol
If
Then
Else
Endif
X
Y
c)
PC
0x100
0x101
0x102
0x103
0x108
0x109
0x10A
0x10B
0x10C
Final Exam Practice
Location
100
104
108
10B
10C
10D
AC
-0x000C
0xFFF8
0xFFF8
0xFFF8
0x0014
0x0008
0x0008
0x0008
M[X]
0x000C
0x000C
0x000C
0x000C
0x000C
0x000C
0x000C
0x000C
0x000C
Problem 8
2
M[Y]
0x0014
0x0014
0x0014
0x0014
0x0014
0x0014
0x0014
0x0008
0x0008
CDA 3103
Fall 2015
Final Exam Practice
Write a MARIE program using a loop that multiplies two positive numbers by using repeated
addition. For example, to multiple 3 x 6, the program would add 3 six times, or 3+3+3+3+3+3.
Problem 9 (8 Points) Determine the required control signal sequence P 5-P0, Cr, A1, A0, MR, MW
and Timing signal T3 through T7 if required for MARIEs ADD X instruction.
T3
1
0
0
T4
0
1
0
T5
0
0
1
T6
0
0
0
T7
0
0
0
P5
0
0
1
P4
0
1
0
P3
1
1
0
P2
1
0
0
Problem 10 Short Answers
1.
2.
P1
1
0
0
P0
1
0
0
MR
0
1
0
MW
0
0
0
A1
0
0
0
A0
0
0
1
Cr
0
0
1
(2 points) Assume a computer has 32-bit integers. Show how the value 0xFEDC1234 would be stored
sequentially in memory, starting at address 0x100, on both a big endian machine and a little endian
machine, assuming that each address holds one byte.
Address
Big Endian
Little Endian
0x100
0xFE
0x34
0x101
0xDC
0x12
0x102
0x12
0xDC
0x103
0x34
0xFE
(2 points) Suppose we have the instruction LOAD 500. Register R1 contains the value 0x200 and
assuming R1 is implied in the indexed addressing mode. Given memory as follows:
Memory
CDA 3103
0x100
0x400
0x500
0x600
0x700
Fall 2015
Final Exam Practice
0x600
0x300
0x100
0x500
0x800
What would be loaded into the AC if
a) the addressing mode for the operating is immediate? (
b) the addressing mode for the operating is direct? (
c) the addressing mode for the operating is indirect? (
d) the addressing mode for the operating is indexed? (
0x500
0x100
0x600
0x800
)
)
)
3.
(2 points) A nonpipelined system takes 400ns to process a task. The same task can be processed in a
5-segment pipeline with a clock cycle of 80ns.
a) Determine the speedup ratio of the pipeline for 100 tasks.
100 400
500
=
= 4.81
(100 + 5 1) 80
104
b) What is the maximum speedup that could be achieved with the pipeline unit over the nonpipelined
unit? (
5
)
4.
(2 points)
a) Convert W X + W ( U V + Z) from infix to reverse Polish (postfix) notation (
WX WUV Z+ +
)
b) Convert W X Y Z + from postfix notion to infix notation. ( W (X + Y Z)
)
(2 points) Suppose the cache access time is 15ns, main memory access time is 220ns, and the cache
hit rate is 80%. Assuming parallel (overlapped) access, what is the average access time for the
processor to access an item? (
80% 15 ns + (1 80%) 220
)
5.
Problem 11
Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes
each, and 4 page frames. Assuming the following page table, answer the questions below:
CDA 3103
Fall 2015
Final Exam Practice
a)
b)
c)
How many bits are in a physical address? (
9
)
How many bits are in a virtual address? (
8
)
What physical address corresponds to the following virtual addresses (if the address causes a page
fault, simply indicate this is the case)?
i.
0x0
ii.
0x44
iii.
0xC2
iv.
0x80
Answer:
Problem 12
A direct-mapped cache consists of eight blocks. A byte-addressable main memory contains 4K blocks of
eight bytes each. Access time for the cache is 22 ns and the time required to fil a cache slot from main
memory is 300 ns (this time will allow us to determine the block is missing and bring it into cache). Assume
a request is always started in parallel to both cache and to main memory (so if it is not found in cache, we
do not have to add this cache search time to the memory access). If a block is missing from cache, the entire
block is brought into the cache and the access is restarted. Initially, the cache is empty.
a) Show the main memory address format that allows us to map addresses from main memory to cache. Be
sure to include the fields as well as their sizes.
b) Compute the hit ratio for a program that loops 4 times from locations 0x0 to 0x43 in memory.
c) Compute the effective access time for this program.
5
CDA 3103
Fall 2015
MARIEs Full Instruction Set
Final Exam Practice
CDA 3103
Fall 2015
Final Exam Practice
