Motorola Ebts Manual
Motorola Ebts Manual
The instruction and service manual for this base radio are not published at this time. However, draft copy of the
manual is available and has been included as part of the filing package in the form of an electronic pdf document.
Upon request, published and/or printed manuals will be sent to the commission and/or telecommunication
certification body (TCB) as soon as they become available. All of the descriptions and schematics included this
filing package are up to date.
EXHIBIT 8
There is no field tune-up procedure. All adjustments are software controlled and are pre-set at the factory. Certain
station operating parameters can be changed via man-machine interface (MMI) commands, within predetermined
limits. Examples include transmit / receiver operating frequencies and power level.
EXHIBIT 9
VOLUME 2 OF 3
BASE RADIOS
68P81099E10-D
ECCN 5E992
SOFTWARE NOTICE/WARRANTY
Laws in the United States and other countries preserve for Motorola certain exclusive rights for copyrighted Motorola software such as the exclusive rights to reproduce in copies
and distribute copies of such Motorola software. Motorola software may be used in only the Product in which the software was originally embodied and such software in such
Product may not be replaced, copied, distributed, modified in any way, or used to produce any derivative thereof. No other use including without limitation alteration, modification,
reproduction, distribution, or reverse engineering of such Motorola software or exercise of rights in such Motorola software is permitted. No license is granted by implication,
estoppel or otherwise under Motorola patent rights or copyrights.
This warranty extends only to individual products: batteries are excluded, but carry their own separate limited warranty.
In order to obtain performance of this warranty, purchaser must contact its Motorola salesperson or Motorola at the address first above shown, attention Quality Assurance
Department.
This warranty applies only within the fifty (50) United States and the District of Columbia.
1 Contents
Contents.......................................................................................................................... i
List of Figures .............................................................................................................. iv
List of Tables ................................................................................................................ vi
Foreword................................................................................................................................. ix
General Safety Information .................................................................................................... xi
800/900/1500 MHz
Base Radio Overview............................................................................................... 1-1
Single Carrier Base Radio Overview.................................................................................... 1-4
QUAD Channel Base Radio Overview ................................................................................ 1-9
Contents
Transmitter & Receiver Verification Procedures for Beta- Release Equipment 12-1
Acronyms .....................................................................................................................13
Index .................................................................................................................... Index-1
ii
68P81099E10-D-C 4/1/2000
Contents
iii
68P81099E10-D 4/1/2000
Contents
List of Figures
List of Figures
Figure:1-1
Figure:1-2
Figure:1-3
Figure:1-4
Figure:1-5
800 MHz QUAD Channel Base Radio Functional Block Diagram ............................................ 1-17
Figure:2-1
Figure:2-2
Figure:2-3
Figure:2-4
Figure:2-5
Figure:2-6
Base Radio Controller, version CLN1469 (with cover removed) ................................................. 2-2
Base Radio Controller, version TLN3425 (with cover removed).................................................. 2-2
BR Controller (Front View)........................................................................................................... 2-3
Base Radio Controller, version CLN1469 (with cover removed) ............................................... 2-12
BR Controller (Front View)......................................................................................................... 2-13
800/900 MHz Base Radio Controller Functional Block Diagram
(Sheet 1 of 2) ................................................................................................................................2-23
800/900 MHz Base Radio Controller Functional Block Diagram
(Sheet 2 of 2) ................................................................................................................................2-24
1500 MHz Base Radio Controller Functional Block Diagram
(Sheet 1 of 2) ................................................................................................................................2-25
1500 MHz Base Radio Controller Functional Block Diagram (Sheet 2 of 2) ............................. 2-26
QUAD CHANNEL Base Radio Controller Functional Block Diagram
(Sheet 1 of 2) ................................................................................................................................2-27
QUAD CHANNEL Base Radio Controller Functional Block Diagram
(Sheet 2 of 2) ................................................................................................................................2-28
800/900 MHz Exciter (with cover removed) ................................................................................. 5-2
1500 MHz Exciter, version TLN3428 (with top removed) ........................................................... 5-3
800 MHz QUAD Channel Exciter (with cover removed) ............................................................. 5-7
Exciter Functional Block Diagram .............................................................................................. 3-11
Exciter Functional Block Diagram .............................................................................................. 3-12
Exciter Functional Block Diagram .............................................................................................. 3-13
Exciter Functional Block Diagram .............................................................................................. 3-14
70W, 800 MHz PA TLN3335 (with cover removed) ................................................................. 6-2
60W, 900 MHz PA CLN1355 (with cover removed)................................................................. 6-3
40W, 1500 PA (with cover removed) ............................................................................................ 6-4
QUAD Channel PA (with cover removed).................................................................................... 6-5
TLF2020 (TTF1580B) 40 W, 800 MHz Power Amplifier Functional Block Diagram
(Sheet 1 of 1)................................................................................................................................ 4-13
TLN3335 (CTF1040) 70 W, 800 MHz Power Amplifier Functional Block Diagram
(Sheet 1 of 1)................................................................................................................................ 4-14
60W, 900 MHz Power Amplifier Functional Block Diagram
(Sheet 1 of 1)................................................................................................................................ 4-15
Figure:2-6
Figure:2-7
Figure:2-8
Figure:2-7
Figure:2-7
Figure:3-1
Figure:3-2
Figure:3-3
Figure:3-4
Figure:3-5
Figure:3-6
Figure:3-7
Figure:4-1
Figure:4-2
Figure:4-3
Figure:4-4
Figure:4-5
Figure:4-6
Figure:4-7
iv
68P81099E10-D 1/15/2000
Contents
List of Figures
Figure:4-8
Figure:4-9
QUAD Channel Power Amplifier Functional Block Diagram (Sheet 1 of 1) ............................. 6-17
Figure:5-1
Figure:5-2
Figure:5-3
Figure:5-3
Figure:5-3
Figure:5-3
Figure:6-1
Figure:6-2
Figure:6-2
Figure:7-1
Figure:7-2
Figure:7-3
Figure:7-4
Figure:7-5
Figure:7-6
Figure:7-7
Figure:8-1
Figure:8-2
Figure:8-3
Figure:8-4
Figure:8-5
Figure:8-6
Figure:8-7
Figure:9-1
Figure:9-2
Figure:9-3
Figure:9-4
Figure:10-1
6 8 P 8 1 0 9 9E10- D 1/15/2000
Contents
List of Tables
List of Tables
vi
Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-7
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 3-1
Table 3-2
Table 4-1
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 6-1
Table 6-2
Table 6-3
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 8-1
Table 8-2
68P81099E10-D 4/1/2000
Contents
List of Tables
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 8-24
Table 9-1
Table 9-2
Table 9-3
Table 9-9
Table 9-10
Table 9-11
Table 9-12
Table 9-13
Table 9-14
Table 9-15
Table 9-16
Table 9-17
6 8 P 8 1 0 9 9E10- D 4/1/2000
vii
Contents
viii
68P81099E10-D 4/1/2000
Foreword
About This Manual
Volume 2 of the Enhanced Base Transceiver System (EBTS) manual, Base Radios,
provides the experienced service technician with an overview of the EBTS
operation and functions, and contains information regarding the 800 MHz,
900 MHz, or 1500 MHz base radios.
The EBTS System has three major components:
Target Audience
The target audience of this document includes eld service technicians
responsible for installing, maintaining, and troubleshooting the EBTS.
In keeping with Motorolas eld replaceable unit (FRU) philosophy, this manual
provides sufcient functional information to the FRU level. Please refer to the
appropriate section of this manual for removal and replacement instructions.
6 8 P 8 1 0 9 9E10-D 4/ 1/ 2000
ix
Foreword
Maintenance Philosophy
The EBTS has been designed using a Field Replaceable Unit (FRU) maintenance
concept. To minimize system down time, faulty FRUs may be quickly and easily
replaced with replacement FRUs. This helps to restore normal system operation
quickly.
Due to the high percentage of surface mount components and multi-layer circuit
boards, eld repair is discouraged. Faulty or suspectFRUs should be returned to
the Motorola Customer Support Center for further troubleshooting and repair.
Each FRU has a bar code label attached to its front panel. This label identies a
sequential serial number for the FRU. Log this number whenever contacting the
Motorola Customer Support Center. For complete information on ordering
replacement FRUs, or instructions on how to return faulty FRUs for repair,
contact:
Nippon Motorola LTD.
Tokyo Service Center
044-366-8860
OR
6 8 P8 1 0 9 9 E1 0 - D 4 / 1 / 2 0 0 0
DO NOT operate the transmitter of any radio unless all RF connectors are
secure and any open connectors are properly terminated.
WARNING
6 8 P 8 1 0 9 9E10-D 4/ 1/ 2000
xi
xii
6 8 P8 1 0 9 9 E1 0 - D 4 / 1 / 2 0 0 0
1 800/900/1500 MHz
Base Radio Overview
Overview
This section provides technical information for the 800/900/1500 MHz Base
Radio (BR). Table 1-1 describes covered topics.
Table 1-1
Chapter Topics
Page
Description
1-3
1-8
2-1
Exciter
3-1
Power Amplier
4-1
DC Power Supply
5-21
AC Power Supply
6-33
Chapter
1-1
Table 1-1
Chapter Topics
Page
Chapter
Description
Receiver
7-39
8-1
8-5
8-9
8-35
9-1
9-5
9-10
9-22
Acronyms
A-39
NOTE
The rst section covers the 800 MHz, 900 MHz and
1500 MHz versions of the Base Radio (BR).
Generalinformation for all versions appears here. The
text notes information specic to the 800 MHz , 900
MHz or 1500 MHz BR.
NOTE
For QUAD Channel BR use, all Single Carrier BR
modules have undergone a redesign process. Single
Carrier BR modules are incompatible with the QUAD
Channel BR. QUAD Channel BR modules are
incompatible with the Single Carrier BR.
Do not try to insert QUAD Channel BR modules into a
Single Carrier BR or Single Carrier BR modules into a
QUAD Channel BR.
1-2
68P81095E02- D 11/9/2000
Exciter
Power Amplier
Receiver
The modular design of the BR also offers increased shielding and provides easy
handling. All FRUs connect to the backplane through blindmate connectors.
Figure 1-1 shows the front view of the BR.
3X RECEIVER
INSERT ONLY IN SLOT RX2 WITH BACKPLANE 0183625X
POWER SUPPLY
EXCITER
STATUS
B R P S E X P A C T L R 1 R 2 RESET
R3
CONTROL
POWER AMPLIFIER
EBTS282
101497JNM
Figure:1-1
6 8 P 8 1 0 9 5 E02- D
11/9/2000
1-3
Performance Specifications
General Specifications
Table 1-2 lists general specications for the BR.
Table 1-2
BR General Specifications
Specification
Value or Range
Dimensions:
Height
Width
Depth
Weight
Operating Temperature
32 to 104 F (0 to 40 C)
Storage Temperature
Rx Frequency Range:
800 MHz iDEN
Tx Frequency Range:
800 MHz iDEN
Tx Rx Spacing:
800 MHz iDEN
45 MHz
39 MHz
48 MHz
Channel Spacing
25 kHz
Frequency Generation
Synthesized
Digital Modulation
M-16QAM
Vdc
Diversity Branches
1-4
Up to 3
68P81095E02- D 11/9/200 0
Transmit Specifications
Table 1-3 lists transmit specications for the BR.
Table 1-3
Transmit Specifications
Specification
Value or Range
2 - 40 W
(800 MHz) 70 W PA
4 - 70 W
(900 MHz) 60 W PA
5 - 60 W
(1500 MHz) 40 W PA
10 - 40 W
0.01%
Occupied Bandwidth
18.5 kHz
Frequency Stability *
1.5 ppm
RF Input Impedance
50 (nom.)
ABZ89FC5772
(800 MHz) 70 W PA
ABZ89FC5763
(900 MHz) 60 W PA
ABZ89FC5791
Receive Specifications
Table 1-4 lists the receive specications.
Table 1-4
Receive Specifications
Specification
Value or Range
Static Sensitivity :
800 MHz BR
900 MHz BR
1500 MHz BR
-80 dBm
IF Frequencies
1st IF (All bands):
2nd IF:
800/900 MHz
1500 MHz
Frequency Stability *
1.5 ppm
RF Input Impedance
50 (nom.)
ABZ89FR5762
900 MHz BR
ABZ89FR5792
6 8 P 8 1 0 9 5 E02- D
11/9/2000
1-5
NOTE
FCC Compliance Notice: The Base Radio (BR) is FCC
Compliant only when used in conjunction with
Motorola supplied RF Distribution Systems. Motorola
does not recommend that this BR be used without a
Motorola approved RF Distribution System. It is the
customers responsibility to le for FCC approval if
the BR is used with a non-Motorola supplied RF
Distribution System.
Theory of Operation
The BR operates in conjunction with other site controllers and equipment that are
properly terminated. The following description assumes such a conguration.
Figures 1-3 and 1-4 show an overall block diagram of the BR.
Power is applied to the AC Power or DC Power inputs located on the BR
backplane. The DC Power input is connected if -48 Vdc or batteries are used in
the site. The AC Power input is used when 120/240 Vac service is used as a
power source within the site.
Power is applied to the BR by setting the Power Supply power switch to the on
position. Upon power-up, the BR performs self-diagnostic tests to ensure the
integrity of the unit. These tests are primarily conned to the BRC and include
memory and Ethernet verication routines.
After the self-diagnostic tests are complete, the BR reports any alarm conditions
present on any of its modules to the site controller via Ethernet. Alarm conditions
may also be veried locally using service computer and the STATUS port located
on the front of the BRC.
The software resident in EPROM on the BRC registers the BR with the site
controller via Ethernet. Once registered, the BR software is downloaded via
Ethernet and is executed from RAM. Operating parameters for the BR are
included in this download. This software allows the BR to perform call
processing functions.
The BR operates in a TDMA (Time Division Multiple Access) mode. This mode,
combined with voice compression techniques, provides an increased channel
capacity ratio of as much as 6 to 1. Both the receive and transmit signals of the BR
are divided into 6 individual time slots. Each receive slot has a corresponding
transmit slot; this pair of slots comprises a logical RF channel.
The BR uses diversity reception for increased coverage area and improved
quality. The Receiver module within the BR contains up to three receivers. Two
Receivers are used with two-branch diversity sites, and three Receivers are used
with three-branch diversity sites.
1-6
68P81095E02- D 11/9/200 0
All Receivers within a given BR are programmed to the same receive frequency.
The signals from each receiver are fed to the BRC where a diversity combining
algorithm is performed on the signals. The resultant signal is processed for error
correction and then sent to the site controller via Ethernet with the appropriate
control information regarding its destination.
The transmit section of the BR is comprised of two separate FRUs, the Exciter and
Power Amplier (PA). Several PA FRUs are available, covering different
applications and power levels; these are individually discussed as applicable in
later subsections.
The Exciter processes the information to transmit from the BRC in the proper
modulation format. This low level signal is sent to the PA where it is amplied to
the desired output power level. The PA is a continuous keyed linear amplier. A
power control routine monitors the output power of the BR and adjusts it as
necessary to maintain the proper output level.
6 8 P 8 1 0 9 5 E02- D
11/9/2000
1-7
The modular design of the QUAD Channel BR also offers increased shielding and
provides easy handling. All FRUs connect to the backplane through blindmate
connectors. Figure 1-2 shows the front view of the BR.
Figure:1-2
1-8
68P81095E02- D 11/9/200 0
Performance Specifications
General Specifications
Table 1-5 lists general specications for the BR.
QUAD Channel BR General Specifications
Table 1-5
Value or Range
Specification
Dimensions:
Height
Width
Depth
Weight
Operating Temperature
32 to 104 F (0 to 40 C)
Storage Temperature
Rx Frequency Range:
800 MHz iDEN
Tx Frequency Range:
800 MHz iDEN
Tx Rx Spacing:
800 MHz iDEN
Carrier Spacing
Carrier
Capacitya
45 MHz
25 kHz
1, 2, 3 or 4
Frequency Generation
Synthesized
Digital Modulation
6 8 P 8 1 0 9 5 E02- D
11/9/2000
1-9
Transmit Specifications
Table 1-6 lists the BR transmit specications.
Table 1-6
Transmit Specifications
Specification
Value or Range
Total PA
Per Carrier
5 - 52 W
5 - 52 W
5 - 52 W
2.5 - 26 W
5 - 48 W
1.7 - 16 W
5 - 42 W
0.01%
Occupied Bandwidth
18.5 kHz
Frequency Stability *
1.5 ppm
RF Input Impedance
50 (nom.)
ABZ89FC5794
* Transmit frequency stability locks to an external site refernce, which controls ultimate frequency stability to a
level of 50 ppb.
Receive Specifications
Table 1-7 lists the receive specications.
Table 1-7
Receive Specifications
Specification
Value or Range
Static Sensitivity :
800 MHz BR
BER Floor (BER = 0.01%)
IF Frequencies
1st IF (All bands):
2nd IF:
Frequency Stability *
1.5 ppm
RF Input Impedance
50 (nom.)
ABZ89FR5793
1-10
68P81095E02- D 11/9/200 0
NOTE
FCC Compliance Notice: The Base Radio (BR) is FCC
Compliant only when used with Motorola-supplied
RF Distribution Systems. Motorola does not
recommend using this BR without a Motorolaapproved RF Distribution System. If customer uses
the BR with a non-Motorola supplied RF Distribution
System, the customer is responsible for ling for FCC
approval.
Theory of Operation
The QUAD Channel BR operates together with other site controllers and
equipment that are properly terminated. The following description assumes such
a conguration. Figures 1-5 show an overall block diagram of the QUAD Channel
BR.
Power is applied to the DC Power inputs located on the QUAD Channel BR
backplane. The DC Power input is connected if -48 Vdc or batteries are used in the
site.
Power is applied to the BR by setting the Power Supply power switch to the on
position. Upon power-up, the QUAD Channel BR performs self-diagnostic tests
to ensure the integrity of the unit. These tests, which include memory and
Ethernet verication routines, primarily examine the EX / CN TL.
After completing self-diagnostic tests, the QUAD Channel BR reports alarm
conditions on any of its modules to the site controller via Ethernet. Alarm
conditions may also be veried locally. Local verication involves using the
service computer and the STATUS port located on the front of the QUAD Channel
EX / CNTL.
The software resident in FLASH on the EX / CNTL registers the BR with the site
controller via Ethernet. After BR registration on initial power-up, the BR software
downloads via Ethernet and executes from RAM. The download includes
operating parameters for the QUAD Channel BR. These parameters allow the
QUAD Channel BR to perform call processing functions.
After software downloads to the BR via Ethernet, FLASH memory stores the
software object. Upon future power-ups, the software object in FLASH loads into
RAM for execution.
The BR operates in a TDMA (Time Division Multiple Access) mode. This mode,
combined with voice compression techniques, increases channel capacity by a
ratio of as much as six to one. TDMA divides both the receive and transmit
signals of the BR into six individual time slots. Each receive slot has a
corresponding transmit slot. This pair of slots comprises a logical RF channel.
6 8 P 8 1 0 9 5 E02- D
11/9/2000
1-11
The BR uses diversity reception for increased coverage area and improved
quality. The Receiver modules within the QUAD Channel BR contain three
receiver paths. Two-branch diversity sites use two Receiver paths, and
three-branch diversity sites use three Receiver paths.
All Receiver paths within a given Receiver module are programmed to the same
receive frequency. Signals from each receiver arrive at the EX / CNTL module.
This module performs a diversity combining algorithm on the signals. The
resultant signal undergoes an error-correction process. Then, via Ethernet, the site
controller acquires the signal, along with control information about signal
destination.
Two separate FRUs comprise the transmit section of the QUAD Channel BR.
These are the Exciter portion of the EX / CNTL and the Power Amplier (PA).
The Exciter processes commands from the CNTL, assuring transmission in the
proper modulation format. Then the low-level signal enters the PA. The PA
amplies this signal to the desired output power level. The PA is a continuously
keyed linear amplier. A power control routine monitors the output power of the
BR. The routine adjusts the power as necessary to maintain the proper output
level.
1-12
68P81095E02- D 11/9/2000
6 8 P 8 1 0 9 5 E02- D
11/9/2000
1-13
1-14
68P81095E02- D 11/9/200 0
3X RECEIVER MODULE
MIXER
FROM
RFDS
(RECEIVER
ANTENNA)
#1
RF IN
FROM
RFDS
(RECEIVER
ANTENNA)
#2
RF IN
FROM
RFDS
(RECEIVER
ANTENNA)
#3
RF IN
DSP BUS
LPF/
PRESELECT/
PREAMP/
IMAGE FILTER
BAND
PASS
FILTER
IF
AMP
BAND
PASS
FILTER
DIGITAL
ATTEN.
CIRCUIT
CUSTOM
RECEIVER
IC
BAND
PASS
FILTER
IF
AMP
BAND
PASS
FILTER
DIGITAL
ATTEN.
CIRCUIT
CUSTOM
RECEIVER
IC
IF
AMP
BAND
PASS
FILTER
DIGITAL
ATTEN.
CIRCUIT
CUSTOM
RECEIVER
IC
MIXER
DSP BUS
LPF/
PRESELECT/
PREAMP/
IMAGE FILTER
MIXER
BAND
PASS
FILTER
AGC
ADDRESS DECODE,
MEMORY,
A/D CONVERTER
267 KHZ
START-UP
INVERTER
CIRCUITRY
133 KHZ
SERIAL BUS
3-WAY
SPLITTER
SPI BUS
+14.2 V
INVERTER
CIRCUITRY
2.1 MHZ
+5 V
INVERTER
CIRCUITRY
SPI BUS
5 MHZ
EXTERNAL
REFERENCE
EXTERNAL
DC INPUT
41 - 72 VDC
133 KHZ
CLOCK
GENERATOR
CIRCUITRY
VCO/
SYNTH
INPUT FILTER
BOARD
MAIN INVERTER
CIRCUITRY
DSP BUS
LPF/
PRESELECT/
PREAMP/
IMAGE FILTER
+14.2 VDC
TO BACKPLANE
+5 VDC
TO BACKPLANE
+28 VDC
TO BACKPLANE
5 MHZ
16.8 MHZ
ETHERNET
INTERFACE
HOST
GLUE
ASIC
TRANSMIT
DSP
TO/FROM
RS-232 PORT
(ON BACKPLANE)
HOST
P
NON-VOLATILE
MEMORY
(EEPROM,
EPROM)
TISIC
EXCITER MODULE
SSI
SCI
TO/FROM
STATUS
PORT
(RS-232)
SPI BUS
RECEIVE
DSP
DRAM
SRAM
970 MHZ
(1025 MHZ)
VCO/SYNTH
FREQUENCY
DOUBLER
SPI BUS
TRANLIN
IC
DATA/CLOCK
SPI BUS
2.1 MHZ
PLL/
VCO
SPI BUS
TO/FROM
ETHERNET
SPI BUS
DATA/CLOCK
SPI BUS
DIAGNOSTICS
CIRCUITRY
IF IN
ADDRESS DECODE,
MEMORY, A/D CONVERTER
237 MHZ
(180.6 MHZ)
VCO
IF OUT
ADDRESS DECODE,
MEMORY, A/D CONVERTER
TO
RFDS
(TRANSMIT
ANTENNA)
RF OUT
EXCITER
IC
RF FEEDBACK
COMBINER
FEEDBACK IN
RF OUT
FINAL
LINEAR
AMPS
SPLITTER
LINEAR
DRIVER
RF IN
LINEAR RF
AMPLIFIER
NOTES:
1. 2-Branch systems must have a 50 load (P/N 5882106P03) installed on Antenna Port #3.
2. Set the RX_FRU_CONFIG parameter as follows:
2-Branch Systems: 12
3-Branch Systems: 123
3. Where two frequencies are given, frequency without parentheses applies to 800 MHz BR only and frequency with parentheses applies to 900 MHz BR only.
EBTS284
120497JNM
Figure:1-3
68 P 8 1 0 95E02- D
11/9/2000
1-15
RECEIVE
ANTENNA
RECEIVER MODULE
POWER SUPPLY MODULE
TLN3429/TLN3339/TLN3338
RECEIVER MODULE
TLN3427
MIXER
RF IN
BAND
PASS
FILTER
IF
AMP
DIGITAL
ATTEN.
CIRCUIT
BAND
PASS
FILTER
CUSTOM
RECEIVER
IC
SPI BUS
2X INJECTION
AMP
BATTERY CHARGING/
REVERT CIRCUITRY
AGC
ADDRESS DECODE,
MEMORY,
A/D CONVERTER
SPI BUS
CLOCK
GENERATOR
CIRCUITRY
START-UP
INVERTER
CIRCUITRY
133 KHZ
+14.2 V
INVERTER
CIRCUITRY
2.1 MHZ
+5 V
INVERTER
CIRCUITRY
SPI BUS
5 MHZ
5 MHZ
EXTERNAL
REFERENCE
16.8 MHZ
HOST
P
NON-VOLATILE
MEMORY
(EEPROM, SRAM,
EPROM)
DRAM
SSI
TRANSMIT
DSP
SCI
TO/FROM
SERVICE
COMPUTER
CORRECTION SIGNALS
HOST
ASIC
SPI BUS
DSP
GLUE
ASIC
EXCITER MODULE
TLN3428
RECEIVE
DSP
ERROR
CORRECTION
DSP
2.1 MHZ
PLL/
VCO
SPI BUS
SPI BUS
SPI BUS
ETHERNET
INTERFACE
TO/FROM
SYNC MODEM
+5 VDC
TO BACKPLANE
TO/FROM STORAGE
BATTERY
DATA/CLOCK
TO/FROM
ETHERNET
+14.2 VDC
TO BACKPLANE
+28 VDC
TO BACKPLANE
DIAGNOSTICS
CIRCUITRY
AC INPUT
47 - 63 HZ
90V/264V
267 KHZ
SERIAL BUS
SYNTH/
VCO
INPUT FILTER
BOARD
MAIN INVERTER
CIRCUITRY
DSP BUS
LPF/
PRESELECT/
PERAMP/
IMAGE FILTER
700 MHZ
VCO/SYNTH
FREQUENCY
DOUBLER
SPI BUS
(TLN3425 ONLY)
ADDRESS DECODE,
MEMORY, A/D CONVERTER
TRANLIN
IC
DATA/CLOCK
236 MHZ
VCO
TRANSMIT
ANTENNA
IF IN
IF OUT
SPI BUS
EXCITER
IC
ADDRESS DECODE,
MEMORY, A/D CONVERTER
RF OUT
RF FEEDBACK
COMBINER
FEEDBACK IN
RF OUT
FINAL
LINEAR
AMP
AGC
CIRCUIT
SPLITTER
LINEAR
DRIVER
RF IN
LINEAR RF
AMPLIFIER
FINAL
LINEAR
AMP
Battery Charging/Revert Circuitry is contained only in the TLN3429 and TLN3339 AC Power Supplies.
Figure:1-4
1-16
11/ 9/ 2000
IF FILTER
AMP, AGC
LPF, AMP,
FILTER
MIXER
IF FILTER
AMP, AGC
LPF, AMP,
FILTER
VCO SYNTH
SPLITTER
ABACUS
RECEIVER
IC
MIXER
IF FILTER
AMP, AGC
PREAMPLIFIER
SPLITTER
/ BYPASS
LPF, AMP,
FILTER
RX3 DATA
16.8MHz
RX4 DATA
Host SPI
RECEIVER 3
IF FILTER
AMP, AGC
MIXER
IF FILTER
AMP, AGC
LPF, AMP,
FILTER
RF IN
PREAMPLIFIER
SPLITTER
/ BYPASS
FROM RFDS
(BRANCH 3)
MIXER
RECEIVER 2
RX1 DATA
MIXER
IF FILTER
AMP, AGC
LPF, AMP,
FILTER
MIXER
RECEIVE
DSP
RX SPI
RF IN
PREAMPLIFIER
SPLITTER
/ BYPASS
BUFFERS
HOST
uP
IF FILTER
AMP, AGC
LPF, AMP,
FILTER
SDRAM
RECEIVE
DSP
ABACUS
RECEIVER
IC
RX INTERFACE,
ADDRESS DECODE.
MEMORY, DIAGNOSTICS
VCO SYNTH
SPLITTER
IF FILTER
AMP, AGC
LPF, AMP,
FILTER
ABACUS
RECEIVER
IC
ABACUS
RECEIVER
IC
SPI BUS
EXCITER-BASE RADIO
CONTROLLER
STATUS
PORT
RS-232
MIXER
LPF, AMP,
FILTER
RX2 DATA
Rx1&2
ABACUS
RECEIVER
IC
Rx3&4
RX INTERFACE,
ADDRESS DECODE.
MEMORY, DIAGNOSTICS
RECEIVER 4
MIXER
ABACUS
RECEIVER
IC
QUAD RX IN DISTRIBUTION
FROM RFDS
(BRANCH 2)
IO LATCHES
MIXER
ABACUS
RECEIVER
IC
RX INTERFACE,
ADDRESS DECODE.
MEMORY, DIAGNOSTICS
VCO SYNTH
SPLITTER
IF FILTER
AMP, AGC
LPF, AMP,
FILTER
ABACUS
RECEIVER
IC
ABACUS
RECEIVER
IC
16.8MHz
FLASH
ETHERNET
INTERFACE
ETHERNET
5 MHZ
EXTERNAL
REFERENCE
IF FILTER
AMP, AGC
LPF, AMP,
FILTER
TRANSMIT
DSP
RF IN
TX RECLOCK
2.4MHz
48MHz
Tx_I
FROM RFDS
(BRANCH 1)
PREAMPLIFIER
SPLITTER
/ BYPASS
MIXER
LINEAR RF
AMPLIFIER
ODCT
ABACUS
RECEIVER
IC
ABACUS
RECEIVER
IC
RX INTERFACE,
ADDRESS DECODE.
MEMORY, DIAGNOSTICS
VCO SYNTH
SPLITTER
IF FILTER
AMP, AGC
LPF, AMP,
FILTER
ABACUS
RECEIVER
IC
Tx_Q
SPI BUS
Exciter
Host SPI
IF FILTER
AMP, AGC
MIXER
EEPROM
PLL/VCOs
MIXER
LPF, AMP,
FILTER
TISIC
16.8MHz
BASE RADIO
CONTROLLER
RECEIVER 1
I
Q
DAC
VCOs/Synths
COMBINER
SPI BUS
ADDRESS DECODE,
MEMORY, ADC
TO RFDS
(TX ANTENNA)
RF FEEDBACK
EXTERNAL
DC INPUT
41 - 60 VDC
LINEAR
DRIVER
SPLITTER
FINAL
LINEAR
AMPS
ADDRESS DECODE,
MEMORY, ADC
Figure:1-5
133 KHZ
+28 VDC
TO BACKPLANE
Main Converter
INPUT FILTER
START-UP
INVERTER
CIRCUITRY
1-17
RF IN
CLOCK
GENERATOR
14.2 V
CONVERTER
267 KHZ
133 KHZ
3.3 V
CONVERTER
+14.2 VDC
TO BACKPLANE
+3.3 VDC
TO BACKPLANE
11/ 9/ 2000
1-18
11/ 9/ 2000
Overview
This section provides technical information for the Base Radio Controller (BRC).
Table 2-1 describes covered topics.
Table 2-1
Chapter Topics
Chapter
Page
Description
2-2
2-13
2-25
2-29
Description
FRU Number
Kit Number
TLN3334
CLN1469
TLN3425
CLN1472
CLN1497
CLF1560
6 8 P 8 1 0 9 5 E02- D
12/6/2000
2-1
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
NOTE
BRC Modules with board level kit number CLN6989
require System Software Release version SR 3.3 or
higher. Using these modules with System Software
versions older than 3.3 causes a PENDULUM lock
error. The Base Radio will not function.
Two BRC modules serve as the main controller for the 1500 MHz Base Radio. The
standard model is the same module that the 800/900 MHz Base Radio uses.
Model TLN3425 contains additional Digital Signal Processing power. This
additional power supports applications that require a modied error correction
routine (available for specic customers only). Figure 2-2 shows a top view of the
BRC (model TLN3425) with the cover removed.
2-2
68P81095E02- D 12/6/200 0
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
Figure:2-1
1.5GHZ-A859
Figure:2-2
6 8 P 8 1 0 9 5 E02- D
12/6/2000
2-3
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
STATUS
CONTROL
B R P S E X P A C T L R 1 R 2 RESET
R3
EBTS316
122796JNM
Figure:2-3
Indicators
Table 2-3 lists and describes the BRC LEDs.
Table 2-3
LED
Color
BR
Green
PS
2-4
BR Controller Indicators
Red
Module
Monitored
Condition
BR
Solid (on)
Station is keyed
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
Power
Supply
Indications
68P81095E02- D 12/6/200 0
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
Table 2-3
LED
Color
EX
Red
PA
Red
CTL
R1
Red
Red
R2
Module
Monitored
Condition
Exciter
Solid (on)
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
Power
Amplier
Controller
Receiver #1,
#2, or #3
R3
Indications
Controls
Table 2-4 lists the controls and descriptions.
Table 2-4
BR Controller Controls
Control
Description
RESET Switch
STATUS
connector
STATUS Connector
Table 2-5 the pin-outs for the STATUS connector.
68 P 8 1 0 9 5 E02- D
12/6/2000
2-5
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
Table 2-5
Pin-out
Signal
CD
TXD
RXD
not used
GND
not used
CTS
RTS
not used
Theory of Operation
Table 2-6 briey describes the BRC circuitry. Figures 2-6 and 2-7 are functional
block diagrams of the Single Channel BRC.
BR Controller Circuitry
Table 2-6
Circuit
Description
Non-Volatile Memory
Consists of:
EPROMs containing the station operating software
one EEPROM containing the station codeplug data
2-6
Volatile Memory
Ethernet Interface
RS-232 Interface
Generates the 16.8 MHz and 2.1 MHz reference signal used
throughout the station.
Input Ports
Output Ports
68P81095E02- D 12/6/200 0
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
Host Microprocessor
The host microprocessor is the the BRs main controller. The host operates at a
clock speed of 16.5 MHz. The Host Glue ASIC provides this clock frequency. The
processor controls Base Radio operation according to station software in
non-volatile memory. Two EPROMs contain the station software. An EEPROM
stores the station codeplug.
Function
6 8 P 8 1 0 9 5 E02- D
12/6/2000
Description
SPI Bus
DRAM Controller
System Reset
Host Microprocessor
Clock
Address Decoding
Interrupt Controller
Accepts interrupt signals from various BRC circuits (such as the DSPs).
Organizes the interrupts based on hardware-dened priority ranking.
Sends interrupt and priority level information to the Host
Microprocessor (via IPL lines 1-3).
2-7
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
Non-Volatile Memory
The Base Radio software resides in two 512K x 8 byte EPROMs. The Host
Microprocessor addresses these EPROMs via 19 of 23 host address bus lines. The
host accesses EPROM data over the 16-line host data bus.
The data that determines the station personality resides in an 8K x 8 byte
codeplug EEPROM. The microprocessor addresses the EEPROM over 15 of 23
host address bus lines. The host accesses EEPROM data over the 16-line data bus.
Stations ship with default data programmed into the codeplug. The BRC must
download eld programming information from network and site controllers. This
data includes operating frequencies and output power level. The station permits
adjustment of many station parameters, but the station does not store
adjustments. Refer to this manuals Software Commands chapter for additional
information.
Volatile Memory
Each BRC contains 2MB of DRAM. The BRC downloads station software code
into DRAM for station use. Since DRAM is volatile memory, it loses data during a
system reset or power failure.
DRAM also provides short-term storage for data generated and required during
normal operation. The BRC performs read and write operations over the Host
Address and Data buses. Read and write operations also involve column and row
select lines. The Host Glue ASIC controls these lines. The Host Glue ASIC also
controls address bus and column row signals. During normal operation, the
address bus and column row signals sequentially refresh DRAM memory
locations.
The BRC also includes two 32K x 8 byte fast Static RAM (SRAM) ICs. The
microprocessor accesses SRAM over the Data Bus and Host Address Bus. Access
requires the entire Data Bus, and 15 of the Host Address Bus 23 lines.
Ethernet Interface
The Ethernet Interface includes a Local Area Network (LAN) Controller. This
LAN Controller is a 32-bit address, 16-bit data LAN coprocessor. The LAN
coprocessor implements the CSMA/CD access method, which supports the IEEE
802.3 10Base2 standard. The LAN coprocessor communicates with the Host
Microprocessor via DRAM. The LAN coprocessor uses 22 of its 32 address lines
for the Ethernet interface.
The LAN coprocessor supports all IEEE 802.3 Medium Access Control, including
the following:
2-8
framing
preamble generation
stripping
68P81095E02- D 12/6/200 0
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
The LAN coprocessor receives commands from the CPU by reading a specied
memory block. The LAN Controllers internal FIFOs optimize microprocessor bus
performance.
The LAN coprocessor includes an on-chip, Direct Memory Access (DMA)
controller. The DMA controller automatically transfers data blocks (buffers and
frames) from Ethernet to DRAM. These automatic data transfers relieve the host
CPU of byte transfer overhead.
The Ethernet Serial Interface works with the LAN coprocessor to perform these
major functions:
Minimum inductance of 75 H
The Coaxial Transceiver Interface (CTI) is a coaxial cable line driver/receiver for
the Ethernet. CTI provides a 10Base2 connection via a coaxial connector on the
board. This device minimizes the number of external components necessary for
Ethernet operations.
A DC/DC converter provides a constant voltage of -9 Vdc for the CTI. The
converters input source voltage is 5 Vdc.
The CTI performs the following functions:
Disables the transmitter when packets are longer than the legal length
(Jabber Timer)
6 8 P 8 1 0 9 5 E02- D
12/6/2000
2-9
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
The RXDSP operates from a 40 MHz clock provided by an on-board crystal. The
RXDSP accepts redigitized signal from the receivers. The RXDSP also provides
address and data buses. These buses receive digitized audio from the TISIC.
The DSP program and signal processing algorithms reside in three 32K x 8 SRAM
ICs. The RXDSP accesses this software there. The RXDSP communicates with the
host bus via an 8-bit interface.
The Synchronous Serial Interface (SSI) port offers a serial data path to the TXDSP.
The Serial Communications Interface (SCI) port provides a serial control path
from the TXDSP.
The TXDSP operates at a clock speed of 40 MHz, provided by a clock oscillator.
The TXDSP sends the digitized signal to the TISIC. The TSCI then passes the
signal to the Exciter.
The TXDSP contains its own address and data buses. It uses these buses to access
its DSP program and signal processing algorithms in local memory. The TXDSP
memory consists of six 32K x 8 SRAM ICs. The TXDSP communicates with the
host bus via an 8-bit interface.
2-10
68P81095E02- D 12/6/200 0
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
TISIC
The TISIC controls internal DSP operations. This circuit provides a number of
functions, including the following:
Interfaces with the DSPs via the DSP address and data buses.
Outputs a 2.1 MHz reference signal used by the Exciter and Receivers.
Outputs a 4.8 MHz reference signal used by the Exciter to clock data into the
TRANLIN IC.
Accepts differential data from the Receiver (RX1 through RX3) via
interface circuitry.
Accepts and sends serial data from the Receiver (RX1 through RX3) via the
serial data bus.
Accepts and formats differential data from the TXDSP for transmission to
the Exciter via interface circuitry.
Generates 15 ms and 7.5 ms ticks. These synchronize to the 1 PPS time mark
from the iSC. The system routes these ticks to the TXDSP and RXDSP,
respectively.
Generates the Receive SSI (RXSSI) frame sync interrupt for the RXDSP.
6 8 P 8 1 0 9 5 E02- D
12/6/2000
2-11
800/900/1500 MHz Base Radio Controller CLN1469; 1500 MHz MC1 Base Radio Controller TLN3425
Input Ports
Two general purpose, 16-line input ports provide for various input signals from
the BRC and station circuitry. These inputs connect to the Host Microprocessor.
Input Port P0 -In and Port P1-In each consist of 16 lines. Via the backplane, these
lines carry signals from BRC circuitry and other station modules. The buses
communicate with the buffers to make data available to the Host Microprocessor
via the Host Data Bus. The DIP switch and Station Reference Circuitry are typical
inputs for these ports.
Output Ports
Three general purpose, 16-line output ports provide various control signals from
the Host Microprocessor. Via the backplane, these output ports carry control
signals to the BRC and station circuitry.
Output ports P0-Out through Port P2-Out each consist of 16 lines. These lines
derive from the Host Data Bus via latches.
Typical control signals include front panel LED control signals and SPI peripheral
address select lines.
2-12
68P81095E02- D 12/6/2000
Figure:2-4
6 8 P 8 1 0 9 5 E02- D
12/6/2000
2-13
allows a manual reset of the Base Radio. Figure 2-5 shows the front panel of the
BRC.
Figure:2-5
Indicators
Table 2-8 lists and describes the BRC LEDs.
Table 2-8
LED
PS
EXBRC
PA
REF
2-14
BR Controller Indicators
Color
Red
Red
Red
Red
Module
Monitored
Condition
Power
Supply
Solid (on)
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
Controller/Exciter is operating
normally (no alarms)
Solid (on)
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
Controller/
Exciter
Power
Amplier
Controller
Station
Reference
Indications
68P81095E02- D 12/6/2000
Table 2-8
LED
Module
Monitored
Condition
Red
Receiver #1,
#2, #3, or #4
Solid (on)
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
Solid (on)
Flashing (on)
Off
RX1
RX2
RX3
RX4
TX1
Green
TX2
Green
TX3
Green
TX4
Green
BR
BR
BR
BR
Indications
Controls
Table 2-9 lists the controls and descriptions.
Table 2-9
BR Controller Controls
Control
Description
RESET Switch
STATUS
connector
STATUS Connector
Table 2-10 the pin-outs for the STATUS connector.
6 8 P 8 1 0 9 5 E02- D
12/6/2000
2-15
Table 2-10
Pin-out
Signal
not used
TXD
RXD
not used
GND
not used
not used
not used
not used
Theory of Operation
Table 2-11 briey describes the BRC circuitry. Figure 2-9 is a functional block
diagram of the BRC.
Table 2-11
BR Controller Circuitry
Circuit
Description
Host Microprocessor
Non-Volatile Memory
Consists of:
FLASH containing the station operating software
EEPROM containing the station codeplug data
Volatile Memory
2-16
68P81095E02- D 12/6/2000
BR Controller Circuitry
Table 2-11
Circuit
Description
Ethernet Interface
RS-232 Interface
TISIC
TX Reclock
RX DSP SPI
Input Ports
Output Ports
Host Microprocessor
The host microprocessor is the main controller for the BR. The processor operates
at a 50-MHz clock speed. The processor controls Base Radio operation according
to station software in memory. Station software resides in FLASH memory. For
normal operation, the system transfers this software to non-volatile memory. An
EEPROM contains the station codeplug.
NOTE
At BR power-up, the EXBRC LED indicates a major
alarm. This indication continues until BR software
achieves a predetermined state of operation.
Afterward, the software turns off the EXBRC LED.
6 8 P 8 1 0 9 5 E02- D
12/6/2000
2-17
SMC port and the front- panel STATUS connector is via EIA-232 Bus Receivers
and Drivers.
Host Processor
The microprocessor incorporates 4k bytes of instruction cache and 4k bytes of
data cache that signicantly enhance processor performance.
The microprocessor has a 32-line address bus. The processor uses this bus to
access non-volatile memory and SDRAM memory. Via memory mapping, the
processor also uses this bus to control other BRC circuitry.
The microprocessor uses its Chip Select capability to decode addresses and assert
an output signal. The eight chip-select signals select non-volatile memory,
SDRAM memory, input ports, output ports, and DSPs.
The Host SPI serves as a general-purpose, serial communications bus. This bus...
The Host supports several internal interrupts from its Communications Processor
Module. These interrupts allow efcient use of peripheral interfaces.
The Host supports 10 Mbps Ethernet/IEEE 802.3.
A 32-line data bus transfers data to and from BRC memory and other BRC
circuitry. Buffers on this data bus allow transfers to and from non-volatile and
SDRAM memory.
Non-Volatile Memory
Base Radio software resides in 2M x 32 bytes of FLASH memory. The Host
Microprocessor addresses the FLASH memory with 20 of the host address bus 32
lines. The host accesses FLASH data over the 32-line host data bus. A
host-operated chip-select line provides control signals for these transactions.
The FLASH contains the operating system and application code. The system
stores application code in FLASH for fast recovery from reset conditions.
Application code transfers from network or site controllers may occur in a
background mode. Background mode transfers allow the station to remain
operational during new code upgrades.
The data that determines the station personality resides in a 32K x eight byte
codeplug EEPROM. The microprocessor addresses the EEPROM with 15 of the
host address bus 32 lines. The host accesses EEPROM data with eight of the data
bus 32 lines. A host-operated chip-select line provides control signals for these
transactions.
2-18
68P81095E02- D 12/6/2000
During the manufacturing process, the factory programs the codeplugs default
data. The BRC must download eld programming data from network and site
controllers. This data includes operating frequencies and output power level. The
station permits adjustment of many station parameters, but the station does not
store these adjustments. Refer to the Software Commands chapter for additional
information.
Volatile Memory
Each BRC contains 8MB x 32 bytes of SDRAM. The BRC downloads station
software code into SDRAM for station use. SDRAM also provides short-term
storage for data generated and required during normal operation. SDRAM is
volatile memory. A loss of power or system reset destroys SDRAM data.
The system performs read and write operations over the Host Address and Data
buses. These operations involve column and row select lines under control of the
Host processors DRAM controller. The Host Glue ASICs address bus and
column row signals sequentially refresh SDRAM memory locations.
Ethernet Interface
The Host processors Communications Processor Module (CPM) provides the
Local Area Network (LAN) Controller for the Ethernet Interface. The LAN
function implements the CSMA/CD access method, which supports the IEEE
802.3 10Base2 standard.
The LAN coprocessor supports all IEEE 802.3 Medium Access Control, including
the following:
framing
preamble generation
stripping
6 8 P 8 1 0 9 5 E02- D
12/6/2000
Minimum inductance of 75 H
2-19
The Coaxial Transceiver Interface (CTI) is a coaxial cable line driver and receiver
for the Ethernet. CTI provides a 10Base2 connection via a coaxial connector on the
board. This device minimizes the number of external components necessary for
Ethernet operations.
A DC/DC converter provides a constant voltage of -9 Vdc for the CTI from a
3.3 Vdc source.
The CTI performs the following functions:
Disables the transmitter when packets are longer than the legal length
(Jabber Timer)
2-20
68P81095E02- D 12/6/2000
The TXDSP operates at an external clock speed of 16.8 MHz, provided by the
EXBRC local station reference. The TXDSP internal operating clock is 150MHz,
produced by an internal Phase Lock Loop (PLL).
The TXDSP sends up to four carriers of digitized signal to the EX11 exciter. The
exciter converts the digital signal to analog. Also at the exciter, a highly stable
clock reclocks the digital data. Reclocking enhances transmit signal integrity. Two
framed and synchronized data streams result. One data stream is I-data, and the
other is the Q-data stream.
The TXDSP contains its own, internal address and data memory. The TXDSP can
store 128k words of DSP program and data memory. An eight-bit interface
handles TXDSP-to-host bus communications.
6 8 P 8 1 0 9 5 E02- D
12/6/2000
2-21
TISIC
The TISIC controls internal DSP operations. This circuit provides the following
functions:
For initialization and control, interfaces with one RXDSP via the DSP
address and data buses.
Accepts a 5 MHz signal, modulated with one pulse per second (1 PPS) from
the site reference.
Outputs a 1 PPS signal and a windowed version of this signal for network
timing alignment.
Generates 15 ms and 7.5 ms ticks. (These ticks synchronize to the 1 PPS time
mark. The system decodes the time mark from the site reference. Then the
system routes the reference to the TXDSP and RXDSPs.)
2-22
68P81095E02- D 12/6/2000
Input Ports
One general-purpose input register provides for BRC and station circuit input
signals. The register has 16 input ports. The Host Data Bus conveys input register
data to the Host Microprocessor. Typical inputs include 16.8 and 48 MHz Station
Reference Circuitry status outputs and reset status outputs.
Output Ports
Two general-purpose output registers distribute control signals from the Host
Microprocessor to the BRC and station circuitry. Each register has 40 output ports.
Control signal distribution occurs over the backplane. The Host Data Bus drives
the output ports latched outputs. Typical control signals include front-panel LED
signals and SPI peripheral enable and address lines.
6 8 P 8 1 0 9 5 E02- D
12/6/2000
2-23
2-24
68P81095E02- D 11/9/2000
HOST
INTERFACE
A2-A23
DATA BUS
EIA-232
BUS
RECEIVERS/
DRIVERS
D0-D15
LANIIC
COPROCESSOR
ADDR BUS
COPROCESSOR
DATA BUS
ETHERNET
COPROCESSOR
(82596DX)
ETHERNET
SERIAL
INTERFACE
ETHERNET
SERIAL
INTERFACE
RCV
ISOLATION
TRANSFORMER
HOST
MICROPROCESSOR
CD
CLSN
RX
TRANSCEIVER
RS-232 PORT
(9 PIN D CONNECTOR
ON BACKPLANE)
RESET SWITCH
(FRONT PANEL)
VCC
10BASE2
HOST DATA BUS
COAX
TX
TRMT
EIA-232
BUS
RECEIVERS/
DRIVERS
STATUS PORT
(9 PIN D CONNECTOR
ON BRC FRONT PANEL)
33 MHZ
TIMING
CIRCUITRY
BUFFERS
ETHERNET INTERFACE
HOST
GLUE
ASIC
SPI BUS
TO/FROM
STATION MODULES
SPI BUS
LED CONTROL
LINES
(P/O I/O PORT
P0 OUT)
BASE
RADIO
POWER
SUPPLY
EXCITER
PA
CTL
R1
R2
R3
NON-VOLATILE MEMORY
DRAM
ADDRESS
DRAM
1M X 16
EPROM
512K X 8
COL
SELECT
(CAS*)
A1-A19
28V
I/O PORT
P2 OUT
SHUTDOWN
CIRCUITRY
SHUTDOWN
(TO POWER
SUPPLY)
A1-A19
HOST
ADDRESS
A1-A18
ROW
SELECT
(RAS*)
EPROM
512K X 8
HOST ADDRESS BUS
D0-D15
DRAM ADDRESS
MULTIPLEXER
8K X 8
EEPROM
CODEPLUG
REMOTE STATION
SHUTDOWN CIRCUITRY
A1-A15
DRAM
COLUMN
ADDRESS
D0-D7
BUFFERS
HOST
ADDRESS
1-23
HOST DATA BUS
FROM HOST
MICROPROCESSOR
32K X 8
SRAM
A1-A15
16
I/O PORT P0 IN
BUFFERS
VARIOUS INPUTS
FROM BRC &
STATION CIRCUITRY
16
I/O PORT P1 IN
BUFFERS
I/O PORT P2 OUT
16
16
A1-A11
VARIOUS
CONTROL
LINES TO BRC &
STATION
CIRCUITRY
D0-D15
BUFFERS
32K X 8
SRAM
A10-A22
DRAM
ROW
ADDRESS
A1-A15
D0-D15
COLUMN/ROW
SELECT
DRAM MEMORY
EBTS286
Figure:2-6
6 8 P 8 1 0 95E02- D
4/16/99
2-25
TRANSMIT SYNCHRONOUS
SERIAL INTERFACE (TXSSI)
RX1 DATA
3
DIFFERENTIAL DATA
FROM RECEIVER MODULE #1
VIA BACKPLANE
SYNCHRONOUS
SERIAL INTERFACE (SSI)
SERIAL BUS
HOST
PORT
HOST
ADDRESS
BUS
SERIAL
COMMUNICATIONS
INTERFACE (SCI)
DIFFERENTIAL-TO-TTL
CONVERTER/BUFFER
RX2 DATA
DIFFERENTIAL-TO-TTL
CONVERTER/BUFFER
RX3 DATA
RX2 DATA
32K X 8
FROM
HOST
MICROPROCESSOR
ADDRESS
HOST
DATA
BUS
RX1 DATA
SERIAL BUS
TO/FROM
RECEIVER
MODULE #1
SERIAL BUS
BUFFERS
RX1 SERIAL
DIFFERENTIAL-TO-TTL
CONVERTER/BUFFER
DATA
RAM
DIFFERENTIAL DATA
FROM RECEIVER MODULE #2
VIA BACKPLANE
32K X 8
TRANSMIT
DIGITAL
SIGNAL
PROCESSOR
(TXDSP)
RAM
SERIAL BUS
32K X 8
SERIAL BUS
TO/FROM
RECEIVER
MODULE #2
SERIAL BUS
BUFFERS
RX2 SERIAL
RAM
32K X 8
RX3 DATA
RAM
32K X 8
DIFFERENTIAL DATA
FROM RECEIVER MODULE #3
VIA BACKPLANE
TISIC
RAM
SERIAL BUS
32K X 8
CLOCK
OSCILLATOR
RAM
SERIAL BUS
BUFFERS
RX3 SERIAL
TTL-TO-DIFFERENTIAL
CONVERTER/BUFFER
FROM
HOST
MICROPROCESSOR
DIFFERENTIAL DATA
TO EXCITER MODULE
VIA BACKPLANE
TTL-TO-DIFFERENTIAL
CONVERTER/BUFFER
TXLIN
DATA
AGC
HOST
DATA
BUS
SERIAL BUS
TO/FROM
RECEIVER
MODULE #3
TO RECEIVERS (1-3)
4
HOST
PORT
HOST
ADDRESS
BUS
RECEIVE
DIGITAL
SIGNAL
PROCESSOR
(RXDSP)
SERIAL
COMMUNICATIONS
INTERFACE (SCI)
3
RECEIVE SYNCHRONOUS
SERIAL INTERFACE BUS
(RXSSI)
2.1 MHZ
OUT
ADDRESS
ADDRESS
16.8 MHZ
IN
BUFFER/
SPLITTER
5 MHz/1PPS
BNC CONNECTOR
ON BACKPLANE
DATA
DATA
5 MHZ REF
32K X 8
OSCIN
SPI BUS
FIN
PHASE
LOCKED
LOOP
IC
1PPS
RAM
16.8 MHZ
RESET
HIGH
STABILITY
VCXO
32K X 8
RAM
32K X 8
ENABLE
INPUT
CONTROL VOLTAGE
RAM
DIGITAL SIGNAL PROCESSOR (DSP) / DSP ASIC
CONTROL VOLTAGE
ENABLE SWITCH
EBTS292
122094JNM
Figure:2-7
26
4/ 16/ 99
20 MHZ
TIMING
CIRCUIT
HOST
INTERFACE
DATA BUS
EIA-232
BUS
RECEIVERS/
DRIVERS
DC/DC
CONVERTER
5 VDC
20 MHz
COPROCESSOR
ADDR BUS
COPROCESSOR
DATA BUS
82596DX
ETHERNET
COPROCESSOR
CD
CLSN
ETHERNET
SERIAL
INTERFACE
ETHERNET
SERIAL
INTERFACE
RCV
ISOLATION
TRANSFORMER
TRANSCEIVER
RX
23
HOST DATA BUS
TX
TRMT
RS232
(9 PIN D CONNECTOR
ON BACKPLANE)
10BASE2
COAX
XMT CLK
(10 MHZ)
EIA-232
BUS
RECEIVERS/
DRIVERS
-9 VDC
HOST
MICROPROCESSOR
STATUS
(9 PIN D CONNECTOR
ON BRC FRONT PANEL)
HOST
ASIC
16
ETHERNET INTERFACE
BUFFERS
33 MHZ
TIMING
CIRCUITRY
SPI BUS
TO/FROM
STATION MODULES
SPI BUS
LED CONTROL
LINES
(P/O I/O PORT
P0 OUT)
DRAM
ADDRESS
BASE
RADIO
POWER
SUPPLY
EXCITER
PA
BRC
RX1
RX2
RX3
DRAM
1M X 8
NON-VOLATILE MEMORY
COL
SELECT
(CAS*)
DRAM
1M X 8
A1-A18
28V
I/O PORT
P3 OUT
SHUTDOWN
CIRCUITRY
ROW
SELECT
(RAS*)
COL
SELECT
(CAS*)
SHUTDOWN
(TO POWER
SUPPLY)
EPROM
256K X 8
A1-A18
HOST
ADDRESS
A1-A23
DRAM ADDRESS
MULTIPLEXER
8K X 8
EEPROM
CODEPLUG
REMOTE STATION
SHUTDOWN CIRCUITRY
A1-A15
BUFFERS
HOST
ADDRESS
1-23
HOST DATA BUS
FROM HOST
MICROPROCESSOR
16
LATCHES
BUFFERS
16
I/O PORT P2 OUT
16
I/O PORT P1 IN
VARIOUS
CONTROL
LINES TO BRC &
STATION
CIRCUITRY
8K X 8
SRAM
A1-A13
BUFFERS
A10-A22
DRAM
ROW
ADDRESS
8K X 8
SRAM
16
COLUMN/ROW
SELECT
A1-A13
STATIC RAM
Figure:2-8
4/16/99
A1-A11
16
I/O PORT P0 IN
6 8 P 8 1 0 95E02- D
DRAM
COLUMN
ADDRESS
VARIOUS INPUTS
FROM BRC &
STATION CIRCUITRY
ROW
SELECT
(RAS*)
DYNAMIC RAM
2-27
TRANSMIT SYNCHRONOUS
SERIAL INTERFACE (TXSSI)
40 MHZ
TIMING
CIRCUITRY
RX1 DATA
3
ADDRESS
SCI
DIFFERENTIAL DATA
FROM RECEIVER MODULE #1
VIA BACKPLANE
32K X 8
DATA
RAM
SERIAL BUS
32K X 8
TRANSMIT
DIGITAL
SIGNAL
PROCESSOR
SSI
RX1 SERIAL
RAM
32K X 8
SERIAL BUS
TO/FROM
RECEIVER
MODULE #1
SERIAL BUS
BUFFERS
6
RX1 DATA
DIFFERENTIAL-TO-TTL
CONVERTER/BUFFER
RX2 DATA
RAM
32K X 8
HOST
PORT
DIFFERENTIAL DATA
FROM RECEIVER MODULE #2
VIA BACKPLANE
RAM
RX2 DATA
DIFFERENTIAL-TO-TTL
CONVERTER/BUFFER
RX3 DATA
32K X 8
LATCH ADDRESS
BUS
SERIAL BUS
RAM
RX2 SERIAL
32K X 8
RX3 DATA
DSP
GLUE
ASIC
10 MHZ TIMING
CIRCUITRY
SERIAL BUS
TO/FROM
RECEIVER
MODULE #2
SERIAL BUS
BUFFERS
RAM
DIFFERENTIAL DATA
FROM RECEIVER MODULE #3
VIA BACKPLANE
ADDRESS
SERIAL BUS
RX3 SERIAL
32K X 8
SERIAL BUS
TO/FROM
RECEIVER
MODULE #3
SERIAL BUS
BUFFERS
6
DATA
SSI
RAM
TTL-TO-DIFFERENTIAL
CONVERTER/BUFFER
3
SSI
TXLIN
DATA
ERROR
CORRECTION
DIGITAL
SIGNAL
PROCESSOR
LATCH
HOST ADDRESS
BUS FROM HOST
MICROPROCESSOR
DIFFERENTIAL-TO-TTL
CONVERTER/BUFFER
32K X 8
DIFFERENTIAL DATA
TO EXCITER MODULE
VIA BACKPLANE
TTL-TO-DIFFERENTIAL
CONVERTER/BUFFER
TXLIN
CLOCK
DIFFERENTIAL DATA
TO EXCITER MODULE
VIA BACKPLANE
RAM
AGC
TO RECEIVER
VIA BACKPLANE
AGC
LATCH ADDRESS
BUS
ADDRESS
ADDRESS
HOST
PORT
DATA
RECEIVE
DIGITAL
SIGNAL
PROCESSOR
SSI
RAM
32K X 8
SCI
RAM
3
1 PPS
1 PPS
IN
32K X 8
2.1 MHZ
OUT
16.8 MHZ
IN
5 MHZ FROM
EXTERNAL
REFERENCE
(FOR NETTING
PENDULUM)
1 PPS
STRIPPER
PAL
BNC CONNECTOR
ON BACKPLANE
OSC
IN
PHASE
LOCKED
LOOP IC
FIN
32K X 8
SPI BUS
40 MHZ
TIMING
CIRCUITRY
RECEIVE SYNCHRONOUS
SERIAL INTERFACE BUS
(RXSSI)
28
5 MHZ REF
SPI BUS
RAM
Figure:2-9
BUFFER/
SPLITTER
HIGH
STABILITY
VCO
16.8 MHZ
16.8 MHZ TO ASIC
CONTROL VOLTAGE
ENABLE SWITCH
CONTROL VOLTAGE
FREQUENCY NET ENABLE
(I/O PORT P1 OUT)
4/ 16/ 99
LED
CONTROL
LINES
HOST
LATCH
P0 OUT
12
3.3V
POWER
SUPPLY
EXCITER/
CONTROL
PA
REF
RX1
RX2
RX3
RX4
TX1
TX2
TX3
P0_OUT
TX4
REMOTE STATION
SHUTDOWN CIRCUITRY
G
A
T
I
N
G
5MHZ_1PPS
BASE RADIO
INPUT
5MHZ
1PPS
SHUTDOWN
(TO POWER
SUPPLY)
SHUTDOWN
CIRCUITRY
SYNTHESIZER
IC / CIRCUITRY
PHASE
DETECTION/
FILTERING/
CONTROL
SPI
BUS
STEARING
LINE
HIGH
STABILITY
VCXO
16.8 MHZ
16.8MHZ
DISCONNECT/
CONNECT
CONTROL
SYNTHESIZER
IC / CIRCUITRY
PHASE
DETECTION/
FILTERING
STEARING
LINE
HIGH
STABILITY
VCXO
48 MHZ
SPI
BUS
(Sheet 1 of 2)
68 P 8 1 0 95E02- D
12/4/2000
2--29
QUAD Channel
Base Radio Controller
Functional Block Diagram
2
SCC1
ETHERNET
SERIAL
INTERFACE
EIA-232
BUS
RECEIVERS/
DRIVERS
STATUS PORT
(9 PIN D CONNECTOR
ON BRC FRONT PANEL)
DIFFERENTIAL
TO SINGLE END
DIFFERENTIAL
TO SINGLE END
DIFFERENTIAL
TO SINGLE END
DIFFERENTIAL
TO SINGLE END
ETHERNET INTERFACE
CLSN
ETHERNET
SERIAL
INTERFACE
CD
RCV
RX
ISOLATION
TRANSFORMER
TRMT
TRANSCEIVER
10BASE2
COAX
TX
RECEIVE
DIGITAL
SIGNAL
PROCESSOR
(RX DSP 2)
D[16:23]
RECEIVE
DIGITAL
SIGNAL
PROCESSOR
(RX DSP 1)
SPI BUS TO
RECEIVER 3 & 4
PARALLEL
TO SERIAL
CIRCUITRY
D[16:23]
SPI BUS TO
RECEIVER 1 & 2
D[0, 23]
2.4 MHz
TO EXCITER
D[0, 8:23]
TISIC
A[0:5]
SPI BUS
TO/FROM
STATION MODULES
BUFFER
SPI
BUS
NETWORKED
SCI
EXTENDED HOST
BUS BUFFERS
A[10:31]
HOST
A[0:7]
MICROPROCESSOR
GPLA0, A[8,9,17,18,20:29],RAS,CAS,WE
5MHZ
1PPS
FRONT PANEL
RESET
16
16
BUFFER
DRAM MEMORY
16.8MHZ
MA[21:0]
CS2
CS3
SDRAM
4M x 16
BUFFER
D[0:15]
SDRAM
4M x 16
D[0:15]
16
16
DSP_A[31:24]
BUFFER
SDRAM
4M x 16
SDRAM
4M x 16
D[16:31]
16
D[16:31]
D[0:31]
BUFFER
16
TRANSMIT
DIGITAL
SIGNAL
PROCESSOR
(TX DSP)
MD[31:0]
D[0:31]
BUFFER
16
16
CS4
BUFFER
MD[0:32]
FLASH
1M x 16
P0_IN
STATUS BUS
FROM
STATION MODULES
SERIAL DATA
TO EXCITER
MA[0:14]
CS0
CS1
50 MHZ
CLOCK
SINGLE END
TO DIFFERENTIAL
MA[2:21]
MA[2:21]
I/Q DATA
48 MHZ
DSP SPI
DSP_D[31:24]
TRANSMIT
CLOCK AND
FRAME SYNCH
CIRCUITRY
MD[0:15]
FLASH
1M x 16
MD[16:31]
NON-VOLATILE MEMORY
FLASH
1M x 16
FLASH
1M x 16
P0_IN
BUFFER
MD[0:15]
EEPROM
32k x 8
P0_OUT
LATCH
MD[24:31]
8
MD[16,17,20-24,28-31]
MD[16:31]
P1_OUT
LATCH
SPI
BUS
32
MD[24:31]
40
EXCITER
SPI
CONTROL
SPI BUS
TO EXCITER
P0_OUT/P1_OUT
CONTROL BUS
TO
STATION MODULES
(Sheet 2 of 2)
2--30
12/ 4/ 2000
3 Exciter
Overview
This section provides technical information for the Exciter (EX). Table 3-1
describes covered topics.
Table 3-1
Chapter Topics
Chapter
Page
Description
3-2
3-7
3-11
3-13
Description
FRU Number
Kit Number
TLN3337
CLF1490
CLN1357
CLF1500
TLN3428
CTX1120
CLN1497
CLF1560
6 8 P 8 1 0 9 5 E02- D
11/9/2000
3-1
800 MHz Exciter TLN3337; 900 MHz Exciter CLN1357; 1500 MHz Exciter TLN3428
Figure:3-1
3-2
68P81095E02- D 11/9/200 0
Figure:3-2
Theory of Operation
Table 3-3 lists and describes basic Exciter circuitry. Figures 3-4 and 3-5 show the
functional block diagram of the Single Carrier Exciter. Figures 3-6 show the
functional block diagram of the QUAD Carrier Exciter.
Memory Circuitry
The memory circuitry consists of an EEPROM located on the Exciter. The BRC
performs all memory read and write operations via the SPI bus. Information
6 8 P 8 1 0 9 5 E02- D
11/9/2000
3-3
800 MHz Exciter TLN3337; 900 MHz Exciter CLN1357; 1500 MHz Exciter TLN3428
Table 3-3
Exciter Circuitry
Circuit
Tranlin IC
Description
Performs the following functions:
up-converts the baseband data to the rst IF
down-converts the IF feedback signal to baseband
uses a baseband Cartesian feedback loop system, which is
necessary to obtain linearity from the transmitter and
avoid splattering power into adjacent channels
performs training functions for proper linearization of the
transmitter
Exciter IC
Frequency Synthesizer
Circuitry
Regulator Circuitry
stored in this memory device includes the kit number, revision number, module
specic scaling and correction factors, and free form information (scratch pad).
3-4
68P81095E02- D 11/9/200 0
The BRC monitors the regulated voltages, the external wattmeter (optional), the
PLL circuit, and other internal signals.
Tranlin IC Circuitry
The Tranlin IC is a main interface between the Exciter and BRC. The Digital Signal
Processors (DSP) of the BRC send Digitized signals (baseband data) to the Exciter
via the DSP data bus. The DSP clock signal from the Receiver clocks these data
signals.
The differential data clock signal also serves as a 4.8 MHz reference signal to the
internal synthesizer circuit of the Tranlin IC. The Tranlin compares the reference
signal with the output of the 237 MHz or 180.6 MHz (900 MHz BR) or 236 MHz
(1500 MHz BR) Voltage Controlled Oscillator (VCO). If the VCO output is out of
phase or differs in frequency, correction pulses arrive at the Oscillator and adjust
the VCO output.
The Tranlin IC up-converts the baseband data received from the BRC to the rst IF
of 118.5 MHz (90.3 MHz for 900 MHz BR). It also down-converts an IF feedback
signal from the Exciter IC to baseband data for summing.
The Serial Peripheral Interface (SPI) bus is used to communicate with the Tranlin
IC. The SPI bus serves as a general purpose bi-directional serial link between the
BRC and other modules of the Base Radio, including the Exciter. The SPI bus is
used to send control and operational data signals to and from the various circuits
of the Exciter.
Exciter IC Circuitry
The Exciter IC interfaces directly with the Tranlin IC to perform up-conversion
from the rst IF to the programmed transmit operating frequency. The rst IF
signal is passed through a band-pass lter before it reaches the Exciter IC.
The Exciter IC also down-converts the RF feedback signal from the PA to its IF
signal. The IF signal is then input to the Tranlin IC for conversion to baseband
data, which computes the Cartesian feedback.
Synthesizer Circuitry
The synthesizer circuitry consists of the Phase-Locked Loop (PLL) IC and
associated circuitry. The output of this circuit is combined with the 970 MHz
VCO (1025 MHz for 900 MHz BR, 700 MHz for 1500 MHz BR) to supply a Local
Oscillator (LO) signal to the Exciter IC for the second up-conversion of the
programmed transmit frequency. This signal is also used for the rst
down-conversion of the feedback signal from the PA.
An internal phase detector generates a logic pulse in proportion to the difference
in phase or frequency between the reference frequency and loop pulse signal.
If the reference frequency is faster than the VCO feedback frequency, the PLL IC
outputs an up signal. If the reference frequency is slower than the VCO feedback
frequency, the PLL IC outputs a down signal. These pulses are used as correction
signals and are fed to a charge pump circuit.
6 8 P 8 1 0 9 5 E02- D
11/9/2000
3-5
800 MHz Exciter TLN3337; 900 MHz Exciter CLN1357; 1500 MHz Exciter TLN3428
The charge pump circuit consists of ve transistors and its associated biasing
components. This circuit generates the correction signal and causes it to move up
or down in response to the phase detector output pulses. The correction signal
passes through the low-pass loop lter to the 970 MHz Voltage Controlled
Oscillator (VCO) circuit (1025 MHz VCO for 900 MHz BR).
Regulator Circuity
This circuit generates three regulated voltages of +5 Vdc, +10 Vdc, and +11.8 Vdc.
All voltages are obtained from the +14.2 Vdc backplane voltage. These voltages
provide power to various ICs and RF devices of the Exciter.
3-6
68P81095E02- D 11/9/200 0
Figure:3-3
6 8 P 8 1 0 9 5 E02- D
11/9/2000
3-7
Theory of Operation
Table 3-4 describes the basic circuitry of the Exciter. Figures 3-4 and 3-5 show the
functional block diagram of the Single Carrier Exciter. Figures 3-6 show the
QUAD Carrier Exciters functional block diagram.
Table 3-4 Exciter Circuitry
Circuit
LNODCT IC
Description
Up-converts baseband data to the transmit frequency
Down-converts the PA feedback signal to baseband
Uses a baseband Cartesian feedback loop system, necessary
to obtain linearity from the transmitter and avoid
splattering power into adjacent channels
Performs training functions for proper linearization of the
transmitter
Frequency Synthesizer
Circuitry
Memory Circuitry
The memory circuitry is an EEPROM on the Controller portion of the Exciter/
Controller module. The Controller performs memory read and write operations
over the SPI bus. The memory device stores the following data...
3-8
kit number
revision number
serial number
68P81095E02- D 11/9/200 0
LNODCT IC Circuitry
The LNODCT IC is a main interface between the Exciter and BRC. The BRCs
Digital Signal Processor (DSP) sends digitized signals (baseband data) to the
Exciter over the DSP data bus.
The differential data clock signal serves as a 4.8 MHz reference signal to the
LNODCT ICs internal synthesizer. The LNODCT compares the reference signal
with the outputs of Voltage Controlled Oscillators (VCOs). The LNODCT might
sense that a VCOs output is out of phase or off-frequency. If so, then the
LNODCT sends correction pulses to the VCO. The pulses adjust VCO output,
thereby matching phase and frequency with the reference.
The LNODCT IC up-converts baseband data from the BRC to the transmit
frequency. The LNODCT IC also down-converts the Transmit signal from the
Power Amplier to baseband data for summing.
The BRC uses the Serial Peripheral Interface (SPI) bus to communicate with the
LNODCT IC. The SPI bus serves as a general purpose, bi-directional, serial link
between the BRC and other Base Radio modules, including the Exciter. The SPI
carries control and operational data signals to and from Exciter circuits.
Synthesizer Circuitry
The synthesizer circuit consists of the Phase-Locked Loop (PLL) IC and associated
circuitry. This circuits output combines with the 970 MHz VCO signal. The result
is a Local Oscillator (LO) signal for the LNODCT IC. The LNODCT uses this LO
signal to up-convert the programmed transmit frequency. The LNODCT also
uses the LO signal to down-convert the PA feedback signal.
An internal phase detector generates a logic pulse. This pulse is proportional to
the phase or frequency difference between the reference frequency and loop pulse
signal.
If the reference frequency is faster than the VCO feedback frequency, the PLL IC
outputs an up signal. If the reference frequency is slower than the VCO feedback
frequency, the PLL IC outputs a down signal. The synthesizer uses these pulses as
correction signals and feed them to a charge pump circuit.
The charge pump circuit consists of ve transistors and associated biasing
components. This circuit generates the correction signal. The correction signal
moves up or down in response to phase detector output pulses. The correction
6 8 P 8 1 0 9 5 E02- D
11/9/2000
3-9
signal passes through the low-pass loop lter. The signal then enters the 970 MHz
Voltage Controlled Oscillator (VCO) circuit.
Regulator Circuitry
The voltage regulator generates three regulated voltages: +3 Vdc, +5 Vdc and
+11.7 Vdc. The regulator obtains input voltages from the +3.3 Vdc and +14.2 Vdc
backplane voltages. The regulated voltages power various ICs and RF devices in
the Exciter.
3-10
68P81095E02- D 11/9/200 0
Exciter
800 MHz Functional
Block Diagram
970 MHZ
(1025 MHZ)
VCO CIRCUITRY
EXCITER IC CIRCUITRY
TRANLIN IC CIRCUITRY
RF FEEDBACK
FROM PA MODULE
+10 V
SUPER
FILTER
DIFFERENTIAL
TISIC DATA & CLOCK
IFOUT
BPF
TRANLIN IC
EXCITER IC
IFIN
237 MHZ
(180.6 MHZ)
VCO
CIRCUITRY
CONTROL VOLTAGE
(+2.5 TO +7.5 VDC)
2ND LO
INJECTION
CIRCUITRY
1ST LO
INJECTION
CIRCUITRY
OSCILLATOR
BUFFER
AMP
VCO FEEDBACK
OSCILLATOR
BUFFER
AMP
SYNTHESIZER
CIRCUITRY
REGULATOR
CIRCUITRY
CHIP
SELECT
+14.2 V
FROM
BACKPLANE
CHIP SELECT
DECODE
CIRCUITRY
CHIP
SELECT
+10 V
REGULATOR
(U3702)
MEMORY
+10 V
SOURCE
2.1 MHZ
BUFFER
ADDRESS BUS
FROM CONTROL
MODULE
CHARGE
PUMP
LOW-PASS
LOOP
FILTER
+11.8 V
SOURCE
+11.8 V
REGULATOR
BOARD SELECT
DECODE
CIRCUITRY
PHASE
LOCKED
LOOP
RIN
IC
FIN
VARIOUS
SIGNALS
TO MONITOR
A/D
CONVERTER
+5 V
REGULATOR
VCO
FEEDBACK
FILTER
ANALOG
+5 V SOURCE
SPI BUS
TO/FROM CONTROL
MODULE
LINEAR RF AMPLIFIER
CIRCUITRY
RF OUTPUT
TO PA MODULE
BPF
EBTS283
101597JNM
NOTE: Where two frequencies are given, frequency without parentheses applies to 800 MHz BR only and frequency with parentheses applies to 900 MHz BR only.
Figure:3-4
6 8 P 8 1 0 95E02- D
4/1/2000
3-11
Exciter
Exciter
Functional Block Diagram
Model TLN3428
RF FEEDBACK
FROM PA MODULE
TRANLIN IC
CIRCUITRY
RESET
RESET FROM
BRC MODULE
POWER
CONTROL
BAND-PASS
FILTER
IFOUT
TRANLIN IC
(U3600)
EXCITER IC
CIRCUITRY
IFIN
SPI BUS
TO/FROM
BRC MODULE
RF FEEDBACK
FOR AGC DIFF AMP
700 MHZ
VCO CIRCUITRY
EXCITER IC
(U3500)
+10 V
SUPER
FILTER
(Q3300)
+10 V
SUPER
FILTER
(Q3200)
1ST LO
INJECTION
CIRCUITRY
(L3201, C3206)
FREQUENCY
DOUBLER
(U4100, T4100,
CR4100)
CONTROL VOLTAGE
(+2.5 TO +7.5 VDC)
OSCILLATOR
(Q3301)
VCO FEEDBACK
CONTROL VOLTAGE
(+2.5 TO +7.5 VDC)
2ND LO
INJECTION
CIRCUITRY
(C4104, R3513)
REGULATOR
CIRCUITRY
+14.2 V
FROM
BACKPLANE
+10 V
REGULATOR
(U3702)
OSCILLATOR
(Q3201)
+10 V
SOURCE
SYNTHESIZER
CIRCUITRY
+11.8 V
REGULATOR
(U3701)
+11.8 V
SOURCE
CHIP SELECT
+5 V
REGULATOR
(U3703)
LO-PASS
LOOP
FILTER
(U3401)
ANALOG
+5 V SOURCE
REFERENCE
BUFFER
(Q3401)
PHASE
LOCKED
LOOP IC
(U3400)
RIN
CHARGE
PUMP
(Q3404, Q3405,
Q3406, Q3407,
Q3408)
CHIP SELECT
DECODE
CIRCUITRY
(U3000)
ADDRESS BUS
FROM BRC
2.1 MHZ
CHIP SELECT
CHIP SELECT
CHIP SELECT
MEMORY
(U3006)
VCO
FEEDBACK
FILTER
(U3400)
AGC CIRCUITRY
CHIP SELECT
BOARD SELECT
DECODE
CIRCUITRY
(U3000)
VARIOUS
SIGNALS
TO MONITOR
SPI BUS
TO/FROM BRC
DIFF AMP
(U3801,
U3802)
A/D
CONVERTER
(U3100)
OPEN LOOP
ALARM
TO A/D
FIN
EXTERNAL
2.1 MHZ
REFERENCE
INTEGRATION/ATTN DRIVER
LINEAR RF AMPLIFIER
CIRCUITRY
RF FEEDBACK
FOR AGC
DIFF AMP
ATTENUATOR
IMAGE FILTER
(FL4000, FL4001
CR4000, CR4002)
RF OUTPUT
TO PA MODULE
AMP 4
(Q4002, Q4003)
Figure:3-5
3-12
AMP 3
(Q4200, Q4201)
AMP 2
(Q3902, Q3903)
AMP 1
(Q3900, Q3901)
4/ 1/ 2000
3
Exciter
800 MHz QUAD ChannelFunctional Block
970 MHZ
(1025 MHZ)
VCO CIRCUITRY
EXCITER IC CIRCUITRY
TRANLIN IC CIRCUITRY
RF FEEDBACK
FROM PA MODULE
+10 V
SUPER
FILTER
DIFFERENTIAL
TISIC DATA & CLOCK
IFOUT
BPF
TRANLIN IC
EXCITER IC
IFIN
237 MHZ
(180.6 MHZ)
VCO
CIRCUITRY
CONTROL VOLTAGE
(+2.5 TO +7.5 VDC)
2ND LO
INJECTION
CIRCUITRY
1ST LO
INJECTION
CIRCUITRY
OSCILLATOR
BUFFER
AMP
!
D
E
G
N
A
CH
BE PS
T -U
S
MU ARK
E
M
R
U EE
T
C
S
I
P
SYNTHESIZER
CIRCUITRY
REGULATOR
CIRCUITRY
OSCILLATOR
BUFFER
AMP
CHIP
SELECT
+14.2 V
FROM
BACKPLANE
CHIP SELECT
DECODE
CIRCUITRY
CHIP
SELECT
+10 V
REGULATOR
(U3702)
MEMORY
+10 V
SOURCE
VARIOUS
SIGNALS
TO MONITOR
A/D
CONVERTER
+5 V
REGULATOR
SPI BUS
TO/FROM CONTROL
MODULE
S
I
TH
PHASE
LOCKED
LOOP
RIN
IC
CHARGE
PUMP
LOW-PASS
LOOP
FILTER
+11.8 V
SOURCE
+11.8 V
REGULATOR
BOARD SELECT
DECODE
CIRCUITRY
2.1 MHZ
BUFFER
ADDRESS BUS
FROM CONTROL
MODULE
VCO FEEDBACK
ANALOG
+5 V SOURCE
FIN
VCO
FEEDBACK
FILTER
LINEAR RF AMPLIFIER
CIRCUITRY
RF OUTPUT
TO PA MODULE
BPF
EBTS283
101597JNM
NOTE: Where two frequencies are given, frequency without parentheses applies to 800 MHz BR only and frequency with parentheses applies to 900 MHz BR only.
Figure:3-6
6 8 P 8 1 0 95E02- D
11/10/2000
3-13
68 P 8 1 0 95E02- D
11/10/2000
3-14
4 Power Amplifier
Overview
This section provides technical information for the Power Amplier (PA). Table
4-1 describes covered topics.
Table 4-1
Chapter Topics
Chapter
Page
Description
4-2
4-15
4-16
4-17
4-18
4-19
Kit Number
TLF2020
CLF1772
TLN3335
CLF1771
CLN1355
CLN7125
TLN3426
TTG1000
CLF1499
CLF1400
Description
6 8 P 8 1 0 9 9 E10 D
11/9/2000
4-1
y
40W, 800 MHz TLF2020 (TTF1580); 70W, 800 MHz TLN3335 (CTF1040); 60W, 900 MHz CLN1355 (CLF1300); 40W, 1500 MHz
TLN3426 (TLN3426); 800 MHz QUAD CLF1400 (CLF1400)
4-2
68P81099E10 D 11/9/200 0
y
40W, 800 MHz TLF2020 (TTF1580); 70W, 800 MHz TLN3335 (CTF1040); 60W, 900 MHz CLN1355 (CLF1300); 40W, 1500 MHz
TLN3426 (TLN3426); 800 MHz QUAD CLF1400 (CLF1400)
Figure:4-1
6 8 P 8 1 0 9 9 E10 D
11/9/2000
4-3
y
40W, 800 MHz TLF2020 (TTF1580); 70W, 800 MHz TLN3335 (CTF1040); 60W, 900 MHz CLN1355 (CLF1300); 40W, 1500 MHz
TLN3426 (TLN3426); 800 MHz QUAD CLF1400 (CLF1400)
Figure:4-2
4-4
68P81099E10 D 11/9/200 0
y
40W, 800 MHz TLF2020 (TTF1580); 70W, 800 MHz TLN3335 (CTF1040); 60W, 900 MHz CLN1355 (CLF1300); 40W, 1500 MHz
TLN3426 (TLN3426); 800 MHz QUAD CLF1400 (CLF1400)
1.5GHZ-Z858
Figure:4-3
6 8 P 8 1 0 9 9 E10 D
11/9/2000
4-5
y
40W, 800 MHz TLF2020 (TTF1580); 70W, 800 MHz TLN3335 (CTF1040); 60W, 900 MHz CLN1355 (CLF1300); 40W, 1500 MHz
TLN3426 (TLN3426); 800 MHz QUAD CLF1400 (CLF1400)
Figure:4-4
4-6
68P81099E10 D 11/9/200 0
y
Theory of Operation
Theory of Operation
Table 4-3 describes the basic functions of the PA circuitry. Figures 4-5, 4-6 and 4-9 show
the functional block diagrams of 40W, 800 MHz PA; 70W, 800 MHz PA and the 800MHz,
Quad PA, respectively. Figures 4-7 shows the functional block diagram of the 60W, 900
MHz PA. Figures 4-8 shows a functional block diagram of the 40W, 1500 MHz PA.
Table 4-3
DC/Metering Board
Description
Serves as the main interface between the PA and the backplane board
Accepts RF input from the Exciter via a blindmate RF connector
Routes the RF input via a 50 stripline to the Linear Driver Module RF
amplifier
Routes the RF feedback from the RF Combiner/Peripheral Module to the
Exciter via a blindmate RF connector
Provides digital alarm and metering information of the PA to the BRC via
the SPI bus
Routes DC power to the fans and PA
Contains one Class AB stage which, in turn, drives a parallel Class AB stage
Amplifies the low-level RF signal ~25 mW average power from the Exciter
via the DC/Metering Board (800MHz and 900MHz)
Amplifies the low-level RF signal ~8 mW average power from the Exciter
via the DC/Metering Board (1500MHz)
Provides an output of:
~10 W (800MHz) average power
~8 W (800MHz Quad) average power
~17 W (900MHz) average power
~16 W (1500MHz) average power
Interconnect Board
(800 MHz only)
RF Splitter/DC board
Contains splitter circuits that split the RF output signal of the LDM to the
three Linear Final Modules (40W, 800MHz)
Contains splitter circuits that split the RF output signal of the LDM to the
six Linear Final Modules (70W, 800MHz and 800MHz Quad)
Contains a Quadrature splitter circuit to split the RF output signal of the
LDM to the two Linear Final Modules (900 MHz and 1500 MHz)
6 8 P 8 1 0 9 9 E10 D
11/9/2000
4-7
y
Theory of Operation
Table 4-3
Circuit
Linear Final Module
(LFM)
Description
Each module contains two Class AB amplifiers in parallel. Each module
amplifies one of three RF signals (~ 8 W average power) from the LDM
(via the Splitter/DC board). Three LFMs provide a sum RF output of
approximately 48 W average power. (40W, 800MHz)
Each module contains two Class AB amplifiers in parallel. Each module
amplifies one of six RF signals (~ 8 W average power) from the LDM (via
the Splitter/DC board). Six LFMs provide a sum RF output of
approximately 97 W average power. (70W, 800MHz)
Each module contains two Class AB amplifiers in parallel. Each module
amplifies one of six RF signals from the LDM (via the Splitter/DC board).
Six LFMs sum to provide the final RF power. (800MHz Quad)
Each module contains two Class AB amplifiers in parallel. Each module
amplifies one of two RF signals (~ 17 W average power) from the LDM
(via the Splitter/DC board). Two LFMs provide a sum RF output of
approximately 75 W average power. (900MHz)
Each module contains two Class AB amplifiers in parallel. Each module
amplifies one of two RF signals (~ 16 W average power) from the LDM
(via the Splitter/DC board). Two LFMs provide a sum RF output of
approximately 28 W average power. (1500MHz)
RF Interconnect Board
(40W, 800 MHz PA only)
Combiner Board
(70W, 800 MHz PA and
800MHz Quad only)
RF Combiner/Peripheral
Module
Contains a combiner circuit that combines the three RF signals from the RF
Interconnect Board (40W PA) or the Combiner Board (70W PA and Quad
PA). It routes the combined RF signal through a circulator and a Low Pass
Filter. The final output signal is routed to the blindmate RF connector (800
MHz)
Contains a Quadrature combiner circuit to combine the RF signal from the
two LFMs. It routes the combined RF signal through a circulator and a Low
Pass Filter. The output signal is routed to the blindmate RF connector (900
MHz and 1500 MHz)
Contains an RF coupler that provides an RF feedback signal to the Exciter
via a blindmate RF connector. Also contains a forward and reverse power
detector for alarm and power monitoring purposes
Fan Assembly
DC/Metering Board(Non-Quad)
The DC/Metering Board provides the interface between the PA and the Base Radio
backplane. The preamplified/modulated RF signal is input directly from the Exciter via
the Base Radio backplane.
The RF input signal is applied to the input of the Linear Driver Module (LDM). The RF
feedback signal is fed back to the Exciter, where it is monitored for errors.
The primary function of the DC/Metering Boards is to monitor proper operation of the PA.
This information is forwarded to the Base Radio Controller (BRC) via the SPI bus. The
alarms diagnostic points monitored by the BRC on the PA include the following:
4-8
Forward power
68P81099E10 D 11/9/200 0
y
Theory of Operation
Reflected power
PA temperature sense
A and B Currents
Fan Sensor
900 MHz
The Linear Driver Module (LDM) amplifies the low-level RF signal from the Exciter.
The LDM consists of a three-stage cascaded amplifier. This output is fed directly to the
RF Splitter/DC Distribution Board.
The RF input signal applied to the LDM has an average power level of approximately 25
mW. The LDM amplifies this signal to an average output level of approximately 17 Watts.
1500 MHz
The Linear Driver Module (LDM) takes the low level RF signal and amplifies it. The
LDM consists of a four stage cascaded amplifier. The RF input signal has an average
power level of 8 mW. The LDM amplifies the input signal to an average output level of
approximately 16 Watts. This output is fed directly to the RF Splitter/DC Distribution
Board.
The current drain of the Power Amplifiers is monitored by the A/D converter on the DC/
Metering board. A voltage signal representative of the LDM current drain is sent to the
BRC. A Power Amplifier alarm is generated if the signal is outside of either the upper or
lower limits.
68 P 8 1 0 9 9 E10 D
11/9/2000
4-9
y
Theory of Operation
4-10
68P81099E10 D 11/9/200 0
y
Theory of Operation
1500 MHz
The two RF signals from the outputs of the RF Splitter are input directly into the Linear
Final Module (LFM) for final amplification. Each LFM contains dual power amplifiers
that amplify the RF signals to an output equal to approximately 28 Watts average power.
The amplified signal is then sent directly to the RF Combiner circuit for final distribution.
The current drain of the Power Amplifiers is monitored by the A/D converter on the DC/
Metering board. A voltage signal representative of the LFM current drain is sent to the
BRC. A Power Amplifier alarm is generated if the signal is outside of either the upper or
lower limits.
RF Combiner/Peripheral Module
800 MHz and 800MHz Quad
This module consists of two portions: an RF combiner and a peripheral module. The RF
Combiner portion of the module combines the three RF signals from the RF Interconnect
Board (40W PA) or the Combiner Board (70W PA) into a single signal using a Wilkinson
coupler arrangement.
Following the combiner circuit, the single combined RF signal is then passed through a
directional coupler which derives a signal sample of the LFM RF power output. Via the
coupler, a sample of the RF output signal is fed to the Exciter as a feedback signal.
Following the coupler, the power output signal is passed through a circulator, which
protects the PA in the event of high reflected power.
The peripheral portion of the module provides a power monitor circuit that monitors the
forward and reflected power of the output signal. This circuit furnishes the A/D converter
on the DC/Metering Board with input signals representative of the forward and reflected
power levels.
For forward power, a signal representative of the measured value is sent to the BRC via
the SPI bus. The BRC determines if this level is within tolerance of the programmed
forward power level. If the level is not within parameters, the BRC will issue a warning to
the site controller which, in turn, will shut down the Exciter if required.
Reflected power is monitored in the same manner. The BRC uses the reflected power to
calculate the voltage standing wave ratio (VSWR). If the VSWR is determined to be
excessive, the forward power is rolled back. . If it is extremely excessive, the BRC issues
a shut-down command to the Exciter.
6 8 P 8 1 0 9 9 E10 D
11/9/2000
4-11
y
Theory of Operation
4-12
68P81099E10 D 11/9/200 0
y
Theory of Operation
Fan Module
The PA contains a fan assembly to maintain normal operating temperature through the use
of a cool air intake. The fan assembly consists of three individual fans in which airflow is
directed across the PA heatsink.
The current draw of the fans is monitored by the DC/Metering Board. A voltage
representative of the current draw is monitored by the BRC. The BRC flags the iSC if an
alarm is triggered. The PA LED on the front panel of the BRC also lights, however the PA
does not shut down.
6 8 P 8 1 0 9 9 E10 D
11/9/2000
4-13
4-14
68P81099E10 D 11/9/200 0
4
40W, 800 MHz Power Amplifier TLF2020 (TTF1580)
Functional Block Diagram
INTERCONNECT
BOARD
LINEAR FINAL
MODULES
RF
INTERCONNECT
BOARD
STAGE
1
RF INPUT
CLASS AB
STAGE 2
CLASS AB
DC
FILTER
CLK/DATA
+28 VDC
50 OHM
LOAD
CHIP SELECT
DECODE
CIRCUITRY
CHIP SELECT
MEMORY
50 OHM
LOAD
SPI BUS
TO/FROM BRC
CHIP
SELECT
ADDRESS BUS
FROM BRC
FAN ASSEMBLY
FAN SENSE
BOARD SELECT
DECODE
CIRCUITRY
A/D
CONVERTER
PA TEMP SENSE
FWD PWR
REF PWR
RF COMBINER/
PERIPHERAL MODULE
TEMPERATURE
SENSOR
LOW-PASS
FILTER
50 OHM
LOAD
RF OUT
TO ANTENNA
STAGE 3
CLASS AB
50 OHM
LOAD
CIRCULATOR
50 OHM
LOAD
RF FEEDBACK
TO EXCITER
MODULE
EBTS611
051398LLN
Figure:4-5
6 8 P 8 1 0 95E02- D
4/1/2000
4-15
Power Amplifier
LINEAR FINAL
MODULES
COMBINER
BOARD
50 OHM
LOAD
INTERCONNECT
BOARD
STAGE
1
RF INPUT
CLASS AB
50 OHM
LOAD
DC
FILTER
CLK/DATA
50 OHM
LOAD
50 OHM
LOAD
STAGE 2
CLASS AB
CHIP SELECT
DECODE
CIRCUITRY
50 OHM
LOAD
MEMORY
CHIP SELECT
SPI BUS
TO/FROM BRC
+28 VDC
CHIP
SELECT
ADDRESS BUS
FROM BRC
FAN ASSEMBLY
FAN SENSE
A/D
CONVERTER
50 OHM
LOAD
BOARD SELECT
DECODE
CIRCUITRY
PA TEMP SENSE
FWD PWR
REF PWR
50 OHM
LOAD
RF COMBINER/
PERIPHERAL MODULE
TEMPERATURE
SENSOR
50 OHM
LOAD
LOW-PASS
FILTER
RF OUT
TO ANTENNA
50 OHM
LOAD
RF FEEDBACK
TO EXCITER
MODULE
Figure:4-6
4-16
50 OHM
LOAD
50 OHM
LOAD
CIRCULATOR
STAGE 3
CLASS AB
EBTS417
120497JNM
4/ 1/ 2000
STAGE
1
RF INPUT
CLASS A
RF SPLITTER/
DC DISTRIBUTION BOARD
STAGE
2
STAGE
3
CLASS AB
CLASS AB
50 OHM
LOAD
CLK/DATA
CHIP SELECT
DECODE
CIRCUITRY
CHIP SELECT
MEMORY
50 OHM
LOAD
SPI BUS
TO/FROM BRC
CHIP
SELECT
ADDRESS BUS
FROM BRC
FAN ASSEMBLY
FAN SENSE
BOARD SELECT
DECODE
CIRCUITRY
A/D
CONVERTER
PA TEMP SENSE
FWD PWR
REF PWR
TEMPERATURE
SENSOR
LOW-PASS
FILTER
50 OHM
LOAD
RF OUT
TO ANTENNA
50 OHM
LOAD
RF COMBINER/
PERIPHERAL MODULE
50 OHM
LOAD
CIRCULATOR
RF FEEDBACK
TO EXCITER
MODULE
EBTS326
011497JNM
Figure:4-7
6 8 P 8 1 0 95E02- D
4/1/2000
4-17
Power Amplifier
Power Amplifier
Functional Block Diagram
Model TLN3426
STAGE
1
RF INPUT
STAGE
2
STAGE
3
CLASS AB
CLASS AB
CHIP SELECT
(Q5433)
50 OHM
LOAD
CHIP SELECT
DECODE
CIRCUITRY
(U5000)
CLASS AB
50 OHM
LOAD
MEMORY
(U5004)
(Q5433)
50 OHM
LOAD
SPI BUS
TO/FROM BRC
STAGE
4
CLASS A
RF SPLITTER/
DC DISTRIBUTION BOARD
TLG4023
CHIP
SELECT
ADDRESS BUS
FROM BRC
FAN ASSEMBLY
BOARD SELECT
DECODE
CIRCUITRY
(U5000)
A/D
CONVERTER
(U5100)
PA TEMP SENSE
FAN
FAN
FAN
(Q5417)
FWD PWR
REF PWR
(Q5417)
50 OHM
LOAD
RF OUT
TO ANTENNA
RF COMBINER/
PERIPHERAL MODULE
TLG4022
50 OHM
LOAD
TEMPERATURE
SENSOR
(RT5401)
LOW-PASS
FILTER
50 OHM
LOAD
CIRCULATOR
Figure:4-8
4-18
50 OHM
LOAD
RF FEEDBACK
TO EXCITER
MODULE
Power
Amplifier
4/ 1/ 2000
4
800 MHz QUAD Carrier Power Amplifier
Functional Block Diagram
LINEAR FINAL
MODULES
COMBINER
BOARD
50 OHM
LOAD
INTERCONNECT
BOARD
STAGE
1
RF INPUT
CLASS AB
50 OHM
LOAD
DC
FILTER
CLK/DATA
50 OHM
LOAD
50 OHM
LOAD
STAGE 2
CLASS AB
CHIP SELECT
DECODE
CIRCUITRY
50 OHM
LOAD
MEMORY
CHIP SELECT
SPI BUS
TO/FROM BRC
+28 VDC
CHIP
SELECT
ADDRESS BUS
FROM BRC
FAN ASSEMBLY
FAN SENSE
A/D
CONVERTER
50 OHM
LOAD
BOARD SELECT
DECODE
CIRCUITRY
PA TEMP SENSE
FWD PWR
REF PWR
50 OHM
LOAD
RF COMBINER/
PERIPHERAL MODULE
TEMPERATURE
SENSOR
50 OHM
LOAD
LOW-PASS
FILTER
RF OUT
TO ANTENNA
50 OHM
LOAD
50 OHM
LOAD
CIRCULATOR
STAGE 3
CLASS AB
RF FEEDBACK
TO EXCITER
MODULE
Figure:4-9
6 8 P 8 1 0 95E02- D
11/9//2000
EBTS417
120497JNM
4-19
Power Amplifier
4-20
11/ 9/ / 2000
5 DC Power Supply
Overview
This section provides technical information for the DC Power Supply (PS). Table
5-1 describes covered topics.
Table 5-1
Chapter Topics
Chapter
Page
Description
5-22
5-29
5-30
5-31
Description
Kit Number
TLN3338
CPN1027
CLN1498
CLF1550
6 8 P 8 1 0 9 5 E02- D
11/9/2000
5-21
LED
Green
Red
Indications
Solid (on)
Off
Solid (on)
Off
Performance Specifications
Table 5-4 lists the specications for the DC Power Supply.
5-22
68P81095E02- D 4/16/9 9
Figure:5-1
DC Power Supply
Table 5-4
Description
Operating Temperature
Input Voltage
41 to 60 Vdc
Input Polarity
Startup Voltage
43 Vdc (minimum)
Input Current
6 8 P 8 1 0 9 5 E02- D
11/9/2000
5-23
Table 5-4
Output Ripple
Value or Range
All outputs 50mV p-p (measured with
20 MHz BW oscilloscope at 25C)
High Frequency individual harmonic voltage
limits (10kHz to 100MHz) are:
28.6 Vdc
1.5 mV p-p
14.2 Vdc
3.0 mV p-p
5.1 Vdc
5.0 mV p-p
Theory of Operation
Table 5-5 briey describes the basic DC Power Supply circuitry. Figure 5-3 shows
the functional block diagrams for the DC Power Supply.
Table 5-5
Circuit
5-24
Description
Input Circuit
Routes input current from the DC power input cable through the
high current printed circuit edge connector, EMI lter, panel mounted
combination circuit breaker, and on/off switch
Startup Inverter
Circuitry
Temperature Protection
The Power Supply contains a built-in cooling fan that runs whenever
the supply is powered on. The supply shuts down if the temperature
exceeds a preset threshold
+5 Vdc Secondary
Converter Circuitry
Clock Generator
Circuitry
Generates the 267 kHz and 133 kHz clock signals used by the pulse
width modulators in the four inverter circuits
Address Decode,
Memory, & A/D
Converter
Serves as the main interface between A/D on the Power Supply and
the BRC via the SPI bus
68P81095E02- D 4/16/9 9
LED
Green
Red
Indications
Solid (on)
Off
Solid (on)
Off
Performance Specifications
Table 5-7 lists the specications for the QUAD Channel DC Power Supply.
68 P 8 1 0 9 5 E02- D
11/9/2000
5-25
Figure:5-2
Table 5-7
Description
Operating Temperature
Input Voltage
41 to 60 Vdc
Input Polarity
Startup Voltage
43 Vdc (minimum)
Input Current
5-26
68P81095E02- D 4/16/99
Table 5-7
Output Ripple
Value or Range
All outputs 150mV p-p (measured with
20 MHz BW oscilloscope at 25C)
High Frequency individual harmonic voltage
limits (10kHz to 100MHz) are:
28.6 Vdc
1.5 mV p-p
14.2 Vdc
3.0 mV p-p
3.3 Vdc
5.0 mV p-p
Theory of Operation
Table 5-8 briey describes the basic DC Power Supply circuitry. Figure 5-5 shows
the functional block diagrams for the DC Power Supply.
Table 5-8
Circuit
6 8 P 8 1 0 9 5 E02- D
11/9/2000
Description
Input Circuit
Routes input current from the DC power input cable through the
high current printed circuit edge connector, EMI lter, panel mounted
combination circuit breaker, and on/off switch
Startup Inverter
Circuitry
Temperature Protection
The Power Supply contains a built-in cooling fan that runs whenever
the supply is powered on. The supply shuts down if the temperature
exceeds a preset threshold
Clock Generator
Circuitry
Generates the 267 kHz and 133 kHz clock signals used by the pulse
width modulators in the four inverter circuits
Address Decode,
Memory, & A/D
Converter
Serves as the main interface between A/D on the Power Supply and
the BRC via the SPI bus
5-27
5-28
68P81095E02- D 11/9/200 0
MAIN ISOLATION
TRANSFORMER
MOD FAIL
SOFTSTART
CIRCUITRY
+28 V BULK TO
DIAGNOSTICS
CIRCUITRY
SHUTDOWN
PULSE
WIDTH
MODULATOR
3
4
POWER FET
SWITCHES
TRANSISTOR
DRIVERS
P/O
BACKPLANE
CONNECTOR
+28.6 VDC
TO
STATION
MODULES
VIA
BACKPLANE
+28.6 VDC
FILTERING
CIRCUITRY
14
15
VCC
267 KHZ
133 KHZ
133 KHZ
+28.6 V OVERVOLTAGE
DETECT
VCC
REF
FRONT PANEL
ON / OFF
SWITCH
CURRENT
DETECT
OVERCURRENT
DETECT
REF
FILTER
CIRCUITRY
EXTERNAL
DC INPUT
41-60 VDC
+28 V BULK
POWER FET
SWITCH
VCC
P/O
BACKPLANE
CONNECTOR
+14.2V
+14.2V DC
TO
STATION
MODULES
VIA
BACKPLANE
16
17
FILTER
CIRCUITRY
22
23
133 KHZ
VCC
PULSE
WIDTH
MODULATOR
STARTUP ISOLATION
TRANSFORMER
FET
DRIVER
FET
+ 14.2V OVERCURRENT
DETECT
OVERVOLTAGE
DETECT
PULSE
WIDTH
MODULATOR
TRANSISTOR
SWITCH
SURGE CURRENT
DELAY
CROWBAR
CIRCUIT
REF
133 KHZ
REF
BULK DETECT
TO
DIAGNOSTICS
CIRCUITRY
+ 28V BULK
P/O
BACKPLANE
CONNECTOR
133 KHZ
POWER FET
SWITCH
VCC
FILTER
CIRCUITRY
VCC
267 KHZ
133 KHZ
+5.1 V DC
TO
STATION
MODULES
VIA
BACKPLANE
24
25
30
31
267 KHZ
CLOCK
GENERATOR
CIRCUITRY
+5.1 V
133 KHZ
PULSE
WIDTH
MODULATOR
FET
DRIVER
133 KHZ
FET
+ 5V OVERCURRENT
DETECT
OVERVOLTAGE
DETECT
REF
SURGE CURRENT
DELAY
REF
CROWBAR
CIRCUIT
267 KHZ
REF
EBTS323
011497JNM
Figure:5-3
6 8 P 8 1 0 95E02- D
11/9/2000
5-29
DC Power Supply
DC Power Supply
REF
DIAGNOSTICS CIRCUITRY
MODULE
FAIL
(RED)
REF
INPUT GOOD
(GREEN)
MOD FAIL
BULK DETECT
FROM STARTUP
INVERTER
CIRCUITRY
INPUT FAIL
REF
HEATSINK STATUS
DETECT
HEATSINK DIAG
REF
VBAT DIAG
HI-TEMP
DETECT
(FOR AC ONLY)
FROM BATTERY
CHARGER/REVERT
CIRCUITRY
REF
BAT TEMP
SPI BUS
A/D
CONVERTER
J300
REF
COOLING
FAN
SPI BUS
TO/FROM
STATION CONTROL
MODULE
+5.1 V
THERMISTOR
MOUNTED ON
HEATSINK
+14.2V DIAG
FROM
DETECT
CIRCUITRY
+5.1 V DIAG
+28.6 V DIAG
FROM
STATION
CONTROL
BOARD
ADDRESS
DECODE
CIRCUITRY
ENABLE
ENABLE
EBTS324
012097JNM
Figure:5-4
5-30
11/ 9/ 2000
DC Power Supply
MAIN ISOLATION
TRANSFORMER
MOD FAIL
SOFTSTART
CIRCUITRY
+28 V BULK TO
DIAGNOSTICS
CIRCUITRY
SHUTDOWN
PULSE
WIDTH
MODULATOR
3
4
POWER FET
SWITCHES
TRANSISTOR
DRIVERS
P/O
BACKPLANE
CONNECTOR
+28.6 VDC
TO
STATION
MODULES
VIA
BACKPLANE
+28.6 VDC
FILTERING
CIRCUITRY
14
15
VCC
267 KHZ
133 KHZ
133 KHZ
+28.6 V OVERVOLTAGE
DETECT
VCC
REF
FRONT PANEL
ON / OFF
SWITCH
CURRENT
DETECT
OVERCURRENT
DETECT
REF
FILTER
CIRCUITRY
EXTERNAL
DC INPUT
41-60 VDC
+28 V BULK
POWER FET
SWITCH
VCC
P/O
BACKPLANE
CONNECTOR
+14.2V
+14.2V DC
TO
STATION
MODULES
VIA
BACKPLANE
16
17
FILTER
CIRCUITRY
22
23
133 KHZ
VCC
PULSE
WIDTH
MODULATOR
STARTUP ISOLATION
TRANSFORMER
FET
DRIVER
FET
+ 14.2V OVERCURRENT
DETECT
OVERVOLTAGE
DETECT
PULSE
WIDTH
MODULATOR
TRANSISTOR
SWITCH
SURGE CURRENT
DELAY
CROWBAR
CIRCUIT
REF
133 KHZ
REF
BULK DETECT
TO
DIAGNOSTICS
CIRCUITRY
+ 28V BULK
P/O
BACKPLANE
CONNECTOR
133 KHZ
POWER FET
SWITCH
VCC
VCC
267 KHZ
133 KHZ
+3.3 V DC
TO
STATION
MODULES
VIA
BACKPLANE
24
25
30
31
267 KHZ
CLOCK
GENERATOR
CIRCUITRY
+3.3 V
FILTER
CIRCUITRY
133 KHZ
PULSE
WIDTH
MODULATOR
FET
DRIVER
133 KHZ
FET
+ 3.3V OVERCURRENT
DETECT
OVERVOLTAGE
DETECT
REF
SURGE CURRENT
DELAY
REF
CROWBAR
CIRCUIT
267 KHZ
REF
EBTS323Q
101900 spf
Figure:5-5
5-31
11/ 9/ 2000
DC Power Supply
REF
DIAGNOSTICS CIRCUITRY
MODULE
FAIL
(RED)
REF
INPUT GOOD
(GREEN)
MOD FAIL
ULK DETECT
OM STARTUP
INVERTER
CIRCUITRY
INPUT FAIL
REF
HEATSINK STATUS
DETECT
HEATSINK DIAG
REF
VBAT DIAG
HI-TEMP
DETECT
(FOR AC ONLY)
FROM BATTERY
CHARGER/REVERT
CIRCUITRY
REF
BAT TEMP
SPI BUS
A/D
CONVERTER
J300
REF
COOLING
FAN
SPI BUS
TO/FROM
STATION CONTROL
MODULE
+3.3 V
THERMISTOR
MOUNTED ON
HEATSINK
+14.2V DIAG
FROM
DETECT
CIRCUITRY
+3.3 V DIAG
+28.6 V DIAG
ADDRESS
DECODE
CIRCUITRY
ENABLE
ENABLE
EBTS324Q
101900spf
Figure:5-6
5-32
11/ 9/ 2000
6 AC Power Supply
LED
Green
Red
Indications
Solid (on)
Off
Solid (on)
Off
Performance Specifications
Table 6-2 lists the specications for the AC Power Supply.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
6-33
Figure:6-1
Table 6-2
Operating Temperature
Value or Range
-30 to +45 C (no derating)
-30 to +60 C (derating)
Input Voltage
90 to 280 Vac
47 to 63 Hz
Input Current
8.5 A (maximum)
6-34
26 to 32.5 Vdc
68P81095E02- D 4/1/2000
Table 6-2
Value or Range
Output Ripple
28.6 Vdc
1.5 mV p-p
14.2 Vdc
3 mV p-p
5.1 Vdc
5 mV p-p
Theory of Operation
Table 6-3 briey describes the basic AC Power Supply circuitry. Figure 6-2 shows
the functional block diagrams for the AC Power Supply.
Table 6-3
Circuit
Description
Input Conditioning
Circuitry
Start-up Inverter
Circuitry
Temperature Protection
+5 Vdc Secondary
Converter Circuitry
Clock Generator
Circuitry
Generates 267 kHz and 133 kHz clock signals for the pulse width
modulators in the four inverter circuits
Diagnostics Circuitry
Address Decode,
Memory, & A/D
Converter
Serves as the main interface between A/D and D/A on the Power
Supply and the BRC via the SPI bus
Battery Charging/
Revert Circuitry
6 8 P 8 1 0 9 5 E02- D
4/1/2000
6-35
6-36
68P81095E02- D 4/1/2000
6
6
AC Power Supply
MAIN ISOLATION
TRANSFORMER
133 KHZ
133 KHZ
SOFTSTART
CIRCUITRY
SHUTDOWN
MOD FAIL
PULSE
WIDTH
MODULATOR
POWER FET
SWITCHES
TRANSISTOR
DRIVERS
B
D
+28 V BULK TO
DIAGNOSTICS
CIRCUITRY
VCC
267 KHZ
VCC
FILTERING
CIRCUITRY
+28.6 VDC
+28.6 V OVERVOLTAGE
DETECT
REF
FRONT PANEL
ON / OFF
SWITCH
FULL WAVE
BRIDGE
RECTIFIER
67 KHZ
FILTER
CIRCUITRY
PULSE
WIDTH
MODULATOR
TRANSISTOR
DRIVER
+28.6 VDC
TO
STATION
MODULES
VIA
14 BACKPLANE
15
A
REF
FET
SWITCHES
3
4
OVERCURRENT
DETECT
CURRENT
DETECT
TRANSIENT / EMI
PROTECTION
CIRCUITRY
AC INPUT
47 - 60 HZ
90V / 280V AC
P/O
BACKPLANE
CONNECTOR
+ 28V BULK
POWER FET
SWITCH
STARTUP INVERTER CIRCUITRY
VCC
VCC
PULSE
WIDTH
MODULATOR
STARTUP ISOLATION
TRANSFORMER
VCC
PULSE
WIDTH
MODULATOR
+14.2V
FILTER
CIRCUITRY
133 KHZ
VCC
FET
FET
DRIVER
OVERVOLTAGE
DETECT
+ 14.2V OVERCURRENT
DETECT
TRANSISTOR
SWITCH
REF
133 KHZ
CROWBAR
CIRCUIT
REF
SURGE CURRENT
DELAY
+ 28V BULK
133 KHZ
267 KHZ
267 KHZ
+5.1V
FILTER
CIRCUITRY
267 KHZ
VCC
CLOCK
GENERATOR
CIRCUITRY
133 KHZ
+14.2V DC
TO
STATION
MODULES
VIA
22 BACKPLANE
23
REF
BULK DETECT
TO
DIAGNOSTICS
CIRCUITRY
16
17
133 KHZ
PULSE
WIDTH
MODULATOR
VCC
133 KHZ
FET
FET
DRIVER
OVERVOLTAGE
DETECT
+ 5V OVERCURRENT
DETECT
REF
24
25
+5.1V DC
TO
STATION
MODULES
VIA
30 BACKPLANE
31
CROWBAR
CIRCUIT
REF
SURGE CURRENT
DELAY
P/O
BACKPLANE
CONNECTOR
REF
EBTS009
051594JNM
Figure:6-2
6 8 P 8 1 0 95E02- D
4/1/2000
6-37
AC Power Supply
AC Power Supply
BATTERY CHARGING / REVERT CIRCUITRY
SCR
APPROX. 33 V DC
FILTER
CIRCUITRY
POWER FET
SWITCH
FILTERING
CIRCUITRY
BATTERY
REVERT
RELAY
133 KHZ
_
PULSE
WIDTH
MODULATOR
CHARGER OUTPUT
SELECT LINES
SPI BUS
(CLOCK & DATA)
2
D/A
CONVERTER
1 PPS
FROM SCM
STATION
CONTROL
MODULE
FAIL DETECT
FET
DRIVER
RELAY
CONTROL
CIRCUITRY
AC FAIL
STORAGE
BATTERY
VBAT DIAG
TO DIAGNOSTICS
CIRCUITRY
133 KHZ
SHUTDOWN
FROM CLOCK
GENERATOR
CIRCUITRY
SPI BUS
(CLOCK & DATA)
2
DIAGNOSTICS CIRCUITRY
REF
MODULE
FAIL
(RED)
REF
AC ON
(GREEN)
MOD FAIL
BULK DETECT
FROM STARTUP
INVERTER
CIRCUITRY
AC FAIL
REF
RIPPLE
DETECT
CIRCUITRY
+ 28V BULK
FROM MAIN
INVERTER
CIRCUITRY
28 RIPPLE
HEATSINK STATUS
DETECT
HEATSINK DIAG
REF
VBAT DIAG
HI-TEMP
DETECT
REF
FROM BATTERY
CHARGER/REVERT
CIRCUITRY
BAT TEMP
FAN ON
FAN CONTROL
REF
FET
SWITCH
A/D
CONVERTER
SPI BUS
3
SPI BUS
TO/FROM
STATION
CONTROL
MODULE
COOLING
FAN
+5V
THERMISTOR
MOUNTED ON
HEATSINK
FAN FAULT
DETECT
ENABLE
FAN FAIL
+14.2V DIAG
FROM
DETECT
CIRCUITRY
+5.1V DIAG
+28.6V DIAG
FROM
STATION
CONTROL
BOARD
ADDRESS
DECODE
CIRCUITRY
ENABLE
ENABLE
EBTS010
042594JNM
Figure:6-2
6-38
4/ 1/ 2000
7 Receiver
Overview
This section provides technical information for the Receiver (RX). Table 7-1
describes covered topics.
Table 7-1
Chapter Topics
Chapter
Page
Description
7-40
7-47
7-51
7-57
7-58
7-59
Kit Number
CLN1283
CLF1470
CLN1356
CLF1480
TLN3427
CRX1020
CLN1496
CLF1550
Description
6 8 P 8 1 0 9 5 E02- D
4/1/2000
7-39
Figure:7-1
7-40
68P81095E02- D 4/1/2000
receiver slot, the front panel of a 3X receiver reads: INSERT ONLY IN SLOT RX2
WITH BACKPLANE 0183625X 3X RECEIVER .
The two remaining receiver slots are covered with blank panels. A summary of
the Receiver FRUs available for the Base Radio is provided in the chart below.
Table 7-3
Receiver FRUs
Receiver FRUs
Chassis FRUs
3X Receiver:
800 MHz
CLN1283
800 MHz
CLN1282
900 MHz
CLN1356
900 MHz
N/A
Single Receiver:
800 MHz
TLN3336
900 MHz
N/A
TLN3333
900 MHz
N/A
Replacement Compatibility
The 3X Receiver board (CRF6010 or CRF6030) can only be used in receive slot 2
(middle receiver slot) with backplane 0183625X _ _. The backplane connector is
different than the TRF6560 version of the receiver board. This is why there is a
need for a new backplane. The receiver will function only when it is installed in
slot 2. The TRF6560 receiver will not make electrical connection in any slot of the
new backplane. Compatibility between the new and old receiver boards is
summarized in Tables 7-4 and 7-5 for 800 MHz and 900 MHz Base Radios,
respectively.
Table 7-4
TRF6560 Receiver
Compatible
Not compatible
Not compatible
Compatible
Table 7-5
6 8 P 8 1 0 9 5 E02- D
4/1/2000
Compatible
Not compatible
7-41
Diversity Configuration
There is a new software parameter used for diversity purposes with the CLN1283
and CLN1356 3X Receivers. The parameter is the rx_fru_config parameter. The
diversity issues to consider are described in the following paragraph. This
parameter can be accessed through the MMI commands using the Motorola
password. ROMs prior to version R06.06.17 do not support the rx_fru_config
parameter. The ROM version in a base repeater can be checked using the MMI
command ver . If a repeater contains the CRF6010 or CRF6030 receiver, the BRC
board must be populated with a compatible version of ROM. Table 7-6 lists the
ROM compatibilities.
Table 7-6
CRF6010/CRF6030
ROM version R06.03.40
Not compatible
Compatible
Not compatible
Compatible
Not compatible
Compatible
Compatible
Compatible
NOTE
When replacing FRUs, ensure that the ROM version
on the BRC installed in the base radio is compatible
with the ROM version on the Receiver.
NOTE
If downloaded code is used, then the downloaded
code can be used to change the needed parameter (the
rx_fru_config parameter).
7-42
68P81095E02- D 4/1/2000
CAUTION
There will be signicant system degradation if the
rx_fru_config parameter is not properly set in
systems with the CLN1283 or CLN1356 3X receiver
kit.
When modifying a three branch Base Radio to a two branch Base Radio, it is
important to observe all precautionary statements in the previous paragraph.
To modify a three branch Base Radio to a two branch Base Radio:
1.
Disconnect the RF cable from the RX3 connector on the Base Radio.
2.
Connect an SMA male load (Motorola part number 5882106P03) to the RX3
connector on the Base Radio.
The SMA male load is required to limit the amount of radiated emissions.
3.
68 P 8 1 0 9 5 E02- D
4/1/2000
7-43
Remove the SMA male load from the RX3 connector of the Base Radio you
wish to convert from two branch diversity to three branch diversity.
2.
Connect the Receive Antenna #3 RF cable to the RX3 connector on the Base
Radio.
3.
Theory of Operation
The Receiver performs highly selective bandpass ltering and dual down
conversion of the station receive RF signal. A custom Receiver IC outputs the
baseband information in a differential data format and sends it to the BRC.
Table 7-7 lists the Receiver circuitry and Figure 7-4 shows a functional block
diagram for the Receiver.
Table 7-7
Receiver Circuitry
Circuit
Description
Frequency
Synthesizer Circuitry
Receiver Front-End
Circuitry
Custom Receiver IC
Circuitry
Address Decode,
A/D Converter, &
Memory Circuitry
Performs address decoding for board and chip select signal, converts
analog status signals to digital format for use by the BRC. A memory
device holds module specic information.
Accepts +14.2 Vdc input from the backplane interconnect board and
generates two +10 Vdc, a +11.5 Vdc, and two +5 Vdc signals for the
receiver.
7-44
68P81095E02- D 4/1/2000
Correction pulses are generated by the PLL IC, depending on whether the
feedback signal is higher or lower in frequency than the 2.1 MHz reference. The
width of these pulses is dependent on the amount of difference between the
2.1 MHz reference and the VCO feedback.
The up/down pulses are fed to a charge pump circuit that outputs a DC voltage
proportional to the pulse widths. This DC voltage is low-pass ltered and fed to
the VCO circuit as the control voltage. The control voltage is between +2.5 Vdc
and +7.5 Vdc.
The DC control voltage from the synthesizer is fed to the VCO, which generates
the RF signal used to produce the 1st LO injection signal. The VCO responds to
the DC control voltage by generating the appropriate RF signal. This signal is fed
through a buffer to the 1st LO injection amplier. A sample of this signal is
returned to the PLL IC through a buffer to close the VCO feedback loop.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
7-45
Memory Circuitry
The memory circuitry consists of three EEPROMs located on the Receiver. The
BRC performs all memory read and write operations via the SPI bus. Information
stored in this memory device includes the kit number, revision number, module
specic scaling and correction factors, and free form module information
(scratch pad).
7-46
68P81095E02- D 4/1/2000
Figure:7-2
Theory of Operation
The Receiver module performs highly selective bandpass ltering and dual
down-conversion of the station receive RF signal. A custom receiver IC outputs
the baseband information in a differential data format and sends it to the Base
Radio Controller module (BRC).
Table 7-8 lists and describes the Receiver circuitry and Figure 7-5 shows the
functional block diagram.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
7-47
Table 7-8
Receiver Circuit
This Circuit . . .
Frequency
Synthesizer
Circuitry
Receiver Front-End
Circuitry
Custom Receiver IC
Circuitry
Address Decode,
A/D Converter, &
Memory Circuitry
Phase-Locked Loop
The PLL IC receives frequency selection data from the BRC module
microprocessor via the SPI bus. Once programmed, the PLL IC compares a 2.1
MHz reference signal from the BRC with a feedback sample of the VCO output
from its feedback buffer.
Correction pulses are generated by the PLL IC, depending on whether the
feedback signal is higher or lower in frequency than the 2.1 MHz reference. The
width of these pulses is dependent on the amount of difference between the 2.1
MHz reference and the VCO feedback.
The up/down pulses are fed to a charge pump circuit that outputs a dc voltage
proportional to the pulse widths. This dc voltage is low-pass ltered and fed to
the VCO circuit as the control voltage. The control voltage is between +2.5 Vdc
and +7.5 Vdc.
VCO
The dc control voltage from the synthesizer is fed to the VCO, which generates
the RF signal used to produce the 1st LO injection signal. The VCO responds to
the dc control voltage by generating the appropriate RF signal. A sample of this
signal is returned to the PLL IC through a buffer to close the VCO feedback loop.
Most of this signal is fed through a buffer to the doubler .
7-48
68P81095E02- D 4/1/2000
The frequency doubler is used to double the frequency of the RF signal from the
VCO to produce the 1st LO injection signal. This frequency-doubled signal is sent
to the injection amplier to provide the 1st LO injection signal to the mixer in the
receiver front end circuitry.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
7-49
Memory Circuitry
The memory circuitry consists of an EEPROM located on the receiver module.
The BRC module performs all memory read and write operations via the SPI bus.
Information stored in this memory device includes the kit number, revision
number, module specic scaling and correction factors, and free form module
information (scratch pad).
7-50
68P81095E02- D 4/1/2000
S
I
TH
E
R
U
T
C
I
P
Figure:7-3
T
S
MU
BE
!
D
E
G
N
A
CH
6 8 P 8 1 0 9 5 E02- D
4/1/2000
7-51
CAUTION
Improperly setting the rx_fru_config parameter will
cause serious system degradation.
Disconnect the RF cable from the RX3 connector on the Base Radio.
2.
Connect an SMA male load (Motorola part number 5882106P03) to the RX3
connector on the Base Radio.
The SMA male load is required to limit the amount of radiated emissions.
3.
7-52
68P81095E02- D 4/1/2000
Remove the SMA male load from the RX3 connector of the Base Radio that
you wish to convert from two-branch diversity to three-branch diversity.
2.
Connect the Receive Antenna #3 RF cable to the RX3 connector on the Base
Radio.
3.
Theory of Operation
The Receiver performs highly selective bandpass ltering and dual down
conversion of the station receive RF signal. A custom Receiver IC outputs the
baseband information in a differential data format and sends it to the BRC.
Table 7-7 lists the Receiver circuitry. Figure 7-6 shows a functional block diagram
for the Receiver.
Table 7-9
Receiver Circuitry
Circuit
Description
Frequency
Synthesizer Circuitry
Receiver Front-End
Circuitry
Custom Receiver IC
Circuitry
Address Decode,
A/D Converter, &
Memory Circuitry
Accepts +14.2 Vdc input from the backplane interconnect board. Also
generates two +10 Vdc, a +11.5 Vdc, and two +5 Vdc signals for the
receiver.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
7-53
The PLL ICC generates correction pulses, depending on whether the feedback
signal is higher or lower in frequency than the 2.1 MHz reference. The width of
these pulses depends on the amount of difference between the 2.1 MHz reference
and the VCO feedback.
The up/down pulses enter a charge pump circuit. The charge pump outputs a DC
voltage proportional to the pulse widths. After low-pass ltering, this DC voltage
enters the VCO circuit as the control voltage. The control voltage measures
between +2.5 Vdc and +7.5 Vdc.
The DC control voltage from the synthesizer is enters the VCO. The VCO
generates the RF signal that the circuit uses to produce the 1st LO injection signal.
The VCO responds to the DC control voltage by generating the appropriate RF
signal. This signal passes through a buffer to the 1st LO injection amplier. A
sample of this signal returns to the PLL IC through a buffer to close the VCO
feedback loop.
7-54
68P81095E02- D 4/1/2000
Memory Circuitry
The memory circuitry consists of three EEPROMs located on the Receiver. The
BRC performs memory read and write operations via the SPI bus. Information
stored in this memory device includes...
revision number
6 8 P 8 1 0 9 5 E02- D
4/1/2000
7-55
7-56
68P81095E02- D 4/1/2000
7
3X Receiver
Functional Block Diagram
RECEIVER #3 FRONT END CIRCUITRY
RECEIVER #2 FRONT END CIRCUITRY
RECEIVER #1 FRONT END CIRCUITRY
1ST
MIXER
RECEIVE RF
FROM RX ANTENNA
(MULTICOUPLER)
LO-PASS
FILTER
HI-PASS
FILTER
4-POLE
BANDPASS
FILTER
PREAMPLIFIER
CIRCUITRY
4-POLE
BANDPASS
FILTER
SMA-TYPE
CONNECTOR
DIGITAL
ATTENUATOR
CIRCUITRY
AGC
FROM CONTROL
MODULE
3 WAY
SPLITTER
TO RECEIVER #2 MIXER
TO RECEIVER #3 MIXER
REGULATORY
CIRCUITRY
ABACUS #3
MEMORY #3
+10 V
REGULATOR
MEMORY #2
+5 V
REGULATOR
DIGITAL
+5 V
SOURCE
CUSTOM RECEIVER
IC CIRCUITRY
(ABACUS #1 )
CHIP
SELECT
MEMORY #1
CHIP SELECT
DECODE CIRCUITRY
+10 V
REGULATOR
CHIP
SELECT
ADDRESS BUS
FROM CONTROL
MODULE
#3 A/D
CONVERTER
RECEIVER SELECT
DECODE CIRCUITRY
VARIOUS
SIGNALS
TO MONITOR
ABACUS #2
DIFFERENTIAL
DATA
TO CONTROL
MODULE
+10 V
SOURCE
73.35 MHZ
1ST IF
+14.2 V
FROM
BACKPLANE
#2 A/D
CONVERTER
+10 V
REGULATOR
+5 V
REGULATOR
ANALOG
+5 V
SOURCE
DRIVER
CIRCUITRY
#1 A/D
CONVERTER
SPI BUS
TO/FROM CONTROL
MODULE
SECOND
+10 V
SOURCE
SYNTHESIZER
CIRCUITRY
VCO
CIRCUITRY
CHIP
SELECT
BUFFER
RIN
PHASE
LOCKED
LOOP
IC
INJECTION
AMPLIFIER
CUSTOM
RECEIVER
IC
+10 V
SUPER
FILTER
CHARGE
PUMP
LO-PASS
LOOP
FILTER
CONTROL
VOLTAGE
(+2.5 TO +7.5 VDC)
450 KHZ
FILTER
CIRCUITRY
SERIAL BUS
TO/FROM CONTROL
MODULE
14.4 MHZ
TIMING
CIRCUITRY
VCO
OSCILLATOR
2ND LO
VCO
BUFFER
AMP
(NOTE)
FIN
VCO
FEEDBACK
BUFFER
VCO FEEDBACK
VCO
FEEDBACK
EBTS293
120597JNM
NOTE: 14.4 MHz TIMING CIRCUITRY AND 2ND LO VCO PRESENT ONLY ON ABACUS #2.
FUNCTIONS ARE SHARED FOR ALL THREE ABACUS SECTIONS.
Figure:7-4
6 8 P 8 1 0 95E02- D
4/1/2000
7-57
Receiver
7
Receiver
Functional Block Diagram
Model TLN3427
RECEIVE RF
FROM RX ANTENNA
(MULTICOUPLER)
PRESELECTOR
FILTER
(FL2000)
PREAMPLIFIER
CIRCUITRY
(Q2030, Q2031)
BUFFER
AMP
(Q2100)
IMAGE
FILTER
CIRCUITRY
(FL2070)
1ST LO
INJ AMP
CIRCUITRY
(Q2302, Q2303,
FL2300)
CHIP SELECT
DECODE CIRCUITRY
(U2804)
CHIP SELECT
ADDRESS BUS
FROM BRC
MODULE
REGULATORY
CIRCUITRY
EEPROM
MEMORY
(U2601)
VARIOUS
SIGNALS
TO MONITOR
+5 V
REGULATOR
(U2700)
LINE
DRIVER
(U2805)
DIGITAL
ATTENUATOR
CIRCUITRY
(U2100)
BUFFER
AMP
(Q2300)
DOUBLER
(Q2301)
DIGITAL
+5 V
SOURCE
CUSTOM
RECEIVER IC
CIRCUITRY
DIFFERENTIAL
DATA (DSP BUS)
TO BRC
MODULE
+10 V
SOURCE
+14.2 V
FROM
BACKPLANE
A/D
CONVERTER
(U2600)
AGC
FROM BRC
MODULE
73.35 MHZ
1ST IF
+10 V
REGULATOR
(U2703)
CHIP SELECT
BOARD SELECT
DECODE CIRCUITRY
(U2804)
4-POLE
BANDPASS
FILTER
(Y2101)
4-POLE
BANDPASS
FILTER
(Y2100)
+10 V
REGULATOR
(U2702)
+5 V
REGULATOR
(U2701)
DRIVER
CIRCUITRY
(U2501)
ANALOG
+5 V
SOURCE
450 KHZ
FILTER
CIRCUITRY
VCO
CIRCUITRY
CHIP
SELECT
REFERENCE
BUFFER
(Q2402)
14.4 MHZ
TIMING
CIRCUITRY
+10 V
SYNTHESIZER
CIRCUITRY
CUSTOM
RECEIVER IC
(U2500)
SECOND
+10 V
SOURCE
SPI BUS
TO/FROM BRC
MODULE
RIN
PHASE
LOCKED
LOOP IC
(U2401)
SUPER
FILTER
(Q2280)
CHARGE PUMP
(Q2405, Q2406,
Q2407, Q2408,
Q2409)
LOW-PASS
LOOP
FILTER
(U2403)
CONTROL
VOLTAGE
(+2.5 TO +7.5 VDC)
SERIAL BUS
TO/FROM BRC
MODULE
2ND LO
TANK
CIRCUITRY
OSCILLATOR
(U2200)
FIN
VCO
FEEDBACK
BUFFER
(Q2401)
VCO FEEDBACK
VCO
FEEDBACK
Figure:7-5
7-58
4/ 1/ 2000
7
QUAD Receiver
Functional Block Diagram
RECEIVER #3 FRONT END CIRCUITRY
RECEIVER #2 FRONT END CIRCUITRY
RECEIVER #1 FRONT END CIRCUITRY
1ST
MIXER
RECEIVE RF
FROM RX ANTENNA
(MULTICOUPLER)
LO-PASS
FILTER
HI-PASS
FILTER
!
D
E
G
N
A
CH
4-POLE
BANDPASS
FILTER
PREAMPLIFIER
CIRCUITRY
SMA-TYPE
CONNECTOR
DIGITAL
ATTENUATOR
CIRCUITRY
AGC
FROM CONTROL
MODULE
3 WAY
SPLITTER
TO RECEIVER #2 MIXER
BE
4-POLE
BANDPASS
FILTER
TO RECEIVER #3 MIXER
REGULATORY
CIRCUITRY
T
S
U
M
MEMORY #3
+10 V
REGULATOR
MEMORY #2
CHIP
SELECT
MEMORY #1
CHIP SELECT
DECODE CIRCUITRY
#3 A/D
CONVERTER
RECEIVER SELECT
DECODE CIRCUITRY
VARIOUS
SIGNALS
TO MONITOR
#2 A/D
CONVERTER
#1 A/D
CONVERTER
SPI BUS
TO/FROM CONTROL
MODULE
SYNTHESIZER
CIRCUITRY
CHIP
SELECT
BUFFER
RIN
PHASE
LOCKED
LOOP
IC
E
R
U
T
C
I
P
S
I
TH
CHARGE
PUMP
LO-PASS
LOOP
FILTER
ABACUS #2
CUSTOM RECEIVER
IC CIRCUITRY
(ABACUS #1 )
+10 V
REGULATOR
CHIP
SELECT
ADDRESS BUS
FROM CONTROL
MODULE
+5 V
REGULATOR
ABACUS #3
DIGITAL
+5 V
SOURCE
DIFFERENTIAL
DATA
TO CONTROL
MODULE
+10 V
SOURCE
73.35 MHZ
1ST IF
+14.2 V
FROM
BACKPLANE
+10 V
REGULATOR
VCO
CIRCUITRY
+5 V
REGULATOR
SECOND
+10 V
SOURCE
ANALOG
+5 V
SOURCE
INJECTION
AMPLIFIER
450 KHZ
FILTER
CIRCUITRY
CUSTOM
RECEIVER
IC
+10 V
SUPER
FILTER
CONTROL
VOLTAGE
(+2.5 TO +7.5 VDC)
DRIVER
CIRCUITRY
SERIAL BUS
TO/FROM CONTROL
MODULE
14.4 MHZ
TIMING
CIRCUITRY
VCO
OSCILLATOR
2ND LO
VCO
BUFFER
AMP
(NOTE)
FIN
VCO
FEEDBACK
BUFFER
VCO FEEDBACK
VCO
FEEDBACK
EBTS293
120597JNM
NOTE: 14.4 MHz TIMING CIRCUITRY AND 2ND LO VCO PRESENT ONLY ON ABACUS #2.
FUNCTIONS ARE SHARED FOR ALL THREE ABACUS SECTIONS.
Figure:7-6
6 8 P 8 1 0 95E02- D
4/1/2000
7-59
Receiver
7-60
4/ 1/ 2000
8 Troubleshooting
Single Channel Base
Radios
Overview
This chapter isolates single channel Base Radio failures to the FRU level. The
chapter contains procedures for:
chapter contains procedures for:
Troubleshooting
Verication
Station Operation
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-1
Table 8-1
Test Equipment
Model Number
Use
Communications Analyzer
none
Service Computer
Portable Rubidium
Frequency Standard
Ball Efratom
Power Meter
none
RF Attenuator, 250 W, 10 dB
Motorola 0180301E72
Communication
Procomm Plus
File Compression
PKZip
Compress/Decompress data
Software:
8-2
68P81095E02- D 4/1/200 0
Troubleshooting Procedures
Many of the troubleshooting and station operation procedures require
Man-Machine Interface (MMI) commands. These commands are used to
communicate station level commands to the Base Radio via the RS-232
communications port located on the front of the BRC.
Routine Checkout
Procedure 1 is a quick, non-intrusive test performed during a routine site visit.
Use this procedure to verify proper station operation without taking the station
out of service. Figure 8-1 shows the Procedure 1 Troubleshooting Flowchart.
ROUTINE
SITE VISIT
PROCEDURE 1
OBSERVE LED
INDICATORS
Refer to
Controls and Indicators
for LED Definitions
Module Suspected
of Being Faulty?
Yes
Go to Troubleshooting
Procedure 2 Flow Chart
No
CHECK CURRENT
ALARM STATUS
Use MMI command
get alarms
to check alarm status
Module Suspected
of Being Faulty?
Yes
Go to Troubleshooting
Procedure 2 Flow Chart
No
DONE
EBTS021
071895JNM
Figure:8-1
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-3
Reported/Suspected Problem
Use Procedure 2 to troubleshoot reported or suspected equipment malfunctions.
Perform this procedure with equipment in service (non-intrusive) and with
equipment taken temporarily out of service (intrusive).
Figure 8-2 shows the Procedure 2 Troubleshooting Flowchart.
PROBLEM
REPORTED OR SUSPECTED
PROCEDURE 2
OBSERVE LED
INDICATORS
Refer to
Controls and Indicators
for LED Definitions
Module Suspected
of Being Faulty?
Yes
Go to Module Replacement
Procedures Section
No
CHECK CURRENT
ALARM STATUS
Use MMI command
get alarms
to check alarm status
Module Suspected
of Being Faulty?
Yes
Go to Module Replacement
Procedures Section
No
PERFORM
VERIFICATION TESTS
Use MMI commands to
perform tests as specified in
station verification procedure.
Module Suspected
of Being Faulty?
Yes
Go to Module Replacement
Procedures Section
No
DONE
Clear Problem Report
EBTS022
071895JNM
Figure:8-2
8-4
68P81095E02- D 4/1/2000
Removal
Remove BR from Equipment Cabinet as follows:
1.
Remove power from the Base Radio by setting the Power Supply ON/OFF
switch to the OFF position.
2.
Tag and disconnect the cabling from the BR rear panel connectors.
3.
Remove the four M6 TORX screws which secure the BR front panel to the
Equipment Cabinet mounting rails.
WARNING
4.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
While supporting the BR, carefully remove the BR from the Equipment
Cabinet by sliding the BR from the front of cabinet.
8-5
Installation
Install BR in Equipment Cabinet as follows:
1.
2.
While supporting the BR, carefully lift and slide the BR in the Equipment
Cabinet mounting position.
3.
4.
Connect the cabling to the BR rear panel connectors as tagged during the BR
removal. If adding a BR, perform the required cabling in accordance with
the Cabling Information subsection of the RFDS section applicable to the
system.
5.
Anti-Static Precautions
CAUTION
The Base Radio contains static-sensitive devices.
when replacing Base Radio FRUs, always wear a
grounded wrist strap and observe proper anti-static
procedures to prevent electrostatic discharge damage
to Base Radio modules.
Wear a wrist strap (Motorola Part No. 4280385A59 or equivalent) at all times
when servicing the Base Radio to minimize static build-up.
A grounding clip is provided with each EBTS cabinet. If not available, use
another appropriate grounding point.
DO NOT insert or remove modules with power applied to the Base Radio.
ALWAYS turn the power OFF using the Power Supply rocker switch on the
front of the Power Supply module.
8-6
68P81095E02- D 4/1/2000
NOTE
When servicing Base Radios (BRs), in situations where
the Control Board or the entire BR is replaced, the
integrated Site Controller (iSC) will automatically
reboot the serviced BR given that the BR has been
off-line for a period not less than that stipulated by the
Replacement BRC Accept Timer (default is 3
minutes). If the BR is turned on prior to the expiration
of the Replacement BRC Accept Timer, power the
BR back down and wait the minimum timer length
before turning the BR back on.
1.
Remove power from the Base Radio by setting the Power Supply rocker
switch (located behind the front panel of the Power Supply) to the OFF (0)
position.
2.
Loosen the front panel fasteners. These are located on each side of the
module being replaced.
3.
4.
5.
Gently push the replacement module completely into the Base Radio chassis
assembly using the module handle(s).
CAUTION
DO NOT slam or force the module into the chassis
assembly. This will damage the connectors
or backplane.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
6.
Secure the replacement module by tightening the front panel fasteners to the
specied torque of 5 in-lbs.
7.
Apply power to the Base Radio by setting the switch to the ON position.
8.
8-7
Remove the Power Amplier from the Base Radio per FRU Replacement
Procedure.
2.
3.
4.
NOTE
Reverse above procedure to install new fan kit.
8-8
68P81095E02- D 4/1/2000
6 8 P 8 1 0 9 5 E02- D
4/1/2000
1.
2.
Connect the other end of the RS-232 cable to the STATUS port, located on the
front panel of the BRC.
3.
8-9
4.
BRC>dekey
BRC>test_mode
BRC>get brc_rev_no
BRC>get rx1_rev_no
BRC>get rx2_rev_no
BRC>get rx3_rev_no
BRC>get pa_rev_no
BRC>get ex_rev_no
(if BR is 3 branch)
BRC>
5.
If all modules return revision numbers of the format Rxx.xx.xx, then all
revision numbers are present and no further action is required. Log out and
repeat steps 1 through 4 for each additional BR.
If revision numbers were returned as blank or not in the format Rxx.xx.xx,
contact your local Motorola representative or Technical Support.
6.
Transmitter Verification
The transmitter verication procedure veries the transmitter operation and the
integrity of the transmit path. This verication procedure is recommended after
replacing an Exciter, Power Amplier, BRC, or Power Supply module.
NOTE
The following procedure requires the Base Radio to be
out of service. Unless the Base Radio is currently out
of service, Motorola recommends performing this
procedure during off-peak hours. This minimizes or
eliminates disruption of service to system users.
Equipment Setup
To set up the equipment, use the following procedure:
8-10
1.
Remove power from the Base Radio by setting the Power Supply rocker
switch (located behind the front panel of the Power Supply) to the OFF (0)
position.
2.
68P81095E02- D 4/1/200 0
3.
Connect the other end of the RS-232 cable to the STATUS port located on the
front panel of the BRC.
4.
5.
6.
7.
8.
Remove power from the R2660 and connect the Rubidium Frequency
Standard 10MHZ OUTPUT to a 10 dB attenuator.
9.
NOTE
Refer to the equipment manual provided with the
R2660 for further information regarding mode
conguration of the unit (Motorola Part
No. 68P80386B72).
10.
11.
12.
Set the R2660 to the SPECTRUM ANALYZER mode with the center
frequency set to the transmit frequency of the Base Radio under test.
13.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-11
1.
Apply power to the Base Radio by setting the switch to the 1 position.
The following message displays on the service computer during power-up.
Base Radio
fi r mwa re rev i s i on R X X .X X .X X
Copyright 1998
Motorola, Inc. All rights reserved.
U n a u th o r i ze d a ccess prohi bi ted
E n te r l o g i n p a s sword:
2.
Enter the proper password. After entering the correct password, the BRC>
prompt is displayed on the service computer.
The default password is motorola
NOTE
Motorola recommends that you change the default
password once proper operation of the equipment is
veried.
3.
BRC> dekey
XMIT OFF INITIATED
CAUTION
The following command keys the transmitter. Make
sure that transmission only occurs on licensed
frequencies or into a RF load.
8-12
68P81095E02- D 4/1/2000
4.
After keying the Base Radio, verify the forward and reected powers of the
station along with the station VSWR with the parameters listed in Table 8-2.
Table 8-2
5.
Value or Range
Forward Power
Reected Power
VSWR
B RC > g et fwd_pwr
F ORWA R D P OW E R i s 39.13 watts [45.92 dB m]
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-13
6.
B R C > g e t r e f_ pwr
R EF L E C T E D P OW E R i s 0.27 watts [24.28 dB m]
7.
8.
NOTE
If the get alarms command displays alarms, refer to
the System Troubleshooting section of this manual for
corrective actions.
9.
10.
BRC> dekey
XMIT OFF INITIATED
8-14
68P81095E02- D 4/1/2000
EBTS071
032394JNM
Figure:8-3
Apply power to the Base Radio by setting the switch to the 1 position.
The following message displays on the service computer during power-up.
B a se R adi o
fi r mware revi si on R X X .X X .X X
Copyright 1998
Motorola, Inc. All rights reserved.
U n author i zed access prohi bi ted
E n ter l ogi n password:
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-15
2.
Enter the proper password. After entering the correct password, the BRC>
prompt is displayed on the service computer.
The default password is motorola
NOTE
Motorola recommends that you change the default
password once proper operation of the equipment is
veried.
3.
BRC> dekey
XMIT OFF INITIATED
CAUTION
The following command keys the transmitter. Make
sure that transmission only occurs on licensed
frequencies or into an RF load.
8-16
68P81095E02- D 4/1/2000
4.
After keying the Base Radio, verify the forward and reected powers of the
station along with the station VSWR with the parameters listed in Table 8-3.
Table 8-3
5.
Value or Range
Forward Power
Reected Power
VSWR
B RC > g et fwd_pwr
F ORWA R D P OW E R i s 68.55 watts [48.36 dB m]
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-17
6.
B R C > g e t r e f_ pwr
R EF L E C T E D P OW E R i s 2.10 watts [33.22 dB m]
7.
8.
NOTE
If the get alarms command displays alarms, refer to
the System Troubleshooting section of this manual for
corrective actions.
9.
10.
BRC> dekey
XMIT OFF INITIATED
8-18
68P81095E02- D 4/1/2000
EBTS071
032394JNM
Figure:8-4
Apply power to the Base Radio by setting the switch to the 1 position.
The following message displays on the service computer during power-up.
B a se R adi o
fi r mware revi si on R X X .X X .X X
Copyright 1998
Motorola, Inc. All rights reserved.
U n author i zed access prohi bi ted
E n ter l ogi n password:
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-19
2.
Enter the proper password. After entering the correct password, the BRC>
prompt is displayed on the service computer.
The default password is motorola
NOTE
Motorola recommends that you change the default
password once proper operation of the equipment is
veried.
3.
BRC> dekey
XMIT OFF INITIATED
CAUTION
The following command keys the transmitter. Make
sure that transmission only occurs on licensed
frequencies or into an RF load.
8-20
68P81095E02- D 4/1/2000
4.
After keying the Base Radio, verify the forward and reected powers of the
station along with the station VSWR with the parameters listed in Table 8-4.
Table 8-4
5.
Value or Range
Forward Power
Reected Power
VSWR
B RC > g et fwd_pwr
F ORWA R D P OW E R i s 61.0 watts [47.88 dB m]
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-21
6.
B R C > g e t r e f_ pwr
R EF L E C T E D P OW E R i s 1.67 watts [32.22 dB m]
7.
8.
NOTE
If the get alarms command displays alarms, refer to
the System Troubleshooting section of this manual for
corrective actions.
9.
10.
BRC> dekey
XMIT OFF INITIATED
8-22
68P81095E02- D 4/1/2000
937.5000
EBTS418
EBTS071
101797JNM
032394JNM
Figure:8-5
Apply power to the Base Radio by setting the switch to the 1 position.
The following message displays on the service computer during power-up.
B a se R adi o
fi r mware revi si on R X X .X X .X X
Copyright 1998
Motorola, Inc. All rights reserved.
U n author i zed access prohi bi ted
E n ter l ogi n password:
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-23
2.
Enter the proper password. After entering the correct password, the BRC>
prompt is displayed on the service computer.
The default password is motorola
NOTE
Motorola recommends that you change the default
password once proper operation of the equipment is
veried.
3.
BRC> dekey
XMIT OFF INITIATED
CAUTION
The following command keys the transmitter. Make
sure that transmission only occurs on licensed
frequencies or into a RF load.
8-24
68P81095E02- D 4/1/2000
4.
After keying the Base Radio, verify the forward and reected powers of the
station along with the station VSWR with the parameters listed in Table 8-5.
Table 8-5
5.
Value or Range
Forward Power
Reected Power
VSWR
B RC > g et fwd_pwr
F ORWA R D P OW E R i s 39.13 watts [45.92 dB m]
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-25
6.
B R C > g e t r e f_ pwr
R EF L E C T E D P OW E R i s 0.27 watts [24.28 dB m]
7.
8.
NOTE
If the get alarms command displays alarms, refer to
the System Troubleshooting section of this manual for
corrective actions.
9.
10.
BRC> dekey
XMIT OFF INITIATED
8-26
68P81095E02- D 4/1/2000
Figure:8-6
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-27
Equipment Disconnection
Use the following steps to disconnect equipment after verifying the transmitter.
1.
Remove power from the Base Radio by setting the Power Supply rocker
switch (located behind the front panel of the Power Supply) to the OFF (0)
position.
2.
Disconnect the RS-232 cable from the connector on the service computer.
3.
Disconnect the other end of the RS-232 cable from the RS-232 connector
located on the front panel of the BRC.
4.
Disconnect the test cable from the PA OUT connector located on the
backplane of the Base Radio.
5.
6.
Disconnect the 10 dB attenuator from the other end of the test cable.
7.
8.
Restore power to the Base Radio by setting the Power Supply rocker switch
to the ON (1) position.
If necessary, continue with the Receiver Verication Procedure.
Receiver Verification
The receiver verication procedure sends a known test signal to the Base Radio to
verify the receive path. This verication procedure is recommended after
replacing a Receiver, BRC, or Power Supply module.
NOTE
The following procedure requires the Base Radio to be
out of service. Unless the Base Radio is currently out
of service, Motorola recommends performing this
procedure during off-peak hours. This minimizes or
eliminates disruption of service to system users.
Equipment Setup
Set up the equipment for the receiver verication procedure as follows:
8-28
1.
Remove power from the Base Radio by setting the Power Supply rocker
switch (located behind the front panel of the Power Supply) to the OFF (0)
position.
2.
68P81095E02- D 4/1/2000
3.
Connect the other end of the RS-232 cable to the STATUS port located on the
front panel of the BRC.
4.
Disconnect the existing cable from the connector labeled RX1 (or the
connector corresponding to the receiver under test).
This connector is located on the backplane of the Base Radio.
5.
6.
Connect the other end of the test cable to the RF IN/OUT connector on the
R2660 Communications Analyzer.
7.
Remove power from the R2660 and connect the Rubidium Frequency
Standard 10MHZ OUTPUT to a 10 dB attenuator.
8.
9.
10.
NOTE
Refer to the equipment manual provided with the
R2660 for further information regarding mode
conguration of the unit (Motorola Part
No. 68P80386B72).
11.
Set the R2660 to the receive frequency of the Base Radio under test.
All receivers within a single Base Radio have the same receive frequency.
12.
Set the R2660 to generate the test signal at an output level of -80dBm.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-29
13.
Restore power to the Base Radio by setting the Power Supply rocker switch
to the ON (1) position.
The following message displays on the service computer during power-up.
Base Radio
fi r mwa re rev i s i on R X X .X X .X X
Copyright 1998
Motorola, Inc. All rights reserved.
U n a u th o r i ze d a ccess prohi bi ted
E n te r l o g i n p a s sword:
14.
Enter the proper password. After entering the correct password, the BRC>
prompt is displayed on the service computer.
The default password is motorola
NOTE
Motorola recommends that you change the default
password once proper operation of the equipment
is veried.
8-30
68P81095E02- D 4/1/2000
15.
16.
Verify that the R2660 transmit frequency is set to the frequency determined
in the previous step.
17.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-31
18.
RSSI 2 R S S I 3
SGC
dBm
dBm
dBm
dB
------
------
------
----
- 80. 0
- 131. 5 - 1 3 1 . 5
CI
BER
dBmdBm %
---------------------
OffsetSyncMiss
Hz%
-------
---------
- 7 9 . 2 - 1 2 1 . 9 0 . 0 0 0 e +0 0 - 5 . 4 . 0 0 0 e +0 0
19.
Verify that the RSSI dBm signal strength, for the receiver under test, is
-80.0 dBm 1.0 dBm. Adjust the R2660 signal output level to get the
appropriate RSSI dBm level. The BER oor % value is valid only if the RSSI
signal strength is within the limits of -81.0 dBm to -79.0 dBm.
20.
NOTE
If the get alarms command displays alarms, refer to
the System Troubleshooting section for corrective
actions.
8-32
68P81095E02- D 4/1/2000
21.
NOTE
If the kit number is CRF6010 or CRF6030, continue to
step 22, otherwise to Equipment Disconnection.
22.
NOTE
If the antenna conguration does not match the
receiver conguration, use the set rx_fru_config
MMI command to properly set the parameter.
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-33
Equipment Disconnection
Disconnect equipment after verifying the receiver as follows:
1.
Remove power from the Base Radio by setting the Power Supply rocker
switch (located behind the front panel of the Power Supply) to the OFF (0)
position.
2.
Disconnect the RS-232 cable from the connector on the service computer.
3.
Disconnect the other end of the RS-232 cable from the RS-232 connector on
the front panel of the BRC.
4.
Disconnect the test cable from the RX 1 connector located on the backplane
of the Base Radio.
5.
6.
7.
Restore power to the Base Radio by setting the Power Supply rocker switch
to the ON (1) position.
This completes the Receiver Verication Procedure for the receiver under
test.
Repeat the Receiver Verication Procedure for each receiver in every Base Radio
in the EBTS.
8-34
68P81095E02- D 4/1/2000
Connector
Description
Type
RX 1 through RX 3
RF-type
connector in
Table 8
RF-type
connectors
in Table 21
and Table 22
PA OUT
RF-type
connector in
Table 22
ETHERNET A
BNC-type
connector in
Table 18
BNC-type
connector in
Table 20
(or labeled
ETHERNET on
some production
units)
5MHZ/ 1 PPS-A
(or labeled SPARE
on some
production units)
RS-232
DB-9-type
connectors
in Table 17
ALARM
DB-25-type
connector
Line cord
connector
DC POWER
Card edge
connector
GROUND
Ground stud
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-35
Figure 8-7 shows the locations of the Base Radio external connections.
RX 3
*
AC POWER
GROUND
RX 2
DC POWER
RX 1
BLACK
RE
EX
EX OUT
PA FB
PA IN
ETHERNET A
5MHZ/1 PPS B
5MHZ/1 PPS A
ALARM
RS 232
PA OUT
Figure:8-7
EBTS327
021997JNM
Backplane RF Connections
When Base Radios are shipped from the factory as FRUs, each connection on the
back of a repeater has a designated color dot beside it as listed in Table 8-7. To
nd where a cable should be connected, match the label wrapped around the
cable to the dot on the back of the repeater.
Table 8-7
Connectors
TX
8-36
RX 1
Red
RX 2
Green
RX 3
Yellow
Ethernet
White
5 MHz/1 pps A
or Spare
Gray
68P81095E02- D 4/1/2000
P1 Connector Pin-outs
Pin No.
Row A
Row B
Row C
P1 Connector Pin-outs
Pin No.
Row A
Row B
Row C
AGC3
GND
AGC1
AGC4
GND
AGC2
GND
GND
GND
GND
GND
GND
AGC3
14.2V
AGC1
AGC4
14.2V
AGC2
GND
GND
GND
14.2V
14.2V
14.2V
RESET
GND
GND
14.2V
14.2V
14.2V
BATT_STAT
GND
GND
GND
GND
GND
CTS
GND
GND
GND
GND
GND
RTS
5V
5V
5V
5V
5V
5V
5V
5V
10
5V
5V
5V
5V
5V
5V
10
SHUTDOWN
5V
11
RCLK
5V
DATA1
12
ODC_1
5V
DATA1*
13
TCLK
GND
DATA3
11
GND
GND
GND
12
GND
GND
GND
13
DATA1*
GND
GND
14
DATA1
GND
GND
15
ODC_1
GND
GND
16
GND
GND
GND
17
GND
GND
GND
18
SBI_1
GND
GND
19
GND
GND
GND
20
GND
GND
GND
14
ODC_3
GND
DATA3*
15
RXD
GND
DATA2
16
ODC_2
17
TXD
18
SSI
SBI_1
19
SSI*
SBI_3
22
20
BRG
SBI_2
23
A5
21
CLK
24
WP*
22
CLK*
23
GND
24
A5
DATA2*
GND
GND
GND
21
A4
25
A3
26
A2
27
A0_CS1
A1_CS2
A4_RXSEL
SPI_MISO
25
A0
GND
A1
28
SPI_MOSI
26
CD
GND
5MHZ/
SPARE
29
SPI_CLK
30
GND
GND
27
METER_STAT
GND
SPI_MISO
31
GND
GND
GND
28
WP*
GND
SPI_CLK
32
GND
GND
2.1MHZ_RX
29
GND
GND
SPI_MOSI
30
GND
GND
GD
31
1PPS_GPS
GND
2.1MHZ_TX
32
GND
GND
2.1MHZ_RX
GND
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-37
Table 11
P2 Connector Pin-outs
P3 Connector Pin-outs
Pin No.
Row A
Row B
Row C
Pin No.
Row A
Row B
Row C
AGC3
GND
AGC1
AGC3
GND
AGC1
AGC4
GND
AGC2
AGC4
GND
AGC2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
14.2V
14.2V
14.2V
14.2V
14.2V
14.2V
14.2V
14.2V
14.2V
14.2V
14.2V
14.2V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5V
5V
5V
5V
5V
5V
10
5V
5V
5V
10
5V
5V
5V
11
GND
GND
GND
11
GND
GND
GND
12
GND
GND
GND
12
GND
GND
GND
13
DATA2*
GND
GND
13
DATA3*
GND
GND
14
DATA2
GND
GND
14
DATA3
GND
GND
15
ODC_2
GND
GND
15
ODC_3
GND
GND
16
GND
GND
GND
16
GND
GND
GND
17
GND
GND
GND
17
GND
GND
GND
18
SBI_2
GND
GND
18
SBI_3
GND
GND
19
GND
GND
GND
19
GND
GND
GND
20
GND
GND
GND
20
GND
GND
GND
A0_CS1
21
21
22
A1_CS2
22
A0_CS1
A1_CS2
23
A5
23
A5
24
WP*
24
WP*
25
A3_RXSEL
25
26
27
A2_RXSEL
26
SPI_MISO
27
28
SPI_MOSI
29
SPI_CLK
30
GND
GND
31
GND
GND
32
GND
GND
8-38
SPI_MISO
28
SPI_MOSI
29
SPI_CLK
GND
30
GND
GND
GND
GND
31
GND
GND
GND
2.1MHZ_RX
32
GND
GND
2.1MHZ_RX
68P81095E02- D
4/1/200 0
Pin
No.
P2 Connector Pin-outs
Table 14
Row A
Row B
Row C
Row D
GND
AGC4
AGC3
GND
GND
AGC2
AGC1
A0
GND
RX1_DAT
A
RX1_DAT
A
A1
GND
RX1_SBI
RX1_ODC
GND
RX2_DAT
A
5V
Pin No.
P5 Connector Pin-outs
Row A
Row B
Row C
28V
28V
28V
28V
28V
28V
14.2V
14.2V
14.2V
14.2V
14.2V
14.2V
A2
5V
5V
5V
RX2_DAT
A
A3
5V
5V
5V
GND
GND
EXT_VFWD
RX2_SBI
RX2_ODC
A4
GND
GND
EXT_VREF
GND
RX3_DAT
A
RX3_DAT
A
A5
GND
RX3_SBI
RX3_ODC
WP*
10
GND
GND
GND
14.2V
SCLK
MOSI
MISO
11
GND
GND
VBLIN
10
14.2V
GND
GND
GND
12
GND
GND
RESET
11
14.2V
GND
REF
GND
12
GND
GND
GND
GND
14
GND
GND
GND
15
GND
GND
SPI_MISO
16
A0
GND
GND
17
GND
GND
SPI_CLK
18
A1
GND
WP*
19
GND
GND
GND
20
A5
GND
SPI_MOSI
21
GND
GND
GND
22
A4
GND
GND
23
GND
GND
CLK*
24
A3
GND
GND
P3 Connector Pin-outs
Pin
No.
Row
A
Row B
GND
2
3
Row C
Row
D
Row E
GND
GND
GND
GND
RX1
GND
13
25
GND
GND
CLK
26
GND
GND
GND
27
GND
GND
SSI*
28
GND
GND
GND
29
GND
GND
SSI
30
GND
GND
GND
31
GND
GND
2.1MHz_TX
32
GND
GND
GND
6
7
GND
8
9
GND
RX2
GND
GND
RX3
GND
GND
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-39
Pin No.
P6 Connector Pin-outs
Row A
Row B
Row C
VBLIN
GND
28V
GND
GND
28V
A0
GND
28V
GND
GND
28V
A1
GND
28V
GND
GND
28V
A2
GND
28V
GND
GND
28V
A3
GND
28V
10
GND
GND
28V
11
SPI_MISO
GND
28V
12
GND
GND
28V
13
SPI_MOSI
GND
28V
14
GND
GND
28V
15
SPI_CLK
GND
28V
16
GND
GND
28V
17
WP*
GND
28V
18
GND
GND
28V
19
GND
GND
28V
20
GND
GND
28V
21
GND
GND
28V
22
GND
GND
28V
23
GND
GND
28V
24
GND
GND
28V
25
GND
5V
28V
26
GND
5V
28V
27
GND
14.2V
28V
28
GND
14.2V
28V
29
GND
14.2V
28V
30
GND
14.2V
28V
31
GND
28V
28V
32
GND
28V
28V
Table 16
P7 Connector Pin-outs
Pin No.
Signal
SPI_MISO
SPI_MOSI
SPI_CLK
A0
A1
A2
A3
A4
A5
10
GND
11
28V
12
14.2V
13
14.2V
14
WP*
15
5V
16
GND
17
BATT_STAT
18
MTR_STAT
19
EXT_VFWD
20
EXT_VREF
21
GND
22
GND
23
BAT_TEMP
24
VAT_TEMP
25
GND
8-40
68P81095E02- D
4/1/200 0
Table 17
P8 Connector Pin-outs
Pin No.
Signal
CD
RxD
TxD
RCLK
GND
TCLK
RTS
CTS
BRG
Table 18
Connector
Signal
Table 19
Connector
Signal
P19
RCV ONE RF IN
P20
RCV TWO RF IN
P21
RCV THREE RF IN
Table 20
Connector
Signal
P10
P11
Table 21
Connector
Signal
P14
EXCITER OUT
P15
EXCITER FEEDBACK
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-41
Blind Mates - PA
Table 22
Connector
Signal
P16
PA FEEDBACK
P17
PA IN
P18
PA RF OUT
Table 23
8-42
P9 Connector Pin-outs
Pin No.
Signal
GND
GND
28V
28V
28V
28V
28V
28V
28V
10
28V
11
28V
12
28V
13
28V
14
28V
15
28V
16
14.2V
17
14.2V
18
14.2V
19
14.2V
20
14.2V
21
14.2V
22
14.2V
23
14.2V
24
5V
25
5V
26
5V
27
5V
28
5V
29
5V
30
5V
31
5V
68P81095E02- D 4/1/2000
Table 23
Signal
32
GND
33
GND
34
GND
35
GND
36
GND
37
GND
38
GND
39
GND
40
GND
41
GND
42
GND
43
GND
44
GND
45
GND
46
GND
47
GND
48
GND
49
GND
50
GND
51
GND
52
GND
53
GND
54
SCR_SHUT
55
SCR_THRESH
56
RELAY_ENABLE
57
SHUTDOWN
58
28V_AVG
59
BATT_TEMP
60
SPI_MISO
61
SPI_MOSI
62
SPI_CLK
63
64
65
66
67
A0(CS1)
68
A1(CS2)
6 8 P 8 1 0 9 5 E02- D
4/1/2000
8-43
Table 23
Signal
69
A5
70
71
A4
72
8-44
73
A3
74
GND
75
A2
76
GND
77
GND
78
GND
68P81095E02- D 4/1/2000
Signal Name
6 8 P 8 1 0 9 5 E02- D
4/1/2000
Signal Description
GND
Station ground
28V
28VDC
14.2V
14.2VDC
5.1V
5.1 VDC
A0,A1,A2,A3,A4,A5
SPI_MOSI
SPI_MISO
SPI_CLK
2.1MHz_RX
2.1MHz_TX
DATA1, DATA1*
DATA2 DATA2*
DATA3, DATA3*
SSI, SSI*
CLK, CLK*
BRCVBLIN
VBLIN
RESET
EXT_VFWD
EXT_VREF
WP*
BAT_STAT
8-45
Table 8-24
Signal Name
Signal Description
METER_STAT
1PPS
RCLK
TCLK
CTS
RTS
CD
RXD
TXD
BRG
5MHz / Spare
EXCITER_OUT
EXCITER_FEEDBACK
PA_IN
PA_FEEDBACK
RX1_IN
RF into Receiver 1
RX2_IN
RF into Receiver 2
RX3_IN
RF into Receiver 3
5MHZ REFERENCE
ETHERNET
Interface between the BRC and the ACG. This connects the
Base to the 10 MHz LAN
SCR_SHUT
SCR_THRESH
RELAY ENABLE
SHUTDOWN
28V_AVG
BATT_TEMP
8-46
68P81095E02- D 4/1/2000
9 Troubleshooting
QUAD Channel Base
Radios
Overview
This chapter is a guide for installing a Quad Base Radio and isolating Base Radio
failures to the FRU level. The chapter contains procedures for:
Troubleshooting
Installation
Verication
Station Operation
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-1
Table 9-1
Test Equipment
Model Number
Use
Communications Analyzer
Signal Generator
HP4432b
RX testing
none
3 way RF splitter
none
Service Computer
Portable Rubidium
Frequency Standard
Ball Efratom
Power Meter
none
RF Attenuator, 250 W, 10 dB
Motorola 0180301E72
Communication
Procomm Plus
Quad BR waveform
Motorola supplied
with HP4432b
Software:
9-2
68P81095E02-D 12/12/2000
Troubleshooting Procedures
Many troubleshooting and station operation procedures require Man-Machine
Interface (MMI) commands. These commands communicate station level
commands to the Base Radio via the RS-232 communications port on the front of
the BRC.
Routine Checkout
Procedure 1 is a quick, non-intrusive test performed during a routine site visit.
Use this procedure to verify proper station operation without taking the station
out of service. Figure 9-1 shows the Procedure 1 Troubleshooting Flowchart.
ROUTINE
SITE VISIT
PROCEDURE 1
OBSERVE LED
INDICATORS
Refer to
Controls and Indicators
for LED Definitions
Module Suspected
of Being Faulty?
Yes
Go to Troubleshooting
Procedure 2 Flow Chart
No
CHECK CURRENT
ALARM STATUS
Use MMI command
get alarms
to check alarm status
Module Suspected
of Being Faulty?
Yes
Go to Troubleshooting
Procedure 2 Flow Chart
No
DONE
EBTS021
071895JNM
Figure:9-1
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-3
Reported/Suspected Problem
Use Procedure 2 to troubleshoot reported or suspected equipment malfunctions.
Perform this procedure with equipment in service (non-intrusive) and with
equipment taken temporarily out of service (intrusive).
Figure 9-2 shows the Procedure 2 Troubleshooting Flowchart.
PROBLEM
REPORTED OR SUSPECTED
PROCEDURE 2
OBSERVE LED
INDICATORS
Refer to
Controls and Indicators
for LED Definitions
Module Suspected
of Being Faulty?
Yes
Go to Module Replacement
Procedures Section
No
CHECK CURRENT
ALARM STATUS
Use MMI command
get alarms
to check alarm status
Module Suspected
of Being Faulty?
Yes
Go to Module Replacement
Procedures Section
No
PERFORM
VERIFICATION TESTS
Use MMI commands to
perform tests as specified in
station verification procedure.
Module Suspected
of Being Faulty?
Yes
Go to Module Replacement
Procedures Section
No
DONE
Clear Problem Report
EBTS022
071895JNM
Figure:9-2
9-4
68P81095E02-D 12/12/2000
CAUTION
Removal
Remove the BR from the Equipment Cabinet as follows:
CAUTION
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-5
1.
Remove power from the Base Radio by setting the Power Supply ON/OFF
switch to the OFF position.
2.
Tag and disconnect the cabling from the BR rear panel connectors.
3.
Remove the Power Amplier module to reduce the BR weight. Remove the
two M10 Torx screws that secure the Power Amplier module. Slide the
module out of the chassis.
4.
Remove the four M30 TORX screws which secure the BR front panel to the
Equipment Cabinet mounting rails.
5.
While supporting the BR, carefully remove the BR from the Equipment
Cabinet by sliding the BR from the front of cabinet. When the BR becomes free
from its mounting rails, be sure to fully support it.
Installation
Install BR in Equipment Cabinet as follows:
CAUTION
9-6
1.
2.
Remove the Power Amplier module to reduce the BR weight. Remove the
two M10 Torx screws that secure the Power Amplier module. Slide the
module out of the chassis.
3.
While supporting the BR, carefully lift and slide the BR in the Equipment
Cabinet mounting position.
4.
Secure the BR to the Equipment Cabinet mounting rails using four M30 Torx
screws. Tighten the screws to 40 in-lb (4.5 Nm).
5.
Slide the Power Amplier module back into the BR chassis. Replace two
M10 Torx screws that secure the Power Amplier module. Secure the
module by tightening the screws to the specied torque of 5 in-lbs.
6.
Connect the cabinet cabling to the BR. Refer to Backplane gure XX.
7.
68P81095E02-D 12/12/2000
NOTE
Base Radio removal and installation procedures
appear for reference or buildout purposes. Field
maintenance of Base Radios typically consists of
replacement of FRUs within the Base Radio. Perform
Base Radio FRU replacement according to Base Radio
FRU Replacement Procedure below.
Anti-Static Precautions
CAUTION
The Base Radio contains static-sensitive devices.
Prevent electrostatic discharge damage to Base Radio
modules! When replacing Base Radio FRUs, wear a
grounded wrist strap. Observe proper anti-static
procedures.
Wear a wrist strap (Motorola Part No. 4280385A59 or equivalent) at all times
when servicing the Base Radio to minimize static build-up.
A grounding clip is provided with each EBTS cabinet. If not available, use
another appropriate grounding point.
DO NOT insert or remove modules with power applied to the Base Radio.
ALWAYS turn the power OFF using the Power Supply rocker switch on the
front of the Power Supply module.
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-7
NOTE
After a Control Board or BR replacement, the
integrated Site Controller (iSC) reboots the BR.
Whenever the BR goes off-line, the Replacement BRC
Accept Timer begins counting down. A BR reboot
occurs if the BR remains off-line as the timer times out.
(The timers default period is three minutes.) If
someone turns on the BR before the timer times out,
power down the BR. Then wait for the minimum
timer period before turning on the BR.
1.
Notice the Power Supply rocker switch, behind the front panel of the Power
Supply. Set the Power Supply rocker switch to the OFF (0) position. Turning
off this switch removes power from the Base Radio.
2.
Loosen the front panel fasteners. These are located on each side of the
module being replaced.
3.
4.
5.
Gently push the replacement module completely into the Base Radio chassis
assembly using the module handle(s).
CAUTION
DO NOT slam or force the module into the chassis
assembly. Rough handling can damage the connectors
or backplane.
9-8
6.
Secure the replacement module by tightening the front panel fasteners to the
specied torque of 5 in-lbs.
7.
Apply power to the Base Radio by setting the switch to the ON position.
8.
68P81095E02-D 12/12/2000
Remove the Power Amplier from the Base Radio per FRU Replacement
Procedure.
2.
3.
4.
NOTE
To install the new fan kit, reverse above procedure.
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-9
1.
2.
Connect the other end of the RS-232 cable to the STATUS port, located on the
front panel of the EX/CNTL module.
3.
Power on the BR using the front switch on the Power Supply Module. Press
the reset button on the Control Module front panel. At the prompt, hit a
Carriage Return on the service computer to enter the test application mode.
Using the password Motorola, log in to the BR.
:> l og i n - u f ie ld
p a sswor d: *****
fi e l d>m o t o ro la
fi e l d>
9-10
68P81095E02-D 12/12/2000
4.
5.
If all modules return revision numbers of the format Rxx.xx.xx, then all
revision numbers are present. In that case, verication requires no further
action. If revision numbers return as blank, or not in the format Rxx.xx.xx,
contact your local Motorola representative or Technical Support.
6.
7.
After checking all BRs, log out by keying the following command:
field> logout
field>
Transmitter Verification
The transmitter verication procedure veries transmitter operation and transmit
path integrity. Motorola recommends this verication procedure after replacing
an Exciter, Power Amplier, BRC, or Power Supply module.
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-11
NOTE
The following procedure requires the Base Radio to be
out of service. Unless the Base Radio is currently out
of service, Motorola recommends performing this
procedure during off-peak hours. Performing this
procedure then minimizes or eliminates disruption of
service to system users.
Equipment Setup
To set up the equipment, use the following procedure:
1.
Remove power from the Base Radio by setting the Power Supply rocker
switch (located behind the front panel of the Power Supply) to the OFF (0)
position.
2.
3.
Connect the other end of the RS-232 cable to the STATUS port located on the
front panel of the BRC.
4.
Disconnect the existing cable from the connector labeled PA OUT. This
connector is located on the backplane of the Base Radio.
5.
6.
7.
8.
Remove power from the R2660. Connect the Rubidium Frequency Standard
10MHZ OUTPUT to a 10 dB attenuator.
9.
NOTE
Refer to the R2660 equipment manual for further
information regarding mode conguration of the unit.
(Motorola Part No. 68P80386B72.)
9-12
10.
11.
12.
Set the R2660 to the SPECTRUM ANALYZER mode with the center
frequency set to the transmit frequency of the Base Radio under test.
68P81095E02-D 12/12/2000
13.
Power on the BR using the front switch on the Power Supply Module. Press
the reset button on the Control Module front panel. At the prompt, hit a
Carriage Return on the service computer to enter the test application mode.
Using the password Motorola, login to the BR.
:> lo g in -u fie ld
pa s swo rd : * * * * *
fi eld >mo to ro la
fi eld >
2.
fi e ld > p tm -o tx _ a ll -ms to p
fi e ld > p owe r -o tx ch 1 -p 0
fi e ld >
CAUTION
3.
Key the BR to 40 watts, following the steps below from the eld> prompt :
3.1
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-13
fi el d> f re q - o t x ch 1 -f8 6 0
fi el d> f re q - o t x ch 2 -f8 6 0 .0 2 5
fi el d> f re q - o t x ch 3 -f8 6 0 .0 5
fi el d> f re q - o t x ch 4 -f8 6 0 .0 7 5
fi el d>
3.2
fi el d> p t m - o t x_ a ll -md n lk _ fr a me d
fi el d>
3.3
fi el d> d p m - o t x ch 1 -mid e n
fi el d> d p m - o t x ch 2 -mid e n
fi el d> d p m - o t x ch 3 -mid e n
fi el d> d p m - o t x ch 4 -mid e n
fi el d>
3.4
4.
After keying the Base Radio, verify the stations forward and reected
power and VSWR. Check these gures against the parameters in Table 9-2.
Table 9-2
9-14
Value or Range
Forward Power
Reected Power
VSWR
68P81095E02-D 12/12/2000
4.1
4.2
4.3
4.4
5.
This command returns all active alarms of the Base Radio. At the eld>
prompt, type:
NOTE
If the alarms command displays alarms, refer to the
System Troubleshooting chapter for corrective actions.
6.
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-15
Figure:9-3
7.
Equipment Disconnection
Use the following steps to disconnect equipment after verifying the transmitter.
9-16
1.
Remove power from the Base Radio by setting the Power Supply rocker
switch (located behind the front panel of the Power Supply) to the OFF (0)
position.
2.
Disconnect the RS-232 cable from the connector on the service computer.
3.
Disconnect the other end of the RS-232 cable from the RS-232 connector
located on the front panel of the BRC.
68P81095E02-D 12/12/2000
4.
Disconnect the test cable from the PA OUT connector located on the
backplane of the Base Radio.
5.
6.
Disconnect the 10 dB attenuator from the other end of the test cable.
7.
8.
Restore power to the Base Radio by setting the Power Supply rocker switch
to the ON (1) position.
9.
Receiver Verification
The receiver verication procedure sends a known test signal into the Base Radio
to verify the receive path. This verication procedure is recommended after
replacing a Receiver.
NOTE
The following procedure requires the Base Radio to be
out of service. Unless the base radio is currently out of
service, Motorola recommends performing this
procedure during off-peak hours. Performing this
procedure then minimizes or eliminates disruption of
services to system users.
Equipment Setup
Set up equipment for the receiver verication procedure as follows:
6 8 P 8 1 0 9 5E02- D
12/12/2000
1.
Remove power from the Base Radio by setting the Power Supply rocker
switch (located behind the front panel of the Power Supply) to the OFF (0)
position.
2.
3.
Connect the other end of the RS-232 cable to the STATUS port located on the
front panel of the BRC.
4.
Disconnect the existing cable from the connector labeled RX1 (or the
connector corresponding to the receiver under test). Connector RX1 is on the
Base Radio backplane.
5.
6.
9-17
7.
Attach RF output from the HP4432b to a 3 way splitter. Attach the output of
the three way splitter to the antenna connections in the back of the BR.
8.
Attach the 'event 2' port in the rear panel to pin 6 on the front panel of the
BR.
9.
10.
Turn on the 4432b. Press the 'mode' key. Select the 'arbitrary waveform
generator'. Select 'Dual Arb'. Goto 'waveform select' and choose Tornado.
Choose 'waveform segments'. Select the 'load' softkey. Choose the softkey
'Store all To NVARB Memory'. Press the 'return' softkey.
11.
12.
13.
Set the reference frequency to the correct frequency (5Mhz) and select 'ARB
Reference' EXT for external reference.
14.
Select the I/Q key. Goto the next page by selecting 'More (1 of 2)'. Turn 'ALC'
off by selecting the softkey.
15.
Select the 'Mode' key again, followed by the 'arbitrary waveform generator'
softkey, 'Dual Arb'
16.
Set the frequency and power out and turn on the modulation and RF out.
Power on the BR using the front switch on the Power Supply Module. Press
the reset button on the Control Module front panel. At the prompt, hit a
Carriage Return on the service computer to enter the test application mode.
Using the password Motorola, login to the BR..
>l o g i n u fi e ld
>pa sswor d: **** *
fi e l d>m o t o ro la
fi e l d>
2.
9-18
68P81095E02-D 12/12/2000
3.
Using the MMI commands below, issue the command to put the BR into
3RX mode. If the resulting bit error rates for receiver branches 1, 2, and 3 are
less than 8%, the receiver has passed the test.
3.1
fi e ld > fr e q -o r x ch 1 -f8 1 0
fi e ld > e n a ble -o r x ch 1 -s o n
fi e ld > s g e -o r x _ a ll -s o ff
fi e ld > e s -o r x _ a ll -tex t_ tr igg e r
fi e ld > p e e r _ p e r fo r ma n c e _ c o n fig -o r x ch 1 -mp a th -p a ll
fi e ld > p e e r _ p e r fo r ma n c e _ r e p o r t -o r x ch 1 -a 1 0 0 -r 1
field>
3.2
fi e ld > fr e q -o r x ch 2 -f8 1 0
fi e ld > e n a ble -o r x ch 2 -s o n
fi e ld > s g e -o r x _ a ll -s o ff
fi e ld > e s -o r x _ a ll -tex t_ tr igg e r
fi e ld > p e e r _ p e r fo r ma n c e _ c o n fig -o r x ch 2 -mp a th -p a ll
fi e ld > p e e r _ p e r fo r ma n c e _ r e p o r t -o r x ch 2 -a 1 0 0 -r 1
field>
3.3
fi e ld > fr e q -o r x ch 3 -f8 1 0
fi e ld > e n a ble -o r x ch 3 -s o n
fi e ld > s g e -o r x _ a ll -s o ff
fi e ld > e s -o r x _ a ll -tex t_ tr igg e r
fi e ld > p e e r _ p e r fo r ma n c e _ c o n fig -o r x ch 3 -mp a th -p a ll
fi e ld > p e e r _ p e r fo r ma n c e _ r e p o r t -o r x ch 3 -a 1 0 0 -r 1
field>
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-19
3.4
4.
Enter the command to return all active alarms of the Base Radio. At the
eld> prompt, type:
fi e l d> a la rm s_ o fa u lt_ h n d lr
field>
NOTE
If the command displays alarms, refer to the System
Troubleshooting section for corrective actions.
5.
As an option, you may check kit numbers for the receiver and other
modules. The following command returns this data. (The example below
species 800 MHz Quad Base Radios.) At the eld> prompt, type:
fi e l d> f v - o p latfo r m
field>
Equipment Disconnection
After verifying receiver operation, disconnect equipment as follows:
9-20
1.
Notice the Power Supply rocker switch, behind the front panel of the Power
Supply. Set the Power Supply rocker switch to the OFF (0) position. Turning
off this switch removes power from the Base Radio.
2.
Disconnect the RS-232 cable from the connector on the service computer.
68P81095E02-D 12/12/2000
6 8 P 8 1 0 9 5E02- D
12/12/2000
3.
Disconnect the other end of the RS-232 cable from the RS-232 connector on
the front panel of the BRC.
4.
Disconnect the test cable from the RX1, RX2, and RX3 connectors located on
the backplane of the Base Radio.
5.
6.
Restore power to the Base Radio by setting the Power Supply rocker switch
to the ON (1) position. This step completes the Receiver Verication
Procedure for the receiver under test.
7.
Repeat the Receiver Verication Procedure for each Quad receiver in every
Base Radio in the EBTS.
9-21
Table 9-3
Connector
Module
Description
Connector Type
P1
EXBRC
Signal
P2
RX1
Signal
P3
RX1
RF
P4
RX2
Signal
P5
RX2
RF
P6
RX3
Signal
P7
RX3
RF
P8
RX4
Signal
P9
RX4
RF
P10
PA
Signal
96 Pin EURO
P11
PS
P12a
PS
P13
EX
SMA blindmate
P14
EX
RF(EX to PA)
SMA blindmate
P15
External / EXBRC
Ethernet
BNC blindmate
P16
External / PA
SMA blindmate
P17
External / PA
RF (PA to EX)
SMA Blindmate
P18
External / PA
TX Output
SMA blindmate
P19
RX Branch 1
RF
SMA
P20
RX Branch 2
RF
SMA
P21
RX Branch 3
RF
SMA
P22b
External
RS232
Dsub-9
P23
External
Alarm
Dsub-25
P24
External
5MHz/1PPS
BNC
a. P12 is a cutout in the backplane with threaded inserts for securing the connector which
mates directly to the power supply.
b. P22 will not be placed on the Tornado backplane. However, the backplane shall be
designed with P22 to allow for reuse on other products.
9-22
68P81095E02-D 12/12/2000
Figure 9-4 shows the locations of the Base Radio external connections.
RX 3
*
AC POWER
GROUND
RX 2
E
B
T
DC POWER
RX 1
RE
ETHERNET A
5MHZ/1 PPS B
T
*
5MHZ/1 PPS A
P
IH S
R
U
CI T
ALARM
S
U
M
E
RS 232
PA OUT
N
A
CH
BLACK
EX
EX OUT
PA FB
PA IN
Figure:9-4
!
D
GE
EBTS327
021997JNM
Backplane RF Connections
When the factory ships Base Radios as FRUs, each connection on the back of a
repeater has a designated color dot beside it. See Table 9-4. To nd where a cable
should be connected, match the label wrapped around the cable to the dot on the
back of the repeater.
Table: 9-4Color Codes for RF Connections on Rear of Base Radio
Connectors
TX
6 8 P 8 1 0 9 5E02- D
12/12/2000
RX 1
Red
RX 2
Green
RX 3
Yellow
Ethernet
White
5 MHz/1 pps A
or Spare
Gray
9-23
9-24
Row
GND
3.3 Vdc
3.3 Vdc
NC
GND
3.3 Vdc
14.2 Vdc
14.2 Vdc
GND
3.3 Vdc
14.2 Vdc
14.2 Vdc
GND
GND
GND
GND
NC
NC
NC
NC
GND
GND
GND
GND
GND
16.8MHz_RX
16.8MHz_RX_RTN
GND
GND
GND
GND
GND
GND
5 MHz/1 PPS
3.3 Vdc
3.3 Vdc
10
NC
NC
NC
3.3 Vdc
11
TxD
CTS
DTR
BRG
12
RTS
RxD
DSR
CD
13
NC
NC
NC
3.3 Vdc
14
NC
NC
SHUTDOWN_
SLEEP_
15
PA_ENABLE
NC
28.6 Vdc
14.2 Vdc
16
NC
NC
NC
3.3 Vdc
17
EXT_GPI_1_
EXT_GPI_2_
EXT_GPO_1_
EXT_GPO_2_
18
BAT_STAT_
MTR_STAT_
EXT_VFWD
EXT_VREV
19
SPI_M3
SPI_M2
SPI_M1
SPI_M0
20
SPI_ENABLE
SPI_MOSI
SPI_MISO
SPI_CLK
21
SPI_A2
SPI_A1
SPI_A0
WP_
22
NC
RxRESET_
NC
NC
23
NC
Clock_SyncB_
NC
NC
24
GND
GND
3.3 Vdc
3.3 Vdc
25
SSI_Data_D
SSI_CLK_D
SSI_FS_D
3.3 Vdc
26
SSI_Data_D_RTN
SSI_CLK_D_RTN
NC
3.3 Vdc
27
GND
GND
3.3 Vdc
3.3 Vdc
28
DSPIb_MOSI
DSPIb_CLK
DSPIb_EN_1
DSPIb_EN_2
29
DSPIb_MOSI_RTN
DSPIb_CLK_RTN
DSPIb_EN_3
NC
30
GND
GND
3.3 Vdc
3.3 Vdc
31
GND
SSI_Data_C
SSI_CLK_C
SSI_FS_C
32
GND
SSI_Data_C_RTN
SSI_CLK_C_RTN
NC
33
NC
Clock_SyncA_
NC
NC
34
GND
GND
3.3 Vdc
3.3 Vdc
35
SSI_Data_B
SSI_CLK_B
SSI_FS_B
3.3 Vdc
68P81095E02-D 12/12/2000
Row
36
SSI_Data_B_RTN
SSI_CLK_B_RTN
NC
3.3 Vdc
37
GND
GND
3.3 Vdc
3.3 Vdc
38
DSPIa_MOSI
DSPIa_CLK
DSPIa_EN_1
DSPIa_EN_2
39
DSPIa_MOSI_RTN
DSPIa_CLK_RTN
DSPIa_EN_3
NC
40
GND
GND
3.3 Vdc
3.3 Vdc
41
GND
SSI_Data_A
SSI_CLK_A
SSI_FS_A
42
GND
SSI_Data_A_RTN
SSI_CLK_A_RTN
NC
Coaxial
Description
Center
PA IN
Outer
GND
Coaxial
Description
Center
PA Feedback
Outer
GND
Coaxial
6 8 P 8 1 0 9 5E02- D
12/12/2000
Description
Center
Ethernet
Outer
GND
9-25
RX1 Connections
Table 9-9
Row
NC
GND
GND
Clock_SyncA_
GND
DSPIa_MOSI_RTN
DSPIa_CLK_RTN
DSPIa_EN_1
GND
DSPIa_MOSI
DSPIa_CLK
DSPIa_EN_2
GND
GND
GND
GND
14.2
SSI_CLK_A_RTN
SSI_FS_B
SSI_CLK_B_RTN
14.2
SSI_CLK_A
SSI_FS_A
SSI_CLK_B
14.2
GND
GND
GND
14.2
SSI_Data_A_RTN
GND
SSI_Data_B
GND
SSI_Data_A
GND
SSI_Data_B_RTN
10
GND
NC
NC
NC
11
3.3
RxRESET_
GND (ID0)
GND (ID1)
12
3.3
WP_
SPI_A0
SPI_A1
13
3.3
SPI_MISO
SPI_CLK
SPI_A2
14
GND
SPI_M0
SPI_ENABLE
SPI_MOSI
15
GND
SPI_M1
SPI_M2
SPI_M3
16
GND
GND
GND
NC
17
GND
16.8MHz_RX
GND
NC (WB switch)
18
GND
16.8MHz_RX_RTN
GND
NC (MC switch)
Table 9-10
9-26
Row
GND
GND
GND
RX3_EXP3
RX1_EXP3
GND
GND
GND
GND
GND
GND
RX2_EXP2
RX1_EXP2
GND
GND
GND
GND
GND
GND
RX Branch 1
RX1_EXP1
GND
GND
GND
68P81095E02-D 12/12/2000
RX2 Connections
Table 9-11
Row
NC
GND
GND
Clock_SyncA_
GND
DSPIa_MOSI_RTN
DSPIa_CLK_RTN
DSPIa_EN_3
GND
DSPIa_MOSI
DSPIa_CLK
DSPIa_EN_2
GND
GND
GND
GND
14.2
SSI_CLK_B_RTN
NC
NC
14.2
SSI_CLK_B
SSI_FS_B
NC
14.2
GND
GND
GND
14.2
SSI_Data_B_RTN
GND
NC
GND
SSI_Data_B
GND
NC
10
GND
NC
NC
NC
11
3.3
RxRESET_
NC (ID0)
GND (ID1)
12
3.3
WP_
SPI_A0
SPI_A1
13
3.3
SPI_MISO
SPI_CLK
SPI_A2
14
GND
SPI_M0
SPI_ENABLE
SPI_MOSI
15
GND
SPI_M2
SPI_M1
SPI_M3
16
GND
GND
GND
NC
17
GND
16.8MHz_RX
GND
NC (WB switch)
18
GND
16.8MHz_RX_RTN
GND
NC (MC switch)
Table 9-12
6 8 P 8 1 0 9 5E02- D
Row
GND
GND
GND
RX3_EXP2
RX2_EXP3
GND
GND
GND
GND
GND
GND
RX1_EXP1
RX2_EXP2
GND
GND
GND
GND
GND
GND
RX Branch 2
RX2_EXP1
GND
GND
GND
12/12/2000
9-27
RX3 Connections
Table 9-13
Row
NC
GND
GND
Clock_SyncB_
GND
DSPIb_MOSI_RTN
DSPIb_CLK_RTN
DSPIb_EN_1
GND
DSPIb_MOSI
DSPIb_CLK
DSPIb_EN_2
GND
GND
GND
GND
14.2
SSI_CLK_C_RTN
SSI_FS_D
SSI_CLK_D_RTN
14.2
SSI_CLK_C
SSI_FS_C
SSI_CLK_D
14.2
GND
GND
GND
14.2
SSI_Data_C_RTN
GND
SSI_Data_D
GND
SSI_Data_C
GND
SSI_Data_D_RTN
10
GND
NC
NC
NC
11
3.3
RxRESET_
GND (ID0)
NC (ID1)
12
3.3
WP_
SPI_A0
SPI_A1
13
3.3
SPI_MISO
SPI_CLK
SPI_A2
14
GND
SPI_M2
SPI_ENABLE
SPI_MOSI
15
GND
SPI_M1
SPI_M0
SPI_M3
16
GND
GND
GND
NC
17
GND
16.8MHz_RX
GND
18
GND
16.8MHz_RX_RTN
GND
NC (MC switch)
Table 9-14
9-28
Row
GND
GND
GND
RX1_EXP2
RX3_EXP3
GND
GND
GND
GND
GND
GND
RX2_EXP1
RX3_EXP2
GND
GND
GND
GND
GND
GND
RX Branch 3
RX3_EXP1
GND
GND
GND
68P81095E02-D 12/12/2000
RX4 Connections
Table 9-15
Row
NC
GND
GND
Clock_SyncB_
GND
DSPIb_MOSI_RTN
DSPIb_CLK_RTN
DSPIb_EN_3
GND
DSPIb_MOSI
DSPIb_CLK
DSPIb_EN_2
GND
GND
GND
GND
14.2
SSI_CLK_D_RTN
NC
NC
14.2
SSI_CLK_D
SSI_FS_D
NC
14.2
GND
GND
GND
14.2
SSI_Data_D_RTN
GND
NC
GND
SSI_Data_D
GND
NC
10
GND
NC
NC
NC
11
3.3
RxRESET_
NC (ID0)
NC (ID1)
12
3.3
WP_
SPI_A0
SPI_A1
13
3.3
SPI_MISO
SPI_CLK
SPI_A2
14
GND
SPI_M0
SPI_ENABLE
SPI_MOSI
15
GND
SPI_M3
SPI_M2
SPI_M1
16
GND
GND
GND
NC
17
GND
16.8MHz_RX
GND
NC (WB switch)
18
GND
16.8MHz_RX_RTN
GND
Table 9-16
6 8 P 8 1 0 9 5E02- D
Row
GND
GND
GND
RX1_EXP3
NC
GND
GND
GND
GND
GND
GND
RX2_EXP3
NC
GND
GND
GND
GND
GND
GND
RX3_EXP1
NC
GND
GND
GND
12/12/2000
9-29
PA Connections
Table 9-17
Row
SPI_ENABLE
GND
28.6 Vdc
GND
GND
28.6 Vdc
SPI_A0
GND
28.6 Vdc
GND
GND
28.6 Vdc
SPI_A1
GND
28.6 Vdc
GND
GND
28.6 Vdc
SPI_A2
GND
28.6 Vdc
GND
GND
28.6 Vdc
SPI_M0
GND
28.6 Vdc
10
GND
GND
28.6 Vdc
11
SPI_M1
GND
28.6 Vdc
12
GND
GND
28.6 Vdc
13
SPI_M2
GND
28.6 Vdc
14
GND
GND
28.6 Vdc
15
SPI_M3
GND
28.6 Vdc
16
GND
GND
28.6 Vdc
17
SPI_MISO
GND
28.6 Vdc
18
GND
GND
28.6 Vdc
19
SPI_MOSI
GND
28.6 Vdc
20
GND
GND
28.6 Vdc
21
SPI_CLK
GND
28.6 Vdc
22
GND
3.3 Vdc
28.6 Vdc
23
WP*
3.3 Vdc
28.6 Vdc
24
GND
GND
28.6 Vdc
25
PA_ENABLE
GND
28.6 Vdc
26
GND
14.2 Vdc
28.6 Vdc
27
GND
14.2 Vdc
28.6 Vdc
28
GND
14.2 Vdc
28.6 Vdc
29
GND
14.2 Vdc
28.6 Vdc
30
GND
28.6 Vdc
28.6 Vdc
31
GND
28.6 Vdc
28.6 Vdc
32
GND
28.6 Vdc
28.6 Vdc
Coaxial
9-30
Description
Center
PA IN
Outer
GND
68P81095E02-D 12/12/2000
Coaxial
Description
Center
PA Feedback
Outer
GND
Coaxial
Description
Center
PA RF OUT
Outer
GND
External Connections
Table: 9-21Backplane Coaxial and DC
Signal
P12
P13
EX Out
P14
Feedback
P15
Ethernet
P16
PA In
P17
PA Feedback
P18
PA RF OUT
P19
RX Branch 1
P20
RX Branch 2
P21
RX Branch 3
P24
5 MHz/1 PPS
)
Table: 9-22Backplane Alarm 25Pin Dsub (P23)
Alarm Signal
1
EXT_GPI_1_
EXT_GPO_1_
GND
EXT_GPI_2_
EXT_GPO_2_
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-31
Alarm Signal
7
8
9
10
GND
11
12
13
14
15
16
GND
17
BAT_STAT_
18
MTR_STAT_
19
EXT_VFWD
20
EXT_VREV
21
GND
22
GND
23
24
25
GND
RS-232 Signal
9-32
CD
RxD
TxD
DTR
GND
DSR
RTS
CTS
BRG*
68P81095E02-D 12/12/2000
PS Connections
Table: 9-24PS Power and Signal (P11)
Pin
Description
Pin
Description
Pin
Description
1
2
31
GND
32
3.3 Vdc
61
SPI_MOSI
GND
62
SPI_CLK
GND
33
GND
63
N.C.
4
5
28.6 Vdc
34
GND
64
N.C.
28.6 Vdc
35
GND
65
N.C.
28.6 Vdc
36
GND
66
N.C.
28.6 Vdc
37
GND
67
SPI_A0
28.6 Vdc
38
GND
68
SPI_A1
28.6 Vdc
39
GND
69
SPI_M2
10
28.6 Vdc
40
GND
70
SPI_M3
11
28.6 Vdc
41
GND
71
SPI_M1
12
28.6 Vdc
42
GND
72
SLEEP_
13
28.6 Vdc
43
GND
73
SPI_M0
14
28.6 Vdc
44
GND
74
WP_
15
28.6 Vdc
45
GND
75
SPI_A2
16
14.2 Vdc
46
GND
76
GND
17
14.2 Vdc
47
GND
77
GND
18
14.2 Vdc
48
GND
78
GND
19
14.2 Vdc
49
GND
20
14.2 Vdc
50
GND
21
14.2 Vdc
51
GND
14.2 Vdc
52
GND
23
14.2 Vdc
53
GND
24
3.3 Vdc
54
NC (FAN CONTROL)
25
3.3 Vdc
55
N.C.
26
3.3 Vdc
56
N.C.
27
3.3 Vdc
57
SHUTDOWN_
28
3.3 Vdc
58
NC (Power sharing)
29
3.3 Vdc
59
SPI_ENABLE
30
3.3 Vdc
60
SPI_MISO
6 8 P 8 1 0 9 5E02- D
12/12/2000
9-33
9-34
Pin
Description
Description
Pin
+ BATTERY
+ BATTERY
+ BATTERY
+ BATTERY
- BATTERY (RTN)
- BATTERY (RTN)
- BATTERY (RTN)
- BATTERY (RTN)
68P81095E02-D 12/12/2000
6 8 P 8 1 0 9 5E02- D
Signal Name
Description
28.6 Vdc
14.2 Vdc
3.3 Vdc
GND
Station Ground
RX Branch 1
50
RX Branch 2
50
RX Branch 3
50
RX1_EXP1
50
RX1_EXP2
50
RX1_EXP3
50
RX2_EXP1
50
RX2_EXP2
50
RX2_EXP3
50
RX3_EXP1
50
RX3_EXP2
50
50
RX3_EXP3
5 MHz/1 PPS
SPI_ENABLE
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_A0
SPI_A1
SPI_A2
SPI_M0
SPI_M1
SPI_M2
SPI_M3
WP_
PA_ENABLE
SLEEP_
SHUTDOWN_
CD
RxD
RS232 RX Data
12/12/2000
Special
9-35
9-36
Signal Name
Description
TxD
RS232 TX Data
DTR
DSR
RTS
CTS
Special
BRG
RxRESET_
16.8MHz_RX
differential
16.8MHz_RX_RTN
differential
Clock_SyncA_
Clock_SyncB_
SSI_Data_A
differential
SSI_Data_A_RTN
differential
SSI_Data_B
differential
SSI_Data_B_RTN
differential
SSI_Data_C
differential
SSI_Data_C_RTN
differential
SSI_Data_D
differential
SSI_Data_D_RTN
differential
SSI_CLK_A
differential
SSI_CLK_A_RTN
differential
SSI_CLK_B
differential
SSI_CLK_B_RTN
differential
SSI_CLK_C
differential
SSI_CLK_C_RTN
differential
SSI_CLK_D
differential
SSI_CLK_D_RTN
differential
SSI_FS_A
SSI_FS_B
SSI_FS_C
SSI_FS_D
DSPIa_En_1
DSPIa_En_3
DSPIa_En_2
DSPIb_En_1
DSPIb_En_3
DSPIb_En_2
DSPIa_MOSI
differential
DSPIa_MOSI_RTN
differential
DSPIb_MOSI
differential
68P81095E02-D 12/12/2000
6 8 P 8 1 0 9 5E02- D
Signal Name
Description
Special
DSPIb_MOSI_RTN
differential
DSPIa_CLK
differential
DSPIa_CLK_RTN
differential
DSPIb_CLK
differential
DSPIb_CLK_RTN
differential
MTR_STAT_
BAT_STAT_
Battery Status
EXT_VFWD
EXT_VREV
EXT_GPO_1_
EXT_GPO_2_
EXT_GPI_1_
EXT_GPI_2_
NC
Not connected
12/12/2000
reserved
9-37
9-38
68P81095E02-D 12/12/2000
Appendix A
A Acronyms
A/D
Analog-to-Digital
CC
Control Cabinet
Amperes
CD
Carrier Detect
AC
Alternating Current
cd
change directory
ACT
active
CLK
Clock
ADA
CLT
Controller
AGC
cm
centimeter
AIC
CMOS
AIS
ANSI
CPU
ASCII
CSMA/CD
ASIC
CTI
Aux
auxiliary
CTL
avg
average
CTS
Clear-to-Send
AWG
D/A
Digital-to-Analog
bd
baud
DAP
BDM
DB-15
15-pin D-subminiature
BER
DB-9
9-pin D-subminiature
BERT
dB
Decibel
BMR
dBc
BNC
Baby N Connector
dBm
BPV
Bipolar Variation
DC
Direct Current
BR
Base Radio
DCE
BRC
DCSPLY
DC Supply
BSC
DDM
BTU
deg
degree
BW
bandwidth
DIN
Deutsche Industrie-Norm
C/N + 1
DIP
div
division
4/1/2000
A-39
Appendix A Acronyms
DMA
HSO
DOP
Dilution of Precision
HVAC
Heating/Ventilation/Air Conditioning
DRAM
Hz
Hertz
DSP
I/O
Input/Output
DTE
IC
Integrated Circuit
DTTA
iDEN
DVM
IEEE
E1
IF
intermediate frequency
EAS
iMU
E-NET
Ethernet
in
inches
EBTS
in
injection
EGB
ISA
EIA
iSC
EMI
Electro-Magnetic Interference
kg
kilogram
EPROM
Erasable Programmable
Memory
kHz
kiloHertz
LAN
EEPROM
LANIIC
ERFC
Expansion RF Cabinet
LAPD
ESI
lbs
pounds
ESMR
LDM
EX
Exciter
LED
FB
feedback
LFM
FCC
LIU
FIFO
First-In, First-Out
LLC
FNE
LNA
freq
frequency
LO
Local Oscillator
FRU
LOS
Loss of Signal
GFI
MAU
GND
ground
max
maximum
GPS
MC
Multicoupler
GPSR
MGB
HDLC
MGN
Multi-Grounded Neutral
HSMR
MHz
MegaHertz
min
minimum
A-40
Read
Only
68P81095E06- B
4/1/200 0
Appendix A Acronyms
min
minute
PS
Power Supply
MISO
PSTN
mm
millimeter
PVC
Polyvinyl Chloride
MMI
Man-Machine-Interface
pwr
power
MOSI
Master Out/Slave In
QAM
MPM
QRSS
MPS
Qty
Quantity
MS
Mobile Station
R1
Receiver #1
ms
millisecond
R2
Receiver #2
MSC
R3
Receiver #3
MSO
RAM
MST
RCVR
Receiver
mV
milliVolt
Ref
Reference
mW
milliWatt
RF
Radio Frequency
N.C.
Normally Closed
RFC
RF Cabinet
N.O.
Normally Open
RFDS
RF Distribution System
NEC
RFS
RF System
NIC
ROM
no.
number
RPM
NTM
RSSI
NTWK
Network
RTN
Return
OMC
RU
Rack Unit
OSHA
Rx
Receive
PA
Power Amplier
RXDSP
PAL
SCI
PC
Personal Computer
SCON
PCCH
SCRF
PDOP
pF
picoFarad
SCSI
PLL
sec
second
P/N
Part Number
SGC
P/O
Part Of
SINAD
ppm
SMART
PPS
6 8 P 8 1 095E06- B
4/1/2000
A-41
Appendix A Acronyms
SPI
Vac
SQE
VCO
SRAM
VCXO
SRC
Subrate Controller
Vdc
SRI
VFWD
SRIB
VME
Versa-Module Eurocard
SRRC
Vp-p
Voltage peak-to-peak
VREF
SRSC
VSWR
SS
Surge Suppressor
Watt
SSC
WDT
Watchdog Timer
SSI
WP
Write Protect
ST
Status
WSAPD
STAT
Status
Std
Standard
S/W
Software
T1
TB
Terminal Board
TDM
telco
telephone company
SCON
TISIC
TSI
TSI
TTA
Tower-Top Amplier
TTL
Tx
Transmit
TXD
Transmit Data
TXDSP
Txlin
Tranlin IC
typ
typical
UL
Underwriters Laboratories
A-42
Volts
68P81095E06- B
4/1/200 0
Index
Appendix A Index
B
Base Radio
40W, 800 MHz Power Amplifier TLF2020 (version 1580A)
Testing/verification (Base Radio section) ............................................................................10-11, 10-23
40W, 800 MHz Power Amplifier TLF2020 (version 1580B)
Testing/verification (Base Radio section) ............................................................................10-11, 10-23
60W, 900 MHz Power Amplifier CLN1355A
Testing/verification (Base Radio section) .......................................................................................10-19
70W, 800 MHz Power Amplifier TLN3335 (version CTF1040)
Testing/verification (Base Radio section) .........................................................................................12-2
Testing/verification (Base Radio section) .......................................................................................10-15
70W, 800 MHz Power Amplifier TLN3335 (version CTF1050)
Testing/verification (Base Radio section) .........................................................................................12-2
Testing/verification (Base Radio section) .......................................................................................10-15
800 MHz, 3X Receiver CLN1283 and 900 MHz, 3X Receiver CLN1356
Diversity uses and cautions (Base Radio section).....................................................................9-3, 9-12
Overview (Base Radio section) ....................................................................................................9-1, 9-12
Replacement compatibility (Base Radio section) ..............................................................................9-2
Theory of operation (Base Radio section) ..................................................................................9-5, 9-14
AC Power Supply
Controls and indicators (Base Radio section) .....................................................................................8-1
Overview (Base Radio section) .............................................................................................................8-1
Theory of operation (Base Radio section) ...........................................................................................8-3
Backplane connector information (Base Radio section) ...........................................................10-35, 11-22
Base Radio Controller
Controls and indicators (Base Radio section) ............................................................................2-3, 2-12
Theory of operation (Base Radio section) ..................................................................................2-5, 2-15
Base Radio/Base Radio FRU replacement procedures (Base Radio section)..........................10-5, 11-5
Controls and indicators (Base Radio section) ....................................................................................1-5, 1-10
DC Power Supply (Base Radio section)
Controls and indicators ....................................................................................................................7-1, 7-5
Description .........................................................................................................................................7-1, 7-4
Theory of operation ..........................................................................................................................7-3, 7-6
Exciter
Description (Base Radio section) ...................................................................................................5-1, 5-7
Theory of operation (Base Radio section) ....................................................................................5-3, 5-8
Overview (Base Radio section) ................................................................................................................1-4, 1-9
Performance specifications (Base Radio section) .............................................................................1-5, 1-10
Station verification procedures (Base Radio section) ..................................................................10-9, 11-10
Theory of operation (Base Radio section)...........................................................................................1-7, 1-12
Troubleshooting (Base Radio section) ...............................................................................................10-1, 11-1
Index-1
Index
M
Maintenance Philosophy (Foreword) ................................................................................................................... x
Motorola Customer Support Center
Support Center address and phone number (Foreword) ........................................................................... x
P
Purpose of Manual (Foreword)............................................................................................................................. ix
Index-2
68P81095E69-D
11/10/2000