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Synopsys ASIC Design Flow

1) The document provides a tutorial on Synopsys' ASIC design flow, including the front-end design flow using Design Compiler and the back-end design flow using IC Compiler. 2) The Design Compiler tutorial describes how to set up the tool, analyze and elaborate a design, apply constraints, perform synthesis, and view reports. 3) The IC Compiler tutorial describes how to set up the tool, import the synthesized design, define power rails, perform floorplanning, placement, routing, extraction, and output the final GDS file.

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Nishant Singh
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
852 views

Synopsys ASIC Design Flow

1) The document provides a tutorial on Synopsys' ASIC design flow, including the front-end design flow using Design Compiler and the back-end design flow using IC Compiler. 2) The Design Compiler tutorial describes how to set up the tool, analyze and elaborate a design, apply constraints, perform synthesis, and view reports. 3) The IC Compiler tutorial describes how to set up the tool, import the synthesized design, define power rails, perform floorplanning, placement, routing, extraction, and output the final GDS file.

Uploaded by

Nishant Singh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Synopsys ASIC Design Flow

FRONT-END DESIGN FLOW


Synopsys VCS Tutorial
Running Verilog Compiler Simulator (VCS)
1. Open the terminal window in your working directory.
2. Type this command: source ~CadTools/bashrc/bashrc615 and then press enter.
3. Launch VCS: vcs <module1.v module2.v.... moduleN.v> <testbench.v> -debug_all
4. For simulation execute the following command: ./simv -gui
5. This will open Discovery Visualization Environment (DVE) window.
i)

In hierarchy window, select the testbench module and with a right click of the mouse,
click on Dump.

ii) Start simulation by pressing F5 or Start/Continue button.


iii) To see the waveforms, select the input/output pins and with a right click select
Add to Waves New Wave View.

Synopsys Design Compiler Tutorial


Running Design Compiler (DC)
This Tutorial describes how to use Synopsys Synthesis tool, Design Compiler, to generate a synthesized
netlist of a design. The figure below illustrates the basic DC toolflow and how it fits into the larger
ASIC Design Flow.

To start design synthesis create new folder named as syn and copy your constraint and Verilog/VHDL
module files in it.
1. Launch DC by command dc_shell gui This will open Design Vision window.

Library Setup
File > Setup
Search path: /designpackages/scl_pdk/stdlib/fs120/liberty

Link library:
/designPackages/design_installer/scl/scl_pdk/stdlib/fs120/liberty/lib_flow_ff/tsl18fs120_s
cl_ff.db
/designPackages/design_installer/scl/scl_pdk/stdlib/fs120/liberty/lib_flow_ss/tsl18fs120_s
cl_ss.db
Target library: :
/designPackages/design_installer/scl/scl_pdk/stdlib/fs120/liberty/lib_flow_ff/tsl18fs120_s
cl_ff.db
The screenshot below shows the Application Setup window.

Analysis and Elaboration


The analysis command checks your HDL design for proper syntax and synthesizable logic, and then
translates this design into an intermediate format inside the specified WORK directory. Elaboration
then takes this intermediate representation and begins the task of turning your RTL description into
actual hardware.
1. File > Analyze. Select all the HDL models required for the design. Select Format >
2. Elaborate your design by File > Elaborate. This will call Elaborate Designs window where
you make topmodule as your current design.

Removing Multiple Instances


If your design references has any design more than once, you must resolve these multiple instances
before running the compile command. You can resolve multiple instances by using any of the following
method:
1. Uniquify method:
This method used the uniquify command to create a copy of the design for each instance.
2. Ungroup method:

This method uses the ungroup command to remove the hierarchy.


In the GUI window, select the most top design of the hierarchy.
Select Hierarchy > Ungroup. The following window will popup. Keep the settings as shown.

Constraints
DC makes a best effort attempt to synthesize your design while still metting the two types of constraints:
user specified constraints and design rule constraints. User specified constraints can be used to
constrain the clock period as well as arrival of certain input signals, the drive strength of the input
signals, and the capacitive load on the output signals. Design rule constraints are fixed constraints which
are specified by the standard cell library. For example, there are restrictions on the loads specific gates
can drive and also on the transition times of certain pins.
The constraints in your design can be written in a TCL script.
File > Execute Script <user_constraint_file.tcl>
Alternatively, in GUI mode the clock constraints can be specified by
1. Schematic > New Schematic View
2. In the schematic select the clock port.
3. Attributes > Specify Clock

Synthesis
The compile_ultra command will syhthesize your design into a gate level netlist and during the
compilation process report how the design is being optimized. Some of the steps you should observe
DC performing are technology mapping, delay optimization and area reduction. Alternatively, in the
GUI do the following:
Design > Compile Ultra

To view the schematic of the synthesized design:


Schematic > New Schematic View

Reports
We have now finished the entire synthesis process, but need to analyze the results of the
synthesis to determine if we need to change our code to achieve our goals, or verify that
goals have been met. These reports can be used to offer comparisons of several synthesis
attempts.

1. Design > Report Area


2. Design > Report Power
3. Timing > Report Timing Path
The following screenshot illustrates the timing path information.

Save the Design


Finally, save the synthesized design in Verilog format by going to File > Save as. Also, save the
Synopsys Design Constraint (SDC) and Standard Delay Format (SDF) files.
File > Save As..

This completes the Design Compiler tutorial.

BACK-END DESIGN FLOW


Synopsys IC Compiler Tutorial
Running IC Compiler
To start physical synthesis, you will need to source the bashrc script and launch IC Compiler.
1. Open the terminal window in your working directory.
2. Type this command: source ~CadTools/bashrc/bashrc615 and then press enter.
3. Launch IC Compiler: icc_shell gui

Setting up the Work Environment


Setup the logic library, physical library, timing and parasitic files by going to:
1. File > Setup > Application Setup. This step is same as the one done in DC Compiler.
2. To setup the TLU+ files use the following command.
icc_shell > set_tlu_plus_files
-max_tluplus
/designPackages/design_installer/scl/scl_pdk/tlup/RCE_TS18SL_STA
R_RCXT_4M1L_USG.tlup
-min_tluplus
/designPackages/design_installer/scl/scl_pdk/tlup/RCE_TS18SL_STA
R_RCXT_4M1L_USG.tlup
3. Creating Milkyway Library
File > Create Library.
New Library Path: Your default working directory path.
New Library Name: <yourdesignname>.mw {example: counter.mw}
Technology File: /designPackages/design_installer/scl/scl_pdk/tffile/icc.tf
Input reference libraries:
/designPackages/design_installer/scl/scl_pdk/fs120/mw/fs120_scl
Tick on the Open Library and then click OK.

Adding your design


Now add your synthesized Verilog files for place and route. You can do this by going to:
1. File > Import Designs..

This will bring up the Layout window.

2. Read the timing constraints for the design by using the read_sdc command (or by
choosing File > Import > Read SDC in the GUI).
3. Save the design.
icc_shell > save_mw_cel as <yourdesignname>

Define the Power Rails


Connect the Power and Ground pins with the command below:
icc_shell > derive_pg_connection -power_net {VDD} -ground_net {VSS} -power_pin
{VDD} -ground_pin {VSS} -create_ports top
icc_shell > derive_pg_connection -power_net {VDD} -ground_net {VSS} tie

Floorplanning
Create the floorplan: Floorplan > Create Floorplan
Put the values as shown in the figure below or as per your requirement.

Add Power Rings


Select Preroute > Create Rings..
The following window will popup. Insert values as shown in figure below or else type the
following command in the command window.
icc_shell > create_rectilinear_rings -around core -nets {VDD VSS} -offset {0.5 0.5} -width
{1 1} -space {0.5 0.5} -layers {M3 TOP_M}

The layout window will look as shown in figure below.

Preroute Instances
In the layout window, select Preroute > Preroute Instances.
Follow the settings as shown in the figure below and Click OK.

Preroute Standard Cells


Select Preroute > Preroute Standard Cells and follow the settings as mentioned below.

Placement
Place your standard cells: Placement > Core Placements and Optimization
Follow the setting as shown in below figure.

Clock Tree Synthesis


Next we need to do clock tree synthesis:
Clock > Core CTS and Optimization
Following window will popup. Tick on the available options as per your need.

Make sure to check your timing reports before continuing. If you have hold time errors, you
will need to fix them now.
icc_shell > report_clock_tree
icc-shell > report_timing

Routing
Select Route > Core Routing and Optimization
Follow the figure as given below and select the various options depending on your design
requirement.

Extract RC
For parasitic extraction: Route > Extract RC.

Filler Insertion
Now that your design is routed, it is time to add filler cells. Execute the following command:
icc_shell > insert_stdcell_filler -respect_keepout -cell_without_metal "feedth9 feedth3
feedth" -cell_with_metal "feedth3 feedth feedth9" -connect_to_power {VDD} connect_to_ground {VSS}

Stream Out the final GDS


Finally, save your design as a GDS file: File > Export > Write Stream
This completes the tutorial describing Automatic Placement and Routing using Synopsys IC
Compiler.

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