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SV MiniProject Part 2

The document provides instructions for fixing bugs in RTL code, running logic synthesis, and reporting delay and area numbers at two design points: minimum delay and minimum area. It describes setting up a working directory with the necessary files, editing the setup and constraints files with design-specific information, running the synthesis tool to generate reports on gates, area, and timing, and reviewing the synthesized netlist output file.

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Pushtivardhan Soni
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37 views3 pages

SV MiniProject Part 2

The document provides instructions for fixing bugs in RTL code, running logic synthesis, and reporting delay and area numbers at two design points: minimum delay and minimum area. It describes setting up a working directory with the necessary files, editing the setup and constraints files with design-specific information, running the synthesis tool to generate reports on gates, area, and timing, and reviewing the synthesized netlist output file.

Uploaded by

Pushtivardhan Soni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

E0-284:

Mini Project Part 2: Bug Fixing


+ Logic Synthesis
Due Date: October 12 2015.


1. Fix the bugs in your HoG RTL code and make it run with the
provided test bench. Once all bugs are cleared, submit as
before.

2. Once all bugs are fixed, run the logic synthesis tool to
synthesize your design at two design points:

a. Min Delay point
b. Min Area point

Report the delay and area numbers for both the points.


Logic Synthesis Procedure: By Sreejith S.

Create your working directory. For this example, we will assume that
your design name is "counter"

mkdir ~/counter_synthesis
cd ~/counter_synthesis

Replace counter with <your_design_name>
Copy the required setup files and scripts to your working directory.
This includes the following folders and files.
/lib
setup.g
constraints_top.g
template.tcl
Make a folder /rtl for your design rtl files. (dont put test bench files).

The directory structure for the working folder should be
Counter_synthesis
o rtl/

o
o
o
o

lib/
constraints_top.g
setup.g
template.tcl


vim setup.g (to edit this file), or you can open in gedit.

On line number 11, please specify your rtl files. By default, the line
would look like this

set FILE_LIST{mem.v top.v mux_2to1.v phase_inc.v}

Change it to

set FILE_LIST {<your_rtl_file_1.v>
<your_rtl_file_2.v>, etc..}

On line number 16, you need to specify your top module name. By
default, the line would look like this

set DESIGN
top

Change it to

set DESIGN
<your_top_module_name>

Close the file setup.g

open constraints_top.g (vim or gedit)

Change line 1 as :

create_clock -name clk -period 10 -waveform {0 5}
[get_ports "clk"]

Change to

create_clock -name clk -period 10 -waveform {0 5}
[get_ports "<your_clock_port_name>"]

(this generates a clock of 10ns period, 50% duty cycle, give the clock
of your requirement)


Modify lines 7 to 12 as (add or delete lines wherever necessary) (add
all input ports of your top module)

[get_ports "<your_input_port_names>"]

Modify line 14 as (add or delete lines wherever necessary) (add all
output ports of your top module)

[get_ports "<your_output_port_names>"]

Close constraints_top.g.

To start RC compiler,

csh
source /home/smart/word_cad_65nm/cadence.cshrc
rc
rc:/> source setup.g
rc:/> source template.tcl
(This is your main synthesis script)



Your design should get synthesized after this step if everything was
done right.

rc:/> exit

Reports_<timestamp>, will have your synthesis reports. You can go
through the following reports to see a few metrics of your design.
your_top_module_name_gates.rpt
your_top_module_name_area.rpt
your_top_module_name_C2C_post_incr.rpt
These files will provide details on gates used, area occupied
and timing details.

Outputs_<timestamp>, would have the output files after synthesis.
<your_top_module_name.v> is the synthesized netlist. You should
have a look at this file. This is the netlist that would be taken forward
for Place and Route.

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