Link Layer
Sue Vining
Principal USB Architect
Texas Instruments
Agenda
g
General Terminology
SuperSpeed System Topology
Link Layer Functions
Li k T
Link
Training
i i & St
Status
t St
State
t Machine
M hi (LTSSM)
Link Layer Building Blocks
Packet Construction by Link Layer
Header Packet Exchange
Link Errors During Bit Transfer: Detection, Response & Count
Initialization for HP Integrity & FC after Link Training
Link Power State Transitions
Disconnect Detection
Inband Reset
Summary
General Terminology
gy
8b/10b encoded control character or data
byte
K-symbol
8b/10b encoded control character
D symbol
D-symbol
8b/10b encoded data byte
Ordered Set
Predefined symbol sequence
Header Packet (HP) Fixed size packet that contains information
consumed
db
by lilink
k or h
hostt or d
device
i
Data Packet (DP)
Compound packet containing
header (DPH) and variable size data
payload
l d (DPP)
USP
Upstream-facing port
DSP
Downstream-facing port
LFPS
Low frequency period signaling
Symbol
SuperSpeed
p
p
System
y
Topology
p gy
Link Layer
y Functions
Link ttraining
a
g co
control
to a
and
d coo
coordination
d at o with
t link pa
partner
t e
Build and transmit packets
Receive and unpack packets
Ensure reliable header packet exchange
Header packet (HP) integrity assurance
Header packet flow control (FC)
Robust p
packet framing
g
Perform entry & exit sequences for low power states
Handle link errors during all functions
Aid disconnect detection by
y all ports
p
Initiate or detect inband reset
Link Training & Status State
Machine
M hi (LTSSM)
SS.Disabled
Rx termination removed
SS.Inactive
Error and inactive state
Rx.Detect
Look for termination resistors
LFPS-based inband reset
Polling
Training, RxEQ
Compliance
p
Test Transmitter compliance
U0
Normal operational state
U1, U2, U3
Lower power, longer latency
Recovery
Retrain. No RxEQ
Loopback
Test mode
Hot Reset
TS2 based (SS) inband reset
6
SS.Inactive
Function
F
i
Term resistors present
DSP or self-powered USP
periodically
i di ll checks
h k ffor
loss of far-end Rx
termination
Purpose
Software or Warm Reset
needed to resolve USB
3.0 error conditions
SS.Disabled
Function
Term resistors removed
Default state for self-powered
p
devices
DSP exits to Rx.Detect if directed
USP exits to Rx.Detect when
VBUS transitions to valid or
A USB 2.0 reset is detected
Purpose
Allow transition to USB 2.0 for peripheral devices only
A downstream port will transition to SS
SS.Disabled
Disabled if the hubs
hub s
upstream port does not detect a far-end receiver
8
Rx.Detect
Initial power
power-on
on state
for DSP and for USP of
bus-powered devices
Detects far-end
far end
termination resistors
Peripheral USP times
out to USB 2.0
(SS.Disabled) after 8
unsuccessful Rx
Detection cycles
R
Rx.Detect.Reset
D t tR
t allows
ll
synch of warm reset
pulse (USP waits for
reset to complete)
Polling
g
10
Polling
g
Link training after Rx.Detect
Polling.LFPS
g
Sync entry to RxEQ by removing up to 12 ms skew from Rx.Detect
Establish LFPS DC operating point within 80us,
Establish SS DC operating point upon exit
Time
Ti
outt to
t Compliance
C
li
St
State
t when
h jjustt resistors
i t
tto ground
d
Polling.RxEQ
Send TSEQ ordered sets.
Train Rx Equalizer
Lane Polarity
Bit and Symbol Lock
Polling.Active
Send TS1 ordered sets
Sync entry to Config from RxEQ
Polling.Config
Send TS2 ordered sets to complete SS Handshake
Polling.Idle
Decode link configuration field & exit to U0
11
Loopback
p
For bit error rate test (BERT)
Master initiated as directed
Master function is optional &
implementation specific
Slave function is required
Two modes
Traditional
T diti
l
BERT with scrambled logical idle
Master sets Loopback bit in TS2 to
initiate from Recovery or Polling
Master
M t sends
d 8b10b with
ith SKPs
SKP
Slave supports the BERT protocol
Slave responds to BERT
commands
Slave checks the incoming data for
the loopback data pattern
Slave re-transmits the 8b10b but
with
Lane polarity inversion (if
necessary)
Clock tolerance compensation (as
necessary)
Exits to Rx.Detect
12
Link Layer Building Blocks:
Li k C
Link
Commands
d
Link commands (LCs) enable all link layer functions
other than link training control and inband reset
Robust design of link commands
LCSTART is a 4-symbol ordered set
Start of link command word is deterministic with any 3 symbols
No
N end
dd
delimiter
li it iis needed
d d
Bogus LCs not created due to even 2 corrupted symbols
The link command word is sent twice
Detection of missing LCs is ensured by
Timers, with fixed timeout values defined in standard
Sequence checks
13
Link Layer Building Blocks:
Li k C
Link
Command
d St
Structure
t
Fixed 8-Symbol size:
4 K-Symbols
K Symbols at start followed by two
two-byte
byte Link Command Word(LCMD) repeated
Valid receipt: 3 of 4 K-Symbols & both LCMDs are valid & identical {ECN}
Link Command Word:
Total content: 2 scrambled bytes
5-bit CRC-5 protects 11-bit link command information
14
Link Layer Building Blocks:
Li t off Link
List
Li k C
Commands
d
HP Integrity LGOOD_n (n=0 to 7), LBAD, LRTY
HP Flow Control LCRD_x (x=A,B,C,D)
Link Power Management LGO_U1, LGO_U2,
LGO_U3, LAU, LXU, LPMA
Announce Presence in U0 LUP, LDN
DSP: detect disconnect by loss of LUP
USP: [ECN] detect disabled by loss of LDN
15
Link Layer Building Blocks:
HP St
Structure
t
for
f Integrity
I t it A
Assurance
Robust HP framing
4-symbol ordered set, HPSTART, similar to LCSTART
No end framing needed or used
HPs have 2 CRCs & a header sequence number (HSEQ#)
HSEQ# is independent of the transaction layer data sequence
number and ranges from 0 to 7
Correct receipt of HPs is checked using the 2 CRCs
Correct receipt of HP is acknowledged using the LGOOD_n link
command, where n=Rx HSEQ#
Incorrect receipt of HP is acknowledged using LBAD link command
Every HP must be acknowledged with LGOOD
LGOOD_n
n or LBAD
Missing HPs detectable by a skipped HSEQ#
Every receiver must advertise its expected HSEQ# at entry to U0
Advertised HSEQ#
S Q# must be accepted by link even during
Polling.Idle or Recovery.Idle
16
Link Layer Building Blocks:
HP St
Structure
t
for
f Integrity
I t it A
Assurance
Link Control Word:
Integrity
I t it assurance
Header Sequence #
CRC-5: for other 11 bits
Hub forwarding support
Hub Depth, Delayed, Deferred
Header Packet:
20 symbol structure
4 K-symbol start framing
12 Byte end-to-end header content
CRC-16
CRC
16 over the 12 Byte header
2 Byte Link Control Word
17
Packet Construction by
Link
Li k L
Layer
Link Layer constructs HPs by adding
Link
Li k C
Controll W
Word
d ((may b
be updated
d db
by lilink
k llayer))
Header sequence # is unique to each link
Hub forwarding support values must be maintained, if set
CRC-16, if not added by higher layer
HPSTART (framing)
Link Layer constructs data packets (DPs) by
Constructing header (DPH) as defined above
Constructing data payload (DPP) by adding start
(DPPSTART) and end (DPPEND or DPPABORT) framing
CRC is added by higher layer
Combining DPH and DPP back-to-back (no gap)
No gap is required between packets sent by hubs or
peripherals
18
HP Exchange:
Link
Li k Fl
Flow C
Control
t lB
Background
k
d
Link flow control (FC) is only for HPs
HPs, not data payload
Every receiver must advertise its 4 initial credits (Local Rx
Header Buffer Credit) to its partners transmitter using LCRD_x
link commands
Transmitter needs at least 1 credit from partner (Remote Rx
Header Buffer Credit) to send a header packet
C
Credit
dit iis returned
t
d whenever
h
a packet
k t iis processed,
d
independently of when it was received relative to other packets
LCRD_x index(x:A,B,C,D) is solely to detect missing LCRD_x
Delayed processing of any packet does not prevent credit return for
subsequent packets
Each LCRD_x always returns exactly 1 header packet credit
19
HP Exchange:
g Terminology
gy
Link partner
Device at one end of link
HP Rx
Link partner receiving an HP
R H
Rx
Header
d B
Buffer
ff
Received & unprocessed HP storage
Local Rx Header Buffer Credit
Available space to receive HPs
HP s in Rx
Header Buffer
Rx Header Sequence Number
Expected in next received HP
Rx LCRD_x index
Assigned to next LCRD_x sent
HP Tx
Link partner transmitting a header packet
Tx Header Buffer
Transmitted & unacknowledged HP storage
Remote Rx Header Buffer Credit
C di to transmit
Credit
i HP
HPs
Tx Header Sequence Number
Assigned to next new HP
ACK Tx Header Sequence Number
Points to oldest HP in Tx Header Buffer
Remote Rx LCRD_x index
Expected index of next received LCRD_x
PENDING_HP_TIMER
3 us timer to check for missing acknowledgment
CREDIT_HP_TIMER
5 ms timer to check for missing credit return
20
HP Exchange:
g Initial Conditions
The initial conditions for the following
illustration of HP Exchange happen to
match the reset state but could be
random
Initial and final exchange
g conditions of
an idle state were chosen to allow a
simpler sequence
All buffers are empty
No timers are running
21
HP Exchange:
g No Errors
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Tx Header Sequence Number = 0
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 4
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = 0,IDLE
22
HP Exchange:
g No Errors
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#=0
HP,
HSEQ# 0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 4
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = 0,IDLE
23
HP Exchange:
g No Errors
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
HP HSEQ#=0
HP,
HSEQ# 0
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = running
CREDIT_HP_TIMER = running
24
HP Exchange:
g No Errors
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
HP HSEQ#
HP,
HSEQ#=0
0, good CRC
CRCs
s
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 1
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 3
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = running
CREDIT_HP_TIMER = running
25
HP Exchange:
g No Errors
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
Empty
Empty
Empty
Empty
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 1
Rx Header Sequence Number = 1
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 3
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = running
26
HP Exchange:
g No Errors
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
Empty
Empty
Empty
Empty
Processing complete
complete, Empty
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 1
Rx Header Sequence Number = 1
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = running
27
HP Exchange:
g No Errors
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 1
Rx Header Sequence Number = 1
Remote Rx Header Buffer Credit = 4
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = B
Rx LCRD_x index = B
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = 0,IDLE
28
HP Exchange:
g Retry
y
The following sequence has both
An initial header packet receive error and
A successful retry using a sequence of
Header packet transmit,
LBAD,
LRTY,
Header packet retransmit,
LGOOD_n and
LCRD_x
29
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Tx Header Sequence Number = 0
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 4
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = 0,IDLE
30
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#=0
HP,
HSEQ# 0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 4
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = 0,IDLE
31
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
HP HSEQ#=0
HP,
HSEQ# 0
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = running
CREDIT_HP_TIMER = running
32
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
HP HSEQ#
HP,
HSEQ#=0
0, bad CRC
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = running
CREDIT_HP_TIMER = running
33
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = 0,IDLE
34
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = 0,IDLE
35
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
HP HSEQ#=0
HP,
HSEQ# 0
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 0
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = running
CREDIT_HP_TIMER = running
36
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
HP HSEQ#
HP,
HSEQ#=0
0, good CRC
CRCs
s
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 0
Rx Header Sequence Number = 1
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 3
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = running
CREDIT_HP_TIMER = running
37
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
Empty
Empty
Empty
Empty
HP HSEQ#
HP,
HSEQ#=0
0
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 1
Rx Header Sequence Number = 1
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 3
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = running
38
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
Empty
Empty
Empty
Empty
Processing complete
complete, Empty
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 1
Rx Header Sequence Number = 1
Remote Rx Header Buffer Credit = 3
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = A
Rx LCRD_x index = A
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = running
39
HP Exchange:
g Retry
y
Link Partner HP Tx
Link Partner HP Rx
Tx Header Buffer
Rx Header Buffer
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Tx Header Sequence Number = 1
ACK Tx Header Sequence Number = 1
Rx Header Sequence Number = 1
Remote Rx Header Buffer Credit = 4
Local Rx Header Buffer Credit = 4
Remote Rx LCRD_x index = B
Rx LCRD_x index = B
PENDING_HP_TIMER = 0,IDLE
CREDIT_HP_TIMER = 0,IDLE
40
Link Errors During Bit Transfer:
Detection,
D t ti
R
Response & C
Countt
Packet Framing Errors:
Receiver ignores
g
insufficiently
y framed p
packets
Detected by Pending_HP_Timer Go to Recovery
Header Sequence Number Error:
Get a Header Sequence Number that is not expected Go to Recovery
Possible consequence of packet framing error observed on subsequent HP
Packet CRC Errors:
Header Packet is Retried up to 2 times
Header Packet has CRC Error on 3rd attempt Go to Recovery
Training Sequence Error:
Timeout from Polling or Recovery
Timeout from Recovery is a serious error that requires SW intervention to fix
Missing Link Command:
Go to Recovery if not LPMA
Corrupt Link Command:
Ignore
Link Error Count is incremented by the downstream port each time link
enters Recovery due to an error
41
Initialization for HP Integrity & FC
Aft Link
After
Li k Training
T i i
Advertise expected Rx Header Sequence Number
Send
S d LGOOD
LGOOD_n, where
h
n = 7 after reset or
n = HSEQ# of last good received HP otherwise
Receive LGOOD
LGOOD_n
n from link partner
Flush the HPs from Tx Header Buffer with HSEQ# <= n (considering
rollunder)
Set ACK Tx Header Sequence Number to n+1 (with rollover)
Advertise Local Rx Header Buffer Credit
Send credit for all available buffers using 1 LCRD_x for each
First credit is always returned using LCRD_A
Must advertise all 4 credits after reset.
Receive first credit (LCRD_A)
May now send a packet
Receive remaining credits (LCRD_B-D)
May now initiate power state transitions
42
Link Power State Transitions:
B k
Background
d
Higher
g
layer
y conditions for initiating,
g, accepting
p g or rejecting
j
g U1 or U2 are
mainly defined elsewhere
U1 and U2 can be requested by either side of a link
U2 can also be entered by timeout from U1
U3 is initiated only by software request to a downstream port
U3 must be accepted
Entry requests can be sent and received concurrently
Request
R
tb
by DSP ttakes
k precedence
d
Entry sequence completed through link commands
LGO_U1, LGO_U2, or LGO_U3 is sent to request a low power link state
LAU or LXU is sent to accept or reject a request respectively
LPMA is sent to confirm receipt of LAU and resulting entry to U1, U2 or U3
Defined to ensure that both ends of the link are in the same power state
Exit from U1/U2 and wake from U3 byy LFPS handshake
43
Link Power State Transitions:
R l and
Rules
dT
Terms
Rules for a p
port to request
q
or accept
p a low power
p
link state
It has transmitted an LGOOD_n, LCRD_x sequence for all packets received
It has received an LGOOD_n, LCRD_x sequence for all packets transmitted
Itt has
as no
o pe
pending
d g pac
packets
ets for
o ttransmission
a s ss o
It is permitted to request or accept by the higher layer
It must be directed by a higher layer to request a low power link state
Terms
PM_LC_TIMER:
Runs while waiting 3us for response (LAU or LXU)
PM ENTRY TIMER: Runs while waiting 6us for LPMA or TS1 for Recover
PM_ENTRY_TIMER:
U2 inactivity timer: Runs while link is idle to qualify entry to U2
Timeout value set by USB system software
44
Link Power State Transitions:
C
Concurrent
t Requests
R
t
DSP
USP
1 LGO_U1/2
1a Start PM_LC_TIMER
PM LC TIMER
2 LXU
.
.
5 Reset & stop PM_LC_TIMER
.
6 LPMA
7 Go to U1/2
.
LGO_U1/2 1
Start PM_LC_TIMER
PM LC TIMER 1a
.
Reset & stop PM_LC_TIMER 3
LAU 4
Start PM_ENTRY_TIMER 4a
.
.
Reset & stop PM_ENTRY_TIMER 7
Go to U1/2 8
45
Link Power State Transitions:
Single
Si l R
Rejected
j t d U1 or U2 R
Requestt
Link b
Link a
.
.
2 LXU
.
.
.
.
.
.
.
LGO_U1/2 1
Start PM_LC_TIMER
PM LC TIMER 1a
1
.
Reset & stop PM_LC_TIMER 3
Stay in U0 3a
.
.
.
.
.
46
Link Power State Transitions:
Corrupted
C
t d LAU
Link a
Link b
1 LGO_U1/2/3
St t PM_LC_TIMER
PM LC TIMER
1a Start
.
3 LAU is corrupted & lost
3a PM_LC_TIMER expires
4 Send TS1 to initiate Recovery
.
.
7 Complete Recovery
R
t U1/2/3
8 Re-request
.
LAU,
LAU 2
Start PM_ENTRY_TIMER 2a
.
.
.
Reset & stop PM_ENTRY_TIMER
PM ENTRY TIMER 5
Join Recovery 6
Complete Recovery 7
.
47
Link Power State Transitions:
Corrupted
C
t d LPMA
Link a
1 LGO_U1/2/3
St t PM_LC_TIMER
PM LC TIMER
1a Start
.
.
3 Reset & stop PM_LC_TIMER
4 LPMA
5 Go to U1/2/3
.
.
.
Link b
.
LAU,
LAU 2
Start PM_ENTRY_TIMER 2a
.
.
.
LPMA is corrupted & lost 5
PM_ENTRY_TIMER expires 5a
Go to U1/2/3 6
.
48
Link Power State Transitions:
Direct
Di t E
Entry
t tto U2 ffrom U1
Link a
Link b
1 Go to U1
1a Reset & start U2 inactivity timer
1b U2 inactivity timer expires
2 Go to U2
Go to U1
1
Reset & start U2 inactivity timer 1a
U2 inactivity timer expires 1b
Go to U2
49
Link Power State Transitions:
U1 E
Exit,
it U2 E
Exit,
it U3 W
Wakeup
k
LFPS handshake sequence
Link Partner 1
Link partner 1 initiates exit by
transmitting LFPS at time t10
Link Partner 2
Link partner 2 detects valid
LFPS on its receiver and
responds by transmitting
LFPS at time t11
t 10
t 11
t 12 t 13
Time
U-033
Link partner 1 enters
Recovery and starts
transmitting TS1 Ordered Sets
at time t12
Link partner 2 enters
Recovery and starts
transmitting TS1 Ordered Sets
at time t13
50
Disconnect Detection
From U0 (active state)
LUP/LDN Link Command ping sent by Upstream/Downstream Port once
every 10 us
Downstream/Upstream Port (DSP/USP) goes to Recovery if it doesnt see a link
command
d within
ithi 1
1ms. F
From R
Recovery, it would
ld go tto SS
SS.Inactive
I
ti and
d th
then
Rx.Detect. An Upstream Port would end in SS.Disabled, if Rx.Detect failed 8
times, and the device would switch to USB 2.0
From U1 (fast-exit reduced-power idle link state)
Upstream Port sends a Ping.LFPS every 200 ms
Cant use Rx.Detect must maintain common mode to reduce U1 exit latency
DSP goes to Rx.Detect if doesnt get one Ping.LFPS per 300 ms
From U2 (slow-exit
(slow exit reduced
reduced-power
power idle link state) or U3 (suspend)
Downstream Port performs an Rx.Detect every 100 ms
Common mode is disturbed 64 us to restore is OK for U2, U3 exit latencies
DSP remains in Rx.Detect
Rx Detect if it doesn
doesntt detect the appropriate Rx termination
51
Inband Reset
Inband Reset relies on SuperSpeed or LFPS signaling, depending on
type
Two types of inband reset:
Hot Reset A reset bit within TS2 Ordered Sets (SuperSpeed signaling)
Warm
W
Reset
R
t Big
Bi H
Hammer
100 ms LFPS meeting
ti tR
tResett requirements
i
t
Inband reset is initiated by software request to downstream port
Two types of reset request
PORT_RESET:
PORT RESET LTSSM decides
d id which
hi h inband
i b d resett based
b
d on link
li k states
t t
LTSSM = U0, Polling, Recovery use Hot Reset
LTSSM = U1, U2 exit to Recovery use Hot Reset
p
Compliance
p
use Warm Reset
LTSSM = U3, SS.Inactive, Loopback,
LTSSM = SS.Disabled reset is prohibited
If Hot Reset fails at Recovery Go to Rx.Detect then do a Warm Reset
BH_PORT_RESET: LTSSM must issue warm reset
52
Summaryy
Robust and reliable delivery of HPs
Enables receiver detection by phy
Controls and coordinates link training
g with link p
partner
Completes entry to and exit from low power link states
Ensures both link partners are in the same power state
Signals or detects inband reset
53
Backup: LUP for Disconnect
Detection
D t ti During
D i U0
During U0,
The downstream port does not check Rx termination
It can detect a disconnect only by lack of traffic
To ensure regular traffic during long periods of logical idle in U0 when U1
or U2 is either not enabled or not possible, LUP was defined
It is intentionally unique to an upstream port to allow the opportunity to
distinguish between active USP Tx and crosstalk (NEXT) from DSP Tx to
DSP Rx while Rx is electrically idle due to disconnect
LUP is sent every 10 us
And not more frequently, to limit its impact on throughput
And not less frequently, to ensure that it is seen within the 1ms
window even if the timer expiration is very loose and 1 or more of
these LUPs are missed
Transition to Recovery
Recovery, then to SS
SS.Inactive
Inactive and then to Rx.Detect
Rx Detect is
to enable distinction between link error and disconnect
54
