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Built in Logic Block Observer

Built-In Logic Block Observer (BILBO) was the first BIST approach proposed in 1979. It adds BIST logic to each flip-flop to implement test pattern generation and output response analysis. BILBO requires at least two test sessions to test different circuits, and uses scan mode to retrieve results and re-initialize test pattern generators. While it provides pseudo-exhaustive testing without fault simulation, BILBO is difficult to implement practically due to problems with test session scheduling and register self-adjacency.

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626 views10 pages

Built in Logic Block Observer

Built-In Logic Block Observer (BILBO) was the first BIST approach proposed in 1979. It adds BIST logic to each flip-flop to implement test pattern generation and output response analysis. BILBO requires at least two test sessions to test different circuits, and uses scan mode to retrieve results and re-initialize test pattern generators. While it provides pseudo-exhaustive testing without fault simulation, BILBO is difficult to implement practically due to problems with test session scheduling and register self-adjacency.

Uploaded by

sreekanth
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Built-In Logic Block Observer - Organization

z
z
z
z
z
z

C. Stroud 10/06

Architecture
Operation
Test Session Scheduling
BIST Controller
Concurrent BILBO
Benefits & Limitations

BILBO

Built-In Logic Block Observer (BILBO)


z

by Koenemann & Mucha, 1979


1st BIST approach proposed
BIST logic added to all FFs
plus logic for characteristic polynomial
BILBO control leads B1 & B2 facilitate
system mode - normal operation
reset mode - initialization
LFSR mode - TPG
MISR mode ORA
Scan mode needed
BIST results retrieval
Initialization of TPGs
9 to non-0 values

Zi
B1
B2
Qi-1

BILBO
Q
B1
B2

Comb
Logic
Z

BILBO
Comb
Logic
added
to FF

BILBO FF
D Q

Qi

CK Q

Qi

Test-per-clock BIST
Exhaustive testing of combinational logic
C. Stroud 10/06

BILBO

BILBO Evolution
z

Original implementation
Required mode pin B1
to control TPG vs.
MISR mode during
testing
Forcing logic 0s on Z
inputs causes MISR to
function as LSFR for
TPG

Used external FB LFSR


Later implementation added
control signal B3
To control TPG vs.
MISR modes
C. Stroud 10/06

BILBO

BILBO Evolution
z

Modified BILBO was


introduced for practical
ASIC implementations
NAND gates used
for CMOS friendly
standard cells
Only two control
signals needed
Minimizes area
overhead
Most frequently used
BILBO approach
C. Stroud 10/06

BILBO

BILBO Operation
z

At least 2 test sessions required


Test session 1:
Ckts A & C are CUTs
BILBO 1 = MISR
BILBO 2 = LFSR

Test session 2:

z
z

Ckt B is CUT
BILBO 1 = LFSR
BILBO 2 = MISR

Scan In

LFSR

Test
Session
1

CUT A

Test
Session
2

MISR

BILBO 1

LFSR

CUT B

Need scan mode to


BILBO 2
LFSR
Retrieve BIST results from MISRs
CUT C
Initialize LFSRs to non-0 values
Works well for pipelined architectures
MISR
Otherwise, problems with feedback
Scan Out
Requires test session scheduling
C. Stroud 10/06

BILBO

MISR

Test Session Scheduling


z

Practical application
of BILBO typically
requires scheduling
of multiple test
sessions based on
interconnection of
registers and
combinational logic

C. Stroud 10/06

BILBO

Register Self-Adjacency
z

Common in FSMs
Next state is function of current state
BILBO must simultaneously function as TPG and ORA
Signatures act as test vectors
Loose pseudo-exhaustive nature of test vectors
One solution the Concurrent BILBO (CBILBO)
Doubles #FFs to create independent TPG and ORA

Register R1

R1=TPG(LFSR)

R1=TPG(LFSR)

Combinational
Logic

Combinational
Logic

Combinational
Logic

Register R2

R2=ORA(MISR)

system operation
C. Stroud 10/06

BILBO operation
BILBO

R2=ORA R2=TPG
CBILBO operation
7

Concurrent BILBO
z

Adds additional register to allow TPG and MISR to operate


independently in cases of register self-adjacency

C. Stroud 10/06

BILBO

BILBO Summary
z

Not practical but historically significant since it got BIST started


Led to pseudo-exhaustive self-test (PEST)
Led to Circular BIST

C. Stroud 10/06

BILBO

Advantages
z
z

BILBO Summary

Test-per-clock archtecture
Pseudo-exhaustive testing
No need for fault simulation
Works well for pipelined applications

Disadvantages
z

Difficult to implement in practical applications


Multiple test sessions require
Test session scheduling can be difficult

Requires multiple primitive polynomials of varying degrees


Register self-adjacency difficult to overcome
Higher area overhead than other BIST approaches
More than two gate delays in every critical path
C. Stroud 10/06

BILBO

10

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