MicroStar BGA
Packaging

Reference Guide

Literature Number: SSYZ015B

Third Edition September 2000

MicroStar BGA is a trademark of Texas Instruments Incorporated.

Printed on Recycled Paper

IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customers applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TIs publication of information regarding any third
partys products or services does not constitute TIs approval, warranty or endorsement thereof.

Copyright 2000, Texas Instruments Incorporated

Introduction
The parallel pursuit of cost reduction and miniaturization
in recent years has given rise to an increasing emphasis
on very small integrated circuit (IC) package solutions.
This is particularly evident in consumer-based end

equipment using digital signal processor (DSP) solutions

such as wireless telephones, laptop computers, and
hard-disk drives. Despite the formal definition, packages
with an area similar in size to the IC they encapsulate are
loosely referred to as chip scale packages (CSPs).
Figure 1 illustrates this trend.

Figure 1. Packaging Trends

Package trend (customer requirement)
QFP
0.5 mm pitch

BGA (ball grid array)

1.27 mm ball pitch

QFP
0.4 mm pitch

Fine pitch requirement

Infra. issue (KGD)

Soldering difficulties

Bare chip
(flip chip)

PWB/ASSY cost up

CSP (chip scale pkg.) solution

Fine pitch BGA
(0.5, 0.8, 1.0 mm ball pitch)

QFP-0.5
BGA

Package size

QFP-0.4

CSP

Bare chip (bump)

Pin count

Chip scale packages are in many ways an ideal solution

to the cost reduction and miniaturization requirements.
They offer enormous area reductions in comparison to
quad flat packages (QFPs) and have increasing potential
to do so without adding to system-level cost. In the best
case, CSPs compete today on a cost-per-terminal basis
with QFPs. For example, various CSPs from Texas
Instruments (TI) are now available at cost parity with thin
QFPs.
Texas Instruments produces a polyimide film-based
family of CSPs called MicroStar BGA
. Like most other
CSPs, MicroStar BGAs use solder alloy balls as the
interconnect between the package substrate and the
board on which the package is soldered. The MicroStar
BGA family comes in a range of solder ball pitch (0.5 mm,
0.8 mm, and 1.0 mm). Currently, TIs most popular
packages are 64- and 144-ball packages. Figure 2
shows the structure of TIs MicroStar BGA package.

Figure 2. Structure of TIs MicroStar BGA

Conforms to JEDEC Outlines: MO-192 and MO-205-A
Encapsulant
0.8 mm
pitch
Chip
(11 mils)
Wire bond

Die
paste

PWB

Via
(0.375 mm DIA.)
0.5 mm DIA./0.8 mm ball pitch
Sn/Pb: near eutectic

Cu pattern
(30 m line/
40 m space)
Flex substrate
(polyimide)
(Single electrical layer)

MicroStar BGA is a trademarks of Texas Instruments.

MicroStar BGA Packaging Reference Guide

iii

Texas Instruments addressed several key issues in

package assembly in order to produce a CSP that is not
only physically and mechanically stable but
cost-effective for a wide variety of applications. Figure 3
demonstrates how MicroStar BGAs resolve reliability
and cost issues. An overall view of the flow used to
produce TI MicroStar BGA packages is shown in
Figure 4. The process for solder ball attachment is
shown in Figure 5.

Figure 4. MicroStar BGA Package Assembly Flow

Same as QFP assembly

Die attach

Wire bond

Encap

Non-Ag paste

Short loop

Xfer mode

Figure 3. MicroStar BGA Package Assembly

Issues
Substrate

Ceramic

selection

Glass-epoxy
Polyimide

BGA unique process

Ball attach

Interconnection

Bump (flip chip)

Wire bond

Molten
solder

Flux wash

Capillary

0.30 mm DIA.

Orifice

Solder ball form

IR reflow

Solder wire

Transducer

Ultrasonic clean

Solder jet
Stud bump
Paste print

Solder
paste

Printing mask

Pick and place

Laser symbol
and singulation

Vacuum
Encapsulation

Potting

Test

Transfer mold
Tray
These are the processes used by TI.

Figure 5. Solder Ball Attachment

Pick and place
Vacuum

Solder ball attach

Squeegee

Solder
paste

Printing mask

Substrate
Ball pads (via)

Solder paste print

Solder ball
Solder ball attach
(12 mil DIA.)

Solder ball shear tests

SS
125
125

Fail
0
0

Ave. Reading
668 g
734 g

144GGU, 0.8-mm pitch, 0.5 mm DIA. ball TI spec. is 400 g min

The MicroStar BGA package has been fully qualified in

numerous applications and is being used extensively in
mobile phones, laptops, modems, handheld devices,
and office environment equipment. Your local TI field
sales office can give you more information on using
reliable and cost-effective MicroStar BGA packaging in
iv

your application.
This guide is designed to give you technical background
on MicroStar BGA packages as well as how they can be
used to build advanced board layouts. Any additional
help desired with your specific design is also available
through your local TI field sales office.
MicroStar BGA Packaging Reference Guide

Contents
1 PCB Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Solder Land Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conductor Width/Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Density Routing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Via Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conventional PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Design Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11
12
12
13
13
14
14

2 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy-Chained Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21
22
22
24
26
26
26

3 Surface-Mounting MicroStar BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . .

Design for Manufacturability (DFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Solder Paste . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Solder Ball Collapse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31
32
32
33
33
34

4 Packing and Shipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Trays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tape-and-Reel Packing Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tape Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41
42
44
44
45
45

5 Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Design Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Ball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Establishing Contact Force . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

51
52
52
53
53

6 Lead-Free Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Land Finishes and Solder Paste . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

61
64
65
69

7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Appendix A
Frequently Asked Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . A1
Package Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A1
Assembly Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A2
Appendix B
Package Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B1
80GJK
(Pitch = 0.5 mm; Size = 6 x 6 mm) . . . . . . . . . . . . . . . . . . . . . B2
167GJJ
(Pitch = 0.5 mm; Size = 8 x 8 mm) . . . . . . . . . . . . . . . . . . . . . B3
151GHZ
(Pitch = 0.5 mm; Size = 10 x 10 mm) . . . . . . . . . . . . . . . . . . . B4
100GGM (Pitch = 0.8 mm; Size = 10 x 10 mm) . . . . . . . . . . . . . . . . . . . B5
64GGV
(Pitch = 0.8 mm; Size = 8 x 8 mm) . . . . . . . . . . . . . . . . . . . . . B6
80GGM
(Pitch = 0.8 mm; Size = 10 x 10 mm) . . . . . . . . . . . . . . . . . . . B7
100GGF
(Pitch = 0.5 mm; Size = 10 x 10 mm) . . . . . . . . . . . . . . . . . . . B8
100GGT
(Pitch = 0.8 mm; Size = 11 x 11 mm) . . . . . . . . . . . . . . . . . . . B9
144GGU (Pitch = 0.8 mm; Size = 12 x 12 mm) . . . . . . . . . . . . . . . . . B10
179GHH (Pitch = 0.8 mm; Size = 12 x 12 mm) . . . . . . . . . . . . . . . . . . B11
176GGW (Pitch = 0.8 mm; Size = 15 x 15 mm) . . . . . . . . . . . . . . . . . B12
208GGW (Pitch = 0.8 mm; Size = 15 x 15 mm) . . . . . . . . . . . . . . . . . B13
MicroStar BGA Packaging Reference Guide

Contents (continued)
240GGW
196GHC
257GHK
257GJG

vi

(Pitch = 0.8 mm; Size = 15 x 15 mm)

(Pitch = 1.0 mm; Size = 15 x 15 mm)
(Pitch = 0.8 mm; Size = 16 x 16 mm)
(Pitch = 0.8 mm; Size = 16 x 16 mm)

.................
.................
.................
.................

B14
B15
B16
B17

MicroStar BGA Packaging Reference Guide

List of Figures
Figure

Page

Packaging Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Structure of TIs MicroStar BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

MicroStar BGA Package Assembly Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

MicroStar BGA Package Assembly Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

Solder Ball Attachment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

Package Via to Board Land Area Configuration . . . . . . . . . . . . . . . . . . . . . 12

Effects of Via-to-Land Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Optimum Land Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PCB Design Considerations (Conventional) . . . . . . . . . . . . . . . . . . . . . . . . 13

10

Microvia Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

11

Dog Bone Via Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

12

Buried Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

13

Daisy-Chained Pinout List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

14

General Net List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

15

PCB Layout for Daisy-Chained Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

16

Daisy-Chain Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

17

Board-Level Reliability Test Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

18

Board-Level Reliability Test Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

19

Thermal Modeling Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

20

Electrical Modeling Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

21

Solder Ball Collapse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

22

Ideal Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

23

Shipping Tray Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

24

Packing Method for Trays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

25

Single Sprocket Tape Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

26

Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

27

Tape-and-Reel Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

28

Approaches for Contacting the Solder Ball . . . . . . . . . . . . . . . . . . . . . . . . . 52

29

Pinch Contact for Solder Balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

30

Contact Area on Solder Ball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

31

Witness Marks on Solder Ball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

32

Effect of Burn-in on Probe Marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

33

Assembly Testing of Eutectic vs. Pb-free Solder Balls . . . . . . . . . . . . . . . 63

34

Standard Reflow Profile for Pb/Sn Alloy Solder . . . . . . . . . . . . . . . . . . . . . 63

35

Proposed Reflow Profile for Non-Pb Alloy Solders . . . . . . . . . . . . . . . . . . 64

36

Typical SAM Pictures After Moisture Sensitivity Testing . . . . . . . . . . . . . . 65

37

Broad-Level Reliability Study

(Solder Paste: Sn/Pb Eutectic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

MicroStar BGA Packaging Reference Guide

vii

List of Figures (continued)

Figure

Page

38

Broad-Level Reliability Study

(Solder Paste: Pb-free-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

39

Broad-Level Reliability Study

(Solder Paste: Pb-free-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

40

Key Push Test Apparatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

41

Typical Key Push Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

42

Key Push Test Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

43

TIs Strategic Package Line-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B1

List of Tables
Table

viii

Page

Package-Level Reliability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Package-Level Reliability Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Board-Level Reliability Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Summary of Significant BLR Improvements . . . . . . . . . . . . . . . . . . . . . . . . 25

Effects of Pad Size and Board Thickness on Fatigue Life . . . . . . . . . . . . 25

Number of Units per Shipping Tray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Tape Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Component Relialibility Testing and BLR for Pb-free Solder Balls . . . . . . 62

10

Moisture Sensitivity test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

11

Solder paste compositions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

MicroStar BGA Packaging Reference Guide

 
 
 


1
PCB Design Considerations

MicroStar BGA Packaging Reference Guide

11

PCB Design Considerations

 
 
 


Solder Land Areas

Design of both the MicroStar BGA itself and the printed
circuit board (PCB) are important in achieving good
manufacturability and optimum reliability. In particular,
the diameters of the package vias and the board lands
are critical. While the actual sizes of these dimensions
are important, their ratio is more critical. Figure 6
illustrates the package via-to-PCB configuration and
Figure 7 illustrates why this ratio is critical.

Solder lands on the PCB are generally simple round

pads. Solder lands are either solder-mask-defined or
non-solder-mask-defined.
Figure 8. Optimum Land Configurations
Solder-Mask-Defined Land

Figure 6. Package Via to Board Land Area

Configuration

Package ball via

PCB

 




 

 




 

 
 
  
  

 
  
  
   

Non-Solder-Mask-Defined Land

MicroStar BGA package

Land on PCB

 
 


 

A
B

(Not to scale)
A = Via diameter on package
B = Land diameter on PCB
Ratio A/B should equal 1.0 for optimum reliability.

Figure 7. Effects of Via-to-Land Ratios

Package

PCB
Package

 
 


 

 
 
 
 

 
 
  
 

 
 
  
  

 
  
  
   

Solder-mask-defined (SMD) land. With this method, the

copper pad is made larger than the desired land area,
and the opening size is defined by the opening in the
solder mask material. The advantages normally
associated with this technique include more closely
controlled size and better copper adhesion to the
laminate. Better size control is the result of photoimaging
the stencils for masks. The chief disadvantage of this
method is that the larger copper spot can make routing
more difficult.
Non-solder-mask-defined (NSMD) land. Here, the land
area is etched inside the solder mask area. While the
size control is dependent on copper etching and is not as
accurate as the solder mask method, the overall pattern
registration is dependent on the copper artwork, which is
quite accurate. The tradeoff is between accurate dot
placement and accurate dot size.
See Figure 8 for an example of optimum land diameters
and configurations for a common MicroStar BGA pitch.

PCB
Package

PCB

In the top view of Figure 7, the package via is larger than

the PCB via, and the solder ball is prone to crack
prematurely at the PCB interface. In the middle view, the
PCB via is larger than the package via, which leads to
cracks at the package surface. In the bottom view, where
the ratio is almost 1:1, the stresses are equalized and
neither site is more susceptible to cracking than the
other.
12

Conductor Width/Spacing
Many of todays circuit board layouts are based on at
most a 100-m conductor line width and 200-m
spacing. To route between 0.8-mm-pitch balls, given a
clearance of roughly 380 m between ball lands, only
one signal can be routed between ball pads. The 380-m
ball spacing is worst case and is calculated by assuming
the diameter of the solder ball land is 410 m.
Figure 9 presents some design considerations based on
commonly used PCB design rules. Conventionally, the
pads are connected by wide copper traces to other
devices or to plated through holes (PTH). As a rule, the
mounting pads must be isolated from the PTH. Placing
the PTH interstitially to the land pads often achieves this.
MicroStar BGA Packaging Reference Guide

PCB Design Considerations

 
 
 


Figure 9. PCB Design Considerations (Conventional)

(Not to scale)
1.0 mm
pitch

0.125 mm line

0.50 mm DIA.
solder mask
opening

0.254 mm
DIA. hole

0.55 mm DIA.
solder mask
opening

0.254 mm
DIA. hole

NSMD pads

0.100 mm line

NSMD pads

0.400 mm
DIA. pad

0.125 mm line

0.350 mm
DIA. pad

0.125 mm line

0.8 mm
pitch

0.375 mm DIA.
solder mask
opening

0.480 mm
DIA. pad
SMD pads

High-Density Routing Techniques

A challenge when designing with CSP packages is that
as available space contracts, the space available for
signal fanout also decreases. By using a few
high-density routing techniques, the PCB designer can
minimize many of these design and manufacturing
challenges. This section focuses on TI designators GGU
(144-pin) and GGW (176-pin) packages. Both packages
have 0.8-mm pitch, but each is distinctly different in array
style. The GGW ball array has wide channels in the four
corners, providing the inner balls with space for routing
and VCC connectivity. Mechanical drawings of these
MicroStar BGA packages can be found in Appendix B.
The GGU package has a solid four-row array
configuration which can cause difficulties when routing
inner rows on two-layer boards.

Via Density
Via density, as mentioned earlier, can be a limiting factor
when designing high-density boards. Via density is
defined as the number of vias in a particular board area.
Using smaller vias increases the routability of the board
by requiring less board space and increasing via density.
The invention of the microvia, shown in Figure 10, has
solved many of the problems associated with via density.
MicroStar BGA Packaging Reference Guide

0.450 mm DIA.
solder mask
opening

0.550 mm
DIA. pad
SMD pads

Figure 10.

Microvia Structure

Microvias are often created using a laser to penetrate the

first few layers of dielectric. The laser can penetrate a
4-mil-thick dielectric layer, creating the 4-m microvia
shown in Figure 10. The layout designer can now route
to the first internal board layer. Two layers (each 4 mils
thick) can be laser-drilled, creating a 200-m microvia
diameter. In this case, routing to the first two internal
layers is possible.
The number of board layers increases as board chip
density and functional pin count increase. As an
example, the TMS320VC549GGU digital signal
processor (DSP) is in a 144-GGU package and uses
32 balls for power and ground. Routing of roughly
13

 
 
 


PCB Design Considerations

112 signals can be accomplished on three layers. The

power and ground planes increase the board to five
layers. The sixth layer can be used on the bottom side to
place discrete components. Furthermore, by increasing
the board layer stack-up to eight layers, high-density
applications are possible with only 10 to 15 mils between
the chips.

Advanced Design Methods

Another option is to use a combination of blind and buried
vias. Blind vias connect either the top or bottom side of
the board to inner layers. Buried vias usually connect
only the inner layers. Figure 12 illustrates this method
using 4-mil laser-drilled microvias in the center of the
pads and burying the dog bone on layer 2.

Conventional PCB Design

The relatively large via density on the package periphery,
mentioned earlier, is caused by limited options when
routing the signal from the ball. To reduce or eliminate the
via density problem on the periphery of the package,
designers can build the PCB vertically from the BGA pad
through the internal layers of the board, as shown in
Figure 11. By working vertically and mechanical drilling
250-m vias between the pads on the board and the
internal
layers,
designers
can
create
a
pick-and-choose method. They can pick the layer and
choose the route. A dog bone method is used to
connect the through-hole via and the pad.
This method requires a very small mechanical drill to
create the necessary number of 144 or 176 vias for one
package. Although this method is the least expensive, a
disadvantage is that the vias go through the board,
creating a matrix of vias on the bottom side of the board.
Figure 11.

Dog Bone Via Structure

Cross-sectional view

Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6

14

Top side view

Since the buried via does not extend through the

underside of the board, the designer can use another set
of laser-drilled blind microvias, if needed, to connect the
bypass capacitors and other discrete components to the
bottom side.
More information on these advanced techniques is
available by contacting your local TI field sales office.
Figure 12.

Buried Vias

Solder wicks into

blind via filling void
Layer 1
Layer 2

Micro blind vias

Layer 3
Layer 4
Layer 5
Layer 6

10-mil through-hole
buried via

4-mil laser-drilled microvia may be

required to connect discretes on
bottom side of board

MicroStar BGA Packaging Reference Guide




2
Reliability

MicroStar BGA Packaging Reference Guide

21




Reliability

Daisy-Chained Units

Reliability Data

Daisy-chained units are used to gain experience in the

handling and mounting of CSPs, for board-reliability
testing, to check PCB electrical layouts, and to confirm
the accuracy of the mounting equipment. To facilitate
this, Texas Instruments offers daisy-chained units in all
production MicroStar BGA packages.

Reliability is one of the first questions designers ask

about any new packaging technology. They want to know
how well the package will survive handling and assembly
operation, and how long it will last on the board. The
elements of package reliability and system reliability,
while related, focus on different material properties and
characteristics and are tested by different methods.

Each daisy-chained pinout differs slightly depending on

package layout. An example is shown in Figure 13.
Daisy-chained packages are wired to provide a
continuous path through the package for easy testing.
TI issues a net list for each package, which correlates
each ball position with a corresponding wire pad number.
The daisy-chained net list is a special case of the general
net list shown in Figure 14. Package net lists and
daisy-chained net lists for all production packages are
included in Appendix B.

Figure 14.

100GGT Top View

11
10
9
8
7
6
5
4
3

A PCB layout for a 144-GGU daisy-chained package is

shown in Figure 15. When a daisy-chained package is
assembled on the PCB, a complete circuit is formed,
which allows continuity testing. The circuit includes the
solder balls, the metal pattern on the die, the bond wires,
and the PCB traces. The entire package or only a
quadrant can be interconnected and tested. A diagram
of the test configuration is shown in Figure 16.

2
1

A B C D E F G H J K L
Index
mark

PIN#

Figure 13.

Daisy-Chained Pinout List

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

100GGT Top View

11
10
9
8
7
6
5
4
3
2
1

General Net List

BALL#

PIN#

A1
B2
B1
C2
C1
D2
E3
D1
E2
F3
F2
E1
F1
G1
G2
G3
H1
H2
H3
H4
J1
J2
J3
K1
J4

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

BALL#

PIN#

L1
K2
L2
K3
L3
K4
J5
L4
K5
J6
K6
L5
L6
L7
L8
K7
J7
K8
J8
L9
H8
K9
J9
L10
H9

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

BALL#

PIN#

L11
K10
K11
J10
J11
H10
H11
G9
G10
F9
F10
G11
F11
E11
D11
E10
E9
D10
C11
D9
D8
C10
B11
C9
C8

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

BALL#

A11
B10
A10
B9
A9
B8
A8
B7
A7
C7
C6
B6
A6
B5
A5
C5
D4
A4
B4
C4
A3
B3
C3
A2
D3

A B C D E F GH J K L
Index
mark

Figure 15.
A1
B1
C1
D1
F3
E1
G1
G3
H2
H4
J2
K1

B2
C2
D2
E2
F2
F1
G2
H1
H3
J1
J3
J4

L1
L2
L3
L4
J6
L5
L7
K7
K8
L9
K9
L10

K2
K3
K4
K5
K6
L6
L8
J7
J8
H8
J9
H9

L11
K11
J11
G9
F9
G11
E11
E10
D10
D9
C10
C9

K10
J10
H10
G10
F10
F11
D11
E9
C11
D8
B11
C8

A11
A10
A9
B7
C7
B6
B5
C5
A4
C4
B3
A2

PCB Layout for Daisy-Chained Unit

B10
B9
B8
A7
C6
A6
A5
D4
B4
A3
C3
D3

NC E3, J5, H11, A8

22

MicroStar BGA Packaging Reference Guide

Reliability

Daisy-Chain Test Configuration

Wire bonds

MicroStar BGA

Solder
balls

Tester

PCB
Copper traces

reliability, and thermal cycling tests are generally used to

predict behavior and reliability. Many of these are used
in conjunction with solder fatigue life models using a
modified Coffin-Manson strain range-fatigue life plots.
Table 1. Package-Level Reliability Tests

Test pads

Package reliability focuses on materials of construction,

thermal flows, material adherence/delamination issues,
resistance to high temperatures, moisture resistance
and ball/stitch bond reliability. Thorough engineering of
the package is performed to prevent delamination
caused by the interaction of the substrate material and
the mold compound.
TI subjects each MicroStar BGA to rigorous qualification
testing before the package is released to production.
These tests are summarized in Table 1. All samples used
in these tests are preconditioned according to Joint
Electronic Device Committee (JEDEC) A113 at various
levels. Typical data is presented in Table 2. MicroStar
BGA packages have proven robust and reliable.
Board-level reliability (BLR) issues generally focus on
the complex interaction of various materials under the
influence of heat generated by the operation of electronic
devices. Not only is there a complex thermal situation
caused by multiple heat sources, but there are cyclical
strains due to expansion mismatches, warping and
transient conditions, non-linear material properties, and
solder fatigue behavior influenced by geometry,
metallurgy, stress relaxation phenomenon, and cycle
conditions. In addition to material issues, board and
package design can influence reliability. Thermal
management from a system level is critical for optimum

Test Environments

Conditions

Read Points

HAST

85RH/85C

600 hrs.
1000 hrs.

Autoclave

121C, 15 psig

96 hrs.
240 hrs.

Temp. Cycle

55/125C
65/150C

500 cycles
750 cycles
1000 cycles

Thermal Shock

65/150C
55/125C

200 cycles
500 cycles
750 cycles
1000 cycles

HTOL

125C, Op. voltage

500 hrs.
600 hrs.
1000 hrs.

HTOL

140C, Op. voltage

500 hrs.

HTOL

155C, Op. voltage

240 hrs.

Bake

150C
170C

600 hrs.
1000 hrs.
420 hrs.

130C

96 hrs.

HAST

All samples used in these tests are preconditioned according to Joint

Electronic Device Committee (JEDEC) A113 at various levels.
Optional tests. One or more of them may be added to meet customer
requirements.

Table 2. Package-Level Reliability Test Results

Package Types
Leads

64

80

144

196

Body (mm)

8x8

10 x 10

12 x 12

15 x 15

Device

MSP

ASP

DSP

DSP

5.3 x 5.8

7.5 x 7.5

2a

Die (mm)
Level
Test Environment

9.3 x 9.5
4

Failures/Sample Size

Autoclave

(240 hrs.)

0/70

0/78

0/77

0/77

0/77

T/C, 55/125C

(1000 cycles)

0/116

0/78

0/77

0/77

0/76

T/S, 65/150C

(500 cycles)
(750 cycles)
(1000 cycles)

0/116

0/77

0/77

HAST,
85C/85%RH

(1000 hrs.)
(1250 hrs.)

0/115

150C Storage

(600 hrs.)
(1000 hrs.)

0/43

(1000 hrs.)

0/116

HTOL

0/78
0/77

0/78
0/77
0/77

0/77

0/77

0/78

MicroStar BGA Packaging Reference Guide

23



Figure 16.

Reliability

In addition to device/package testing, board-level

reliability testing has been extensively performed on the
MicroStar BGA packages. Various types of
daisy-chained packages were assembled to special
boards shown in Figure 17. Electrical measurements

were made in the initial state and then at intervals after

temperature cycles were run. The overall test conditions
are shown in Figure 18. A summary of a wide range of
board-level reliability is shown in Table 3. This data
includes testing by TI and by end manufacturers.

Figure 17.

Table 4 summarizes conclusions from the testing. Two

important conclusions are that the PCB pad size needs
to match the via size, and that solder paste is needed for
attachment to give optimal reliability.

Board-Level Reliability Test Boards



Board Material FR-4

Structure: Two external
metal layers
Traces: 1oz cu design rule
100 m (4 mils) width,
100 m (4 mils) space
Paste: Eutectic
(SENJU 63-330F-21-10.5)
Paste thickness: 0.15 m
Board thickness: 31 mils

Reliability Calculations

Reflow profile: 225C

max, time above 200C is
50 sec, time above 150C
is 240 sec
Screen opening: match
land pad diameter
Precondition: Level 3

Another important aspect of predicting how a package

will perform in any given application is reliability
modeling. Thermal, electrical, and thermomechanical
modeling, verified by experimental results, provide
insight into system behavior, shorten package
Figure 18.

Board-Level Reliability Test Data

Test condition: Open short @25C, 10% resistance

change or 200
Sample size: Greater or equal to 32
Temperature cycle range: 40C to 125C
Sampling rate: Every 100 cycles, up to first failure; every
50 cycles thereafter up to 1000 cycles; every 100 cycles
between 1000 to 1500 cycles; every 250 cycles between
1500 to 2500 cycles; Test stopping point min (2500 cycles,
50% failures)

TI-Houston test board

5 min

Ramp time: 2 min5 min

Dwell time: 11 min13 min

TI-HIJI test board

Table 3. Board-Level Reliability Summary

Failures/Sample Size
Conditions (With Solder Paste)

Package

TI Mfg Site
Test Site

Requirements

Body
(mm)

Pitch
(mm)

Die
(mm)

Temp.
Cycle (C)

500

800
1000
(Cycles)

Extended Range
1100

1200
1300
(Cycles)

1500

GGU
144 balls

TI HIJI
TI HIJI

12 x 12

0.8

8.8 x 8.8

40/125

0/85

0/85

0/85

4/85

5/77

5/72

15/39

GGU
144 balls

TI Philippines
TI HIJI

12 x 12

0.8

8.8 x 8.8

40/125

0/36

0/36

0/36

0/36

0/36

0/36

1/35

GGF
100 balls

TI HIJI
TI HIJI

10 x 10

0.5

6.6 x 6.6

25/125

0/32

0/32

0/32

0/32

0/32

0/16

6/16

GHC
196 balls

TI TIPI
TI Hou

15 x 15

1.0

8.8 x 8.8

40/125

0/62

0/62

0/62

0/62

0/62

0/62

4/62

GGU
144 balls

TI Philippines
Customer A

12 x 12

0.8

8.8 x 8.8

40/100

0/180

0/180

0/180

0/180

GGW
176 balls

TI HIJI
Customer B

15 x 15

0.8

6.6 x 6.6

25/125

0/35

0/35

0/35

0/35

0/35

0/35

1/35

GGM
80 balls

TI HIJI
Customer C

10 x 10

0.8

5.0 x 5.0

40/125

0/12

0/12

0/12

0/10

24

MicroStar BGA Packaging Reference Guide

Reliability

Improved BLR

Condition
Die size

Larger

Smaller

Die edge

Over balls

Within ball matrix

Ball count

Smaller

Larger

Ball size

Smaller

Larger

PCB pad size

Over/undersized

Matches package via

(for NSMD ~90% of via)

Solder paste

None or
insufficient

Thickness 0.15 nom.

(type matches reflow)

development time, predict system lifetimes, and provide

an important analytical tool. In applications such as
BGAs, where the interconnections are made through
solder balls, the useful life of the package is, in most
cases, dependent on the useful life of the solder itself.
This is an area that has been studied extensively, and
very accurate models for predicting both solder behavior
and interpreting accelerated life testing exist.
The current methodology employed at Texas
Instruments includes both extensive model refinement
and constant experimental verification. For a given
package, a detailed 2D Finite Element Model (FEM) is
constructed. This model will be used to carry out 2D plain
strain elastoplastic analysis to predict areas of high
stress. These models also account for the thermal
variation of material properties, such as Modulus of
Elasticity, Coefficient of Thermal Expansion, and
Poissons Ratio as a function of temperature. These
allow the FEM to calculate the thermomechanical plastic
strains in the solder joints for a given thermal loading.

The combination of Finite Element Analysis (FEA),

accurate thermal property information, and advanced
statistical methods allows prediction of the number of
cycles to failure for various probability levels. Using the
assumption that cyclic fatigue lifetime follows a Weibull
distribution, various probability levels can be calculated.
For these calculations, the Weibull shape parameter
used is = 4, which is based on experimental data
calibration. It is also consistent with available
experimental data found in the literature for leadless
packages. This then results in the following equation:
Nf(x%) = Nf(50%)[ln(10.01x)/ln(0.5)]1/
Using this equation, and using the plastic strain p in
combination with the S-N curves, the data below is an
example of the accuracy possible with this method:
Sample Finite Element Simulation and Life
Prediction:
144 GGU @ T/C: 40/125C
{Model} p = 0.353% on the outmost joint
Nf(50%)= 4434 cycles
Nf(1%) = 1539 cycles
{BLR Testing} 40/125C (10 min/10 min)
Nf(1%) = 1657 cycles
Modeling is most useful in exploring changes in
materials, designs and process parameters without the
need to build experimental units. For example, modeling
was used to study the effects of changes in board
thickness and pad size. Table 5 shows the simulated
effects of pad size and board thickness on the fatigue life
of a 144-GGU package.

Table 5. Effects of Pad Size and Board Thickness on Fatigue Life

Example1: Effects of pad size on fatigue life

Package: 144 GGU

Die: 8.8 x 8.8 x 0.279 mm
Board: FR-4 board 52 mils thick

Example 2: Effects of board thickness on fatigue

life

Package:
g 144 GGU
Die: 8.8 x 8.8 x 0.279 mm
Board: FR-4
Pad Size: 13 mils

MicroStar BGA Packaging Reference Guide

Pad Dia.
(mils)

Pad
Standoff
(mm)

Solder
Center Dia.
(mm)

Plastic
Strain (%)

Nf (1%)
(cycles to
failure)

Difference

12

0.3847

0.4908

0.4400

998

0.88x

13

0.3689

0.4951

0.4127

1134

14

0.3523

0.5005

0.3908

1263

1.11x

15

0.3350

0.5060

0.3741

1377

1.21x

Board
Thickness
(mils)

Plastic
Strain (%)

Nf (1%)
(cycles to
failure)

Difference

50

0.4095

1152

31

0.393

1249

1.08x

25



Table 4. Summary of Significant BLR

Improvements

Reliability

Texas
Instruments
has
extensive
package
characterization capabilities, including an electrical
measurements lab with TDR/LRC (Time Domain
Reflectometer/inductance resistance capacitance) and
network analysis capabilities, a thermal measurements
lab with JEDEC standard test conditions up to
1000 watts, and extensive electrical, thermal, and
mechanical modeling capability. Modeling was
implemented at TI starting in 1984. Stress analysis is
done with the Ansys Analysis tool, which provides full
linear, nonlinear, 2D and 3D capabilities for solder
reliability, package warpage, and stress analysis studies.
An internally developed tool (PACED) is used for
electrical modeling that gives 2.5D and full 3D capability
for LRC models, transmission lines, lossy dielectrics,
and SPICE deck outputs. The thermal modeling tool was
also internally developed (ThermCAL) and it provides
full 3D automatic mesh generation for most packages.
Figure 19.

Thermal Modeling Process

Heat-Transfer Paths

Complex geometries, transient analysis, and anisotropic

materials can be modeled with it. With these capabilities,
a full range of modeling from device level through system
level can be provided. Package modeling is used to
predict package performance at the design stage, to
provide a package development tool, to aid qualification
by similarity, and is used as a failure analysis tool.

Thermal Modeling
Figure 19 outlines the thermal modeling process. Data
for each package is included in Appendix B.

Electrical Modeling
Figure 20 outlines the electrical modeling process. Data
for each package is included in Appendix B.
Figure 20.

Electrical Modeling Process

Chip
Pad
Package

Calculates inductances,
capacitances, resistances,
transmission line characteristics of
package geometries

Uses as loads for circuit simulation

Process
Select solution algroithms for
problem domain
Identify package structures to be
modeled
Generate spice deck of package
parameters
Simulate impact on driver output
waveforms
Calculate ground/power bounce

PWB

Conduction

Convection

Radiation

(TQFP shown for illustration purposes)

Models three heat-transfer mechanisms:

Conduction
Convection
Radiation
Method:
Define solid
Mesh solid
Solve large number of simultaneous equations relating
each defined mesh point to each other

Die

Pin 1
Pin 2

5
Voltage (V)



Package Characteristics

4
Input pin 1
Output pin1
Crosstalk pin 1

3
2
1
0
0

2.00E-09

4.00E-09

Time (sec)

Sources of error:
Convection coefficients
Material properties
Solid definition inaccuracies

PACED and ThermCAL are trademarks of Texas Instruments Incorporated.

26

MicroStar BGA Packaging Reference Guide


   
  


3
Surface-Mounting
MicroStar BGA Packages

MicroStar BGA Packaging Reference Guide

31

Surface-Mounting MicroStar BGA Packages

Surface-mount technology (SMT) has evolved over the

past decade from an art into a science with the
development of design guidelines and rules. While these
guidelines are specific enough to incorporate many
shared conclusions, they are general enough to allow
flexibility in board layouts, solder pastes, stencils,
fixturing, and reflow profiles. From experience, most
assembly operations have found MicroStar BGA
packages to be robust, manufacturing-friendly packages
that fit easily within existing processes and profiles. In
addition, they do not require special handling. However,
as ball pitch becomes smaller, layout methodology and
placement accuracy become more critical. Below is a
review of the more important aspects of
surface-mounted CSPs. The suggestions provided may
aid in efficient, cost-effective production.

If the edges of the boards are to be used for conveyer

transfer, a cleared zone of at least 3.17 mm should be
allowed. Normally, the longest edges of the board are
used for this purpose, and the actual width is dependent
on equipment capability. While no component lands or
fiducials can be in this area, breakaway tabs may be.
Interpackage spacing is a key aspect of DFM, and the
question of how close you can safely put components to
each other is a critical one. The following component
layout considerations are recommendations based on TI
experience:

There should be a minimum of 0.508 mm between

land areas of adjacent components to reduce the risk
of shorting.

The recommended minimum spacing between SMD

discrete component bodies is equal to the height of
the tallest component. This allows for a 45 soldering
angle in case manual work is needed.

Polarization symbols need to be provided for

discrete SMDs (diodes, capacitors, etc.) next to the
positive pin.

Pin-1 indicators or features are needed to determine

the keying of SMD components.

Space between lands (under components) on the

backside discrete components should be a minimum
of 0.33 mm. No open vias may be in this space.

The direction of backside discretes for wave solder

should be perpendicular to the direction through the
wave.

Do not put SMT components on the bottom side that

exceed 200 grams per square inch of contact area
with the board.

If space permits, symbolize all reference

designators within the land pattern of the respective
components.

It is preferable to have all components oriented in

well-ordered columns and rows.


   
  


Design for Manufacturability (DFM)

A well-designed board that follows the basic
surface-mount technology considerations greatly
improves the cost, cycle time, and quality of the end
product. Board design should comprehend the
SMT-automated equipment used for assembly, including
minimum and maximum dimensional limits and
placement accuracy. Many board shapes can be
accommodated, but the front of the board should have a
straight and square edge to help machine sensors detect
it. While odd-shaped or small boards can be assembled,
they require panelization or special tooling to process
in-line. The more irregular the boardnon-rectangular
with no cutoutsthe more expensive the assembly cost.
Fiducials (the optical alignment targets that align the
module to the automated equipment) should allow
vision-assisted equipment to accommodate the shrink
and stretch of the raw board during processing. They
also define the coordinate system for all automated
equipment, such as printing and pick-and-place. The
following guidelines may be helpful:

Automated equipment requires a minimum of two

and preferably three fiducials.

A wide range of fiducial shapes and sizes can be

used. Among the most useful is a circle 1.6 mm in
diameter with an annulus of 3.175/3.71 mm. The
outer ring is optional, but no other feature may be
within 0.76 mm of the fiducial.

Group similar components together whenever

possible.

Room for testing needs to be allowed.

The most useful placement for the fiducials is an

L configuration, which is orthogonal to optimize the
stretch/shrink algorithms. When possible, the
lower left fiducial should be the design origin
(coordinate 0,0).

All components should be within 101.6 mm of a

fiducial to guarantee placement accuracy. For large
boards or panels, a fourth fiducial should be added.
32

Solder Paste
TI recommends the use of paste when mounting
MicroStar BGAs. The use of paste offers the following
advantages:

It acts as a flux to aid wetting of the solder ball to the

PCB land.

The adhesive properties of the paste will hold the

component in place during reflow.
MicroStar BGA Packaging Reference Guide

Surface-Mounting MicroStar BGA Packages

It helps compensate for minor variations in the

planarity of the solder balls.

Paste contributes to the final volume of solder in the

joint, and thus allows this volume to be varied to give
an optimum joint.

Figure 21.

Solder Ball Collapse

0.40 0.05 mm
Land on PCB

Nearly as critical as paste selection is stencil design. A

proactive approach to stencil design can pay large
dividends in assembly yields and lower costs. In general,
MicroStar BGA packages are special cases of BGA
packages, and the general design guidelines for BGA
package assembly applies to them as well. There are
some excellent papers on BGA assembly, so only a brief
overview of issues especially important to MicroStar
BGA packages will be presented here.
The typical stencil hole diameter should be the same size
as the land area, and 125- to 150-m-thick stencils have
been found to give the best results. Good release and a
consistent amount of solder paste and shapes are
critical, especially as ball pitches decrease. The use of
metal squeegee blades, or at the very least, high
durometer polyblades, is important in achieving this.
Paste viscosity and consistency during screening are
some variables that require close control.

Solder Ball Collapse

In order to produce the optimum solder joint, it is
important to understand the amount of collapse of the
solder balls, and the overall shape of the joint. These are
a function of:

The diameter of the package solder ball via.

The diameter of the PCB land.

The volume and type of paste screened onto the

PCB.

The board assembly reflow conditions.

The weight of the package.

The original ball height on the package for a typical

0.8-mm-pitch package is 0.40 mm. After the package is
mounted, this typically drops to 0.35 mm, as illustrated in
Figure 21.
MicroStar BGA Packaging Reference Guide

PCB

0.35 mm typical

PCB
(Not to scale)

Controlling the collapse, and thus defining the package

standoff, is critical to obtaining the optimum joint
reliability. Generally, a larger standoff gives better solder
joint fatigue strength, but this should not be achieved by
reducing the board land diameter. Reducing the land
diameter will increase the standoff, but will also reduce
the minimum cross-section area of the joint. This, in turn,
will increase the maximum shear force at the PCB side
of the solder joint. Thus, a reduction of land diameter will
normally result in a worse fatigue life, and should be
avoided unless all the consequences are well
understood.

Reflow
Solder reflow conditions are the next critical step in the
mounting process. During reflow, the solvent in the
solder paste evaporates, the flux cleans the metal
surfaces, the solder particles melt, wetting of the
surfaces takes place by wicking of molten solder, the
solder balls collapse, and finally solidification of the
solder into a strong metallurgical bond completes the
process. The desired end result is a uniform solder
structure strongly bonded to both the PCB and the
package with small or no voids and a smooth, even fillet
at both ends. Conversely, when all the steps do not
carefully fit together, voids, gaps, uneven joint thickness,
discontinuities, and insufficient fillet can occur. While the
exact cycle used depends on the reflow system and
paste composition, there are several key points all
successful cycles have in common.
The first of these is a warm-up period sufficient to safely
evaporate the solvent. This can be done with a pre-heat
or a bake, or, more commonly, a hold in the cycle at
evaporation temperatures. If there is less solvent in the
paste (such as in a high-viscosity, high-metal-content
paste), then the hold can be shorter. However, when the
hold is not long enough to get all of the solvent out or too
fast to allow it to evaporate, many negative things
happen. These range from solder-particle splatter to
33


   
  


Paste selection is normally driven by overall system

assembly requirements. In general, the no clean
compositions are preferred due to the difficulty in
cleaning under the mounted component. Most assembly
operations have found that no changes in existing pastes
are required by the addition of MicroStar BGA, but due
to the large variety of board designs and tolerances, it is
not possible to say this will be true for any specific
application.

Surface-Mounting MicroStar BGA Packages

The second key point that successful reflow cycles have

in common is uniform heating across the package and
the board. Uneven solder thickness and non-uniform
solder joints may be an indicator that the profile needs
adjustment. There can also be a problem when different
sized components are reflowed at the same time. Care
needs to be taken when profiling an oven to be sure that
the indicated temperatures are representative of what
the most difficult to reflow parts are seeing. These
problems are more pronounced with some reflow
methods, such as infrared (IR) reflow, than with others,
such as forced hot-air convection.

Figure 22.

The profile shown in Figure 22 is an ideal one for use in

a forced-air-convection furnace, which is the most highly
recommended type. The best results have been found in
a nitrogen atmosphere.
The guidelines upon which this profile is based, also
shown in Figure 22, are general. Modification to the ideal
reflow profile will be driven by the interplay of
solder-paste particle size and flux percentage with
process variables such as heating rates, peak
temperatures, board construction factors and
atmosphere. These modifications are dependent upon
specific applications.
It should be noted that while they are more rugged than
most CSP-type packages, many MicroStar BGA
packages are still slightly moisture-sensitive at the time
of printing of this Reference Guide. The time out of a dry
environment should be controlled according to the label
on the packing material. This will prevent moisture
absorption problems with the package such as
popcorning, or delamination.

34


   
  


6090 sec
60120 sec
60150 sec
220C 5C
1020 sec
6C/sec maximum

Ideal Reflow Profile

300
200
100
0
0

100

200

300

Time (sec)
Note:

Finally, successful reflow cycles strike a balance among

temperature, timing, and length of cycle. Mistiming may
lead to excessive fluxing activation, oxidation, excessive
voiding, or even damage to the package. Heating the
paste too hot too fast before it melts can also dry the
paste, which leads to poor wetting. Process
development is needed to optimize reflow profiles for
each solder paste/flux combination.

Ideal Reflow Profile

RT to 140C:
140C to 180C:
Time above 183C:
Peak temperature:
Time within 5C peak temperature:
Ramp-down rate:

Temperature (C)

trapped gases, which can cause voids and

embrittlement. A significant number of reliability
problems with solder joints can be solved with the
warm-up step, so it needs careful attention.

This is an ideal profile, and actual conditions obtained

in any specific reflow oven will vary. This profile is based
on convection or RF plus forced convection heating.

Other concerns with BGA packages are those caused by

a PCB bowing or twisting during reflow. As PCBs get
thinner, these problems will become more significant.
Potential problems from these effects will show up as
open pins, hourglass solder joints, or solder
discontinuities. Proper support of the PCB through the
furnace, balancing the tab attachments to a panel, and,
in worst cases, using a weight to stiffen the PCB can help
prevent this. In general, the small size of CSPs create
fewer problems than standard BGAs. It is also true that
BGAs generally have fewer problems than leaded
components.

Inspection
MicroStar BGA packages have been designed to be
consistent with very high-yield assembly processes.
Because of their relatively light weight, MicroStar BGA
packages tend to self-align during reflow. Since the pitch
of the ball pattern is large compared to that of fine-pitch
leaded packages, solder bridging is rarely encountered.
It is recommended that a high-quality solder joint
assembly process be developed using the various
inspection and analytical techniques, such as
cross-sectioning. Once a quality process has been
developed, detailed inspection should not be necessary.
Visual methods, while obviously limited, can offer
valuable clues to the general stability of the process.
Electrical checks can confirm interconnection. Both
transmission X-rays and laminographic X-rays have
proven to be useful nondestructive tools, if desired.

MicroStar BGA Packaging Reference Guide

4

    

Packing and Shipping

MicroStar BGA Packaging Reference Guide

41

Packing and Shipping

MicroStar BGAs are shipped in either of two packing

methods:
Trays
Tape and reel

Trays
Thermally resistant plastic trays are currently used to
ship the majority of the packages. Each family of parts


    

Figure 23.

with the same package outline has its own individually

designed tray. The trays are designed to be used with
pick-and-place machines. Figure 23 gives typical tray
details, and Table 6 shows the number of units per tray.
Figure 24 shows the packing method used to ship trays.
Before the trays are sealed in the aluminum-lined plastic
bag, they are baked in accordance with the requirements
for dry-packing at the appropriate level.

Shipping Tray Detail

Table 6. Number of Units per Shipping Tray

Body
Size
(mm)

42

Package Code

Matrix

Units/
Tray

Units/
Box

16 x 16

GZY, GHK

6 x 15

90

450

15 x 15

GGW,GHC

6 x 15

90

450

13 x 13

GHG, GHJ, GHV

8 x 20

160

800

12 x 12

GZG, GGB

8 x 20

160

800

11 x 11

GGT

8 x 20

160

800

10 x 10

GGF, GHZ, GGM

8 x 25

200

1000

8x8

GGV, GJJ

9 x 25

225

1125

9 x 13

GFZ, GHB, GHN

10 x 18

180

900

MicroStar BGA Packaging Reference Guide

Packing and Shipping

Figure 24.

Packing Method for Trays

1. Arrange the stack of trays to be packed with a tray pad on top and
bottom.

4. Wrap and tape bubble pack around the bag for a snug fit in the inner
carton. Place the necessary labels on the inner carton.

Tray
pad

ESD
label

Tray
stack

Tray
pad

Bar-code
label
5. Add bubble pack around the inner carton for a snug fit in the
skidboard liner.
2. Strap the tray stack and pads together with four strapsthree
crosswise and one lengthwise. Then place the desiccants and the
humidity indicator on top.


    

Humidity
indicator

Desiccant
packs

3. Place the lot inside the aluminum-lined bag and vacuum-seal it.
Place the necessary labels on the sealed bag.

6. Place four foam corner spacers on the folded skidboard liner before
placing it in the outer carton. An enhanced skidboard liner, which
eliminates the need for foam corner spacers, may be used. Seal
outer carton and apply necessary labels.

Aluminum-lined
bag

ESD
label

Moisture-sensitivity label
Bar-code
label

MicroStar BGA Packaging Reference Guide

43

Packing and Shipping

Tape-and-Reel Packing Method

The embossed tape-and-reel method is generally
preferred by automatic pick-and-place machines. This
will be the standard way MicroStar BGA packages will be
shipped. Trays will remain an option for those customers
who prefer them. The tape is made from an
antistatic/conductive material. The cover tape, which
peels back during use, is heat-sealed to the carrier tape
to keep the devices in their cavities during shipping and
handling. The tape-and-reel packaging used by Texas
Instruments is in full compliance with EIA
Standard 481-A, Taping of Surface-Mount Components
for Automatic Placement. The static-inhibiting materials
used in the carrier-tape manufacturing provides device

Figure 25.

protection from static damage, while the rigid, dust-free

polystyrene reels provide mechanical protection and
clean-room compatibility with dereeling equipment
currently available on most high-speed automated
placement systems.

Tape Format
Typical tape format is shown in Figure 25. The variables
used in Figure 25 and Table 7 are defined as follows:
W is the tape width; P is the pocket pitch; A0 is the pocket
width; B0 is the pocket length; K0 is the pocket depth; K is
the maximum tape depth; and F is the distance between
the drive hole and the centerline of the pocket.

Single Sprocket Tape Dimensions

4.0 0.10

1.75 0.1

+ 0.1
1.5 0.0

2.00 0.05

K
0.8 MIN

0.40

F
W


    

B0

Cover
tape

A0

Carrier tape
embossment

0 MIN

1.5 MIN
Diameter

Direction
of feed

Notes:

K0

A. Tape widths are 16 and 24 mm.

B. Camber per EIA Standard 481-A
C. Minimum bending radius per
EIA Standard 481-A
D. All linear dimensions are in millimeters.

Table 7. Tape Dimensions

Tape Width
(W)

Pocket Pitch
(P)

Pocket Width
(A0)

Pocket Length
(B0)

Pocket Depth
(K0)

Max. Tape
Depth (K)

Centerline to
Drive Hole (F)

Package
Size

16

12

8.2

8.2

1.7

2.0

7.5

8x8

24

16

10.2

10.2

1.7

2.0

11.5

10 x 10

24

16

11.35

11.35

1.9

2.2

11.5

11 x 11

24

16

12.4

12.4

1.9

2.2

11.5

12 x 12

24

20

15.25

15.25

2.2

2.5

11.5

15 x 15

All dimensions are in millimeters.

44

MicroStar BGA Packaging Reference Guide

Packing and Shipping

Figure 26.

Reel Dimensions
N is the diameter of the reel hub.
T MAX

13.0 0.2

+ 0.0
330 4.0

20.2 MIN

2.5 MIN
G

1.5 MIN width

Note A: All linear dimensions are in millimeters.

TI bar code label

Table 8. Reel Dimensions

Tape
Width
(G)

Reel Hub
Diameter
(N)

Reel Total
Thickness
(T MAX)

Parts per
Reel

16

100

28

1000

24

100

28

1000

Devices are inserted toward the outer periphery of the

tape by placing the side with the device name face up and
the side with the balls attached face down. The pin-1
indicator is placed in the top right-hand corner of the
pocket, next to the sprocket holes.

All dimensions are in millimeters.

The reels are shown in Figure 26. In this figure, G is the

width of the tape, N is the diameter of the hub, and T is
the total reel thickness.
After the parts are loaded into the reel, each individual
reel is packed in its own pizza box for shipping, as
shown in Figure 27.
Figure 27.

Tape-and-Reel Packing

Desiccant
Humidity
indicator

Packaging Method
For reels, once the taping has been completed, the end
of the leader is fixed onto the reel with tape. The product
name, lot number, quantity, and date code are recorded
on the reel and the cardboard box used for tape delivery.
Each reel is separately packed in a cardboard box for
delivery.
Trays are packed with five loaded trays and one empty
tray on top for support and to keep packages secure. The
stack is secured with stable plastic straps and sealed in
a moisture-proof bag.

Reeled units
Aluminum
bag

Pizza box

Bar code

Customer-specific bar code labels can be added under

request or general purchasing specification.
Moisture-sensitive packages are baked before packing
and are packed within 8 hours of coming out of the oven.
Both the tape-and-reel and the tray moisture-proof bags
are sealed and marked with appropriate labeling warning
that the packages inside the bags are dry-packed and
giving the level of moisture sensitivity.

ESD label

MicroStar BGA Packaging Reference Guide

45


    

Device Insertion


    

Packing and Shipping

46

MicroStar BGA Packaging Reference Guide



Sockets

MicroStar BGA Packaging Reference Guide

51

Sockets

The Design Challenge

The fine pitch of MicroStar BGA packages makes
socketing a special challenge. Mechanical, thermal, and
electrical issues must be accommodated by the socket
designer. CSP packaging is at the cutting edge of
package design and it appears that it is being adopted
faster than any other previous package technology.
Standards are only now beginning to be established. TI
fully supports these efforts, and all MicroStar BGA
outlines are being engineered to fit within JEDEC
standards where they exist. For instance, all
0.8-mm-pitch packages fit within JEDEC MO205. While
these standards detail the pitch and I/O placement, they
do allow wide latitude for overall body size variation. The
size of a specific package within the TI MicroStar BGA
family is based on the package construction, and is
independent of die size. Thus, a range of die sizes and
I/Os within a family will have the same package
dimensions. Each different family has a specific I/O pitch
and array. For maximum socket versatility, an adapter or
personalizer can be customized for each application,
allowing a single-socket body to be used with many
packages. This feature is especially useful in the early
days as the technology is being developed and adopted
and the total volume required is small.

Contacting the Ball

A number of different approaches for contacting the solder ball are shown schematically in Figure 28. The pinch
style contact has been used extensively for contacting
solder balls in conventional BGAs. A benefit of the pinch
style is that the socket does not have to push down on the
package to provide the necessary contact force to penetrate the oxide film on the solder balls. The issues in utilizing this approach for pitches below 1.27 mm involve:

Figure 28.

Approaches for Contacting the Solder

Ball

a) Metal pinch

c) Rough bump on flex

e) Etched pocket in silicon

Figure 29.

b) Metal Y

d) Conductive

f) Metal

Pinch Contact for Solder Balls

1. Miniaturizing the contact



2. Developing injection-molding tooling for the pitch

3. Developing cost-effective manufacturing procedures for handling and assembling the fragile contact
For pitches of 0.75 mm and above, Texas Instruments
has designed a pinch contact that satisfies all of these
requirements. Further information on the availability of
these sockets can be obtained from your local TI Field
Sales representative.
The contact is designed to grip the solder ball with a
pinching action. This not only provides electrical contact
to the solder ball but also helps retain the package in the
socket. The contact is shown in Figure 29. The contact
is stamped and formed from a 0.12-mm-thick strip of
CDA 172, the high-yield-strength beryllium copper alloy.
This alloy is used for spring applications that are exposed
to high stresses and temperatures because of its
excellent stress relaxation performance and formability.
52

Each contact incorporates two beams that provide an

oxide-piercing interface with the sides of the balls above
the central areathe equator. Since the contact is above
the equator, the resultant force is downward and ensures
package retention in the socket. No contact is made on
MicroStar BGA Packaging Reference Guide

Sockets

the bottom of the solder ball and the original package

planarity specifications are unchanged. A photomicrograph of the contact touching the solder balls is
shown in Figure 30.
Figure 30.

Figure 32.

Effect of Burn-in on Probe Marks

Contact Area on Solder Ball

Establishing Contact Force

The witness marks left on the solder ball from the contact
are shown in Figure 31. This ball was contacted at room
temperature and it is clear that there was no damage to
the bottom of the ball or any witness marks from the
contact above the equator.
The effect of burn-in on the probe marks was examined
by simulating a cycle and placing a loaded socket into an
oven at 125C for 9 hours. The result is shown in
Figure 32. The penetration of the contact into the solder
ball due to the higher temperature is greater but is well
within the acceptable range. There was no visible pickup
of solder on the contact tips. This experiment is being
continued to evaluate the impact of longer times on the
witness marks and the solder pickup. The location of the
contact pinch is clearly seen in this photograph.
Figure 31.

Contact force is typically generated as a result of the

deflection of the contact arm. The actual force generated
is a function of the modulus of the material and the
specific geometric details of the design. The solder ball
diameters for CSPs tend to be smallin the range of
0.25 mm to 0.4 mm, which limits the deflection of the
contact arm to a very small distance. Typically, this
distance is half the ball diameter. This presents a
challenge to the designer who must generate the
required 15 grams of force at the contact tip, yet keep the
bending stresses within the contact arms at a low enough
value to achieve a 20K-cycle life. The contact force
requirements are met by incorporating a pre-load, so that
even for small displacements, the desired force is
achieved and the socket can operate within acceptable
stress levels.
The 15-gram target force is smaller than that associated
with TSOP-type contact force levels, which require a
30-gram minimum. However, based on the contact tip
geometry, this lower force translates to contact
pressures that are high enough to achieve oxide
penetration and good electrical continuity.

Witness Marks on Solder Ball

The importance of continuing the development to
0.5-mm pitch is clear. End users want more and more
electronic functionality in smaller and smaller packages.
Sockets for testing these fine pitches are available today
but are specialty and are considered too expensive for
broad commercial application. Continued development
includes innovative approaches as well as refining
present methods, but at the time of the preparation of this
Reference Guide, a clear-cut favorite technology had not
emerged. For current progress in this and other areas of
0.5-mm-pitch technology, your local TI Field Sales
representative can give you up-to-date information.

MicroStar BGA Packaging Reference Guide

53



Conclusions and Future Work

Sockets

early days of the introduction of a new technology and is

due entirely to the embryonic state of the industry and the
low volume. It is believed that once this packaging
technology matures and volumes increase to those of
conventional burn-in sockets, then the prices for sockets
for CSPs will decrease and be more in line with other
commercial sockets.



Growth rates as high as 400% for CSPs in 1998 over

those in 1997 have been forecasted. The opportunity to
participate in a market with this growth has provided the
incentive for the socket companies to develop solutions
for the infrastructure needed for burn-in test sockets. The
issues of contacting the small, soft solder balls on CSPs
have been solved. The price disparity between CSP
sockets and TSOP sockets is to be expected during the

54

MicroStar BGA Packaging Reference Guide

  

Lead-Free Solutions

MicroStar BGA Packaging Reference Guide

61

Lead-Free Solutions

Environmental concerns are driving the need for

lead-free solutions to electronic components and
systems. Texas Instruments (TI) has been a leader in
working with our customers to provide them with
products which meet their specific needs. The first
practical lead-free alternative was the Nickel/Palladium
(Ni/Pd) finish introduced by TI in 1989. Since then, more
than 30 billion lead-free Ni/Pd components have been
supplied. Texas Instruments continues to be active in this
field, working with other manufacturers to evaluate other
lead-free finishes to understand their manufacturability
and reliability.
Continuing this position of leadership, TI has introduced
a lead-free solder ball option for the MicroStar BGA
packages. Texas Instruments is also evaluating
lead-free solder ball applications for other area array
packages. In conjunction with this effort, TI is an active
participant in the industry-wide effort to evaluate

lead-free solder alloys and lead-free printing wiring

board finishes. Several of the lead-free systems being
proposed require a maximum reflow temperature higher
than that needed with the Sn/Pb systems, so package
and system reliability data must be developed. Securing
the required Board Level Reliability (BLR) under various
customer conditions depends on many factors: solder
ball composition, solder paste, PCB design, land finish
and reflow conditions.
The composition TI has selected for lead-free MicroStar
BGA packages is an Sn-Ag-Cu alloy. Reliability data
presented in Table 9 shows it to be a robust performer,
equivalent to the Sn/Pb eutectic balls it replaces.
Extensive assembly testing has shown it to be virtually
indistinguishable from Sn/Pb eutectic ball performance
in current systems and superior in high temperature,
lead-free systems. Figure 33 shows a summary of these
tests.

Table 9. Component Reliability Testing and BLR for Pb-free Solder Balls
TEST VEHICLE:

64GGV:D76563GGV

257GJG:F712521GJG

257GHK:F722500AGHK

BODY SIZE:

8 mmsq

16 mmsq

16 mmsq

CHIP SIZE:

230 x 225 mil

407 x 407 mil

312 x 312 mil

TEST ITEM

CRITERIA

TEST RESULTS

PRECON (LEVEL3)

0/All sample

64GGV:0/330, 257GJG:0/330, 257GHK:0/84

(Condition: 125C 24h Bake 30C/60% 192h Soak IRR peak255260x3time Elec. test)
THB (85oC/85%, 3.6 V)
STRG

(150oC)

0/77/600h

257GHK:0/78/1000h,

0/77/600h

64GGV:0/78/1000h,

257GJG:0/78/1000h

T/C (55/+125oC)

0/77/1000cy

64GGV:0/78/1000cy,

257GJG:0/78/1000cy

T/S (55/+125oC)

0/77/200cy

64GGV:0/78/1000cy,

257GJG:0/78/1000cy

PCT

0/77/96h

64GGV:0/78/240h,

257GJG:0/78/240h

BLR (40/+125oC)

0/77/1000cy

64GGV:0/96/1000cy,

257GJG:0/96/1000cy

  

(Solder paste for PCB mount: Sn/2.5Ag/1Bi/0.5Cu)

62

MicroStar BGA Packaging Reference Guide

Lead-Free Solutions

Figure 33.

Assembly Testing of Eutectic vs. Pb-free Solder Balls

Sn/Pb Ball

Transition
Period

Pb-free Paste
250oC reflow

Current

Goal

Sn/Pb Ball
Sn/Pb Paste

Pb-free Ball
Pb-free Paste

230oC reflow

250oC reflow

Pb-free Ball
Sn/Pb Paste
230oC reflow

Not recommended

Because IRR peak temperature

is not good enough for making
consistent solder joint

The higher reflow temperatures required with the

lead-free solders present challenges in two areas: BLR
and component moisture sensitivity testing. A
representative standard reflow profile for Sn/Pb eutectic
solder is shown in Figure 34. The 235C peak represents
the highest recommended peak for current package
Standard Reflow Profile for Pb/Sn Alloy Solder

Recommended Reflow Profile

In the case of Sn/Pb eutectic solder paste

oC

235

  

Figure 34.

moisture levels. The new alloys will require a peak

temperature well in excess of even the 235C shown.
While the exact temperature requirements are not well
established, the profile shown in Figure 35 represents
the cycle TI recommends for preconditioning and other
non-Pb evaluation studies.

Peak Temperature
235oC Max < 10 sec

200
30 60 sec
160
140

90 +/ 30 sec

15oC/sec

time
Reflow temperature is defined at package top.

MicroStar BGA Packaging Reference Guide

63

Lead-Free Solutions

Figure 35.

Example Reflow Profile for Non-Pb Alloy Solder Evaluation/Preconditioning

Texas Instruments Recommended 260oC Reflow Profile
300.0

Temperature (C)

250.0

200.0

150.0

100.0

50.0

0.0
0

20

40

60

80

100

120 140 160 180

200 220

240 260 280 300 320 340 360 380 400

Time (seconds)
Reflow temperature is defined at package top.

Moisture Sensitivity

Evaluation flow: 30C/60%/192hr Soak (JEDEC level 3)

+ IRR 3 times
Pkg.
Type

Pkg.
Size
(mm)

Chip
Size
(mm)

260oC Chip Surface

Delamination

GGV64

88

55

0/24 (8 3 lot)

GGM100

10 10

7.5 7.5

0/24 (8 3 lot)

GGB128

12 12

99

0/24 (8 3 lot)

GJG257

16 16

10 10

0/24 (8 3 lot)

  

A drop of 2+ levels in moisture sensitivity (as per

J-STD-20) has been indicated for several package types
with the peak temperature of 260C. Extensive testing of
MicroStar BGA packages has shown they are capable of
resisting the 260C cycles without an impact on the
moisture sensitivity classification. Data shown in
Table 10 shows several package and die sizes. The
Scanning Acoustic Microscope (SAM) picture in
Figure 36 is typical of the results obtained.

Table 10. Moisture Sensitivity Test Results

64

MicroStar BGA Packaging Reference Guide

Lead-Free Solutions

Figure 36.

Typical SAM Pictures After Moisture

Sensitivity Testing

Evaluation flow: 30C/60%/192hr Soak + IRR 3 times

SAM picture

Package: GJG257 (1616 mm)

Chip: 10 x 10 mm
MSL:L3
IRR peak temperature: 256.4C

Board Land Finishes and Solder Paste

Any study of BLR must take into account the many
choices available to the PCB manufacturer. There are at
least two main board land finishes and many candidates
for the solder paste. The board finishes are generally an
organic protective layer over bare copper or an Ni plate
protected with Au flash. The organic finishes are
formulated to protect the bare copper from oxidation but
to burn off early enough in the reflow cycle so they do not
interfere with the soldering. The various lead-free solder
paste candidates are generally tin-based with various
metals added as alloying compounds. Texas
Instruments conducted a series of tests with two of these
newer solder paste over both types of board finishes.
Lead-free balls on the packages were used. As a control,
the present near-eutectic solder balls were used. The
solder paste compositions used are listed in Table 11.
Table 11. Solder Paste Compositions
Reflow
Peak for
Soldering
Evaluation
(oC)

Liquidus
Temp
(oC)

Sn

Pb

Ag

Bi

Cu

Eutectic
(ref.)

183

183

63

37

230

Pb-free-1

216

220

95.75

3.5

0.75

250

Pb-free-2

205

220

94.25

0.75

250

The results on 0.8-mm-pitch MicroStar BGA are shown

in Figure 37, Figure 38, and Figure 39. Figure 37 shows
that for the current Sn/Pb solders, there is virtually no
difference in performance between the lead-bearing and
the lead-free ball compositions. However, as the new,
lead-free solders are introduced, the lead-free balls
delay the onset of failure, usually by a significant amount.
Failure does tend to be on a steeper slope, and further
work is being done to explain this phenomenon. Of
additional interest, in each case, the pure copper was
superior to the gold-bearing surface. In the case of the
leaded solders, this is expected due to the well-known
embrittlement of lead by gold. In the lead-free systems,
not as much detailed analysis has been done and no
detailed explanation exists.

MicroStar BGA Packaging Reference Guide

65

  

Metal Composition (wt%)

Solidus
Temp
(oC)

Solder
Paste

Lead-Free Solutions

Figure 37.

Board-Level Reliability Study

(Solder Paste: Sn/Pb Eutectic)

Figure 38.

Board-Level Reliability Study

(Solder Paste: Pb-free-1)

PCB land : Cu bare

PCB land : Cu bare

99%

90%
80%
70%
60%
50%
40%
30%
20%

Cumulative Probability

Cumulative Probability

99%

Pb-free
solder ball
Standard
solder ball

10%

1%

1000
cycles

100

90%
80%
70%
60%
50%
40%
30%

Pb-free
solder ball

20%
10%

Standard
solder ball
1%

10000

100

1000
cycles

10000

PCB land : Au/Ni finish

PCB land : Au/Ni finish

99%
90%
80%
70%
60%
50%
40%
30%
20%

Standard
solder ball

Cumulative Probability

Cumulative Probability

99%

Pb-free
solder ball

10%

1%

100

1000
cycles

Standard
solder ball
Pb-free
solder ball

20%
10%

1%

100

1000
cycles

10000

Package: 12 12 mm body, 144i/o, 0.8 mm ball pitch

Chip: 6-mmsq daisy-chain test chip,
PCB: FR-4 25 30 0.8 mmt
Solder paste: Pb-free-1 (Sn/Ag/Cu), Reflow temp: max 250C
Test condition: 40/ +125C, 10/10 min

  

Package: 12 12 mm body, 144i/o, 0.8 mm ball pitch

Chip: 6-mmsq daisy-chain test chip,
PCB: FR-4 25 30 0.8 mmt
Solder paste: Sn/Pb eutectic, Reflow temp: max 230C
Test condition: 40/ +125C, 10/10 min

10000

90%
80%
70%
60%
50%
40%
30%

66

MicroStar BGA Packaging Reference Guide

Lead-Free Solutions

Figure 39.

Board-Level Reliability Study

(Solder Paste: Pb-free-2)

PCB land : Cu bare

Cumulative Probability

99%
90%
80%
70%
60%
50%
40%
30%
20%

Pb-free
solder ball

Standard
solder ball

10%

1%

100

1000
cycles

10000

PCB land : Au/Ni finish

Cumulative Probability

99%
90%
80%
70%
60%
50%
40%
30%
20%
10%

For many applications, such as wireless phones,

electrical reliability after repeated mechanical
displacements is a critical parameter. This is commonly
measured with a Key Push Test, shown in Figure 40. An
evaluation board with a daisy-chained package mounted
to it is continually cycled by a load cell. The load is applied
from the PCB backside at a constant stain of
1300 microstrain through a distance of 3.5 mm at a
constant frequency. Electrical resistivity is continuously
monitored and when it reaches 1.2 times the initial value,
the test is terminated. A typical test pattern is seen in
Figure 41. While there are no specific industry-wide
limits for this test, Texas Instruments has determined that
20k cycles for 0.8-mm-pitch packages and 10k cycles
for 0.5-mm-pitch packages represent acceptable
guidelines. Typical results for MicroStar packages are
shown in Figure 42 .

Pb-free
solder ball

Standard
solder ball

1%

100

1000

10000

cycles

  

Package: 12 12 mm body, 144i/o, 0.8 mm ball pitch

Chip: 6-mmsq daisy-chain test chip,
PCB: FR-4 25 30 0.8 mmt
Solder paste: Pb-free-2 (Sn/Ag/Cu/Bi), Reflow temp: max 250C
Test condition: 40/ +125C, 10/10 min

MicroStar BGA Packaging Reference Guide

67

Lead-Free Solutions

Figure 40.

Key Push Test Apparatus

Load cell
120 30 0.8 mm FR-4

90 mm
Offset push
1300 microstrain at B/D near package corner
100 cyc/min > 20 kcyc (for 0.8-mm pitch)
> 10 kcyc (for 0.5-mm pitch)

Figure 41.

Typical Key Push Test Results

Test Termination Criteria: Resistance is 1.2X from initial.

1.95E+01
1.90E+01
1.85E+01
1.80E+01

Resistance ()

  

1.75E+01
1.70E+01
1.65E+01
1.60E+01
1.55E+01
1.50E+01
1.45E+01
1.40E+01
1

223

445

667

889

1111

1333 1555 1777 1999 2221 2443 2665 2887 3109 3331 3553 3775 3997 4219 4441 4663 4885

Key push cycle

68

MicroStar BGA Packaging Reference Guide

Lead-Free Solutions

Figure 42.

Key Push Test Performance

Key Push Test Performance :GHZ151 (0.5mmP)

90000

N=4
Average

80000
Key Push Cycle (cyc)

Minimum
70000

Maximum

60000
50000
40000
30000
20000
10000
0

Ball

Sn/Pb/0.4Ag
Au/Ni

OSP

Pb-free system

Sn/Pb system

Solder paste
PCB

Au/Ni

Sn/2.5Ag/1Bi/0.5Cu
OSP

Au/Ni

OSP

Summary
Lead-free MicroStar BGAs showed feasible BLR

New packages are being added to the list of MicroStar

BGAs available in the Pb-free version every day. Contact
your local Field Sales representative for the current list
of available packages along with qualification notices
and reliability data.

  

performance with Sn/Ag/Cu and Sn/Ag/Cu/Bi solder

paste. The Pb-free balls performed better with

non-Pb-containing solder paste in 0.8-mm-pitch
applications.
Evaluation samples with daisy-chained chips are
already available.
Individual customer requirements may need specific
BLR evaluation to ensure compliance. Key factors
include:
PCB specification
Solder paste
Single-side mount or double-side mount?
Reflow condition
Package location on PCB
Storage condition (environment for board
mount)
Criteria of requirement (BLR, mechanical
performance)
Other

MicroStar BGA Packaging Reference Guide

69

  

Lead-Free Solutions

610

MicroStar BGA Packaging Reference Guide



References

MicroStar BGA Packaging Reference Guide

71

References

K. Ano et al., MicroStar BGAs, Application Note,

TI SCJ 2328, July 1998.
Gerald Capwell, High Density Design with MicroStar
BGAs, Texas Instruments Application Note, July 1998.
James Forster, Performance Drivers for Fine Pitch BGA
Sockets, Chip Scale Processing, June 1998.

Les Stark and Mhamed Idnabdeljalil, MicroStar BGA

vs. FC-CSP: Finite Element Simulation of BLR
Performance: 144GGF Footprint, Texas Instruments
Application Note, August 1998.



Kevin Lyne, Chip Scale Packaging From Texas

Instruments: MicroStar BGA, Texas Instruments
Application Note, June 1997.

Gary Morrison, Les Stark, Ron Azcarte, S. Capistrano,

K. Ano, K. Murata, M. Watanabe, T. Ohuchida,
Y. Takahashi, Greg Ryan, MicroStar BGA Packaging:
Critical Interconnections, SEMICON 98.

72

MicroStar BGA Packaging Reference Guide

Appendix

A
Frequently Asked Questions
Package Questions
Q. Do the solder balls come off during shipping?
A. No, this has never been observed. The balls are
100% inspected for coplanarity, diameter, and other
physical properties prior to packing for shipment.
Because solder is used during the ball-attachment
process, uniformly high ball-attachment strengths
are developed. Also, the ball-attachment strength is
monitored frequently in the assembly process to
prevent ball loss from vibration and other shipping
forces.
Q. Is package repair possible? Are tools available?
A. Yes, some limited package repair is possible, and
there are some semiautomatic M/C tools available.
However, TI does not guarantee the reliability of
repaired packages.
Q. What are the leads that appear on the package
edge for? Are they connected to the inner
pattern?
A. Those leads are used for plating connections during
the plating of Ni/Au on the copper trace during the
fabrication of the substrate. Since they do have
electrical connection with the inner pattern, they can
be used for test probing and signal analysis. There
is no reliability risk with them.
Q. What is the composition and melting point of the
solder balls?

A. There are commercial sockets available for

1.00-mm and 0.8-mm pitch package burn-in.
Sockets for 0.5-mm pitch packages are now
becoming available. Vendors include Texas
Instruments, Yamaichi, Wells and Enplas. The ball
damage observed falls within specified tolerances,
so the testing does not affect board mount.
Q. Is tape-and-reel shipping available?
A. Tape-and-reel is the preferred method for shipping
MicroStar BGA packages. Tray shipping methods
are available upon customer request.
Q. What about actual market experience?
A. Since TI started production in May of 1996, well over
70 million units have been shipped. End products are
primarily DSP Solutions such as wireless phones
and digital camcorders where MicroStar BGA can
create significant space savings. Technologies
available in MicroStar BGAs include DSP, ASIC,
Mixed Signal, and Linear devices.
Q. How does the packaging cost compare to QFPs?
A. CSPs are in many ways an ideal solution to cost
reduction and miniaturization requirements. They
offer enormous area reductions in comparison to
QFPs and have increasing potential to do so without
adding to system-level costs. In the best case, CSPs
compete today on a cost-per-terminal basis with
QFPs. For example, various CSPs from Texas
Instruments are now available at cost parity with thin
QFPs.
  



A. The balls are a near-Sn/Pb eutectic solder that

includes some additives to improve thermal fatigue
life. The liquidus temperature is 178C to 210C.

Q. Is burn-in testing possible? How about ball

damage?

MicroStar BGA Packaging Reference Guide

A1

Frequently Asked Questions

Assembly Questions
Q. What alignment accuracy is possible?
A. Alignment accuracy for the 0.8-mm-pitch package is
dependent upon board-level pad tolerance,
placement accuracy, and solder ball position
tolerance. Nominal ball position tolerances are
specified at 80 m. These packages are
self-aligning during solder reflow, so final alignment
accuracy may be better than placement accuracy.
Q. Can the solder joints be inspected after reflow?
A. Process yields of 5-ppm (parts per million) rejects
are typically seen, so no final in-line inspection is
required. Some customers are achieving
satisfactory results during process set-up with
lamographic X-ray techniques.
Q. How do the board assembly yields of MicroStar
BGAs compare to QFPs?

A. Texas Instruments recommends alignment with the

solder balls for the CSP package, although it is
possible to use the package outline for alignment.
Most customers have found they do not need to
change their reflow profile.
Q. Can the boards be repaired?
A. Yes, there are rework and repair tools and profiles
available. We strongly recommend that removed
packages be discarded.
Q. Is TI developing a lead-free version of MicroStar
BGAs?
A. Yes, Texas Instruments is working toward
eliminating lead in the solder balls to comply with
lead-free environmental policies. The lead-free
solder is in final evaluation. Only the solder will
change, not the package structure or the mechanical
dimensions. The solder system under development
is based on Sn-Ag metallurgy. Check with your local
TI Field Sales representative for sample availability.
Q. What size land diameter for these packages
should I design on my board?
A. Land size is the key to board-level reliability, and
Texas Instruments strongly recommends following
the design rules included in this bulletin.

  



A. Many customers are initially concerned about

assembly yields. However, once they had MicroStar
BGAs in production, most of them report improved
process yields compared to QFPs. This is due to the
elimination of bent and misoriented leads, the wider
terminal pitch than with 0.5-mm-pitch QFPs, and the
ability of these packages to self-align during reflow.
The collapsing solder balls also mean that the
coplanarity is improved over leaded components.

Q. Are there specific recommendations for SMT

processing?

A2

MicroStar BGA Packaging Reference Guide

Appendix

B
Package Data Sheets
strategic package lineup. Contact your TI field sales
office for information on the most current offerings.
Samples are available for all packages shown in
Figure 43.

Figure 43 shows TIs strategic package lineup, followed

by the package data sheets for the package families
offered as standard products by Texas Instruments. As
new packages are added, they will be placed on the
Figure 43.

TIs Strategic Package Line-Up

MicroStar BGA
Package Product Guide
Strategic Package Lineup: HIJI and Philippines

PITCH (mm)

PACKAGE SIZE (mm)

66

88

GJK 80

GJJ 167

10 10
GHZ 151

GGF 100

Qual: Complete

Qual: Complete

0.5

Qual: 4Q 99
88
GGV 64

0.8

Qual: Complete

Qual: 4Q 99

10 10
GGM 80

Qual: Complete

11 11
GGT 100

12 12
GGU 144

GGW 176

16 16

1.0 mm PITCH
GHC 196

Qual: Complete
Qual: Complete

GHK 257

Qual: Complete
Qual: Complete

GGM 100

GHH 179

GGW 208

GGW 240

Qual: Complete

Qual: Complete

Qual: Complete

Qual: Complete

GJG 257

Qual: Complete


  

 



Qual: Complete

15 15

MicroStar BGA Packaging Reference Guide

B1

Package Data Sheets

 

 
 '  ""  "" $ &
GJK (S-PBGA-N80)

PLASTIC BALL GRID ARRAY

GJK 80 TOP VIEW

DAISY CHAIN NET LIST

9
8
7
6
5
4
3
2
1

INDEX
MARK
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration

A
B1C1
D1E1
F1G1
H1J1
J2J3
J4J5
J6J7
J8J9
H9G9
F9E9

Electrical Characteristics

Thermal Characteristics

D9C9
B9A9
A8A7
A6A5
A4A3
A2B2
C2D2
E2F2
G2H2
H3H4

GJK 80

$$# ' 
! & &%

Productization

PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

D E

G H

H5H6
H7H8
G8F8
E8D8
C8B8
B7B6
B5B4
B3C3
D3E3
F3G3

J
G4G5
G6G7
F7E7
D7C7
C6C5
C4D4
E4F4
F5F6
E6D6
D5E5

PIN ASSIGNMENT NET LIST

BALL#
C2
B1
D3
E4
C1
D2
E3
D1
E2
F4
E1
F3
F1
F2
G3
G1
G2
H2
H1
J1

PIN#
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

BALL#
H3
J2
G4
F5
J3
H4
G5
J4
H5
F6
J5
G6
J6
H6
G7
J7
H7
H8
J8
J9

PIN#
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

BALL#
G8
H9
F7
E6
G9
F8
E7
F9
E8
D6
E9
D7
D9
D8
C7
C9
C8
B8
B9
A9

PIN#
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

BALL#
B7
A8
C6
D5
A7
B6
C5
A6
B5
D4
A5
C4
A4
B4
C3
A3
B3
B2
A2
E5

MicroStar BGA is a trademark of Texas Instruments.

B2

MicroStar BGA Packaging Reference Guide

Package Data Sheets


  
 )  $$  $$ &"(!
GJJ (S-PBGA-N167)

PLASTIC BALL GRID ARRAY

GJJ 167 TOP VIEW

DAISY CHAIN NET LIST

13
12
11
10
9
8
7
6
5
4
3
2
1

Electrical Characteristics

Thermal Characteristics

INDEX MARK

A B C D E F G H J K L M N

B1C1 F3G3
D1E1 H3J3
F1G1 K3L3
H1J1 M3M4
K1L1 B4B5
M1N1 C4D4
A2B2 E4F4
C2D2 G4H4
E2F2 J4K4
G2H2 L4L5
J2K2 N4N5
L2M2 A5A6
N2N3 C5C6
A3A4 D5E5
B3C3 F5G5
D3E3 H5J5
NC F7

K5K6
M5M6
B6B7
D6D7
E6F6
G6H6
J6J7
L6L7
N6N7
A7A8
C7C8
E7E8
H7H8
K7K8
M7M8
B8B9

D8D9
F8G8
J8J9
L8L9
N8N9
A9A10
C9C10
E9F9
G9H9
K9K10
M9M10
B10B11
D10E10
F10G10
H10J10
L10L11

GJJ 167

N10N11 G13H13
A11A12 J13K13
C11D11 L13M13
E11F11
G11H11
J11K11
M11M12
B12C12
D12E12
F12G12
H12J12
K12L12
N12N13
A13B13
C13D13
E13F13

PIN ASSIGNMENT NET LIST

PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL#

Productization

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

C3
D4
B1
C2
D3
E4
C1
D2
E3
D1
F5
E2
F4
E1
F3
F2
F1
F6
F7
G1
G2
G3
G4
H1
H2
G5
J1
H3

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

J2
H4
K1
J3
K2
H5
L1
J4
L2
M1
K3
J5
M2
N1
L3
K4
N2
M3
L4
K5
N3
M4
L5
N4
J6
M5
K6
N5

57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

L6
M6
N6
H6
G6
N7
M7
L7
K7
N8
M8
J7
N9
L8
M9
K8
N10
L9
M10
J8
N11
K9
M11
N12
L10
J9
M12
N13

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

L11
K10
M13
L12
K11
J10
L13
K12
J11
K13
H9
J12
H10
J13
H11
H12
H13
H8
H7
G13
G12
G11
G10
F13
F12
G9
E13
F11

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

E12
F10
D13
E11
D12
F9
C13
E10
C12
B13
D11
E9
B12
A13
C11
D10
A12
B11
C10
D9
A11
B10
C9
A10
E8
B9
D8
A9

PIN# BALL#
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167

C8
B8
A8
F8
G8
A7
B7
C7
D7
A6
B6
E7
A5
C6
B5
D6
A4
C5
B4
E6
A3
D5
B3
A2
C4
E5
B2

MicroStar BGA is a trademark of Texas Instruments.

MicroStar BGA Packaging Reference Guide

B3

&&%")
#  ( !('

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration

Package Data Sheets

    
 '  ""  "" $ &
GHZ (S-PBGA-N151)

PLASTIC BALL GRID ARRAY

GHZ 151 TOP VIEW

DAISY CHAIN NET LIST

18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
INDEX MARK
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Electrical Characteristics

Thermal Characteristics

B1B2
C1E5
D1D3
E3E4
F1F4
F3G4
G3H4
H1H3
J3J4
K3K4
K1L4
L3M4
M1M3
N3N4
N5P3
P1P4

A B C D E F G H J K L MN P R T U V

R3R4
T1T3
U1V1
U2V2
P5V3
T4V4
R5T5
R6V6
R7T6
R8T7
T8V8
R9T9
R10T10
R11V10
R12T11
T12V12

R13T13
P13T14
R14V14
R15T15
T16V16
V17V18
U17U18
P14T18
R16R18
P15P16
N15N18
M15N16
L15M16
L16L18
K15K16
J15J16

H15J18
G15H16
G16G18
F15F16
E16F14
E15E18
D15D16
C16C18
A18B18
A17B17
A16E14
A15C15
C14D14
A13D13
C13D12
C12D11

A11C11
C10D10
C9D9
A9D8
C8D7
A7C7
C6D6
A5C5
C4D5
C3D4
A2A3

NC E6

GHZ 151
PIN# BALL#

$$# '

! & &%

Productization

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

B2
B1
C1
E5
D1
D3
E4
E3
F4
F1
F3
G4
G3
H4
H1
H3
J4
J3
K4
K3
K1
L4
L3
M4
M3
M1
N4
N3
N5
P3

PIN ASSIGNMENT NET LIST

PIN#

BALL#

PIN#

BALL#

PIN#

BALL#

PIN#

BALL#

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

P1
P4
R3
R4
T3
T1
U1
V1
U2
V2
V3
P5
V4
T4
R5
T5
R6
V6
T6
R7
T7
R8
V8
T8
R9
T9
R10
T10
V10
R11

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

T11
R12
T12
V12
R13
T13
P13
T14
V14
R14
T15
R15
T16
V16
V17
V18
U17
U18
T18
P14
R18
R16
P15
P16
N15
N18
N16
M15
M16
L15

91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

L18
L16
K15
K16
J15
J16
J18
H15
H16
G15
G16
G18
F15
F16
F14
E16
E18
E15
D16
D15
C16
C18
B18
A18
B17
A17
A16
E14
A15
C15

121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151

D14
C14
D13
A13
C13
D12
C12
D11
A11
C11
D10
C10
D9
C9
A9
D8
C8
D7
C7
A7
D6
C6
E6
C5
A5
D5
C4
D4
C3
A3
A2

MicroStar BGA is a trademark of Texas Instruments.

B4

MicroStar BGA Packaging Reference Guide

Package Data Sheets

    
 &  !!  !! #%
GGM (S-PBGA-N100)

PLASTIC BALL GRID ARRAY

GGM 100 TOP VIEW

DAISY CHAIN NET LIST

10
9
8
7
6
5
4
3
2
1
INDEX MARK
A B C D E F G H J

Electrical Characteristics
R ()
Min.
Mean
Max.

0.071
0.076
0.081

L (nH)

C (pF)

1.999
2.425
2.957

0.296
0.440
0.589

J2K2
J3H3
K3J4
K4H4
K5J5
H5G5
K6J6
H6G6
G7K7
J7H7
K8J8
K9K10

B2B1
C2C3
C1D2
D1D3
E1E2
E3E4
F1F2
F3F4
G4G1
G2G3
H1H2
J1K1

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration

Thermal Characteristics

J9J10
H9H8
H10G9
G10G8
F10F9
F8F7
E10E9
E8E7
D7D10
D9D8
C10C9
B10A10

B9A9
B8C8
A8B7
A7C7
A6B6
C6D6
A5B5
C5D5
D4A4
B4C4
A3B3
A2A1

NC E5,E6,F5,F6

Productization

PIN ASSIGNMENT NET LIST

PIN#

BALL#

PIN#

BALL#

PIN#

BALL#

PIN#

BALL#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

B2
B1
C2
C3
C1
D2
D1
D3
E1
E2
E3
E4
E5
F1
F2
F3
F4
G4
G1
G2
G3
H1
H2
J1
K1

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

J2
K2
J3
H3
K3
J4
K4
H4
K5
J5
H5
G5
F5
K6
J6
H6
G6
G7
K7
J7
H7
K8
J8
K9
K10

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

J9
J10
H9
H8
H10
G9
G10
G8
F10
F9
F8
F7
F6
E10
E9
E8
E7
D7
D10
D9
D8
C10
C9
B10
A10

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

B9
A9
B8
C8
A8
B7
A7
C7
A6
B6
C6
D6
E6
A5
B5
C5
D5
D4
A4
B4
C4
A3
B3
A2
A1

##"&

  % %$

GGM 100

MicroStar BGA is a trademark of Texas Instruments.

MicroStar BGA Packaging Reference Guide

B5

Package Data Sheets

 

 
 ' ""  "" $ &
GGV (S-PBGA-N64)

PLASTIC BALL GRID ARRAY

GGV 64 TOP VIEW

DAISY CHAIN NET LIST

8
7
6
5
4
3
2
1
INDEX MARK

A1B1
C2C1
D4D3
D1D2
E2E1
E3F1
F2F3
G1G2
H1H2
G3H3
E4F4
H4G4
G5H5
F5H6
G6F6
H7G7

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Electrical Characteristics

Min.
Mean
Max.

R ()

L (nH)

C (pF)

0.071
0.076
0.082

2.002
2.544
3.443

0.273
0.380
0.580

A B C D E F G H

Thermal Characteristics

GGV 64

PIN ASSIGNMENT NET LIST

PIN# BALL#

$$# ' 
! & &%

Productization

H8G8
F7F8
E5E6
E8E7
D7D8
D6C8
C7C6
B8B7
A8A7
B6A6
D5C5
A5B5
B4A4
C4A3
B3C3
A2B2

1 A1
2 B1
3 C2
4 C1
5 D4
6 D3
7 D1
8 D2
9 E2
10 E1
11 E3
12 F1
13 F2
14 F3
15 G1
16 G2

PIN# BALL# PIN# BALL# PIN# BALL#

17 H1
18 H2
19 G3
20 H3
21 E4
22 F4
23 H4
24 G4
25 G5
26 H5
27 F5
28 H6
29 G6
30 F6
31 H7
32 G7

33 H8
34 G8
35 F7
36 F8
37 E5
38 E6
39 E8
40 E7
41 D7
42 D8
43 D6
44 C8
45 C7
46 C6
47 B8
48 B7

49 A8
50 A7
51 B6
52 A6
53 D5
54 C5
55 A5
56 B5
57 B4
58 A4
59 C4
60 A3
61 B3
62 C3
63 A2
64 B2

MicroStar BGA is a trademark of Texas Instruments.

B6

MicroStar BGA Packaging Reference Guide

Package Data Sheets

    
 &  !!  !! #%
GGM (S-PBGA-N80)

PLASTIC BALL GRID ARRAY

GGM 80 TOP VIEW

DAISY CHAIN NET LIST

10
9
8
7
6
5
4
3
2
1
INDEX MARK

B2B1
C2C3
C1D2
D1D3
E1E2
E3F1
F2F3
G1G2
G3H1
H2J1

Electrical Characteristics

Min.
Mean
Max.

R ()

L (nH)

C (pF)

0.054
0.062
0.074

1.487
1.920
2.659

0.215
0.315
0.428

Thermal Characteristics

J2K2
J3H3
K3J4
K4H4
K5J5
H5K6
J6H6
K7J7
H7K8
J8K9

GGM 80

Productization

PIN# BALL#
1
B2
2
B1
3
C2
4
C3
5
C1
6
D2
7
D1
8
D3
9
E1
10
E2
11
E3
12
F1
13
F2
14
F3
15
G1
16
G2
17
G3
18
H1
19
H2
20
J1

J9J10
H9H8
H10G9
G10G8
F10F9
F8E10
E9E8
D10D9
D8C10
C9B10

B9A9
B8C8
A8B7
A7C7
A6B6
C6A5
B5C5
A4B4
C4A3
B3A2

PIN ASSIGNMENT NET LIST

PIN#
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

BALL#
J2
K2
J3
H3
K3
J4
K4
H4
K5
J5
H5
K6
J6
H6
K7
J7
H7
K8
J8
K9

PIN#
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

BALL# PIN#
J9
61
J10
62
H9
63
H8
64
H10
65
G9
66
G10
67
G8
68
F10
69
F9
70
F8
71
E10
72
E9
73
E8
74
D10
75
D9
76
D8
77
C10
78
C9
79
B10
80

BALL#
B9
A9
B8
C8
A8
B7
A7
C7
A6
B6
C6
A5
B5
C5
A4
B4
C4
A3
B3
A2

MicroStar BGA is a trademark of Texas Instruments.

MicroStar BGA Packaging Reference Guide

B7

##"&

  % %$

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration

A B C D E F G HJ K

Package Data Sheets

    
 &  !!  !! #%
GGF (S-PBGA-N100)

PLASTIC BALL GRID ARRAY

GGF 100 TOP VIEW

DAISY CHAIN NET LIST

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
INDEX MARK

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration

B1C2
R2P3
C1D2
R3P4
D1E2
R4P5
E1F2
R5P6
F1G2
R6P7
G1H2
R7P8
J1J2
R9P9
K1K2
R10P10
L1L2
R11P11
M1M2
R12P12
N1N2
R13P13
P1R1
R14R15
NC H1, R8, H15, A8

Electrical Characteristics

Min.
Mean
Max.

R ()

L (nH)

C (pF)

0.011
0.022
0.035

0.676
1.026
1.606

0.102
0.172
0.339

Thermal Characteristics

GGF 100

##"&

  % %$

Productization

A B C D E F G H J K L MN P R

P15N14
N15M14
M15L14
L15K14
K15J14
J15H14
G15G14
F15F14
E15E14
D15D14
C15C14
B15A15

A14B13
A13B12
A12B11
A11B10
A10B9
A9B8
A7B7
A6B6
A5B5
A4B4
A3B3
A2A1

PIN ASSIGNMENT NET LIST

PIN# BALL# PIN# BALL# PIN#

51
26
1
R2
B1
52
27
2
P3
C2
53
28
3
R3
C1
54
29
4
P4
D2
55
30
5
R4
D1
56
31
6
P5
E2
57
32
7
R5
E1
58
33
8
P6
F2
59
34
9
R6
F1
60
35
10
P7
G2
61
36
11
R7
G1
62
37
12
P8
H2
63
38
13
R8
H1
64
39
14
R9
J1
65
40
15
P9
J2
41
16
R10 66
K1
67
42
17
P10
K2
68
43
18
R11
L1
69
44
19
P11
L2
45
20
R12 70
M1
71
46
21
P12
M2
47
22
R13 72
N1
73
48
23
P13
N2
49
24
R14 74
P1
50
25
R15 75
R1

BALL# PIN#
P15 76
N14 77
N15 78
M14 79
M15 80
L14 81
L15 82
K14 83
K15 84
J14 85
J15 86
H14 87
H15 88
G15 89
G14 90
F15 91
F14 92
E15 93
E14 94
D15 95
D14 96
C15 97
C14 98
B15 99
A15 100

BALL#
A14
B13
A13
B12
A12
B11
A11
B10
A10
B9
A9
B8
A8
A7
B7
A6
B6
A5
B5
A4
B4
A3
B3
A2
A1

MicroStar BGA is a trademark of Texas Instruments.

B8

MicroStar BGA Packaging Reference Guide

Package Data Sheets

    
 % 
 
"$
GGT (S-PBGA-N100)

PLASTIC BALL GRID ARRAY

GGT 100 TOP VIEW

DAISY CHAIN NET LIST

11
10
9
8
7
6
5
4
3
2
1
INDEX MARK

B2
A1
L1
C2
B1
L2
D2
C1
L3
E2
D1
L4
F2
F3
J6
E1
F1
L5
G2
L7
G1
H1
G3
K7
H3
H2
K8
J1
H4
L9
J2
K9
J3
J4
K1
L10
NC E3,J5,H11,A8

Electrical Characteristics

Min.
Mean
Max.

L (nH)

C (pF)

0.072
0.077
0.086

2.200
2.636
3.633

0.254
0.398
0.582

Thermal Characteristics

GGT 100
PIN#

Productization

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

K2
K3
K4
K5
K6
L6
L8
J7
J8
H8
J9
H9

L11
K11
J11
G9
F9
G11
E11
E10
D10
D9
C10
C9

K10
J10
H10
G10
F10
F11
D11
E9
C11
D8
B11
C8

PIN ASSIGNMENT NET LIST

BALL# PIN#
A1
B2
B1
C2
C1
D2
E3
D1
E2
F3
F2
E1
F1
G1
G2
G3
H1
H2
H3
H4
J1
J2
J3
K1
J4

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

BALL# PIN#
L1
K2
L2
K3
L3
K4
J5
L4
K5
J6
K6
L5
L6
L7
L8
K7
J7
K8
J8
L9
H8
K9
J9
L10
H9

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

BALL# PIN#
L11
K10
K11
J10
J11
H10
H11
G9
G10
F9
F10
G11
F11
E11
D11
E10
E9
D10
C11
D9
D8
C10
B11
C9
C8

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

BALL#
A11
B10
A10
B9
A9
B8
A8
B7
A7
C7
C6
B6
A6
B5
A5
C5
D4
A4
B4
C4
A3
B3
C3
A2
D3

MicroStar BGA is a trademark of Texas Instruments.

MicroStar BGA Packaging Reference Guide

B9

""!%

 $ $#

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
R ()

A B C D E F G HJ K L

Package Data Sheets

    
 '  "" 
"" $ &
GGU (S-PBGA-N144)

PLASTIC BALL GRID ARRAY

GGU 144 TOP VIEW

DAISY CHAIN NET LIST

13
12
11
10
9
8
7
6
5
4
3
2
1
INDEX MARK

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Electrical Characteristics
R ()
Min.
Mean
Max.

0.052
0.055
0.062

L (nH)

C (pF)

1.438
1.958
3.095

0.215
0.305
0.563

Thermal Characteristics

A1B1
C2C1
D4D3
D2D1
E4E3
E2E1
F4F3
F2F1
G2G1
G3G4
H1H2
H3H4
J1J2
J3J4
K1K2
K3L1
L2L3
M1M2

A B C D E F G H J K L MN

N1N2
M3N3
K4L4
M4N4
K5L5
M5N5
K6L6
M6N6
M7N7
L7K7
N8M8
L8K8
N9M9
L9K9
N10M10
L10N11
M11L11
N12M12

GGU 144

$$# ' 
! & &%

Productization

PIN# BALL#
1
A1
2
B1
3
C2
4
C1
5
D4
6
D3
7
D2
8
D1
9
E4
10
E3
11
E2
12
E1
13
F4
14
F3
15
F2
16
F1
17 G2
18 G1
19 G3
20 G4
21 H1
22 H2
23 H3
24 H4
25
J1
26
J2
27
J3
28
J4
29
K1
30
K2
31
K3
32
L1
33
L2
34
L3
35 M1
36 M2

N13M13
L12L13
K10K11
K12K13
J10J11
J12J13
H10H11
H12H13
G12G13
G11G10
F13F12
F11F10
E13E12
E11E10
D13D12
D11C13
C12C11
B13B12

A13A12
B11A11
D10C10
B10A10
D9C9
B9A9
D8C8
B8A8
B7A7
C7D7
A6B6
C6D6
A5B5
C5D5
A4B4
C4A3
B3C3
A2B2

PIN ASSIGNMENT NET LIST

PIN# BALL#
37 N1
38 N2
39 M3
40 N3
41 K4
42 L4
43 M4
44 N4
45 K5
46 L5
47 M5
48 N5
49 K6
50 L6
51 M6
52 N6
53 M7
54 N7
55 L7
56 K7
57 N8
58 M8
59 L8
60 K8
61 N9
62 M9
63 L9
64 K9
65 N10
66 M10
67 L10
68 N11
69 M11
70 L11
71 N12
72 M12

PIN#
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108

BALL#
N13
M13
L12
L13
K10
K11
K12
K13
J10
J11
J12
J13
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
F10
E13
E12
E11
E10
D13
D12
D11
C13
C12
C11
B13
B12

PIN# BALL#
109 A13
110 A12
111 B11
112 A11
113 D10
114 C10
115 B10
116 A10
117 D9
118 C9
119 B9
120 A9
121 D8
122 C8
123 B8
124 A8
125 B7
126 A7
127 C7
128 D7
129 A6
130 B6
131 C6
132 D6
133 A5
134 B5
135 C5
136 D5
137 A4
138 B4
139 C4
140 A3
141 B3
142 C3
143 A2
144 B2

MicroStar BGA is a trademark of Texas Instruments.

B10

MicroStar BGA Packaging Reference Guide

Package Data Sheets

   
 )  $$ 
$$ &"(!
GHH (S-PBGA-N179)

PLASTIC BALL GRID ARRAY

GHH 179 TOP VIEW

DAISY CHAIN NET LIST

14
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G HJ K L MN P

INDEX MARK

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Electrical Characteristics

B2B1

H3H1

N2P2

M8P8

N13N14 G12G14 B13A13 C7A7

C3C2

H2H4

M3N3

N8L8

M12M13 G13G11 C12B12 B7D7

C1D4

H5J1

P3L4

K8P9

M14L11 G10F14 A12D11 E7A6

D3D2

J2J3

M4N4

N9M9

L12L13

D1E4

J4K1

P4L5

L9P10

L14K11

E3E2

K2K3

M5N5

E1F4

J5L1

P5L6

F3F2

L2L3

M6N6

F1F5

K4M1

P6K6

G5G2

M2K5

K7N7

G1G3

N1P1

P7M7

F13F12

C11B11

B6C6

A11D10

D6A5
N10M10 K12K13 E13E12 C10B10 B5C5
K9P11
K14J11 F10D14 A10D9 E6A4
N11M11 J12J13 D13D12 C9B9
B4C4
L10P12 J14J10 E11C14 A9E9
D5A3
F11E14

N12K10 H10H13 C13E10 E8B8

P13P14 H14H12 B14A14 A8C8

B3E5
F6A2

NC D8,G4,H11,L7,A2

Thermal Characteristics

GHH 179

PIN ASSIGNMENT NET LIST

Productization

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

B2
B1
C3
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
F5
G5
G2
G1
G3
G4
H3
H1
H2
H4
H5
J1
J2

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

J3
J4
K1
K2
K3
J5
L1
L2
L3
K4
M1
M2
K5
N1
P1
N2
P2
M3
N3
P3
L4
M4
N4
P4
L5
M5
N5
P5
L6
M6

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

N6
P6
K6
K7
N7
P7
M7
L7
M8
P8
N8
L8
K8
P9
N9
M9
L9
P10
N10
M10
K9
P11
N11
M11
L10
P12
N12
K10
P13
P14

91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

N13
N14
M12
M13
M14
L11
L12
L13
L14
K11
K12
K13
K14
J11
J12
J13
J14
J10
H10
H13
H14
H12
H11
G12
G14
G13
G11
G10
F14
F13

121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150

F12
F11
E14
E13
E12
F10
D14
D13
D12
E11
C14
C13
E10
B14
A14
B13
A13
C12
B12
A12
D11
C11
B11
A11
D10
C10
B10
A10
D9
C9

151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
(179
180

B9
A9
E9
E8
B8
A8
C8
D8
C7
A7
B7
D7
E7
A6
B6
C6
D6
A5
B5
C5
E6
A4
B4
C4
D5
A3
B3
E5
F6 (ID ball))
A2

MicroStar BGA is a trademark of Texas Instruments.

MicroStar BGA Packaging Reference Guide

B11

&&%")
#  ( !('

PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL#

Package Data Sheets


  
 )  $$  $$ &"(!
GGW (S-PBGA-N176)

PLASTIC BALL GRID ARRAY

GGW 176 TOP VIEW

DAISY CHAIN NET LIST

17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
INDEX MARK

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Electrical Characteristics

Min.
Mean
Max.

R ()

L (nH)

C (pF)

0.075
0.083
0.099

1.595
2.417
3.284

0.204
0.298
0.425

Thermal Characteristics

B1C2
C1D3
D2D1
E3E2
E1F3
F2F1
G4G3
G2G1
H1H4
H3H2
J1J4
J3J2
K1K2
K3K4
L1L2
L3L4
M1M2
M3N1
N2N3
P1P2
P3R1
R2T1

A B C D E F G H J K L MN P R T U

U2T3
U3R4
T4U4
R5T5
U5R6
T6U6
P7R7
T7U7
U8P8
R8T8
U9P9
R9T9
U10T10
R10P10
U11T11
R11P11
U12T12
R12U13
T13R13
U14T14
R14U15
T15U16

GGW 176

&&%")
#  ( !('

Productization

MicroStar BGA is a trademark of Texas Instruments.

B12

T17R16
R17P15
P16P17
N15N16
N17M15
M16M17
L14L15
L16L17
K17K14
K15K16
J17J14
J15J16
H17H16
H15H14
G17G16
G15G14
F17F16
F15E17
E16E15
D17D16
D15C17
C16B17

A16B15
A15C14
B14A14
C13B13
A13C12
B12A12
D11C11
B11A11
A10D10
C10B10
A9D9
C9B9
A8B8
C8D8
A7B7
C7D7
A6B6
C6A5
B5C5
A4B4
C4A3
B3A2

PIN ASSIGNMENT NET LIST

PIN# BALL# PIN#BALL#

1
36 N1
B1
2 C2
37 N2
3 C1
38 N3
4 D3
39 P1
5 D2
40 P2
6 D1
41 P3
7
42 R1
E3
8
43 R2
E2
9
44 T1
E1
10 F3
45 U2
11 F2
46 T3
12 F1
47 U3
13 G4
48 R4
14 G3
49 T4
15 G2
50 U4
16 G1
51 R5
17 H1
52 T5
18 H4
53 U5
19 H3
54 R6
20 H2
55 T6
21 J1
56 U6
22 J4
57 P7
23 J3
58 R7
24 J2
59 T7
25 K1
60 U7
26 K2
61 U8
27 K4
62 P8
28 K3
63 R8
29 L1
64 T8
30 L2
65 U9
31 L3
66 P9
32 L4
67 R9
33 M1
68 T9
34 M2
69 U10
35 M3
70 T10

PIN#
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105

BALL# PIN# BALL# PIN#

P10
106 K14
141
R10
107 K15
142
U11
108 K16
143
J17
T11
109
144
J14
R11
110
145
J15
P11
111
146
J16
U12
112
147
T12
113 H17 148
R12
114 H16 149
U13
115 H14 150
T13
116 H15 151
R13
117 G17 152
U14
118 G16 153
T14
119 G15 154
R14
120 G14 155
U15
121 F17
156
T15
122 F16
157
U16
123 F15
158
T17
124 E17
159
R16
125 E16
160
R17
126 E15
161
P15
127 D17 162
P16
128 D16 163
P17
129 D15 164
N15
130 C17 165
N16
131 C16 166
N17
132 B17
167
M15
133 A16
168
M16
134 B15
169
M17
135 A15
170
L14
136 C14 171
L15
137 B14
172
L16
138 A14
173
L17
139 C13 174
K17
140 B13
175
176

BALL#
A13
C12
B12
A12
D11
C11
B11
A11
A10
D10
C10
B10
A9
D9
C9
B9
A8
B8
D8
C8
A7
B7
C7
D7
A6
B6
C6
A5
B5
C5
A4
B4
C4
A3
B3
A2

MicroStar BGA Packaging Reference Guide

Package Data Sheets


   
 (  ## 
## %!' 
GGW (S-PBGA-N208)

PLASTIC BALL GRID ARRAY

GGW 208 TOP VIEW

DAISY CHAIN NET LIST

17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
INDEX MARK

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Electrical Characteristics
R ()
Min.
Mean
Max.

0.070
0.075
0.079

L (nH)
1.824
2.266
3.416

C (pF)
0.217
0.278
0.433

Thermal Characteristics

A B C D E F G H J K L MN P R T U

B2C2

J1K4

T2T3

U9P10

T16R16

J17H14

B16B15

A9D8

B1C1

K3K2

U2U3

R10T10

T17R17

H15H16 A16A15

C8B8

D3D2

K1L4

R4T4

U10P11

P15P16

H17G14 C14B14

A8D7

D1E4

L3L2

U4P5

R11T11

P17N14 G15G16 A14D13

C7B7

E3E2

L1M4

R5T5

U11P12

N15N16 G17F14

C13B13

A7D6

E1F4

M3M2

U5P6

R12T12

N17M14 F15F16

A13D12

C6B6

F3F2

M1N4

R6T6

U12P13

M15M16 F17E14

C12B12

A6D5

F1G4

N3N2

U6P7

R13T13

M17L14 E15E16

A12D11

C5B5

G3G2

N1P4

R7T7

U13P14

L15L16

E17D14

C11B11

A5D4

G1H4

P1P3

U7P8

U14R14

L17K14

D17D15 A11D10

A4C4

H3H2

P2R1

R8T8

T14U15

K15K16

D16C17 C10B10

B4A3

H1J4

R2T1

U8P9

T15U16

K17J14

C16B17

A10D9

B3A2

J3J2

R3U1

R9T9

R15U17

J15J16

C15A17

C9B9

C3A1

GGW 208

PIN ASSIGNMENT NET LIST

Productization

B2

27

J1

53

T2

79

U9

105

T16

131

J17

157

B16

183

A9

C2

28

K4

54

T3

80

P10

106

R16

132

H14

158

B15

184

D8

B1

29

K3

55

U2

81

R10

107

T17

133

H15

159

A16

185

C8

C1

30

K2

56

U3

82

T10

108

R17

134

H16

160

A15

186

B8

D3

31

K1

57

R4

83

U10

109

P15

135

H17

161

C14

187

A8

D2

32

L4

58

T4

84

P11

110

P16

136

G14

162

B14

188

D7

D1

33

L3

59

U4

85

R11

111

P17

137

G15

163

A14

189

C7

E4

34

L2

60

P5

86

T11

112

N14

138

G16

164

D13

190

B7

E3

35

L1

61

R5

87

U11

113

N15

139

G17

165

C13

191

A7

10

E2

36

M4

62

T5

88

P12

114

N16

140

F14

166

B13

192

D6

11

E1

37

M3

63

U5

89

R12

115

N17

141

F15

167

A13

193

C6

12

F4

38

M2

64

P6

90

T12

116

M14

142

F16

168

D12

194

B6

13

F3

39

M1

65

R6

91

U12

117

M15

143

F17

169

C12

195

A6

14

F2

40

N4

66

T6

92

P13

118

M16

144

E14

170

B12

196

D5

15

F1

41

N3

67

U6

93

R13

119

M17

145

E15

171

A12

197

C5

16

G4

42

N2

68

P7

94

T13

120

L14

146

E16

172

D11

198

B5

17

G3

43

N1

69

R7

95

U13

121

L15

147

E17

173

C11

199

A5

18

G2

44

P4

70

T7

96

P14

122

L16

148

D14

174

B11

200

D4

19

G1

45

P1

71

U7

97

U14

123

L17

149

D17

175

A11

201

A4

20

H4

46

P3

72

P8

98

R14

124

K14

150

D15

176

D10

202

C4

21

H3

47

P2

73

R8

99

T14

125

K15

151

D16

177

C10

203

B4

22

H2

48

R1

74

T8

100

U15

126

K16

152

C17

178

B10

204

A3

23

H1

49

R2

75

U8

101

T15

127

K17

153

C16

179

A10

205

B3

24

J4

50

T1

76

P9

102

U16

128

J14

154

B17

180

D9

206

A2

25

J3

51

R3

77

R9

103

R15

129

J15

155

C15

181

C9

207

C3

26

J2

52

U1

78

T9

104

U17

130

J16

156

A17

182

B9

208

A1

MicroStar BGA is a trademark of Texas Instruments.

MicroStar BGA Packaging Reference Guide

B13

%%$!( 
" '  '&

PIN# BALL# PIN# BALL#PIN# BALL#PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN#BALL#

Package Data Sheets

   

) 
$$  $$ &"(!
GGW (S-PBGA-N240)

PLASTIC BALL GRID ARRAY

GGW 240 TOP VIEW

DAISY CHAIN NET LIST

17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

INDEX MARK

A B C D E F GH J K L MNP R T U

B2C2

J2J1

T2T3

T9U9

T16R16

J16J17

B16B15 B9A9

B1C1

K5K4

U2U3

N10P10

T17R17

H13H14

A16A15 E8D8

D3D2

K3K2

R4T4

R10T10

P15P16

H15H16

C14B14 C8B8

D1E5

K1L5

U4N5

U10N11

P17N13 H17G13

A14E13 A8E7

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration

E4E3

L4L3

P5R5

P11R11

N14N15 G14G15

D13C13 D7C7

E2E1

L2L1

T5U5

T11U11

N16N17 G16G17

B13A13 B7A7

F5F4

M5M4

N6P6

N12P12

M13M14 F13F14

E12D12 E6D6

Electrical Characteristics

F3F2

M3M2

R6T6

R12T12

M15M16 F15F16

C12B12 C6B6

F1G5

M1N4

U6N7

U12P13

M17L13 F17E14

A12E11 A6D5

G4G3 N3N2

P7R7

R13T13

L14L15

E15E16

D11C11 C5B5

G2G1 N1P4

T7U7

U13P14

L16L17

E17D14

B11A11

H5H4

N8P8

U14R14

K13K14

D17D15

E10D10 A4C4

Thermal Characteristics

P1P3

A5D4

H3H2

P2R1

R8T8

T14U15

K15K16

D16C17

C10B10 B4A3

H1J5

R2T1

U8N9

T15U16

K17J13

C16B17

A10E9

B3A2

J4J3

R3U1

P9R9

R15U17

J14J15

C15A17

D9C9

C3A1

GGW 240

PIN ASSIGNMENT NET LIST

PIN#BALL# PIN#BALL# PIN#BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL#

&&%")
#  ( !('

Productization

B2

31

J2

61

T2

91

T9

121

T16

151

J16

181

B16

211

B9

C2

32

J1

62

T3

92

U9

122 R16

152

J17

182

B15

212

A9

B1

33

K5

63

U2

93

N10

123

T17

153

H13

183

A16

213

E8

C1

34

K4

64

U3

94

P10

124 R17

154

H14

184

A15

214

D8

D3

35

K3

65

R4

95

R10

125

P15

155

H15

185

C14

215

C8

D2

36

K2

66

T4

96

T10

126

P16

156

H16

186

B14

216

B8

D1

37

K1

67

U4

97

U10

127

P17

157

H17

187

A14

217

A8

E5

38

L5

68

N5

98

N11

128 N13

158

G13

188

E13

218

E7

E4

39

L4

69

P5

99

P11

129 N14

159

G14

189

D13

219

D7

10

E3

40

L3

70

R5

100

R11

130 N15

160

G15

190

C13

220

C7

11

E2

41

L2

71

T5

101

T11

131 N16

161

G16

191

B13

221

B7

12

E1

42

L1

72

U5

102

U11

132 N17

162

G17

192

A13

222

A7

13

F5

43

M5

73

N6

103

N12

133 M13

163

F13

193

E12

223

E6

14

F4

44

M4

74

P6

104

P12

134 M14

164

F14

194

D12

224

D6

15

F3

45

M3

75

R6

105

R12

135 M15

165

F15

195

C12

225

C6

16

F2

46

M2

76

T6

106

T12

136 M16

166

F16

196

B12

226

B6

17

F1

47

M1

77

U6

107

U12

137 M17

167

F17

197

A12

227

A6

18

G5

48

N4

78

N7

108

P13

138

L13

168

E14

198

E11

228

D5

19

G4

49

N3

79

P7

109

R13

139

L14

169

E15

199

D11

229

C5

20

G3

50

N2

80

R7

110

T13

140

L15

170

E16

200

C11

230

B5

21

G2

51

N1

81

T7

111

U13

141

L16

171

E17

201

B11

231

A5

22

G1

52

P4

82

U7

112

P14

142

L17

172

D14

202

A11

232

D4

23

H5

53

P1

83

N8

113

U14

143

K13

173

D17

203

E10

233

A4

24

H4

54

P3

84

P8

114

R14

144

K14

174

D15

204

D10

234

C4

25

H3

55

P2

85

R8

115

T14

145

K15

175

D16

205

C10

235

B4

26

H2

56

R1

86

T8

116

U15

146

K16

176

C17

206

B10

236

A3

27

H1

57

R2

87

U8

117

T15

147

K17

177

C16

207

A10

237

B3

28

J5

58

T1

88

N9

118

U16

148

J13

178

B17

208

E9

238

A2

29

J4

59

R3

89

P9

119

R15

149

J14

179

C15

209

D9

239

C3

30

J3

60

U1

90

R9

120

U17

150

J15

180

A17

210

C9

240

A1

MicroStar BGA is a trademark of Texas Instruments.

B14

MicroStar BGA Packaging Reference Guide

Package Data Sheets


   
 (  ##  ## %!' 
GHC (S-PBGA-N196)

PLASTIC BALL GRID ARRAY

GHC 196 TOP VIEW

DAISY CHAIN NET LIST

14
13
12
11
10
9
8
7
6
5
4
3
2
1
INDEX MARK

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Electrical Characteristics
R ()
Min.
Mean
Max.

0.078
0.092
0.123

L (nH)
2.174
3.288
6.418

C (pF)
0.256
0.470
1.071

Thermal Characteristics

A B

C D

E F

G H J

M N

B2

C2

H5

J4

N5 P5

M10

P10

J14

J11

D13

B14

E8

C7

A1

D2

J1

J2

M5 L5

N10

P11

J10

H11 C13

C12

A7

B7

B1

D3

J3

J5

K5

M6

L11

P12

H13

H14 B13

B12

D7

E7

C1

D1

K4

K3

N6 P6

M11

N11

H12

H10 A14

B11

D6

A6

E2

E1

K1

K2

L6

K6

P13

N12

G12

G14 A13

C11

B6

C6

E3

E4

L1

L4

L7

N7

M12

N13

G13

G11 A12

A11

E6

D5

F3

F2

M1

L3

P7

M7

M13

P14

G10

F11 B10

A10

C5

A5

F1

F4

L2

N1

K7

M8

L13

N14

F14

F13 C10

D10

B5

A4

F5

G4

M2

M3 P8

N8

L12

M14

F12

F10 E10

C9

D4

A3

G2

G1

N2

N3

L8

K8

L14

K13

E11

E12 B9

A9

C4

B4

G3

G5

P1

N4

L9

P9

K14

K12

E14

E13 D9

E9

A2

B3

H3

H1

P2

M4 N9 M9

K11

K10

D14

D11 D8

B8

H2

H4

P3

P4

K9

J12

J13

C14

D12 A8

C8

L10

Internal connection E5,F6,F7,F8,F9,G6,G7,G8,G9,H6,H7,H8,H9,J6,J7,J8,J9

NC C3

GHC 196

PIN ASSIGNMENT NET LIST

Productization

B2

27

H5

53

N5

79

M10

105

J14

131

D13

157

E8

C2

28

J4

54

P5

80

P10

106

J11

132

B14

158

C7

A1

29

J1

55

M5

81

N10

107

J10

133

C13

159

A7

D2

30

J2

56

L5

82

P11

108

H11

134

C12

160

B7

B1

31

57

K5

83

H13

135

B13

161

D7

D3

32

58

M6

84

L11
P12

109

J3
J5

110

H14

136

B12

162

E7

33

K4

59

N6

85

M11

111

H12

137

A14

163

D6

C1
D1

34

K3

60

P6

86

N11

112

H10

138

B11

164

A6

E2

35

K1

61

L6

87

P13

113

G12

139

165

B6

10

E1

36

K2

62

K6

88

N12

114

G14

140

A13
C11

166

C6

141

A12

167

11

E3

37

L1

63

E4

38

L4

64

L7
N7

89

12

116

142

A11

168

E6
D5

13

F3

39

M1

65

P7

91

N13
M13

G13
G11

117

G10

143

B10

169

C5

14

F2

40

L3

66

M7

92

P14

118

F11

144

A10

170

A5

15

41

L2

67

K7

93

L13

119

C10

171

B5

42

N1

68

M8

94

N14

120

F14
F13

145

16

F1
F4

146

D10

172

A4

17

F5

43

M2

69

P8

95

L12

121

F12

147

E10

173

D4

18

G4

44

M3

70

N8

96

M14

122

F10

148

C9

174

A3

19

G2

45

N2

71

L8

97

L14

123

149

B9

175

C4

20

G1

46

N3

72

K8

98

K13

124

E11
E12

150

A9

176

B4

21

G3

47

P1

73

L9

99

K14

125

E14

151

D9

177

A2

22

G5

48

N4

74

P9

100

K12

126

E13

152

E9

178

B3

P2

75

N9

101

K11

127

D14

153

D8

179

C3

24

H3
H1

49
50

M4

76

M9

102

K10

128

D11

154

B8

25

H2

51

P3

77

103

J12

129

C14

155

A8

26

H4

52

P4

78

K9
L10

104

J13

130

D12

156

C8

23

90

M12

115

Internal connection E5,F6,F7,F8,F9,G6,G7,G8,G9,H6,H7,H8,H9,J6,J7,J8,J9

MicroStar BGA is a trademark of Texas Instruments.

MicroStar BGA Packaging Reference Guide

B15

%%$!( 
" '  '&

PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL#

Package Data Sheets

     

* 
%%  %% '#)"
GHK (S-PBGA-N257)

PLASTIC BALL GRID ARRAY

GHK 257 TOP VIEW

DAISY CHAIN NET LIST

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
INDEX MARK

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Electrical Characteristics

Thermal Characteristics

A B C D E F G H J K L M N P R T U V W

B2B1 K5K6 V2W2

R10P10

K15K14

B18A18

D3C2 L1L2

U4V3

W11V11 T17U18

J19J18

C16B17 A9B9

C1D2 L3L6

W3V4

U11P11

V18V19

E10F10
C9F9

U19T18

J17J14

A17B16

D1E3 L5M1 W4U5

R11W12 T19R17

J15H19

A16C15 E9A8

F5G6 M2M3 R6P7

V12U12

P15N14

H18H17

E14F13

B8C8

E2E1 M6M5 V5W5

P12R12

R18R19

H14H15

B15A15

F8E8

F3F2

W13V13 P17P18

G19G18

C14B14 A7B7

G5F1 N3N6 R7W6

U13P13

G17G14

E13A14

C7F7

H6G3 P1P2 P8U7

W14V14 M14N17 F19F18

F12C13

A6B6

G2G1 N5P3 V7W7

R13U14

B13A13

E7C6

H5H3 R1P6 R8U8

W15P14 M15M17 E19F14

E12C12 A5F6

H2H1 R2P5 V8W8

V15R14

N1N2 U6V6

N15P19
N18N19

G15F17

B12A12

B5E6

J1J2

R3T1 W9V9

U15W16 L19L18

E17D19

A11B11

C5A4

J3J5

T2U1 U9R9

V16W17 L17L15

D18C19

C11E11

B4A3

J6K1

T3U2 P9W10 U16V17

L14K19

D17C18

F11A10

C4B3

K2K3 V1U3 V10U10 W18U17 K18K17

B19C17

B10C10 A2C3

M18M19 E18F15

NCE5

GHK 257

PIN ASSIGNMENT NET LIST

PIN#BALL# PIN#BALL# PIN#BALL# PIN#BALL# PIN#BALL#

'' &#* 
$! ) " )(

Productization

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

B2
B1
D3
C2
C1
D2
D1
E3
F5
G6
E2
E1
F3
F2
G5
F1
H6
G3
G2
G1
H5
H3
H2
H1
J1
J2
J3
J5
J6
K1
K2
K3

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

K5
K6
L1
L2
L3
L6
L5
M1
M2
M3
M6
M5
N1
N2
N3
N6
P1
P2
N5
P3
R1
P6
R2
P5
R3
T1
T2
U1
T3
U2
V1
U3

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

V2
W2
U4
V3
W3
V4
W4
U5
R6
P7
V5
W5
U6
V6
R7
W6
P8
U7
V7
W7
R8
U8
V8
W8
W9
V9
U9
R9
P9
W10
V10
U10

97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

R10
P10
W11
V11
U11
P11
R11
W12
V12
U12
P12
R12
W13
V13
U13
P13
W14
V14
R13
U14
W15
P14
V15
R14
U15
W16
V16
W17
U16
V17
W18
U17

129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160

V18
V19
T17
U18
U19
T18
T19
R17
P15
N14
R18
R19
P17
P18
N15
P19
M14
N17
N18
N19
M15
M17
M18
M19
L19
L18
L17
L15
L14
K19
K18
K17

PIN#BALL# PIN#BALL# PIN#BALL#

161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192

K15
K14
J19
J18
J17
J14
J15
H19
H18
H17
H14
H15
G19
G18
G17
G14
F19
F18
G15
F17
E19
F14
E18
F15
E17
D19
D18
C19
D17
C18
B19
C17

193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224

B18
A18
C16
B17
A17
B16
A16
C15
E14
F13
B15
A15
C14
B14
E13
A14
F12
C13
B13
A13
E12
C12
B12
A12
A11
B11
C11
E11
F11
A10
B10
C10

225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256

E10
F10
A9
B9
C9
F9
E9
A8
B8
C8
F8
E8
A7
B7
C7
F7
A6
B6
E7
C6
A5
F6
B5
E6
C5
A4
B4
A3
C4
B3
A2
C3

ID BALL E5

MicroStar BGA is a trademark of Texas Instruments.

B16

MicroStar BGA Packaging Reference Guide

Package Data Sheets

     

* 
%%  %% '#)"
GJG (S-PBGA-N257)

PLASTIC BALL GRID ARRAY

GJG 257 TOP VIEW

DAISY CHAIN NET LIST

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

INDEX MARK

B2B1

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Electrical Characteristics

C1C2
D1D2
E4E5
E1E2
F5F4
F1F2
G6G5
G2G1
G4H6
H1H2
H4H5
J4J1
J2J5
J6K6
K1K2

K4K5
L6L1
L2L4
L5M6
M1M2
M4M5
N7N1
N2N4
N5N6
P1P2
P4P5
P6R1
R2R4
T1T2
U1T4
U2V1

A B C D E F G H J K L MN P R T U V W

V2W2 T10R10
W3V3 P11W11
W4V4 V11T11
R11P12
T5R5
W5V5 W12V12
T12R12
R6T6
W6V6 N13W13
V13T13
P7R7
V7W7 R13P13
W14V14
T7P8
W8V8 T14R14
P14W15
T8R8
T9W9 V15T15
W16V16
V9R9
P9P10 W17T16
W10V10 V17W18

V18V19
U19U18
T19T18
R16R15
R19R18
P15P16
P19P18
N14N15
N18N19
N16M14
M19M18
M16M15
L16L19
L18L15
L14K14
K19K18

K16K15

B18A18 D10E10

J14J19
J18J16
J15H14
H19H18
H16H15
G13G19
G18G16
G15G14
F19F18
F16F15
F14E19
E18E16
D19D18
C19D16
C18B19

A17B17
A16B16
D15E15
A15B15
E14D14
A14B14
F13E13
B13A13
D13F12
A12B12
D12E12
D11A11
B11E11
F11F10
A10B10

F9A9
B9D9
E9F8
A8B8
D8E8
G7A7
B7D7
E7F7
A6B6
D6E6
F6A5
B5D5
A4B4
A3D4
B3A2

ID BALLC3

Thermal Characteristics
GJG 257

PIN ASSIGNMENT NET LIST

Productization

B2

33

K4

65 V2

97 T10

129 V18

161 K16

193 B18

225 D10

B1

34

K5

66 W2

98 R10

130 V19

162 K15

194 A18

226 E10

C1

35

L6

67 W3

99 P11

131 U19

163 J14

195 A17

227 F9

C2

36

L1

68 V3

100 W11

132 U18

164 J19

196 B17

228 A9

69 W4

101 V11

133 T19

165 J18

197 A16

229 B9

D1

37

L2

D2

38

L4

70 V4

102 T11

134 T18

166 J16

198 B16

230 D9

E4

39

L5

71 T5

103 R11

135 R16

167 J15

199 D15

231 E9

E5

40

M6

72 R5

104 P12

136 R15

168 H14

200 E15

232 F8

E1

41

M1

73 W5

105 W12

137 R19

169 H19

201 A15

233 A8

10 E2

42

M2

74 V5

106 V12

138 R18

170 H18

202 B15

234 B8

11 F5

43

M4

75 R6

107 T12

139 P15

171 H16

203 E14

235 D8

12 F4

44

M5

76 T6

108 R12

140 P16

172 H15

204 D14

236 E8

13 F1

45

N7

77 W6

109 N13

141 P19

173 G13

205 A14

237 G7

14 F2

46

N1

78 V6

110 W13

142 P18

174 G19

206 B14

238 A7

15 G6

47

N2

79 P7

111 V13

143 N14

175 G18

207 F13

239 B7

16 G5

48

N4

80 R7

112 T13

144 N15

176 G16

208 E13

240 D7

17 G2

49

N5

81 V7

145 N18

177 G15

209 B13

241 E7

18 G1

50

N6

82 W7

113 R13
114 P13

146 N19

178 G14

210 A13

242 F7

19 G4

51

P1

83 T7

115 W14

147 N16

179 F19

211 D13

243 A6

20 H6

52

P2

84 P8

116 V14

148 M14

180 F18

212 F12

244 B6

21 H1

53

P4

85 W8

117 T14

149 M19

181 F16

213 A12

245 D6

22 H2

54

P5

86 V8

118 R14

150 M18

182 F15

214 B12

246 E6

23 H4

55

P6

87 T8

119 P14

151 M16

183 F14

215 D12

247 F6

24 H5

56

R1

88 R8

120 W15

152 M15

184 E19

216 E12

248 A5

25 J4

57

R2

89 T9

153 L16

185 E18

217 D11

249 B5

26 J1

58

R4

90 W9

121 V15
122 T15

154 L19

186 E16

218 A11

250 D5

27 J2

59

T1

91 V9

123 W16

155 L18

187 D19

219 B11

251 A4

28 J5

60

T2

92 R9

124 V16

156 L15

188 D18

220 E11

252 B4

29 J6

61

U1

93 P9

125 W17

157 L14

189 C19

221 F11

253 A3

30 K6

62

T4

94 P10

126 T16

158 K14

190 D16

222 F10

254 D4

31 K1

63

U2

95 W10

127 V17

159 K19

191 C18

223 A10

255 B3

32 K2

64

V1

96 V10

128 W18

160 K18

192 B19

224 B10

256 A2

1PIN MARK C3

MicroStar BGA is a trademark of Texas Instruments.

MicroStar BGA Packaging Reference Guide

B17

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PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN#BALL# PIN#BALL#

Package Data Sheets

Notes

B18

MicroStar BGA Packaging Reference Guide