NC State University
ECE Department
ECE 746
VLSI Systems Design
Page 1 of 5
Fall 2005
Final Exam
(December 6, 2005)
Name:
Problem
Points
Score
1
30
2
30
3
25
4
15
Honor Pledge: I have not received any information about this test, nor will I
reveal any information about this test to any person until 5:00pm, Friday,
December 9th.
Signature:
TIPS:
Show all steps needed to arrive at an answer for full credit.
Budget your time wisely.
The problems are intended to require only a few short steps to complete.
If you find yourself writing a page of text, you are probably on the wrong
track.
NC State University
ECE Department
ECE 746
VLSI Systems Design
Page 2 of 5
Fall 2005
(30 points) Problem 1 (Sequential Circuits)
In the circuit below, assume that the rising edge of the clock arrives at time zero for both R1 and
R3 (tclk1=tclk3=0).
Cell
NAND
NOR
XOR
Flip-Flop (clk-q delay)
(setup time)
(hold time)
Delay (ps)
30
20
40
20
10
10
R3
tclk3
R1
tclk1
R2
tclk2
a) (15 points) What is the latest that the rising edge of the clock may arrive at R2 in order for the
circuit to work properly as drawn? Give an equation with symbols, and also plug in the values
and simplify the equation for full credit.
b) (15 points) Assume now that the rising edge of the clock arrives at R2 at time 30 ps. What is
the minimum clock-period for this circuit?
NC State University
ECE Department
ECE 746
VLSI Systems Design
Page 3 of 5
Fall 2005
(30 points) Problem 2 (Arithmetic Circuits)
For the carry-propagation circuit below, assume the following delays for each block:
Delay Variable
Delay Value
tsetup
3
tcarry
2
tAND
3
tMUX
1
a) (5 points) What kind of adder is represented by this circuit?
b) (10 points) What is the critical-path delay for this circuit? Give an equation with symbols and
compute the numerical value for full credit.
c) (15 points) Consider the case when the A inputs are all low (0) and the B inputs are all high
(1). (Assume also that the Ci,0 input is 0). Then input A changes in one of two ways, as shown
below. Compute the delay for each case, giving both an equation and a numerical answer.
Which one is greater? (Note that the LSB is on the left in the figure, but the right in the table)
A input
Initial Value
Next Value
Case 1
Case 2
MSB
LSB
0000 0000
0000 1000
0010 0000
NC State University
ECE Department
ECE 746
VLSI Systems Design
Page 4 of 5
Fall 2005
(25 points) Problem 3 (Memory)
The circuit diagram for a 6T-SRAM cell in a 100nm technology is given below. VDD is 1 V.
During the Read Operation, the Bit-Lines are precharged to 0.8 V, and during the Write
operation, the Bit-Lines are driven to 0.8V and 0V. Assume that the minimum transistor size is
W/L = 150nm/100nm and that all transistors are minimum-sized.
NMOS
PMOS
VT0 (V)
0.2
-0.2
(V0.5)
0
0
VDSAT (V)
0.40
-0.80
k (A/V2)
200x10-6
-100x10-6
(V-1)
0
0
WL
M2
Q
M5
BL
M1
M4
Q M6
M3
BL
a) (10 points) Equations 12.2-12.4 from your text can
be used to determine if this circuit is vulnerable to a
read-upset problem. Based on these equations, in
order to ensure proper operation would you
(circle one and show your work)
(a) Increase the width of M5, M6
(b) Increase the length of M5 & M6
(c) Leave both the length and the width of M5 &
M6 as they are
b) (10 points) Are equations 12.2 12.4 appropriate to solve this problem? Why or why not?
(Show your work for full credit)
c) (5 points) Equations 12.5 12.5 can be used to determine if a new value can be successfully
written to the bit-cell. Based on those equations, will the circuit above work? Why or why not?
NC State University
ECE Department
ECE 746
VLSI Systems Design
Page 5 of 5
Fall 2005
(15 points) Problem 4 (Memory - continued)
A rough sketch of the bit-cell layout from Problem 3 is given below. The word-line is
implemented in poly-silicon, and the bit-lines are in metal 1. Assume that each of the accesstransistors (M5 & M6) occurs when the word-line crosses a 150nm-wide strip of nactive. Each
access-transistor has the capacitance values given below. Assume that the memory array size is
256 bits per word and 256 words.
Estimate the time needed for a read-operation. Include the time needed to charge the word-line
to 0.5 V and discharge the bit-line by 0.1 V. Draw the equivalent circuit and compute the value
for full credit.
1300 nm
ca (aF/m2)
cf (aF/m)
R (/)
M1
30
40
0.05
poly
100
150
5
M5 & M6
CGS (fF)
3
CDB (fF)
2
150 nm
BL BL
2100
nm
WL
100 nm
