CUELLAR VENTURA ESTTYWAR BRIAAM 1223210038
PROGRAMAS EN VHDL
1.-Compuerta not:
library IEEE;
use IEEE.std_logic_1164.all;
entity compuerta _nor is
port (
A: in std_logic;
F: out std_logic
);
end compuerta _nor;
architecture com_arch of compuerta _nor is
begin
process (A) begin
if (A=0 ) then
F <= 1;
else
F <= 0;
end if;
end process;
end com_arch;
2.-Compuerta nor:
library IEEE;
use IEEE.std_logic_1164.all;
entity compuerta _noris
port (A: in std_logic;
B: in std_logic;
F: out std_logic);
end com_nor;
architecture com_arch of compuerta_nor is
begin
process (A,B) begin
if (A=0 and B = 0) then
F <= 1;
else
F <= 0;
end if;
end process;
end com_arch;
3.-Compuerta nand:
library IEEE;
use IEEE.std_logic_1164.all;
entity compuerta_nand is
port (
A: in std_logic;
B: in std_logic;
F: out std_logic
);
end compuerta_nand;
architecture com_arch of compuerta_nand is
begin
CUELLAR VENTURA ESTTYWAR BRIAAM 1223210038
process (A,B) begin
if (A=1 and B = 1) then
F <= 0;
else
F <= 1;
end if;
end process;
end com_arch;
4.-Compuerta and:
library IEEE;
use IEEE.std_logic_1164.all;
entity compuerta_and is
port ( A: in std_logic;
B: in std_logic;
F: out std_logic );
end compuerta_and;
architecture com_arch of compuerta_and is
begin
process (A,B) begin
if (A=1 and B = 1) then
F <= 1;
else
F <= 0;
end if;
end process;
end com_arch;
5.-Compuerte or:
library IEEE;
use IEEE.std_logic_1164.all;
entity compuerta_or is
port (A: in std_logic;
B: in std_logic;
F: out std_logic);
end compuerta_or;
architecture com_arch of compuerta_or is
begin
process (A,B) begin
if (A=0 and B = 0) then
F <= 0;
else
F <= 1;
end if;
end process;
end com_arch;
6.-Compuerta xor:
library IEEE;
use IEEE.std_logic_1164.all;
entity compuerta_xor is
port (A: in std_logic;
B: in std_logic;
F: out std_logic);
end compuerta_xor;
architecture com_arch of compuerta_xor is
CUELLAR VENTURA ESTTYWAR BRIAAM 1223210038
begin
process (A,B) begin
if (A = B) then
F <= 0;
else
F <= 1;
end if;
end process;
end com_arch;
7.-Compuerta xnor:
library IEEE;
use IEEE.std_logic_1164.all;
entity compuerta_xnor is
port (A: in std_logic;
B: in std_logic;
F: out std_logic);
end compuerta_xnor;
architecture com_arch of compuerta_xnor is
begin
process (A,B) begin
if A = B then
F <= 1;
else
F <= 0;
end if;
end process;
end com_arch;
8.- MUX DE 4 a 1 :
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (output_signal:
out std_logic;
in1, in2, in3, in4: in std_logic;
sel:
in std_logic_vector( 1 downto 0)
);
end mux;
architecture behave of mux is
begin
process (in1, in2, in3, in4, sel)
begin
case sel is
when "00" =>
output_signal <= in1;
when "01" =>
output_signal <= in2;
when "10" =>
output_signal <= in3;
CUELLAR VENTURA ESTTYWAR BRIAAM 1223210038
when "11" =>
output_signal <= in4;
when others =>
output_signal <= 'X';
end case;
end process;
end behave;
9.-
F=A'B'+B'C+AC
library ieee;
use ieee.std_logic_1164.all;
entity operacion basica is
port
(A,B,C: in std_logic;
F: out std_logic);
end operacion basica;
architecture com_arch of operacion basica is
begin
process (A,B) begin
begin
F<= (not A AND not B)OR(not B AND C)OR(A AND not C);
end process;
end com_arch;
10.-CODOFICADOR:
library ieee;
use ieee.std_logic_1164.all;
entity BCD_9 is port(
A: in std_logic_vector(3 downto 0);
Y: out std_logic_vector(9 downto 0));
end BCD_9;
architecture archBCD_9 of BCD_9 is
begin
with A select
Y<="0000000001" when "0000",
"0000000010" when "0001",
"0000000100" when "0010",
"0000001000" when "0011",
"0000010000" when "0100",
"0000100000" when "0101",
"0001000000" when "0110",
"0010000000" when "0111",
"0100000000" when "1000",
"1000000000" when "1001",
"0000000000" when others;
end archBCD_9;
