Bibliography of Papers related to Reversible Logic

last update: May 2013

J. E. Rice
University of Lethbridge
[Link]@[Link]
Contents
1 Introduction 2
2 Reversible Logic in General 2
3 Reversible Logic Synthesis 3
3.1 Group Theory Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Transformation Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.3 Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.4 ESOP-based Approaches (and related) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.5 Peres and other (non-Tooli) Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.6 Decision Diagram-Based Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.7 Cycle-Based Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.8 Other Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.9 Post-synthesis Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Testing and Testability of Reversible Logic Circuits 6
5 Fault Tolerant Reversible Logic/Computing 8
6 Connections to Quantum Computing 8
7 Multiple-Valued Reversible Logic 9
8 Sequential Reversible Logic 10
1
9 Technologies and (Gate) Implementations 10
10 Circuits and Designs 11
11 Resources 11
12 Books 11
13 Related Resources 11
1 Introduction
This document provides a list of reversible logic papers and categorizes them according to the topic they are
addressing. There is likely to be overlap, and there is likely to be disagreement on appropriate categorization.
However the main purpose of this categorization is to provide some direction for students pursuing any of
these topics for research or undergraduate projects, and thus this is intended only to be a starting point.
Updates are welcome and should be emailed to [Link]@[Link] with full bibliographic details, the topic(s)
under which to list the paper(s) and if possible a pdf of the paper to be added.
2 Reversible Logic in General
1961: Irreversibility and Heat Generation in the Computing Process [Lan61]
1973: Logical Reversibility of Computation [Ben73]
1979: Conservative Logic Elements and Their Universality [SK79]
1980: Reversible Computing [Tof80]
1982: Conservative Logic [FT82]
1986: Quantum mechanical computers [Fey86]
1991: Optoelectronic, Multivalued, Conservative Logic [Pic91]
1994: Results on two-bit gate design for quantum computers [DS94]
2003: Time, space, and energy in reversible computing [Fra03]
2005: Thermodynamical cost of reversible computing [LT05]
2005: Reversible Logic, Pan and Nalasani [PN05]
2005: Time, space, and energy in reversible computing [Vit05]
2005: Approaching the Physical Limits of Computing [Fra05a]
2005: Introduction to Reversible Computing: Motivation, Progress, and Challenges [Fra05b]
2009: On the CNOT-cost of TOFFOLI gates, Shende & Markov [SM09]
2
2011: From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits,
Drechsler and Wille [DW11]
2012: Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technol-
ogy, Drechsler and Wille [DW12]
2012: Berut, Antoine et al., Experimental verication of Landauers principle linking information and
thermodynamics, [BAP
+
12]
3 Reversible Logic Synthesis
2012: Synthesis and Optimization of Reversible Circuits - A Survey, Saeedi and Markov [SM12]
2010: Wille and Drechsler, Synthesis of Boolean Functions in Reversible Logic [SB10] (Chapter 4)
2011: Wille, R. and Keszocze, O. and Drechsler, R., Determining the minimal number of lines for large
reversible circuits [WKD11]
3.1 Group Theory Approaches
1999: Group Theoretical Aspects of Reversible Logic Gates [SVJ99]
2004: New Classes of Kronecker-Based Reversible Decision Trees and their Group-Theoretic Represen-
tations [AR04a]
2005: Implementing an Arbitrary Reversible Logic Gate [RVS05]
2006: Using Group Theory in Reversible Computing [RVK06]
2006: The Decomposition of an Arbitrary Reversible Logic Circuit [VRK06]
2007: Synthesis of Reversible Logic for Nanoelectronic Circuits [VR07]
2009: Multiple-Valued Reversible Logic Circuits [DR09]
3.2 Transformation Approaches
2002: Transformation Rules for Designing CNOT-based Quantum Circuits [IKY02]
2003: A transformation based algorithm for reversible logic synthesis [MMD03]
2003: Transformation-based Synthesis of Networks of Tooli/Fredkin Gates [DMM03]
2005: Synthesis of Fredkin-Tooli Reversible Networks [MDM05a]
2007: Techniques for the synthesis of reversible Tooli networks [MDM07]
2007: A novel synthesis algorithm for reversible circuits, Saeedi, Sedighi and Zamani [SSZ07]
2008: Moving forward: A non-search based synthesis method toward ecient CNOT-based quantum
circuit synthesis algorithms, Saeedi, Zamani and Sedighi [SZS08]
2010: ESOP-Based Tooli Network Generation with Transformations [SD10]
3
3.3 Templates
2003: (this is the paper to cite for work on templates) A Transformation Based Algorithm for Reversible
Logic Synthesis, Miller, Maslov and Dueck [MMD03]
2003: Fredkin/Tooli Templates for Reversible Logic Synthesis[MDM03a]
2003: Simplication of Tooli Networks via Templates[MDM03b]
2003: Templates for Tooli Network Synthesis[MDM03c]
2005: Tooli Network Synthesis with Templates[MDM05b]
2007: Techniques for the synthesis of reversible Tooli networks[MDM07]
3.4 ESOP-based Approaches (and related)
2007: ESOP-based Tooli Gate Cascade Generation [FTR07] (this is the original ESOP-based synthesis
work)
2009: Tooli Gate Cascade Generation Using ESOP Minimization and QMDD-Based Swapping [RFTK09]
2009: Generating Tooli Networks from ESOP Expressions [SD09]
2010: ESOP-Based Tooli Network Generation with Transformations [SD10]
2010: Using Autocorrelation Coecients-based Cost Functions in ESOP-based Tooli Gate Cascade
Generation [RS10]
2010: Near-Optimal Ordering of ESOP Cubes for Tooli Networks [HD10]
2010: Decomposition of Reversible Logic Function Based on Cube-Reordering [LKPK11]
2010: Rule-Based Optimization of Reversible Circuits, Arabzadeh, Saeedi and Zamani [ASZ10]
2011: Ordering Techniques for ESOP-Based Tooli Cascade Generation [RN11]
2011: Improved ESOP-based Synthesis of Reversible Logic [NR11a]
3.5 Peres and other (non-Tooli) Gates
2003: Improved quantum cost for n-bit Tooli gates [MD03c]
2008: Reversible logic synthesis with Fredkin and Peres gates [DJ08]
3.6 Decision Diagram-Based Approaches
2006: Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams [AP06]
2006: QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits [MT06]
2006: A Decision Diagram Package for Reversible and Quantum Circuit Simulation [TMG06]
2009: Equivalence Checking of Reversible Circuits [WGMD09]
2009: BDD-based synthesis of reversible logic for large functions [WD09]
2010: BDD-Based Synthesis of Reversible Logic, Robert Wille and Rolf Drechsler [WD10]
4
3.7 Cycle-Based Approaches
2009: A cycle-based synthesis algorithm for reversible logic, Sasanian, Saeedi, Sedighi and Zamani [SSSZ09]
2010: Reversible circuit synthesis using a cycle-based approach, Saeedi, Zamani, Sedighi and Sasa-
nian [SZSS10]
2010: A library-based synthesis methodology for reversible logic, Saeedi, Zamani and Sedighi [SSZ10]
3.8 Other Approaches (grouped somewhat by topic)
2001: A General Decomposition for Reversible Logic [PJM
+
01]
2001: Regular Realization of Symmetric Functions using Reversible Logic [PKB
+
01b]
2001: Regularity and Symmetry as a Base for Ecient Realization of Reversible Logic Circuits [PKB
+
01a]
2002: Synthesis of Multipurpose Reversible Logic Gates [Ker02]
2002: Logic Synthesis of Reversible Wave Cascades [MP02]
2002: Reversible Logic Synthesis by Iterative Compositions [KPK02]
2003: Multi-Output ESOP Synthesis with Cascades of New Reversible Gate Family [KP03]
2004: A New Heuristic Algorithm for Reversible Logic Synthesis [Ker04]
2004: Synthesis of Reversible Logic [AJ04]
2006: An Algorithm for Synthesis of Reversible Logic Circuits [GAJ06]
2002: Spectral and Two-Place Decomposition Techniques in Reversible Logic [Mil02]
2007: Techniques for the synthesis of reversible Tooli networks [MDM07]
2004: A Synthesis Method for MVL Reversible Logic [MDM04]
2002: Reversible Logic Circuit Synthesis [SPMH02]
2003: Synthesis of Reversible Logic Circuits [SPMH03]
2003: Garbage in Reversible Designs of Multiple-Output Functions [MD03b]
2003: Reversible Function Synthesis with Minimum Garbage Outputs [DM03]
2003: Complexity of Reversible Tooli Cascades and EXOR PLAs [MD03a]
2003: Reversible Logic Synthesis (PhD Thesis) [Mas03]
2003: Improved quantum cost for n-bit Tooli gates [MD03c]
2004: Reversible Cascades with Minimal Garbage [MD04]
2003: Spectral Techniques for Reversible Logic Synthesis [MD03d]
5
1978: Realization of Minimum Circuits with Two-Input Conservative Logic Elements [SK78b]
1978: Cascade Realization of 3-Input 3-Output Conservative Logic Circuits [SK78a]
2003: Evolutionary approach to Quantum and Reversible Circuits synthesis [LPG
+
03]
2003: Evolutionary Synthesis of Logic Circuits Using Information Theory [AC03]
2004: Genetic algorithm based synthesis of multi-output ternary functions using quantum cascade of
generalized ternary gates [KP04]
2008: Evolutionary approach to quantum symbolic logic synthesis [LP08]
2011: Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms, Drechsler,
Finder and Wille [DFW11]
2008: Bi-Directional Synthesis of 4-Bit Reversible Circuits [YSHP08]
2008: Quantum Circuit Simplication and Level Compaction [MDMN08]
2010: Reducing the Number of Lines in Reversible Circuits [WSD10]
2010: Reducing Reversible Circuit Cost by Adding Lines [MWD10]
2007: Fast Exact Tooli Network Synthesis of Reversible Logic [WG07]
2012: Exact Synthesis of Tooli Gate Circuits with Negative Control Lines, Wille, Soeken, Przigoda
and Drechsler [WSPD12]
2007: On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation
and Improvement Saeedi, Zamani and Sedighi [SZS07]
2010: Lowering the Quantum Gate Cost of Reversible Circuits, Miller and Sasanian [MS10]
2012: Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic, Wille, R. and Soeken,
M. and Schonborn, E. and Drechsler, R. [WDOGO12]
3.9 Post-synthesis Optimization
2011: Synthesis of quantum circuits for linear nearest neighbor architectures
Saeedi, Wille and Drechsler [SWD11]
4 Testing and Testability of Reversible Logic Circuits
2004: Online Testable Reversible Logic Circuit Design using NAND Blocks [VLP04]
2003: Fault testing for reversible circuits, Patel, Hayes and Markov [PHM03]
2004: Fault testing for reversible circuits, Patel, Hayes and Markov [PHM04]
6
2004: Testing for Missing-Gate Faults in Reversible Circuits, Hayes, Polian and Becker [HPB04]
2005: Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Re-
versible Iterative Logic Arrays Chakraborty [Cha05]
2005: A Family of Logical Fault Models for Reversible Circuits, Polian, Hayes, Fiehn and Becker [PHFB05]
2005: Reversible Fault-Tolerant Logic [BR05]
2005: The construction of a fault tolerant reversible gate for quantum computation [VLP05]
2005: Test generation and fault localization for quantum circuits [PBL05]
2006: Constructing Online Testable Circuits using Reversible Logic, Mahammad, Hari, Shro and
Kamakoti [MHSK06]
2006: Reversible-Logic Design With Online Testability [VLDP06]
2006: Fault-Tolerant Reversible Circuits [Par06]
2006: Analyzing Fault Models for Reversible Logic Circuits [ZM06]
2007: Fault tolerant error coding and detection using reversible gates [JSJS07]
2007: A DFT methodology for detecting bridging faults in reversible logic circuits, Bubna, M. and
Goyal, N. and Sengupta, I. [BGS07]
2007: Optimum Test Set for Bridging Fault Detection in Reversible Circuits
Rahaman, H. and Kole, D.K. and Das, D.K. and Bhattacharya, B.B. [RKDB07]
2008: Design of a Novel Fault Tolerant Reversible Full Adder for Nanotechnology Based Systems [HN08]
2008: Minimization of CTS of k-CNOT Circuits for SSF and MSF Model, Ibrahim, Chowdhury and
Babu [ICB08a]
2008: On the Minimization of Complete Test Set of Reversible k-CNOT Circuits for Stuck-at Fault
Model,Ibrahim, Chowdhury and Babu [ICB08b]
2008: On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set, Rahaman,
Kole, Das and Bhattacharya [RKDB08]
2008: Fault detection for single and multiple missing-gate faults in reversible circuits, Xiao Fang-ying
and Chen Han-wu and Liu Wen-jie and Li Zhi-giang [FyHwWjZg08]
2008: Universal test set for bridging fault detection in reversible circuit, Sarkar, P. and Chakrabarti,
S. [SC08]
2009: Synthesis of Fault Tolerant Reversible Logic Circuits[IRB
+
09]
2009: Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders[IRBH09]
2010: Fault Models for Quantum Mechanical Switching Networks, Biamonte, Allen and Perkowski [BAP10]
2010: Constructing Online Testable Circuits Using Reversible Logic, Mahammad and Veezhinathan [MV10]
2010:Synthesis of online testable reversible circuit, Kole, D.K. and Rahaman, H. and Das, D.K. and
Bhattacharya, B.B. [KRDB10b]
2010: Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible
Circuits, Kole, D.K. and Rahaman, H. and Das, D.K. and Bhattacharya, B.B. [KRDB10a]
2010: Online Multiple Fault Detection in Reversible Circuits, Farazmand, N. and Zamani, M. and
Tahoori, M.B. [FZT10a]
2010: Online fault testing of reversible logic using dual rail coding, Farazmand, N. and Zamani, M.
and Tahoori, M.B. [FZT10b]
7
2011: Online Testable Ternary Reversible Circuit, Rahman and Rice [RR11a]
2011: On Designing a Ternary Reversible Circuit for Online Testability, Rahman and Rice [RR11b]
2011: Online Fault Detection in Reversible Logic, Nayeem and Rice [NR11b]
2011: A Simple Approach for Designing Online Testable Reversible Circuits, Nayeem and Rice [NR11c]
2011: Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits,
Kole, D.K. and Rahaman, H. and Das, D.K. and Bhattacharya, B.B [KRDB11]
2011: Online Missing/Repeated Gate Faults Detection in Reversible Circuits Zamani, M. and Tahoori,
M.B., [ZT11]
2011: Fault Masking and Diagnosis in Reversible Circuits, Zamani, M. and Farazmand, N. and Tahoori,
M.B. [ZFT11]
2011: Debugging reversible circuits, Robert Wille, Daniel Groe, Stefan Frehse, Gerhard W. Dueck
and Rolf Drechsler [WGF
+
11]
2012: Design of an Online Testable Ternary Circuit from the Truth Table, Nayeem and Rice [NR12]
2012: A DFT methodology targeting online testing of reversible circuit, Sen, B. and Das, J. and Sikdar,
B.K. [SDS12]
5 Fault Tolerant Reversible Logic/Computing
2005: The construction of a fault tolerant reversible gate for quantum computation, Vasudevan et
al. [VLP05]
2005: Reversible fault-tolerant logic, Boykin and Roychowdhury [BR05]
2006: Fault-Tolerant Reversible Circuits, Parhami [Par06]
2009: Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders, Islam, Rahman,
Begumand and Haz [IRBH09]
2009: Synthesis of Fault Tolerant Reversible Logic Circuits, Islam, Rahman, Begum, Haz and Al
Mahmud [IRB
+
09]
2012: Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis, Mitra and Chowd-
hury [MC12]
6 Connections to Quantum Computing
1995: Quantum Computation [DiV95]
2000: The Physical Implementation of Quantum Computation [DiV00]
2000: Quantum Computation and Quantum Information [NC00]
2000: Multivalued logic gates for quantum computation, Muthukrishnan and Stroud [MS00]
2002: Multiple-Valued Quantum Logic [ARCP02]
2003: Improving Gate-Level Simulation of Quantum Circuits [VMH03]
2004: Quantum Circuit Synthesis Using Classes of GF(3) Reversible Fast Spectral Transforms [AR04b]
2005: Graph-based Simulation of Quantum Computation in the Density Matrix Representation [VMH05a]
8
2005: Is Quantum Search Practical? [VMH05b]
2006: A Decision Diagram Package for Reversible and Quantum Circuit Simulation [TMG06]
2006: Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams [AP06]
2006: QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits [MT06]
2006: Quantum Programming Languages Survey and Bibliography, Gay [Gay06]
2007: Quantum Logic Circuit Simulation Based on the QMDD Data Structure [GTFM07]
2008: Quantum Circuit Simplication and Level Compaction [MDMN08]
2009: Tooli Gate Cascade Generation Using ESOP Minimization and QMDD-Based Swapping [RFTK09]
2011: Reversible Circuit Optimization Via Leaving the Boolean Domain, Maslov and Saeedi [MS11]
2012: Constant-optimized quantum circuits for modular multiplication and exponentiation, Markov
and Saeedi [MS12]
2012: Synthesis of reversible circuits with minimal lines for large functions, Soeken, Wille, Hilken,
Przigoda and Drechsler [SWH
+
12]
2013: Faster quantum number factoring via circuit synthesis, Markov and Saeedi [MS13]
7 Multiple-Valued Reversible Logic
1991: Optoelectronic, Multivalued, Conservative Logic[Pic91]
1996: Multi-Valued Sequential Logic Design using Fredkin Gates[Pic96]
2000: Multivalued logic gates for quantum computation, Muthukrishnan and Stroud [MS00]
2002: Multiple-Valued Quantum Logic[ARCP02]
2004: A Synthesis Method for MVL Reversible Logic[MDM04]
2004: Genetic algorithm based synthesis of multi-output ternary functions using quantum cascade of
generalized ternary gates[KP04]
2006: Using Multiple-Valued Gates to Implement Reversible Logic[MBLO06]
2006: On Universality of General Reversible Multiple-Valued Logic Gates[?] ADD TO BIB
2006: Synthesis of Quantum Multiple-Valued Circuits[MT06]
2009: Multiple-Valued Reversible Logic Circuits[DR09]
2009: Quantum Realization of Multiple-Valued Feynman and Tooli Gates Without Ancilla Input,
Khan [Kha09]
2012: Design of an Online Testable Ternary Circuit from the Truth Table, Nayeem and Rice [NR12]
9
8 Sequential Reversible Logic
1996: Multi-Valued Sequential Logic Design using Fredkin Gates[Pic96]
2005: A Beginning in the Reversible Logic Synthesis of Sequential Circuits[TSZ05]
2005: An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits
using Fredkin Gates[TS05a]
2006: A New Look at Reversible Memory Elements[Ric06]
2006: Reversible Logic Designs for Sequential Elements[CW06]
2007: An Introduction to Reversible Latches[Ric07]
2008: Synthesis of reversible sequential elements[CW08]
2010: Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs[TR10]
2011: Synthesis of Reversible Synchronous Counters[KP11]
2012: A Synthesis Flow for Sequential Reversible Circuits, Soeken, M. and Wille, R. and Otterstedt,
C. and Drechsler, R. [SWOD12]
9 Technologies and (Gate) Implementations
1994: Reversible logic issues in adiabatic CMOS [AS94]
1995: Elementary Gates for Quantum Computations [BBC
+
95]
1995: Asymptotically Zero Power in Reversible Sequential Machines [Pat95]
1996: Energy Recovery Circuits Using Reversible and Partially Reversible Logic [YR96]
2000: The Physical Implementation of Quantum Computation [DiV00]
2000: A three-port nRERL register le for ultra-low-energy applications [KLC00]
2002: NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison Versus the
Fan-In, Alioto and Palumbo [AP02]
2002: Desoete, Bart and De Vos, Alexis, A reversible carry-look-ahead adder using control gates [DDV02]
2005: Making Adiabatic Circuits Attractive for Todays VLSI Industry by Multi-mode Operation-
adiabatic Mode Circuits [HNE
+
05]
2005: Reversible Computing: From Mathematical Group Theory to Electronical Circuit Experi-
ment [VR05]
2005: Implementation of a Simple 8-bit Microprocessor with Reversible Energy Recovery Logic [KC05]
2006: Using Multiple-Valued Gates to Implement Reversible Logic [MBLO06]
2008: J. Chen et al., Extended Tooli gate implementation with photons [CZW
+
08]
2012: De Vos, Alexis and Burignat, Ste phane and Thomsen, Michael Kirkedal, Reversible implemen-
tation of a discrete integer linear transformation [DVBT12]
2012: Wille, R. and Drechsler, R. and Osewold, C. and Garcia-Ortiz, A., Automatic design of low-power
encoders using reversible circuit synthesis [WDOGO12]
10
10 Circuits and Designs
2005: A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead
and Other Adder Architectures, Thapliyal and Srinivas [TS05a]
2005: A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look Ahead
Adder and Other Adder Architectures, Thapliyal and Srinivas [TS05b]
2005: The construction of a fault tolerant reversible gate for quantum computation, Vasudevan et
al. [VLP05]
2006: A new approach to synthesize multiple-output functions using reversible programmable logic
array[CNB06]
2006: Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format, Thapliyal,
Kotiyal and Srinivas [TKS06]
2008: Ecient approaches for designing reversible Binary Coded Decimal adders[BHCB08]
2008: Design of a Novel Fault Tolerant Reversible Full Adder for Nanotechnology Based Systems[HN08]
2009: Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders[IRBH09]
2010: Adder Designs using Reversible Logic Gates, Lala, Parkerson and Chakraborty [LPC10]
2011: Synthesis of Reversible Synchronous Counters[KP11]
2012: An ecient approach for designing and minimizing reversible programmable logic arrays[MJKHB12]
2013: Design of a 4-bit 2s Complement Reversible Circuit for Arithmetic Logic Unit Applications, [SSMT13]
11 Resources
2008: RevLib: An Online Resource for Reversible Functions and Reversible Circuits[WGT
+
08]
2008: Reversible Logic Synthesis Benchmarks Page[MDS08]
12 Books
2004: Reversible Logic Synthesis [AR04b]
13 Related Resources
1999: Sasao, Switching Theory for Logic Synthesis [Sas99]
2002: International Technology Roadmap for Semiconductors (ITRS) [ITR02]; 2009 update [ITR09];
2011 update [ITR11]
2008: Multiple Valued Logic: Concepts and Representations[MT08]
11
References
[AC03] A. H. Aguirre and C. A. Coello Coello. Evolutionary synthesis of logic circuits using infor-
mation theory. Articial Intelligence Review, 20(34), December 2003.
[AJ04] A. Agrawal and N. K. Jha. Synthesis of reversible logic. In Proceedings of the Design,
Automation and Test in Europe Conference and Exhibition (DATE), pages 13841385, 2004.
1620 February, Paris, France, IEEE Computer Society.
[AP02] Massimo Alioto and Gaetano Palumbo. Nand/nor adiabatic gates: Power consumption
evaluation and comparison versus the fan-in. IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS I, 49(9):12531262, Sept. 2002.
[AP06] A. Abdollahi and M. Pedram. Analysis and synthesis of quantum circuits by using quantum
decision diagrams. In Volume 1 of the Proceedings of Design, Automation and Test in Europe
(DATE), pages 16, 2006.
[AR04a] A. N. Al-Rabadi. New classes of Kronecker-based reversible decision trees and their group-
theoretic representations. In Proceedings of the International Workshop on Spectral Meth-
ods and Multirate Signal Processing (SMMSP), pages 233243, 2004. Vienna, Austria,
[Link] 11-12.
[AR04b] A. N. Al-Rabadi. Reversible Logic Synthesis: From Fundamentals to Quantum Computing.
Springer-Verlag, 2004.
[ARCP02] A. Al-Rabadi, L. Casperson, and M. Perkowski. Multiple-valued quantum logic. Quantum
Computers and Computing, 3(1):6391, 2002.
[AS94] W. C. Athas and L. J. Svensson. Reversible logic issues in adiabatic CMOS. In Proceedings
of the Workshop on Physics and Computation (PhysComp), pages 111118, Dallas, TX,
1994.
[ASZ10] Mona Arabzadeh, Mehdi Saeedi, and Morteza Saheb Zamani. Rule-based optimization of
reversible circuits. In Proceedings of the 15th Asia and South Pacic Design Automation
Conference (ASPDAC), pages 849854, 2010.
[BAP10] Jacob D. Biamonte, Je S. Allen, and Marek A. Perkowski. Fault models for quantum
mechanical switching networks. (JETTA), 26(5):499511, 2010.
[BAP
+
12] Antoine Berut, Artak Arakelyan, Artyom Petrosyan, Sergio Ciliberto, Raoul Dillenschneider,
and Eric Lutz. Experimental verication of landauers principle linking information and
thermodynamics. Nature, 483:187189, 2012.
[BBC
+
95] A. Barenco, C. H. Bennett, R. Cleve, D. P. DiVincenzo, N. Margolus, P. Shor, T. Sleator,
J. A. Smolin, and H. Weinfurter. Elementary gates for quantum computations. Physical
Review A, 52(5):34573467, November 1995.
[Ben73] C. H. Bennett. Logical reversibility of computation. IBM Journal of Research and Devel-
opment, 6:525532, 1973.
[BGS07] M. Bubna, N. Goyal, and I. Sengupta. A DFT methodology for detecting bridging faults in
reversible logic circuits. In Proceedings of TENCON IEEE Region 10 Conference, pages
14, 30 2007-nov. 2 2007.
[BHCB08] Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, and Haz Md. Hasan
Babu. Ecient approaches for designing reversible Binary Coded Decimal adders. Micro-
electronics Journal, 39(12):16931703, 2008.
[BR05] P.O. Boykin and V.P. Roychowdhury. Reversible fault-tolerant logic. In Proceedings of
the International Conference on Dependable Systems and Networks (DSN), pages 444453,
june-1 july 2005.
12
[Cha05] A. Chakraborty. Synthesis of reversible circuits for testing with universal test set and
C-testability of reversible iterative logic arrays. In Proceedings of the 18th International
Conference on VLSI Design, pages 249254, 2005.
[CNB06] A. R. Chowdhury, R. Nazmul, and H. Md. Hasan Babu. A new approach to synthesize
multiple-output functions using reversible programmable logic array. In Proceedings of the
19th International Conference on VLSI Design (held jointly with 5th International Confer-
ence on Embedded Systems and Design), pages 16, 2006. 3-7 Jan.
[CW06] M.-L. Chuang and C-Y. Wang. Reversible logic designs for sequential elements. In Pro-
ceedings of the 13th Workshop on Synthesis and System Integration of Mixed Information
Technologies (SASIMI), pages 127133, 2006. April 34, Nagoya, Japan, Sasimi Workshop.
[CW08] Min-Lun Chuang and Chun-Yao Wang. Synthesis of reversible sequential elements. Journal
of Emerging Technolies in Computer Systems, 3(4):4:14:19, January 2008.
[CZW
+
08] J. Chen, X. Zhang, L. Wang, X. Wei, and W. Zhao. Extended Tooli gate implementation
with photons. In Proceedings of 9th International Conference on Solid-State and Integrated-
Circuit Technology (ICSICT), pages 575578, China, 20-23 Oct 2008.
[DDV02] Bart Desoete and Alexis De Vos. A reversible carry-look-ahead adder using control gates.
Integr. VLSI J., 33(1):89104, December 2002.
[DFW11] Rolf Drechsler, Alexander Finder, and Robert Wille. Improving ESOP-based synthesis of
reversible logic using evolutionary algorithms. EvoApplications, 2:151161, 2011.
[DiV95] David P. DiVincenzo. Quantum computation. Science, 270, 1995.
[DiV00] David P. DiVincenzo. The physical implementation of quantum computation. Fortschritte
der Physik, 48(911):771783, Sept. 2000.
[DJ08] James Donald and Niraj K. Jha. Reversible logic synthesis with Fredkin and Peres gates.
Journal of Emerging Technologies in Computer Systems, 4(1):2:12:19, April 2008.
[DM03] G. W. Dueck and D. Maslov. Reversible function synthesis with minimum garbage outputs.
In Proceedings of the 6th International Symposium on Representations and Methodology of
Future Computing Technologies, 2003.
[DMM03] G. W. Dueck, D. Maslov, and D. M. Miller. Transformation-based synthesis of networks of
Tooli/Fredkin gates. In Proceedings of the IEEE Canadian Conference on Electrical and
Computer Engineering, pages 211214, vol.1, 2003.
[DR09] A. De Vos and Y. Van Rentergem. Multiple-valued reversible logic circuits. Journal of
Multiple-Valued Logic & Soft Computing, 15(5/6):489505, 2009.
[DS94] David P. DiVincenzo and J. Smolin. Results on two-bit gate design for quantum computers.
In Proceedings of the Workshop on Physics and Computation (PhysComp), pages 1423,
November, 1994.
[DVBT12] Alexis De Vos, Ste phane Burignat, and Michael Kirkedal Thomsen. Reversible implemen-
tation of a discrete integer linear transformation. JOURNAL OF MULTIPLE-VALUED
LOGIC AND SOFT COMPUTING, 18(1):2535, 2012.
[DW11] R. Drechsler and R. Wille. From truth tables to programming languages: Progress in the
design of reversible circuits. In Proceedings of the 2011 41st IEEE International Symposium
onMultiple-Valued Logic (ISMVL), pages 7885, May 2011.
[DW12] R. Drechsler and R. Wille. Reversible circuits: Recent accomplishments and future chal-
lenges for an emerging technology. In Proceedings of the International Symposium on VLSI
Design and Test (published as Lecture Notes in Computer Science Volume 7373), pages
383392, 2012. invited paper.
[Fey86] Richard Feynman. Quantum mechanical computers. Foundations of Physics, 16:507531,
1986. 10.1007/BF01886518.
13
[Fra03] M. P. Frank. Adiabatic circuits and reversible computing: Dispelling the misconceptions,
2003. downloaded from [Link]
[Fra05a] M. P. Frank. Approaching the physical limits of computing. In Proceedings of the Inter-
national Symposium on Multiple-Valued Logic (ISMVL), pages 168187, 2005. May 1821,
Calgary, Alberta, IEEE Computer Society.
[Fra05b] M. P. Frank. Introduction to reversible computing: Motivation, progress, and challenges. In
Proceedings of the 2nd Conference on Computing Frontiers, pages 385390, 2005. May 46,
Ischia, Italy, ACM Press.
[FT82] E. Fredkin and T. Tooli. Conservative logic. International Journal of Theoretical Physics,
21(3/4):219253, 1982.
[FTR07] K. Fazel, M. Thornton, and J. E. Rice. ESOP-based Tooli gate cascade generation. In
Proceedings of the IEEE Pacic Rim Conference on Communications, Computers and Signal
Processing (PACRIM), pages 206209, 2007. Aug. 2224 2007, Victoria, BC, Canada, IEEE
Press.
[FyHwWjZg08] Xiao Fang-ying, Chen Han-wu, Liu Wen-jie, and Li Zhi-giang. Fault detection for single and
multiple missing-gate faults in reversible circuits. In Proceedings of the IEEE World Congress
on Computational Intelligence, IEEE Congress on Evolutionary Computation, pages 131
135, june 2008.
[FZT10a] N. Farazmand, M. Zamani, and M. B. Tahoori. Online multiple fault detection in reversible
circuits. In Proceedings of the 2010 IEEE 25th International Symposium on Defect and Fault
Tolerance in VLSI Systems (DFT), pages 420437, 2010.
[FZT10b] N. Farazmand, M. Zamani, and M.B. Tahoori. Online fault testing of reversible logic using
dual rail coding. In Proceedings of the IEEE 16th International On-Line Testing Symposium
(IOLTS), pages 204205, july 2010.
[GAJ06] P. Gupta, A. Agrawal, and N. K. Jha. An algorithm for synthesis of reversible logic cir-
cuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
25(11):23172330, November 2006.
[Gay06] S. J. Gay. Quantum programming languages survey and bibliography. Mathematical Struc-
tures in Computer Science, 16(4), 2006.
[GTFM07] D. Goodman, M. A. Thornton, D. Feinstein, and D. M. Miller. Quantum logic circuit
simulation based on the QMDD data structure. In Proceedings of Representations and
Methodologies, pages 99105, 2007.
[HD10] Z. Hamza and G. W. Dueck. Near-optimal ordering of ESOP cubes for Tooli networks. In
Proceedings of the 2nd Annual Workshop on Reversible Computation (RC), 2010. July 23
Bremen, Germany.
[HN08] M. Haghparast and K. Navi. Design of a novel fault tolerant reversible full adder for nan-
otechnology based systems. World Applied Sciences Journal, 3(1):114118, 2008.
[HNE
+
05] S. Henzler, T. Nirschl, M. Eireiner, E. Amirante, and D. Schmitt-Landsiedel. Making adia-
batic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode
circuits. In Proceedings of the 2nd Conference on Computing Frontiers, pages 414420, 2005.
May 46, Ischia, Italy, ACM Press.
[HPB04] J. P. Hayes, I. Polian, and B. Becker. Testing for missing-gate faults in reversible circuits. In
Proceedings of the 13th Asian Test Symposium, ATS 04, pages 100105, Washington, DC,
USA, 2004. IEEE Computer Society.
[ICB08a] M. Ibrahim, A. R. Chowdhury, and H. M. H. Babu. Minimization of CTS of k-CNOT
circuits for SSF and MSF model. In Proceedings of the IEEE International Symposium on
Defect and Fault Tolerance of VLSI Systems, pages 290298, Boston, MA, 2008.
14
[ICB08b] M. Ibrahim, A. R. Chowdhury, and H. M. H. Babu. On the minimization of complete test
set of reversible k-CNOT circuits for stuck-at fault. In Proceedings of the 11th Interna-
tional Conference on Computer and Information Technology (ICCIT), pages 712, Khulna,
Bangladesh, December 2008.
[IKY02] K. Iwama, Y. Kambayashi, and S. Yamashita. Transformation rules for designing CNOT-
based quantum circuits. In Proceedings of the 39th Design Automation Conference, pages
419424, 2002.
[IRB
+
09] S. Islam, M.M. Rahman, Z. Begum, Z. Haz, and A. Al Mahmud. Synthesis of fault tolerant
reversible logic circuits. In IEEE Circuits and Systems International Conference on Testing
and Diagnosis (ICTD), pages 14, April 2009.
[IRBH09] M. S. Islam, M. M. Rahman, Z. Begumand, and M. Z. Haz. Fault tolerant reversible
logic synthesis: Carry look-ahead and carry-skip adders. In Proceedings of the International
Conference on Advances in Computational Tools for Engineering Applications, pages 296
401, 2009.
[ITR02] International technology roadmap for semiconductors (itrs). [Link] 2002
update, 2002.
[ITR09] International technology roadmap for semiconductors (itrs). [Link] 2009
executive summary, 2009.
[ITR11] International technology roadmap for semiconductors (itrs). [Link] 2011
executive summary, 2011.
[JSJS07] R. K. James, T. K. Shahana, K. P. Jacob, and S. Sasi. Fault tolerant error coding and
detection using reversible gates. In Proceedings of TENCON 2007 - 2007 IEEE Region 10
Conference, pages 14, 2007.
[KC05] S. Kim and S.-I. Chae. Implementation of a simple 8-bit microprocessor with reversible
energy recovery logic. In Proceedings of the 2nd Conference on Computing Frontiers, pages
421426, Ischia, Italy, 2005. ACM Press.
[Ker02] P. Kerntopf. Synthesis of multipurpose reversible logic gates. In Proceedings of the Euromicro
Symposium on Digital System Design: Architectures, Methods and Tools (DSD), pages 269
267, 2002.
[Ker04] P. Kerntopf. A new heuristic algorithm for reversible logic synthesis. In Proceedings of the
Design Automation Conference (DAC), pages 834837, 2004. June 711, San Diego, CA,
USA, ACM.
[Kha09] M. H. A. Khan. Quantum realization of multiple-valued Feynman and Tooli gates without
ancilla input. In Proceedings of the 39th International Symposium on Multiple-Valued Logic
(ISMVL), pages 103108, 21-23 May, Naha, Okinawa, Japan, 2009.
[KLC00] J.-H. Kwon, J. Lim, and S.-I. Chae. A three-port nRERL register le for ultra-low-energy
applications. In Proceedings of the 2000 International Symposium on Low Power Electronics
and Design (ISLPED 00), pages 161166, 2000.
[KP03] M. H. A. Khan and M. A. Perkowski. Multi-output ESOP synthesis with cascades of new
reversible gate family. In Proceedings of the 6th International Symposium on Representations
and Methodology of Future Computing Technology (RM 2003), pages 144153, 2003.
[KP04] M. H. A. Khan and M. Perkowski. Genetic algorithm based synthesis of multi-output ternary
functions using quantum cascade of generalized ternary gates. In Proceedings of the Congress
on Evolutionary Computation (CEC), volume 2, pages 21942201, 2004.
[KP11] M. H. A. Khan and M. Perkowski. Synthesis of reversible synchronous counters. In Proceed-
ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL), pages
242247, 2011.
15
[KPK02] A. B. Khlopotine, M. Perkowski, and P. Kerntopf. Reversible logic synthesis by iterative
compositions. In Proceedings of the International Workshop on Logic Synthesis (IWLS),
2002.
[KRDB10a] D.K. Kole, H. Rahaman, D.K. Das, and B.B. Bhattacharya. Derivation of optimal test set
for detection of multiple missing-gate faults in reversible circuits. In Proceedings of the 19th
IEEE Asian Test Symposium (ATS), pages 3338, dec. 2010.
[KRDB10b] D.K. Kole, H. Rahaman, D.K. Das, and B.B. Bhattacharya. Synthesis of online testable
reversible circuit. In Proceedings of the IEEE 13th International Symposium on Design and
Diagnostics of Electronic Circuits and Systems (DDECS), pages 277280, 2010.
[KRDB11] D.K. Kole, H. Rahaman, D.K. Das, and B.B. Bhattacharya. Derivation of automatic test set
for detection of missing gate faults in reversible circuits. In Proceedings of the International
Symposium on Electronic System Design (ISED), pages 200205, dec. 2011.
[Lan61] R. Landauer. Irreversibility and heat generation in the computing process. IBM Journal of
Research and Development, 5:183191, 1961.
[LKPK11] M. Lukac, M. Kameyama, M. Perkowski, and P. Kerntopf. Decomposition of reversible logic
function based on cube-reordering. In Proceedings of the Reed-Muller 2011 Workshop, pages
6370, 2011. May 2526, Tuusula, Finland.
[LP08] M. Lukac and M. Perkowski. Evolutionary approach to quantum symbolic logic synthesis. In
Proceedings of the IEEE Congress on Evolutionary Computation (CEC), pages 33743380,
2008.
[LPC10] P. K. Lala, J. P. Parkerson, and P. Chakraborty. Adder designs using reversible logic gates.
WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, 9:369378, June 2010.
[LPG
+
03] M. Lukac, M. Perkowski, H. Goi, M. Pivtoraiko, C. H. Yu, K. Chung, H. Jee, B-G. Kim, and
Y-D. Kim. Evolutionary approach to quantum and reversible circuits synthesis. Articial
Intelligence Review, Special Issue on Articial Intelligence in Logic Design, 20(34):361417,
December 2003.
[LT05] L. B. Levitin and T. Tooli. Thermodynamical cost of reversible computing. In Proceedings
of the 2nd Conference on Computing Frontiers, pages 445446, 2005. extended abstract for
invited talk.
[Mas03] D. Maslov. Reversible Logic Synthesis. PhD thesis, University of New Brunswick, Sept.
2003.
[MBLO06] O. Mirmotahari, Y. Berg, J. Lomsdalen, and V. Overas. Using multiple-valued gates to im-
plement reversible logic. In Proceedings of PhD Research in Microelectronics and Electronics
(PRIME), pages 361364, 2006.
[MC12] S.K. Mitra and A.R. Chowdhury. Minimum cost fault tolerant adder circuits in reversible
logic synthesis. In Proceedings of the 25th International Conference on VLSI Design (VL-
SID), pages 334339, January 2012.
[MD03a] D. Maslov and G. W. Dueck. Complexity of reversible Tooli cascades and EXOR PLAs.
In Proceedings of the International Workshop on Ultra-Large Scale Intergration, 2003.
[MD03b] D. Maslov and G. W. Dueck. Garbage in reversible designs of multiple-output functions.
In Proceedings of the 6th International Symposium on Representations and Methodology of
Future Computing Technologies, 2003.
[MD03c] D. Maslov and G. W. Dueck. Improved quantum cost for n-bit tooli gates. Electronics
Letters, 39(25):17901791, December 2003.
[MD03d] D. M. Miller and G. W. Dueck. Spectral techniques for reversible logic synthesis. In Pro-
ceedings of the 6th International Symposium on Representations and Methodology of Future
Computing Technologies, 2003.
16
[MD04] D. Maslov and G. W. Dueck. Reversible cascades with minimal garbage. IEEE Transactions
on Computer-Aided Design, 23(11):14971509, November 2004.
[MDM03a] D. Maslov, G. W. Dueck, and D. M. Miller. Fredkin/Tooli templates for reversible logic
synthesis. In International Conference on Computer Aided Design (ICCAD), pages 256261,
2003.
[MDM03b] D. Maslov, G. W. Dueck, and D. M. Miller. Simplication of Tooli networks via templates.
In Proceedings of the 16th Symposium on Integrated Circuits and System Design, 2003.
[MDM03c] D. Maslov, G. W. Dueck, and D. M. Miller. Templates for Tooli network synthesis. In
Proceedings of the International Workshop on Logic Synthesis, 2003.
[MDM04] D. M. Miller, G. W. Dueck, and D. Maslov. A synthesis method for MVL reversible logic. In
Proceedings of the 34th International Symposium on Multiple-Valued Logic (ISMVL), pages
7480, 2004. May 19-22, Toronto, Canada , IEEE.
[MDM05a] D. Maslov, G. W. Dueck, and D. M. Miller. Synthesis of Fredkin-Tooli reversible networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(6):765769, June
2005.
[MDM05b] D. Maslov, G. W. Dueck, and D. M. Miller. Tooli network synthesis with templates.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),
24(6):807817, June 2005.
[MDM07] D. Maslov, G. W. Dueck, and D. M. Miller. Techniques for the synthesis of reversible Tooli
networks. ACM Transactions on Design Automation of Electronic Systems (TODAES),
12(4):42, 2007.
[MDMN08] D. Maslov, G. W. Dueck, D. M. Miller, and C. Negrevergne. Quantum circuit simplication
and level compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, 27(3):436444, 2008.
[MDS08] D. Maslov, G. W. Dueck, and N. Scott. Reversible logic synthesis benchmarks page, 2008.
[MHSK06] S. N. Mahammad, S. Hari, S. Shro, and V. Kamakoti. Constructing online testable circuits
using reversible logic. In Proceedings of the 10th IEEE International VLSI Design and Test
Symposium (VDAT), pages 373383, Goa, India, August 2006.
[Mil02] D. M. Miller. Spectral and two-place decomposition techniques in reversible logic. In Pro-
ceedings of the IEEE Midwest Symposium on Circuits and Systems (MWCAS), pages II493
II496, 2002.
[MJKHB12] Sajib Kumar Mitra, Lafa Jamal, Mineo Kaneko, and Haz Md. Hasan Babu. An ecient
approach for designing and minimizing reversible programmable logic arrays. In Proceedings
of the great lakes symposium on VLSI, GLSVLSI 12, pages 215220, New York, NY, USA,
2012. ACM.
[MMD03] D. M. Miller, D. Maslov, and G. W. Dueck. A transformation based algorithm for reversible
logic synthesis. In DAC 03: Proceedings of the 40th conference on Design automation, pages
318323, New York, NY, USA, 2003. ACM.
[MP02] A. Mishchenko and M. Perkowski. Logic synthesis of reversible wave cascades. In Proceedings
of the International Workshop on Logic Synthesis (IWLS), pages 197202, 2002. June 4-7,
New Orleans, USA, IWLS Workshop.
[MS00] Ashok Muthukrishnan and C. R. Stroud. Multivalued logic gates for quantum computation.
Physical Review A, 62:052309, Oct 2000.
[MS10] D. Michael Miller and Zahra Sasanian. Lowering the quantum gate cost of reversible circuits.
In IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pages
260263, 2010.
17
[MS11] Dmitri Maslov and Mehdi Saeedi. Reversible circuit optimization via leaving the boolean
domain. IEEE Transactions on CAD of Integrated Circuits and Systems, 30(6):806816,
2011.
[MS12] Igor L. Markov and Mehdi Saeedi. Constant-optimized quantum circuits for modular multi-
plication and exponentiation. Quantum Information & Computation, 12(5-6):361394, 2012.
[MS13] Igor L. Markov and Mehdi Saeedi. Faster quantum number factoring via circuit synthesis.
Physical Review A, 87:012310, Jan 2013.
[MT06] D. M. Miller and M. A. Thornton. QMDD: A decision diagram structure for reversible and
quantum circuits. In Proceedings of the IEEE International Symposium on Multiple-Valued
Logic (ISMVL), page #30 on Proceedings CDROM, 2006. May 1720.
[MT08] D. M. Miller and M. A. Thornton. Multiple Valued Logic: Concepts and Representations.
Morgan & Claypool, 2008.
[MV10] Sk. N. Mahammad and K. Veezhinathan. Constructing online testable circuits using re-
versible logic. IEEE Transactions on Instrumentation and Measurement, 59(1):101109,
January 2010.
[MWD10] D. M. Miller, R. Wille, and R. Drechsler. Reducing reversible circuit cost by adding lines. In
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic (ISMVL),
pages 217222, 2010. 2628 May, Barcelona, Spain.
[NC00] M. A. Nielsen and I. L. Chuang. Quantum Computation and Quantum Information. Cam-
bridge University Press, 2000.
[NR11a] N. M. Nayeem and J. E. Rice. Improved ESOP-based synthesis of reversible logic. In
Proceedings of the 2011 Reed-Muller Workshop, pages 5762, 2011. 2526 May, Tuusula,
Finland.
[NR11b] N. M. Nayeem and J. E. Rice. Online fault detection in reversible logic. In Proceedings of
the 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
(DFT), pages 426434, Vancouver, BC, Canada, October 2011.
[NR11c] N. M. Nayeem and J. E. Rice. A simple approach for designing online testable reversible
circuits. In Proceedings of the 2011 IEEE Pacic Rim Conference on Communications, Com-
puters and Signal Processing (PACRIM), pages 274279, Victoria, B.C., Canada, August
2011. Best paper award.
[NR12] N. M. Nayeem and J. E. Rice. Design of an online testable ternary circuit from the truth ta-
ble. In Proceedings of the 4th Workshop on Reversible Computation (RC2012), Copenhagen,
Denmark July 2-3, 2012.
[Par06] B. Parhami. Fault-tolerant reversible circuits. In Proceedings of the Fortieth Asilomar
Conference on Signals, Systems and Computers (ACSSC), pages 17261729, 29 2006-nov. 1
2006.
[Pat95] Priyadarsan Patra. Asymptotically zero power in reversible sequential machines. Technical
Report CS-TR-95-14, Dept. of Computing Sciences, University of Texas at Austin, January
1995.
[PBL05] M. Perkowski, J. Biamonte, and M. Lukac. Test generation and fault localization for quan-
tum circuits. In Proceedings of the 35th International Symposium on Multiple-Valued Logic
(ISMVL), pages 6268, 2005.
[PHFB05] I. Polian, J. P. Hayes, T. Fiehn, and B. Becker. A family of logical fault models for reversible
circuits. In Proceedings of the 14th Asian Test Symposium (ATS), pages 422427, 821 Dec.,
Calcutta, India, 2005.
[PHM03] K. N. Patel, J. P. Hayes, and I. L. Markov. Fault testing for reversible circuits. In Proceedings
of the IEEE VLSI Test Symposium (VTS), pages 410416, Napa, CA, April, 2003.
18
[PHM04] K. N. Patel, J. P. Hayes, and I. L. Markov. Fault testing for reversible circuits. IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(8):1220
1230, 2004.
[Pic91] P. Picton. Optoelectronic, multivalued, conservative logic. International Journal of Optical
Computing, 2:1929, 1991.
[Pic96] P. Picton. Multi-valued sequential logic design using fredkin gates. Multiple-Valued Logic,
1:241251, 1996.
[PJM
+
01] M. Perkowski, L. Jozwiak, A. Mishchenko, A. Al-Rabadi, A. Coppola, A. Buller, X. Song,
M. Khan, S. N. Yanushkevich, V. P. Shmerko, and M. Chrzanowska-Jeske. A general decom-
position for reversible logic. In Proceedings of the International Workshop on Methods and
Representations (RM), pages 119138, 2001. August 1011, Starkville, Mississippi, USA,
RM Workshop.
[PKB
+
01a] M. Perkowski, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, X. Song,
A. Al-Rabadi, L. Jozwiak, and A. Coppola. Regularity and symmetry as a base for ecient
realization of reversible logic circuits. In Proceedings of the International Workshop on Logic
Synthesis (IWLS), 2001.
[PKB
+
01b] M. Perkowski, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, X. Song,
A. Al-Rabadi, L. Jozwiak, A. Coppola, and B. Massey. Regular realization of symmetric
functions using reversible logic. In Proceedings of the Euromicro Symposium on Digital
System Design (DSD), pages 245252, 2001.
[PN05] W. D. Pan and M. Nalasani. Reversible logic. IEEE Potentials, pages 3841, Febru-
ary/March 2005.
[RFTK09] J. E. Rice, K. B. Fazel, M. A. Thornton, and K. B. Kent. Tooli gate cascade generation using
ESOP minimization and QMDD-based swapping. In Proceedings of the International Sym-
posium on Representations and Methodology of Future Computing Technologies (RM2009),
pages 6372, 2009. May 2324, Naha, Okinawa, Japan.
[Ric06] J. E. Rice. A new look at reversible memory elements. In Proceedings of the Interna-
tional Symposium on Circuits and Systems (ISCAS), 2006. May 2124, Kos, Greece, IEEE
(CDROM paper [Link]).
[Ric07] J. E. Rice. An introduction to reversible latches. The Computer Journal, 51(6):700709,
2007.
[RKDB07] H. Rahaman, D.K. Kole, D.K. Das, and B.B. Bhattacharya. Optimum test set for bridging
fault detection in reversible circuits. In Proceedings of the 16th Asian Test Symposium
(ATS), pages 125128, Oct. 2007.
[RKDB08] H. Rahaman, D. K. Kole, D. K. Das, and B. B. Bhattacharya. On the detection of missing-
gate faults in reversible circuits by a universal test set. In Proceedings of the 21st Interna-
tional Conference on VLSI Design, pages 163168, 2008.
[RN11] J. E. Rice and N. Nayeem. Ordering techniques for ESOP-based Tooli cascade generation.
In Proceedings of the IEEE Pacic Rim Conference on Communications, Computers and
Signal Processing (PACRIM), pages 274279, 2011. Victoria, BC, Canada, 2326 Aug.
[RR11a] M. R. Rahman and J. E. Rice. Online testable ternary reversible circuit. In Proceedings of
the Reed-Muller 2011 Workshop, pages 7179, 2011. May 2526, Tuusula, Finland.
[RR11b] Md. R. Rahman and J. E. Rice. On designing a ternary reversible circuit for online testability.
In Proceedings of the 2011 IEEE Pacic Rim Conference on Communications, Computers
and Signal Processing (PACRIM), pages 119124, Victoria, B.C., Canada, August 2011.
[RS10] J. E. Rice and V. Suen. Using autocorrelation coecients-based cost functions in ESOP-
based Tooli gate cascade generation. In Proceedings of the 23rd IEEE Canadian Conference
on Electrical and Computer Engineering (CCECE), pages 16, 2010. May, Calgary, Canada.
19
[RVK06] Y. Van Rentergem, A. De Vos, and K. De Keyser. Using group theory in reversible comput-
ing. In Proceedings of the 2006 IEEE Congress on Evolutionary Computation (CEC2006),
pages 23972404, 2006.
[RVS05] Y. Van Rentergem, A. De Vos, and L. Storme. Implementing an arbitrary reversible logic
gate. Journal of Physics A: Mathematical and General, 38(16):35553577, April 2005.
[Sas99] T. Sasao. Switching Theory for Logic Synthesis. Kluwer Academic Publishers, 1999.
[SB10] Tsutomu Sasao and Jon T. Butler, editors. Progress in Applications of Boolean Functions:
Synthesis Lectures on Digital Circuits and Systems. Synthesis Lectures on Digital Circuits
and Systems, M. Thornton (ed.). Morgan and Claypool, 2010. 153 pages.
[SC08] P. Sarkar and S. Chakrabarti. Universal test set for bridging fault detection in reversible
circuit. In Proceedings of the 3rd International Design and Test Workshop (IDT), pages
5156, dec. 2008.
[SD09] Y. Sanaee and G. W. Dueck. Generating Tooli networks from ESOP expressions. In
Proceedings of the IEEE Pacic Rim Conference on Communications, Computers and Signal
Processing (PACRIM), pages 715719, 2009. Victoria, BC, Canada, 2326 Aug.
[SD10] Y. Sanaee and G. W. Dueck. ESOP-based Tooli network generation with transforma-
tions. In Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic
(ISMVL), pages 276281, 2010. 2628 May, Barcelona, Spain.
[SDS12] B. Sen, J. Das, and B.K. Sikdar. A DFT methodology targeting online testing of reversible
circuit. In Proceedings of the International Conference on Devices, Circuits and Systems
(ICDCS), pages 689693, march 2012.
[SK78a] T. Sasao and K. Kinoshita. Cascade realization of 3-input 3-output conservative logic cir-
cuits. IEEE Transactions on Computers, C-27(3):214221, March 1978.
[SK78b] T. Sasao and K. Kinoshita. Realization of minimum circuits with two-input conservative
logic elements. IEEE Transactions on Computers, C-27(8):749752, August 1978.
[SK79] T. Sasao and K. Kinoshita. Conservative logic elements and their universality. IEEE Trans-
actions on Computers, C-28(9):682685, Sept. 1979.
[SM09] Vivek V. Shende and Igor L. Markov. On the cnot-cost of tooli gates. Quantum Info.
Comput., 9(5):461486, May 2009.
[SM12] Mehdi Saeedi and Igor L. Markov. Synthesis and optimization of reversible circuits - a
survey. ACM Computing Surveys, 2012. to appear; downloaded from arXiv:1110.2574.
[SPMH02] V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes. Reversible logic circuit synthesis.
In IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 353
360, 2002. November 1014, San Jose, CA, USA, ACM.
[SPMH03] V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes. Synthesis of reversible
logic circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems,
22(6):710722, June 2003.
[SSMT13] Vandana Shukla, O. P. Singh, G. R. Mishra, and R. K. Tiwari. Article: Design of a 4-bit
2s complement reversible circuit for arithmetic logic unit applications. IJCA Special Issue
on International Conference on Communication, Computing and Information Technology,
ICCCMIT(2):15, February 2013. Published by Foundation of Computer Science, New York,
USA.
[SSSZ09] Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, and Morteza Saheb Zamani. A cycle-based
synthesis algorithm for reversible logic. In Proceedings of Asia South Pacic Design Au-
tomation Conference (ASP-DAC), pages 745750, 2009.
20
[SSZ07] Mehdi Saeedi, Mehdi Sedighi, and Morteza Saheb Zamani. A novel synthesis algorithm
for reversible circuits. In Proceedings of the International Conference on Computer-Aided
Design (ICCAD), pages 6568, 2007.
[SSZ10] Mehdi Saeedi, Mehdi Sedighi, and Morteza Saheb Zamani. A library-based synthesis
methodology for reversible logic. Microelectronics Journal, 41(4):185194, 2010.
[SVJ99] L. Storme, A. De Vos, and G. Jacobs. Group theoretical aspects of reversible logic gates.
Journal of Universal Computer Science, (5):307321, 1999.
[SWD11] Mehdi Saeedi, Robert Wille, and Rolf Drechsler. Synthesis of quantum circuits for linear
nearest neighbor architectures. Quantum Information Processing, 10(3):355377, June 2011.
[SWH
+
12] M. Soeken, R. Wille, C. Hilken, N. Przigoda, and R. Drechsler. Synthesis of reversible
circuits with minimal lines for large functions. In Proceedings of the 17th Asia and South
Pacic Design Automation Conference (ASP-DAC), pages 8592, 2012.
[SWOD12] M. Soeken, R. Wille, C. Otterstedt, and R. Drechsler. A synthesis ow for sequential
reversible circuits. In Proceedings of the 42nd IEEE International Symposium on Multiple-
Valued Logic (ISMVL), pages 299304, 2012.
[SZS07] Mehdi Saeedi, Morteza Saheb Zamani, and Mehdi Sedighi. On the behavior of substitution-
based reversible circuit synthesis algorithms: Investigation and improvement. In Proceedings
of the International Symposium on VLSI (ISVLSI), pages 428436, 2007.
[SZS08] Mehdi Saeedi, Morteza Saheb Zamani, and Mehdi Sedighi. Moving forward: A non-search
based synthesis method toward ecient CNOT-based quantum circuit synthesis algorithms.
In Proceedings of the Asia South Pacic Design Automation Conference (ASP-DAC), pages
8388, 2008.
[SZSS10] Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, and Zahra Sasanian. Reversible
circuit synthesis using a cycle-based approach. JETC, 6(4):13, 2010.
[TKS06] Himanshu Thapliyal, Saurabh Kotiyal, and MB. Srinivas. Novel BCD adders and their
reversible logic implementation for ieee 754r format. In Proceedings of the 19th IEEE/ACM
International Conference on VLSI Design and the 5th International Conference on Embedded
Systems (VLSI Design 2006), pages 387392, Hyderabad, Jan. 47, 2006.
[TMG06] M. Thornton, D. M. Miller, and D. Goodman. A decision diagram package for reversible and
quantum circuit simulation. In Proceedings of the IEEE Congress on Evolutionary Compu-
tation, pages 85978604, July 2006. held at the IEEE World Congress on Computational
Intelligence (WCCI).
[Tof80] T. Tooli. Reversible computing. Technical Report MIT/LCS/TM No. 151, MIT, 1980.
[TR10] Himanshu Thapliyal and Nagarajan Ranganathan. Design of reversible sequential circuits
optimizing quantum cost, delay, and garbage outputs. Journal of Emerging Technologies in
Computer Systems, 6(4):14:114:31, December 2010.
[TS05a] H. Thapliyal and M. B. Srinivas. An extension to DNA based Fredkin gate circuits: Design
of reversible sequential circuits using Fredkin gates. In Proceedings of SPIE Volume: 6050
Optomechatronic Micro/Nano Devices and Components, pages pp.196202, 2005. article
number 60500O.
[TS05b] Himanshu Thapliyal and MB. Srinivas. A novel reversible TSG gate and its application for
designing reversible carry look ahead adder and other adder architectures. In Lecture Notes
of Computer Science, vol. 3740, Proceedings of the 10th Asia-Pacic Computer Systems
Architecture Conference (ACSAC 05), pages 775786. Springer-Verlag, 2005.
[TSZ05] H. Thapliyal, M. B. Srinivas, and M. Zwolinski. A beginning in the reversible logic syn-
thesis of sequential circuits. In Proceedings of Military and Aerospace Programmable Logic
Devices (MAPLD) International Conference, page number 1012 (online proceedings), 2005.
September 79, Washington, DC, USA, NASA Oce of Logic Design.
21
[Vit05] P. Vitanyi. Time, space, and energy in reversible computing. In Proceedings of the 2nd
Conference on Computing Frontiers, pages 435444, 2005. May 46, Ischia, Italy, ACM
Press.
[VLDP06] D. P. Vasudevan, P. K. Lala, J. Di, and J. P. Parkerson. Reversible-logic design with online
testability. IEEE Transactions on Instrumentation and Measurement, 59(2):406413, April
2006.
[VLP04] D. P. Vasudevan, P. K. Lala, and J. P. Parkerson. Online testable reversible logic circuit
design using NAND blocks. In Proceedings of the 19th IEEE International Symposium on
Defect and Fault Tolerance in VLSI Systems (DFT04), 2004.
[VLP05] D.P. Vasudevan, P.K. Lala, and J.P. Parkerson. The construction of a fault tolerant re-
versible gate for quantum computation. In Proceedings of the 5th IEEE Conference on
Nanotechnology, pages 112115 vol. 1, July 2005.
[VMH03] G. F. Viamontes, I. L. Markov, and J. P. Hayes. Improving gate-level simulation of quantum
circuits. Quantum Information Processing, 2(5):347380, October 2003. preprint available
at quant-ph/0309060.
[VMH05a] G. F. Viamontes, I. L. Markov, and J. P. Hayes. Graph-based simulation of quantum
computation in the density matrix representation. Quantum Information & Computation,
5(2):113130, 2005. preprint available at quant-ph/0403114.
[VMH05b] G. F. Viamontes, I. L. Markov, and J. P. Hayes. Is quantum search practical? Comput-
ing in Science and Engineering, 7(4):2230, May/June 2005. preprint available at quant-
ph/0405001.
[VR05] A. De Vos and Y. Van Rentergem. Reversible computing: From mathematical group theory
to electronical circuit experiment. In Proceedings of the 2nd Conference on Computing
Frontiers, pages 3544, 2005. May 46, Ischia, Italy, ACM Press.
[VR07] A. De Vos and Y. Van Rentergem. Synthesis of reversible logic for nanoelectronic circuits.
International Journal of Circuit Theory and Applications, 35(3):325341, 2007. Published
online 17 April 2007 in Wiley InterScience ([Link]).
[VRK06] A. De Vos, Y. Van Rentergem, and K. De Keyser. The decomposition of an arbitrary
reversible logic circuit. Journal of Physics A: Mathematical and General, 39(18):50155035,
May 2006.
[WD09] Robert Wille and Rolf Drechsler. BDD-based synthesis of reversible logic for large functions.
In Proceedings of the 46th Annual Design Automation Conference, DAC 09, pages 270275,
New York, NY, USA, 2009. ACM.
[WD10] Robert Wille and Rolf Drechsler. BDD-based synthesis of reversible logic. International
Journal of Applied Metaheuristic Computing (IJAMC), 1(4):2541, 2010.
[WDOGO12] R. Wille, R. Drechsler, C. Osewold, and A. Garcia-Ortiz. Automatic design of low-power
encoders using reversible circuit synthesis. In Design, Automation Test in Europe Conference
Exhibition (DATE), 2012, pages 10361041, 2012.
[WG07] R. Wille and D. Groe. Fast exact Tooli network synthesis of reversible logic. In Intl Conf.
on CAD, pages 6064, 2007.
[WGF
+
11] Robert Wille, Daniel Groe, Stefan Frehse, Gerhard W. Dueck, and Rolf Drechsler. Debug-
ging reversible circuits. Integration, the VLSI Journal, 44(1):5161, 2011.
[WGMD09] R. Wille, D. Groe, D. M. Miller, and R. Drechsler. Equivalence checking of reversible
circuits. In Proceedings of the 39th International Symposium on Multiple-Valued Logic (IS-
MVL), pages 324330, 2009.
[WGT
+
08] R. Wille, D. Groe, L. Teuber, G. W. Dueck, and R. Drechsler. RevLib: An online resource
for reversible functions and reversible circuits. In International Symposium on Multiple
Valued Logic, pages 220225, 2008. RevLib is available at [Link]
22
[WKD11] R. Wille, O. Keszocze, and R. Drechsler. Determining the minimal number of lines for large
reversible circuits. In Design, Automation Test in Europe Conference Exhibition (DATE),
2011, pages 14, 2011.
[WSD10] R. Wille, M. Soeken, and R. Drechsler. Reducing the number of lines in reversible circuits.
In Proceedings of the Design Automation Conference (DAC), pages 647652, 2010. June
1318, Anaheim, California.
[WSPD12] R. Wille, M. Soeken, N. Przigoda, and R. Drechsler. Exact synthesis of tooli gate circuits
with negative control lines. In Proceedings of the 42nd IEEE International Symposium on
Multiple-Valued Logic (ISMVL), pages 6974, 2012.
[YR96] Y. Ye and K. Roy. Energy recovery circuits using reversible and partially reversible logic.
IEEE Trans. on Circuits and Systems, 43(9):769778, Sept. 1996.
[YSHP08] Guowu Yang, Xiaoyu Song, William N. N. Hung, and Marek A. Perkowski2. Bi-directional
synthesis of 4-bit reversible circuits. The Computer Journal, 51(2):207215, 2008.
[ZFT11] M. Zamani, N. Farazmand, and M.B. Tahoori. Fault masking and diagnosis in reversible
circuits. In Proceedings of the 16th IEEE European Test Symposium (ETS), pages 6974,
may 2011.
[ZM06] J. Zhong and J. C. Muzio. Analyzing fault models for reversible logic circuits. In IEEE
Congress on Evolutionary Computation (CEC), pages 24222427, 2006. Vancouver, BC.
[ZT11] M. Zamani and M.B. Tahoori. Online missing/repeated gate faults detection in reversible
circuits. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance
in VLSI and Nanotechnology Systems (DFT), pages 435442, oct. 2011.
23