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VHDL Code For Arithmetic and Logic Unit

The document describes VHDL code for an arithmetic and logic unit (ALU) that performs arithmetic and logic operations on 4-bit inputs a and b based on a 3-bit selection signal s. The ALU contains logic to perform operations like addition, subtraction, AND, OR, and NOT.

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3K views4 pages

VHDL Code For Arithmetic and Logic Unit

The document describes VHDL code for an arithmetic and logic unit (ALU) that performs arithmetic and logic operations on 4-bit inputs a and b based on a 3-bit selection signal s. The ALU contains logic to perform operations like addition, subtraction, AND, OR, and NOT.

Uploaded by

meaow88
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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VHDL CODE FOR ARITHMETIC AND LOGIC UNIT

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu is

Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);

s : in STD_LOGIC_VECTOR (2 downto 0);

y : out STD_LOGIC_VECTOR (3 downto 0));

end alu;

architecture Behavioral of alu is

signal arith,logic:std_logic_vector(3 downto 0);

begin

with s(1 downto 0) select

arith<= a when "00",

a+b when "01",

not b when "10",

a+1 when others;

with s(1 downto 0) select

logic<= not a when "00",

not b when "01",

a or b when "10",
a and b when others;

with s(2) select

y<= arith when '0',

logic when others;

end Behavioral;
(a)

(b)

FIG5.2 SCHEMATIC DIAGRAM FOR ARITHMETIC AND LOGIC UNIT


FIG5.3 WAVEFORM FOR ARITHMETIC AND LOGIC UNIT

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