Interfacing Devices
BY Prof. Y. P. Jadhav Physics Department Smt. CHM college, Ulhasnagar -
Tri-state Devices
Microcomputer contains
at least one microprocessor and large number of interfacing devices (Peripheral or I !s or hips"# These devices are connected to microprocessor through a bus oriented s$stem# The microprocessor can access (communicate %ith" onl$ one (I& or memor$" device at a time' hence all other devices (chips" must be disconnected# But all the devices cannot be disconnected %ithin ver$ short duration (1 (sec" ph$sicall$# )ence tri-state logic is used to disconnect un%anted chips or devices from the bus electricall$* but not ph$sicall$#
Tri-state logic devices Three states , logic 1* logic - and high impedance state (logic ."# It has third input line called /nable* enabled - device %or0s in its normal %a$# disabled - the logic device goes in to high impedance state-as if it is disconnected from the s$stem# Tri-state logic is used to ma0e devices compatible %ith bus oriented s$stem#
Input /nable /23
&utput
Input /nable / 2 3
&utput
Truth tables4
E I/P O/P 0 X Logic z 1 0 1 1 1 0
I/P X 0 1
O/P Logic z 1 0
1 0 0
Buffer
the logic device %hich amplifies the current or po%er# It has one input and one output line# non inverting or inverting output tri-state devices to facilitate their uses in bus oriented s$stem# 6se - primaril$ to increase the driving capabilit$ of a logic circuit (compared to logic gate" therefore also 0no%s as driver# T%o t$pes4
6nidirectional Bidirectional
Input /nable &utput
6nidirectional buffer4
=cc
++ 5 8 9 1< 5 11 11 17 1:
+<5 +Y5 +<1 1Y5 +Y1 1<1
13
1 1Y 1 19 18 15 1+ ; : 7 1
I :5?@ ++5 - an octal tri-state non inverting unidirectional buffer# also 0no%n as line driver or line receiver# used as a driver for the address bus , to improve driving capabilit$ of address lines# t%o groups of four buffers %ith tri-state output and controlled b$ t%o active lo% enable lines# /ach buffer is capable of sin0ing +5 m< and sourcing 17 m< of current# :5 ?@ +5- is another eAample of tri-state buffer %ith inverted output#
13>D
1;
+3
:5?@+55 is &ctal Buffer and ?ine Driver designed to be emplo$ed as memor$ address drivers* cloc0 drivers and bus-oriented transmitters2receivers %hich provide improved P board densit$# B )$steresis at Inputs - to Improve >oise Margins B 1-@tate &utputs - to drive Bus ?ines or Buffer Memor$ <ddress Cegisters B Input lamp Diodes - to limit )igh-@peed Termination /ffects
Bidirectional buffer4
Vcc A1 A2 A3 A4 A5 A6 A7 A8
+ 1 5 7 8 : 9 ; 1 +-
GND
119 1: 18 17 15 11 1+ 11 1;
The data bus of microprocessor is bidirectional therefore it reDuires a buffer that allo%s data to flo% in both directions#
B1 B2 B3 B4 B5 B6 B7 B8
bidirectional buffer :5?@ +57# also called octal bus transceiver# The direction of data flo% is controlled b$ the pin DIC#
Enable L L H
G
DIR L H X
Operation B data to A bus A data to B bus Isolation
Direction ontrol
DIR
G
/nable
<nother eAample - Intel 9+98 high capabilit$ than :5?@+57# These t%o buffers are not pin compatible#
Bidirectional buffer :5?@ +57
!N"#I$NA% DE&"RI'#I$N $ $"#A% B!& #RAN&"EIVER The @>752:5?@+57 is an &ctal Bus Transmitter2Ceceiver designed for 9line as$nchronous +-%a$ data communication bet%een data buses# Direction Input (DIC" controls transmission of Data from bus < to bus B or bus B to bus < depending upon its logic level# The /nable input Ecan be used to isolate the buses# )$steresis Inputs to Improve >oise Immunit$ +-Ea$ <s$nchronous Data Bus ommunication Input Diodes ?imit )igh-@peed Termination /ffects
< decoder is a circuit that changes a code into a set of signals# used to convert one form of binar$ code into another form# it is a multi-input multi-output combinational logic device# For a particular input combination onl$ one output line is activated# is a logic device that identifies each combination of the input signal and decodes it into a proper output line# decoder having n input lines %ill decode maAimum ( ) 2n lines t$pes - +-5* 1-9* 5-18* 5 -1- (B D" etc#
Decoder
uses: interfacing I/O peripherals and memory. built internal to a memory chip to identify individual memory register (location). as an 8-output demultiplexer.
:5?@119 and Intel 9+-7 are eAamples of 1-to-9 decoder %ith active lo% output lines#
18
9
<: <8 <7 9+-7 <5 or 61 <1 119 <+ <1 /+ / 1 <-
1 + 1
Y: Y8 Y7 Y5 B :5?@119 61 Y1 Y+ < Y1 3+< 3+B 31 Y-
3>D
: ; 111 1+ 11 15 17
= 1 + 1 <+ <1 </1 5
3>D
: ; 111 1+ 11 15 17
/nable
/nable
!N"#I$NA% DE&"RI'#I$N The :5?@119 is a high speed 1-of-9 Decoder2DemultipleAer fabricated %ith the lo% po%er @chott0$ barrier diode process#
Thest$les decoder accepts three binar$ %eighted inputs (<+* <1* c0 to edit Master teAt = 3>D <-" and provides eight mutuall$ eAclusive active ?&E
1
Y: Y8 Y7 Y5 B :5?@119 61 Y1 Y+ < Y1 3+< 3+B 31 Y-
econd level
+ hird level
Fourth 1 level Fifth level
5 7
: ; 111 1+ 11 15 17
&utputs (&-,&: or Y-,Y:"# The ?@119 features three /nable inputs* t%o active ?&E (/1* /+" and one active )I3) (/1"# <ll outputs %ill be )I3) unless 3+< and 3+B are ?&E and 31 is )I3)# The :5 ?@119 can be used as an 9-output demultipleAer b$ using one of the active ?&E /nable inputs as the data input and the other /nable inputs as strobes# The /nable inputs %hich are not used must be permanentl$ tied to their appropriate active )I3) or active ?&E state#
/nable
Multiple enable inputs also allo%s eas$ parallel eApansion of the decoder device to a 1-of-1+ (7 lines to 1+ lines" decoder %ith Gust four ?@119s and one inverter (as sho%n in figure"#
:5?@119 Function Table
Inputs Enable Select
G1 X L H H H H H H H H G2 H X L L L L L L L L C X X L L L L H H H H B X X L L H H L L H H A X X L H L H L H L H Y0 H H L H H H H H H H Y1 H H H L H H H H H H Y2 H H H H L H H H H H
Outputs
Y3 H H H H H L H H H H Y4 H H H H H H L H H H Y5 H H H H H H H L H H Y6 H H H H H H H H L H Y7 H H H H H H H H H L
/ncoder
<n encoder is a circuit that changes a set of signals into a code# The encoder is the logic circuit that provides the appropriate code as output for each input signal.
18 5 1 + 1 : 8 7
=
9
3>D
<+ <1 <61 :5?@159 3@
8 : ;
:5?@1594 an 9 , to , 1 *ri+rit, enc+-er# ascading circuitr$ (enable input /I and enable output /&" has been provided to allo% octal eApansion %ithout the need for eAternal circuitr$# data inputs and outputs are active at the lo% logic level# <ll inputs are buffered
5 11 1 1+ + 11 1 1-
/- 17 /1
7
/nable
15
.ncti+n #able +f 74%& 148
Inputs
E1
H L L L L L L L L L
Outputs
4
X H X X X L H H H H
0
X H X X X X X X X L
1
X H X X X X X X L H
2
X H X X X X X L H H
3
X H X X X X L H H H
5
X H X X L H H H H H
6
X H X L H H H H H H
7
X H L H H H H H H H
A 2
H H L L L L H H H H
A 1
H H L L H H L L H H
A 0
H H L H L H L H L H
G S
H H L L L L L L L L
E0
H L H H H H H H H H
Enc+-ers are c+((+nl, .se/ #+ interface in*.t -evices 0 in n/Bit Enc+-ing circ.its 0 in "+-e "+nverters an- Generat+rs
'ri+rit, enc+-er / in *ri+rit, interr.*ts in c+(*.ters an- (icr+*r+cess+rs1
?atch
In its simplest from* a latch is a data flip-flop
?atch
Input
?H
D I 61 :5:7 3 I
T1+
?H
t1 t+
T+1
t1
T15
t5 t7
Input ?atch &utput Data ?atch
Input
PC 61 :5:5 ?C
Data ?atch
(a" (b"
?H
Positive /dge Triggered
Trigger
Trigger
&utput Eaveforms of ?atch (a" and Positive /dge T riggered Flip-Flop (b"
< latch is commonl$ used to interface output devices# /Aample4 :5?@1:1 - a transparent latch
+=cc 1 5 13>D
1D
D
?H
1I + +I 1I 8
7
It includes eight D latches %ith tri-state buffers t%o input signals* /nable (3" and &utput ontrol ( OC "
The Enable is the active high input connected to clock input of the flip-flops. The Output Control is active low, and it enables the tri-state buffers to output data
+D : 1D 9 5D
11
5I ;
:5?@1:1 61
7D 15 8D
1:
7I 17 8I
1+
:D 19 9D
3
11 /nable
&
:I 18 9I 1;
1 &utput ontrol
This latch can be vie%ed as register in a memor$ chip#
.ncti+n table +f 74%&373
+=cc 1 5 13>D
1D
D
?H
1I + +I 1I 8
7
+D : 1D
9
Output Control
Enable G
Data D
Output Q
5D
:5?@1:1 61
5I ; 7I 17 8I :I 18 9I 1;
1 &utput ontrol 1+
11
7D 15 8D
1:
L L L H
H H L X
H L X X
H L 0 Logic !
:D 19 9D
3
11 /nable
&
Ehat is a MultipleAer (M6J"K
< M6J is a digital s%itch that has multiple inputs (sources" and a single output (destination"# The select lines determine %hich input is connected to the output# M6J T$pes
+-to-1 (1 select line" 5-to-1 (+ select lines" 9-to-1 (1 select lines" 18-to-1 (5 select lines"
Inputs
(sources)
MultipleAer
Bloc0 Diagram
M6J
2N
&utput
(destination)
N @elect ?ines
T$pical <pplication of a M6J
Multiple @ources
MP1 Pla$er Doc0ing @tation
@elector
@ingle Destination
D2
M6J
?aptop @ound ard
D1 D2 D3
@urround @ound @$stem Digital @atellite B 1 Digital able T= 1 < 1 1 @elected @ource MP1 ?aptop @atellite able T=
+5
M6?TIP?/J/C (D<T< @/?/ T&C"
< multipleAer is a logic circuit that accepts inputs from several different channels and feeds all of them into a single output channel in a seDuential order It is a circuit that gates one of several inputs to a single output# It is multi-input single output combinational logic circuit# The input selected is controlled b$ a set of select (control" lines# M6J has n input lines and one output line# For selecting one input out of n inputs* a set of m select lines are reDuired* %here+ m L n# >ormall$* a active lo% strobe (enable" input (3" is incorporated#
Bloc0 Diagram4
II1 I+ I1 In-1
n41 M6J
@trob 2 /nable
@m-1 @+ @1 @-
5-to-1 MultipleAer (M6J"
DD1 D+ D1
M6J
<
B 1 1
< 1 1
Y DD1 D+ D1
541 MultipleAer4
?ogic eDuation 4 Y = # S1 S 0 I 0 + S1S 0 I1 + S1 S 0 I 2 + S1S 0 I 3 " G Truth table4
Enable input G 0 0 0 0 1 Select inputs S1 S0 0 0 1 1 " 0 1 0 1 " output ! I0 I1 I2 I3 0
I1
@elect lines
@1
@-
@trobe or /nable 3
I-
I+
I1
< 541 MultipleAer using ><>D 3ates
@tandard I s are available for +41* 541* 941 and 1841 multipleAers#
I# $o%
74157 7415$ 74153 74352 74151A 74152 74150
Description
uad 2%1 &ulti'l()(*+ uad 2%1 &ulti'l()(*+ ,ual 4%1 &ulti'l()(*+ ,ual 4%1 &ulti'l()(*+ $%1 &ulti'l()(*+ $%1 &ulti'l()(*+ 16%1 &ulti'l()(*+
Output
-a.( as in'ut In/(*t(d in'ut+ -a.( as in'ut In/(*t(d in'ut+ In/(*t(d in'ut+ In/(*t(d in'ut+ In/(*t(d in'ut+
A**licati+n +f 4!56 1# @eDuence generator# +# Parallel to serial data converter 1# ombinational logic device# 5# <s a MultipleAer #
8/t+/1 4!5
Medium @cale Integration M6J
5-to-1 M6J
Inputs @elect /nable &utput (Y"
(and inverted output"
9-to-1 M6J
18-to-1 M6J
MultipleAer Tree4
941 M6J using t%o 5 41 M6J Inputs
1 541 + YM6J 1 3 @1 @-
Output A 0 1 0 1 0 1 0 1 ! ,0 ,1 ,2 ,3 ,4 ,5 ,6 ,7
# 0 0
Y
& 0 0 1 1 0 0 1 1
< B
@1 @5 7 541 8 Y1 M6J : 3
0 0 1 1 1 1
<lternative method4
lic0 to edit Master teAt st$les @econd - level 1 Third level 541 + Y Fourth level M6J 1 Fifth level
?ogic 3 @1 @1 @1 @?ogic 3 @Y
< B
5 7 541 8 Y1 M6J : 3
?ogic -
Full adder using multipleAer4
Implementation table for sum
Truth table4
Inputs A 0 0 0 0 1 1 1 1 & 0 0 1 1 0 0 1 1 #in 0 1 0 1 0 1 0 1 Outputs #arr' 0 0 0 1 0 1 1 1 Su( 0 1 1 0 1 0 0 1
D0
D1
D2
D3
A 0 1 1 0 A 1 0 0 1 A A A A
A
Implementation table for arr$
D0
D1
D2
D3
0 0 0
0 1
0 1
1 1 1
A A
Implementation of full adder using 541 M6J4
< B
in
1 + 541 Y 1 M6 J 3 ?ogic - @1 @-
@6M
?ogic -
?ogic 1 ?ogic -
@1 @1 541 + Y M6 J 1 3
<CCY
Implementation of 5-variable logic eDuation using 941 M6J#
f # A0 B0 C 0 D" = m( 204060701010011012015)
@olution4
1#Erite the truth table for the logic eDuation +# onnect inputs <* B and to @+* @1* @- select inputs respectivel$# 1#&bserve the relation bet%een D and Y and prepared the reduction table# 5#Implement this truth table using 941 M6J#
Truth table
Inputs
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Output
# 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ! 0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 1
Truth table after reduction logic
Inputs Output
& 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0
Y 0 D
D
1 0 1 0 1 1 , 1
D
,
?ogic D
?ogic1
1 + 1 5 7 8 :
MuA
941 Y
&utput
?ogic -
< B
f # A0 B0 C 0 D" = m#104050701012013" AB" D
-
D
1
1
1
D 1
II1 I+ I1 I5 I7 I8 I: @+ @1 @-
7 1 8
:
1
;
D D 1
941 M6J
1-
1
11
1+
11
1
15
1
17
<
Ehat is a DemultipleAer (D/M6J"K
< D/M6J is a digital s%itch %ith a single input (source" and a multiple outputs (destinations"# The select lines determine %hich output the input is connected to# D/M6J T$pes
1-to-+ (1 select line" 1-to-5 (+ select lines" 1-to-9 (1 select lines" 1-to-18 (5 select lines"
Input
(source)
DemultipleAer
Bloc0 Diagram
D/M6J
2N
&utputs
(destinations)
N @elect ?ines
T$pical <pplication of a D/M6J
@ingle @ource @elector Multiple Destinations
B2E ?aser Printer FaA Machine
D/M6J
D2 D1 D2 D3
olor In0Get Printer
B 1 1
< 1 1
@elected Destination B2E ?aser Printer FaA Machine olor In0Get Printer Pen Plotter Pen Plotter
51
D/M6?TIP?/J/C@
DemultipleAer is a logic circuit %ith one input and man$ outputs# B$ appl$ing proper control signal* %e can steer (transfer" the input signal to one of the output lines# Fig sho%s bloc0 diagram of 14n D/M6J# Din D/M6J The circuit has one input line n output lines and m select (control" lines# Ehere @m -1 @+ @1 @nL+(
YY1 Y+ Y1 Yn-1
1-to-5 De-MultipleAer (D/M6J"
D/M6J
DD1 D+ D1 J
<
B 1 1
< 1 1
D- D1 D+ D1 J J J J
145 (+-line to 5-line" DemultipleAer4
?ogic diagram Bloc0 diagram
@1 @@trobe
Din
YDin Y-
Y1 145 D/M6J Y+ 3 @1 @Y1
Y1
Y+
Y1
I# $o% 7413) 222222222222222222222 74155 222222222222222222222 74156 222222222222222222222 7413* 222222222222222222222 74154 222222222222222222222 7415)
Description ,ual 1%4 ,(.ulti'l()(* #22lin( to 42lin( d(cod(*" 222222222222222222222222222222222 22do3 222222222222222222222222222222222 22do3 222222222222222222222222222222222 1% $ ,(.ulti'l()(* #32lin( to $2lin( d(cod(*" 222222222222222222222222222222222 1%16 ,(.ulti'l()(* #42lin( to 162lin( d(cod(*" 222222222222222222222222222222222 22do22
Output In/(*t(d in'ut+ 222222222222222222222222222222222 1Y 4 In/(*t(d in'ut+ 2Y 4 -a.( as in'ut 222222222222222222222222222222222 5'(n coll(cto*+ 1Y 4 In/(*t(d in'ut+ 2Y 4 -a.( as in'ut 222222222222222222222222222222222 In/(*t(d in'ut+ 222222222222222222222222222222222 -a.( as in'ut+ 2222222222222222222222222222222222 -a.( as in'ut+ 5'(n coll(cto*+
Medium @cale Integration D/M6J
1-to-5 D/M6J
@elect Input
(inverted"
1-to-9 D/M6J
18-to-1 M6J
&utputs
(inverted"
>ote 4 Most Medium @cale Integrated (M@I" D/M6Js * li0e the three sho%n* have outputs that are inverted# This is done because it reDuires fe% logic gates to implement D/M6Js %ith inverted outputs rather than no-inverted outputs#
<pplications of D/M6J4
Data Distributor. Decoder To i ple ent ulti-output co binational logic e!pression.
MultipleAer and DemultipleAer in combination are used in Data transmission s$stems#
DemultipleAer tree4
/nable
<1 B1 1 D1
< B
(M@B"
D / (?@B"
<+ B+ + D+
1 + 1 5 7 8 : 9 ; 111 1+ 11 15 17 18 1: 19 1; ++1 ++ +1 +5 +7 +8 +: +9 +; 111
/nable
Implementation of 149 D/M6J using t%o 1 4 5 D/M6J
Din
Din YY1 145 D/M6J Y+ 3 @1 @Y1
< B
@1 Din @Y5
Y7 145 D/M6J Y8 3 Y:
The multi-output combinational circuit using D/M6J and some additional logic gates
/Aample4 Implement the follo%ing multi-output combinational circuit using 5 ,to , 18 lines D/M6J# F1 L M m (-* 1* 7* 1-" F+ L M m (-* +* 5* 1-" F1 L M m (+* 5* 11* 17" standard @&P form
D in (To ?ogic 1"
Binar$ Inputs
/nable (To ?ogic -"
1 + 1 5 < (M@B"7 8 B : 9 ; D (?@B" 111 1+ 11 15 17
>1
F1
>+
F+
>1
F1
F1 L M m (-* 1* 7* 1-" F+ L M m (-* +* 5* 1-" F1 L M m (+* 5* 11* 17"
MuA 2 DemuA applications4 <ll these siA (muA* DemuA* encoder* decoder* serial to parallel and NN to serial convertors" devices are used in digital processing* telecommunications* instrumentation and computer architecture etc# <nd in a particular complete s$stem the$ appear in pairs* li0e compleA conGugates in maths# FreDuenc$ division* time division* %avelength division etc#
